diff --git a/.vs/D21_ADC_with_DMA/v14/.atsuo b/.vs/D21_ADC_with_DMA/v14/.atsuo
index 9d14bfa..4a8c8e9 100644
Binary files a/.vs/D21_ADC_with_DMA/v14/.atsuo and b/.vs/D21_ADC_with_DMA/v14/.atsuo differ
diff --git a/D21_ADC_with_DMA.atsln b/D21_ADC_with_DMA.atsln
index 55c28c5..52e8c4e 100644
--- a/D21_ADC_with_DMA.atsln
+++ b/D21_ADC_with_DMA.atsln
@@ -1,22 +1,22 @@
-
-Microsoft Visual Studio Solution File, Format Version 12.00
-# Atmel Studio Solution File, Format Version 11.00
-VisualStudioVersion = 14.0.23107.0
-MinimumVisualStudioVersion = 10.0.40219.1
-Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "D21_ADC_with_DMA", "D21_ADC_with_DMA\D21_ADC_with_DMA.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
-EndProject
-Global
-	GlobalSection(SolutionConfigurationPlatforms) = preSolution
-		Debug|ARM = Debug|ARM
-		Release|ARM = Release|ARM
-	EndGlobalSection
-	GlobalSection(ProjectConfigurationPlatforms) = postSolution
-		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
-		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
-		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
-		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
-	EndGlobalSection
-	GlobalSection(SolutionProperties) = preSolution
-		HideSolutionNode = FALSE
-	EndGlobalSection
-EndGlobal
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "D21_ADC_with_DMA", "D21_ADC_with_DMA\D21_ADC_with_DMA.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/D21_ADC_with_DMA/D21_ADC_with_DMA.componentinfo.xml b/D21_ADC_with_DMA/D21_ADC_with_DMA.componentinfo.xml
index e275755..52c412d 100644
--- a/D21_ADC_with_DMA/D21_ADC_with_DMA.componentinfo.xml
+++ b/D21_ADC_with_DMA/D21_ADC_with_DMA.componentinfo.xml
@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
-	<ProjectComponents />
+<?xml version="1.0" encoding="utf-8"?>
+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+	<ProjectComponents />
 </Store>
\ No newline at end of file
diff --git a/D21_ADC_with_DMA/D21_ADC_with_DMA.cproj b/D21_ADC_with_DMA/D21_ADC_with_DMA.cproj
index 8d3986b..c8e0e97 100644
--- a/D21_ADC_with_DMA/D21_ADC_with_DMA.cproj
+++ b/D21_ADC_with_DMA/D21_ADC_with_DMA.cproj
@@ -1,1337 +1,1337 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
-  <PropertyGroup>
-    <SchemaVersion>2.0</SchemaVersion>
-    <ProjectVersion>7.0</ProjectVersion>
-    <ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
-    <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid>
-    <avrdevice>ATSAMD21J18A</avrdevice>
-    <avrdeviceseries>samd21</avrdeviceseries>
-    <OutputType>Executable</OutputType>
-    <Language>C</Language>
-    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
-    <OutputFileExtension>.elf</OutputFileExtension>
-    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
-    <AssemblyName>D21_ADC_with_DMA</AssemblyName>
-    <Name>D21_ADC_with_DMA</Name>
-    <RootNamespace>D21_ADC_with_DMA</RootNamespace>
-    <ToolchainFlavour>Native</ToolchainFlavour>
-    <KeepTimersRunning>true</KeepTimersRunning>
-    <OverrideVtor>false</OverrideVtor>
-    <CacheFlash>true</CacheFlash>
-    <ProgFlashFromRam>true</ProgFlashFromRam>
-    <RamSnippetAddress>0x20000000</RamSnippetAddress>
-    <UncachedRange />
-    <preserveEEPROM>true</preserveEEPROM>
-    <OverrideVtorValue>exception_table</OverrideVtorValue>
-    <BootSegment>2</BootSegment>
-    <ResetRule>0</ResetRule>
-    <eraseonlaunchrule>0</eraseonlaunchrule>
-    <EraseKey />
-    <AsfFrameworkConfig>
-      <framework-data>
-  <options>
-    <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="sam0.drivers.port" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="sam0.drivers.system" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="sam0.utils.stdio.stdio_serial" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="sam0.drivers.adc" value="Add" config="polled" content-id="Atmel.ASF" />
-    <option id="sam0.drivers.dma" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="common2.services.delay" value="Add" config="systick" content-id="Atmel.ASF" />
-    <option id="common.applications.user_application.xplained_pro2" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="common.utils" value="Add" config="" content-id="Atmel.ASF" />
-    <option id="sam0.utils.cmsis.samd21.source.template" value="Add" config="" content-id="Atmel.ASF" />
-  </options>
-  <configurations>
-    <configuration key="config.sam0.drivers.sercom.usart" value="callback" default="callback" content-id="Atmel.ASF" />
-  </configurations>
-  <files>
-    <file path="src/main.c" framework="" version="" source="common2/applications/xplained_pro_user_application/main.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/config/conf_board.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config/conf_board.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/config/conf_clocks.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config/conf_clocks.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/common/boards/board.h" framework="" version="" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/common/utils/interrupt.h" framework="" version="" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/common/utils/parts.h" framework="" version="" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/boards/samd21_xplained_pro/board_init.c" framework="" version="" source="sam0/boards/samd21_xplained_pro/board_init.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h" framework="" version="" source="sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/port/port.c" framework="" version="" source="sam0/drivers/port/port.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/port/port.h" framework="" version="" source="sam0/drivers/port/port.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h" framework="" version="" source="sam0/drivers/port/quick_start/qs_port_basic.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/clock/clock.h" framework="" version="" source="sam0/drivers/system/clock/clock.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/clock/gclk.h" framework="" version="" source="sam0/drivers/system/clock/gclk.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.c" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.c" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.h" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" framework="" version="" source="sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h" framework="" version="" source="sam0/drivers/system/power/power_sam_d_r_h/power.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h" framework="" version="" source="sam0/drivers/system/reset/reset_sam_d_r_h/reset.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/system.c" framework="" version="" source="sam0/drivers/system/system.c" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/drivers/system/system.h" framework="" version="" source="sam0/drivers/system/system.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/ac.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/adc.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dac.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dsu.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/eic.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/evsys.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/gclk.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/hmatrixb.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/i2s.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/mtb.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/nvmctrl.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pac.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pm.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pm_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pm_variant_d.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/rtc.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/sercom.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/sysctrl.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc_lighting.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/wdt.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/ac1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/ac1.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dac.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dsu.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/i2s.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/mtb.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/nvmctrl.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h" changed="False" content-id="Atmel.ASF" />
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-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac1.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac2.h" changed="False" content-id="Atmel.ASF" />
-    <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pm.h" changed="False" content-id="Atmel.ASF" />
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-    <None Include="src\ASF\thirdparty\CMSIS\Lib\license.txt">
-      <SubType>compile</SubType>
-    </None>
-    <None Include="src\ASF\thirdparty\CMSIS\README.txt">
-      <SubType>compile</SubType>
-    </None>
-  </ItemGroup>
-  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
+    <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid>
+    <avrdevice>ATSAMD21J18A</avrdevice>
+    <avrdeviceseries>samd21</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>C</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>D21_ADC_with_DMA</AssemblyName>
+    <Name>D21_ADC_with_DMA</Name>
+    <RootNamespace>D21_ADC_with_DMA</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>0</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options>
+          <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam0.drivers.port" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam0.drivers.system" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam0.utils.stdio.stdio_serial" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam0.drivers.adc" value="Add" config="polled" content-id="Atmel.ASF" />
+          <option id="sam0.drivers.dma" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="common2.services.delay" value="Add" config="systick" content-id="Atmel.ASF" />
+          <option id="common.applications.user_application.xplained_pro2" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="common.utils" value="Add" config="" content-id="Atmel.ASF" />
+          <option id="sam0.utils.cmsis.samd21.source.template" value="Add" config="" content-id="Atmel.ASF" />
+        </options>
+        <configurations>
+          <configuration key="config.sam0.drivers.sercom.usart" value="callback" default="callback" content-id="Atmel.ASF" />
+        </configurations>
+        <files>
+          <file path="src/main.c" framework="" version="" source="common2/applications/xplained_pro_user_application/main.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/config/conf_board.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config/conf_board.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/config/conf_clocks.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config/conf_clocks.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/common/boards/board.h" framework="" version="" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/common/utils/interrupt.h" framework="" version="" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/common/utils/parts.h" framework="" version="" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/boards/samd21_xplained_pro/board_init.c" framework="" version="" source="sam0/boards/samd21_xplained_pro/board_init.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h" framework="" version="" source="sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/port/port.c" framework="" version="" source="sam0/drivers/port/port.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/port/port.h" framework="" version="" source="sam0/drivers/port/port.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h" framework="" version="" source="sam0/drivers/port/quick_start/qs_port_basic.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/clock/clock.h" framework="" version="" source="sam0/drivers/system/clock/clock.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/clock/gclk.h" framework="" version="" source="sam0/drivers/system/clock/gclk.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.c" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.c" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.h" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" framework="" version="" source="sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h" framework="" version="" source="sam0/drivers/system/power/power_sam_d_r_h/power.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h" framework="" version="" source="sam0/drivers/system/reset/reset_sam_d_r_h/reset.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/system.c" framework="" version="" source="sam0/drivers/system/system.c" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/drivers/system/system.h" framework="" version="" source="sam0/drivers/system/system.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/ac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/adc.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dmac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dsu.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/eic.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/evsys.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/gclk.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/hmatrixb.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/i2s.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/mtb.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/nvmctrl.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pm.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pm_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pm_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/port.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/port.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/rtc.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/sercom.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/sysctrl.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tc.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc_lighting.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/usb.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/wdt.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/ac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/ac1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/ac1.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/adc.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dmac.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dsu.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/eic.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/evsys.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/gclk.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/i2s.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/mtb.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/nvmctrl.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac0.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac1.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac2.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pm.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/port.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/port_variant_d.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/port_variant_d.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/rtc.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sbmatrix.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom0.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom1.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom2.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom3.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom4.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom5.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sysctrl.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc3.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc4.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc5.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc6.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc7.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tcc0.h" changed="False" content-id="Atmel.ASF" />
+          <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tcc1.h" changed="False" content-id="Atmel.ASF" />
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
+    </Compile>
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+      <SubType>compile</SubType>
+    </Compile>
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+    <Compile Include="src\ASF\sam0\drivers\system\system.c">
+      <SubType>compile</SubType>
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+    </Compile>
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+    </Compile>
+    <Compile Include="src\ASF\sam0\utils\syscalls\gcc\syscalls.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\main.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="src\ASF\thirdparty\CMSIS\Lib\GCC\libarm_cortexM0l_math.a">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="src\ASF\thirdparty\CMSIS\Lib\license.txt">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="src\ASF\thirdparty\CMSIS\README.txt">
+      <SubType>compile</SubType>
+    </None>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
 </Project>
\ No newline at end of file
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diff --git a/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.lss b/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.lss
index 8f4674e..028939f 100644
--- a/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.lss
+++ b/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.lss
@@ -1,9180 +1,9180 @@
-
-D21_ADC_with_DMA.elf:     file format elf32-littlearm
-
-Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         00003960  00000000  00000000  00010000  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, CODE
-  1 .relocate     0000007c  20000000  00003960  00020000  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  2 .bss          00000220  20000080  000039e0  0002007c  2**4
-                  ALLOC
-  3 .stack        00002000  200002a0  00003c00  0002007c  2**0
-                  ALLOC
-  4 .ARM.attributes 00000028  00000000  00000000  0002007c  2**0
-                  CONTENTS, READONLY
-  5 .comment      00000059  00000000  00000000  000200a4  2**0
-                  CONTENTS, READONLY
-  6 .debug_info   0002e296  00000000  00000000  000200fd  2**0
-                  CONTENTS, READONLY, DEBUGGING
-  7 .debug_abbrev 00004281  00000000  00000000  0004e393  2**0
-                  CONTENTS, READONLY, DEBUGGING
-  8 .debug_loc    00004e91  00000000  00000000  00052614  2**0
-                  CONTENTS, READONLY, DEBUGGING
-  9 .debug_aranges 00000548  00000000  00000000  000574a5  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 10 .debug_ranges 00000610  00000000  00000000  000579ed  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 11 .debug_macro  0001ca44  00000000  00000000  00057ffd  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 12 .debug_line   0000e317  00000000  00000000  00074a41  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 13 .debug_str    00090169  00000000  00000000  00082d58  2**0
-                  CONTENTS, READONLY, DEBUGGING
- 14 .debug_frame  000014c8  00000000  00000000  00112ec4  2**2
-                  CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-00000000 <exception_table>:
-       0:	a0 22 00 20 51 1c 00 00 4d 1c 00 00 4d 1c 00 00     .". Q...M...M...
-	...
-      2c:	4d 1c 00 00 00 00 00 00 00 00 00 00 4d 1c 00 00     M...........M...
-      3c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
-      4c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 05 00 00     M...M...M...M...
-      5c:	4d 1c 00 00 4d 1c 00 00 15 15 00 00 25 15 00 00     M...M.......%...
-      6c:	35 15 00 00 45 15 00 00 55 15 00 00 65 15 00 00     5...E...U...e...
-      7c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
-      8c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
-      9c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
-      ac:	4d 1c 00 00 00 00 00 00                             M.......
-
-000000b4 <__do_global_dtors_aux>:
-      b4:	b510      	push	{r4, lr}
-      b6:	4c06      	ldr	r4, [pc, #24]	; (d0 <__do_global_dtors_aux+0x1c>)
-      b8:	7823      	ldrb	r3, [r4, #0]
-      ba:	2b00      	cmp	r3, #0
-      bc:	d107      	bne.n	ce <__do_global_dtors_aux+0x1a>
-      be:	4b05      	ldr	r3, [pc, #20]	; (d4 <__do_global_dtors_aux+0x20>)
-      c0:	2b00      	cmp	r3, #0
-      c2:	d002      	beq.n	ca <__do_global_dtors_aux+0x16>
-      c4:	4804      	ldr	r0, [pc, #16]	; (d8 <__do_global_dtors_aux+0x24>)
-      c6:	e000      	b.n	ca <__do_global_dtors_aux+0x16>
-      c8:	bf00      	nop
-      ca:	2301      	movs	r3, #1
-      cc:	7023      	strb	r3, [r4, #0]
-      ce:	bd10      	pop	{r4, pc}
-      d0:	20000080 	.word	0x20000080
-      d4:	00000000 	.word	0x00000000
-      d8:	00003960 	.word	0x00003960
-
-000000dc <frame_dummy>:
-      dc:	4b08      	ldr	r3, [pc, #32]	; (100 <frame_dummy+0x24>)
-      de:	b510      	push	{r4, lr}
-      e0:	2b00      	cmp	r3, #0
-      e2:	d003      	beq.n	ec <frame_dummy+0x10>
-      e4:	4907      	ldr	r1, [pc, #28]	; (104 <frame_dummy+0x28>)
-      e6:	4808      	ldr	r0, [pc, #32]	; (108 <frame_dummy+0x2c>)
-      e8:	e000      	b.n	ec <frame_dummy+0x10>
-      ea:	bf00      	nop
-      ec:	4807      	ldr	r0, [pc, #28]	; (10c <frame_dummy+0x30>)
-      ee:	6803      	ldr	r3, [r0, #0]
-      f0:	2b00      	cmp	r3, #0
-      f2:	d100      	bne.n	f6 <frame_dummy+0x1a>
-      f4:	bd10      	pop	{r4, pc}
-      f6:	4b06      	ldr	r3, [pc, #24]	; (110 <frame_dummy+0x34>)
-      f8:	2b00      	cmp	r3, #0
-      fa:	d0fb      	beq.n	f4 <frame_dummy+0x18>
-      fc:	4798      	blx	r3
-      fe:	e7f9      	b.n	f4 <frame_dummy+0x18>
-     100:	00000000 	.word	0x00000000
-     104:	20000084 	.word	0x20000084
-     108:	00003960 	.word	0x00003960
-     10c:	00003960 	.word	0x00003960
-     110:	00000000 	.word	0x00000000
-
-00000114 <adc_get_config_defaults>:
- *
- * \param[out] config  Pointer to configuration struct to initialize to
- *                     default values
- */
-void adc_get_config_defaults(struct adc_config *const config)
-{
-     114:	b510      	push	{r4, lr}
-	Assert(config);
-	config->clock_source                  = GCLK_GENERATOR_0;
-     116:	2200      	movs	r2, #0
-     118:	2300      	movs	r3, #0
-     11a:	7002      	strb	r2, [r0, #0]
-	config->reference                     = ADC_REFERENCE_INT1V;
-     11c:	7042      	strb	r2, [r0, #1]
-	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
-     11e:	2100      	movs	r1, #0
-     120:	8042      	strh	r2, [r0, #2]
-	config->resolution                    = ADC_RESOLUTION_12BIT;
-     122:	7101      	strb	r1, [r0, #4]
-	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
-     124:	7603      	strb	r3, [r0, #24]
-	config->window.window_upper_value     = 0;
-     126:	6202      	str	r2, [r0, #32]
-	config->window.window_lower_value     = 0;
-     128:	61c2      	str	r2, [r0, #28]
-	config->gain_factor                   = ADC_GAIN_FACTOR_1X;
-     12a:	6082      	str	r2, [r0, #8]
-#if SAMR21
-	config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
-#else
- 	config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
-     12c:	7303      	strb	r3, [r0, #12]
-#endif
-	config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
-     12e:	24c0      	movs	r4, #192	; 0xc0
-     130:	0164      	lsls	r4, r4, #5
-     132:	81c4      	strh	r4, [r0, #14]
-	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
-     134:	7403      	strb	r3, [r0, #16]
-	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
-     136:	7443      	strb	r3, [r0, #17]
-	config->left_adjust                   = false;
-     138:	7483      	strb	r3, [r0, #18]
-	config->differential_mode             = false;
-     13a:	74c3      	strb	r3, [r0, #19]
-	config->freerunning                   = false;
-     13c:	7503      	strb	r3, [r0, #20]
-	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
-     13e:	242a      	movs	r4, #42	; 0x2a
-     140:	5503      	strb	r3, [r0, r4]
-	config->run_in_standby                = false;
-     142:	7543      	strb	r3, [r0, #21]
-	config->reference_compensation_enable = false;
-     144:	7583      	strb	r3, [r0, #22]
-	config->correction.correction_enable  = false;
-     146:	3c06      	subs	r4, #6
-     148:	5503      	strb	r3, [r0, r4]
-	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
-     14a:	84c2      	strh	r2, [r0, #38]	; 0x26
-	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
-     14c:	8502      	strh	r2, [r0, #40]	; 0x28
-	config->sample_length                 = 0;
-     14e:	75c1      	strb	r1, [r0, #23]
-	config->pin_scan.offset_start_scan    = 0;
-     150:	232b      	movs	r3, #43	; 0x2b
-     152:	54c1      	strb	r1, [r0, r3]
-	config->pin_scan.inputs_to_scan       = 0;
-     154:	3301      	adds	r3, #1
-     156:	54c1      	strb	r1, [r0, r3]
-}
-     158:	bd10      	pop	{r4, pc}
-	...
-
-0000015c <adc_init>:
- */
-enum status_code adc_init(
-		struct adc_module *const module_inst,
-		Adc *hw,
-		struct adc_config *config)
-{
-     15c:	b5f0      	push	{r4, r5, r6, r7, lr}
-     15e:	46d6      	mov	lr, sl
-     160:	464f      	mov	r7, r9
-     162:	4646      	mov	r6, r8
-     164:	b5c0      	push	{r6, r7, lr}
-     166:	b096      	sub	sp, #88	; 0x58
-     168:	0007      	movs	r7, r0
-     16a:	0016      	movs	r6, r2
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
-
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
-     16c:	6001      	str	r1, [r0, #0]
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg |= mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg |= mask;
-     16e:	4acb      	ldr	r2, [pc, #812]	; (49c <adc_init+0x340>)
-     170:	6a10      	ldr	r0, [r2, #32]
-     172:	2380      	movs	r3, #128	; 0x80
-     174:	025b      	lsls	r3, r3, #9
-     176:	4303      	orrs	r3, r0
-     178:	6213      	str	r3, [r2, #32]
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
-
-	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
-     17a:	780b      	ldrb	r3, [r1, #0]
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-     17c:	2005      	movs	r0, #5
-	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
-     17e:	07db      	lsls	r3, r3, #31
-     180:	d505      	bpl.n	18e <adc_init+0x32>
-	}
-#endif
-
-	/* Write configuration to module */
-	return _adc_set_config(module_inst, config);
-}
-     182:	b016      	add	sp, #88	; 0x58
-     184:	bc1c      	pop	{r2, r3, r4}
-     186:	4690      	mov	r8, r2
-     188:	4699      	mov	r9, r3
-     18a:	46a2      	mov	sl, r4
-     18c:	bdf0      	pop	{r4, r5, r6, r7, pc}
-	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
-     18e:	780b      	ldrb	r3, [r1, #0]
-		return STATUS_ERR_DENIED;
-     190:	3017      	adds	r0, #23
-	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
-     192:	079b      	lsls	r3, r3, #30
-     194:	d4f5      	bmi.n	182 <adc_init+0x26>
-	module_inst->reference = config->reference;
-     196:	7873      	ldrb	r3, [r6, #1]
-     198:	713b      	strb	r3, [r7, #4]
-	if (module_inst->reference == ADC_REFERENCE_INT1V) {
-     19a:	2b00      	cmp	r3, #0
-     19c:	d104      	bne.n	1a8 <adc_init+0x4c>
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
-			break;
-
-		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
-			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
-     19e:	4ac0      	ldr	r2, [pc, #768]	; (4a0 <adc_init+0x344>)
-     1a0:	6c13      	ldr	r3, [r2, #64]	; 0x40
-     1a2:	2104      	movs	r1, #4
-     1a4:	430b      	orrs	r3, r1
-     1a6:	6413      	str	r3, [r2, #64]	; 0x40
-	Adc *const adc_module = module_inst->hw;
-     1a8:	683b      	ldr	r3, [r7, #0]
-     1aa:	4698      	mov	r8, r3
-	gclk_chan_conf.source_generator = config->clock_source;
-     1ac:	7833      	ldrb	r3, [r6, #0]
-     1ae:	466a      	mov	r2, sp
-     1b0:	7013      	strb	r3, [r2, #0]
-	system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
-     1b2:	4669      	mov	r1, sp
-     1b4:	201e      	movs	r0, #30
-     1b6:	4bbb      	ldr	r3, [pc, #748]	; (4a4 <adc_init+0x348>)
-     1b8:	4798      	blx	r3
-	system_gclk_chan_enable(ADC_GCLK_ID);
-     1ba:	201e      	movs	r0, #30
-     1bc:	4bba      	ldr	r3, [pc, #744]	; (4a8 <adc_init+0x34c>)
-     1be:	4798      	blx	r3
-	if (config->pin_scan.inputs_to_scan != 0) {
-     1c0:	232c      	movs	r3, #44	; 0x2c
-     1c2:	5cf2      	ldrb	r2, [r6, r3]
-     1c4:	2a00      	cmp	r2, #0
-     1c6:	d054      	beq.n	272 <adc_init+0x116>
-		uint8_t offset = config->pin_scan.offset_start_scan;
-     1c8:	3b01      	subs	r3, #1
-     1ca:	5cf5      	ldrb	r5, [r6, r3]
-		uint8_t start_pin =
-     1cc:	7b33      	ldrb	r3, [r6, #12]
-     1ce:	18eb      	adds	r3, r5, r3
-     1d0:	b2db      	uxtb	r3, r3
-		uint8_t end_pin =
-     1d2:	18d1      	adds	r1, r2, r3
-		while (start_pin < end_pin) {
-     1d4:	b2c9      	uxtb	r1, r1
-     1d6:	428b      	cmp	r3, r1
-     1d8:	d221      	bcs.n	21e <adc_init+0xc2>
-     1da:	1952      	adds	r2, r2, r5
-     1dc:	b2d3      	uxtb	r3, r2
-     1de:	4699      	mov	r9, r3
-	const uint32_t pinmapping[] = {
-     1e0:	4bb2      	ldr	r3, [pc, #712]	; (4ac <adc_init+0x350>)
-     1e2:	469a      	mov	sl, r3
-     1e4:	e003      	b.n	1ee <adc_init+0x92>
-			offset++;
-     1e6:	3501      	adds	r5, #1
-     1e8:	b2ed      	uxtb	r5, r5
-		while (start_pin < end_pin) {
-     1ea:	45a9      	cmp	r9, r5
-     1ec:	d017      	beq.n	21e <adc_init+0xc2>
-			_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
-     1ee:	240f      	movs	r4, #15
-     1f0:	402c      	ands	r4, r5
-     1f2:	7b33      	ldrb	r3, [r6, #12]
-     1f4:	18e4      	adds	r4, r4, r3
-	const uint32_t pinmapping[] = {
-     1f6:	2250      	movs	r2, #80	; 0x50
-     1f8:	49ad      	ldr	r1, [pc, #692]	; (4b0 <adc_init+0x354>)
-     1fa:	a802      	add	r0, sp, #8
-     1fc:	47d0      	blx	sl
-	if (pin <= ADC_EXTCHANNEL_MSB) {
-     1fe:	2c13      	cmp	r4, #19
-     200:	d8f1      	bhi.n	1e6 <adc_init+0x8a>
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
-     202:	00a4      	lsls	r4, r4, #2
-     204:	ab02      	add	r3, sp, #8
-     206:	58e0      	ldr	r0, [r4, r3]
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->mux_position = SYSTEM_PINMUX_GPIO;
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-     208:	a901      	add	r1, sp, #4
-     20a:	2300      	movs	r3, #0
-     20c:	704b      	strb	r3, [r1, #1]
-	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
-	config->powersave    = false;
-     20e:	70cb      	strb	r3, [r1, #3]
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-     210:	708b      	strb	r3, [r1, #2]
-		config.mux_position = 1;
-     212:	3301      	adds	r3, #1
-     214:	700b      	strb	r3, [r1, #0]
-		system_pinmux_pin_set_config(pin_map_result, &config);
-     216:	b2c0      	uxtb	r0, r0
-     218:	4ba6      	ldr	r3, [pc, #664]	; (4b4 <adc_init+0x358>)
-     21a:	4798      	blx	r3
-     21c:	e7e3      	b.n	1e6 <adc_init+0x8a>
-		_adc_configure_ain_pin(config->negative_input);
-     21e:	89f4      	ldrh	r4, [r6, #14]
-	const uint32_t pinmapping[] = {
-     220:	2250      	movs	r2, #80	; 0x50
-     222:	49a3      	ldr	r1, [pc, #652]	; (4b0 <adc_init+0x354>)
-     224:	a802      	add	r0, sp, #8
-     226:	4ba1      	ldr	r3, [pc, #644]	; (4ac <adc_init+0x350>)
-     228:	4798      	blx	r3
-	if (pin <= ADC_EXTCHANNEL_MSB) {
-     22a:	2c13      	cmp	r4, #19
-     22c:	d913      	bls.n	256 <adc_init+0xfa>
-	adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
-     22e:	7d73      	ldrb	r3, [r6, #21]
-     230:	009b      	lsls	r3, r3, #2
-     232:	b2db      	uxtb	r3, r3
-     234:	4642      	mov	r2, r8
-     236:	7013      	strb	r3, [r2, #0]
-			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
-     238:	7db3      	ldrb	r3, [r6, #22]
-     23a:	01db      	lsls	r3, r3, #7
-     23c:	7872      	ldrb	r2, [r6, #1]
-     23e:	4313      	orrs	r3, r2
-     240:	b2db      	uxtb	r3, r3
-	adc_module->REFCTRL.reg =
-     242:	4642      	mov	r2, r8
-     244:	7053      	strb	r3, [r2, #1]
-	switch (config->resolution) {
-     246:	7933      	ldrb	r3, [r6, #4]
-     248:	2b34      	cmp	r3, #52	; 0x34
-     24a:	d900      	bls.n	24e <adc_init+0xf2>
-     24c:	e178      	b.n	540 <adc_init+0x3e4>
-     24e:	009b      	lsls	r3, r3, #2
-     250:	4a99      	ldr	r2, [pc, #612]	; (4b8 <adc_init+0x35c>)
-     252:	58d3      	ldr	r3, [r2, r3]
-     254:	469f      	mov	pc, r3
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
-     256:	00a4      	lsls	r4, r4, #2
-     258:	ab02      	add	r3, sp, #8
-     25a:	58e0      	ldr	r0, [r4, r3]
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-     25c:	a901      	add	r1, sp, #4
-     25e:	2300      	movs	r3, #0
-     260:	704b      	strb	r3, [r1, #1]
-	config->powersave    = false;
-     262:	70cb      	strb	r3, [r1, #3]
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-     264:	708b      	strb	r3, [r1, #2]
-		config.mux_position = 1;
-     266:	3301      	adds	r3, #1
-     268:	700b      	strb	r3, [r1, #0]
-		system_pinmux_pin_set_config(pin_map_result, &config);
-     26a:	b2c0      	uxtb	r0, r0
-     26c:	4b91      	ldr	r3, [pc, #580]	; (4b4 <adc_init+0x358>)
-     26e:	4798      	blx	r3
-     270:	e7dd      	b.n	22e <adc_init+0xd2>
-		_adc_configure_ain_pin(config->positive_input);
-     272:	7b34      	ldrb	r4, [r6, #12]
-	const uint32_t pinmapping[] = {
-     274:	2250      	movs	r2, #80	; 0x50
-     276:	498e      	ldr	r1, [pc, #568]	; (4b0 <adc_init+0x354>)
-     278:	a802      	add	r0, sp, #8
-     27a:	4b8c      	ldr	r3, [pc, #560]	; (4ac <adc_init+0x350>)
-     27c:	4798      	blx	r3
-	if (pin <= ADC_EXTCHANNEL_MSB) {
-     27e:	2c13      	cmp	r4, #19
-     280:	d915      	bls.n	2ae <adc_init+0x152>
-		_adc_configure_ain_pin(config->negative_input);
-     282:	89f4      	ldrh	r4, [r6, #14]
-	const uint32_t pinmapping[] = {
-     284:	2250      	movs	r2, #80	; 0x50
-     286:	498a      	ldr	r1, [pc, #552]	; (4b0 <adc_init+0x354>)
-     288:	a802      	add	r0, sp, #8
-     28a:	4b88      	ldr	r3, [pc, #544]	; (4ac <adc_init+0x350>)
-     28c:	4798      	blx	r3
-	if (pin <= ADC_EXTCHANNEL_MSB) {
-     28e:	2c13      	cmp	r4, #19
-     290:	d8cd      	bhi.n	22e <adc_init+0xd2>
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
-     292:	00a4      	lsls	r4, r4, #2
-     294:	ab02      	add	r3, sp, #8
-     296:	58e0      	ldr	r0, [r4, r3]
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-     298:	a901      	add	r1, sp, #4
-     29a:	2300      	movs	r3, #0
-     29c:	704b      	strb	r3, [r1, #1]
-	config->powersave    = false;
-     29e:	70cb      	strb	r3, [r1, #3]
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-     2a0:	708b      	strb	r3, [r1, #2]
-		config.mux_position = 1;
-     2a2:	3301      	adds	r3, #1
-     2a4:	700b      	strb	r3, [r1, #0]
-		system_pinmux_pin_set_config(pin_map_result, &config);
-     2a6:	b2c0      	uxtb	r0, r0
-     2a8:	4b82      	ldr	r3, [pc, #520]	; (4b4 <adc_init+0x358>)
-     2aa:	4798      	blx	r3
-     2ac:	e7bf      	b.n	22e <adc_init+0xd2>
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
-     2ae:	00a4      	lsls	r4, r4, #2
-     2b0:	ab02      	add	r3, sp, #8
-     2b2:	58e0      	ldr	r0, [r4, r3]
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-     2b4:	a901      	add	r1, sp, #4
-     2b6:	2300      	movs	r3, #0
-     2b8:	704b      	strb	r3, [r1, #1]
-	config->powersave    = false;
-     2ba:	70cb      	strb	r3, [r1, #3]
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-     2bc:	708b      	strb	r3, [r1, #2]
-		config.mux_position = 1;
-     2be:	3301      	adds	r3, #1
-     2c0:	700b      	strb	r3, [r1, #0]
-		system_pinmux_pin_set_config(pin_map_result, &config);
-     2c2:	b2c0      	uxtb	r0, r0
-     2c4:	4b7b      	ldr	r3, [pc, #492]	; (4b4 <adc_init+0x358>)
-     2c6:	4798      	blx	r3
-     2c8:	e7db      	b.n	282 <adc_init+0x126>
-		accumulate = ADC_ACCUMULATE_SAMPLES_16;
-     2ca:	2304      	movs	r3, #4
-		resolution = ADC_RESOLUTION_16BIT;
-     2cc:	2410      	movs	r4, #16
-		adjres = ADC_DIVIDE_RESULT_4;
-     2ce:	2102      	movs	r1, #2
-     2d0:	e01a      	b.n	308 <adc_init+0x1ac>
-		adjres = config->divide_result;
-     2d2:	7c71      	ldrb	r1, [r6, #17]
-		accumulate = config->accumulate_samples;
-     2d4:	7c33      	ldrb	r3, [r6, #16]
-		resolution = ADC_RESOLUTION_16BIT;
-     2d6:	2410      	movs	r4, #16
-     2d8:	e016      	b.n	308 <adc_init+0x1ac>
-		accumulate = ADC_ACCUMULATE_SAMPLES_64;
-     2da:	2306      	movs	r3, #6
-		resolution = ADC_RESOLUTION_16BIT;
-     2dc:	2410      	movs	r4, #16
-		adjres = ADC_DIVIDE_RESULT_2;
-     2de:	2101      	movs	r1, #1
-     2e0:	e012      	b.n	308 <adc_init+0x1ac>
-		accumulate = ADC_ACCUMULATE_SAMPLES_256;
-     2e2:	2308      	movs	r3, #8
-		resolution = ADC_RESOLUTION_16BIT;
-     2e4:	2410      	movs	r4, #16
-		adjres = ADC_DIVIDE_RESULT_DISABLE;
-     2e6:	2100      	movs	r1, #0
-     2e8:	e00e      	b.n	308 <adc_init+0x1ac>
-	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
-     2ea:	2300      	movs	r3, #0
-		resolution = ADC_RESOLUTION_8BIT;
-     2ec:	2430      	movs	r4, #48	; 0x30
-	uint8_t adjres = 0;
-     2ee:	2100      	movs	r1, #0
-     2f0:	e00a      	b.n	308 <adc_init+0x1ac>
-	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
-     2f2:	2300      	movs	r3, #0
-		resolution = ADC_RESOLUTION_10BIT;
-     2f4:	2420      	movs	r4, #32
-	uint8_t adjres = 0;
-     2f6:	2100      	movs	r1, #0
-     2f8:	e006      	b.n	308 <adc_init+0x1ac>
-	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
-     2fa:	2300      	movs	r3, #0
-		resolution = ADC_RESOLUTION_12BIT;
-     2fc:	2400      	movs	r4, #0
-	uint8_t adjres = 0;
-     2fe:	2100      	movs	r1, #0
-     300:	e002      	b.n	308 <adc_init+0x1ac>
-		accumulate = ADC_ACCUMULATE_SAMPLES_4;
-     302:	2302      	movs	r3, #2
-		resolution = ADC_RESOLUTION_16BIT;
-     304:	2410      	movs	r4, #16
-		adjres = ADC_DIVIDE_RESULT_2;
-     306:	2101      	movs	r1, #1
-	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
-     308:	0109      	lsls	r1, r1, #4
-     30a:	2270      	movs	r2, #112	; 0x70
-     30c:	400a      	ands	r2, r1
-     30e:	4313      	orrs	r3, r2
-     310:	4642      	mov	r2, r8
-     312:	7093      	strb	r3, [r2, #2]
-	if (config->sample_length > 63) {
-     314:	7df3      	ldrb	r3, [r6, #23]
-		return STATUS_ERR_INVALID_ARG;
-     316:	2017      	movs	r0, #23
-	if (config->sample_length > 63) {
-     318:	2b3f      	cmp	r3, #63	; 0x3f
-     31a:	d900      	bls.n	31e <adc_init+0x1c2>
-     31c:	e731      	b.n	182 <adc_init+0x26>
-		adc_module->SAMPCTRL.reg =
-     31e:	70d3      	strb	r3, [r2, #3]
-	struct adc_module *const module_inst)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	Adc *const adc_module = module_inst->hw;
-     320:	683a      	ldr	r2, [r7, #0]
-
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-     322:	7e53      	ldrb	r3, [r2, #25]
-	while (adc_is_syncing(module_inst)) {
-     324:	b25b      	sxtb	r3, r3
-     326:	2b00      	cmp	r3, #0
-     328:	dbfb      	blt.n	322 <adc_init+0x1c6>
-			(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
-     32a:	7cf3      	ldrb	r3, [r6, #19]
-			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
-     32c:	8872      	ldrh	r2, [r6, #2]
-     32e:	4313      	orrs	r3, r2
-			(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
-     330:	2224      	movs	r2, #36	; 0x24
-     332:	5cb2      	ldrb	r2, [r6, r2]
-     334:	00d2      	lsls	r2, r2, #3
-			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
-     336:	4313      	orrs	r3, r2
-			(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
-     338:	7d32      	ldrb	r2, [r6, #20]
-     33a:	0092      	lsls	r2, r2, #2
-			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
-     33c:	4313      	orrs	r3, r2
-     33e:	7cb2      	ldrb	r2, [r6, #18]
-     340:	0052      	lsls	r2, r2, #1
-     342:	4313      	orrs	r3, r2
-     344:	4323      	orrs	r3, r4
-	adc_module->CTRLB.reg =
-     346:	4642      	mov	r2, r8
-     348:	8093      	strh	r3, [r2, #4]
-	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
-     34a:	7e33      	ldrb	r3, [r6, #24]
-     34c:	2b00      	cmp	r3, #0
-     34e:	d020      	beq.n	392 <adc_init+0x236>
-		switch (resolution) {
-     350:	2c10      	cmp	r4, #16
-     352:	d100      	bne.n	356 <adc_init+0x1fa>
-     354:	e0d6      	b.n	504 <adc_init+0x3a8>
-     356:	d800      	bhi.n	35a <adc_init+0x1fe>
-     358:	e080      	b.n	45c <adc_init+0x300>
-     35a:	2c20      	cmp	r4, #32
-     35c:	d100      	bne.n	360 <adc_init+0x204>
-     35e:	e0b3      	b.n	4c8 <adc_init+0x36c>
-     360:	2c30      	cmp	r4, #48	; 0x30
-     362:	d116      	bne.n	392 <adc_init+0x236>
-			if (config->differential_mode &&
-     364:	7cf2      	ldrb	r2, [r6, #19]
-     366:	2a00      	cmp	r2, #0
-     368:	d00a      	beq.n	380 <adc_init+0x224>
-					(config->window.window_lower_value > 127 ||
-     36a:	69f2      	ldr	r2, [r6, #28]
-     36c:	3280      	adds	r2, #128	; 0x80
-				return STATUS_ERR_INVALID_ARG;
-     36e:	2017      	movs	r0, #23
-			if (config->differential_mode &&
-     370:	2aff      	cmp	r2, #255	; 0xff
-     372:	d900      	bls.n	376 <adc_init+0x21a>
-     374:	e705      	b.n	182 <adc_init+0x26>
-					config->window.window_lower_value < -128 ||
-     376:	6a32      	ldr	r2, [r6, #32]
-     378:	3280      	adds	r2, #128	; 0x80
-     37a:	2aff      	cmp	r2, #255	; 0xff
-     37c:	d900      	bls.n	380 <adc_init+0x224>
-     37e:	e700      	b.n	182 <adc_init+0x26>
-				return STATUS_ERR_INVALID_ARG;
-     380:	2017      	movs	r0, #23
-			} else if (config->window.window_lower_value > 255 ||
-     382:	69f2      	ldr	r2, [r6, #28]
-     384:	2aff      	cmp	r2, #255	; 0xff
-     386:	dd00      	ble.n	38a <adc_init+0x22e>
-     388:	e6fb      	b.n	182 <adc_init+0x26>
-     38a:	6a32      	ldr	r2, [r6, #32]
-     38c:	2aff      	cmp	r2, #255	; 0xff
-     38e:	dd00      	ble.n	392 <adc_init+0x236>
-     390:	e6f7      	b.n	182 <adc_init+0x26>
-	Adc *const adc_module = module_inst->hw;
-     392:	6839      	ldr	r1, [r7, #0]
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-     394:	7e4a      	ldrb	r2, [r1, #25]
-	while (adc_is_syncing(module_inst)) {
-     396:	b252      	sxtb	r2, r2
-     398:	2a00      	cmp	r2, #0
-     39a:	dbfb      	blt.n	394 <adc_init+0x238>
-	adc_module->WINCTRL.reg = config->window.window_mode;
-     39c:	4642      	mov	r2, r8
-     39e:	7213      	strb	r3, [r2, #8]
-	Adc *const adc_module = module_inst->hw;
-     3a0:	683a      	ldr	r2, [r7, #0]
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-     3a2:	7e53      	ldrb	r3, [r2, #25]
-	while (adc_is_syncing(module_inst)) {
-     3a4:	b25b      	sxtb	r3, r3
-     3a6:	2b00      	cmp	r3, #0
-     3a8:	dbfb      	blt.n	3a2 <adc_init+0x246>
-	adc_module->WINLT.reg =
-     3aa:	8bb3      	ldrh	r3, [r6, #28]
-     3ac:	4642      	mov	r2, r8
-     3ae:	8393      	strh	r3, [r2, #28]
-	Adc *const adc_module = module_inst->hw;
-     3b0:	683a      	ldr	r2, [r7, #0]
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-     3b2:	7e53      	ldrb	r3, [r2, #25]
-	while (adc_is_syncing(module_inst)) {
-     3b4:	b25b      	sxtb	r3, r3
-     3b6:	2b00      	cmp	r3, #0
-     3b8:	dbfb      	blt.n	3b2 <adc_init+0x256>
-	adc_module->WINUT.reg = config->window.window_upper_value <<
-     3ba:	8c33      	ldrh	r3, [r6, #32]
-     3bc:	4642      	mov	r2, r8
-     3be:	8413      	strh	r3, [r2, #32]
-	uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
-     3c0:	232c      	movs	r3, #44	; 0x2c
-     3c2:	5cf3      	ldrb	r3, [r6, r3]
-	if (inputs_to_scan > 0) {
-     3c4:	2b00      	cmp	r3, #0
-     3c6:	d005      	beq.n	3d4 <adc_init+0x278>
-		inputs_to_scan--;
-     3c8:	3b01      	subs	r3, #1
-     3ca:	b2db      	uxtb	r3, r3
-		return STATUS_ERR_INVALID_ARG;
-     3cc:	2017      	movs	r0, #23
-	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
-     3ce:	2b0f      	cmp	r3, #15
-     3d0:	d900      	bls.n	3d4 <adc_init+0x278>
-     3d2:	e6d6      	b.n	182 <adc_init+0x26>
-			config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
-     3d4:	222b      	movs	r2, #43	; 0x2b
-     3d6:	5cb1      	ldrb	r1, [r6, r2]
-		return STATUS_ERR_INVALID_ARG;
-     3d8:	2017      	movs	r0, #23
-	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
-     3da:	290f      	cmp	r1, #15
-     3dc:	d900      	bls.n	3e0 <adc_init+0x284>
-     3de:	e6d0      	b.n	182 <adc_init+0x26>
-	Adc *const adc_module = module_inst->hw;
-     3e0:	6838      	ldr	r0, [r7, #0]
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-     3e2:	7e42      	ldrb	r2, [r0, #25]
-	while (adc_is_syncing(module_inst)) {
-     3e4:	b252      	sxtb	r2, r2
-     3e6:	2a00      	cmp	r2, #0
-     3e8:	dbfb      	blt.n	3e2 <adc_init+0x286>
-			config->negative_input |
-     3ea:	89f2      	ldrh	r2, [r6, #14]
-			config->positive_input;
-     3ec:	7b30      	ldrb	r0, [r6, #12]
-			config->negative_input |
-     3ee:	4302      	orrs	r2, r0
-     3f0:	68b0      	ldr	r0, [r6, #8]
-     3f2:	4302      	orrs	r2, r0
-			(config->pin_scan.offset_start_scan <<
-     3f4:	0509      	lsls	r1, r1, #20
-			config->negative_input |
-     3f6:	430a      	orrs	r2, r1
-			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
-     3f8:	041b      	lsls	r3, r3, #16
-			config->negative_input |
-     3fa:	4313      	orrs	r3, r2
-	adc_module->INPUTCTRL.reg =
-     3fc:	4642      	mov	r2, r8
-     3fe:	6113      	str	r3, [r2, #16]
-	adc_module->EVCTRL.reg = config->event_action;
-     400:	232a      	movs	r3, #42	; 0x2a
-     402:	5cf3      	ldrb	r3, [r6, r3]
-     404:	7513      	strb	r3, [r2, #20]
-	adc_module->INTENCLR.reg =
-     406:	230f      	movs	r3, #15
-     408:	7593      	strb	r3, [r2, #22]
-	if (config->correction.correction_enable){
-     40a:	3315      	adds	r3, #21
-     40c:	5cf3      	ldrb	r3, [r6, r3]
-     40e:	2b00      	cmp	r3, #0
-     410:	d012      	beq.n	438 <adc_init+0x2dc>
-		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
-     412:	8cf3      	ldrh	r3, [r6, #38]	; 0x26
-     414:	4a29      	ldr	r2, [pc, #164]	; (4bc <adc_init+0x360>)
-			return STATUS_ERR_INVALID_ARG;
-     416:	2017      	movs	r0, #23
-		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
-     418:	4293      	cmp	r3, r2
-     41a:	d900      	bls.n	41e <adc_init+0x2c2>
-     41c:	e6b1      	b.n	182 <adc_init+0x26>
-			adc_module->GAINCORR.reg = config->correction.gain_correction <<
-     41e:	4642      	mov	r2, r8
-     420:	8493      	strh	r3, [r2, #36]	; 0x24
-		if (config->correction.offset_correction > 2047 ||
-     422:	8d32      	ldrh	r2, [r6, #40]	; 0x28
-     424:	2380      	movs	r3, #128	; 0x80
-     426:	011b      	lsls	r3, r3, #4
-     428:	18d3      	adds	r3, r2, r3
-     42a:	4924      	ldr	r1, [pc, #144]	; (4bc <adc_init+0x360>)
-     42c:	b29b      	uxth	r3, r3
-     42e:	428b      	cmp	r3, r1
-     430:	d900      	bls.n	434 <adc_init+0x2d8>
-     432:	e6a6      	b.n	182 <adc_init+0x26>
-			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
-     434:	4643      	mov	r3, r8
-     436:	84da      	strh	r2, [r3, #38]	; 0x26
-			ADC_CALIB_BIAS_CAL(
-     438:	4b21      	ldr	r3, [pc, #132]	; (4c0 <adc_init+0x364>)
-     43a:	681b      	ldr	r3, [r3, #0]
-     43c:	015b      	lsls	r3, r3, #5
-     43e:	22e0      	movs	r2, #224	; 0xe0
-     440:	00d2      	lsls	r2, r2, #3
-     442:	4013      	ands	r3, r2
-			ADC_CALIB_LINEARITY_CAL(
-     444:	4a1f      	ldr	r2, [pc, #124]	; (4c4 <adc_init+0x368>)
-     446:	6851      	ldr	r1, [r2, #4]
-     448:	0149      	lsls	r1, r1, #5
-     44a:	6812      	ldr	r2, [r2, #0]
-     44c:	0ed2      	lsrs	r2, r2, #27
-     44e:	430a      	orrs	r2, r1
-     450:	b2d2      	uxtb	r2, r2
-			) |
-     452:	4313      	orrs	r3, r2
-	adc_module->CALIB.reg =
-     454:	4642      	mov	r2, r8
-     456:	8513      	strh	r3, [r2, #40]	; 0x28
-	return STATUS_OK;
-     458:	2000      	movs	r0, #0
-     45a:	e692      	b.n	182 <adc_init+0x26>
-		switch (resolution) {
-     45c:	2c00      	cmp	r4, #0
-     45e:	d198      	bne.n	392 <adc_init+0x236>
-			if (config->differential_mode &&
-     460:	7cf2      	ldrb	r2, [r6, #19]
-     462:	2a00      	cmp	r2, #0
-     464:	d00f      	beq.n	486 <adc_init+0x32a>
-					(config->window.window_lower_value > 2047 ||
-     466:	69f2      	ldr	r2, [r6, #28]
-     468:	2180      	movs	r1, #128	; 0x80
-     46a:	0109      	lsls	r1, r1, #4
-     46c:	468c      	mov	ip, r1
-     46e:	4462      	add	r2, ip
-			if (config->differential_mode &&
-     470:	4912      	ldr	r1, [pc, #72]	; (4bc <adc_init+0x360>)
-				return STATUS_ERR_INVALID_ARG;
-     472:	2017      	movs	r0, #23
-			if (config->differential_mode &&
-     474:	428a      	cmp	r2, r1
-     476:	d900      	bls.n	47a <adc_init+0x31e>
-     478:	e683      	b.n	182 <adc_init+0x26>
-					config->window.window_lower_value < -2048 ||
-     47a:	6a32      	ldr	r2, [r6, #32]
-     47c:	4462      	add	r2, ip
-     47e:	490f      	ldr	r1, [pc, #60]	; (4bc <adc_init+0x360>)
-     480:	428a      	cmp	r2, r1
-     482:	d900      	bls.n	486 <adc_init+0x32a>
-     484:	e67d      	b.n	182 <adc_init+0x26>
-			} else if (config->window.window_lower_value > 4095 ||
-     486:	4a0d      	ldr	r2, [pc, #52]	; (4bc <adc_init+0x360>)
-				return STATUS_ERR_INVALID_ARG;
-     488:	2017      	movs	r0, #23
-			} else if (config->window.window_lower_value > 4095 ||
-     48a:	69f1      	ldr	r1, [r6, #28]
-     48c:	4291      	cmp	r1, r2
-     48e:	dd00      	ble.n	492 <adc_init+0x336>
-     490:	e677      	b.n	182 <adc_init+0x26>
-     492:	6a31      	ldr	r1, [r6, #32]
-     494:	4291      	cmp	r1, r2
-     496:	dd00      	ble.n	49a <adc_init+0x33e>
-     498:	e673      	b.n	182 <adc_init+0x26>
-     49a:	e77a      	b.n	392 <adc_init+0x236>
-     49c:	40000400 	.word	0x40000400
-     4a0:	40000800 	.word	0x40000800
-     4a4:	00001af5 	.word	0x00001af5
-     4a8:	00001a69 	.word	0x00001a69
-     4ac:	000026c9 	.word	0x000026c9
-     4b0:	000037a4 	.word	0x000037a4
-     4b4:	00001bed 	.word	0x00001bed
-     4b8:	000036d0 	.word	0x000036d0
-     4bc:	00000fff 	.word	0x00000fff
-     4c0:	00806024 	.word	0x00806024
-     4c4:	00806020 	.word	0x00806020
-			if (config->differential_mode &&
-     4c8:	7cf2      	ldrb	r2, [r6, #19]
-     4ca:	2a00      	cmp	r2, #0
-     4cc:	d00f      	beq.n	4ee <adc_init+0x392>
-					(config->window.window_lower_value > 511 ||
-     4ce:	69f2      	ldr	r2, [r6, #28]
-     4d0:	2180      	movs	r1, #128	; 0x80
-     4d2:	0089      	lsls	r1, r1, #2
-     4d4:	468c      	mov	ip, r1
-     4d6:	4462      	add	r2, ip
-			if (config->differential_mode &&
-     4d8:	491a      	ldr	r1, [pc, #104]	; (544 <adc_init+0x3e8>)
-				return STATUS_ERR_INVALID_ARG;
-     4da:	2017      	movs	r0, #23
-			if (config->differential_mode &&
-     4dc:	428a      	cmp	r2, r1
-     4de:	d900      	bls.n	4e2 <adc_init+0x386>
-     4e0:	e64f      	b.n	182 <adc_init+0x26>
-					config->window.window_lower_value < -512 ||
-     4e2:	6a32      	ldr	r2, [r6, #32]
-     4e4:	4462      	add	r2, ip
-     4e6:	4917      	ldr	r1, [pc, #92]	; (544 <adc_init+0x3e8>)
-     4e8:	428a      	cmp	r2, r1
-     4ea:	d900      	bls.n	4ee <adc_init+0x392>
-     4ec:	e649      	b.n	182 <adc_init+0x26>
-			} else if (config->window.window_lower_value > 1023 ||
-     4ee:	4a15      	ldr	r2, [pc, #84]	; (544 <adc_init+0x3e8>)
-				return STATUS_ERR_INVALID_ARG;
-     4f0:	2017      	movs	r0, #23
-			} else if (config->window.window_lower_value > 1023 ||
-     4f2:	69f1      	ldr	r1, [r6, #28]
-     4f4:	4291      	cmp	r1, r2
-     4f6:	dd00      	ble.n	4fa <adc_init+0x39e>
-     4f8:	e643      	b.n	182 <adc_init+0x26>
-     4fa:	6a31      	ldr	r1, [r6, #32]
-     4fc:	4291      	cmp	r1, r2
-     4fe:	dd00      	ble.n	502 <adc_init+0x3a6>
-     500:	e63f      	b.n	182 <adc_init+0x26>
-     502:	e746      	b.n	392 <adc_init+0x236>
-			if (config->differential_mode &&
-     504:	7cf2      	ldrb	r2, [r6, #19]
-     506:	2a00      	cmp	r2, #0
-     508:	d00f      	beq.n	52a <adc_init+0x3ce>
-					(config->window.window_lower_value > 32767 ||
-     50a:	69f2      	ldr	r2, [r6, #28]
-     50c:	2180      	movs	r1, #128	; 0x80
-     50e:	0209      	lsls	r1, r1, #8
-     510:	468c      	mov	ip, r1
-     512:	4462      	add	r2, ip
-			if (config->differential_mode &&
-     514:	490c      	ldr	r1, [pc, #48]	; (548 <adc_init+0x3ec>)
-				return STATUS_ERR_INVALID_ARG;
-     516:	2017      	movs	r0, #23
-			if (config->differential_mode &&
-     518:	428a      	cmp	r2, r1
-     51a:	d900      	bls.n	51e <adc_init+0x3c2>
-     51c:	e631      	b.n	182 <adc_init+0x26>
-					config->window.window_lower_value < -32768 ||
-     51e:	6a32      	ldr	r2, [r6, #32]
-     520:	4462      	add	r2, ip
-     522:	4909      	ldr	r1, [pc, #36]	; (548 <adc_init+0x3ec>)
-     524:	428a      	cmp	r2, r1
-     526:	d900      	bls.n	52a <adc_init+0x3ce>
-     528:	e62b      	b.n	182 <adc_init+0x26>
-			} else if (config->window.window_lower_value > 65535 ||
-     52a:	4a07      	ldr	r2, [pc, #28]	; (548 <adc_init+0x3ec>)
-				return STATUS_ERR_INVALID_ARG;
-     52c:	2017      	movs	r0, #23
-			} else if (config->window.window_lower_value > 65535 ||
-     52e:	69f1      	ldr	r1, [r6, #28]
-     530:	4291      	cmp	r1, r2
-     532:	dd00      	ble.n	536 <adc_init+0x3da>
-     534:	e625      	b.n	182 <adc_init+0x26>
-     536:	6a31      	ldr	r1, [r6, #32]
-     538:	4291      	cmp	r1, r2
-     53a:	dd00      	ble.n	53e <adc_init+0x3e2>
-     53c:	e621      	b.n	182 <adc_init+0x26>
-     53e:	e728      	b.n	392 <adc_init+0x236>
-		return STATUS_ERR_INVALID_ARG;
-     540:	2017      	movs	r0, #23
-     542:	e61e      	b.n	182 <adc_init+0x26>
-     544:	000003ff 	.word	0x000003ff
-     548:	0000ffff 	.word	0x0000ffff
-
-0000054c <DMAC_Handler>:
-/**
- * \brief DMA interrupt service routine.
- *
- */
-void DMAC_Handler( void )
-{
-     54c:	b510      	push	{r4, lr}
- * are only re-enabled upon leaving the outermost nested critical section.
- *
- */
-static inline void system_interrupt_enter_critical_section(void)
-{
-	cpu_irq_enter_critical();
-     54e:	4b26      	ldr	r3, [pc, #152]	; (5e8 <DMAC_Handler+0x9c>)
-     550:	4798      	blx	r3
-	uint32_t total_size;
-
-	system_interrupt_enter_critical_section();
-
-	/* Get Pending channel */
-	active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
-     552:	4926      	ldr	r1, [pc, #152]	; (5ec <DMAC_Handler+0xa0>)
-     554:	8c0b      	ldrh	r3, [r1, #32]
-     556:	220f      	movs	r2, #15
-
-	Assert(_dma_active_resource[active_channel]);
-
-	/* Get active DMA resource based on channel */
-	resource = _dma_active_resource[active_channel];
-     558:	4013      	ands	r3, r2
-     55a:	009b      	lsls	r3, r3, #2
-     55c:	4824      	ldr	r0, [pc, #144]	; (5f0 <DMAC_Handler+0xa4>)
-     55e:	5818      	ldr	r0, [r3, r0]
-
-	/* Select the active channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-     560:	7803      	ldrb	r3, [r0, #0]
-     562:	401a      	ands	r2, r3
-     564:	233f      	movs	r3, #63	; 0x3f
-     566:	54ca      	strb	r2, [r1, r3]
-	isr = DMAC->CHINTFLAG.reg;
-     568:	330f      	adds	r3, #15
-     56a:	5cca      	ldrb	r2, [r1, r3]
-     56c:	b2d2      	uxtb	r2, r2
-
-	/* Calculate block transfer size of the DMA transfer */
-	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
-     56e:	7803      	ldrb	r3, [r0, #0]
-     570:	011b      	lsls	r3, r3, #4
-     572:	4920      	ldr	r1, [pc, #128]	; (5f4 <DMAC_Handler+0xa8>)
-     574:	18c9      	adds	r1, r1, r3
-     576:	8849      	ldrh	r1, [r1, #2]
-	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
-     578:	4c1f      	ldr	r4, [pc, #124]	; (5f8 <DMAC_Handler+0xac>)
-     57a:	18e3      	adds	r3, r4, r3
-     57c:	885b      	ldrh	r3, [r3, #2]
-	resource->transfered_size = total_size - write_size;
-     57e:	1acb      	subs	r3, r1, r3
-     580:	6143      	str	r3, [r0, #20]
-
-	/* DMA channel interrupt handler */
-	if (isr & DMAC_CHINTENCLR_TERR) {
-     582:	07d3      	lsls	r3, r2, #31
-     584:	d50f      	bpl.n	5a6 <DMAC_Handler+0x5a>
-		/* Clear transfer error flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
-     586:	2101      	movs	r1, #1
-     588:	234e      	movs	r3, #78	; 0x4e
-     58a:	4a18      	ldr	r2, [pc, #96]	; (5ec <DMAC_Handler+0xa0>)
-     58c:	54d1      	strb	r1, [r2, r3]
-
-		/* Set I/O ERROR status */
-		resource->job_status = STATUS_ERR_IO;
-     58e:	3b3e      	subs	r3, #62	; 0x3e
-     590:	7443      	strb	r3, [r0, #17]
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
-     592:	7c03      	ldrb	r3, [r0, #16]
-     594:	07db      	lsls	r3, r3, #31
-     596:	d503      	bpl.n	5a0 <DMAC_Handler+0x54>
-				(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
-     598:	6843      	ldr	r3, [r0, #4]
-		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
-     59a:	2b00      	cmp	r3, #0
-     59c:	d000      	beq.n	5a0 <DMAC_Handler+0x54>
-			resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
-     59e:	4798      	blx	r3
- * are only re-enabled upon leaving the outermost nested critical section.
- *
- */
-static inline void system_interrupt_leave_critical_section(void)
-{
-	cpu_irq_leave_critical();
-     5a0:	4b16      	ldr	r3, [pc, #88]	; (5fc <DMAC_Handler+0xb0>)
-     5a2:	4798      	blx	r3
-			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
-		}
-	}
-
-	system_interrupt_leave_critical_section();
-}
-     5a4:	bd10      	pop	{r4, pc}
-	} else if (isr & DMAC_CHINTENCLR_TCMPL) {
-     5a6:	0793      	lsls	r3, r2, #30
-     5a8:	d50d      	bpl.n	5c6 <DMAC_Handler+0x7a>
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
-     5aa:	2102      	movs	r1, #2
-     5ac:	234e      	movs	r3, #78	; 0x4e
-     5ae:	4a0f      	ldr	r2, [pc, #60]	; (5ec <DMAC_Handler+0xa0>)
-     5b0:	54d1      	strb	r1, [r2, r3]
-		resource->job_status = STATUS_OK;
-     5b2:	2300      	movs	r3, #0
-     5b4:	7443      	strb	r3, [r0, #17]
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
-     5b6:	7c03      	ldrb	r3, [r0, #16]
-     5b8:	079b      	lsls	r3, r3, #30
-     5ba:	d5f1      	bpl.n	5a0 <DMAC_Handler+0x54>
-				(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
-     5bc:	6883      	ldr	r3, [r0, #8]
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
-     5be:	2b00      	cmp	r3, #0
-     5c0:	d0ee      	beq.n	5a0 <DMAC_Handler+0x54>
-			resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
-     5c2:	4798      	blx	r3
-     5c4:	e7ec      	b.n	5a0 <DMAC_Handler+0x54>
-	} else if (isr & DMAC_CHINTENCLR_SUSP) {
-     5c6:	0753      	lsls	r3, r2, #29
-     5c8:	d5ea      	bpl.n	5a0 <DMAC_Handler+0x54>
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
-     5ca:	2104      	movs	r1, #4
-     5cc:	234e      	movs	r3, #78	; 0x4e
-     5ce:	4a07      	ldr	r2, [pc, #28]	; (5ec <DMAC_Handler+0xa0>)
-     5d0:	54d1      	strb	r1, [r2, r3]
-		resource->job_status = STATUS_SUSPEND;
-     5d2:	3b48      	subs	r3, #72	; 0x48
-     5d4:	7443      	strb	r3, [r0, #17]
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
-     5d6:	7c03      	ldrb	r3, [r0, #16]
-     5d8:	075b      	lsls	r3, r3, #29
-     5da:	d5e1      	bpl.n	5a0 <DMAC_Handler+0x54>
-			(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
-     5dc:	68c3      	ldr	r3, [r0, #12]
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
-     5de:	2b00      	cmp	r3, #0
-     5e0:	d0de      	beq.n	5a0 <DMAC_Handler+0x54>
-			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
-     5e2:	4798      	blx	r3
-     5e4:	e7dc      	b.n	5a0 <DMAC_Handler+0x54>
-     5e6:	46c0      	nop			; (mov r8, r8)
-     5e8:	000015e1 	.word	0x000015e1
-     5ec:	41004800 	.word	0x41004800
-     5f0:	2000009c 	.word	0x2000009c
-     5f4:	200001e0 	.word	0x200001e0
-     5f8:	200000b0 	.word	0x200000b0
-     5fc:	00001621 	.word	0x00001621
-
-00000600 <dma_get_config_defaults>:
- */
-void dma_get_config_defaults(struct dma_resource_config *config)
-{
-	Assert(config);
-	/* Set as priority 0 */
-	config->priority = DMA_PRIORITY_LEVEL_0;
-     600:	2300      	movs	r3, #0
-     602:	7003      	strb	r3, [r0, #0]
-	/* Only software/event trigger */
-	config->peripheral_trigger = 0;
-     604:	7043      	strb	r3, [r0, #1]
-	/* Transaction trigger */
-	config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
-     606:	2203      	movs	r2, #3
-     608:	7082      	strb	r2, [r0, #2]
-
-	/* Event configurations, no event input/output */
-	config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
-     60a:	70c3      	strb	r3, [r0, #3]
-	config->event_config.event_output_enable = false;
-     60c:	7103      	strb	r3, [r0, #4]
-#ifdef FEATURE_DMA_CHANNEL_STANDBY
-	config->run_in_standby = false;
-#endif
-}
-     60e:	4770      	bx	lr
-
-00000610 <dma_allocate>:
- * \retval STATUS_OK The DMA resource was allocated successfully
- * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
- */
-enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config)
-{
-     610:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-     612:	46ce      	mov	lr, r9
-     614:	4647      	mov	r7, r8
-     616:	b580      	push	{r7, lr}
-     618:	0005      	movs	r5, r0
-     61a:	000e      	movs	r6, r1
-	cpu_irq_enter_critical();
-     61c:	4b45      	ldr	r3, [pc, #276]	; (734 <dma_allocate+0x124>)
-     61e:	4798      	blx	r3
-
-	Assert(resource);
-
-	system_interrupt_enter_critical_section();
-
-	if (!_dma_inst._dma_init) {
-     620:	4b45      	ldr	r3, [pc, #276]	; (738 <dma_allocate+0x128>)
-     622:	781b      	ldrb	r3, [r3, #0]
-     624:	2b00      	cmp	r3, #0
-     626:	d118      	bne.n	65a <dma_allocate+0x4a>
-	PM->AHBMASK.reg |= ahb_mask;
-     628:	4b44      	ldr	r3, [pc, #272]	; (73c <dma_allocate+0x12c>)
-     62a:	695a      	ldr	r2, [r3, #20]
-     62c:	2120      	movs	r1, #32
-     62e:	430a      	orrs	r2, r1
-     630:	615a      	str	r2, [r3, #20]
-			PM->APBBMASK.reg |= mask;
-     632:	69da      	ldr	r2, [r3, #28]
-     634:	3910      	subs	r1, #16
-     636:	430a      	orrs	r2, r1
-     638:	61da      	str	r2, [r3, #28]
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
-				PM_APBBMASK_DMAC);
-#endif
-
-		/* Perform a software reset before enable DMA controller */
-		DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
-     63a:	4b41      	ldr	r3, [pc, #260]	; (740 <dma_allocate+0x130>)
-     63c:	881a      	ldrh	r2, [r3, #0]
-     63e:	390e      	subs	r1, #14
-     640:	438a      	bics	r2, r1
-     642:	801a      	strh	r2, [r3, #0]
-		DMAC->CTRL.reg = DMAC_CTRL_SWRST;
-     644:	2201      	movs	r2, #1
-     646:	801a      	strh	r2, [r3, #0]
-
-		/* Setup descriptor base address and write back section base
-		 * address */
-		DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
-     648:	4a3e      	ldr	r2, [pc, #248]	; (744 <dma_allocate+0x134>)
-     64a:	635a      	str	r2, [r3, #52]	; 0x34
-		DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
-     64c:	4a3e      	ldr	r2, [pc, #248]	; (748 <dma_allocate+0x138>)
-     64e:	639a      	str	r2, [r3, #56]	; 0x38
-
-		/* Enable all priority level at the same time */
-		DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
-     650:	4a3e      	ldr	r2, [pc, #248]	; (74c <dma_allocate+0x13c>)
-     652:	801a      	strh	r2, [r3, #0]
-
-		_dma_inst._dma_init = true;
-     654:	4b38      	ldr	r3, [pc, #224]	; (738 <dma_allocate+0x128>)
-     656:	2201      	movs	r2, #1
-     658:	701a      	strb	r2, [r3, #0]
-     65a:	4b36      	ldr	r3, [pc, #216]	; (734 <dma_allocate+0x124>)
-     65c:	4798      	blx	r3
-	tmp = _dma_inst.allocated_channels;
-     65e:	4b36      	ldr	r3, [pc, #216]	; (738 <dma_allocate+0x128>)
-     660:	685b      	ldr	r3, [r3, #4]
-		if (!(tmp & 0x00000001)) {
-     662:	07da      	lsls	r2, r3, #31
-     664:	d50f      	bpl.n	686 <dma_allocate+0x76>
-		tmp = tmp >> 1;
-     666:	085b      	lsrs	r3, r3, #1
-	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
-     668:	2401      	movs	r4, #1
-		if (!(tmp & 0x00000001)) {
-     66a:	2201      	movs	r2, #1
-     66c:	421a      	tst	r2, r3
-     66e:	d00b      	beq.n	688 <dma_allocate+0x78>
-		tmp = tmp >> 1;
-     670:	085b      	lsrs	r3, r3, #1
-	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
-     672:	3401      	adds	r4, #1
-     674:	b2e4      	uxtb	r4, r4
-     676:	2c05      	cmp	r4, #5
-     678:	d1f8      	bne.n	66c <dma_allocate+0x5c>
-	cpu_irq_leave_critical();
-     67a:	4b35      	ldr	r3, [pc, #212]	; (750 <dma_allocate+0x140>)
-     67c:	4798      	blx	r3
-     67e:	4b34      	ldr	r3, [pc, #208]	; (750 <dma_allocate+0x140>)
-     680:	4798      	blx	r3
-
-	/* If no channel available, return not found */
-	if (new_channel == DMA_INVALID_CHANNEL) {
-		system_interrupt_leave_critical_section();
-
-		return STATUS_ERR_NOT_FOUND;
-     682:	2014      	movs	r0, #20
-     684:	e051      	b.n	72a <dma_allocate+0x11a>
-	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
-     686:	2400      	movs	r4, #0
-			_dma_inst.allocated_channels |= 1 << count;
-     688:	4a2b      	ldr	r2, [pc, #172]	; (738 <dma_allocate+0x128>)
-     68a:	6851      	ldr	r1, [r2, #4]
-     68c:	2301      	movs	r3, #1
-     68e:	40a3      	lsls	r3, r4
-     690:	430b      	orrs	r3, r1
-     692:	6053      	str	r3, [r2, #4]
-			_dma_inst.free_channels--;
-     694:	7a13      	ldrb	r3, [r2, #8]
-     696:	3b01      	subs	r3, #1
-     698:	7213      	strb	r3, [r2, #8]
-     69a:	4b2d      	ldr	r3, [pc, #180]	; (750 <dma_allocate+0x140>)
-     69c:	4798      	blx	r3
-	if (new_channel == DMA_INVALID_CHANNEL) {
-     69e:	2cff      	cmp	r4, #255	; 0xff
-     6a0:	d0ed      	beq.n	67e <dma_allocate+0x6e>
-	}
-
-	/* Set the channel */
-	resource->channel_id = new_channel;
-     6a2:	702c      	strb	r4, [r5, #0]
-
-	/** Perform a reset for the allocated channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-     6a4:	230f      	movs	r3, #15
-     6a6:	4698      	mov	r8, r3
-     6a8:	401c      	ands	r4, r3
-     6aa:	4f25      	ldr	r7, [pc, #148]	; (740 <dma_allocate+0x130>)
-     6ac:	3330      	adds	r3, #48	; 0x30
-     6ae:	4699      	mov	r9, r3
-     6b0:	54fc      	strb	r4, [r7, r3]
-	DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
-     6b2:	3301      	adds	r3, #1
-     6b4:	5cfa      	ldrb	r2, [r7, r3]
-     6b6:	2102      	movs	r1, #2
-     6b8:	438a      	bics	r2, r1
-     6ba:	54fa      	strb	r2, [r7, r3]
-	DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
-     6bc:	2401      	movs	r4, #1
-     6be:	54fc      	strb	r4, [r7, r3]
-	cpu_irq_enter_critical();
-     6c0:	4b1c      	ldr	r3, [pc, #112]	; (734 <dma_allocate+0x124>)
-     6c2:	4798      	blx	r3
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-     6c4:	782b      	ldrb	r3, [r5, #0]
-     6c6:	4642      	mov	r2, r8
-     6c8:	4013      	ands	r3, r2
-     6ca:	464a      	mov	r2, r9
-     6cc:	54bb      	strb	r3, [r7, r2]
-	DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
-     6ce:	693b      	ldr	r3, [r7, #16]
-     6d0:	782a      	ldrb	r2, [r5, #0]
-     6d2:	4094      	lsls	r4, r2
-     6d4:	43a3      	bics	r3, r4
-     6d6:	613b      	str	r3, [r7, #16]
-	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
-     6d8:	7832      	ldrb	r2, [r6, #0]
-     6da:	0152      	lsls	r2, r2, #5
-     6dc:	2360      	movs	r3, #96	; 0x60
-     6de:	4013      	ands	r3, r2
-			DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
-     6e0:	7872      	ldrb	r2, [r6, #1]
-     6e2:	0212      	lsls	r2, r2, #8
-     6e4:	21fc      	movs	r1, #252	; 0xfc
-     6e6:	0189      	lsls	r1, r1, #6
-     6e8:	400a      	ands	r2, r1
-	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
-     6ea:	4313      	orrs	r3, r2
-			DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
-     6ec:	78b2      	ldrb	r2, [r6, #2]
-     6ee:	0592      	lsls	r2, r2, #22
-     6f0:	21c0      	movs	r1, #192	; 0xc0
-     6f2:	0409      	lsls	r1, r1, #16
-     6f4:	400a      	ands	r2, r1
-	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
-     6f6:	4313      	orrs	r3, r2
-	if(resource_config->event_config.input_action){
-     6f8:	78f1      	ldrb	r1, [r6, #3]
-     6fa:	2900      	cmp	r1, #0
-     6fc:	d004      	beq.n	708 <dma_allocate+0xf8>
-	temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
-     6fe:	2207      	movs	r2, #7
-     700:	400a      	ands	r2, r1
-     702:	2108      	movs	r1, #8
-     704:	430a      	orrs	r2, r1
-     706:	4313      	orrs	r3, r2
-	if (resource_config->event_config.event_output_enable) {
-     708:	7932      	ldrb	r2, [r6, #4]
-     70a:	2a00      	cmp	r2, #0
-     70c:	d001      	beq.n	712 <dma_allocate+0x102>
-		temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
-     70e:	2210      	movs	r2, #16
-     710:	4313      	orrs	r3, r2
-	DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
-     712:	4a0b      	ldr	r2, [pc, #44]	; (740 <dma_allocate+0x130>)
-     714:	6453      	str	r3, [r2, #68]	; 0x44
-	cpu_irq_leave_critical();
-     716:	4c0e      	ldr	r4, [pc, #56]	; (750 <dma_allocate+0x140>)
-     718:	47a0      	blx	r4
-#endif
-
-	/** Configure the DMA control,channel registers and descriptors here */
-	_dma_set_config(resource, config);
-
-	resource->descriptor = NULL;
-     71a:	2300      	movs	r3, #0
-     71c:	61ab      	str	r3, [r5, #24]
-
-	/* Log the DMA resource into the internal DMA resource pool */
-	_dma_active_resource[resource->channel_id] = resource;
-     71e:	782b      	ldrb	r3, [r5, #0]
-     720:	009b      	lsls	r3, r3, #2
-     722:	4a0c      	ldr	r2, [pc, #48]	; (754 <dma_allocate+0x144>)
-     724:	509d      	str	r5, [r3, r2]
-     726:	47a0      	blx	r4
-
-	system_interrupt_leave_critical_section();
-
-	return STATUS_OK;
-     728:	2000      	movs	r0, #0
-}
-     72a:	bc0c      	pop	{r2, r3}
-     72c:	4690      	mov	r8, r2
-     72e:	4699      	mov	r9, r3
-     730:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-     732:	46c0      	nop			; (mov r8, r8)
-     734:	000015e1 	.word	0x000015e1
-     738:	20000000 	.word	0x20000000
-     73c:	40000400 	.word	0x40000400
-     740:	41004800 	.word	0x41004800
-     744:	200001e0 	.word	0x200001e0
-     748:	200000b0 	.word	0x200000b0
-     74c:	00000f02 	.word	0x00000f02
-     750:	00001621 	.word	0x00001621
-     754:	2000009c 	.word	0x2000009c
-
-00000758 <dma_start_transfer_job>:
- * \retval STATUS_OK The transfer was started successfully
- * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
- * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
- */
-enum status_code dma_start_transfer_job(struct dma_resource *resource)
-{
-     758:	b570      	push	{r4, r5, r6, lr}
-     75a:	0004      	movs	r4, r0
-	cpu_irq_enter_critical();
-     75c:	4b19      	ldr	r3, [pc, #100]	; (7c4 <dma_start_transfer_job+0x6c>)
-     75e:	4798      	blx	r3
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	system_interrupt_enter_critical_section();
-
-	/* Check if resource was busy */
-	if (resource->job_status == STATUS_BUSY) {
-     760:	7c63      	ldrb	r3, [r4, #17]
-     762:	2b05      	cmp	r3, #5
-     764:	d008      	beq.n	778 <dma_start_transfer_job+0x20>
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
-
-	/* Check if transfer size is valid */
-	if (resource->descriptor->BTCNT.reg == 0) {
-     766:	69a3      	ldr	r3, [r4, #24]
-     768:	885b      	ldrh	r3, [r3, #2]
-     76a:	b29b      	uxth	r3, r3
-     76c:	2b00      	cmp	r3, #0
-     76e:	d107      	bne.n	780 <dma_start_transfer_job+0x28>
-	cpu_irq_leave_critical();
-     770:	4b15      	ldr	r3, [pc, #84]	; (7c8 <dma_start_transfer_job+0x70>)
-     772:	4798      	blx	r3
-		system_interrupt_leave_critical_section();
-		return STATUS_ERR_INVALID_ARG;
-     774:	2017      	movs	r0, #23
-	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-
-	system_interrupt_leave_critical_section();
-
-	return STATUS_OK;
-}
-     776:	bd70      	pop	{r4, r5, r6, pc}
-     778:	4b13      	ldr	r3, [pc, #76]	; (7c8 <dma_start_transfer_job+0x70>)
-     77a:	4798      	blx	r3
-		return STATUS_BUSY;
-     77c:	2005      	movs	r0, #5
-     77e:	e7fa      	b.n	776 <dma_start_transfer_job+0x1e>
- * \param[in] vector Interrupt vector to enable
- */
-static inline void system_interrupt_enable(
-		const enum system_interrupt_vector vector)
-{
-	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
-     780:	2640      	movs	r6, #64	; 0x40
-     782:	4b12      	ldr	r3, [pc, #72]	; (7cc <dma_start_transfer_job+0x74>)
-     784:	601e      	str	r6, [r3, #0]
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-     786:	7822      	ldrb	r2, [r4, #0]
-     788:	230f      	movs	r3, #15
-     78a:	4013      	ands	r3, r2
-     78c:	4d10      	ldr	r5, [pc, #64]	; (7d0 <dma_start_transfer_job+0x78>)
-     78e:	223f      	movs	r2, #63	; 0x3f
-     790:	54ab      	strb	r3, [r5, r2]
-	DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
-     792:	7823      	ldrb	r3, [r4, #0]
-     794:	4a0f      	ldr	r2, [pc, #60]	; (7d4 <dma_start_transfer_job+0x7c>)
-     796:	5cd2      	ldrb	r2, [r2, r3]
-     798:	2307      	movs	r3, #7
-     79a:	4013      	ands	r3, r2
-     79c:	224d      	movs	r2, #77	; 0x4d
-     79e:	54ab      	strb	r3, [r5, r2]
-	resource->job_status = STATUS_BUSY;
-     7a0:	2305      	movs	r3, #5
-     7a2:	7463      	strb	r3, [r4, #17]
-	memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
-     7a4:	7820      	ldrb	r0, [r4, #0]
-     7a6:	0100      	lsls	r0, r0, #4
-     7a8:	4b0b      	ldr	r3, [pc, #44]	; (7d8 <dma_start_transfer_job+0x80>)
-     7aa:	18c0      	adds	r0, r0, r3
-     7ac:	69a1      	ldr	r1, [r4, #24]
-     7ae:	3a3d      	subs	r2, #61	; 0x3d
-     7b0:	4b0a      	ldr	r3, [pc, #40]	; (7dc <dma_start_transfer_job+0x84>)
-     7b2:	4798      	blx	r3
-	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-     7b4:	5dab      	ldrb	r3, [r5, r6]
-     7b6:	2202      	movs	r2, #2
-     7b8:	4313      	orrs	r3, r2
-     7ba:	55ab      	strb	r3, [r5, r6]
-	cpu_irq_leave_critical();
-     7bc:	4b02      	ldr	r3, [pc, #8]	; (7c8 <dma_start_transfer_job+0x70>)
-     7be:	4798      	blx	r3
-	return STATUS_OK;
-     7c0:	2000      	movs	r0, #0
-     7c2:	e7d8      	b.n	776 <dma_start_transfer_job+0x1e>
-     7c4:	000015e1 	.word	0x000015e1
-     7c8:	00001621 	.word	0x00001621
-     7cc:	e000e100 	.word	0xe000e100
-     7d0:	41004800 	.word	0x41004800
-     7d4:	20000100 	.word	0x20000100
-     7d8:	200001e0 	.word	0x200001e0
-     7dc:	000026c9 	.word	0x000026c9
-
-000007e0 <dma_descriptor_create>:
- * \param[in] config Pointer to the descriptor configuration structure
- *
- */
-void dma_descriptor_create(DmacDescriptor* descriptor,
-	struct dma_descriptor_config *config)
-{
-     7e0:	b5f0      	push	{r4, r5, r6, r7, lr}
-	/* Set block transfer control */
-	descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
-     7e2:	780a      	ldrb	r2, [r1, #0]
-     7e4:	8803      	ldrh	r3, [r0, #0]
-     7e6:	2601      	movs	r6, #1
-     7e8:	4032      	ands	r2, r6
-     7ea:	2401      	movs	r4, #1
-     7ec:	43a3      	bics	r3, r4
-     7ee:	4313      	orrs	r3, r2
-     7f0:	8003      	strh	r3, [r0, #0]
-	descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
-     7f2:	784b      	ldrb	r3, [r1, #1]
-     7f4:	8804      	ldrh	r4, [r0, #0]
-     7f6:	2703      	movs	r7, #3
-     7f8:	403b      	ands	r3, r7
-     7fa:	005b      	lsls	r3, r3, #1
-     7fc:	2206      	movs	r2, #6
-     7fe:	4394      	bics	r4, r2
-     800:	431c      	orrs	r4, r3
-     802:	8004      	strh	r4, [r0, #0]
-	descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
-     804:	788d      	ldrb	r5, [r1, #2]
-     806:	8804      	ldrh	r4, [r0, #0]
-     808:	403d      	ands	r5, r7
-     80a:	00ed      	lsls	r5, r5, #3
-     80c:	2318      	movs	r3, #24
-     80e:	439c      	bics	r4, r3
-     810:	432c      	orrs	r4, r5
-     812:	8004      	strh	r4, [r0, #0]
-	descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
-     814:	78ca      	ldrb	r2, [r1, #3]
-     816:	8803      	ldrh	r3, [r0, #0]
-     818:	403a      	ands	r2, r7
-     81a:	0212      	lsls	r2, r2, #8
-     81c:	4c16      	ldr	r4, [pc, #88]	; (878 <dma_descriptor_create+0x98>)
-     81e:	4023      	ands	r3, r4
-     820:	4313      	orrs	r3, r2
-     822:	8003      	strh	r3, [r0, #0]
-	descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
-     824:	790b      	ldrb	r3, [r1, #4]
-     826:	8804      	ldrh	r4, [r0, #0]
-     828:	4033      	ands	r3, r6
-     82a:	029b      	lsls	r3, r3, #10
-     82c:	4a13      	ldr	r2, [pc, #76]	; (87c <dma_descriptor_create+0x9c>)
-     82e:	4014      	ands	r4, r2
-     830:	431c      	orrs	r4, r3
-     832:	8004      	strh	r4, [r0, #0]
-	descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
-     834:	794d      	ldrb	r5, [r1, #5]
-     836:	8804      	ldrh	r4, [r0, #0]
-     838:	4035      	ands	r5, r6
-     83a:	02ed      	lsls	r5, r5, #11
-     83c:	4b10      	ldr	r3, [pc, #64]	; (880 <dma_descriptor_create+0xa0>)
-     83e:	401c      	ands	r4, r3
-     840:	432c      	orrs	r4, r5
-     842:	8004      	strh	r4, [r0, #0]
-	descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
-     844:	798a      	ldrb	r2, [r1, #6]
-     846:	8803      	ldrh	r3, [r0, #0]
-     848:	4032      	ands	r2, r6
-     84a:	0312      	lsls	r2, r2, #12
-     84c:	4c0d      	ldr	r4, [pc, #52]	; (884 <dma_descriptor_create+0xa4>)
-     84e:	4023      	ands	r3, r4
-     850:	4313      	orrs	r3, r2
-     852:	8003      	strh	r3, [r0, #0]
-	descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
-     854:	79cb      	ldrb	r3, [r1, #7]
-     856:	2207      	movs	r2, #7
-     858:	401a      	ands	r2, r3
-     85a:	8803      	ldrh	r3, [r0, #0]
-     85c:	0352      	lsls	r2, r2, #13
-     85e:	04db      	lsls	r3, r3, #19
-     860:	0cdb      	lsrs	r3, r3, #19
-     862:	4313      	orrs	r3, r2
-     864:	8003      	strh	r3, [r0, #0]
-
-	/* Set transfer size, source address and destination address */
-	descriptor->BTCNT.reg = config->block_transfer_count;
-     866:	890b      	ldrh	r3, [r1, #8]
-     868:	8043      	strh	r3, [r0, #2]
-	descriptor->SRCADDR.reg = config->source_address;
-     86a:	68cb      	ldr	r3, [r1, #12]
-     86c:	6043      	str	r3, [r0, #4]
-	descriptor->DSTADDR.reg = config->destination_address;
-     86e:	690b      	ldr	r3, [r1, #16]
-     870:	6083      	str	r3, [r0, #8]
-
-	/* Set next transfer descriptor address */
-	descriptor->DESCADDR.reg = config->next_descriptor_address;
-     872:	694b      	ldr	r3, [r1, #20]
-     874:	60c3      	str	r3, [r0, #12]
-}
-     876:	bdf0      	pop	{r4, r5, r6, r7, pc}
-     878:	fffffcff 	.word	0xfffffcff
-     87c:	fffffbff 	.word	0xfffffbff
-     880:	fffff7ff 	.word	0xfffff7ff
-     884:	ffffefff 	.word	0xffffefff
-
-00000888 <dma_add_descriptor>:
-enum status_code dma_add_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor)
-{
-	DmacDescriptor* desc = resource->descriptor;
-
-	if (resource->job_status == STATUS_BUSY) {
-     888:	7c42      	ldrb	r2, [r0, #17]
-		return STATUS_BUSY;
-     88a:	2305      	movs	r3, #5
-	if (resource->job_status == STATUS_BUSY) {
-     88c:	2a05      	cmp	r2, #5
-     88e:	d00b      	beq.n	8a8 <dma_add_descriptor+0x20>
-	DmacDescriptor* desc = resource->descriptor;
-     890:	6983      	ldr	r3, [r0, #24]
-	}
-
-	/* Look up for an empty space for the descriptor */
-	if (desc == NULL) {
-     892:	2b00      	cmp	r3, #0
-     894:	d00a      	beq.n	8ac <dma_add_descriptor+0x24>
-		resource->descriptor = descriptor;
-	} else {
-		/* Looking for end of descriptor link */
-		while(desc->DESCADDR.reg != 0) {
-     896:	68da      	ldr	r2, [r3, #12]
-     898:	2a00      	cmp	r2, #0
-     89a:	d003      	beq.n	8a4 <dma_add_descriptor+0x1c>
-			desc = (DmacDescriptor*)(desc->DESCADDR.reg);
-     89c:	68db      	ldr	r3, [r3, #12]
-		while(desc->DESCADDR.reg != 0) {
-     89e:	68da      	ldr	r2, [r3, #12]
-     8a0:	2a00      	cmp	r2, #0
-     8a2:	d1fb      	bne.n	89c <dma_add_descriptor+0x14>
-		}
-
-		/* Set to the end of descriptor list */
-		desc->DESCADDR.reg = (uint32_t)descriptor;
-     8a4:	60d9      	str	r1, [r3, #12]
-	}
-
-	return STATUS_OK;
-     8a6:	2300      	movs	r3, #0
-}
-     8a8:	0018      	movs	r0, r3
-     8aa:	4770      	bx	lr
-		resource->descriptor = descriptor;
-     8ac:	6181      	str	r1, [r0, #24]
-	return STATUS_OK;
-     8ae:	2300      	movs	r3, #0
-     8b0:	e7fa      	b.n	8a8 <dma_add_descriptor+0x20>
-
-000008b2 <long_division>:
-/**
- * \internal Calculate 64 bit division, ref can be found in
- * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
- */
-static uint64_t long_division(uint64_t n, uint64_t d)
-{
-     8b2:	b5f0      	push	{r4, r5, r6, r7, lr}
-     8b4:	46de      	mov	lr, fp
-     8b6:	4657      	mov	r7, sl
-     8b8:	464e      	mov	r6, r9
-     8ba:	4645      	mov	r5, r8
-     8bc:	b5e0      	push	{r5, r6, r7, lr}
-     8be:	b087      	sub	sp, #28
-     8c0:	4680      	mov	r8, r0
-     8c2:	9104      	str	r1, [sp, #16]
-     8c4:	0016      	movs	r6, r2
-     8c6:	001f      	movs	r7, r3
-	int32_t i;
-	uint64_t q = 0, r = 0, bit_shift;
-     8c8:	2200      	movs	r2, #0
-     8ca:	2300      	movs	r3, #0
-     8cc:	2100      	movs	r1, #0
-     8ce:	468b      	mov	fp, r1
-	for (i = 63; i >= 0; i--) {
-     8d0:	243f      	movs	r4, #63	; 0x3f
-		bit_shift = (uint64_t)1 << i;
-     8d2:	2001      	movs	r0, #1
-     8d4:	0021      	movs	r1, r4
-     8d6:	9600      	str	r6, [sp, #0]
-     8d8:	9701      	str	r7, [sp, #4]
-     8da:	465c      	mov	r4, fp
-     8dc:	9403      	str	r4, [sp, #12]
-     8de:	4644      	mov	r4, r8
-     8e0:	9405      	str	r4, [sp, #20]
-     8e2:	e013      	b.n	90c <long_division+0x5a>
-     8e4:	2420      	movs	r4, #32
-     8e6:	1a64      	subs	r4, r4, r1
-     8e8:	0005      	movs	r5, r0
-     8ea:	40e5      	lsrs	r5, r4
-     8ec:	46a8      	mov	r8, r5
-     8ee:	e014      	b.n	91a <long_division+0x68>
-		if (n & bit_shift) {
-			r |= 0x01;
-		}
-
-		if (r >= d) {
-			r = r - d;
-     8f0:	9c00      	ldr	r4, [sp, #0]
-     8f2:	9d01      	ldr	r5, [sp, #4]
-     8f4:	1b12      	subs	r2, r2, r4
-     8f6:	41ab      	sbcs	r3, r5
-			q |= bit_shift;
-     8f8:	465c      	mov	r4, fp
-     8fa:	464d      	mov	r5, r9
-     8fc:	432c      	orrs	r4, r5
-     8fe:	46a3      	mov	fp, r4
-     900:	9c03      	ldr	r4, [sp, #12]
-     902:	4645      	mov	r5, r8
-     904:	432c      	orrs	r4, r5
-     906:	9403      	str	r4, [sp, #12]
-	for (i = 63; i >= 0; i--) {
-     908:	3901      	subs	r1, #1
-     90a:	d325      	bcc.n	958 <long_division+0xa6>
-		bit_shift = (uint64_t)1 << i;
-     90c:	2420      	movs	r4, #32
-     90e:	4264      	negs	r4, r4
-     910:	190c      	adds	r4, r1, r4
-     912:	d4e7      	bmi.n	8e4 <long_division+0x32>
-     914:	0005      	movs	r5, r0
-     916:	40a5      	lsls	r5, r4
-     918:	46a8      	mov	r8, r5
-     91a:	0004      	movs	r4, r0
-     91c:	408c      	lsls	r4, r1
-     91e:	46a1      	mov	r9, r4
-		r = r << 1;
-     920:	1892      	adds	r2, r2, r2
-     922:	415b      	adcs	r3, r3
-     924:	0014      	movs	r4, r2
-     926:	001d      	movs	r5, r3
-		if (n & bit_shift) {
-     928:	9e05      	ldr	r6, [sp, #20]
-     92a:	464f      	mov	r7, r9
-     92c:	403e      	ands	r6, r7
-     92e:	46b4      	mov	ip, r6
-     930:	9e04      	ldr	r6, [sp, #16]
-     932:	4647      	mov	r7, r8
-     934:	403e      	ands	r6, r7
-     936:	46b2      	mov	sl, r6
-     938:	4666      	mov	r6, ip
-     93a:	4657      	mov	r7, sl
-     93c:	433e      	orrs	r6, r7
-     93e:	d003      	beq.n	948 <long_division+0x96>
-			r |= 0x01;
-     940:	0006      	movs	r6, r0
-     942:	4326      	orrs	r6, r4
-     944:	0032      	movs	r2, r6
-     946:	002b      	movs	r3, r5
-		if (r >= d) {
-     948:	9c00      	ldr	r4, [sp, #0]
-     94a:	9d01      	ldr	r5, [sp, #4]
-     94c:	429d      	cmp	r5, r3
-     94e:	d8db      	bhi.n	908 <long_division+0x56>
-     950:	d1ce      	bne.n	8f0 <long_division+0x3e>
-     952:	4294      	cmp	r4, r2
-     954:	d8d8      	bhi.n	908 <long_division+0x56>
-     956:	e7cb      	b.n	8f0 <long_division+0x3e>
-     958:	9b03      	ldr	r3, [sp, #12]
-		}
-	}
-
-	return q;
-}
-     95a:	4658      	mov	r0, fp
-     95c:	0019      	movs	r1, r3
-     95e:	b007      	add	sp, #28
-     960:	bc3c      	pop	{r2, r3, r4, r5}
-     962:	4690      	mov	r8, r2
-     964:	4699      	mov	r9, r3
-     966:	46a2      	mov	sl, r4
-     968:	46ab      	mov	fp, r5
-     96a:	bdf0      	pop	{r4, r5, r6, r7, pc}
-
-0000096c <_sercom_get_sync_baud_val>:
- */
-enum status_code _sercom_get_sync_baud_val(
-		const uint32_t baudrate,
-		const uint32_t external_clock,
-		uint16_t *const baudvalue)
-{
-     96c:	b510      	push	{r4, lr}
-	uint16_t baud_calculated = 0;
-	uint32_t clock_value = external_clock;
-
-
-	/* Check if baudrate is outside of valid range */
-	if (baudrate > (external_clock / 2)) {
-     96e:	0849      	lsrs	r1, r1, #1
-		/* Return with error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-     970:	2340      	movs	r3, #64	; 0x40
-     972:	2400      	movs	r4, #0
-	if (baudrate > (external_clock / 2)) {
-     974:	4281      	cmp	r1, r0
-     976:	d202      	bcs.n	97e <_sercom_get_sync_baud_val+0x12>
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	} else {
-		*baudvalue = baud_calculated;
-		return STATUS_OK;
-	}
-}
-     978:	0018      	movs	r0, r3
-     97a:	bd10      	pop	{r4, pc}
-		baud_calculated++;
-     97c:	001c      	movs	r4, r3
-		clock_value = clock_value - baudrate;
-     97e:	1a09      	subs	r1, r1, r0
-		baud_calculated++;
-     980:	1c63      	adds	r3, r4, #1
-     982:	b29b      	uxth	r3, r3
-	while (clock_value >= baudrate) {
-     984:	4288      	cmp	r0, r1
-     986:	d9f9      	bls.n	97c <_sercom_get_sync_baud_val+0x10>
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-     988:	2340      	movs	r3, #64	; 0x40
-	if (baud_calculated > 0xFF) {
-     98a:	2cff      	cmp	r4, #255	; 0xff
-     98c:	d8f4      	bhi.n	978 <_sercom_get_sync_baud_val+0xc>
-		*baudvalue = baud_calculated;
-     98e:	8014      	strh	r4, [r2, #0]
-		return STATUS_OK;
-     990:	2300      	movs	r3, #0
-     992:	e7f1      	b.n	978 <_sercom_get_sync_baud_val+0xc>
-
-00000994 <_sercom_get_async_baud_val>:
-		const uint32_t baudrate,
-		const uint32_t peripheral_clock,
-		uint16_t *const baudval,
-		enum sercom_asynchronous_operation_mode mode,
-		enum sercom_asynchronous_sample_num sample_num)
-{
-     994:	b5f0      	push	{r4, r5, r6, r7, lr}
-     996:	b083      	sub	sp, #12
-     998:	000f      	movs	r7, r1
-     99a:	0016      	movs	r6, r2
-     99c:	aa08      	add	r2, sp, #32
-     99e:	7811      	ldrb	r1, [r2, #0]
-	uint8_t baud_fp;
-	uint32_t baud_int = 0;
-	uint64_t temp1;
-
-	/* Check if the baudrate is outside of valid range */
-	if ((baudrate * sample_num) > peripheral_clock) {
-     9a0:	0004      	movs	r4, r0
-     9a2:	434c      	muls	r4, r1
-		/* Return with error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-     9a4:	2240      	movs	r2, #64	; 0x40
-	if ((baudrate * sample_num) > peripheral_clock) {
-     9a6:	42bc      	cmp	r4, r7
-     9a8:	d902      	bls.n	9b0 <_sercom_get_async_baud_val+0x1c>
-		baud_calculated = baud_int | (baud_fp << 13);
-	}
-
-	*baudval = baud_calculated;
-	return STATUS_OK;
-}
-     9aa:	0010      	movs	r0, r2
-     9ac:	b003      	add	sp, #12
-     9ae:	bdf0      	pop	{r4, r5, r6, r7, pc}
-	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
-     9b0:	2b00      	cmp	r3, #0
-     9b2:	d114      	bne.n	9de <_sercom_get_async_baud_val+0x4a>
-		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
-     9b4:	0002      	movs	r2, r0
-     9b6:	0008      	movs	r0, r1
-     9b8:	2100      	movs	r1, #0
-     9ba:	4c19      	ldr	r4, [pc, #100]	; (a20 <_sercom_get_async_baud_val+0x8c>)
-     9bc:	47a0      	blx	r4
-     9be:	0001      	movs	r1, r0
-		ratio = long_division(temp1, peripheral_clock);
-     9c0:	003a      	movs	r2, r7
-     9c2:	2300      	movs	r3, #0
-     9c4:	2000      	movs	r0, #0
-     9c6:	4c17      	ldr	r4, [pc, #92]	; (a24 <_sercom_get_async_baud_val+0x90>)
-     9c8:	47a0      	blx	r4
-		scale = ((uint64_t)1 << SHIFT) - ratio;
-     9ca:	2200      	movs	r2, #0
-     9cc:	2301      	movs	r3, #1
-     9ce:	1a12      	subs	r2, r2, r0
-     9d0:	418b      	sbcs	r3, r1
-		baud_calculated = (65536 * scale) >> SHIFT;
-     9d2:	0c12      	lsrs	r2, r2, #16
-     9d4:	041b      	lsls	r3, r3, #16
-     9d6:	431a      	orrs	r2, r3
-	*baudval = baud_calculated;
-     9d8:	8032      	strh	r2, [r6, #0]
-	return STATUS_OK;
-     9da:	2200      	movs	r2, #0
-     9dc:	e7e5      	b.n	9aa <_sercom_get_async_baud_val+0x16>
-	uint64_t baud_calculated = 0;
-     9de:	2200      	movs	r2, #0
-	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
-     9e0:	2b01      	cmp	r3, #1
-     9e2:	d1f9      	bne.n	9d8 <_sercom_get_async_baud_val+0x44>
-		temp1 = ((uint64_t)baudrate * sample_num);
-     9e4:	000a      	movs	r2, r1
-     9e6:	2300      	movs	r3, #0
-     9e8:	2100      	movs	r1, #0
-     9ea:	4c0d      	ldr	r4, [pc, #52]	; (a20 <_sercom_get_async_baud_val+0x8c>)
-     9ec:	47a0      	blx	r4
-     9ee:	0002      	movs	r2, r0
-     9f0:	000b      	movs	r3, r1
-     9f2:	9200      	str	r2, [sp, #0]
-     9f4:	9301      	str	r3, [sp, #4]
-		baud_int = long_division( peripheral_clock, temp1);
-     9f6:	0038      	movs	r0, r7
-     9f8:	2100      	movs	r1, #0
-     9fa:	4c0a      	ldr	r4, [pc, #40]	; (a24 <_sercom_get_async_baud_val+0x90>)
-     9fc:	47a0      	blx	r4
-     9fe:	0005      	movs	r5, r0
-		if(baud_int > BAUD_INT_MAX) {
-     a00:	2380      	movs	r3, #128	; 0x80
-     a02:	019b      	lsls	r3, r3, #6
-				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-     a04:	2240      	movs	r2, #64	; 0x40
-		if(baud_int > BAUD_INT_MAX) {
-     a06:	4298      	cmp	r0, r3
-     a08:	d8cf      	bhi.n	9aa <_sercom_get_async_baud_val+0x16>
-		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
-     a0a:	0f79      	lsrs	r1, r7, #29
-     a0c:	00f8      	lsls	r0, r7, #3
-     a0e:	9a00      	ldr	r2, [sp, #0]
-     a10:	9b01      	ldr	r3, [sp, #4]
-     a12:	47a0      	blx	r4
-		baud_fp = temp1 - 8 * baud_int;
-     a14:	00ea      	lsls	r2, r5, #3
-     a16:	1a82      	subs	r2, r0, r2
-		baud_calculated = baud_int | (baud_fp << 13);
-     a18:	b2d2      	uxtb	r2, r2
-     a1a:	0352      	lsls	r2, r2, #13
-     a1c:	432a      	orrs	r2, r5
-     a1e:	e7db      	b.n	9d8 <_sercom_get_async_baud_val+0x44>
-     a20:	00001f0d 	.word	0x00001f0d
-     a24:	000008b3 	.word	0x000008b3
-
-00000a28 <sercom_set_gclk_generator>:
- *                                         forced.
- */
-enum status_code sercom_set_gclk_generator(
-		const enum gclk_generator generator_source,
-		const bool force_change)
-{
-     a28:	b510      	push	{r4, lr}
-     a2a:	b082      	sub	sp, #8
-     a2c:	0004      	movs	r4, r0
-	/* Check if valid option */
-	if (!_sercom_config.generator_is_set || force_change) {
-     a2e:	4b0e      	ldr	r3, [pc, #56]	; (a68 <sercom_set_gclk_generator+0x40>)
-     a30:	781b      	ldrb	r3, [r3, #0]
-     a32:	2b00      	cmp	r3, #0
-     a34:	d007      	beq.n	a46 <sercom_set_gclk_generator+0x1e>
-     a36:	2900      	cmp	r1, #0
-     a38:	d105      	bne.n	a46 <sercom_set_gclk_generator+0x1e>
-		/* Save config */
-		_sercom_config.generator_source = generator_source;
-		_sercom_config.generator_is_set = true;
-
-		return STATUS_OK;
-	} else if (generator_source == _sercom_config.generator_source) {
-     a3a:	4b0b      	ldr	r3, [pc, #44]	; (a68 <sercom_set_gclk_generator+0x40>)
-     a3c:	785b      	ldrb	r3, [r3, #1]
-     a3e:	4283      	cmp	r3, r0
-     a40:	d010      	beq.n	a64 <sercom_set_gclk_generator+0x3c>
-		/* Return status OK if same config */
-		return STATUS_OK;
-	}
-
-	/* Return invalid config to already initialized GCLK */
-	return STATUS_ERR_ALREADY_INITIALIZED;
-     a42:	201d      	movs	r0, #29
-     a44:	e00c      	b.n	a60 <sercom_set_gclk_generator+0x38>
-		gclk_chan_conf.source_generator = generator_source;
-     a46:	a901      	add	r1, sp, #4
-     a48:	700c      	strb	r4, [r1, #0]
-		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
-     a4a:	2013      	movs	r0, #19
-     a4c:	4b07      	ldr	r3, [pc, #28]	; (a6c <sercom_set_gclk_generator+0x44>)
-     a4e:	4798      	blx	r3
-		system_gclk_chan_enable(SERCOM_GCLK_ID);
-     a50:	2013      	movs	r0, #19
-     a52:	4b07      	ldr	r3, [pc, #28]	; (a70 <sercom_set_gclk_generator+0x48>)
-     a54:	4798      	blx	r3
-		_sercom_config.generator_source = generator_source;
-     a56:	4b04      	ldr	r3, [pc, #16]	; (a68 <sercom_set_gclk_generator+0x40>)
-     a58:	705c      	strb	r4, [r3, #1]
-		_sercom_config.generator_is_set = true;
-     a5a:	2201      	movs	r2, #1
-     a5c:	701a      	strb	r2, [r3, #0]
-		return STATUS_OK;
-     a5e:	2000      	movs	r0, #0
-}
-     a60:	b002      	add	sp, #8
-     a62:	bd10      	pop	{r4, pc}
-		return STATUS_OK;
-     a64:	2000      	movs	r0, #0
-     a66:	e7fb      	b.n	a60 <sercom_set_gclk_generator+0x38>
-     a68:	20000108 	.word	0x20000108
-     a6c:	00001af5 	.word	0x00001af5
-     a70:	00001a69 	.word	0x00001a69
-
-00000a74 <_sercom_get_default_pad>:
- */
-uint32_t _sercom_get_default_pad(
-		Sercom *const sercom_module,
-		const uint8_t pad)
-{
-	switch ((uintptr_t)sercom_module) {
-     a74:	4b40      	ldr	r3, [pc, #256]	; (b78 <_sercom_get_default_pad+0x104>)
-     a76:	4298      	cmp	r0, r3
-     a78:	d031      	beq.n	ade <_sercom_get_default_pad+0x6a>
-     a7a:	d90a      	bls.n	a92 <_sercom_get_default_pad+0x1e>
-     a7c:	4b3f      	ldr	r3, [pc, #252]	; (b7c <_sercom_get_default_pad+0x108>)
-     a7e:	4298      	cmp	r0, r3
-     a80:	d04d      	beq.n	b1e <_sercom_get_default_pad+0xaa>
-     a82:	4b3f      	ldr	r3, [pc, #252]	; (b80 <_sercom_get_default_pad+0x10c>)
-     a84:	4298      	cmp	r0, r3
-     a86:	d05a      	beq.n	b3e <_sercom_get_default_pad+0xca>
-     a88:	4b3e      	ldr	r3, [pc, #248]	; (b84 <_sercom_get_default_pad+0x110>)
-     a8a:	4298      	cmp	r0, r3
-     a8c:	d037      	beq.n	afe <_sercom_get_default_pad+0x8a>
-		/* Auto-generate a lookup table for the default SERCOM pad defaults */
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-	}
-
-	Assert(false);
-	return 0;
-     a8e:	2000      	movs	r0, #0
-}
-     a90:	4770      	bx	lr
-	switch ((uintptr_t)sercom_module) {
-     a92:	4b3d      	ldr	r3, [pc, #244]	; (b88 <_sercom_get_default_pad+0x114>)
-     a94:	4298      	cmp	r0, r3
-     a96:	d00c      	beq.n	ab2 <_sercom_get_default_pad+0x3e>
-     a98:	4b3c      	ldr	r3, [pc, #240]	; (b8c <_sercom_get_default_pad+0x118>)
-     a9a:	4298      	cmp	r0, r3
-     a9c:	d1f7      	bne.n	a8e <_sercom_get_default_pad+0x1a>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     a9e:	2901      	cmp	r1, #1
-     aa0:	d017      	beq.n	ad2 <_sercom_get_default_pad+0x5e>
-     aa2:	2900      	cmp	r1, #0
-     aa4:	d05d      	beq.n	b62 <_sercom_get_default_pad+0xee>
-     aa6:	2902      	cmp	r1, #2
-     aa8:	d015      	beq.n	ad6 <_sercom_get_default_pad+0x62>
-     aaa:	2903      	cmp	r1, #3
-     aac:	d015      	beq.n	ada <_sercom_get_default_pad+0x66>
-	return 0;
-     aae:	2000      	movs	r0, #0
-     ab0:	e7ee      	b.n	a90 <_sercom_get_default_pad+0x1c>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     ab2:	2901      	cmp	r1, #1
-     ab4:	d007      	beq.n	ac6 <_sercom_get_default_pad+0x52>
-     ab6:	2900      	cmp	r1, #0
-     ab8:	d051      	beq.n	b5e <_sercom_get_default_pad+0xea>
-     aba:	2902      	cmp	r1, #2
-     abc:	d005      	beq.n	aca <_sercom_get_default_pad+0x56>
-     abe:	2903      	cmp	r1, #3
-     ac0:	d005      	beq.n	ace <_sercom_get_default_pad+0x5a>
-	return 0;
-     ac2:	2000      	movs	r0, #0
-     ac4:	e7e4      	b.n	a90 <_sercom_get_default_pad+0x1c>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     ac6:	4832      	ldr	r0, [pc, #200]	; (b90 <_sercom_get_default_pad+0x11c>)
-     ac8:	e7e2      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     aca:	4832      	ldr	r0, [pc, #200]	; (b94 <_sercom_get_default_pad+0x120>)
-     acc:	e7e0      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     ace:	4832      	ldr	r0, [pc, #200]	; (b98 <_sercom_get_default_pad+0x124>)
-     ad0:	e7de      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     ad2:	4832      	ldr	r0, [pc, #200]	; (b9c <_sercom_get_default_pad+0x128>)
-     ad4:	e7dc      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     ad6:	4832      	ldr	r0, [pc, #200]	; (ba0 <_sercom_get_default_pad+0x12c>)
-     ad8:	e7da      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     ada:	4832      	ldr	r0, [pc, #200]	; (ba4 <_sercom_get_default_pad+0x130>)
-     adc:	e7d8      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     ade:	2901      	cmp	r1, #1
-     ae0:	d007      	beq.n	af2 <_sercom_get_default_pad+0x7e>
-     ae2:	2900      	cmp	r1, #0
-     ae4:	d03f      	beq.n	b66 <_sercom_get_default_pad+0xf2>
-     ae6:	2902      	cmp	r1, #2
-     ae8:	d005      	beq.n	af6 <_sercom_get_default_pad+0x82>
-     aea:	2903      	cmp	r1, #3
-     aec:	d005      	beq.n	afa <_sercom_get_default_pad+0x86>
-	return 0;
-     aee:	2000      	movs	r0, #0
-     af0:	e7ce      	b.n	a90 <_sercom_get_default_pad+0x1c>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     af2:	482d      	ldr	r0, [pc, #180]	; (ba8 <_sercom_get_default_pad+0x134>)
-     af4:	e7cc      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     af6:	482d      	ldr	r0, [pc, #180]	; (bac <_sercom_get_default_pad+0x138>)
-     af8:	e7ca      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     afa:	482d      	ldr	r0, [pc, #180]	; (bb0 <_sercom_get_default_pad+0x13c>)
-     afc:	e7c8      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     afe:	2901      	cmp	r1, #1
-     b00:	d007      	beq.n	b12 <_sercom_get_default_pad+0x9e>
-     b02:	2900      	cmp	r1, #0
-     b04:	d031      	beq.n	b6a <_sercom_get_default_pad+0xf6>
-     b06:	2902      	cmp	r1, #2
-     b08:	d005      	beq.n	b16 <_sercom_get_default_pad+0xa2>
-     b0a:	2903      	cmp	r1, #3
-     b0c:	d005      	beq.n	b1a <_sercom_get_default_pad+0xa6>
-	return 0;
-     b0e:	2000      	movs	r0, #0
-     b10:	e7be      	b.n	a90 <_sercom_get_default_pad+0x1c>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     b12:	4828      	ldr	r0, [pc, #160]	; (bb4 <_sercom_get_default_pad+0x140>)
-     b14:	e7bc      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b16:	4828      	ldr	r0, [pc, #160]	; (bb8 <_sercom_get_default_pad+0x144>)
-     b18:	e7ba      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b1a:	4828      	ldr	r0, [pc, #160]	; (bbc <_sercom_get_default_pad+0x148>)
-     b1c:	e7b8      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b1e:	2901      	cmp	r1, #1
-     b20:	d007      	beq.n	b32 <_sercom_get_default_pad+0xbe>
-     b22:	2900      	cmp	r1, #0
-     b24:	d023      	beq.n	b6e <_sercom_get_default_pad+0xfa>
-     b26:	2902      	cmp	r1, #2
-     b28:	d005      	beq.n	b36 <_sercom_get_default_pad+0xc2>
-     b2a:	2903      	cmp	r1, #3
-     b2c:	d005      	beq.n	b3a <_sercom_get_default_pad+0xc6>
-	return 0;
-     b2e:	2000      	movs	r0, #0
-     b30:	e7ae      	b.n	a90 <_sercom_get_default_pad+0x1c>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     b32:	4823      	ldr	r0, [pc, #140]	; (bc0 <_sercom_get_default_pad+0x14c>)
-     b34:	e7ac      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b36:	4823      	ldr	r0, [pc, #140]	; (bc4 <_sercom_get_default_pad+0x150>)
-     b38:	e7aa      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b3a:	4823      	ldr	r0, [pc, #140]	; (bc8 <_sercom_get_default_pad+0x154>)
-     b3c:	e7a8      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b3e:	2901      	cmp	r1, #1
-     b40:	d007      	beq.n	b52 <_sercom_get_default_pad+0xde>
-     b42:	2900      	cmp	r1, #0
-     b44:	d015      	beq.n	b72 <_sercom_get_default_pad+0xfe>
-     b46:	2902      	cmp	r1, #2
-     b48:	d005      	beq.n	b56 <_sercom_get_default_pad+0xe2>
-     b4a:	2903      	cmp	r1, #3
-     b4c:	d005      	beq.n	b5a <_sercom_get_default_pad+0xe6>
-	return 0;
-     b4e:	2000      	movs	r0, #0
-     b50:	e79e      	b.n	a90 <_sercom_get_default_pad+0x1c>
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-     b52:	481e      	ldr	r0, [pc, #120]	; (bcc <_sercom_get_default_pad+0x158>)
-     b54:	e79c      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b56:	481e      	ldr	r0, [pc, #120]	; (bd0 <_sercom_get_default_pad+0x15c>)
-     b58:	e79a      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b5a:	481e      	ldr	r0, [pc, #120]	; (bd4 <_sercom_get_default_pad+0x160>)
-     b5c:	e798      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b5e:	481e      	ldr	r0, [pc, #120]	; (bd8 <_sercom_get_default_pad+0x164>)
-     b60:	e796      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b62:	2003      	movs	r0, #3
-     b64:	e794      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b66:	481d      	ldr	r0, [pc, #116]	; (bdc <_sercom_get_default_pad+0x168>)
-     b68:	e792      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b6a:	481d      	ldr	r0, [pc, #116]	; (be0 <_sercom_get_default_pad+0x16c>)
-     b6c:	e790      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b6e:	481d      	ldr	r0, [pc, #116]	; (be4 <_sercom_get_default_pad+0x170>)
-     b70:	e78e      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b72:	481d      	ldr	r0, [pc, #116]	; (be8 <_sercom_get_default_pad+0x174>)
-     b74:	e78c      	b.n	a90 <_sercom_get_default_pad+0x1c>
-     b76:	46c0      	nop			; (mov r8, r8)
-     b78:	42001000 	.word	0x42001000
-     b7c:	42001800 	.word	0x42001800
-     b80:	42001c00 	.word	0x42001c00
-     b84:	42001400 	.word	0x42001400
-     b88:	42000800 	.word	0x42000800
-     b8c:	42000c00 	.word	0x42000c00
-     b90:	00050003 	.word	0x00050003
-     b94:	00060003 	.word	0x00060003
-     b98:	00070003 	.word	0x00070003
-     b9c:	00010003 	.word	0x00010003
-     ba0:	001e0003 	.word	0x001e0003
-     ba4:	001f0003 	.word	0x001f0003
-     ba8:	00090003 	.word	0x00090003
-     bac:	000a0003 	.word	0x000a0003
-     bb0:	000b0003 	.word	0x000b0003
-     bb4:	00110003 	.word	0x00110003
-     bb8:	00120003 	.word	0x00120003
-     bbc:	00130003 	.word	0x00130003
-     bc0:	000d0003 	.word	0x000d0003
-     bc4:	000e0003 	.word	0x000e0003
-     bc8:	000f0003 	.word	0x000f0003
-     bcc:	00170003 	.word	0x00170003
-     bd0:	00180003 	.word	0x00180003
-     bd4:	00190003 	.word	0x00190003
-     bd8:	00040003 	.word	0x00040003
-     bdc:	00080003 	.word	0x00080003
-     be0:	00100003 	.word	0x00100003
-     be4:	000c0003 	.word	0x000c0003
-     be8:	00160003 	.word	0x00160003
-
-00000bec <_sercom_get_sercom_inst_index>:
- *
- * \return Index of given instance.
- */
-uint8_t _sercom_get_sercom_inst_index(
-		Sercom *const sercom_instance)
-{
-     bec:	b530      	push	{r4, r5, lr}
-     bee:	b087      	sub	sp, #28
-	/* Save all available SERCOM instances for compare */
-	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
-     bf0:	4b0b      	ldr	r3, [pc, #44]	; (c20 <_sercom_get_sercom_inst_index+0x34>)
-     bf2:	466a      	mov	r2, sp
-     bf4:	cb32      	ldmia	r3!, {r1, r4, r5}
-     bf6:	c232      	stmia	r2!, {r1, r4, r5}
-     bf8:	cb32      	ldmia	r3!, {r1, r4, r5}
-     bfa:	c232      	stmia	r2!, {r1, r4, r5}
-
-	/* Find index for sercom instance */
-	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
-     bfc:	9b00      	ldr	r3, [sp, #0]
-     bfe:	4283      	cmp	r3, r0
-     c00:	d00b      	beq.n	c1a <_sercom_get_sercom_inst_index+0x2e>
-     c02:	2301      	movs	r3, #1
-     c04:	009a      	lsls	r2, r3, #2
-     c06:	4669      	mov	r1, sp
-     c08:	5852      	ldr	r2, [r2, r1]
-     c0a:	4282      	cmp	r2, r0
-     c0c:	d006      	beq.n	c1c <_sercom_get_sercom_inst_index+0x30>
-	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-     c0e:	3301      	adds	r3, #1
-     c10:	2b06      	cmp	r3, #6
-     c12:	d1f7      	bne.n	c04 <_sercom_get_sercom_inst_index+0x18>
-		}
-	}
-
-	/* Invalid data given */
-	Assert(false);
-	return 0;
-     c14:	2000      	movs	r0, #0
-}
-     c16:	b007      	add	sp, #28
-     c18:	bd30      	pop	{r4, r5, pc}
-	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-     c1a:	2300      	movs	r3, #0
-			return i;
-     c1c:	b2d8      	uxtb	r0, r3
-     c1e:	e7fa      	b.n	c16 <_sercom_get_sercom_inst_index+0x2a>
-     c20:	000037f4 	.word	0x000037f4
-
-00000c24 <_read>:
-int __attribute__((weak))
-_read (int file, char * ptr, int len); // Remove GCC compiler warning
-
-int __attribute__((weak))
-_read (int file, char * ptr, int len)
-{
-     c24:	b5f0      	push	{r4, r5, r6, r7, lr}
-     c26:	46c6      	mov	lr, r8
-     c28:	b500      	push	{lr}
-     c2a:	000c      	movs	r4, r1
-     c2c:	4690      	mov	r8, r2
-	int nChars = 0;
-
-	if (file != 0) {
-     c2e:	2800      	cmp	r0, #0
-     c30:	d10f      	bne.n	c52 <_read+0x2e>
-		return -1;
-	}
-
-	for (; len > 0; --len) {
-     c32:	2a00      	cmp	r2, #0
-     c34:	dd11      	ble.n	c5a <_read+0x36>
-     c36:	188f      	adds	r7, r1, r2
-		ptr_get(stdio_base, ptr);
-     c38:	4e09      	ldr	r6, [pc, #36]	; (c60 <_read+0x3c>)
-     c3a:	4d0a      	ldr	r5, [pc, #40]	; (c64 <_read+0x40>)
-     c3c:	6830      	ldr	r0, [r6, #0]
-     c3e:	0021      	movs	r1, r4
-     c40:	682b      	ldr	r3, [r5, #0]
-     c42:	4798      	blx	r3
-		ptr++;
-     c44:	3401      	adds	r4, #1
-	for (; len > 0; --len) {
-     c46:	42bc      	cmp	r4, r7
-     c48:	d1f8      	bne.n	c3c <_read+0x18>
-		nChars++;
-	}
-	return nChars;
-}
-     c4a:	4640      	mov	r0, r8
-     c4c:	bc04      	pop	{r2}
-     c4e:	4690      	mov	r8, r2
-     c50:	bdf0      	pop	{r4, r5, r6, r7, pc}
-		return -1;
-     c52:	2301      	movs	r3, #1
-     c54:	425b      	negs	r3, r3
-     c56:	4698      	mov	r8, r3
-     c58:	e7f7      	b.n	c4a <_read+0x26>
-	for (; len > 0; --len) {
-     c5a:	4680      	mov	r8, r0
-     c5c:	e7f5      	b.n	c4a <_read+0x26>
-     c5e:	46c0      	nop			; (mov r8, r8)
-     c60:	20000238 	.word	0x20000238
-     c64:	20000230 	.word	0x20000230
-
-00000c68 <_write>:
-int __attribute__((weak))
-_write (int file, char * ptr, int len);
-
-int __attribute__((weak))
-_write (int file, char * ptr, int len)
-{
-     c68:	b5f0      	push	{r4, r5, r6, r7, lr}
-     c6a:	46c6      	mov	lr, r8
-     c6c:	b500      	push	{lr}
-     c6e:	000e      	movs	r6, r1
-     c70:	0015      	movs	r5, r2
-	int nChars = 0;
-
-	if ((file != 1) && (file != 2) && (file!=3)) {
-     c72:	3801      	subs	r0, #1
-     c74:	2802      	cmp	r0, #2
-     c76:	d810      	bhi.n	c9a <_write+0x32>
-		return -1;
-	}
-
-	for (; len != 0; --len) {
-     c78:	2a00      	cmp	r2, #0
-     c7a:	d011      	beq.n	ca0 <_write+0x38>
-     c7c:	2400      	movs	r4, #0
-		if (ptr_put(stdio_base, *ptr++) < 0) {
-     c7e:	4b0c      	ldr	r3, [pc, #48]	; (cb0 <_write+0x48>)
-     c80:	4698      	mov	r8, r3
-     c82:	4f0c      	ldr	r7, [pc, #48]	; (cb4 <_write+0x4c>)
-     c84:	4643      	mov	r3, r8
-     c86:	6818      	ldr	r0, [r3, #0]
-     c88:	5d31      	ldrb	r1, [r6, r4]
-     c8a:	683b      	ldr	r3, [r7, #0]
-     c8c:	4798      	blx	r3
-     c8e:	2800      	cmp	r0, #0
-     c90:	db08      	blt.n	ca4 <_write+0x3c>
-			return -1;
-		}
-		++nChars;
-     c92:	3401      	adds	r4, #1
-	for (; len != 0; --len) {
-     c94:	42a5      	cmp	r5, r4
-     c96:	d1f5      	bne.n	c84 <_write+0x1c>
-     c98:	e006      	b.n	ca8 <_write+0x40>
-		return -1;
-     c9a:	2401      	movs	r4, #1
-     c9c:	4264      	negs	r4, r4
-     c9e:	e003      	b.n	ca8 <_write+0x40>
-	for (; len != 0; --len) {
-     ca0:	0014      	movs	r4, r2
-     ca2:	e001      	b.n	ca8 <_write+0x40>
-			return -1;
-     ca4:	2401      	movs	r4, #1
-     ca6:	4264      	negs	r4, r4
-	}
-	return nChars;
-}
-     ca8:	0020      	movs	r0, r4
-     caa:	bc04      	pop	{r2}
-     cac:	4690      	mov	r8, r2
-     cae:	bdf0      	pop	{r4, r5, r6, r7, pc}
-     cb0:	20000238 	.word	0x20000238
-     cb4:	20000234 	.word	0x20000234
-
-00000cb8 <padc_init>:
-
-COMPILER_ALIGNED(16)
-DmacDescriptor adc_descriptor SECTION_DMAC_DESCRIPTOR;
-
-void padc_init(void)
-{
-     cb8:	b530      	push	{r4, r5, lr}
-     cba:	b095      	sub	sp, #84	; 0x54
-	// configure adc
-	struct adc_config adc_conf;
-	adc_get_config_defaults(&adc_conf);
-     cbc:	ac08      	add	r4, sp, #32
-     cbe:	0020      	movs	r0, r4
-     cc0:	4b2a      	ldr	r3, [pc, #168]	; (d6c <padc_init+0xb4>)
-     cc2:	4798      	blx	r3
-	adc_conf.gain_factor = P_ADC_GAIN_FACTOR;
-     cc4:	2300      	movs	r3, #0
-     cc6:	60a3      	str	r3, [r4, #8]
-	adc_conf.resolution = P_ADC_RESOLUTION;
-     cc8:	7123      	strb	r3, [r4, #4]
-	adc_conf.clock_prescaler = P_ADC_CLOCK_PRESCALAR;
-     cca:	2280      	movs	r2, #128	; 0x80
-     ccc:	0092      	lsls	r2, r2, #2
-     cce:	8062      	strh	r2, [r4, #2]
-	adc_conf.reference = P_ADC_VREF;
-     cd0:	2201      	movs	r2, #1
-     cd2:	7062      	strb	r2, [r4, #1]
-	adc_conf.positive_input = P_ADC_POSITIVE_INPUT_PIN;
-     cd4:	2104      	movs	r1, #4
-     cd6:	7321      	strb	r1, [r4, #12]
-	adc_conf.negative_input = P_ADC_NEGATIVE_INPUT_PIN;
-     cd8:	21c0      	movs	r1, #192	; 0xc0
-     cda:	0149      	lsls	r1, r1, #5
-     cdc:	81e1      	strh	r1, [r4, #14]
-	adc_conf.freerunning = true;
-     cde:	7522      	strb	r2, [r4, #20]
-	adc_conf.left_adjust = false;
-     ce0:	74a3      	strb	r3, [r4, #18]
-	
-	adc_init(&adc_mod, ADC, &adc_conf);
-     ce2:	4d23      	ldr	r5, [pc, #140]	; (d70 <padc_init+0xb8>)
-     ce4:	0022      	movs	r2, r4
-     ce6:	4923      	ldr	r1, [pc, #140]	; (d74 <padc_init+0xbc>)
-     ce8:	0028      	movs	r0, r5
-     cea:	4b23      	ldr	r3, [pc, #140]	; (d78 <padc_init+0xc0>)
-     cec:	4798      	blx	r3
-		struct adc_module *const module_inst)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-     cee:	682a      	ldr	r2, [r5, #0]
-     cf0:	7e53      	ldrb	r3, [r2, #25]
-
-	while (adc_is_syncing(module_inst)) {
-     cf2:	b25b      	sxtb	r3, r3
-     cf4:	2b00      	cmp	r3, #0
-     cf6:	dbfb      	blt.n	cf0 <padc_init+0x38>
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
-#   endif
-#endif
-
-	/* Disbale interrupt */
-	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
-     cf8:	230f      	movs	r3, #15
-     cfa:	7593      	strb	r3, [r2, #22]
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
-     cfc:	7613      	strb	r3, [r2, #24]
-
-	adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
-     cfe:	7813      	ldrb	r3, [r2, #0]
-     d00:	2102      	movs	r1, #2
-     d02:	430b      	orrs	r3, r1
-     d04:	7013      	strb	r3, [r2, #0]
-	Adc *const adc_module = module_inst->hw;
-     d06:	4b1a      	ldr	r3, [pc, #104]	; (d70 <padc_init+0xb8>)
-     d08:	681a      	ldr	r2, [r3, #0]
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-     d0a:	7e53      	ldrb	r3, [r2, #25]
-
-	while (adc_is_syncing(module_inst)) {
-     d0c:	b25b      	sxtb	r3, r3
-     d0e:	2b00      	cmp	r3, #0
-     d10:	dbfb      	blt.n	d0a <padc_init+0x52>
-	adc_enable(&adc_mod);
-	
-	// configure dma resource
-	struct dma_resource_config dma_resource_conf;
-	dma_get_config_defaults(&dma_resource_conf);
-     d12:	ac06      	add	r4, sp, #24
-     d14:	0020      	movs	r0, r4
-     d16:	4b19      	ldr	r3, [pc, #100]	; (d7c <padc_init+0xc4>)
-     d18:	4798      	blx	r3
-	dma_resource_conf.peripheral_trigger = ADC_DMAC_ID_RESRDY;
-     d1a:	2327      	movs	r3, #39	; 0x27
-     d1c:	7063      	strb	r3, [r4, #1]
-	dma_resource_conf.trigger_action = DMA_TRIGGER_ACTION_BEAT;
-     d1e:	3b25      	subs	r3, #37	; 0x25
-     d20:	70a3      	strb	r3, [r4, #2]
-	// allocate dma resource
-	dma_allocate(&adc_resource, &dma_resource_conf);
-     d22:	4d17      	ldr	r5, [pc, #92]	; (d80 <padc_init+0xc8>)
-     d24:	0021      	movs	r1, r4
-     d26:	0028      	movs	r0, r5
-     d28:	4b16      	ldr	r3, [pc, #88]	; (d84 <padc_init+0xcc>)
-     d2a:	4798      	blx	r3
-static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
-{
-	Assert(config);
-
-	/* Set descriptor as valid */
-	config->descriptor_valid = true;
-     d2c:	2201      	movs	r2, #1
-     d2e:	466b      	mov	r3, sp
-     d30:	701a      	strb	r2, [r3, #0]
-	/* Disable event output */
-	config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
-     d32:	2300      	movs	r3, #0
-     d34:	4669      	mov	r1, sp
-     d36:	704b      	strb	r3, [r1, #1]
-	/* No block action */
-	config->block_action = DMA_BLOCK_ACTION_NOACT;
-     d38:	708b      	strb	r3, [r1, #2]
-	/* Set beat size to one byte */
-	config->beat_size = DMA_BEAT_SIZE_BYTE;
-	/* Enable source increment */
-	config->src_increment_enable = true;
-	/* Enable destination increment */
-	config->dst_increment_enable = true;
-     d3a:	714a      	strb	r2, [r1, #5]
-	/* Step size is applied to the destination address */
-	config->step_selection = DMA_STEPSEL_DST;
-     d3c:	718b      	strb	r3, [r1, #6]
-	/* Address increment is beat size multiplied by 1*/
-	config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
-     d3e:	71cb      	strb	r3, [r1, #7]
-	// setup transfer descriptor
-	struct dma_descriptor_config dma_desc_conf;
-	dma_descriptor_get_config_defaults(&dma_desc_conf);
-	dma_desc_conf.beat_size = DMA_BEAT_SIZE_HWORD;	// 16 bit
-     d40:	70ca      	strb	r2, [r1, #3]
-	dma_desc_conf.dst_increment_enable = true;
-	dma_desc_conf.src_increment_enable = false;
-     d42:	710b      	strb	r3, [r1, #4]
-	dma_desc_conf.block_transfer_count = sizeof(raw_adc_values) / 2;
-     d44:	3310      	adds	r3, #16
-     d46:	810b      	strh	r3, [r1, #8]
-	dma_desc_conf.source_address = (uint32_t)(&adc_mod.hw->RESULT.reg);
-     d48:	4b09      	ldr	r3, [pc, #36]	; (d70 <padc_init+0xb8>)
-     d4a:	681b      	ldr	r3, [r3, #0]
-     d4c:	331a      	adds	r3, #26
-     d4e:	9303      	str	r3, [sp, #12]
-	dma_desc_conf.destination_address = (uint32_t)(raw_adc_values + (sizeof(raw_adc_values) / 2));
-     d50:	4b0d      	ldr	r3, [pc, #52]	; (d88 <padc_init+0xd0>)
-     d52:	3320      	adds	r3, #32
-     d54:	9304      	str	r3, [sp, #16]
-	dma_desc_conf.next_descriptor_address = (uint32_t)&adc_descriptor;
-     d56:	4c0d      	ldr	r4, [pc, #52]	; (d8c <padc_init+0xd4>)
-     d58:	9405      	str	r4, [sp, #20]
-	dma_descriptor_create(&adc_descriptor, &dma_desc_conf);
-     d5a:	0020      	movs	r0, r4
-     d5c:	4b0c      	ldr	r3, [pc, #48]	; (d90 <padc_init+0xd8>)
-     d5e:	4798      	blx	r3
-	dma_add_descriptor(&adc_resource, &adc_descriptor);
-     d60:	0021      	movs	r1, r4
-     d62:	0028      	movs	r0, r5
-     d64:	4b0b      	ldr	r3, [pc, #44]	; (d94 <padc_init+0xdc>)
-     d66:	4798      	blx	r3
-}
-     d68:	b015      	add	sp, #84	; 0x54
-     d6a:	bd30      	pop	{r4, r5, pc}
-     d6c:	00000115 	.word	0x00000115
-     d70:	2000010c 	.word	0x2000010c
-     d74:	42004000 	.word	0x42004000
-     d78:	0000015d 	.word	0x0000015d
-     d7c:	00000601 	.word	0x00000601
-     d80:	20000114 	.word	0x20000114
-     d84:	00000611 	.word	0x00000611
-     d88:	20000130 	.word	0x20000130
-     d8c:	20000240 	.word	0x20000240
-     d90:	000007e1 	.word	0x000007e1
-     d94:	00000889 	.word	0x00000889
-
-00000d98 <padc_start>:
-
-void padc_start(void)
-{
-     d98:	b510      	push	{r4, lr}
-		struct adc_module *const module_inst)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-     d9a:	4b09      	ldr	r3, [pc, #36]	; (dc0 <padc_start+0x28>)
-     d9c:	681a      	ldr	r2, [r3, #0]
-     d9e:	7e53      	ldrb	r3, [r2, #25]
-
-	while (adc_is_syncing(module_inst)) {
-     da0:	b25b      	sxtb	r3, r3
-     da2:	2b00      	cmp	r3, #0
-     da4:	dbfb      	blt.n	d9e <padc_start+0x6>
-		/* Wait for synchronization */
-	}
-
-	adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
-     da6:	7b13      	ldrb	r3, [r2, #12]
-     da8:	2102      	movs	r1, #2
-     daa:	430b      	orrs	r3, r1
-     dac:	7313      	strb	r3, [r2, #12]
-     dae:	7e53      	ldrb	r3, [r2, #25]
-
-	while (adc_is_syncing(module_inst)) {
-     db0:	b25b      	sxtb	r3, r3
-     db2:	2b00      	cmp	r3, #0
-     db4:	dbfb      	blt.n	dae <padc_start+0x16>
-	adc_start_conversion(&adc_mod);
-	dma_start_transfer_job(&adc_resource);
-     db6:	4803      	ldr	r0, [pc, #12]	; (dc4 <padc_start+0x2c>)
-     db8:	4b03      	ldr	r3, [pc, #12]	; (dc8 <padc_start+0x30>)
-     dba:	4798      	blx	r3
-}
-     dbc:	bd10      	pop	{r4, pc}
-     dbe:	46c0      	nop			; (mov r8, r8)
-     dc0:	2000010c 	.word	0x2000010c
-     dc4:	20000114 	.word	0x20000114
-     dc8:	00000759 	.word	0x00000759
-
-00000dcc <padc_get_raw>:
-	uint16_t raw = padc_get_raw();
-	return (float)((float)raw / 4096.0f * P_ADC_VREF_VAL);
-}
-
-uint16_t padc_get_raw(void)
-{
-     dcc:	4b05      	ldr	r3, [pc, #20]	; (de4 <padc_get_raw+0x18>)
-     dce:	0019      	movs	r1, r3
-     dd0:	3120      	adds	r1, #32
-	uint32_t sum = 0;
-     dd2:	2000      	movs	r0, #0
-	for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
-	{
-		sum += (uint32_t)raw_adc_values[ind];
-     dd4:	881a      	ldrh	r2, [r3, #0]
-     dd6:	1880      	adds	r0, r0, r2
-     dd8:	3302      	adds	r3, #2
-	for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
-     dda:	428b      	cmp	r3, r1
-     ddc:	d1fa      	bne.n	dd4 <padc_get_raw+0x8>
-	}
-	sum /= P_ADC_OVERSAMPLE_RATE;
-     dde:	0900      	lsrs	r0, r0, #4
-	return (uint16_t)sum;
-     de0:	b280      	uxth	r0, r0
-     de2:	4770      	bx	lr
-     de4:	20000130 	.word	0x20000130
-
-00000de8 <padc_get_voltage>:
-{
-     de8:	b510      	push	{r4, lr}
-	uint16_t raw = padc_get_raw();
-     dea:	4b05      	ldr	r3, [pc, #20]	; (e00 <padc_get_voltage+0x18>)
-     dec:	4798      	blx	r3
-	return (float)((float)raw / 4096.0f * P_ADC_VREF_VAL);
-     dee:	4b05      	ldr	r3, [pc, #20]	; (e04 <padc_get_voltage+0x1c>)
-     df0:	4798      	blx	r3
-     df2:	4c05      	ldr	r4, [pc, #20]	; (e08 <padc_get_voltage+0x20>)
-     df4:	21e6      	movs	r1, #230	; 0xe6
-     df6:	0589      	lsls	r1, r1, #22
-     df8:	47a0      	blx	r4
-     dfa:	4904      	ldr	r1, [pc, #16]	; (e0c <padc_get_voltage+0x24>)
-     dfc:	47a0      	blx	r4
-}
-     dfe:	bd10      	pop	{r4, pc}
-     e00:	00000dcd 	.word	0x00000dcd
-     e04:	000025b9 	.word	0x000025b9
-     e08:	00001f61 	.word	0x00001f61
-     e0c:	400eb368 	.word	0x400eb368
-
-00000e10 <usart_serial_getchar>:
- * \param[out]    c       Destination for the read character.
- */
-static inline void usart_serial_getchar(
-		struct usart_module *const module,
-		uint8_t *c)
-{
-     e10:	b570      	push	{r4, r5, r6, lr}
-     e12:	b082      	sub	sp, #8
-     e14:	0005      	movs	r5, r0
-     e16:	000e      	movs	r6, r1
-	uint16_t temp = 0;
-     e18:	2200      	movs	r2, #0
-     e1a:	466b      	mov	r3, sp
-     e1c:	80da      	strh	r2, [r3, #6]
-
-	while(STATUS_OK != usart_read_wait(module, &temp));
-     e1e:	4c06      	ldr	r4, [pc, #24]	; (e38 <usart_serial_getchar+0x28>)
-     e20:	466b      	mov	r3, sp
-     e22:	1d99      	adds	r1, r3, #6
-     e24:	0028      	movs	r0, r5
-     e26:	47a0      	blx	r4
-     e28:	2800      	cmp	r0, #0
-     e2a:	d1f9      	bne.n	e20 <usart_serial_getchar+0x10>
-
-	*c = temp;
-     e2c:	466b      	mov	r3, sp
-     e2e:	3306      	adds	r3, #6
-     e30:	881b      	ldrh	r3, [r3, #0]
-     e32:	7033      	strb	r3, [r6, #0]
-}
-     e34:	b002      	add	sp, #8
-     e36:	bd70      	pop	{r4, r5, r6, pc}
-     e38:	000012a7 	.word	0x000012a7
-
-00000e3c <usart_serial_putchar>:
-{
-     e3c:	b570      	push	{r4, r5, r6, lr}
-     e3e:	0005      	movs	r5, r0
-	while(STATUS_OK !=usart_write_wait(module, c));
-     e40:	b28c      	uxth	r4, r1
-     e42:	4e03      	ldr	r6, [pc, #12]	; (e50 <usart_serial_putchar+0x14>)
-     e44:	0021      	movs	r1, r4
-     e46:	0028      	movs	r0, r5
-     e48:	47b0      	blx	r6
-     e4a:	2800      	cmp	r0, #0
-     e4c:	d1fa      	bne.n	e44 <usart_serial_putchar+0x8>
-}
-     e4e:	bd70      	pop	{r4, r5, r6, pc}
-     e50:	00001281 	.word	0x00001281
-
-00000e54 <pusart_init>:
-#include "pusart.h"
-
-void pusart_init(void)
-{
-     e54:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Set default config in the config struct */
-	config->data_order       = USART_DATAORDER_LSB;
-     e56:	4a2c      	ldr	r2, [pc, #176]	; (f08 <pusart_init+0xb4>)
-     e58:	2380      	movs	r3, #128	; 0x80
-     e5a:	05db      	lsls	r3, r3, #23
-     e5c:	6013      	str	r3, [r2, #0]
-	config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
-     e5e:	2300      	movs	r3, #0
-     e60:	6053      	str	r3, [r2, #4]
-	config->parity           = USART_PARITY_NONE;
-     e62:	21ff      	movs	r1, #255	; 0xff
-     e64:	8111      	strh	r1, [r2, #8]
-	config->stopbits         = USART_STOPBITS_1;
-     e66:	2100      	movs	r1, #0
-     e68:	7293      	strb	r3, [r2, #10]
-	config->character_size   = USART_CHARACTER_SIZE_8BIT;
-     e6a:	72d3      	strb	r3, [r2, #11]
-	config->baudrate         = 9600;
-	config->receiver_enable  = true;
-     e6c:	2401      	movs	r4, #1
-     e6e:	2024      	movs	r0, #36	; 0x24
-     e70:	5414      	strb	r4, [r2, r0]
-	config->transmitter_enable = true;
-     e72:	3001      	adds	r0, #1
-     e74:	5414      	strb	r4, [r2, r0]
-	config->clock_polarity_inverted = false;
-     e76:	3001      	adds	r0, #1
-     e78:	5413      	strb	r3, [r2, r0]
-	config->use_external_clock = false;
-     e7a:	3001      	adds	r0, #1
-     e7c:	5413      	strb	r3, [r2, r0]
-	config->ext_clock_freq   = 0;
-     e7e:	6293      	str	r3, [r2, #40]	; 0x28
-	config->mux_setting      = USART_RX_1_TX_2_XCK_3;
-	config->run_in_standby   = false;
-     e80:	3005      	adds	r0, #5
-     e82:	5413      	strb	r3, [r2, r0]
-	config->generator_source = GCLK_GENERATOR_0;
-     e84:	3001      	adds	r0, #1
-     e86:	5413      	strb	r3, [r2, r0]
-	config->pinmux_pad0      = PINMUX_DEFAULT;
-	config->pinmux_pad1      = PINMUX_DEFAULT;
-	config->pinmux_pad2      = PINMUX_DEFAULT;
-	config->pinmux_pad3      = PINMUX_DEFAULT;
-#ifdef FEATURE_USART_OVER_SAMPLE
-	config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
-     e88:	6153      	str	r3, [r2, #20]
-	config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
-     e8a:	8213      	strh	r3, [r2, #16]
-#endif
-#ifdef FEATURE_USART_LIN_SLAVE
-	config->lin_slave_enable      = false;
-     e8c:	76d3      	strb	r3, [r2, #27]
-	config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
-	config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
-#endif
-
-#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-	config->immediate_buffer_overflow_notification  = false;
-     e8e:	7611      	strb	r1, [r2, #24]
-#endif
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	config->start_frame_detection_enable            = false;
-     e90:	7711      	strb	r1, [r2, #28]
-#endif
-#ifdef FEATURE_USART_IRDA
-	config->encoding_format_enable                  = false;
-     e92:	7651      	strb	r1, [r2, #25]
-	config->receive_pulse_length                    = 19;
-     e94:	2313      	movs	r3, #19
-     e96:	7693      	strb	r3, [r2, #26]
-	config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
-	config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
-	config->iso7816_config.max_iterations           = 7;
-#endif
-#ifdef FEATURE_USART_COLLISION_DECTION
-	config->collision_detection_enable              = false;
-     e98:	7751      	strb	r1, [r2, #29]
-	static struct usart_config uconf;
-	usart_get_config_defaults(&uconf);
-	uconf.pinmux_pad0 = DEBUG_USART_PINMUX_PAD0;
-     e9a:	4b1c      	ldr	r3, [pc, #112]	; (f0c <pusart_init+0xb8>)
-     e9c:	6313      	str	r3, [r2, #48]	; 0x30
-	uconf.pinmux_pad1 = DEBUG_USART_PINMUX_PAD1;
-     e9e:	4b1c      	ldr	r3, [pc, #112]	; (f10 <pusart_init+0xbc>)
-     ea0:	6353      	str	r3, [r2, #52]	; 0x34
-	uconf.pinmux_pad2 = DEBUG_USART_PINMUX_PAD2;
-     ea2:	2301      	movs	r3, #1
-     ea4:	425b      	negs	r3, r3
-     ea6:	6393      	str	r3, [r2, #56]	; 0x38
-	uconf.pinmux_pad3 = DEBUG_USART_PINMUX_PAD3;
-     ea8:	63d3      	str	r3, [r2, #60]	; 0x3c
-	uconf.mux_setting = DEBUG_USART_MUX_SETTING;
-     eaa:	2380      	movs	r3, #128	; 0x80
-     eac:	035b      	lsls	r3, r3, #13
-     eae:	60d3      	str	r3, [r2, #12]
-	uconf.baudrate = DEBUG_USART_BAUDRATE;
-     eb0:	23e1      	movs	r3, #225	; 0xe1
-     eb2:	025b      	lsls	r3, r3, #9
-     eb4:	6213      	str	r3, [r2, #32]
-static inline void stdio_serial_init(
-		struct usart_module *const module,
-		usart_inst_t const hw,
-		const struct usart_config *const config)
-{
-	stdio_base = (void *)module;
-     eb6:	4d17      	ldr	r5, [pc, #92]	; (f14 <pusart_init+0xc0>)
-     eb8:	4b17      	ldr	r3, [pc, #92]	; (f18 <pusart_init+0xc4>)
-     eba:	601d      	str	r5, [r3, #0]
-	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
-     ebc:	4917      	ldr	r1, [pc, #92]	; (f1c <pusart_init+0xc8>)
-     ebe:	4b18      	ldr	r3, [pc, #96]	; (f20 <pusart_init+0xcc>)
-     ec0:	6019      	str	r1, [r3, #0]
-	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
-     ec2:	4918      	ldr	r1, [pc, #96]	; (f24 <pusart_init+0xd0>)
-     ec4:	4b18      	ldr	r3, [pc, #96]	; (f28 <pusart_init+0xd4>)
-     ec6:	6019      	str	r1, [r3, #0]
-	if (usart_init(module, hw, config) == STATUS_OK) {
-     ec8:	4918      	ldr	r1, [pc, #96]	; (f2c <pusart_init+0xd8>)
-     eca:	0028      	movs	r0, r5
-     ecc:	4b18      	ldr	r3, [pc, #96]	; (f30 <pusart_init+0xdc>)
-     ece:	4798      	blx	r3
-
-	usart_serial_init(module, hw, config);
-# if defined(__GNUC__)
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-     ed0:	4f18      	ldr	r7, [pc, #96]	; (f34 <pusart_init+0xe0>)
-     ed2:	683b      	ldr	r3, [r7, #0]
-     ed4:	6898      	ldr	r0, [r3, #8]
-     ed6:	2100      	movs	r1, #0
-     ed8:	4e17      	ldr	r6, [pc, #92]	; (f38 <pusart_init+0xe4>)
-     eda:	47b0      	blx	r6
-	setbuf(stdin, NULL);
-     edc:	683b      	ldr	r3, [r7, #0]
-     ede:	6858      	ldr	r0, [r3, #4]
-     ee0:	2100      	movs	r1, #0
-     ee2:	47b0      	blx	r6
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-     ee4:	682e      	ldr	r6, [r5, #0]
-
-#if USART_CALLBACK_MODE == true
-	/* Enable Global interrupt for module */
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
-     ee6:	0030      	movs	r0, r6
-     ee8:	4b14      	ldr	r3, [pc, #80]	; (f3c <pusart_init+0xe8>)
-     eea:	4798      	blx	r3
-	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
-     eec:	231f      	movs	r3, #31
-     eee:	4018      	ands	r0, r3
-     ef0:	4084      	lsls	r4, r0
-     ef2:	4b13      	ldr	r3, [pc, #76]	; (f40 <pusart_init+0xec>)
-     ef4:	601c      	str	r4, [r3, #0]
-	SercomUsart *const usart_hw = &(module->hw->USART);
-     ef6:	682a      	ldr	r2, [r5, #0]
-	return (usart_hw->SYNCBUSY.reg);
-     ef8:	69d3      	ldr	r3, [r2, #28]
-	while (usart_is_syncing(module)) {
-     efa:	2b00      	cmp	r3, #0
-     efc:	d1fc      	bne.n	ef8 <pusart_init+0xa4>
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Enable USART module */
-	usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
-     efe:	6833      	ldr	r3, [r6, #0]
-     f00:	2202      	movs	r2, #2
-     f02:	4313      	orrs	r3, r2
-     f04:	6033      	str	r3, [r6, #0]
-	stdio_serial_init(&umod, DEBUG_USART_MODULE, &uconf);
-	usart_enable(&umod);
-}
-     f06:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-     f08:	20000150 	.word	0x20000150
-     f0c:	00160002 	.word	0x00160002
-     f10:	00170002 	.word	0x00170002
-     f14:	20000250 	.word	0x20000250
-     f18:	20000238 	.word	0x20000238
-     f1c:	00000e3d 	.word	0x00000e3d
-     f20:	20000234 	.word	0x20000234
-     f24:	00000e11 	.word	0x00000e11
-     f28:	20000230 	.word	0x20000230
-     f2c:	42001400 	.word	0x42001400
-     f30:	00000f45 	.word	0x00000f45
-     f34:	20000018 	.word	0x20000018
-     f38:	00002721 	.word	0x00002721
-     f3c:	000014e5 	.word	0x000014e5
-     f40:	e000e100 	.word	0xe000e100
-
-00000f44 <usart_init>:
- */
-enum status_code usart_init(
-		struct usart_module *const module,
-		Sercom *const hw,
-		const struct usart_config *const config)
-{
-     f44:	b5f0      	push	{r4, r5, r6, r7, lr}
-     f46:	46de      	mov	lr, fp
-     f48:	4657      	mov	r7, sl
-     f4a:	464e      	mov	r6, r9
-     f4c:	4645      	mov	r5, r8
-     f4e:	b5e0      	push	{r5, r6, r7, lr}
-     f50:	b091      	sub	sp, #68	; 0x44
-     f52:	0005      	movs	r5, r0
-     f54:	000c      	movs	r4, r1
-     f56:	0016      	movs	r6, r2
-	Assert(config);
-
-	enum status_code status_code = STATUS_OK;
-
-	/* Assign module pointer to software instance struct */
-	module->hw = hw;
-     f58:	6029      	str	r1, [r5, #0]
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-     f5a:	0008      	movs	r0, r1
-     f5c:	4bba      	ldr	r3, [pc, #744]	; (1248 <usart_init+0x304>)
-     f5e:	4798      	blx	r3
-     f60:	0002      	movs	r2, r0
-#else
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-#endif
-
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
-     f62:	6823      	ldr	r3, [r4, #0]
-		/* The module is busy resetting itself */
-		return STATUS_BUSY;
-     f64:	2005      	movs	r0, #5
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
-     f66:	07db      	lsls	r3, r3, #31
-     f68:	d506      	bpl.n	f78 <usart_init+0x34>
-	_sercom_set_handler(instance_index, _usart_interrupt_handler);
-	_sercom_instances[instance_index] = module;
-#endif
-
-	return status_code;
-}
-     f6a:	b011      	add	sp, #68	; 0x44
-     f6c:	bc3c      	pop	{r2, r3, r4, r5}
-     f6e:	4690      	mov	r8, r2
-     f70:	4699      	mov	r9, r3
-     f72:	46a2      	mov	sl, r4
-     f74:	46ab      	mov	fp, r5
-     f76:	bdf0      	pop	{r4, r5, r6, r7, pc}
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
-     f78:	6823      	ldr	r3, [r4, #0]
-		return STATUS_ERR_DENIED;
-     f7a:	3017      	adds	r0, #23
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
-     f7c:	079b      	lsls	r3, r3, #30
-     f7e:	d4f4      	bmi.n	f6a <usart_init+0x26>
-			PM->APBCMASK.reg |= mask;
-     f80:	49b2      	ldr	r1, [pc, #712]	; (124c <usart_init+0x308>)
-     f82:	6a08      	ldr	r0, [r1, #32]
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-     f84:	1c97      	adds	r7, r2, #2
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-     f86:	2301      	movs	r3, #1
-     f88:	40bb      	lsls	r3, r7
-     f8a:	4303      	orrs	r3, r0
-     f8c:	620b      	str	r3, [r1, #32]
-	gclk_chan_conf.source_generator = config->generator_source;
-     f8e:	a90f      	add	r1, sp, #60	; 0x3c
-     f90:	272d      	movs	r7, #45	; 0x2d
-     f92:	5df3      	ldrb	r3, [r6, r7]
-     f94:	700b      	strb	r3, [r1, #0]
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-     f96:	3214      	adds	r2, #20
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-     f98:	b2d3      	uxtb	r3, r2
-     f9a:	9302      	str	r3, [sp, #8]
-     f9c:	0018      	movs	r0, r3
-     f9e:	4bac      	ldr	r3, [pc, #688]	; (1250 <usart_init+0x30c>)
-     fa0:	4798      	blx	r3
-	system_gclk_chan_enable(gclk_index);
-     fa2:	9802      	ldr	r0, [sp, #8]
-     fa4:	4bab      	ldr	r3, [pc, #684]	; (1254 <usart_init+0x310>)
-     fa6:	4798      	blx	r3
-	sercom_set_gclk_generator(config->generator_source, false);
-     fa8:	5df0      	ldrb	r0, [r6, r7]
-     faa:	2100      	movs	r1, #0
-     fac:	4baa      	ldr	r3, [pc, #680]	; (1258 <usart_init+0x314>)
-     fae:	4798      	blx	r3
-	module->character_size = config->character_size;
-     fb0:	7af3      	ldrb	r3, [r6, #11]
-     fb2:	716b      	strb	r3, [r5, #5]
-	module->receiver_enabled = config->receiver_enable;
-     fb4:	2324      	movs	r3, #36	; 0x24
-     fb6:	5cf3      	ldrb	r3, [r6, r3]
-     fb8:	71ab      	strb	r3, [r5, #6]
-	module->transmitter_enabled = config->transmitter_enable;
-     fba:	2325      	movs	r3, #37	; 0x25
-     fbc:	5cf3      	ldrb	r3, [r6, r3]
-     fbe:	71eb      	strb	r3, [r5, #7]
-	module->lin_slave_enabled = config->lin_slave_enable;
-     fc0:	7ef3      	ldrb	r3, [r6, #27]
-     fc2:	722b      	strb	r3, [r5, #8]
-	module->start_frame_detection_enabled = config->start_frame_detection_enable;
-     fc4:	7f33      	ldrb	r3, [r6, #28]
-     fc6:	726b      	strb	r3, [r5, #9]
-	SercomUsart *const usart_hw = &(module->hw->USART);
-     fc8:	682b      	ldr	r3, [r5, #0]
-     fca:	4698      	mov	r8, r3
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-     fcc:	0018      	movs	r0, r3
-     fce:	4b9e      	ldr	r3, [pc, #632]	; (1248 <usart_init+0x304>)
-     fd0:	4798      	blx	r3
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-     fd2:	3014      	adds	r0, #20
-	uint16_t baud  = 0;
-     fd4:	2200      	movs	r2, #0
-     fd6:	230e      	movs	r3, #14
-     fd8:	a906      	add	r1, sp, #24
-     fda:	468c      	mov	ip, r1
-     fdc:	4463      	add	r3, ip
-     fde:	801a      	strh	r2, [r3, #0]
-	switch (config->sample_rate) {
-     fe0:	8a32      	ldrh	r2, [r6, #16]
-     fe2:	9202      	str	r2, [sp, #8]
-     fe4:	2380      	movs	r3, #128	; 0x80
-     fe6:	01db      	lsls	r3, r3, #7
-     fe8:	429a      	cmp	r2, r3
-     fea:	d100      	bne.n	fee <usart_init+0xaa>
-     fec:	e09a      	b.n	1124 <usart_init+0x1e0>
-     fee:	d90f      	bls.n	1010 <usart_init+0xcc>
-     ff0:	23c0      	movs	r3, #192	; 0xc0
-     ff2:	01db      	lsls	r3, r3, #7
-     ff4:	9a02      	ldr	r2, [sp, #8]
-     ff6:	429a      	cmp	r2, r3
-     ff8:	d100      	bne.n	ffc <usart_init+0xb8>
-     ffa:	e08e      	b.n	111a <usart_init+0x1d6>
-     ffc:	2380      	movs	r3, #128	; 0x80
-     ffe:	021b      	lsls	r3, r3, #8
-    1000:	429a      	cmp	r2, r3
-    1002:	d000      	beq.n	1006 <usart_init+0xc2>
-    1004:	e11b      	b.n	123e <usart_init+0x2fa>
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
-    1006:	2303      	movs	r3, #3
-    1008:	9306      	str	r3, [sp, #24]
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-    100a:	2300      	movs	r3, #0
-    100c:	9307      	str	r3, [sp, #28]
-    100e:	e008      	b.n	1022 <usart_init+0xde>
-	switch (config->sample_rate) {
-    1010:	2380      	movs	r3, #128	; 0x80
-    1012:	019b      	lsls	r3, r3, #6
-    1014:	429a      	cmp	r2, r3
-    1016:	d000      	beq.n	101a <usart_init+0xd6>
-    1018:	e111      	b.n	123e <usart_init+0x2fa>
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-    101a:	2310      	movs	r3, #16
-    101c:	9306      	str	r3, [sp, #24]
-			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
-    101e:	3b0f      	subs	r3, #15
-    1020:	9307      	str	r3, [sp, #28]
-	ctrla = (uint32_t)config->data_order |
-    1022:	6833      	ldr	r3, [r6, #0]
-    1024:	9305      	str	r3, [sp, #20]
-		(uint32_t)config->mux_setting |
-    1026:	68f3      	ldr	r3, [r6, #12]
-    1028:	469b      	mov	fp, r3
-		config->sample_adjustment |
-    102a:	6973      	ldr	r3, [r6, #20]
-    102c:	9303      	str	r3, [sp, #12]
-		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
-    102e:	7e33      	ldrb	r3, [r6, #24]
-    1030:	9304      	str	r3, [sp, #16]
-		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
-    1032:	2326      	movs	r3, #38	; 0x26
-    1034:	5cf3      	ldrb	r3, [r6, r3]
-    1036:	469a      	mov	sl, r3
-	transfer_mode = (uint32_t)config->transfer_mode;
-    1038:	6873      	ldr	r3, [r6, #4]
-    103a:	4699      	mov	r9, r3
-	switch (transfer_mode)
-    103c:	2b00      	cmp	r3, #0
-    103e:	d100      	bne.n	1042 <usart_init+0xfe>
-    1040:	e09c      	b.n	117c <usart_init+0x238>
-    1042:	2380      	movs	r3, #128	; 0x80
-    1044:	055b      	lsls	r3, r3, #21
-    1046:	4599      	cmp	r9, r3
-    1048:	d100      	bne.n	104c <usart_init+0x108>
-    104a:	e080      	b.n	114e <usart_init+0x20a>
-	if(config->encoding_format_enable) {
-    104c:	7e73      	ldrb	r3, [r6, #25]
-    104e:	2b00      	cmp	r3, #0
-    1050:	d002      	beq.n	1058 <usart_init+0x114>
-		usart_hw->RXPL.reg = config->receive_pulse_length;
-    1052:	7eb3      	ldrb	r3, [r6, #26]
-    1054:	4642      	mov	r2, r8
-    1056:	7393      	strb	r3, [r2, #14]
-	usart_hw->BAUD.reg = baud;
-    1058:	230e      	movs	r3, #14
-    105a:	aa06      	add	r2, sp, #24
-    105c:	4694      	mov	ip, r2
-    105e:	4463      	add	r3, ip
-    1060:	881b      	ldrh	r3, [r3, #0]
-    1062:	4642      	mov	r2, r8
-    1064:	8193      	strh	r3, [r2, #12]
-	ctrla |= transfer_mode;
-    1066:	9b05      	ldr	r3, [sp, #20]
-    1068:	465a      	mov	r2, fp
-    106a:	4313      	orrs	r3, r2
-    106c:	9a03      	ldr	r2, [sp, #12]
-    106e:	4313      	orrs	r3, r2
-    1070:	464a      	mov	r2, r9
-    1072:	4313      	orrs	r3, r2
-    1074:	9f02      	ldr	r7, [sp, #8]
-    1076:	431f      	orrs	r7, r3
-		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
-    1078:	9b04      	ldr	r3, [sp, #16]
-    107a:	021b      	lsls	r3, r3, #8
-	ctrla |= transfer_mode;
-    107c:	431f      	orrs	r7, r3
-		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
-    107e:	4653      	mov	r3, sl
-    1080:	075b      	lsls	r3, r3, #29
-	ctrla |= transfer_mode;
-    1082:	431f      	orrs	r7, r3
-	if (config->use_external_clock == false) {
-    1084:	2327      	movs	r3, #39	; 0x27
-    1086:	5cf3      	ldrb	r3, [r6, r3]
-    1088:	2b00      	cmp	r3, #0
-    108a:	d101      	bne.n	1090 <usart_init+0x14c>
-		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
-    108c:	3304      	adds	r3, #4
-    108e:	431f      	orrs	r7, r3
-			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
-    1090:	7e73      	ldrb	r3, [r6, #25]
-    1092:	029b      	lsls	r3, r3, #10
-			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
-    1094:	7f32      	ldrb	r2, [r6, #28]
-    1096:	0252      	lsls	r2, r2, #9
-			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
-    1098:	4313      	orrs	r3, r2
-			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
-    109a:	7f72      	ldrb	r2, [r6, #29]
-    109c:	0212      	lsls	r2, r2, #8
-			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
-    109e:	4313      	orrs	r3, r2
-			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
-    10a0:	2224      	movs	r2, #36	; 0x24
-    10a2:	5cb2      	ldrb	r2, [r6, r2]
-    10a4:	0452      	lsls	r2, r2, #17
-			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
-    10a6:	4313      	orrs	r3, r2
-			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
-    10a8:	2225      	movs	r2, #37	; 0x25
-    10aa:	5cb2      	ldrb	r2, [r6, r2]
-    10ac:	0412      	lsls	r2, r2, #16
-			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
-    10ae:	4313      	orrs	r3, r2
-	ctrlb |= (uint32_t)config->character_size;
-    10b0:	7ab1      	ldrb	r1, [r6, #10]
-    10b2:	7af2      	ldrb	r2, [r6, #11]
-    10b4:	4311      	orrs	r1, r2
-    10b6:	4319      	orrs	r1, r3
-	if (config->parity != USART_PARITY_NONE) {
-    10b8:	8933      	ldrh	r3, [r6, #8]
-    10ba:	2bff      	cmp	r3, #255	; 0xff
-    10bc:	d100      	bne.n	10c0 <usart_init+0x17c>
-    10be:	e081      	b.n	11c4 <usart_init+0x280>
-		ctrla |= SERCOM_USART_CTRLA_FORM(1);
-    10c0:	2280      	movs	r2, #128	; 0x80
-    10c2:	0452      	lsls	r2, r2, #17
-    10c4:	4317      	orrs	r7, r2
-		ctrlb |= config->parity;
-    10c6:	4319      	orrs	r1, r3
-	if (config->run_in_standby || system_is_debugger_present()) {
-    10c8:	232c      	movs	r3, #44	; 0x2c
-    10ca:	5cf3      	ldrb	r3, [r6, r3]
-    10cc:	2b00      	cmp	r3, #0
-    10ce:	d103      	bne.n	10d8 <usart_init+0x194>
- * \retval false Debugger is not connected to the system
- *
- */
-static inline bool system_is_debugger_present(void)
-{
-	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
-    10d0:	4b62      	ldr	r3, [pc, #392]	; (125c <usart_init+0x318>)
-    10d2:	789b      	ldrb	r3, [r3, #2]
-    10d4:	079b      	lsls	r3, r3, #30
-    10d6:	d501      	bpl.n	10dc <usart_init+0x198>
-		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
-    10d8:	2380      	movs	r3, #128	; 0x80
-    10da:	431f      	orrs	r7, r3
-	SercomUsart *const usart_hw = &(module->hw->USART);
-    10dc:	682a      	ldr	r2, [r5, #0]
-	return (usart_hw->SYNCBUSY.reg);
-    10de:	69d3      	ldr	r3, [r2, #28]
-	while (usart_is_syncing(module)) {
-    10e0:	2b00      	cmp	r3, #0
-    10e2:	d1fc      	bne.n	10de <usart_init+0x19a>
-	usart_hw->CTRLB.reg = ctrlb;
-    10e4:	4643      	mov	r3, r8
-    10e6:	6059      	str	r1, [r3, #4]
-	SercomUsart *const usart_hw = &(module->hw->USART);
-    10e8:	682a      	ldr	r2, [r5, #0]
-	return (usart_hw->SYNCBUSY.reg);
-    10ea:	69d3      	ldr	r3, [r2, #28]
-	while (usart_is_syncing(module)) {
-    10ec:	2b00      	cmp	r3, #0
-    10ee:	d1fc      	bne.n	10ea <usart_init+0x1a6>
-	usart_hw->CTRLA.reg = ctrla;
-    10f0:	4643      	mov	r3, r8
-    10f2:	601f      	str	r7, [r3, #0]
-	config->mux_position = SYSTEM_PINMUX_GPIO;
-    10f4:	ab0e      	add	r3, sp, #56	; 0x38
-    10f6:	2280      	movs	r2, #128	; 0x80
-    10f8:	701a      	strb	r2, [r3, #0]
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-    10fa:	2200      	movs	r2, #0
-    10fc:	705a      	strb	r2, [r3, #1]
-	config->powersave    = false;
-    10fe:	70da      	strb	r2, [r3, #3]
-	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
-    1100:	709a      	strb	r2, [r3, #2]
-	uint32_t pad_pinmuxes[] = {
-    1102:	6b33      	ldr	r3, [r6, #48]	; 0x30
-    1104:	930a      	str	r3, [sp, #40]	; 0x28
-    1106:	6b73      	ldr	r3, [r6, #52]	; 0x34
-    1108:	930b      	str	r3, [sp, #44]	; 0x2c
-    110a:	6bb3      	ldr	r3, [r6, #56]	; 0x38
-    110c:	930c      	str	r3, [sp, #48]	; 0x30
-    110e:	6bf3      	ldr	r3, [r6, #60]	; 0x3c
-    1110:	9302      	str	r3, [sp, #8]
-    1112:	930d      	str	r3, [sp, #52]	; 0x34
-    1114:	2700      	movs	r7, #0
-		uint32_t current_pinmux = pad_pinmuxes[pad];
-    1116:	ae0a      	add	r6, sp, #40	; 0x28
-    1118:	e063      	b.n	11e2 <usart_init+0x29e>
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
-    111a:	2308      	movs	r3, #8
-    111c:	9306      	str	r3, [sp, #24]
-			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
-    111e:	3b07      	subs	r3, #7
-    1120:	9307      	str	r3, [sp, #28]
-    1122:	e77e      	b.n	1022 <usart_init+0xde>
-	ctrla = (uint32_t)config->data_order |
-    1124:	6833      	ldr	r3, [r6, #0]
-    1126:	9305      	str	r3, [sp, #20]
-		(uint32_t)config->mux_setting |
-    1128:	68f3      	ldr	r3, [r6, #12]
-    112a:	469b      	mov	fp, r3
-		config->sample_adjustment |
-    112c:	6973      	ldr	r3, [r6, #20]
-    112e:	9303      	str	r3, [sp, #12]
-		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
-    1130:	7e33      	ldrb	r3, [r6, #24]
-    1132:	9304      	str	r3, [sp, #16]
-		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
-    1134:	2326      	movs	r3, #38	; 0x26
-    1136:	5cf3      	ldrb	r3, [r6, r3]
-    1138:	469a      	mov	sl, r3
-	transfer_mode = (uint32_t)config->transfer_mode;
-    113a:	6873      	ldr	r3, [r6, #4]
-    113c:	4699      	mov	r9, r3
-	switch (transfer_mode)
-    113e:	2b00      	cmp	r3, #0
-    1140:	d018      	beq.n	1174 <usart_init+0x230>
-    1142:	2380      	movs	r3, #128	; 0x80
-    1144:	055b      	lsls	r3, r3, #21
-    1146:	4599      	cmp	r9, r3
-    1148:	d001      	beq.n	114e <usart_init+0x20a>
-	enum status_code status_code = STATUS_OK;
-    114a:	2000      	movs	r0, #0
-    114c:	e025      	b.n	119a <usart_init+0x256>
-			if (!config->use_external_clock) {
-    114e:	2327      	movs	r3, #39	; 0x27
-    1150:	5cf3      	ldrb	r3, [r6, r3]
-    1152:	2b00      	cmp	r3, #0
-    1154:	d000      	beq.n	1158 <usart_init+0x214>
-    1156:	e779      	b.n	104c <usart_init+0x108>
-				status_code = _sercom_get_sync_baud_val(config->baudrate,
-    1158:	6a33      	ldr	r3, [r6, #32]
-    115a:	001f      	movs	r7, r3
-    115c:	b2c0      	uxtb	r0, r0
-    115e:	4b40      	ldr	r3, [pc, #256]	; (1260 <usart_init+0x31c>)
-    1160:	4798      	blx	r3
-    1162:	0001      	movs	r1, r0
-    1164:	220e      	movs	r2, #14
-    1166:	ab06      	add	r3, sp, #24
-    1168:	469c      	mov	ip, r3
-    116a:	4462      	add	r2, ip
-    116c:	0038      	movs	r0, r7
-    116e:	4b3d      	ldr	r3, [pc, #244]	; (1264 <usart_init+0x320>)
-    1170:	4798      	blx	r3
-    1172:	e012      	b.n	119a <usart_init+0x256>
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
-    1174:	2308      	movs	r3, #8
-    1176:	9306      	str	r3, [sp, #24]
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-    1178:	2300      	movs	r3, #0
-    117a:	9307      	str	r3, [sp, #28]
-			if (config->use_external_clock) {
-    117c:	2327      	movs	r3, #39	; 0x27
-    117e:	5cf3      	ldrb	r3, [r6, r3]
-    1180:	2b00      	cmp	r3, #0
-    1182:	d00e      	beq.n	11a2 <usart_init+0x25e>
-				status_code =
-    1184:	9b06      	ldr	r3, [sp, #24]
-    1186:	9300      	str	r3, [sp, #0]
-    1188:	9b07      	ldr	r3, [sp, #28]
-    118a:	220e      	movs	r2, #14
-    118c:	a906      	add	r1, sp, #24
-    118e:	468c      	mov	ip, r1
-    1190:	4462      	add	r2, ip
-    1192:	6ab1      	ldr	r1, [r6, #40]	; 0x28
-    1194:	6a30      	ldr	r0, [r6, #32]
-    1196:	4f34      	ldr	r7, [pc, #208]	; (1268 <usart_init+0x324>)
-    1198:	47b8      	blx	r7
-	if (status_code != STATUS_OK) {
-    119a:	2800      	cmp	r0, #0
-    119c:	d000      	beq.n	11a0 <usart_init+0x25c>
-    119e:	e6e4      	b.n	f6a <usart_init+0x26>
-    11a0:	e754      	b.n	104c <usart_init+0x108>
-						_sercom_get_async_baud_val(config->baudrate,
-    11a2:	6a33      	ldr	r3, [r6, #32]
-    11a4:	001f      	movs	r7, r3
-    11a6:	b2c0      	uxtb	r0, r0
-    11a8:	4b2d      	ldr	r3, [pc, #180]	; (1260 <usart_init+0x31c>)
-    11aa:	4798      	blx	r3
-    11ac:	0001      	movs	r1, r0
-				status_code =
-    11ae:	9b06      	ldr	r3, [sp, #24]
-    11b0:	9300      	str	r3, [sp, #0]
-    11b2:	9b07      	ldr	r3, [sp, #28]
-    11b4:	220e      	movs	r2, #14
-    11b6:	a806      	add	r0, sp, #24
-    11b8:	4684      	mov	ip, r0
-    11ba:	4462      	add	r2, ip
-    11bc:	0038      	movs	r0, r7
-    11be:	4f2a      	ldr	r7, [pc, #168]	; (1268 <usart_init+0x324>)
-    11c0:	47b8      	blx	r7
-    11c2:	e7ea      	b.n	119a <usart_init+0x256>
-		if(config->lin_slave_enable) {
-    11c4:	7ef3      	ldrb	r3, [r6, #27]
-    11c6:	2b00      	cmp	r3, #0
-    11c8:	d100      	bne.n	11cc <usart_init+0x288>
-    11ca:	e77d      	b.n	10c8 <usart_init+0x184>
-			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
-    11cc:	2380      	movs	r3, #128	; 0x80
-    11ce:	04db      	lsls	r3, r3, #19
-    11d0:	431f      	orrs	r7, r3
-    11d2:	e779      	b.n	10c8 <usart_init+0x184>
-			current_pinmux = _sercom_get_default_pad(hw, pad);
-    11d4:	0020      	movs	r0, r4
-    11d6:	4b25      	ldr	r3, [pc, #148]	; (126c <usart_init+0x328>)
-    11d8:	4798      	blx	r3
-    11da:	e007      	b.n	11ec <usart_init+0x2a8>
-    11dc:	3701      	adds	r7, #1
-	for (uint8_t pad = 0; pad < 4; pad++) {
-    11de:	2f04      	cmp	r7, #4
-    11e0:	d00d      	beq.n	11fe <usart_init+0x2ba>
-    11e2:	b2f9      	uxtb	r1, r7
-		uint32_t current_pinmux = pad_pinmuxes[pad];
-    11e4:	00bb      	lsls	r3, r7, #2
-    11e6:	5998      	ldr	r0, [r3, r6]
-		if (current_pinmux == PINMUX_DEFAULT) {
-    11e8:	2800      	cmp	r0, #0
-    11ea:	d0f3      	beq.n	11d4 <usart_init+0x290>
-		if (current_pinmux != PINMUX_UNUSED) {
-    11ec:	1c43      	adds	r3, r0, #1
-    11ee:	d0f5      	beq.n	11dc <usart_init+0x298>
-			pin_conf.mux_position = current_pinmux & 0xFFFF;
-    11f0:	a90e      	add	r1, sp, #56	; 0x38
-    11f2:	7008      	strb	r0, [r1, #0]
-			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
-    11f4:	0c00      	lsrs	r0, r0, #16
-    11f6:	b2c0      	uxtb	r0, r0
-    11f8:	4b1d      	ldr	r3, [pc, #116]	; (1270 <usart_init+0x32c>)
-    11fa:	4798      	blx	r3
-    11fc:	e7ee      	b.n	11dc <usart_init+0x298>
-		module->callback[i]            = NULL;
-    11fe:	2300      	movs	r3, #0
-    1200:	60eb      	str	r3, [r5, #12]
-    1202:	612b      	str	r3, [r5, #16]
-    1204:	616b      	str	r3, [r5, #20]
-    1206:	61ab      	str	r3, [r5, #24]
-    1208:	61eb      	str	r3, [r5, #28]
-    120a:	622b      	str	r3, [r5, #32]
-	module->tx_buffer_ptr              = NULL;
-    120c:	62ab      	str	r3, [r5, #40]	; 0x28
-	module->rx_buffer_ptr              = NULL;
-    120e:	626b      	str	r3, [r5, #36]	; 0x24
-	module->remaining_tx_buffer_length = 0x0000;
-    1210:	2200      	movs	r2, #0
-    1212:	85eb      	strh	r3, [r5, #46]	; 0x2e
-	module->remaining_rx_buffer_length = 0x0000;
-    1214:	85ab      	strh	r3, [r5, #44]	; 0x2c
-	module->callback_reg_mask          = 0x00;
-    1216:	3330      	adds	r3, #48	; 0x30
-    1218:	54ea      	strb	r2, [r5, r3]
-	module->callback_enable_mask       = 0x00;
-    121a:	3301      	adds	r3, #1
-    121c:	54ea      	strb	r2, [r5, r3]
-	module->rx_status                  = STATUS_OK;
-    121e:	3301      	adds	r3, #1
-    1220:	54ea      	strb	r2, [r5, r3]
-	module->tx_status                  = STATUS_OK;
-    1222:	3301      	adds	r3, #1
-    1224:	54ea      	strb	r2, [r5, r3]
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
-    1226:	6828      	ldr	r0, [r5, #0]
-    1228:	4b07      	ldr	r3, [pc, #28]	; (1248 <usart_init+0x304>)
-    122a:	4798      	blx	r3
-    122c:	0004      	movs	r4, r0
-	_sercom_set_handler(instance_index, _usart_interrupt_handler);
-    122e:	4911      	ldr	r1, [pc, #68]	; (1274 <usart_init+0x330>)
-    1230:	4b11      	ldr	r3, [pc, #68]	; (1278 <usart_init+0x334>)
-    1232:	4798      	blx	r3
-	_sercom_instances[instance_index] = module;
-    1234:	00a4      	lsls	r4, r4, #2
-    1236:	4b11      	ldr	r3, [pc, #68]	; (127c <usart_init+0x338>)
-    1238:	50e5      	str	r5, [r4, r3]
-	return status_code;
-    123a:	2000      	movs	r0, #0
-    123c:	e695      	b.n	f6a <usart_init+0x26>
-	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-    123e:	2310      	movs	r3, #16
-    1240:	9306      	str	r3, [sp, #24]
-	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-    1242:	2300      	movs	r3, #0
-    1244:	9307      	str	r3, [sp, #28]
-    1246:	e6ec      	b.n	1022 <usart_init+0xde>
-    1248:	00000bed 	.word	0x00000bed
-    124c:	40000400 	.word	0x40000400
-    1250:	00001af5 	.word	0x00001af5
-    1254:	00001a69 	.word	0x00001a69
-    1258:	00000a29 	.word	0x00000a29
-    125c:	41002000 	.word	0x41002000
-    1260:	00001b11 	.word	0x00001b11
-    1264:	0000096d 	.word	0x0000096d
-    1268:	00000995 	.word	0x00000995
-    126c:	00000a75 	.word	0x00000a75
-    1270:	00001bed 	.word	0x00001bed
-    1274:	00001311 	.word	0x00001311
-    1278:	000014a9 	.word	0x000014a9
-    127c:	20000284 	.word	0x20000284
-
-00001280 <usart_write_wait>:
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-    1280:	79c2      	ldrb	r2, [r0, #7]
-		return STATUS_ERR_DENIED;
-    1282:	231c      	movs	r3, #28
-	if (!(module->transmitter_enabled)) {
-    1284:	2a00      	cmp	r2, #0
-    1286:	d101      	bne.n	128c <usart_write_wait+0xc>
-	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
-		/* Wait until data is sent */
-	}
-
-	return STATUS_OK;
-}
-    1288:	0018      	movs	r0, r3
-    128a:	4770      	bx	lr
-	if (module->remaining_tx_buffer_length > 0) {
-    128c:	8dc2      	ldrh	r2, [r0, #46]	; 0x2e
-    128e:	b292      	uxth	r2, r2
-		return STATUS_BUSY;
-    1290:	3b17      	subs	r3, #23
-	if (module->remaining_tx_buffer_length > 0) {
-    1292:	2a00      	cmp	r2, #0
-    1294:	d1f8      	bne.n	1288 <usart_write_wait+0x8>
-	SercomUsart *const usart_hw = &(module->hw->USART);
-    1296:	6802      	ldr	r2, [r0, #0]
-	usart_hw->DATA.reg = tx_data;
-    1298:	8511      	strh	r1, [r2, #40]	; 0x28
-	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
-    129a:	2102      	movs	r1, #2
-    129c:	7e13      	ldrb	r3, [r2, #24]
-    129e:	420b      	tst	r3, r1
-    12a0:	d0fc      	beq.n	129c <usart_write_wait+0x1c>
-	return STATUS_OK;
-    12a2:	2300      	movs	r3, #0
-    12a4:	e7f0      	b.n	1288 <usart_write_wait+0x8>
-
-000012a6 <usart_read_wait>:
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-    12a6:	7982      	ldrb	r2, [r0, #6]
-		return STATUS_ERR_DENIED;
-    12a8:	231c      	movs	r3, #28
-	if (!(module->receiver_enabled)) {
-    12aa:	2a00      	cmp	r2, #0
-    12ac:	d101      	bne.n	12b2 <usart_read_wait+0xc>
-
-	/* Read data from USART module */
-	*rx_data = usart_hw->DATA.reg;
-
-	return STATUS_OK;
-}
-    12ae:	0018      	movs	r0, r3
-    12b0:	4770      	bx	lr
-	if (module->remaining_rx_buffer_length > 0) {
-    12b2:	8d82      	ldrh	r2, [r0, #44]	; 0x2c
-    12b4:	b292      	uxth	r2, r2
-		return STATUS_BUSY;
-    12b6:	3b17      	subs	r3, #23
-	if (module->remaining_rx_buffer_length > 0) {
-    12b8:	2a00      	cmp	r2, #0
-    12ba:	d1f8      	bne.n	12ae <usart_read_wait+0x8>
-	SercomUsart *const usart_hw = &(module->hw->USART);
-    12bc:	6802      	ldr	r2, [r0, #0]
-	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
-    12be:	7e10      	ldrb	r0, [r2, #24]
-    12c0:	0740      	lsls	r0, r0, #29
-    12c2:	d5f4      	bpl.n	12ae <usart_read_wait+0x8>
-	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
-    12c4:	8b53      	ldrh	r3, [r2, #26]
-    12c6:	b2db      	uxtb	r3, r3
-	if (error_code) {
-    12c8:	0698      	lsls	r0, r3, #26
-    12ca:	d01d      	beq.n	1308 <usart_read_wait+0x62>
-		if (error_code & SERCOM_USART_STATUS_FERR) {
-    12cc:	0798      	lsls	r0, r3, #30
-    12ce:	d503      	bpl.n	12d8 <usart_read_wait+0x32>
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-    12d0:	2302      	movs	r3, #2
-    12d2:	8353      	strh	r3, [r2, #26]
-			return STATUS_ERR_BAD_FORMAT;
-    12d4:	3318      	adds	r3, #24
-    12d6:	e7ea      	b.n	12ae <usart_read_wait+0x8>
-		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
-    12d8:	0758      	lsls	r0, r3, #29
-    12da:	d503      	bpl.n	12e4 <usart_read_wait+0x3e>
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-    12dc:	2304      	movs	r3, #4
-    12de:	8353      	strh	r3, [r2, #26]
-			return STATUS_ERR_OVERFLOW;
-    12e0:	331a      	adds	r3, #26
-    12e2:	e7e4      	b.n	12ae <usart_read_wait+0x8>
-		} else if (error_code & SERCOM_USART_STATUS_PERR) {
-    12e4:	07d8      	lsls	r0, r3, #31
-    12e6:	d503      	bpl.n	12f0 <usart_read_wait+0x4a>
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
-    12e8:	2301      	movs	r3, #1
-    12ea:	8353      	strh	r3, [r2, #26]
-			return STATUS_ERR_BAD_DATA;
-    12ec:	3312      	adds	r3, #18
-    12ee:	e7de      	b.n	12ae <usart_read_wait+0x8>
-		else if (error_code & SERCOM_USART_STATUS_ISF) {
-    12f0:	06d8      	lsls	r0, r3, #27
-    12f2:	d503      	bpl.n	12fc <usart_read_wait+0x56>
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
-    12f4:	2310      	movs	r3, #16
-    12f6:	8353      	strh	r3, [r2, #26]
-			return STATUS_ERR_PROTOCOL;
-    12f8:	3332      	adds	r3, #50	; 0x32
-    12fa:	e7d8      	b.n	12ae <usart_read_wait+0x8>
-		else if (error_code & SERCOM_USART_STATUS_COLL) {
-    12fc:	069b      	lsls	r3, r3, #26
-    12fe:	d503      	bpl.n	1308 <usart_read_wait+0x62>
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-    1300:	2320      	movs	r3, #32
-    1302:	8353      	strh	r3, [r2, #26]
-			return STATUS_ERR_PACKET_COLLISION;
-    1304:	3321      	adds	r3, #33	; 0x21
-    1306:	e7d2      	b.n	12ae <usart_read_wait+0x8>
-	*rx_data = usart_hw->DATA.reg;
-    1308:	8d13      	ldrh	r3, [r2, #40]	; 0x28
-    130a:	800b      	strh	r3, [r1, #0]
-	return STATUS_OK;
-    130c:	2300      	movs	r3, #0
-    130e:	e7ce      	b.n	12ae <usart_read_wait+0x8>
-
-00001310 <_usart_interrupt_handler>:
- * \param[in]  instance  ID of the SERCOM instance calling the interrupt
- *                       handler.
- */
-void _usart_interrupt_handler(
-		uint8_t instance)
-{
-    1310:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-	uint16_t callback_status;
-	uint8_t error_code;
-
-
-	/* Get device instance from the look-up table */
-	struct usart_module *module
-    1312:	0080      	lsls	r0, r0, #2
-    1314:	4b62      	ldr	r3, [pc, #392]	; (14a0 <_usart_interrupt_handler+0x190>)
-    1316:	58c5      	ldr	r5, [r0, r3]
-		= (struct usart_module *)_sercom_instances[instance];
-
-	/* Pointer to the hardware module instance */
-	SercomUsart *const usart_hw
-		= &(module->hw->USART);
-    1318:	682c      	ldr	r4, [r5, #0]
-	return (usart_hw->SYNCBUSY.reg);
-    131a:	69e3      	ldr	r3, [r4, #28]
-	while (usart_is_syncing(module)) {
-    131c:	2b00      	cmp	r3, #0
-    131e:	d1fc      	bne.n	131a <_usart_interrupt_handler+0xa>
-
-	/* Wait for the synchronization to complete */
-	_usart_wait_for_sync(module);
-
-	/* Read and mask interrupt flag register */
-	interrupt_status = usart_hw->INTFLAG.reg;
-    1320:	7e23      	ldrb	r3, [r4, #24]
-	interrupt_status &= usart_hw->INTENSET.reg;
-    1322:	7da6      	ldrb	r6, [r4, #22]
-    1324:	401e      	ands	r6, r3
-	callback_status = module->callback_reg_mask &
-    1326:	2330      	movs	r3, #48	; 0x30
-    1328:	5ceb      	ldrb	r3, [r5, r3]
-    132a:	2231      	movs	r2, #49	; 0x31
-    132c:	5caf      	ldrb	r7, [r5, r2]
-    132e:	401f      	ands	r7, r3
-			module->callback_enable_mask;
-
-	/* Check if a DATA READY interrupt has occurred,
-	 * and if there is more to transfer */
-	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
-    1330:	07f3      	lsls	r3, r6, #31
-    1332:	d522      	bpl.n	137a <_usart_interrupt_handler+0x6a>
-		if (module->remaining_tx_buffer_length) {
-    1334:	8deb      	ldrh	r3, [r5, #46]	; 0x2e
-    1336:	b29b      	uxth	r3, r3
-    1338:	2b00      	cmp	r3, #0
-    133a:	d01c      	beq.n	1376 <_usart_interrupt_handler+0x66>
-			/* Write value will be at least 8-bits long */
-			uint16_t data_to_send = *(module->tx_buffer_ptr);
-    133c:	6aaa      	ldr	r2, [r5, #40]	; 0x28
-    133e:	7813      	ldrb	r3, [r2, #0]
-    1340:	b2db      	uxtb	r3, r3
-			/* Increment 8-bit pointer */
-			(module->tx_buffer_ptr)++;
-    1342:	1c51      	adds	r1, r2, #1
-    1344:	62a9      	str	r1, [r5, #40]	; 0x28
-
-			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-    1346:	7969      	ldrb	r1, [r5, #5]
-    1348:	2901      	cmp	r1, #1
-    134a:	d00e      	beq.n	136a <_usart_interrupt_handler+0x5a>
-			uint16_t data_to_send = *(module->tx_buffer_ptr);
-    134c:	b29b      	uxth	r3, r3
-				data_to_send |= (*(module->tx_buffer_ptr) << 8);
-				/* Increment 8-bit pointer */
-				(module->tx_buffer_ptr)++;
-			}
-			/* Write the data to send */
-			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
-    134e:	05db      	lsls	r3, r3, #23
-    1350:	0ddb      	lsrs	r3, r3, #23
-    1352:	8523      	strh	r3, [r4, #40]	; 0x28
-
-			if (--(module->remaining_tx_buffer_length) == 0) {
-    1354:	8deb      	ldrh	r3, [r5, #46]	; 0x2e
-    1356:	3b01      	subs	r3, #1
-    1358:	b29b      	uxth	r3, r3
-    135a:	85eb      	strh	r3, [r5, #46]	; 0x2e
-    135c:	2b00      	cmp	r3, #0
-    135e:	d10c      	bne.n	137a <_usart_interrupt_handler+0x6a>
-				/* Disable the Data Register Empty Interrupt */
-				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
-    1360:	3301      	adds	r3, #1
-    1362:	7523      	strb	r3, [r4, #20]
-				/* Enable Transmission Complete interrupt */
-				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
-    1364:	3301      	adds	r3, #1
-    1366:	75a3      	strb	r3, [r4, #22]
-    1368:	e007      	b.n	137a <_usart_interrupt_handler+0x6a>
-				data_to_send |= (*(module->tx_buffer_ptr) << 8);
-    136a:	7851      	ldrb	r1, [r2, #1]
-    136c:	0209      	lsls	r1, r1, #8
-    136e:	430b      	orrs	r3, r1
-				(module->tx_buffer_ptr)++;
-    1370:	3202      	adds	r2, #2
-    1372:	62aa      	str	r2, [r5, #40]	; 0x28
-    1374:	e7eb      	b.n	134e <_usart_interrupt_handler+0x3e>
-
-			}
-		} else {
-			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
-    1376:	2301      	movs	r3, #1
-    1378:	7523      	strb	r3, [r4, #20]
-		}
-	}
-
-	/* Check if the Transmission Complete interrupt has occurred and
-	 * that the transmit buffer is empty */
-	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
-    137a:	07b3      	lsls	r3, r6, #30
-    137c:	d506      	bpl.n	138c <_usart_interrupt_handler+0x7c>
-
-		/* Disable TX Complete Interrupt, and set STATUS_OK */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
-    137e:	2302      	movs	r3, #2
-    1380:	7523      	strb	r3, [r4, #20]
-		module->tx_status = STATUS_OK;
-    1382:	2200      	movs	r2, #0
-    1384:	3331      	adds	r3, #49	; 0x31
-    1386:	54ea      	strb	r2, [r5, r3]
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
-    1388:	07fb      	lsls	r3, r7, #31
-    138a:	d41a      	bmi.n	13c2 <_usart_interrupt_handler+0xb2>
-		}
-	}
-
-	/* Check if the Receive Complete interrupt has occurred, and that
-	 * there's more data to receive */
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
-    138c:	0773      	lsls	r3, r6, #29
-    138e:	d565      	bpl.n	145c <_usart_interrupt_handler+0x14c>
-
-		if (module->remaining_rx_buffer_length) {
-    1390:	8dab      	ldrh	r3, [r5, #44]	; 0x2c
-    1392:	b29b      	uxth	r3, r3
-    1394:	2b00      	cmp	r3, #0
-    1396:	d05f      	beq.n	1458 <_usart_interrupt_handler+0x148>
-			/* Read out the status code and mask away all but the 4 LSBs*/
-			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
-    1398:	8b63      	ldrh	r3, [r4, #26]
-    139a:	b2db      	uxtb	r3, r3
-#if !SAMD20
-			/* CTS status should not be considered as an error */
-			if(error_code & SERCOM_USART_STATUS_CTS) {
-    139c:	071a      	lsls	r2, r3, #28
-    139e:	d414      	bmi.n	13ca <_usart_interrupt_handler+0xba>
-			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
-    13a0:	223f      	movs	r2, #63	; 0x3f
-    13a2:	4013      	ands	r3, r2
-			if(error_code & SERCOM_USART_STATUS_TXE) {
-				error_code &= ~SERCOM_USART_STATUS_TXE;
-			}
-#endif
-			/* Check if an error has occurred during the receiving */
-			if (error_code) {
-    13a4:	2b00      	cmp	r3, #0
-    13a6:	d034      	beq.n	1412 <_usart_interrupt_handler+0x102>
-				/* Check which error occurred */
-				if (error_code & SERCOM_USART_STATUS_FERR) {
-    13a8:	079a      	lsls	r2, r3, #30
-    13aa:	d511      	bpl.n	13d0 <_usart_interrupt_handler+0xc0>
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_BAD_FORMAT;
-    13ac:	221a      	movs	r2, #26
-    13ae:	2332      	movs	r3, #50	; 0x32
-    13b0:	54ea      	strb	r2, [r5, r3]
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-    13b2:	3b30      	subs	r3, #48	; 0x30
-    13b4:	8363      	strh	r3, [r4, #26]
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-				}
-#endif
-
-				/* Run callback if registered and enabled */
-				if (callback_status
-    13b6:	077b      	lsls	r3, r7, #29
-    13b8:	d550      	bpl.n	145c <_usart_interrupt_handler+0x14c>
-						& (1 << USART_CALLBACK_ERROR)) {
-					(*(module->callback[USART_CALLBACK_ERROR]))(module);
-    13ba:	0028      	movs	r0, r5
-    13bc:	696b      	ldr	r3, [r5, #20]
-    13be:	4798      	blx	r3
-    13c0:	e04c      	b.n	145c <_usart_interrupt_handler+0x14c>
-			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
-    13c2:	0028      	movs	r0, r5
-    13c4:	68eb      	ldr	r3, [r5, #12]
-    13c6:	4798      	blx	r3
-    13c8:	e7e0      	b.n	138c <_usart_interrupt_handler+0x7c>
-				error_code &= ~SERCOM_USART_STATUS_CTS;
-    13ca:	2237      	movs	r2, #55	; 0x37
-    13cc:	4013      	ands	r3, r2
-    13ce:	e7e9      	b.n	13a4 <_usart_interrupt_handler+0x94>
-				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
-    13d0:	075a      	lsls	r2, r3, #29
-    13d2:	d505      	bpl.n	13e0 <_usart_interrupt_handler+0xd0>
-					module->rx_status = STATUS_ERR_OVERFLOW;
-    13d4:	221e      	movs	r2, #30
-    13d6:	2332      	movs	r3, #50	; 0x32
-    13d8:	54ea      	strb	r2, [r5, r3]
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-    13da:	3b2e      	subs	r3, #46	; 0x2e
-    13dc:	8363      	strh	r3, [r4, #26]
-    13de:	e7ea      	b.n	13b6 <_usart_interrupt_handler+0xa6>
-				} else if (error_code & SERCOM_USART_STATUS_PERR) {
-    13e0:	07da      	lsls	r2, r3, #31
-    13e2:	d505      	bpl.n	13f0 <_usart_interrupt_handler+0xe0>
-					module->rx_status = STATUS_ERR_BAD_DATA;
-    13e4:	2213      	movs	r2, #19
-    13e6:	2332      	movs	r3, #50	; 0x32
-    13e8:	54ea      	strb	r2, [r5, r3]
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
-    13ea:	3b31      	subs	r3, #49	; 0x31
-    13ec:	8363      	strh	r3, [r4, #26]
-    13ee:	e7e2      	b.n	13b6 <_usart_interrupt_handler+0xa6>
-				else if (error_code & SERCOM_USART_STATUS_ISF) {
-    13f0:	06da      	lsls	r2, r3, #27
-    13f2:	d505      	bpl.n	1400 <_usart_interrupt_handler+0xf0>
-					module->rx_status = STATUS_ERR_PROTOCOL;
-    13f4:	2242      	movs	r2, #66	; 0x42
-    13f6:	2332      	movs	r3, #50	; 0x32
-    13f8:	54ea      	strb	r2, [r5, r3]
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
-    13fa:	3b22      	subs	r3, #34	; 0x22
-    13fc:	8363      	strh	r3, [r4, #26]
-    13fe:	e7da      	b.n	13b6 <_usart_interrupt_handler+0xa6>
-				else if (error_code & SERCOM_USART_STATUS_COLL) {
-    1400:	2220      	movs	r2, #32
-    1402:	421a      	tst	r2, r3
-    1404:	d0d7      	beq.n	13b6 <_usart_interrupt_handler+0xa6>
-					module->rx_status = STATUS_ERR_PACKET_COLLISION;
-    1406:	3221      	adds	r2, #33	; 0x21
-    1408:	2332      	movs	r3, #50	; 0x32
-    140a:	54ea      	strb	r2, [r5, r3]
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-    140c:	3b12      	subs	r3, #18
-    140e:	8363      	strh	r3, [r4, #26]
-    1410:	e7d1      	b.n	13b6 <_usart_interrupt_handler+0xa6>
-
-			} else {
-
-				/* Read current packet from DATA register,
-				 * increment buffer pointer and decrement buffer length */
-				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
-    1412:	8d23      	ldrh	r3, [r4, #40]	; 0x28
-    1414:	05db      	lsls	r3, r3, #23
-    1416:	0ddb      	lsrs	r3, r3, #23
-
-				/* Read value will be at least 8-bits long */
-				*(module->rx_buffer_ptr) = received_data;
-    1418:	b2da      	uxtb	r2, r3
-    141a:	6a69      	ldr	r1, [r5, #36]	; 0x24
-    141c:	700a      	strb	r2, [r1, #0]
-				/* Increment 8-bit pointer */
-				module->rx_buffer_ptr += 1;
-    141e:	6a6a      	ldr	r2, [r5, #36]	; 0x24
-    1420:	1c51      	adds	r1, r2, #1
-    1422:	6269      	str	r1, [r5, #36]	; 0x24
-
-				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-    1424:	7969      	ldrb	r1, [r5, #5]
-    1426:	2901      	cmp	r1, #1
-    1428:	d010      	beq.n	144c <_usart_interrupt_handler+0x13c>
-					/* Increment 8-bit pointer */
-					module->rx_buffer_ptr += 1;
-				}
-
-				/* Check if the last character have been received */
-				if(--(module->remaining_rx_buffer_length) == 0) {
-    142a:	8dab      	ldrh	r3, [r5, #44]	; 0x2c
-    142c:	3b01      	subs	r3, #1
-    142e:	b29b      	uxth	r3, r3
-    1430:	85ab      	strh	r3, [r5, #44]	; 0x2c
-    1432:	2b00      	cmp	r3, #0
-    1434:	d112      	bne.n	145c <_usart_interrupt_handler+0x14c>
-					/* Disable RX Complete Interrupt,
-					 * and set STATUS_OK */
-					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
-    1436:	3304      	adds	r3, #4
-    1438:	7523      	strb	r3, [r4, #20]
-					module->rx_status = STATUS_OK;
-    143a:	2200      	movs	r2, #0
-    143c:	332e      	adds	r3, #46	; 0x2e
-    143e:	54ea      	strb	r2, [r5, r3]
-
-					/* Run callback if registered and enabled */
-					if (callback_status
-    1440:	07bb      	lsls	r3, r7, #30
-    1442:	d50b      	bpl.n	145c <_usart_interrupt_handler+0x14c>
-							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
-						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
-    1444:	0028      	movs	r0, r5
-    1446:	692b      	ldr	r3, [r5, #16]
-    1448:	4798      	blx	r3
-    144a:	e007      	b.n	145c <_usart_interrupt_handler+0x14c>
-					*(module->rx_buffer_ptr) = (received_data >> 8);
-    144c:	0a1b      	lsrs	r3, r3, #8
-    144e:	7053      	strb	r3, [r2, #1]
-					module->rx_buffer_ptr += 1;
-    1450:	6a6b      	ldr	r3, [r5, #36]	; 0x24
-    1452:	3301      	adds	r3, #1
-    1454:	626b      	str	r3, [r5, #36]	; 0x24
-    1456:	e7e8      	b.n	142a <_usart_interrupt_handler+0x11a>
-					}
-				}
-			}
-		} else {
-			/* This should not happen. Disable Receive Complete interrupt. */
-			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
-    1458:	2304      	movs	r3, #4
-    145a:	7523      	strb	r3, [r4, #20]
-		}
-	}
-
-#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
-    145c:	06f3      	lsls	r3, r6, #27
-    145e:	d504      	bpl.n	146a <_usart_interrupt_handler+0x15a>
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
-    1460:	2310      	movs	r3, #16
-    1462:	7523      	strb	r3, [r4, #20]
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
-    1464:	7623      	strb	r3, [r4, #24]
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
-    1466:	06fb      	lsls	r3, r7, #27
-    1468:	d40e      	bmi.n	1488 <_usart_interrupt_handler+0x178>
-		}
-	}
-#endif
-
-#ifdef FEATURE_USART_LIN_SLAVE
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
-    146a:	06b3      	lsls	r3, r6, #26
-    146c:	d504      	bpl.n	1478 <_usart_interrupt_handler+0x168>
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
-    146e:	2320      	movs	r3, #32
-    1470:	7523      	strb	r3, [r4, #20]
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
-    1472:	7623      	strb	r3, [r4, #24]
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
-    1474:	073b      	lsls	r3, r7, #28
-    1476:	d40b      	bmi.n	1490 <_usart_interrupt_handler+0x180>
-		}
-	}
-#endif
-
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
-    1478:	0733      	lsls	r3, r6, #28
-    147a:	d504      	bpl.n	1486 <_usart_interrupt_handler+0x176>
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
-    147c:	2308      	movs	r3, #8
-    147e:	7523      	strb	r3, [r4, #20]
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
-    1480:	7623      	strb	r3, [r4, #24]
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
-    1482:	06bb      	lsls	r3, r7, #26
-    1484:	d408      	bmi.n	1498 <_usart_interrupt_handler+0x188>
-			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
-		}
-	}
-#endif
-}
-    1486:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
-    1488:	0028      	movs	r0, r5
-    148a:	69eb      	ldr	r3, [r5, #28]
-    148c:	4798      	blx	r3
-    148e:	e7ec      	b.n	146a <_usart_interrupt_handler+0x15a>
-			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
-    1490:	0028      	movs	r0, r5
-    1492:	69ab      	ldr	r3, [r5, #24]
-    1494:	4798      	blx	r3
-    1496:	e7ef      	b.n	1478 <_usart_interrupt_handler+0x168>
-			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
-    1498:	6a2b      	ldr	r3, [r5, #32]
-    149a:	0028      	movs	r0, r5
-    149c:	4798      	blx	r3
-}
-    149e:	e7f2      	b.n	1486 <_usart_interrupt_handler+0x176>
-    14a0:	20000284 	.word	0x20000284
-
-000014a4 <_sercom_default_handler>:
- */
-static void _sercom_default_handler(
-		const uint8_t instance)
-{
-	Assert(false);
-}
-    14a4:	4770      	bx	lr
-	...
-
-000014a8 <_sercom_set_handler>:
- * \param[in]  interrupt_handler  Pointer to instance callback handler.
- */
-void _sercom_set_handler(
-		const uint8_t instance,
-		const sercom_handler_t interrupt_handler)
-{
-    14a8:	b5f0      	push	{r4, r5, r6, r7, lr}
-	/* Initialize handlers with default handler and device instances with 0 */
-	if (_handler_table_initialized == false) {
-    14aa:	4b0a      	ldr	r3, [pc, #40]	; (14d4 <_sercom_set_handler+0x2c>)
-    14ac:	781b      	ldrb	r3, [r3, #0]
-    14ae:	2b00      	cmp	r3, #0
-    14b0:	d10c      	bne.n	14cc <_sercom_set_handler+0x24>
-		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
-    14b2:	4f09      	ldr	r7, [pc, #36]	; (14d8 <_sercom_set_handler+0x30>)
-    14b4:	4e09      	ldr	r6, [pc, #36]	; (14dc <_sercom_set_handler+0x34>)
-			_sercom_instances[i] = NULL;
-    14b6:	4d0a      	ldr	r5, [pc, #40]	; (14e0 <_sercom_set_handler+0x38>)
-    14b8:	2400      	movs	r4, #0
-			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
-    14ba:	51de      	str	r6, [r3, r7]
-			_sercom_instances[i] = NULL;
-    14bc:	195a      	adds	r2, r3, r5
-    14be:	6014      	str	r4, [r2, #0]
-    14c0:	3304      	adds	r3, #4
-		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-    14c2:	2b18      	cmp	r3, #24
-    14c4:	d1f9      	bne.n	14ba <_sercom_set_handler+0x12>
-		}
-
-		_handler_table_initialized = true;
-    14c6:	2201      	movs	r2, #1
-    14c8:	4b02      	ldr	r3, [pc, #8]	; (14d4 <_sercom_set_handler+0x2c>)
-    14ca:	701a      	strb	r2, [r3, #0]
-	}
-
-	/* Save interrupt handler */
-	_sercom_interrupt_handlers[instance] = interrupt_handler;
-    14cc:	0080      	lsls	r0, r0, #2
-    14ce:	4b02      	ldr	r3, [pc, #8]	; (14d8 <_sercom_set_handler+0x30>)
-    14d0:	50c1      	str	r1, [r0, r3]
-}
-    14d2:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    14d4:	20000190 	.word	0x20000190
-    14d8:	20000194 	.word	0x20000194
-    14dc:	000014a5 	.word	0x000014a5
-    14e0:	20000284 	.word	0x20000284
-
-000014e4 <_sercom_get_interrupt_vector>:
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
- */
-enum system_interrupt_vector _sercom_get_interrupt_vector(
-		Sercom *const sercom_instance)
-{
-    14e4:	b500      	push	{lr}
-    14e6:	b083      	sub	sp, #12
-	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
-    14e8:	2309      	movs	r3, #9
-    14ea:	466a      	mov	r2, sp
-    14ec:	7013      	strb	r3, [r2, #0]
-    14ee:	3301      	adds	r3, #1
-    14f0:	7053      	strb	r3, [r2, #1]
-    14f2:	3301      	adds	r3, #1
-    14f4:	7093      	strb	r3, [r2, #2]
-    14f6:	3301      	adds	r3, #1
-    14f8:	70d3      	strb	r3, [r2, #3]
-    14fa:	3301      	adds	r3, #1
-    14fc:	7113      	strb	r3, [r2, #4]
-    14fe:	3301      	adds	r3, #1
-    1500:	7153      	strb	r3, [r2, #5]
-		{
-			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
-		};
-
-	/* Retrieve the index of the SERCOM being requested */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
-    1502:	4b03      	ldr	r3, [pc, #12]	; (1510 <_sercom_get_interrupt_vector+0x2c>)
-    1504:	4798      	blx	r3
-
-	/* Get the vector number from the lookup table for the requested SERCOM */
-	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
-    1506:	466b      	mov	r3, sp
-    1508:	5618      	ldrsb	r0, [r3, r0]
-}
-    150a:	b003      	add	sp, #12
-    150c:	bd00      	pop	{pc}
-    150e:	46c0      	nop			; (mov r8, r8)
-    1510:	00000bed 	.word	0x00000bed
-
-00001514 <SERCOM0_Handler>:
-
-/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
-MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
-    1514:	b510      	push	{r4, lr}
-    1516:	4b02      	ldr	r3, [pc, #8]	; (1520 <SERCOM0_Handler+0xc>)
-    1518:	681b      	ldr	r3, [r3, #0]
-    151a:	2000      	movs	r0, #0
-    151c:	4798      	blx	r3
-    151e:	bd10      	pop	{r4, pc}
-    1520:	20000194 	.word	0x20000194
-
-00001524 <SERCOM1_Handler>:
-    1524:	b510      	push	{r4, lr}
-    1526:	4b02      	ldr	r3, [pc, #8]	; (1530 <SERCOM1_Handler+0xc>)
-    1528:	685b      	ldr	r3, [r3, #4]
-    152a:	2001      	movs	r0, #1
-    152c:	4798      	blx	r3
-    152e:	bd10      	pop	{r4, pc}
-    1530:	20000194 	.word	0x20000194
-
-00001534 <SERCOM2_Handler>:
-    1534:	b510      	push	{r4, lr}
-    1536:	4b02      	ldr	r3, [pc, #8]	; (1540 <SERCOM2_Handler+0xc>)
-    1538:	689b      	ldr	r3, [r3, #8]
-    153a:	2002      	movs	r0, #2
-    153c:	4798      	blx	r3
-    153e:	bd10      	pop	{r4, pc}
-    1540:	20000194 	.word	0x20000194
-
-00001544 <SERCOM3_Handler>:
-    1544:	b510      	push	{r4, lr}
-    1546:	4b02      	ldr	r3, [pc, #8]	; (1550 <SERCOM3_Handler+0xc>)
-    1548:	68db      	ldr	r3, [r3, #12]
-    154a:	2003      	movs	r0, #3
-    154c:	4798      	blx	r3
-    154e:	bd10      	pop	{r4, pc}
-    1550:	20000194 	.word	0x20000194
-
-00001554 <SERCOM4_Handler>:
-    1554:	b510      	push	{r4, lr}
-    1556:	4b02      	ldr	r3, [pc, #8]	; (1560 <SERCOM4_Handler+0xc>)
-    1558:	691b      	ldr	r3, [r3, #16]
-    155a:	2004      	movs	r0, #4
-    155c:	4798      	blx	r3
-    155e:	bd10      	pop	{r4, pc}
-    1560:	20000194 	.word	0x20000194
-
-00001564 <SERCOM5_Handler>:
-    1564:	b510      	push	{r4, lr}
-    1566:	4b02      	ldr	r3, [pc, #8]	; (1570 <SERCOM5_Handler+0xc>)
-    1568:	695b      	ldr	r3, [r3, #20]
-    156a:	2005      	movs	r0, #5
-    156c:	4798      	blx	r3
-    156e:	bd10      	pop	{r4, pc}
-    1570:	20000194 	.word	0x20000194
-
-00001574 <delay_init>:
- *
- * This must be called during start up to initialize the delay routine with
- * the current used main clock. It must run any time the main CPU clock is changed.
- */
-void delay_init(void)
-{
-    1574:	b570      	push	{r4, r5, r6, lr}
-	cycles_per_ms = system_gclk_gen_get_hz(0);
-    1576:	2000      	movs	r0, #0
-    1578:	4b08      	ldr	r3, [pc, #32]	; (159c <delay_init+0x28>)
-    157a:	4798      	blx	r3
-    157c:	0005      	movs	r5, r0
-	cycles_per_ms /= 1000;
-    157e:	4c08      	ldr	r4, [pc, #32]	; (15a0 <delay_init+0x2c>)
-    1580:	21fa      	movs	r1, #250	; 0xfa
-    1582:	0089      	lsls	r1, r1, #2
-    1584:	47a0      	blx	r4
-    1586:	4b07      	ldr	r3, [pc, #28]	; (15a4 <delay_init+0x30>)
-    1588:	6018      	str	r0, [r3, #0]
-	cycles_per_us = cycles_per_ms / 1000;
-    158a:	4907      	ldr	r1, [pc, #28]	; (15a8 <delay_init+0x34>)
-    158c:	0028      	movs	r0, r5
-    158e:	47a0      	blx	r4
-    1590:	4b06      	ldr	r3, [pc, #24]	; (15ac <delay_init+0x38>)
-    1592:	6018      	str	r0, [r3, #0]
-
-	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-    1594:	2205      	movs	r2, #5
-    1596:	4b06      	ldr	r3, [pc, #24]	; (15b0 <delay_init+0x3c>)
-    1598:	601a      	str	r2, [r3, #0]
-}
-    159a:	bd70      	pop	{r4, r5, r6, pc}
-    159c:	000019dd 	.word	0x000019dd
-    15a0:	00001df5 	.word	0x00001df5
-    15a4:	2000000c 	.word	0x2000000c
-    15a8:	000f4240 	.word	0x000f4240
-    15ac:	20000010 	.word	0x20000010
-    15b0:	e000e010 	.word	0xe000e010
-
-000015b4 <delay_cycles_ms>:
- *
- * \param n  Number of milliseconds to wait
- */
-void delay_cycles_ms(
-		uint32_t n)
-{
-    15b4:	b530      	push	{r4, r5, lr}
-	while (n--) {
-		/* Devide up to blocks of 1ms */
-		delay_cycles(cycles_per_ms);
-    15b6:	4b08      	ldr	r3, [pc, #32]	; (15d8 <delay_cycles_ms+0x24>)
-    15b8:	681c      	ldr	r4, [r3, #0]
- */
-static inline void delay_cycles(
-		const uint32_t n)
-{
-	if (n > 0) {
-		SysTick->LOAD = n;
-    15ba:	4a08      	ldr	r2, [pc, #32]	; (15dc <delay_cycles_ms+0x28>)
-		SysTick->VAL = 0;
-    15bc:	2500      	movs	r5, #0
-
-		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
-    15be:	2180      	movs	r1, #128	; 0x80
-    15c0:	0249      	lsls	r1, r1, #9
-	while (n--) {
-    15c2:	3801      	subs	r0, #1
-    15c4:	d307      	bcc.n	15d6 <delay_cycles_ms+0x22>
-	if (n > 0) {
-    15c6:	2c00      	cmp	r4, #0
-    15c8:	d0fb      	beq.n	15c2 <delay_cycles_ms+0xe>
-		SysTick->LOAD = n;
-    15ca:	6054      	str	r4, [r2, #4]
-		SysTick->VAL = 0;
-    15cc:	6095      	str	r5, [r2, #8]
-		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
-    15ce:	6813      	ldr	r3, [r2, #0]
-    15d0:	420b      	tst	r3, r1
-    15d2:	d0fc      	beq.n	15ce <delay_cycles_ms+0x1a>
-    15d4:	e7f5      	b.n	15c2 <delay_cycles_ms+0xe>
-	}
-}
-    15d6:	bd30      	pop	{r4, r5, pc}
-    15d8:	2000000c 	.word	0x2000000c
-    15dc:	e000e010 	.word	0xe000e010
-
-000015e0 <cpu_irq_enter_critical>:
-volatile bool g_interrupt_enabled = true;
-#endif
-
-void cpu_irq_enter_critical(void)
-{
-	if (cpu_irq_critical_section_counter == 0) {
-    15e0:	4b0c      	ldr	r3, [pc, #48]	; (1614 <cpu_irq_enter_critical+0x34>)
-    15e2:	681b      	ldr	r3, [r3, #0]
-    15e4:	2b00      	cmp	r3, #0
-    15e6:	d106      	bne.n	15f6 <cpu_irq_enter_critical+0x16>
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
-    15e8:	f3ef 8310 	mrs	r3, PRIMASK
-		if (cpu_irq_is_enabled()) {
-    15ec:	2b00      	cmp	r3, #0
-    15ee:	d007      	beq.n	1600 <cpu_irq_enter_critical+0x20>
-			cpu_irq_disable();
-			cpu_irq_prev_interrupt_state = true;
-		} else {
-			/* Make sure the to save the prev state as false */
-			cpu_irq_prev_interrupt_state = false;
-    15f0:	2200      	movs	r2, #0
-    15f2:	4b09      	ldr	r3, [pc, #36]	; (1618 <cpu_irq_enter_critical+0x38>)
-    15f4:	701a      	strb	r2, [r3, #0]
-		}
-
-	}
-
-	cpu_irq_critical_section_counter++;
-    15f6:	4a07      	ldr	r2, [pc, #28]	; (1614 <cpu_irq_enter_critical+0x34>)
-    15f8:	6813      	ldr	r3, [r2, #0]
-    15fa:	3301      	adds	r3, #1
-    15fc:	6013      	str	r3, [r2, #0]
-}
-    15fe:	4770      	bx	lr
-  __ASM volatile ("cpsid i" : : : "memory");
-    1600:	b672      	cpsid	i
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-    1602:	f3bf 8f5f 	dmb	sy
-			cpu_irq_disable();
-    1606:	2200      	movs	r2, #0
-    1608:	4b04      	ldr	r3, [pc, #16]	; (161c <cpu_irq_enter_critical+0x3c>)
-    160a:	701a      	strb	r2, [r3, #0]
-			cpu_irq_prev_interrupt_state = true;
-    160c:	3201      	adds	r2, #1
-    160e:	4b02      	ldr	r3, [pc, #8]	; (1618 <cpu_irq_enter_critical+0x38>)
-    1610:	701a      	strb	r2, [r3, #0]
-    1612:	e7f0      	b.n	15f6 <cpu_irq_enter_critical+0x16>
-    1614:	200001ac 	.word	0x200001ac
-    1618:	200001b0 	.word	0x200001b0
-    161c:	20000014 	.word	0x20000014
-
-00001620 <cpu_irq_leave_critical>:
-void cpu_irq_leave_critical(void)
-{
-	/* Check if the user is trying to leave a critical section when not in a critical section */
-	Assert(cpu_irq_critical_section_counter > 0);
-
-	cpu_irq_critical_section_counter--;
-    1620:	4b08      	ldr	r3, [pc, #32]	; (1644 <cpu_irq_leave_critical+0x24>)
-    1622:	681a      	ldr	r2, [r3, #0]
-    1624:	3a01      	subs	r2, #1
-    1626:	601a      	str	r2, [r3, #0]
-
-	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
-	   was enabled when entering critical state */
-	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
-    1628:	681b      	ldr	r3, [r3, #0]
-    162a:	2b00      	cmp	r3, #0
-    162c:	d109      	bne.n	1642 <cpu_irq_leave_critical+0x22>
-    162e:	4b06      	ldr	r3, [pc, #24]	; (1648 <cpu_irq_leave_critical+0x28>)
-    1630:	781b      	ldrb	r3, [r3, #0]
-    1632:	2b00      	cmp	r3, #0
-    1634:	d005      	beq.n	1642 <cpu_irq_leave_critical+0x22>
-		cpu_irq_enable();
-    1636:	2201      	movs	r2, #1
-    1638:	4b04      	ldr	r3, [pc, #16]	; (164c <cpu_irq_leave_critical+0x2c>)
-    163a:	701a      	strb	r2, [r3, #0]
-    163c:	f3bf 8f5f 	dmb	sy
-  __ASM volatile ("cpsie i" : : : "memory");
-    1640:	b662      	cpsie	i
-	}
-}
-    1642:	4770      	bx	lr
-    1644:	200001ac 	.word	0x200001ac
-    1648:	200001b0 	.word	0x200001b0
-    164c:	20000014 	.word	0x20000014
-
-00001650 <system_board_init>:
-void board_init(void);
-#  pragma weak board_init=system_board_init
-#endif
-
-void system_board_init(void)
-{
-    1650:	b5f0      	push	{r4, r5, r6, r7, lr}
-    1652:	b083      	sub	sp, #12
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->direction  = PORT_PIN_DIR_INPUT;
-	config->input_pull = PORT_PIN_PULL_UP;
-    1654:	ac01      	add	r4, sp, #4
-    1656:	2501      	movs	r5, #1
-    1658:	7065      	strb	r5, [r4, #1]
-	config->powersave  = false;
-    165a:	2700      	movs	r7, #0
-    165c:	70a7      	strb	r7, [r4, #2]
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
-
-	/* Configure LEDs as outputs, turn them off */
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-    165e:	7025      	strb	r5, [r4, #0]
-	port_pin_set_config(LED_0_PIN, &pin_conf);
-    1660:	0021      	movs	r1, r4
-    1662:	203e      	movs	r0, #62	; 0x3e
-    1664:	4e06      	ldr	r6, [pc, #24]	; (1680 <system_board_init+0x30>)
-    1666:	47b0      	blx	r6
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
-
-	/* Set the pin to high or low atomically based on the requested level */
-	if (level) {
-		port_base->OUTSET.reg = pin_mask;
-    1668:	2280      	movs	r2, #128	; 0x80
-    166a:	05d2      	lsls	r2, r2, #23
-    166c:	4b05      	ldr	r3, [pc, #20]	; (1684 <system_board_init+0x34>)
-    166e:	619a      	str	r2, [r3, #24]
-	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
-
-	/* Set buttons as inputs */
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-    1670:	7027      	strb	r7, [r4, #0]
-	pin_conf.input_pull = PORT_PIN_PULL_UP;
-    1672:	7065      	strb	r5, [r4, #1]
-	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
-    1674:	0021      	movs	r1, r4
-    1676:	200f      	movs	r0, #15
-    1678:	47b0      	blx	r6
-	port_pin_set_output_level(AT86RFX_RST_PIN, true);
-	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
-#endif	
-}
-    167a:	b003      	add	sp, #12
-    167c:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    167e:	46c0      	nop			; (mov r8, r8)
-    1680:	00001689 	.word	0x00001689
-    1684:	41004480 	.word	0x41004480
-
-00001688 <port_pin_set_config>:
- *  \param[in] config    Configuration settings for the pin
- */
-void port_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct port_config *const config)
-{
-    1688:	b500      	push	{lr}
-    168a:	b083      	sub	sp, #12
-	config->mux_position = SYSTEM_PINMUX_GPIO;
-    168c:	ab01      	add	r3, sp, #4
-    168e:	2280      	movs	r2, #128	; 0x80
-    1690:	701a      	strb	r2, [r3, #0]
-
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
-
-	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
-	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
-    1692:	780a      	ldrb	r2, [r1, #0]
-    1694:	705a      	strb	r2, [r3, #1]
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
-    1696:	784a      	ldrb	r2, [r1, #1]
-    1698:	709a      	strb	r2, [r3, #2]
-	pinmux_config.powersave    = config->powersave;
-    169a:	788a      	ldrb	r2, [r1, #2]
-    169c:	70da      	strb	r2, [r3, #3]
-
-	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
-    169e:	0019      	movs	r1, r3
-    16a0:	4b01      	ldr	r3, [pc, #4]	; (16a8 <port_pin_set_config+0x20>)
-    16a2:	4798      	blx	r3
-}
-    16a4:	b003      	add	sp, #12
-    16a6:	bd00      	pop	{pc}
-    16a8:	00001bed 	.word	0x00001bed
-
-000016ac <system_clock_source_get_hz>:
- *
- * \returns Frequency of the given clock source, in Hz.
- */
-uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clock_source)
-{
-    16ac:	b510      	push	{r4, lr}
-	switch (clock_source) {
-    16ae:	2808      	cmp	r0, #8
-    16b0:	d803      	bhi.n	16ba <system_clock_source_get_hz+0xe>
-    16b2:	0080      	lsls	r0, r0, #2
-    16b4:	4b1c      	ldr	r3, [pc, #112]	; (1728 <system_clock_source_get_hz+0x7c>)
-    16b6:	581b      	ldr	r3, [r3, r0]
-    16b8:	469f      	mov	pc, r3
-
-		return _system_clock_inst.dpll.frequency;
-#endif
-
-	default:
-		return 0;
-    16ba:	2000      	movs	r0, #0
-    16bc:	e032      	b.n	1724 <system_clock_source_get_hz+0x78>
-		return _system_clock_inst.xosc.frequency;
-    16be:	4b1b      	ldr	r3, [pc, #108]	; (172c <system_clock_source_get_hz+0x80>)
-    16c0:	6918      	ldr	r0, [r3, #16]
-    16c2:	e02f      	b.n	1724 <system_clock_source_get_hz+0x78>
-		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
-    16c4:	4b1a      	ldr	r3, [pc, #104]	; (1730 <system_clock_source_get_hz+0x84>)
-    16c6:	6a1b      	ldr	r3, [r3, #32]
-    16c8:	059b      	lsls	r3, r3, #22
-    16ca:	0f9b      	lsrs	r3, r3, #30
-    16cc:	4819      	ldr	r0, [pc, #100]	; (1734 <system_clock_source_get_hz+0x88>)
-    16ce:	40d8      	lsrs	r0, r3
-    16d0:	e028      	b.n	1724 <system_clock_source_get_hz+0x78>
-		return _system_clock_inst.xosc32k.frequency;
-    16d2:	4b16      	ldr	r3, [pc, #88]	; (172c <system_clock_source_get_hz+0x80>)
-    16d4:	6958      	ldr	r0, [r3, #20]
-    16d6:	e025      	b.n	1724 <system_clock_source_get_hz+0x78>
-		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
-    16d8:	4b14      	ldr	r3, [pc, #80]	; (172c <system_clock_source_get_hz+0x80>)
-    16da:	681b      	ldr	r3, [r3, #0]
-			return 0;
-    16dc:	2000      	movs	r0, #0
-		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
-    16de:	079b      	lsls	r3, r3, #30
-    16e0:	d520      	bpl.n	1724 <system_clock_source_get_hz+0x78>
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
-    16e2:	4913      	ldr	r1, [pc, #76]	; (1730 <system_clock_source_get_hz+0x84>)
-    16e4:	2210      	movs	r2, #16
-    16e6:	68cb      	ldr	r3, [r1, #12]
-    16e8:	421a      	tst	r2, r3
-    16ea:	d0fc      	beq.n	16e6 <system_clock_source_get_hz+0x3a>
-		switch(_system_clock_inst.dfll.control &
-    16ec:	4b0f      	ldr	r3, [pc, #60]	; (172c <system_clock_source_get_hz+0x80>)
-    16ee:	681a      	ldr	r2, [r3, #0]
-    16f0:	2324      	movs	r3, #36	; 0x24
-    16f2:	4013      	ands	r3, r2
-    16f4:	2b04      	cmp	r3, #4
-    16f6:	d001      	beq.n	16fc <system_clock_source_get_hz+0x50>
-			return 48000000UL;
-    16f8:	480f      	ldr	r0, [pc, #60]	; (1738 <system_clock_source_get_hz+0x8c>)
-    16fa:	e013      	b.n	1724 <system_clock_source_get_hz+0x78>
-			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
-    16fc:	2000      	movs	r0, #0
-    16fe:	4b0f      	ldr	r3, [pc, #60]	; (173c <system_clock_source_get_hz+0x90>)
-    1700:	4798      	blx	r3
-					(_system_clock_inst.dfll.mul & 0xffff);
-    1702:	4b0a      	ldr	r3, [pc, #40]	; (172c <system_clock_source_get_hz+0x80>)
-    1704:	689b      	ldr	r3, [r3, #8]
-    1706:	041b      	lsls	r3, r3, #16
-    1708:	0c1b      	lsrs	r3, r3, #16
-			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
-    170a:	4358      	muls	r0, r3
-    170c:	e00a      	b.n	1724 <system_clock_source_get_hz+0x78>
-		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
-    170e:	2350      	movs	r3, #80	; 0x50
-    1710:	4a07      	ldr	r2, [pc, #28]	; (1730 <system_clock_source_get_hz+0x84>)
-    1712:	5cd3      	ldrb	r3, [r2, r3]
-			return 0;
-    1714:	2000      	movs	r0, #0
-		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
-    1716:	075b      	lsls	r3, r3, #29
-    1718:	d504      	bpl.n	1724 <system_clock_source_get_hz+0x78>
-		return _system_clock_inst.dpll.frequency;
-    171a:	4b04      	ldr	r3, [pc, #16]	; (172c <system_clock_source_get_hz+0x80>)
-    171c:	68d8      	ldr	r0, [r3, #12]
-    171e:	e001      	b.n	1724 <system_clock_source_get_hz+0x78>
-		return 32768UL;
-    1720:	2080      	movs	r0, #128	; 0x80
-    1722:	0200      	lsls	r0, r0, #8
-	}
-}
-    1724:	bd10      	pop	{r4, pc}
-    1726:	46c0      	nop			; (mov r8, r8)
-    1728:	0000380c 	.word	0x0000380c
-    172c:	200001b4 	.word	0x200001b4
-    1730:	40000800 	.word	0x40000800
-    1734:	007a1200 	.word	0x007a1200
-    1738:	02dc6c00 	.word	0x02dc6c00
-    173c:	00001b11 	.word	0x00001b11
-
-00001740 <system_clock_source_osc8m_set_config>:
- *
- * \param[in] config  OSC8M configuration structure containing the new config
- */
-void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config)
-{
-    1740:	b570      	push	{r4, r5, r6, lr}
-	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
-    1742:	490c      	ldr	r1, [pc, #48]	; (1774 <system_clock_source_osc8m_set_config+0x34>)
-    1744:	6a0b      	ldr	r3, [r1, #32]
-
-	/* Use temporary struct to reduce register access */
-	temp.bit.PRESC    = config->prescaler;
-    1746:	7804      	ldrb	r4, [r0, #0]
-	temp.bit.ONDEMAND = config->on_demand;
-    1748:	7885      	ldrb	r5, [r0, #2]
-	temp.bit.RUNSTDBY = config->run_in_standby;
-
-	SYSCTRL->OSC8M = temp;
-    174a:	7840      	ldrb	r0, [r0, #1]
-    174c:	2201      	movs	r2, #1
-    174e:	4010      	ands	r0, r2
-    1750:	0180      	lsls	r0, r0, #6
-    1752:	2640      	movs	r6, #64	; 0x40
-    1754:	43b3      	bics	r3, r6
-    1756:	4303      	orrs	r3, r0
-    1758:	402a      	ands	r2, r5
-    175a:	01d2      	lsls	r2, r2, #7
-    175c:	2080      	movs	r0, #128	; 0x80
-    175e:	4383      	bics	r3, r0
-    1760:	4313      	orrs	r3, r2
-    1762:	2203      	movs	r2, #3
-    1764:	4022      	ands	r2, r4
-    1766:	0212      	lsls	r2, r2, #8
-    1768:	4803      	ldr	r0, [pc, #12]	; (1778 <system_clock_source_osc8m_set_config+0x38>)
-    176a:	4003      	ands	r3, r0
-    176c:	4313      	orrs	r3, r2
-    176e:	620b      	str	r3, [r1, #32]
-}
-    1770:	bd70      	pop	{r4, r5, r6, pc}
-    1772:	46c0      	nop			; (mov r8, r8)
-    1774:	40000800 	.word	0x40000800
-    1778:	fffffcff 	.word	0xfffffcff
-
-0000177c <system_clock_source_enable>:
- *                                 device
- */
-enum status_code system_clock_source_enable(
-		const enum system_clock_source clock_source)
-{
-	switch (clock_source) {
-    177c:	2808      	cmp	r0, #8
-    177e:	d803      	bhi.n	1788 <system_clock_source_enable+0xc>
-    1780:	0080      	lsls	r0, r0, #2
-    1782:	4b25      	ldr	r3, [pc, #148]	; (1818 <system_clock_source_enable+0x9c>)
-    1784:	581b      	ldr	r3, [r3, r0]
-    1786:	469f      	mov	pc, r3
-		/* Always enabled */
-		return STATUS_OK;
-
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-    1788:	2017      	movs	r0, #23
-    178a:	e044      	b.n	1816 <system_clock_source_enable+0x9a>
-		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
-    178c:	4a23      	ldr	r2, [pc, #140]	; (181c <system_clock_source_enable+0xa0>)
-    178e:	6a13      	ldr	r3, [r2, #32]
-    1790:	2102      	movs	r1, #2
-    1792:	430b      	orrs	r3, r1
-    1794:	6213      	str	r3, [r2, #32]
-		return STATUS_OK;
-    1796:	2000      	movs	r0, #0
-    1798:	e03d      	b.n	1816 <system_clock_source_enable+0x9a>
-		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
-    179a:	4a20      	ldr	r2, [pc, #128]	; (181c <system_clock_source_enable+0xa0>)
-    179c:	6993      	ldr	r3, [r2, #24]
-    179e:	2102      	movs	r1, #2
-    17a0:	430b      	orrs	r3, r1
-    17a2:	6193      	str	r3, [r2, #24]
-	}
-
-	return STATUS_OK;
-    17a4:	2000      	movs	r0, #0
-		break;
-    17a6:	e036      	b.n	1816 <system_clock_source_enable+0x9a>
-		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
-    17a8:	4a1c      	ldr	r2, [pc, #112]	; (181c <system_clock_source_enable+0xa0>)
-    17aa:	8a13      	ldrh	r3, [r2, #16]
-    17ac:	2102      	movs	r1, #2
-    17ae:	430b      	orrs	r3, r1
-    17b0:	8213      	strh	r3, [r2, #16]
-	return STATUS_OK;
-    17b2:	2000      	movs	r0, #0
-		break;
-    17b4:	e02f      	b.n	1816 <system_clock_source_enable+0x9a>
-		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
-    17b6:	4a19      	ldr	r2, [pc, #100]	; (181c <system_clock_source_enable+0xa0>)
-    17b8:	8a93      	ldrh	r3, [r2, #20]
-    17ba:	2102      	movs	r1, #2
-    17bc:	430b      	orrs	r3, r1
-    17be:	8293      	strh	r3, [r2, #20]
-	return STATUS_OK;
-    17c0:	2000      	movs	r0, #0
-		break;
-    17c2:	e028      	b.n	1816 <system_clock_source_enable+0x9a>
-		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
-    17c4:	4916      	ldr	r1, [pc, #88]	; (1820 <system_clock_source_enable+0xa4>)
-    17c6:	680b      	ldr	r3, [r1, #0]
-    17c8:	2202      	movs	r2, #2
-    17ca:	4313      	orrs	r3, r2
-    17cc:	600b      	str	r3, [r1, #0]
-	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
-    17ce:	4b13      	ldr	r3, [pc, #76]	; (181c <system_clock_source_enable+0xa0>)
-    17d0:	849a      	strh	r2, [r3, #36]	; 0x24
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
-    17d2:	0019      	movs	r1, r3
-    17d4:	320e      	adds	r2, #14
-    17d6:	68cb      	ldr	r3, [r1, #12]
-    17d8:	421a      	tst	r2, r3
-    17da:	d0fc      	beq.n	17d6 <system_clock_source_enable+0x5a>
-	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
-    17dc:	4a10      	ldr	r2, [pc, #64]	; (1820 <system_clock_source_enable+0xa4>)
-    17de:	6891      	ldr	r1, [r2, #8]
-    17e0:	4b0e      	ldr	r3, [pc, #56]	; (181c <system_clock_source_enable+0xa0>)
-    17e2:	62d9      	str	r1, [r3, #44]	; 0x2c
-	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
-    17e4:	6852      	ldr	r2, [r2, #4]
-    17e6:	629a      	str	r2, [r3, #40]	; 0x28
-	SYSCTRL->DFLLCTRL.reg = 0;
-    17e8:	2200      	movs	r2, #0
-    17ea:	849a      	strh	r2, [r3, #36]	; 0x24
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
-    17ec:	0019      	movs	r1, r3
-    17ee:	3210      	adds	r2, #16
-    17f0:	68cb      	ldr	r3, [r1, #12]
-    17f2:	421a      	tst	r2, r3
-    17f4:	d0fc      	beq.n	17f0 <system_clock_source_enable+0x74>
-	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
-    17f6:	4b0a      	ldr	r3, [pc, #40]	; (1820 <system_clock_source_enable+0xa4>)
-    17f8:	681b      	ldr	r3, [r3, #0]
-    17fa:	b29b      	uxth	r3, r3
-    17fc:	4a07      	ldr	r2, [pc, #28]	; (181c <system_clock_source_enable+0xa0>)
-    17fe:	8493      	strh	r3, [r2, #36]	; 0x24
-	return STATUS_OK;
-    1800:	2000      	movs	r0, #0
-    1802:	e008      	b.n	1816 <system_clock_source_enable+0x9a>
-		SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
-    1804:	4905      	ldr	r1, [pc, #20]	; (181c <system_clock_source_enable+0xa0>)
-    1806:	2244      	movs	r2, #68	; 0x44
-    1808:	5c8b      	ldrb	r3, [r1, r2]
-    180a:	2002      	movs	r0, #2
-    180c:	4303      	orrs	r3, r0
-    180e:	548b      	strb	r3, [r1, r2]
-	return STATUS_OK;
-    1810:	2000      	movs	r0, #0
-		break;
-    1812:	e000      	b.n	1816 <system_clock_source_enable+0x9a>
-		return STATUS_OK;
-    1814:	2000      	movs	r0, #0
-}
-    1816:	4770      	bx	lr
-    1818:	00003830 	.word	0x00003830
-    181c:	40000800 	.word	0x40000800
-    1820:	200001b4 	.word	0x200001b4
-
-00001824 <system_clock_init>:
- * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
- * the OSC8M default enable can be disabled after system_clock_init. Make sure the
- * clock switch successfully before disabling OSC8M.
- */
-void system_clock_init(void)
-{
-    1824:	b530      	push	{r4, r5, lr}
-    1826:	b085      	sub	sp, #20
-	/* Various bits in the INTFLAG register can be set to one at startup.
-	   This will ensure that these bits are cleared */
-	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
-    1828:	22c2      	movs	r2, #194	; 0xc2
-    182a:	00d2      	lsls	r2, r2, #3
-    182c:	4b1a      	ldr	r3, [pc, #104]	; (1898 <system_clock_init+0x74>)
-    182e:	609a      	str	r2, [r3, #8]
-static inline void system_flash_set_waitstates(uint8_t wait_states)
-{
-	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
-			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
-
-	NVMCTRL->CTRLB.bit.RWS = wait_states;
-    1830:	4a1a      	ldr	r2, [pc, #104]	; (189c <system_clock_init+0x78>)
-    1832:	6853      	ldr	r3, [r2, #4]
-    1834:	211e      	movs	r1, #30
-    1836:	438b      	bics	r3, r1
-    1838:	6053      	str	r3, [r2, #4]
-	gclk_conf.source_generator = GCLK_GENERATOR_1;
-    183a:	2301      	movs	r3, #1
-    183c:	466a      	mov	r2, sp
-    183e:	7013      	strb	r3, [r2, #0]
-	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
-    1840:	2400      	movs	r4, #0
-		system_gclk_chan_set_config(gclk_id, &gclk_conf);
-    1842:	4d17      	ldr	r5, [pc, #92]	; (18a0 <system_clock_init+0x7c>)
-    1844:	b2e0      	uxtb	r0, r4
-    1846:	4669      	mov	r1, sp
-    1848:	47a8      	blx	r5
-	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
-    184a:	3401      	adds	r4, #1
-    184c:	2c25      	cmp	r4, #37	; 0x25
-    184e:	d1f9      	bne.n	1844 <system_clock_init+0x20>
-	config->run_in_standby  = false;
-    1850:	a803      	add	r0, sp, #12
-    1852:	2400      	movs	r4, #0
-    1854:	7044      	strb	r4, [r0, #1]
-	config->on_demand       = true;
-    1856:	2501      	movs	r5, #1
-    1858:	7085      	strb	r5, [r0, #2]
-
-	/* OSC8M */
-	struct system_clock_source_osc8m_config osc8m_conf;
-	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
-
-	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
-    185a:	7004      	strb	r4, [r0, #0]
-	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
-	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
-
-	system_clock_source_osc8m_set_config(&osc8m_conf);
-    185c:	4b11      	ldr	r3, [pc, #68]	; (18a4 <system_clock_init+0x80>)
-    185e:	4798      	blx	r3
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
-    1860:	2006      	movs	r0, #6
-    1862:	4b11      	ldr	r3, [pc, #68]	; (18a8 <system_clock_init+0x84>)
-    1864:	4798      	blx	r3
-
-
-	/* GCLK */
-#if CONF_CLOCK_CONFIGURE_GCLK == true
-	system_gclk_init();
-    1866:	4b11      	ldr	r3, [pc, #68]	; (18ac <system_clock_init+0x88>)
-    1868:	4798      	blx	r3
-	PM->CPUSEL.reg = (uint32_t)divider;
-    186a:	4b11      	ldr	r3, [pc, #68]	; (18b0 <system_clock_init+0x8c>)
-    186c:	721c      	strb	r4, [r3, #8]
-			PM->APBASEL.reg = (uint32_t)divider;
-    186e:	725c      	strb	r4, [r3, #9]
-			PM->APBBSEL.reg = (uint32_t)divider;
-    1870:	729c      	strb	r4, [r3, #10]
-			PM->APBCSEL.reg = (uint32_t)divider;
-    1872:	72dc      	strb	r4, [r3, #11]
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->division_factor    = 1;
-    1874:	9501      	str	r5, [sp, #4]
-	config->high_when_disabled = false;
-    1876:	466b      	mov	r3, sp
-    1878:	705c      	strb	r4, [r3, #1]
-#if SAML21 || SAML22  || SAMR30 || SAMR34 || SAMR35
-	config->source_clock       = GCLK_SOURCE_OSC16M;
-#elif (SAMC20) || (SAMC21)
-	config->source_clock       = GCLK_SOURCE_OSC48M;
-#else
-	config->source_clock       = GCLK_SOURCE_OSC8M;
-    187a:	2306      	movs	r3, #6
-    187c:	466a      	mov	r2, sp
-    187e:	7013      	strb	r3, [r2, #0]
-#endif
-	config->run_in_standby     = false;
-    1880:	7214      	strb	r4, [r2, #8]
-	config->output_enable      = false;
-    1882:	7254      	strb	r4, [r2, #9]
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
-
-	/* GCLK 0 */
-#if CONF_CLOCK_CONFIGURE_GCLK == true
-	/* Configure the main GCLK last as it might depend on other generators */
-	_CONF_CLOCK_GCLK_CONFIG(0, ~);
-    1884:	4669      	mov	r1, sp
-    1886:	2000      	movs	r0, #0
-    1888:	4b0a      	ldr	r3, [pc, #40]	; (18b4 <system_clock_init+0x90>)
-    188a:	4798      	blx	r3
-    188c:	2000      	movs	r0, #0
-    188e:	4b0a      	ldr	r3, [pc, #40]	; (18b8 <system_clock_init+0x94>)
-    1890:	4798      	blx	r3
-#endif
-}
-    1892:	b005      	add	sp, #20
-    1894:	bd30      	pop	{r4, r5, pc}
-    1896:	46c0      	nop			; (mov r8, r8)
-    1898:	40000800 	.word	0x40000800
-    189c:	41004000 	.word	0x41004000
-    18a0:	00001af5 	.word	0x00001af5
-    18a4:	00001741 	.word	0x00001741
-    18a8:	0000177d 	.word	0x0000177d
-    18ac:	000018bd 	.word	0x000018bd
-    18b0:	40000400 	.word	0x40000400
-    18b4:	000018e1 	.word	0x000018e1
-    18b8:	00001999 	.word	0x00001999
-
-000018bc <system_gclk_init>:
-			PM->APBAMASK.reg |= mask;
-    18bc:	4a06      	ldr	r2, [pc, #24]	; (18d8 <system_gclk_init+0x1c>)
-    18be:	6993      	ldr	r3, [r2, #24]
-    18c0:	2108      	movs	r1, #8
-    18c2:	430b      	orrs	r3, r1
-    18c4:	6193      	str	r3, [r2, #24]
-{
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
-
-	/* Software reset the module to ensure it is re-initialized correctly */
-	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
-    18c6:	2201      	movs	r2, #1
-    18c8:	4b04      	ldr	r3, [pc, #16]	; (18dc <system_gclk_init+0x20>)
-    18ca:	701a      	strb	r2, [r3, #0]
-	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
-    18cc:	0019      	movs	r1, r3
-    18ce:	780b      	ldrb	r3, [r1, #0]
-    18d0:	4213      	tst	r3, r2
-    18d2:	d1fc      	bne.n	18ce <system_gclk_init+0x12>
-		/* Wait for reset to complete */
-	}
-}
-    18d4:	4770      	bx	lr
-    18d6:	46c0      	nop			; (mov r8, r8)
-    18d8:	40000400 	.word	0x40000400
-    18dc:	40000c00 	.word	0x40000c00
-
-000018e0 <system_gclk_gen_set_config>:
- * \param[in] config     Configuration settings for the generator
- */
-void system_gclk_gen_set_config(
-		const uint8_t generator,
-		struct system_gclk_gen_config *const config)
-{
-    18e0:	b570      	push	{r4, r5, r6, lr}
-    18e2:	0006      	movs	r6, r0
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Cache new register configurations to minimize sync requirements. */
-	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
-    18e4:	0004      	movs	r4, r0
-	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
-
-	/* Select the requested source clock for the generator */
-	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
-    18e6:	780d      	ldrb	r5, [r1, #0]
-    18e8:	022d      	lsls	r5, r5, #8
-    18ea:	4305      	orrs	r5, r0
-
-	/* Configure the clock to be either high or low when disabled */
-	if (config->high_when_disabled) {
-    18ec:	784b      	ldrb	r3, [r1, #1]
-    18ee:	2b00      	cmp	r3, #0
-    18f0:	d002      	beq.n	18f8 <system_gclk_gen_set_config+0x18>
-		new_genctrl_config |= GCLK_GENCTRL_OOV;
-    18f2:	2380      	movs	r3, #128	; 0x80
-    18f4:	02db      	lsls	r3, r3, #11
-    18f6:	431d      	orrs	r5, r3
-	}
-
-	/* Configure if the clock output to I/O pin should be enabled. */
-	if (config->output_enable) {
-    18f8:	7a4b      	ldrb	r3, [r1, #9]
-    18fa:	2b00      	cmp	r3, #0
-    18fc:	d002      	beq.n	1904 <system_gclk_gen_set_config+0x24>
-		new_genctrl_config |= GCLK_GENCTRL_OE;
-    18fe:	2380      	movs	r3, #128	; 0x80
-    1900:	031b      	lsls	r3, r3, #12
-    1902:	431d      	orrs	r5, r3
-	}
-
-	/* Set division factor */
-	if (config->division_factor > 1) {
-    1904:	6848      	ldr	r0, [r1, #4]
-    1906:	2801      	cmp	r0, #1
-    1908:	d910      	bls.n	192c <system_gclk_gen_set_config+0x4c>
-		/* Check if division is a power of two */
-		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
-    190a:	1e43      	subs	r3, r0, #1
-    190c:	4218      	tst	r0, r3
-    190e:	d134      	bne.n	197a <system_gclk_gen_set_config+0x9a>
-			 * register */
-
-			uint32_t div2_count = 0;
-
-			uint32_t mask;
-			for (mask = (1UL << 1); mask < config->division_factor;
-    1910:	2802      	cmp	r0, #2
-    1912:	d930      	bls.n	1976 <system_gclk_gen_set_config+0x96>
-    1914:	2302      	movs	r3, #2
-    1916:	2200      	movs	r2, #0
-						mask <<= 1) {
-				div2_count++;
-    1918:	3201      	adds	r2, #1
-						mask <<= 1) {
-    191a:	005b      	lsls	r3, r3, #1
-			for (mask = (1UL << 1); mask < config->division_factor;
-    191c:	4298      	cmp	r0, r3
-    191e:	d8fb      	bhi.n	1918 <system_gclk_gen_set_config+0x38>
-			}
-
-			/* Set binary divider power of 2 division factor */
-			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
-    1920:	0212      	lsls	r2, r2, #8
-    1922:	4332      	orrs	r2, r6
-    1924:	0014      	movs	r4, r2
-			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
-    1926:	2380      	movs	r3, #128	; 0x80
-    1928:	035b      	lsls	r3, r3, #13
-    192a:	431d      	orrs	r5, r3
-		}
-
-	}
-
-	/* Enable or disable the clock in standby mode */
-	if (config->run_in_standby) {
-    192c:	7a0b      	ldrb	r3, [r1, #8]
-    192e:	2b00      	cmp	r3, #0
-    1930:	d002      	beq.n	1938 <system_gclk_gen_set_config+0x58>
-		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
-    1932:	2380      	movs	r3, #128	; 0x80
-    1934:	039b      	lsls	r3, r3, #14
-    1936:	431d      	orrs	r5, r3
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    1938:	4a13      	ldr	r2, [pc, #76]	; (1988 <system_gclk_gen_set_config+0xa8>)
-    193a:	7853      	ldrb	r3, [r2, #1]
-	}
-
-	while (system_gclk_is_syncing()) {
-    193c:	b25b      	sxtb	r3, r3
-    193e:	2b00      	cmp	r3, #0
-    1940:	dbfb      	blt.n	193a <system_gclk_gen_set_config+0x5a>
-	cpu_irq_enter_critical();
-    1942:	4b12      	ldr	r3, [pc, #72]	; (198c <system_gclk_gen_set_config+0xac>)
-    1944:	4798      	blx	r3
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the correct generator */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-    1946:	4b12      	ldr	r3, [pc, #72]	; (1990 <system_gclk_gen_set_config+0xb0>)
-    1948:	701e      	strb	r6, [r3, #0]
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    194a:	4a0f      	ldr	r2, [pc, #60]	; (1988 <system_gclk_gen_set_config+0xa8>)
-    194c:	7853      	ldrb	r3, [r2, #1]
-
-	/* Write the new generator configuration */
-	while (system_gclk_is_syncing()) {
-    194e:	b25b      	sxtb	r3, r3
-    1950:	2b00      	cmp	r3, #0
-    1952:	dbfb      	blt.n	194c <system_gclk_gen_set_config+0x6c>
-		/* Wait for synchronization */
-	};
-	GCLK->GENDIV.reg  = new_gendiv_config;
-    1954:	4b0c      	ldr	r3, [pc, #48]	; (1988 <system_gclk_gen_set_config+0xa8>)
-    1956:	609c      	str	r4, [r3, #8]
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    1958:	001a      	movs	r2, r3
-    195a:	7853      	ldrb	r3, [r2, #1]
-
-	while (system_gclk_is_syncing()) {
-    195c:	b25b      	sxtb	r3, r3
-    195e:	2b00      	cmp	r3, #0
-    1960:	dbfb      	blt.n	195a <system_gclk_gen_set_config+0x7a>
-		/* Wait for synchronization */
-	};
-	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
-    1962:	4a09      	ldr	r2, [pc, #36]	; (1988 <system_gclk_gen_set_config+0xa8>)
-    1964:	6853      	ldr	r3, [r2, #4]
-    1966:	2180      	movs	r1, #128	; 0x80
-    1968:	0249      	lsls	r1, r1, #9
-    196a:	400b      	ands	r3, r1
-    196c:	431d      	orrs	r5, r3
-    196e:	6055      	str	r5, [r2, #4]
-	cpu_irq_leave_critical();
-    1970:	4b08      	ldr	r3, [pc, #32]	; (1994 <system_gclk_gen_set_config+0xb4>)
-    1972:	4798      	blx	r3
-
-	system_interrupt_leave_critical_section();
-}
-    1974:	bd70      	pop	{r4, r5, r6, pc}
-			for (mask = (1UL << 1); mask < config->division_factor;
-    1976:	2200      	movs	r2, #0
-    1978:	e7d2      	b.n	1920 <system_gclk_gen_set_config+0x40>
-					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
-    197a:	0204      	lsls	r4, r0, #8
-			new_gendiv_config  |=
-    197c:	4334      	orrs	r4, r6
-			new_genctrl_config |= GCLK_GENCTRL_IDC;
-    197e:	2380      	movs	r3, #128	; 0x80
-    1980:	029b      	lsls	r3, r3, #10
-    1982:	431d      	orrs	r5, r3
-    1984:	e7d2      	b.n	192c <system_gclk_gen_set_config+0x4c>
-    1986:	46c0      	nop			; (mov r8, r8)
-    1988:	40000c00 	.word	0x40000c00
-    198c:	000015e1 	.word	0x000015e1
-    1990:	40000c08 	.word	0x40000c08
-    1994:	00001621 	.word	0x00001621
-
-00001998 <system_gclk_gen_enable>:
- *
- * \param[in] generator  Generic Clock Generator index to enable
- */
-void system_gclk_gen_enable(
-		const uint8_t generator)
-{
-    1998:	b510      	push	{r4, lr}
-    199a:	0004      	movs	r4, r0
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    199c:	4a0b      	ldr	r2, [pc, #44]	; (19cc <system_gclk_gen_enable+0x34>)
-    199e:	7853      	ldrb	r3, [r2, #1]
-	while (system_gclk_is_syncing()) {
-    19a0:	b25b      	sxtb	r3, r3
-    19a2:	2b00      	cmp	r3, #0
-    19a4:	dbfb      	blt.n	199e <system_gclk_gen_enable+0x6>
-	cpu_irq_enter_critical();
-    19a6:	4b0a      	ldr	r3, [pc, #40]	; (19d0 <system_gclk_gen_enable+0x38>)
-    19a8:	4798      	blx	r3
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-    19aa:	4b0a      	ldr	r3, [pc, #40]	; (19d4 <system_gclk_gen_enable+0x3c>)
-    19ac:	701c      	strb	r4, [r3, #0]
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    19ae:	4a07      	ldr	r2, [pc, #28]	; (19cc <system_gclk_gen_enable+0x34>)
-    19b0:	7853      	ldrb	r3, [r2, #1]
-	while (system_gclk_is_syncing()) {
-    19b2:	b25b      	sxtb	r3, r3
-    19b4:	2b00      	cmp	r3, #0
-    19b6:	dbfb      	blt.n	19b0 <system_gclk_gen_enable+0x18>
-		/* Wait for synchronization */
-	};
-
-	/* Enable generator */
-	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
-    19b8:	4a04      	ldr	r2, [pc, #16]	; (19cc <system_gclk_gen_enable+0x34>)
-    19ba:	6851      	ldr	r1, [r2, #4]
-    19bc:	2380      	movs	r3, #128	; 0x80
-    19be:	025b      	lsls	r3, r3, #9
-    19c0:	430b      	orrs	r3, r1
-    19c2:	6053      	str	r3, [r2, #4]
-	cpu_irq_leave_critical();
-    19c4:	4b04      	ldr	r3, [pc, #16]	; (19d8 <system_gclk_gen_enable+0x40>)
-    19c6:	4798      	blx	r3
-
-	system_interrupt_leave_critical_section();
-}
-    19c8:	bd10      	pop	{r4, pc}
-    19ca:	46c0      	nop			; (mov r8, r8)
-    19cc:	40000c00 	.word	0x40000c00
-    19d0:	000015e1 	.word	0x000015e1
-    19d4:	40000c04 	.word	0x40000c04
-    19d8:	00001621 	.word	0x00001621
-
-000019dc <system_gclk_gen_get_hz>:
- *
- * \return The frequency of the generic clock generator, in Hz.
- */
-uint32_t system_gclk_gen_get_hz(
-		const uint8_t generator)
-{
-    19dc:	b570      	push	{r4, r5, r6, lr}
-    19de:	0004      	movs	r4, r0
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    19e0:	4a1a      	ldr	r2, [pc, #104]	; (1a4c <system_gclk_gen_get_hz+0x70>)
-    19e2:	7853      	ldrb	r3, [r2, #1]
-	while (system_gclk_is_syncing()) {
-    19e4:	b25b      	sxtb	r3, r3
-    19e6:	2b00      	cmp	r3, #0
-    19e8:	dbfb      	blt.n	19e2 <system_gclk_gen_get_hz+0x6>
-	cpu_irq_enter_critical();
-    19ea:	4b19      	ldr	r3, [pc, #100]	; (1a50 <system_gclk_gen_get_hz+0x74>)
-    19ec:	4798      	blx	r3
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the appropriate generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-    19ee:	4b19      	ldr	r3, [pc, #100]	; (1a54 <system_gclk_gen_get_hz+0x78>)
-    19f0:	701c      	strb	r4, [r3, #0]
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    19f2:	4a16      	ldr	r2, [pc, #88]	; (1a4c <system_gclk_gen_get_hz+0x70>)
-    19f4:	7853      	ldrb	r3, [r2, #1]
-	while (system_gclk_is_syncing()) {
-    19f6:	b25b      	sxtb	r3, r3
-    19f8:	2b00      	cmp	r3, #0
-    19fa:	dbfb      	blt.n	19f4 <system_gclk_gen_get_hz+0x18>
-		/* Wait for synchronization */
-	};
-
-	/* Get the frequency of the source connected to the GCLK generator */
-	uint32_t gen_input_hz = system_clock_source_get_hz(
-			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
-    19fc:	4e13      	ldr	r6, [pc, #76]	; (1a4c <system_gclk_gen_get_hz+0x70>)
-    19fe:	6870      	ldr	r0, [r6, #4]
-    1a00:	04c0      	lsls	r0, r0, #19
-    1a02:	0ec0      	lsrs	r0, r0, #27
-	uint32_t gen_input_hz = system_clock_source_get_hz(
-    1a04:	4b14      	ldr	r3, [pc, #80]	; (1a58 <system_gclk_gen_get_hz+0x7c>)
-    1a06:	4798      	blx	r3
-    1a08:	0005      	movs	r5, r0
-
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-    1a0a:	4b12      	ldr	r3, [pc, #72]	; (1a54 <system_gclk_gen_get_hz+0x78>)
-    1a0c:	701c      	strb	r4, [r3, #0]
-
-	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
-    1a0e:	6876      	ldr	r6, [r6, #4]
-    1a10:	02f6      	lsls	r6, r6, #11
-    1a12:	0ff6      	lsrs	r6, r6, #31
-
-	/* Select the appropriate generator division register */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-    1a14:	4b11      	ldr	r3, [pc, #68]	; (1a5c <system_gclk_gen_get_hz+0x80>)
-    1a16:	701c      	strb	r4, [r3, #0]
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-    1a18:	4a0c      	ldr	r2, [pc, #48]	; (1a4c <system_gclk_gen_get_hz+0x70>)
-    1a1a:	7853      	ldrb	r3, [r2, #1]
-	while (system_gclk_is_syncing()) {
-    1a1c:	b25b      	sxtb	r3, r3
-    1a1e:	2b00      	cmp	r3, #0
-    1a20:	dbfb      	blt.n	1a1a <system_gclk_gen_get_hz+0x3e>
-		/* Wait for synchronization */
-	};
-
-	uint32_t divider = GCLK->GENDIV.bit.DIV;
-    1a22:	4b0a      	ldr	r3, [pc, #40]	; (1a4c <system_gclk_gen_get_hz+0x70>)
-    1a24:	689c      	ldr	r4, [r3, #8]
-    1a26:	0224      	lsls	r4, r4, #8
-    1a28:	0c24      	lsrs	r4, r4, #16
-	cpu_irq_leave_critical();
-    1a2a:	4b0d      	ldr	r3, [pc, #52]	; (1a60 <system_gclk_gen_get_hz+0x84>)
-    1a2c:	4798      	blx	r3
-
-	system_interrupt_leave_critical_section();
-
-	/* Check if the generator is using fractional or binary division */
-	if (!divsel && divider > 1) {
-    1a2e:	2e00      	cmp	r6, #0
-    1a30:	d107      	bne.n	1a42 <system_gclk_gen_get_hz+0x66>
-    1a32:	2c01      	cmp	r4, #1
-    1a34:	d907      	bls.n	1a46 <system_gclk_gen_get_hz+0x6a>
-		gen_input_hz /= divider;
-    1a36:	0021      	movs	r1, r4
-    1a38:	0028      	movs	r0, r5
-    1a3a:	4b0a      	ldr	r3, [pc, #40]	; (1a64 <system_gclk_gen_get_hz+0x88>)
-    1a3c:	4798      	blx	r3
-    1a3e:	0005      	movs	r5, r0
-    1a40:	e001      	b.n	1a46 <system_gclk_gen_get_hz+0x6a>
-	} else if (divsel) {
-		gen_input_hz >>= (divider+1);
-    1a42:	3401      	adds	r4, #1
-    1a44:	40e5      	lsrs	r5, r4
-	}
-
-	return gen_input_hz;
-}
-    1a46:	0028      	movs	r0, r5
-    1a48:	bd70      	pop	{r4, r5, r6, pc}
-    1a4a:	46c0      	nop			; (mov r8, r8)
-    1a4c:	40000c00 	.word	0x40000c00
-    1a50:	000015e1 	.word	0x000015e1
-    1a54:	40000c04 	.word	0x40000c04
-    1a58:	000016ad 	.word	0x000016ad
-    1a5c:	40000c08 	.word	0x40000c08
-    1a60:	00001621 	.word	0x00001621
-    1a64:	00001df5 	.word	0x00001df5
-
-00001a68 <system_gclk_chan_enable>:
- *
- * \param[in] channel   Generic Clock channel to enable
- */
-void system_gclk_chan_enable(
-		const uint8_t channel)
-{
-    1a68:	b510      	push	{r4, lr}
-    1a6a:	0004      	movs	r4, r0
-	cpu_irq_enter_critical();
-    1a6c:	4b06      	ldr	r3, [pc, #24]	; (1a88 <system_gclk_chan_enable+0x20>)
-    1a6e:	4798      	blx	r3
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-    1a70:	4b06      	ldr	r3, [pc, #24]	; (1a8c <system_gclk_chan_enable+0x24>)
-    1a72:	701c      	strb	r4, [r3, #0]
-
-	/* Enable the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
-    1a74:	4a06      	ldr	r2, [pc, #24]	; (1a90 <system_gclk_chan_enable+0x28>)
-    1a76:	8853      	ldrh	r3, [r2, #2]
-    1a78:	2180      	movs	r1, #128	; 0x80
-    1a7a:	01c9      	lsls	r1, r1, #7
-    1a7c:	430b      	orrs	r3, r1
-    1a7e:	8053      	strh	r3, [r2, #2]
-	cpu_irq_leave_critical();
-    1a80:	4b04      	ldr	r3, [pc, #16]	; (1a94 <system_gclk_chan_enable+0x2c>)
-    1a82:	4798      	blx	r3
-
-	system_interrupt_leave_critical_section();
-}
-    1a84:	bd10      	pop	{r4, pc}
-    1a86:	46c0      	nop			; (mov r8, r8)
-    1a88:	000015e1 	.word	0x000015e1
-    1a8c:	40000c02 	.word	0x40000c02
-    1a90:	40000c00 	.word	0x40000c00
-    1a94:	00001621 	.word	0x00001621
-
-00001a98 <system_gclk_chan_disable>:
- *
- * \param[in] channel  Generic Clock channel to disable
- */
-void system_gclk_chan_disable(
-		const uint8_t channel)
-{
-    1a98:	b510      	push	{r4, lr}
-    1a9a:	0004      	movs	r4, r0
-	cpu_irq_enter_critical();
-    1a9c:	4b0f      	ldr	r3, [pc, #60]	; (1adc <system_gclk_chan_disable+0x44>)
-    1a9e:	4798      	blx	r3
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-    1aa0:	4b0f      	ldr	r3, [pc, #60]	; (1ae0 <system_gclk_chan_disable+0x48>)
-    1aa2:	701c      	strb	r4, [r3, #0]
-
-	/* Sanity check WRTLOCK */
-	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
-
-	/* Switch to known-working source so that the channel can be disabled */
-	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
-    1aa4:	4a0f      	ldr	r2, [pc, #60]	; (1ae4 <system_gclk_chan_disable+0x4c>)
-    1aa6:	8853      	ldrh	r3, [r2, #2]
-    1aa8:	051b      	lsls	r3, r3, #20
-    1aaa:	0f18      	lsrs	r0, r3, #28
-	GCLK->CLKCTRL.bit.GEN = 0;
-    1aac:	8853      	ldrh	r3, [r2, #2]
-    1aae:	490e      	ldr	r1, [pc, #56]	; (1ae8 <system_gclk_chan_disable+0x50>)
-    1ab0:	400b      	ands	r3, r1
-    1ab2:	8053      	strh	r3, [r2, #2]
-
-	/* Disable the generic clock */
-	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
-    1ab4:	8853      	ldrh	r3, [r2, #2]
-    1ab6:	490d      	ldr	r1, [pc, #52]	; (1aec <system_gclk_chan_disable+0x54>)
-    1ab8:	400b      	ands	r3, r1
-    1aba:	8053      	strh	r3, [r2, #2]
-	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
-    1abc:	0011      	movs	r1, r2
-    1abe:	2280      	movs	r2, #128	; 0x80
-    1ac0:	01d2      	lsls	r2, r2, #7
-    1ac2:	884b      	ldrh	r3, [r1, #2]
-    1ac4:	4213      	tst	r3, r2
-    1ac6:	d1fc      	bne.n	1ac2 <system_gclk_chan_disable+0x2a>
-		/* Wait for clock to become disabled */
-	}
-
-	/* Restore previous configured clock generator */
-	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
-    1ac8:	4906      	ldr	r1, [pc, #24]	; (1ae4 <system_gclk_chan_disable+0x4c>)
-    1aca:	884a      	ldrh	r2, [r1, #2]
-    1acc:	0203      	lsls	r3, r0, #8
-    1ace:	4806      	ldr	r0, [pc, #24]	; (1ae8 <system_gclk_chan_disable+0x50>)
-    1ad0:	4002      	ands	r2, r0
-    1ad2:	4313      	orrs	r3, r2
-    1ad4:	804b      	strh	r3, [r1, #2]
-	cpu_irq_leave_critical();
-    1ad6:	4b06      	ldr	r3, [pc, #24]	; (1af0 <system_gclk_chan_disable+0x58>)
-    1ad8:	4798      	blx	r3
-
-	system_interrupt_leave_critical_section();
-}
-    1ada:	bd10      	pop	{r4, pc}
-    1adc:	000015e1 	.word	0x000015e1
-    1ae0:	40000c02 	.word	0x40000c02
-    1ae4:	40000c00 	.word	0x40000c00
-    1ae8:	fffff0ff 	.word	0xfffff0ff
-    1aec:	ffffbfff 	.word	0xffffbfff
-    1af0:	00001621 	.word	0x00001621
-
-00001af4 <system_gclk_chan_set_config>:
-{
-    1af4:	b510      	push	{r4, lr}
-	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
-    1af6:	780c      	ldrb	r4, [r1, #0]
-    1af8:	0224      	lsls	r4, r4, #8
-    1afa:	4304      	orrs	r4, r0
-	system_gclk_chan_disable(channel);
-    1afc:	4b02      	ldr	r3, [pc, #8]	; (1b08 <system_gclk_chan_set_config+0x14>)
-    1afe:	4798      	blx	r3
-	GCLK->CLKCTRL.reg = new_clkctrl_config;
-    1b00:	b2a4      	uxth	r4, r4
-    1b02:	4b02      	ldr	r3, [pc, #8]	; (1b0c <system_gclk_chan_set_config+0x18>)
-    1b04:	805c      	strh	r4, [r3, #2]
-}
-    1b06:	bd10      	pop	{r4, pc}
-    1b08:	00001a99 	.word	0x00001a99
-    1b0c:	40000c00 	.word	0x40000c00
-
-00001b10 <system_gclk_chan_get_hz>:
- *
- * \return The frequency of the generic clock channel, in Hz.
- */
-uint32_t system_gclk_chan_get_hz(
-		const uint8_t channel)
-{
-    1b10:	b510      	push	{r4, lr}
-    1b12:	0004      	movs	r4, r0
-	cpu_irq_enter_critical();
-    1b14:	4b06      	ldr	r3, [pc, #24]	; (1b30 <system_gclk_chan_get_hz+0x20>)
-    1b16:	4798      	blx	r3
-	uint8_t gen_id;
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-    1b18:	4b06      	ldr	r3, [pc, #24]	; (1b34 <system_gclk_chan_get_hz+0x24>)
-    1b1a:	701c      	strb	r4, [r3, #0]
-	gen_id = GCLK->CLKCTRL.bit.GEN;
-    1b1c:	4b06      	ldr	r3, [pc, #24]	; (1b38 <system_gclk_chan_get_hz+0x28>)
-    1b1e:	885c      	ldrh	r4, [r3, #2]
-    1b20:	0524      	lsls	r4, r4, #20
-    1b22:	0f24      	lsrs	r4, r4, #28
-	cpu_irq_leave_critical();
-    1b24:	4b05      	ldr	r3, [pc, #20]	; (1b3c <system_gclk_chan_get_hz+0x2c>)
-    1b26:	4798      	blx	r3
-
-	system_interrupt_leave_critical_section();
-
-	/* Return the clock speed of the associated GCLK generator */
-	return system_gclk_gen_get_hz(gen_id);
-    1b28:	0020      	movs	r0, r4
-    1b2a:	4b05      	ldr	r3, [pc, #20]	; (1b40 <system_gclk_chan_get_hz+0x30>)
-    1b2c:	4798      	blx	r3
-}
-    1b2e:	bd10      	pop	{r4, pc}
-    1b30:	000015e1 	.word	0x000015e1
-    1b34:	40000c02 	.word	0x40000c02
-    1b38:	40000c00 	.word	0x40000c00
-    1b3c:	00001621 	.word	0x00001621
-    1b40:	000019dd 	.word	0x000019dd
-
-00001b44 <_system_pinmux_config>:
- */
-static void _system_pinmux_config(
-		PortGroup *const port,
-		const uint32_t pin_mask,
-		const struct system_pinmux_config *const config)
-{
-    1b44:	b530      	push	{r4, r5, lr}
-
-	/* Track the configuration bits into a temporary variable before writing */
-	uint32_t pin_cfg = 0;
-
-	/* Enabled powersave mode, don't create configuration */
-	if (!config->powersave) {
-    1b46:	78d3      	ldrb	r3, [r2, #3]
-    1b48:	2b00      	cmp	r3, #0
-    1b4a:	d135      	bne.n	1bb8 <_system_pinmux_config+0x74>
-		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
-		 * be written later) and store the new MUX mask */
-		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
-    1b4c:	7813      	ldrb	r3, [r2, #0]
-    1b4e:	2b80      	cmp	r3, #128	; 0x80
-    1b50:	d029      	beq.n	1ba6 <_system_pinmux_config+0x62>
-			pin_cfg |= PORT_WRCONFIG_PMUXEN;
-			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
-    1b52:	061b      	lsls	r3, r3, #24
-    1b54:	2480      	movs	r4, #128	; 0x80
-    1b56:	0264      	lsls	r4, r4, #9
-    1b58:	4323      	orrs	r3, r4
-		}
-
-		/* Check if the user has requested that the input buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
-    1b5a:	7854      	ldrb	r4, [r2, #1]
-    1b5c:	2502      	movs	r5, #2
-    1b5e:	43ac      	bics	r4, r5
-    1b60:	d106      	bne.n	1b70 <_system_pinmux_config+0x2c>
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Enable input buffer flag */
-			pin_cfg |= PORT_WRCONFIG_INEN;
-
-			/* Enable pull-up/pull-down control flag if requested */
-			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
-    1b62:	7894      	ldrb	r4, [r2, #2]
-    1b64:	2c00      	cmp	r4, #0
-    1b66:	d120      	bne.n	1baa <_system_pinmux_config+0x66>
-			pin_cfg |= PORT_WRCONFIG_INEN;
-    1b68:	2480      	movs	r4, #128	; 0x80
-    1b6a:	02a4      	lsls	r4, r4, #10
-    1b6c:	4323      	orrs	r3, r4
-				pin_cfg |= PORT_WRCONFIG_PULLEN;
-			}
-
-			/* Clear the port DIR bits to disable the output buffer */
-			port->DIRCLR.reg = pin_mask;
-    1b6e:	6041      	str	r1, [r0, #4]
-		}
-
-		/* Check if the user has requested that the output buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
-    1b70:	7854      	ldrb	r4, [r2, #1]
-    1b72:	3c01      	subs	r4, #1
-    1b74:	2c01      	cmp	r4, #1
-    1b76:	d91c      	bls.n	1bb2 <_system_pinmux_config+0x6e>
-		port->DIRCLR.reg = pin_mask;
-	}
-
-	/* The Write Configuration register (WRCONFIG) requires the
-	 * pins to to grouped into two 16-bit half-words - split them out here */
-	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
-    1b78:	040d      	lsls	r5, r1, #16
-    1b7a:	0c2d      	lsrs	r5, r5, #16
-
-	/* Configure the lower 16-bits of the port to the desired configuration,
-	 * including the pin peripheral multiplexer just in case it is enabled */
-	port->WRCONFIG.reg
-		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
-    1b7c:	24a0      	movs	r4, #160	; 0xa0
-    1b7e:	05e4      	lsls	r4, r4, #23
-    1b80:	432c      	orrs	r4, r5
-    1b82:	431c      	orrs	r4, r3
-		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-    1b84:	6284      	str	r4, [r0, #40]	; 0x28
-	uint32_t upper_pin_mask = (pin_mask >> 16);
-    1b86:	0c0d      	lsrs	r5, r1, #16
-
-	/* Configure the upper 16-bits of the port to the desired configuration,
-	 * including the pin peripheral multiplexer just in case it is enabled */
-	port->WRCONFIG.reg
-		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
-    1b88:	24d0      	movs	r4, #208	; 0xd0
-    1b8a:	0624      	lsls	r4, r4, #24
-    1b8c:	432c      	orrs	r4, r5
-    1b8e:	431c      	orrs	r4, r3
-		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-    1b90:	6284      	str	r4, [r0, #40]	; 0x28
-			PORT_WRCONFIG_HWSEL;
-
-	if(!config->powersave) {
-    1b92:	78d4      	ldrb	r4, [r2, #3]
-    1b94:	2c00      	cmp	r4, #0
-    1b96:	d122      	bne.n	1bde <_system_pinmux_config+0x9a>
-		/* Set the pull-up state once the port pins are configured if one was
-		 * requested and it does not violate the valid set of port
-		 * configurations */
-		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
-    1b98:	035b      	lsls	r3, r3, #13
-    1b9a:	d51c      	bpl.n	1bd6 <_system_pinmux_config+0x92>
-			/* Set the OUT register bits to enable the pull-up if requested,
-			 * clear to enable pull-down */
-			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
-    1b9c:	7893      	ldrb	r3, [r2, #2]
-    1b9e:	2b01      	cmp	r3, #1
-    1ba0:	d01e      	beq.n	1be0 <_system_pinmux_config+0x9c>
-				port->OUTSET.reg = pin_mask;
-			} else {
-				port->OUTCLR.reg = pin_mask;
-    1ba2:	6141      	str	r1, [r0, #20]
-    1ba4:	e017      	b.n	1bd6 <_system_pinmux_config+0x92>
-	uint32_t pin_cfg = 0;
-    1ba6:	2300      	movs	r3, #0
-    1ba8:	e7d7      	b.n	1b5a <_system_pinmux_config+0x16>
-				pin_cfg |= PORT_WRCONFIG_PULLEN;
-    1baa:	24c0      	movs	r4, #192	; 0xc0
-    1bac:	02e4      	lsls	r4, r4, #11
-    1bae:	4323      	orrs	r3, r4
-    1bb0:	e7dd      	b.n	1b6e <_system_pinmux_config+0x2a>
-			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
-    1bb2:	4c0d      	ldr	r4, [pc, #52]	; (1be8 <_system_pinmux_config+0xa4>)
-    1bb4:	4023      	ands	r3, r4
-    1bb6:	e7df      	b.n	1b78 <_system_pinmux_config+0x34>
-		port->DIRCLR.reg = pin_mask;
-    1bb8:	6041      	str	r1, [r0, #4]
-	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
-    1bba:	040c      	lsls	r4, r1, #16
-    1bbc:	0c24      	lsrs	r4, r4, #16
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
-    1bbe:	23a0      	movs	r3, #160	; 0xa0
-    1bc0:	05db      	lsls	r3, r3, #23
-    1bc2:	4323      	orrs	r3, r4
-		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-    1bc4:	6283      	str	r3, [r0, #40]	; 0x28
-	uint32_t upper_pin_mask = (pin_mask >> 16);
-    1bc6:	0c0c      	lsrs	r4, r1, #16
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
-    1bc8:	23d0      	movs	r3, #208	; 0xd0
-    1bca:	061b      	lsls	r3, r3, #24
-    1bcc:	4323      	orrs	r3, r4
-		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-    1bce:	6283      	str	r3, [r0, #40]	; 0x28
-	if(!config->powersave) {
-    1bd0:	78d3      	ldrb	r3, [r2, #3]
-    1bd2:	2b00      	cmp	r3, #0
-    1bd4:	d103      	bne.n	1bde <_system_pinmux_config+0x9a>
-			}
-		}
-
-		/* Check if the user has requested that the output buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
-    1bd6:	7853      	ldrb	r3, [r2, #1]
-    1bd8:	3b01      	subs	r3, #1
-    1bda:	2b01      	cmp	r3, #1
-    1bdc:	d902      	bls.n	1be4 <_system_pinmux_config+0xa0>
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Set the port DIR bits to enable the output buffer */
-			port->DIRSET.reg = pin_mask;
-		}
-	}
-}
-    1bde:	bd30      	pop	{r4, r5, pc}
-				port->OUTSET.reg = pin_mask;
-    1be0:	6181      	str	r1, [r0, #24]
-    1be2:	e7f8      	b.n	1bd6 <_system_pinmux_config+0x92>
-			port->DIRSET.reg = pin_mask;
-    1be4:	6081      	str	r1, [r0, #8]
-}
-    1be6:	e7fa      	b.n	1bde <_system_pinmux_config+0x9a>
-    1be8:	fffbffff 	.word	0xfffbffff
-
-00001bec <system_pinmux_pin_set_config>:
- * \param[in] config    Configuration settings for the pin
- */
-void system_pinmux_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct system_pinmux_config *const config)
-{
-    1bec:	b510      	push	{r4, lr}
-    1bee:	000a      	movs	r2, r1
-	uint8_t group_index = (gpio_pin / 32);
-
-	/* Array of available ports */
-	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
-
-	if (port_index < PORT_INST_NUM) {
-    1bf0:	09c1      	lsrs	r1, r0, #7
-		return &(ports[port_index]->Group[group_index]);
-	} else {
-		Assert(false);
-		return NULL;
-    1bf2:	2300      	movs	r3, #0
-	if (port_index < PORT_INST_NUM) {
-    1bf4:	2900      	cmp	r1, #0
-    1bf6:	d104      	bne.n	1c02 <system_pinmux_pin_set_config+0x16>
-		return &(ports[port_index]->Group[group_index]);
-    1bf8:	0943      	lsrs	r3, r0, #5
-    1bfa:	01db      	lsls	r3, r3, #7
-    1bfc:	4905      	ldr	r1, [pc, #20]	; (1c14 <system_pinmux_pin_set_config+0x28>)
-    1bfe:	468c      	mov	ip, r1
-    1c00:	4463      	add	r3, ip
-	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask = (1UL << (gpio_pin % 32));
-    1c02:	241f      	movs	r4, #31
-    1c04:	4020      	ands	r0, r4
-    1c06:	2101      	movs	r1, #1
-    1c08:	4081      	lsls	r1, r0
-
-	_system_pinmux_config(port, pin_mask, config);
-    1c0a:	0018      	movs	r0, r3
-    1c0c:	4b02      	ldr	r3, [pc, #8]	; (1c18 <system_pinmux_pin_set_config+0x2c>)
-    1c0e:	4798      	blx	r3
-}
-    1c10:	bd10      	pop	{r4, pc}
-    1c12:	46c0      	nop			; (mov r8, r8)
-    1c14:	41004400 	.word	0x41004400
-    1c18:	00001b45 	.word	0x00001b45
-
-00001c1c <_system_dummy_init>:
- */
-void _system_dummy_init(void);
-void _system_dummy_init(void)
-{
-	return;
-}
-    1c1c:	4770      	bx	lr
-	...
-
-00001c20 <system_init>:
- *  - Board hardware initialization (via the Board module)
- *  - Event system driver initialization (via the EVSYS module)
- *  - External Interrupt driver initialization (via the EXTINT module)
- */
-void system_init(void)
-{
-    1c20:	b510      	push	{r4, lr}
-	/* Configure GCLK and clock sources according to conf_clocks.h */
-	system_clock_init();
-    1c22:	4b05      	ldr	r3, [pc, #20]	; (1c38 <system_init+0x18>)
-    1c24:	4798      	blx	r3
-
-	/* Initialize board hardware */
-	system_board_init();
-    1c26:	4b05      	ldr	r3, [pc, #20]	; (1c3c <system_init+0x1c>)
-    1c28:	4798      	blx	r3
-
-	/* Initialize EVSYS hardware */
-	_system_events_init();
-    1c2a:	4b05      	ldr	r3, [pc, #20]	; (1c40 <system_init+0x20>)
-    1c2c:	4798      	blx	r3
-
-	/* Initialize External hardware */
-	_system_extint_init();
-    1c2e:	4b05      	ldr	r3, [pc, #20]	; (1c44 <system_init+0x24>)
-    1c30:	4798      	blx	r3
-	
-	/* Initialize DIVAS hardware */
-	_system_divas_init();
-    1c32:	4b05      	ldr	r3, [pc, #20]	; (1c48 <system_init+0x28>)
-    1c34:	4798      	blx	r3
-}
-    1c36:	bd10      	pop	{r4, pc}
-    1c38:	00001825 	.word	0x00001825
-    1c3c:	00001651 	.word	0x00001651
-    1c40:	00001c1d 	.word	0x00001c1d
-    1c44:	00001c1d 	.word	0x00001c1d
-    1c48:	00001c1d 	.word	0x00001c1d
-
-00001c4c <Dummy_Handler>:
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Dummy_Handler(void)
-{
-    1c4c:	e7fe      	b.n	1c4c <Dummy_Handler>
-	...
-
-00001c50 <Reset_Handler>:
-{
-    1c50:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-        if (pSrc != pDest) {
-    1c52:	4a2a      	ldr	r2, [pc, #168]	; (1cfc <Reset_Handler+0xac>)
-    1c54:	4b2a      	ldr	r3, [pc, #168]	; (1d00 <Reset_Handler+0xb0>)
-    1c56:	429a      	cmp	r2, r3
-    1c58:	d011      	beq.n	1c7e <Reset_Handler+0x2e>
-                for (; pDest < &_erelocate;) {
-    1c5a:	001a      	movs	r2, r3
-    1c5c:	4b29      	ldr	r3, [pc, #164]	; (1d04 <Reset_Handler+0xb4>)
-    1c5e:	429a      	cmp	r2, r3
-    1c60:	d20d      	bcs.n	1c7e <Reset_Handler+0x2e>
-    1c62:	4a29      	ldr	r2, [pc, #164]	; (1d08 <Reset_Handler+0xb8>)
-    1c64:	3303      	adds	r3, #3
-    1c66:	1a9b      	subs	r3, r3, r2
-    1c68:	089b      	lsrs	r3, r3, #2
-    1c6a:	3301      	adds	r3, #1
-    1c6c:	009b      	lsls	r3, r3, #2
-    1c6e:	2200      	movs	r2, #0
-                        *pDest++ = *pSrc++;
-    1c70:	4823      	ldr	r0, [pc, #140]	; (1d00 <Reset_Handler+0xb0>)
-    1c72:	4922      	ldr	r1, [pc, #136]	; (1cfc <Reset_Handler+0xac>)
-    1c74:	588c      	ldr	r4, [r1, r2]
-    1c76:	5084      	str	r4, [r0, r2]
-    1c78:	3204      	adds	r2, #4
-                for (; pDest < &_erelocate;) {
-    1c7a:	429a      	cmp	r2, r3
-    1c7c:	d1fa      	bne.n	1c74 <Reset_Handler+0x24>
-        for (pDest = &_szero; pDest < &_ezero;) {
-    1c7e:	4a23      	ldr	r2, [pc, #140]	; (1d0c <Reset_Handler+0xbc>)
-    1c80:	4b23      	ldr	r3, [pc, #140]	; (1d10 <Reset_Handler+0xc0>)
-    1c82:	429a      	cmp	r2, r3
-    1c84:	d20a      	bcs.n	1c9c <Reset_Handler+0x4c>
-    1c86:	43d3      	mvns	r3, r2
-    1c88:	4921      	ldr	r1, [pc, #132]	; (1d10 <Reset_Handler+0xc0>)
-    1c8a:	185b      	adds	r3, r3, r1
-    1c8c:	2103      	movs	r1, #3
-    1c8e:	438b      	bics	r3, r1
-    1c90:	3304      	adds	r3, #4
-    1c92:	189b      	adds	r3, r3, r2
-                *pDest++ = 0;
-    1c94:	2100      	movs	r1, #0
-    1c96:	c202      	stmia	r2!, {r1}
-        for (pDest = &_szero; pDest < &_ezero;) {
-    1c98:	4293      	cmp	r3, r2
-    1c9a:	d1fc      	bne.n	1c96 <Reset_Handler+0x46>
-        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
-    1c9c:	4a1d      	ldr	r2, [pc, #116]	; (1d14 <Reset_Handler+0xc4>)
-    1c9e:	21ff      	movs	r1, #255	; 0xff
-    1ca0:	4b1d      	ldr	r3, [pc, #116]	; (1d18 <Reset_Handler+0xc8>)
-    1ca2:	438b      	bics	r3, r1
-    1ca4:	6093      	str	r3, [r2, #8]
-        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
-    1ca6:	39fd      	subs	r1, #253	; 0xfd
-    1ca8:	2390      	movs	r3, #144	; 0x90
-    1caa:	005b      	lsls	r3, r3, #1
-    1cac:	4a1b      	ldr	r2, [pc, #108]	; (1d1c <Reset_Handler+0xcc>)
-    1cae:	50d1      	str	r1, [r2, r3]
-        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
-    1cb0:	4a1b      	ldr	r2, [pc, #108]	; (1d20 <Reset_Handler+0xd0>)
-    1cb2:	78d3      	ldrb	r3, [r2, #3]
-    1cb4:	2503      	movs	r5, #3
-    1cb6:	43ab      	bics	r3, r5
-    1cb8:	2402      	movs	r4, #2
-    1cba:	4323      	orrs	r3, r4
-    1cbc:	70d3      	strb	r3, [r2, #3]
-        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
-    1cbe:	78d3      	ldrb	r3, [r2, #3]
-    1cc0:	270c      	movs	r7, #12
-    1cc2:	43bb      	bics	r3, r7
-    1cc4:	2608      	movs	r6, #8
-    1cc6:	4333      	orrs	r3, r6
-    1cc8:	70d3      	strb	r3, [r2, #3]
-        DMAC->QOSCTRL.bit.DQOS = 2;
-    1cca:	4b16      	ldr	r3, [pc, #88]	; (1d24 <Reset_Handler+0xd4>)
-    1ccc:	7b98      	ldrb	r0, [r3, #14]
-    1cce:	2230      	movs	r2, #48	; 0x30
-    1cd0:	4390      	bics	r0, r2
-    1cd2:	2220      	movs	r2, #32
-    1cd4:	4310      	orrs	r0, r2
-    1cd6:	7398      	strb	r0, [r3, #14]
-        DMAC->QOSCTRL.bit.FQOS = 2;
-    1cd8:	7b99      	ldrb	r1, [r3, #14]
-    1cda:	43b9      	bics	r1, r7
-    1cdc:	4331      	orrs	r1, r6
-    1cde:	7399      	strb	r1, [r3, #14]
-        DMAC->QOSCTRL.bit.WRBQOS = 2;
-    1ce0:	7b9a      	ldrb	r2, [r3, #14]
-    1ce2:	43aa      	bics	r2, r5
-    1ce4:	4322      	orrs	r2, r4
-    1ce6:	739a      	strb	r2, [r3, #14]
-        NVMCTRL->CTRLB.bit.MANW = 1;
-    1ce8:	4a0f      	ldr	r2, [pc, #60]	; (1d28 <Reset_Handler+0xd8>)
-    1cea:	6853      	ldr	r3, [r2, #4]
-    1cec:	2180      	movs	r1, #128	; 0x80
-    1cee:	430b      	orrs	r3, r1
-    1cf0:	6053      	str	r3, [r2, #4]
-        __libc_init_array();
-    1cf2:	4b0e      	ldr	r3, [pc, #56]	; (1d2c <Reset_Handler+0xdc>)
-    1cf4:	4798      	blx	r3
-        main();
-    1cf6:	4b0e      	ldr	r3, [pc, #56]	; (1d30 <Reset_Handler+0xe0>)
-    1cf8:	4798      	blx	r3
-    1cfa:	e7fe      	b.n	1cfa <Reset_Handler+0xaa>
-    1cfc:	00003960 	.word	0x00003960
-    1d00:	20000000 	.word	0x20000000
-    1d04:	2000007c 	.word	0x2000007c
-    1d08:	20000004 	.word	0x20000004
-    1d0c:	20000080 	.word	0x20000080
-    1d10:	200002a0 	.word	0x200002a0
-    1d14:	e000ed00 	.word	0xe000ed00
-    1d18:	00000000 	.word	0x00000000
-    1d1c:	41007000 	.word	0x41007000
-    1d20:	41005000 	.word	0x41005000
-    1d24:	41004800 	.word	0x41004800
-    1d28:	41004000 	.word	0x41004000
-    1d2c:	00002681 	.word	0x00002681
-    1d30:	00001d71 	.word	0x00001d71
-
-00001d34 <_sbrk>:
-extern void _exit(int status);
-extern void _kill(int pid, int sig);
-extern int _getpid(void);
-
-extern caddr_t _sbrk(int incr)
-{
-    1d34:	0003      	movs	r3, r0
-	static unsigned char *heap = NULL;
-	unsigned char *prev_heap;
-
-	if (heap == NULL) {
-    1d36:	4a06      	ldr	r2, [pc, #24]	; (1d50 <_sbrk+0x1c>)
-    1d38:	6812      	ldr	r2, [r2, #0]
-    1d3a:	2a00      	cmp	r2, #0
-    1d3c:	d004      	beq.n	1d48 <_sbrk+0x14>
-		heap = (unsigned char *)&_end;
-	}
-	prev_heap = heap;
-    1d3e:	4a04      	ldr	r2, [pc, #16]	; (1d50 <_sbrk+0x1c>)
-    1d40:	6810      	ldr	r0, [r2, #0]
-
-	heap += incr;
-    1d42:	18c3      	adds	r3, r0, r3
-    1d44:	6013      	str	r3, [r2, #0]
-
-	return (caddr_t) prev_heap;
-}
-    1d46:	4770      	bx	lr
-		heap = (unsigned char *)&_end;
-    1d48:	4902      	ldr	r1, [pc, #8]	; (1d54 <_sbrk+0x20>)
-    1d4a:	4a01      	ldr	r2, [pc, #4]	; (1d50 <_sbrk+0x1c>)
-    1d4c:	6011      	str	r1, [r2, #0]
-    1d4e:	e7f6      	b.n	1d3e <_sbrk+0xa>
-    1d50:	200001cc 	.word	0x200001cc
-    1d54:	200022a0 	.word	0x200022a0
-
-00001d58 <_close>:
-}
-
-extern int _close(int file)
-{
-	return -1;
-}
-    1d58:	2001      	movs	r0, #1
-    1d5a:	4240      	negs	r0, r0
-    1d5c:	4770      	bx	lr
-
-00001d5e <_fstat>:
-
-extern int _fstat(int file, struct stat *st)
-{
-	st->st_mode = S_IFCHR;
-    1d5e:	2380      	movs	r3, #128	; 0x80
-    1d60:	019b      	lsls	r3, r3, #6
-    1d62:	604b      	str	r3, [r1, #4]
-
-	return 0;
-}
-    1d64:	2000      	movs	r0, #0
-    1d66:	4770      	bx	lr
-
-00001d68 <_isatty>:
-
-extern int _isatty(int file)
-{
-	return 1;
-}
-    1d68:	2001      	movs	r0, #1
-    1d6a:	4770      	bx	lr
-
-00001d6c <_lseek>:
-
-extern int _lseek(int file, int ptr, int dir)
-{
-	return 0;
-}
-    1d6c:	2000      	movs	r0, #0
-    1d6e:	4770      	bx	lr
-
-00001d70 <main>:
- */
-#include <asf.h>
-#include "pusart.h"
-#include "padc.h"
-int main (void)
-{
-    1d70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-	system_init();
-    1d72:	4b12      	ldr	r3, [pc, #72]	; (1dbc <main+0x4c>)
-    1d74:	4798      	blx	r3
-	delay_init();
-    1d76:	4b12      	ldr	r3, [pc, #72]	; (1dc0 <main+0x50>)
-    1d78:	4798      	blx	r3
-	
-	pusart_init();
-    1d7a:	4b12      	ldr	r3, [pc, #72]	; (1dc4 <main+0x54>)
-    1d7c:	4798      	blx	r3
-	padc_init();
-    1d7e:	4b12      	ldr	r3, [pc, #72]	; (1dc8 <main+0x58>)
-    1d80:	4798      	blx	r3
-	padc_start();
-    1d82:	4b12      	ldr	r3, [pc, #72]	; (1dcc <main+0x5c>)
-    1d84:	4798      	blx	r3
-	
-	for (;;)
-	{
-		float voltage = padc_get_voltage();
-    1d86:	4f12      	ldr	r7, [pc, #72]	; (1dd0 <main+0x60>)
-		printf("Voltage: %d.%03d\r\n", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
-    1d88:	4e12      	ldr	r6, [pc, #72]	; (1dd4 <main+0x64>)
-		float voltage = padc_get_voltage();
-    1d8a:	47b8      	blx	r7
-    1d8c:	1c05      	adds	r5, r0, #0
-		printf("Voltage: %d.%03d\r\n", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
-    1d8e:	47b0      	blx	r6
-    1d90:	0004      	movs	r4, r0
-    1d92:	4b11      	ldr	r3, [pc, #68]	; (1dd8 <main+0x68>)
-    1d94:	4798      	blx	r3
-    1d96:	1c01      	adds	r1, r0, #0
-    1d98:	1c28      	adds	r0, r5, #0
-    1d9a:	4b10      	ldr	r3, [pc, #64]	; (1ddc <main+0x6c>)
-    1d9c:	4798      	blx	r3
-    1d9e:	4910      	ldr	r1, [pc, #64]	; (1de0 <main+0x70>)
-    1da0:	4b10      	ldr	r3, [pc, #64]	; (1de4 <main+0x74>)
-    1da2:	4798      	blx	r3
-    1da4:	47b0      	blx	r6
-    1da6:	0002      	movs	r2, r0
-    1da8:	0021      	movs	r1, r4
-    1daa:	480f      	ldr	r0, [pc, #60]	; (1de8 <main+0x78>)
-    1dac:	4b0f      	ldr	r3, [pc, #60]	; (1dec <main+0x7c>)
-    1dae:	4798      	blx	r3
-		delay_ms(500);
-    1db0:	20fa      	movs	r0, #250	; 0xfa
-    1db2:	0040      	lsls	r0, r0, #1
-    1db4:	4b0e      	ldr	r3, [pc, #56]	; (1df0 <main+0x80>)
-    1db6:	4798      	blx	r3
-    1db8:	e7e7      	b.n	1d8a <main+0x1a>
-    1dba:	46c0      	nop			; (mov r8, r8)
-    1dbc:	00001c21 	.word	0x00001c21
-    1dc0:	00001575 	.word	0x00001575
-    1dc4:	00000e55 	.word	0x00000e55
-    1dc8:	00000cb9 	.word	0x00000cb9
-    1dcc:	00000d99 	.word	0x00000d99
-    1dd0:	00000de9 	.word	0x00000de9
-    1dd4:	000024d9 	.word	0x000024d9
-    1dd8:	00002519 	.word	0x00002519
-    1ddc:	000021a1 	.word	0x000021a1
-    1de0:	447a0000 	.word	0x447a0000
-    1de4:	00001f61 	.word	0x00001f61
-    1de8:	00003854 	.word	0x00003854
-    1dec:	000026ed 	.word	0x000026ed
-    1df0:	000015b5 	.word	0x000015b5
-
-00001df4 <__udivsi3>:
-    1df4:	2200      	movs	r2, #0
-    1df6:	0843      	lsrs	r3, r0, #1
-    1df8:	428b      	cmp	r3, r1
-    1dfa:	d374      	bcc.n	1ee6 <__udivsi3+0xf2>
-    1dfc:	0903      	lsrs	r3, r0, #4
-    1dfe:	428b      	cmp	r3, r1
-    1e00:	d35f      	bcc.n	1ec2 <__udivsi3+0xce>
-    1e02:	0a03      	lsrs	r3, r0, #8
-    1e04:	428b      	cmp	r3, r1
-    1e06:	d344      	bcc.n	1e92 <__udivsi3+0x9e>
-    1e08:	0b03      	lsrs	r3, r0, #12
-    1e0a:	428b      	cmp	r3, r1
-    1e0c:	d328      	bcc.n	1e60 <__udivsi3+0x6c>
-    1e0e:	0c03      	lsrs	r3, r0, #16
-    1e10:	428b      	cmp	r3, r1
-    1e12:	d30d      	bcc.n	1e30 <__udivsi3+0x3c>
-    1e14:	22ff      	movs	r2, #255	; 0xff
-    1e16:	0209      	lsls	r1, r1, #8
-    1e18:	ba12      	rev	r2, r2
-    1e1a:	0c03      	lsrs	r3, r0, #16
-    1e1c:	428b      	cmp	r3, r1
-    1e1e:	d302      	bcc.n	1e26 <__udivsi3+0x32>
-    1e20:	1212      	asrs	r2, r2, #8
-    1e22:	0209      	lsls	r1, r1, #8
-    1e24:	d065      	beq.n	1ef2 <__udivsi3+0xfe>
-    1e26:	0b03      	lsrs	r3, r0, #12
-    1e28:	428b      	cmp	r3, r1
-    1e2a:	d319      	bcc.n	1e60 <__udivsi3+0x6c>
-    1e2c:	e000      	b.n	1e30 <__udivsi3+0x3c>
-    1e2e:	0a09      	lsrs	r1, r1, #8
-    1e30:	0bc3      	lsrs	r3, r0, #15
-    1e32:	428b      	cmp	r3, r1
-    1e34:	d301      	bcc.n	1e3a <__udivsi3+0x46>
-    1e36:	03cb      	lsls	r3, r1, #15
-    1e38:	1ac0      	subs	r0, r0, r3
-    1e3a:	4152      	adcs	r2, r2
-    1e3c:	0b83      	lsrs	r3, r0, #14
-    1e3e:	428b      	cmp	r3, r1
-    1e40:	d301      	bcc.n	1e46 <__udivsi3+0x52>
-    1e42:	038b      	lsls	r3, r1, #14
-    1e44:	1ac0      	subs	r0, r0, r3
-    1e46:	4152      	adcs	r2, r2
-    1e48:	0b43      	lsrs	r3, r0, #13
-    1e4a:	428b      	cmp	r3, r1
-    1e4c:	d301      	bcc.n	1e52 <__udivsi3+0x5e>
-    1e4e:	034b      	lsls	r3, r1, #13
-    1e50:	1ac0      	subs	r0, r0, r3
-    1e52:	4152      	adcs	r2, r2
-    1e54:	0b03      	lsrs	r3, r0, #12
-    1e56:	428b      	cmp	r3, r1
-    1e58:	d301      	bcc.n	1e5e <__udivsi3+0x6a>
-    1e5a:	030b      	lsls	r3, r1, #12
-    1e5c:	1ac0      	subs	r0, r0, r3
-    1e5e:	4152      	adcs	r2, r2
-    1e60:	0ac3      	lsrs	r3, r0, #11
-    1e62:	428b      	cmp	r3, r1
-    1e64:	d301      	bcc.n	1e6a <__udivsi3+0x76>
-    1e66:	02cb      	lsls	r3, r1, #11
-    1e68:	1ac0      	subs	r0, r0, r3
-    1e6a:	4152      	adcs	r2, r2
-    1e6c:	0a83      	lsrs	r3, r0, #10
-    1e6e:	428b      	cmp	r3, r1
-    1e70:	d301      	bcc.n	1e76 <__udivsi3+0x82>
-    1e72:	028b      	lsls	r3, r1, #10
-    1e74:	1ac0      	subs	r0, r0, r3
-    1e76:	4152      	adcs	r2, r2
-    1e78:	0a43      	lsrs	r3, r0, #9
-    1e7a:	428b      	cmp	r3, r1
-    1e7c:	d301      	bcc.n	1e82 <__udivsi3+0x8e>
-    1e7e:	024b      	lsls	r3, r1, #9
-    1e80:	1ac0      	subs	r0, r0, r3
-    1e82:	4152      	adcs	r2, r2
-    1e84:	0a03      	lsrs	r3, r0, #8
-    1e86:	428b      	cmp	r3, r1
-    1e88:	d301      	bcc.n	1e8e <__udivsi3+0x9a>
-    1e8a:	020b      	lsls	r3, r1, #8
-    1e8c:	1ac0      	subs	r0, r0, r3
-    1e8e:	4152      	adcs	r2, r2
-    1e90:	d2cd      	bcs.n	1e2e <__udivsi3+0x3a>
-    1e92:	09c3      	lsrs	r3, r0, #7
-    1e94:	428b      	cmp	r3, r1
-    1e96:	d301      	bcc.n	1e9c <__udivsi3+0xa8>
-    1e98:	01cb      	lsls	r3, r1, #7
-    1e9a:	1ac0      	subs	r0, r0, r3
-    1e9c:	4152      	adcs	r2, r2
-    1e9e:	0983      	lsrs	r3, r0, #6
-    1ea0:	428b      	cmp	r3, r1
-    1ea2:	d301      	bcc.n	1ea8 <__udivsi3+0xb4>
-    1ea4:	018b      	lsls	r3, r1, #6
-    1ea6:	1ac0      	subs	r0, r0, r3
-    1ea8:	4152      	adcs	r2, r2
-    1eaa:	0943      	lsrs	r3, r0, #5
-    1eac:	428b      	cmp	r3, r1
-    1eae:	d301      	bcc.n	1eb4 <__udivsi3+0xc0>
-    1eb0:	014b      	lsls	r3, r1, #5
-    1eb2:	1ac0      	subs	r0, r0, r3
-    1eb4:	4152      	adcs	r2, r2
-    1eb6:	0903      	lsrs	r3, r0, #4
-    1eb8:	428b      	cmp	r3, r1
-    1eba:	d301      	bcc.n	1ec0 <__udivsi3+0xcc>
-    1ebc:	010b      	lsls	r3, r1, #4
-    1ebe:	1ac0      	subs	r0, r0, r3
-    1ec0:	4152      	adcs	r2, r2
-    1ec2:	08c3      	lsrs	r3, r0, #3
-    1ec4:	428b      	cmp	r3, r1
-    1ec6:	d301      	bcc.n	1ecc <__udivsi3+0xd8>
-    1ec8:	00cb      	lsls	r3, r1, #3
-    1eca:	1ac0      	subs	r0, r0, r3
-    1ecc:	4152      	adcs	r2, r2
-    1ece:	0883      	lsrs	r3, r0, #2
-    1ed0:	428b      	cmp	r3, r1
-    1ed2:	d301      	bcc.n	1ed8 <__udivsi3+0xe4>
-    1ed4:	008b      	lsls	r3, r1, #2
-    1ed6:	1ac0      	subs	r0, r0, r3
-    1ed8:	4152      	adcs	r2, r2
-    1eda:	0843      	lsrs	r3, r0, #1
-    1edc:	428b      	cmp	r3, r1
-    1ede:	d301      	bcc.n	1ee4 <__udivsi3+0xf0>
-    1ee0:	004b      	lsls	r3, r1, #1
-    1ee2:	1ac0      	subs	r0, r0, r3
-    1ee4:	4152      	adcs	r2, r2
-    1ee6:	1a41      	subs	r1, r0, r1
-    1ee8:	d200      	bcs.n	1eec <__udivsi3+0xf8>
-    1eea:	4601      	mov	r1, r0
-    1eec:	4152      	adcs	r2, r2
-    1eee:	4610      	mov	r0, r2
-    1ef0:	4770      	bx	lr
-    1ef2:	e7ff      	b.n	1ef4 <__udivsi3+0x100>
-    1ef4:	b501      	push	{r0, lr}
-    1ef6:	2000      	movs	r0, #0
-    1ef8:	f000 f806 	bl	1f08 <__aeabi_idiv0>
-    1efc:	bd02      	pop	{r1, pc}
-    1efe:	46c0      	nop			; (mov r8, r8)
-
-00001f00 <__aeabi_uidivmod>:
-    1f00:	2900      	cmp	r1, #0
-    1f02:	d0f7      	beq.n	1ef4 <__udivsi3+0x100>
-    1f04:	e776      	b.n	1df4 <__udivsi3>
-    1f06:	4770      	bx	lr
-
-00001f08 <__aeabi_idiv0>:
-    1f08:	4770      	bx	lr
-    1f0a:	46c0      	nop			; (mov r8, r8)
-
-00001f0c <__aeabi_lmul>:
-    1f0c:	b5f0      	push	{r4, r5, r6, r7, lr}
-    1f0e:	46ce      	mov	lr, r9
-    1f10:	4647      	mov	r7, r8
-    1f12:	0415      	lsls	r5, r2, #16
-    1f14:	0c2d      	lsrs	r5, r5, #16
-    1f16:	002e      	movs	r6, r5
-    1f18:	b580      	push	{r7, lr}
-    1f1a:	0407      	lsls	r7, r0, #16
-    1f1c:	0c14      	lsrs	r4, r2, #16
-    1f1e:	0c3f      	lsrs	r7, r7, #16
-    1f20:	4699      	mov	r9, r3
-    1f22:	0c03      	lsrs	r3, r0, #16
-    1f24:	437e      	muls	r6, r7
-    1f26:	435d      	muls	r5, r3
-    1f28:	4367      	muls	r7, r4
-    1f2a:	4363      	muls	r3, r4
-    1f2c:	197f      	adds	r7, r7, r5
-    1f2e:	0c34      	lsrs	r4, r6, #16
-    1f30:	19e4      	adds	r4, r4, r7
-    1f32:	469c      	mov	ip, r3
-    1f34:	42a5      	cmp	r5, r4
-    1f36:	d903      	bls.n	1f40 <__aeabi_lmul+0x34>
-    1f38:	2380      	movs	r3, #128	; 0x80
-    1f3a:	025b      	lsls	r3, r3, #9
-    1f3c:	4698      	mov	r8, r3
-    1f3e:	44c4      	add	ip, r8
-    1f40:	464b      	mov	r3, r9
-    1f42:	4351      	muls	r1, r2
-    1f44:	4343      	muls	r3, r0
-    1f46:	0436      	lsls	r6, r6, #16
-    1f48:	0c36      	lsrs	r6, r6, #16
-    1f4a:	0c25      	lsrs	r5, r4, #16
-    1f4c:	0424      	lsls	r4, r4, #16
-    1f4e:	4465      	add	r5, ip
-    1f50:	19a4      	adds	r4, r4, r6
-    1f52:	1859      	adds	r1, r3, r1
-    1f54:	1949      	adds	r1, r1, r5
-    1f56:	0020      	movs	r0, r4
-    1f58:	bc0c      	pop	{r2, r3}
-    1f5a:	4690      	mov	r8, r2
-    1f5c:	4699      	mov	r9, r3
-    1f5e:	bdf0      	pop	{r4, r5, r6, r7, pc}
-
-00001f60 <__aeabi_fmul>:
-    1f60:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    1f62:	4657      	mov	r7, sl
-    1f64:	464e      	mov	r6, r9
-    1f66:	4645      	mov	r5, r8
-    1f68:	46de      	mov	lr, fp
-    1f6a:	b5e0      	push	{r5, r6, r7, lr}
-    1f6c:	0247      	lsls	r7, r0, #9
-    1f6e:	0046      	lsls	r6, r0, #1
-    1f70:	4688      	mov	r8, r1
-    1f72:	0a7f      	lsrs	r7, r7, #9
-    1f74:	0e36      	lsrs	r6, r6, #24
-    1f76:	0fc4      	lsrs	r4, r0, #31
-    1f78:	2e00      	cmp	r6, #0
-    1f7a:	d047      	beq.n	200c <STACK_SIZE+0xc>
-    1f7c:	2eff      	cmp	r6, #255	; 0xff
-    1f7e:	d024      	beq.n	1fca <__aeabi_fmul+0x6a>
-    1f80:	00fb      	lsls	r3, r7, #3
-    1f82:	2780      	movs	r7, #128	; 0x80
-    1f84:	04ff      	lsls	r7, r7, #19
-    1f86:	431f      	orrs	r7, r3
-    1f88:	2300      	movs	r3, #0
-    1f8a:	4699      	mov	r9, r3
-    1f8c:	469a      	mov	sl, r3
-    1f8e:	3e7f      	subs	r6, #127	; 0x7f
-    1f90:	4643      	mov	r3, r8
-    1f92:	025d      	lsls	r5, r3, #9
-    1f94:	0058      	lsls	r0, r3, #1
-    1f96:	0fdb      	lsrs	r3, r3, #31
-    1f98:	0a6d      	lsrs	r5, r5, #9
-    1f9a:	0e00      	lsrs	r0, r0, #24
-    1f9c:	4698      	mov	r8, r3
-    1f9e:	d043      	beq.n	2028 <STACK_SIZE+0x28>
-    1fa0:	28ff      	cmp	r0, #255	; 0xff
-    1fa2:	d03b      	beq.n	201c <STACK_SIZE+0x1c>
-    1fa4:	00eb      	lsls	r3, r5, #3
-    1fa6:	2580      	movs	r5, #128	; 0x80
-    1fa8:	2200      	movs	r2, #0
-    1faa:	04ed      	lsls	r5, r5, #19
-    1fac:	431d      	orrs	r5, r3
-    1fae:	387f      	subs	r0, #127	; 0x7f
-    1fb0:	1836      	adds	r6, r6, r0
-    1fb2:	1c73      	adds	r3, r6, #1
-    1fb4:	4641      	mov	r1, r8
-    1fb6:	469b      	mov	fp, r3
-    1fb8:	464b      	mov	r3, r9
-    1fba:	4061      	eors	r1, r4
-    1fbc:	4313      	orrs	r3, r2
-    1fbe:	2b0f      	cmp	r3, #15
-    1fc0:	d864      	bhi.n	208c <STACK_SIZE+0x8c>
-    1fc2:	4875      	ldr	r0, [pc, #468]	; (2198 <STACK_SIZE+0x198>)
-    1fc4:	009b      	lsls	r3, r3, #2
-    1fc6:	58c3      	ldr	r3, [r0, r3]
-    1fc8:	469f      	mov	pc, r3
-    1fca:	2f00      	cmp	r7, #0
-    1fcc:	d142      	bne.n	2054 <STACK_SIZE+0x54>
-    1fce:	2308      	movs	r3, #8
-    1fd0:	4699      	mov	r9, r3
-    1fd2:	3b06      	subs	r3, #6
-    1fd4:	26ff      	movs	r6, #255	; 0xff
-    1fd6:	469a      	mov	sl, r3
-    1fd8:	e7da      	b.n	1f90 <__aeabi_fmul+0x30>
-    1fda:	4641      	mov	r1, r8
-    1fdc:	2a02      	cmp	r2, #2
-    1fde:	d028      	beq.n	2032 <STACK_SIZE+0x32>
-    1fe0:	2a03      	cmp	r2, #3
-    1fe2:	d100      	bne.n	1fe6 <__aeabi_fmul+0x86>
-    1fe4:	e0ce      	b.n	2184 <STACK_SIZE+0x184>
-    1fe6:	2a01      	cmp	r2, #1
-    1fe8:	d000      	beq.n	1fec <__aeabi_fmul+0x8c>
-    1fea:	e0ac      	b.n	2146 <STACK_SIZE+0x146>
-    1fec:	4011      	ands	r1, r2
-    1fee:	2000      	movs	r0, #0
-    1ff0:	2200      	movs	r2, #0
-    1ff2:	b2cc      	uxtb	r4, r1
-    1ff4:	0240      	lsls	r0, r0, #9
-    1ff6:	05d2      	lsls	r2, r2, #23
-    1ff8:	0a40      	lsrs	r0, r0, #9
-    1ffa:	07e4      	lsls	r4, r4, #31
-    1ffc:	4310      	orrs	r0, r2
-    1ffe:	4320      	orrs	r0, r4
-    2000:	bc3c      	pop	{r2, r3, r4, r5}
-    2002:	4690      	mov	r8, r2
-    2004:	4699      	mov	r9, r3
-    2006:	46a2      	mov	sl, r4
-    2008:	46ab      	mov	fp, r5
-    200a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    200c:	2f00      	cmp	r7, #0
-    200e:	d115      	bne.n	203c <STACK_SIZE+0x3c>
-    2010:	2304      	movs	r3, #4
-    2012:	4699      	mov	r9, r3
-    2014:	3b03      	subs	r3, #3
-    2016:	2600      	movs	r6, #0
-    2018:	469a      	mov	sl, r3
-    201a:	e7b9      	b.n	1f90 <__aeabi_fmul+0x30>
-    201c:	20ff      	movs	r0, #255	; 0xff
-    201e:	2202      	movs	r2, #2
-    2020:	2d00      	cmp	r5, #0
-    2022:	d0c5      	beq.n	1fb0 <__aeabi_fmul+0x50>
-    2024:	2203      	movs	r2, #3
-    2026:	e7c3      	b.n	1fb0 <__aeabi_fmul+0x50>
-    2028:	2d00      	cmp	r5, #0
-    202a:	d119      	bne.n	2060 <STACK_SIZE+0x60>
-    202c:	2000      	movs	r0, #0
-    202e:	2201      	movs	r2, #1
-    2030:	e7be      	b.n	1fb0 <__aeabi_fmul+0x50>
-    2032:	2401      	movs	r4, #1
-    2034:	22ff      	movs	r2, #255	; 0xff
-    2036:	400c      	ands	r4, r1
-    2038:	2000      	movs	r0, #0
-    203a:	e7db      	b.n	1ff4 <__aeabi_fmul+0x94>
-    203c:	0038      	movs	r0, r7
-    203e:	f000 fb01 	bl	2644 <__clzsi2>
-    2042:	2676      	movs	r6, #118	; 0x76
-    2044:	1f43      	subs	r3, r0, #5
-    2046:	409f      	lsls	r7, r3
-    2048:	2300      	movs	r3, #0
-    204a:	4276      	negs	r6, r6
-    204c:	1a36      	subs	r6, r6, r0
-    204e:	4699      	mov	r9, r3
-    2050:	469a      	mov	sl, r3
-    2052:	e79d      	b.n	1f90 <__aeabi_fmul+0x30>
-    2054:	230c      	movs	r3, #12
-    2056:	4699      	mov	r9, r3
-    2058:	3b09      	subs	r3, #9
-    205a:	26ff      	movs	r6, #255	; 0xff
-    205c:	469a      	mov	sl, r3
-    205e:	e797      	b.n	1f90 <__aeabi_fmul+0x30>
-    2060:	0028      	movs	r0, r5
-    2062:	f000 faef 	bl	2644 <__clzsi2>
-    2066:	1f43      	subs	r3, r0, #5
-    2068:	409d      	lsls	r5, r3
-    206a:	2376      	movs	r3, #118	; 0x76
-    206c:	425b      	negs	r3, r3
-    206e:	1a18      	subs	r0, r3, r0
-    2070:	2200      	movs	r2, #0
-    2072:	e79d      	b.n	1fb0 <__aeabi_fmul+0x50>
-    2074:	2080      	movs	r0, #128	; 0x80
-    2076:	2400      	movs	r4, #0
-    2078:	03c0      	lsls	r0, r0, #15
-    207a:	22ff      	movs	r2, #255	; 0xff
-    207c:	e7ba      	b.n	1ff4 <__aeabi_fmul+0x94>
-    207e:	003d      	movs	r5, r7
-    2080:	4652      	mov	r2, sl
-    2082:	e7ab      	b.n	1fdc <__aeabi_fmul+0x7c>
-    2084:	003d      	movs	r5, r7
-    2086:	0021      	movs	r1, r4
-    2088:	4652      	mov	r2, sl
-    208a:	e7a7      	b.n	1fdc <__aeabi_fmul+0x7c>
-    208c:	0c3b      	lsrs	r3, r7, #16
-    208e:	469c      	mov	ip, r3
-    2090:	042a      	lsls	r2, r5, #16
-    2092:	0c12      	lsrs	r2, r2, #16
-    2094:	0c2b      	lsrs	r3, r5, #16
-    2096:	0014      	movs	r4, r2
-    2098:	4660      	mov	r0, ip
-    209a:	4665      	mov	r5, ip
-    209c:	043f      	lsls	r7, r7, #16
-    209e:	0c3f      	lsrs	r7, r7, #16
-    20a0:	437c      	muls	r4, r7
-    20a2:	4342      	muls	r2, r0
-    20a4:	435d      	muls	r5, r3
-    20a6:	437b      	muls	r3, r7
-    20a8:	0c27      	lsrs	r7, r4, #16
-    20aa:	189b      	adds	r3, r3, r2
-    20ac:	18ff      	adds	r7, r7, r3
-    20ae:	42ba      	cmp	r2, r7
-    20b0:	d903      	bls.n	20ba <STACK_SIZE+0xba>
-    20b2:	2380      	movs	r3, #128	; 0x80
-    20b4:	025b      	lsls	r3, r3, #9
-    20b6:	469c      	mov	ip, r3
-    20b8:	4465      	add	r5, ip
-    20ba:	0424      	lsls	r4, r4, #16
-    20bc:	043a      	lsls	r2, r7, #16
-    20be:	0c24      	lsrs	r4, r4, #16
-    20c0:	1912      	adds	r2, r2, r4
-    20c2:	0193      	lsls	r3, r2, #6
-    20c4:	1e5c      	subs	r4, r3, #1
-    20c6:	41a3      	sbcs	r3, r4
-    20c8:	0c3f      	lsrs	r7, r7, #16
-    20ca:	0e92      	lsrs	r2, r2, #26
-    20cc:	197d      	adds	r5, r7, r5
-    20ce:	431a      	orrs	r2, r3
-    20d0:	01ad      	lsls	r5, r5, #6
-    20d2:	4315      	orrs	r5, r2
-    20d4:	012b      	lsls	r3, r5, #4
-    20d6:	d504      	bpl.n	20e2 <STACK_SIZE+0xe2>
-    20d8:	2301      	movs	r3, #1
-    20da:	465e      	mov	r6, fp
-    20dc:	086a      	lsrs	r2, r5, #1
-    20de:	401d      	ands	r5, r3
-    20e0:	4315      	orrs	r5, r2
-    20e2:	0032      	movs	r2, r6
-    20e4:	327f      	adds	r2, #127	; 0x7f
-    20e6:	2a00      	cmp	r2, #0
-    20e8:	dd25      	ble.n	2136 <STACK_SIZE+0x136>
-    20ea:	076b      	lsls	r3, r5, #29
-    20ec:	d004      	beq.n	20f8 <STACK_SIZE+0xf8>
-    20ee:	230f      	movs	r3, #15
-    20f0:	402b      	ands	r3, r5
-    20f2:	2b04      	cmp	r3, #4
-    20f4:	d000      	beq.n	20f8 <STACK_SIZE+0xf8>
-    20f6:	3504      	adds	r5, #4
-    20f8:	012b      	lsls	r3, r5, #4
-    20fa:	d503      	bpl.n	2104 <STACK_SIZE+0x104>
-    20fc:	0032      	movs	r2, r6
-    20fe:	4b27      	ldr	r3, [pc, #156]	; (219c <STACK_SIZE+0x19c>)
-    2100:	3280      	adds	r2, #128	; 0x80
-    2102:	401d      	ands	r5, r3
-    2104:	2afe      	cmp	r2, #254	; 0xfe
-    2106:	dc94      	bgt.n	2032 <STACK_SIZE+0x32>
-    2108:	2401      	movs	r4, #1
-    210a:	01a8      	lsls	r0, r5, #6
-    210c:	0a40      	lsrs	r0, r0, #9
-    210e:	b2d2      	uxtb	r2, r2
-    2110:	400c      	ands	r4, r1
-    2112:	e76f      	b.n	1ff4 <__aeabi_fmul+0x94>
-    2114:	2080      	movs	r0, #128	; 0x80
-    2116:	03c0      	lsls	r0, r0, #15
-    2118:	4207      	tst	r7, r0
-    211a:	d007      	beq.n	212c <STACK_SIZE+0x12c>
-    211c:	4205      	tst	r5, r0
-    211e:	d105      	bne.n	212c <STACK_SIZE+0x12c>
-    2120:	4328      	orrs	r0, r5
-    2122:	0240      	lsls	r0, r0, #9
-    2124:	0a40      	lsrs	r0, r0, #9
-    2126:	4644      	mov	r4, r8
-    2128:	22ff      	movs	r2, #255	; 0xff
-    212a:	e763      	b.n	1ff4 <__aeabi_fmul+0x94>
-    212c:	4338      	orrs	r0, r7
-    212e:	0240      	lsls	r0, r0, #9
-    2130:	0a40      	lsrs	r0, r0, #9
-    2132:	22ff      	movs	r2, #255	; 0xff
-    2134:	e75e      	b.n	1ff4 <__aeabi_fmul+0x94>
-    2136:	2401      	movs	r4, #1
-    2138:	1aa3      	subs	r3, r4, r2
-    213a:	2b1b      	cmp	r3, #27
-    213c:	dd05      	ble.n	214a <STACK_SIZE+0x14a>
-    213e:	400c      	ands	r4, r1
-    2140:	2200      	movs	r2, #0
-    2142:	2000      	movs	r0, #0
-    2144:	e756      	b.n	1ff4 <__aeabi_fmul+0x94>
-    2146:	465e      	mov	r6, fp
-    2148:	e7cb      	b.n	20e2 <STACK_SIZE+0xe2>
-    214a:	002a      	movs	r2, r5
-    214c:	2020      	movs	r0, #32
-    214e:	40da      	lsrs	r2, r3
-    2150:	1ac3      	subs	r3, r0, r3
-    2152:	409d      	lsls	r5, r3
-    2154:	002b      	movs	r3, r5
-    2156:	1e5d      	subs	r5, r3, #1
-    2158:	41ab      	sbcs	r3, r5
-    215a:	4313      	orrs	r3, r2
-    215c:	075a      	lsls	r2, r3, #29
-    215e:	d004      	beq.n	216a <STACK_SIZE+0x16a>
-    2160:	220f      	movs	r2, #15
-    2162:	401a      	ands	r2, r3
-    2164:	2a04      	cmp	r2, #4
-    2166:	d000      	beq.n	216a <STACK_SIZE+0x16a>
-    2168:	3304      	adds	r3, #4
-    216a:	015a      	lsls	r2, r3, #5
-    216c:	d504      	bpl.n	2178 <STACK_SIZE+0x178>
-    216e:	2401      	movs	r4, #1
-    2170:	2201      	movs	r2, #1
-    2172:	400c      	ands	r4, r1
-    2174:	2000      	movs	r0, #0
-    2176:	e73d      	b.n	1ff4 <__aeabi_fmul+0x94>
-    2178:	2401      	movs	r4, #1
-    217a:	019b      	lsls	r3, r3, #6
-    217c:	0a58      	lsrs	r0, r3, #9
-    217e:	400c      	ands	r4, r1
-    2180:	2200      	movs	r2, #0
-    2182:	e737      	b.n	1ff4 <__aeabi_fmul+0x94>
-    2184:	2080      	movs	r0, #128	; 0x80
-    2186:	2401      	movs	r4, #1
-    2188:	03c0      	lsls	r0, r0, #15
-    218a:	4328      	orrs	r0, r5
-    218c:	0240      	lsls	r0, r0, #9
-    218e:	0a40      	lsrs	r0, r0, #9
-    2190:	400c      	ands	r4, r1
-    2192:	22ff      	movs	r2, #255	; 0xff
-    2194:	e72e      	b.n	1ff4 <__aeabi_fmul+0x94>
-    2196:	46c0      	nop			; (mov r8, r8)
-    2198:	00003868 	.word	0x00003868
-    219c:	f7ffffff 	.word	0xf7ffffff
-
-000021a0 <__aeabi_fsub>:
-    21a0:	b5f0      	push	{r4, r5, r6, r7, lr}
-    21a2:	464f      	mov	r7, r9
-    21a4:	46d6      	mov	lr, sl
-    21a6:	4646      	mov	r6, r8
-    21a8:	0044      	lsls	r4, r0, #1
-    21aa:	b5c0      	push	{r6, r7, lr}
-    21ac:	0fc2      	lsrs	r2, r0, #31
-    21ae:	0247      	lsls	r7, r0, #9
-    21b0:	0248      	lsls	r0, r1, #9
-    21b2:	0a40      	lsrs	r0, r0, #9
-    21b4:	4684      	mov	ip, r0
-    21b6:	4666      	mov	r6, ip
-    21b8:	0a7b      	lsrs	r3, r7, #9
-    21ba:	0048      	lsls	r0, r1, #1
-    21bc:	0fc9      	lsrs	r1, r1, #31
-    21be:	469a      	mov	sl, r3
-    21c0:	0e24      	lsrs	r4, r4, #24
-    21c2:	0015      	movs	r5, r2
-    21c4:	00db      	lsls	r3, r3, #3
-    21c6:	0e00      	lsrs	r0, r0, #24
-    21c8:	4689      	mov	r9, r1
-    21ca:	00f6      	lsls	r6, r6, #3
-    21cc:	28ff      	cmp	r0, #255	; 0xff
-    21ce:	d100      	bne.n	21d2 <__aeabi_fsub+0x32>
-    21d0:	e08f      	b.n	22f2 <__aeabi_fsub+0x152>
-    21d2:	2101      	movs	r1, #1
-    21d4:	464f      	mov	r7, r9
-    21d6:	404f      	eors	r7, r1
-    21d8:	0039      	movs	r1, r7
-    21da:	4291      	cmp	r1, r2
-    21dc:	d066      	beq.n	22ac <__aeabi_fsub+0x10c>
-    21de:	1a22      	subs	r2, r4, r0
-    21e0:	2a00      	cmp	r2, #0
-    21e2:	dc00      	bgt.n	21e6 <__aeabi_fsub+0x46>
-    21e4:	e09d      	b.n	2322 <__aeabi_fsub+0x182>
-    21e6:	2800      	cmp	r0, #0
-    21e8:	d13d      	bne.n	2266 <__aeabi_fsub+0xc6>
-    21ea:	2e00      	cmp	r6, #0
-    21ec:	d100      	bne.n	21f0 <__aeabi_fsub+0x50>
-    21ee:	e08b      	b.n	2308 <__aeabi_fsub+0x168>
-    21f0:	1e51      	subs	r1, r2, #1
-    21f2:	2900      	cmp	r1, #0
-    21f4:	d000      	beq.n	21f8 <__aeabi_fsub+0x58>
-    21f6:	e0b5      	b.n	2364 <__aeabi_fsub+0x1c4>
-    21f8:	2401      	movs	r4, #1
-    21fa:	1b9b      	subs	r3, r3, r6
-    21fc:	015a      	lsls	r2, r3, #5
-    21fe:	d544      	bpl.n	228a <__aeabi_fsub+0xea>
-    2200:	019b      	lsls	r3, r3, #6
-    2202:	099f      	lsrs	r7, r3, #6
-    2204:	0038      	movs	r0, r7
-    2206:	f000 fa1d 	bl	2644 <__clzsi2>
-    220a:	3805      	subs	r0, #5
-    220c:	4087      	lsls	r7, r0
-    220e:	4284      	cmp	r4, r0
-    2210:	dd00      	ble.n	2214 <__aeabi_fsub+0x74>
-    2212:	e096      	b.n	2342 <__aeabi_fsub+0x1a2>
-    2214:	1b04      	subs	r4, r0, r4
-    2216:	003a      	movs	r2, r7
-    2218:	2020      	movs	r0, #32
-    221a:	3401      	adds	r4, #1
-    221c:	40e2      	lsrs	r2, r4
-    221e:	1b04      	subs	r4, r0, r4
-    2220:	40a7      	lsls	r7, r4
-    2222:	003b      	movs	r3, r7
-    2224:	1e5f      	subs	r7, r3, #1
-    2226:	41bb      	sbcs	r3, r7
-    2228:	2400      	movs	r4, #0
-    222a:	4313      	orrs	r3, r2
-    222c:	075a      	lsls	r2, r3, #29
-    222e:	d004      	beq.n	223a <__aeabi_fsub+0x9a>
-    2230:	220f      	movs	r2, #15
-    2232:	401a      	ands	r2, r3
-    2234:	2a04      	cmp	r2, #4
-    2236:	d000      	beq.n	223a <__aeabi_fsub+0x9a>
-    2238:	3304      	adds	r3, #4
-    223a:	015a      	lsls	r2, r3, #5
-    223c:	d527      	bpl.n	228e <__aeabi_fsub+0xee>
-    223e:	3401      	adds	r4, #1
-    2240:	2cff      	cmp	r4, #255	; 0xff
-    2242:	d100      	bne.n	2246 <__aeabi_fsub+0xa6>
-    2244:	e079      	b.n	233a <__aeabi_fsub+0x19a>
-    2246:	2201      	movs	r2, #1
-    2248:	019b      	lsls	r3, r3, #6
-    224a:	0a5b      	lsrs	r3, r3, #9
-    224c:	b2e4      	uxtb	r4, r4
-    224e:	402a      	ands	r2, r5
-    2250:	025b      	lsls	r3, r3, #9
-    2252:	05e4      	lsls	r4, r4, #23
-    2254:	0a58      	lsrs	r0, r3, #9
-    2256:	07d2      	lsls	r2, r2, #31
-    2258:	4320      	orrs	r0, r4
-    225a:	4310      	orrs	r0, r2
-    225c:	bc1c      	pop	{r2, r3, r4}
-    225e:	4690      	mov	r8, r2
-    2260:	4699      	mov	r9, r3
-    2262:	46a2      	mov	sl, r4
-    2264:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    2266:	2cff      	cmp	r4, #255	; 0xff
-    2268:	d0e0      	beq.n	222c <__aeabi_fsub+0x8c>
-    226a:	2180      	movs	r1, #128	; 0x80
-    226c:	04c9      	lsls	r1, r1, #19
-    226e:	430e      	orrs	r6, r1
-    2270:	2a1b      	cmp	r2, #27
-    2272:	dc7b      	bgt.n	236c <__aeabi_fsub+0x1cc>
-    2274:	0031      	movs	r1, r6
-    2276:	2020      	movs	r0, #32
-    2278:	40d1      	lsrs	r1, r2
-    227a:	1a82      	subs	r2, r0, r2
-    227c:	4096      	lsls	r6, r2
-    227e:	1e72      	subs	r2, r6, #1
-    2280:	4196      	sbcs	r6, r2
-    2282:	430e      	orrs	r6, r1
-    2284:	1b9b      	subs	r3, r3, r6
-    2286:	015a      	lsls	r2, r3, #5
-    2288:	d4ba      	bmi.n	2200 <__aeabi_fsub+0x60>
-    228a:	075a      	lsls	r2, r3, #29
-    228c:	d1d0      	bne.n	2230 <__aeabi_fsub+0x90>
-    228e:	2201      	movs	r2, #1
-    2290:	08df      	lsrs	r7, r3, #3
-    2292:	402a      	ands	r2, r5
-    2294:	2cff      	cmp	r4, #255	; 0xff
-    2296:	d133      	bne.n	2300 <__aeabi_fsub+0x160>
-    2298:	2f00      	cmp	r7, #0
-    229a:	d100      	bne.n	229e <__aeabi_fsub+0xfe>
-    229c:	e0a8      	b.n	23f0 <__aeabi_fsub+0x250>
-    229e:	2380      	movs	r3, #128	; 0x80
-    22a0:	03db      	lsls	r3, r3, #15
-    22a2:	433b      	orrs	r3, r7
-    22a4:	025b      	lsls	r3, r3, #9
-    22a6:	0a5b      	lsrs	r3, r3, #9
-    22a8:	24ff      	movs	r4, #255	; 0xff
-    22aa:	e7d1      	b.n	2250 <__aeabi_fsub+0xb0>
-    22ac:	1a21      	subs	r1, r4, r0
-    22ae:	2900      	cmp	r1, #0
-    22b0:	dd4c      	ble.n	234c <__aeabi_fsub+0x1ac>
-    22b2:	2800      	cmp	r0, #0
-    22b4:	d02a      	beq.n	230c <__aeabi_fsub+0x16c>
-    22b6:	2cff      	cmp	r4, #255	; 0xff
-    22b8:	d0b8      	beq.n	222c <__aeabi_fsub+0x8c>
-    22ba:	2080      	movs	r0, #128	; 0x80
-    22bc:	04c0      	lsls	r0, r0, #19
-    22be:	4306      	orrs	r6, r0
-    22c0:	291b      	cmp	r1, #27
-    22c2:	dd00      	ble.n	22c6 <__aeabi_fsub+0x126>
-    22c4:	e0af      	b.n	2426 <__aeabi_fsub+0x286>
-    22c6:	0030      	movs	r0, r6
-    22c8:	2720      	movs	r7, #32
-    22ca:	40c8      	lsrs	r0, r1
-    22cc:	1a79      	subs	r1, r7, r1
-    22ce:	408e      	lsls	r6, r1
-    22d0:	1e71      	subs	r1, r6, #1
-    22d2:	418e      	sbcs	r6, r1
-    22d4:	4306      	orrs	r6, r0
-    22d6:	199b      	adds	r3, r3, r6
-    22d8:	0159      	lsls	r1, r3, #5
-    22da:	d5d6      	bpl.n	228a <__aeabi_fsub+0xea>
-    22dc:	3401      	adds	r4, #1
-    22de:	2cff      	cmp	r4, #255	; 0xff
-    22e0:	d100      	bne.n	22e4 <__aeabi_fsub+0x144>
-    22e2:	e085      	b.n	23f0 <__aeabi_fsub+0x250>
-    22e4:	2201      	movs	r2, #1
-    22e6:	497a      	ldr	r1, [pc, #488]	; (24d0 <__aeabi_fsub+0x330>)
-    22e8:	401a      	ands	r2, r3
-    22ea:	085b      	lsrs	r3, r3, #1
-    22ec:	400b      	ands	r3, r1
-    22ee:	4313      	orrs	r3, r2
-    22f0:	e79c      	b.n	222c <__aeabi_fsub+0x8c>
-    22f2:	2e00      	cmp	r6, #0
-    22f4:	d000      	beq.n	22f8 <__aeabi_fsub+0x158>
-    22f6:	e770      	b.n	21da <__aeabi_fsub+0x3a>
-    22f8:	e76b      	b.n	21d2 <__aeabi_fsub+0x32>
-    22fa:	1e3b      	subs	r3, r7, #0
-    22fc:	d1c5      	bne.n	228a <__aeabi_fsub+0xea>
-    22fe:	2200      	movs	r2, #0
-    2300:	027b      	lsls	r3, r7, #9
-    2302:	0a5b      	lsrs	r3, r3, #9
-    2304:	b2e4      	uxtb	r4, r4
-    2306:	e7a3      	b.n	2250 <__aeabi_fsub+0xb0>
-    2308:	0014      	movs	r4, r2
-    230a:	e78f      	b.n	222c <__aeabi_fsub+0x8c>
-    230c:	2e00      	cmp	r6, #0
-    230e:	d04d      	beq.n	23ac <__aeabi_fsub+0x20c>
-    2310:	1e48      	subs	r0, r1, #1
-    2312:	2800      	cmp	r0, #0
-    2314:	d157      	bne.n	23c6 <__aeabi_fsub+0x226>
-    2316:	199b      	adds	r3, r3, r6
-    2318:	2401      	movs	r4, #1
-    231a:	015a      	lsls	r2, r3, #5
-    231c:	d5b5      	bpl.n	228a <__aeabi_fsub+0xea>
-    231e:	2402      	movs	r4, #2
-    2320:	e7e0      	b.n	22e4 <__aeabi_fsub+0x144>
-    2322:	2a00      	cmp	r2, #0
-    2324:	d125      	bne.n	2372 <__aeabi_fsub+0x1d2>
-    2326:	1c62      	adds	r2, r4, #1
-    2328:	b2d2      	uxtb	r2, r2
-    232a:	2a01      	cmp	r2, #1
-    232c:	dd72      	ble.n	2414 <__aeabi_fsub+0x274>
-    232e:	1b9f      	subs	r7, r3, r6
-    2330:	017a      	lsls	r2, r7, #5
-    2332:	d535      	bpl.n	23a0 <__aeabi_fsub+0x200>
-    2334:	1af7      	subs	r7, r6, r3
-    2336:	000d      	movs	r5, r1
-    2338:	e764      	b.n	2204 <__aeabi_fsub+0x64>
-    233a:	2201      	movs	r2, #1
-    233c:	2300      	movs	r3, #0
-    233e:	402a      	ands	r2, r5
-    2340:	e786      	b.n	2250 <__aeabi_fsub+0xb0>
-    2342:	003b      	movs	r3, r7
-    2344:	4a63      	ldr	r2, [pc, #396]	; (24d4 <__aeabi_fsub+0x334>)
-    2346:	1a24      	subs	r4, r4, r0
-    2348:	4013      	ands	r3, r2
-    234a:	e76f      	b.n	222c <__aeabi_fsub+0x8c>
-    234c:	2900      	cmp	r1, #0
-    234e:	d16c      	bne.n	242a <__aeabi_fsub+0x28a>
-    2350:	1c61      	adds	r1, r4, #1
-    2352:	b2c8      	uxtb	r0, r1
-    2354:	2801      	cmp	r0, #1
-    2356:	dd4e      	ble.n	23f6 <__aeabi_fsub+0x256>
-    2358:	29ff      	cmp	r1, #255	; 0xff
-    235a:	d049      	beq.n	23f0 <__aeabi_fsub+0x250>
-    235c:	199b      	adds	r3, r3, r6
-    235e:	085b      	lsrs	r3, r3, #1
-    2360:	000c      	movs	r4, r1
-    2362:	e763      	b.n	222c <__aeabi_fsub+0x8c>
-    2364:	2aff      	cmp	r2, #255	; 0xff
-    2366:	d041      	beq.n	23ec <__aeabi_fsub+0x24c>
-    2368:	000a      	movs	r2, r1
-    236a:	e781      	b.n	2270 <__aeabi_fsub+0xd0>
-    236c:	2601      	movs	r6, #1
-    236e:	1b9b      	subs	r3, r3, r6
-    2370:	e789      	b.n	2286 <__aeabi_fsub+0xe6>
-    2372:	2c00      	cmp	r4, #0
-    2374:	d01c      	beq.n	23b0 <__aeabi_fsub+0x210>
-    2376:	28ff      	cmp	r0, #255	; 0xff
-    2378:	d021      	beq.n	23be <__aeabi_fsub+0x21e>
-    237a:	2480      	movs	r4, #128	; 0x80
-    237c:	04e4      	lsls	r4, r4, #19
-    237e:	4252      	negs	r2, r2
-    2380:	4323      	orrs	r3, r4
-    2382:	2a1b      	cmp	r2, #27
-    2384:	dd00      	ble.n	2388 <__aeabi_fsub+0x1e8>
-    2386:	e096      	b.n	24b6 <__aeabi_fsub+0x316>
-    2388:	001c      	movs	r4, r3
-    238a:	2520      	movs	r5, #32
-    238c:	40d4      	lsrs	r4, r2
-    238e:	1aaa      	subs	r2, r5, r2
-    2390:	4093      	lsls	r3, r2
-    2392:	1e5a      	subs	r2, r3, #1
-    2394:	4193      	sbcs	r3, r2
-    2396:	4323      	orrs	r3, r4
-    2398:	1af3      	subs	r3, r6, r3
-    239a:	0004      	movs	r4, r0
-    239c:	000d      	movs	r5, r1
-    239e:	e72d      	b.n	21fc <__aeabi_fsub+0x5c>
-    23a0:	2f00      	cmp	r7, #0
-    23a2:	d000      	beq.n	23a6 <__aeabi_fsub+0x206>
-    23a4:	e72e      	b.n	2204 <__aeabi_fsub+0x64>
-    23a6:	2200      	movs	r2, #0
-    23a8:	2400      	movs	r4, #0
-    23aa:	e7a9      	b.n	2300 <__aeabi_fsub+0x160>
-    23ac:	000c      	movs	r4, r1
-    23ae:	e73d      	b.n	222c <__aeabi_fsub+0x8c>
-    23b0:	2b00      	cmp	r3, #0
-    23b2:	d058      	beq.n	2466 <__aeabi_fsub+0x2c6>
-    23b4:	43d2      	mvns	r2, r2
-    23b6:	2a00      	cmp	r2, #0
-    23b8:	d0ee      	beq.n	2398 <__aeabi_fsub+0x1f8>
-    23ba:	28ff      	cmp	r0, #255	; 0xff
-    23bc:	d1e1      	bne.n	2382 <__aeabi_fsub+0x1e2>
-    23be:	0033      	movs	r3, r6
-    23c0:	24ff      	movs	r4, #255	; 0xff
-    23c2:	000d      	movs	r5, r1
-    23c4:	e732      	b.n	222c <__aeabi_fsub+0x8c>
-    23c6:	29ff      	cmp	r1, #255	; 0xff
-    23c8:	d010      	beq.n	23ec <__aeabi_fsub+0x24c>
-    23ca:	0001      	movs	r1, r0
-    23cc:	e778      	b.n	22c0 <__aeabi_fsub+0x120>
-    23ce:	2b00      	cmp	r3, #0
-    23d0:	d06e      	beq.n	24b0 <__aeabi_fsub+0x310>
-    23d2:	24ff      	movs	r4, #255	; 0xff
-    23d4:	2e00      	cmp	r6, #0
-    23d6:	d100      	bne.n	23da <__aeabi_fsub+0x23a>
-    23d8:	e728      	b.n	222c <__aeabi_fsub+0x8c>
-    23da:	2280      	movs	r2, #128	; 0x80
-    23dc:	4651      	mov	r1, sl
-    23de:	03d2      	lsls	r2, r2, #15
-    23e0:	4211      	tst	r1, r2
-    23e2:	d003      	beq.n	23ec <__aeabi_fsub+0x24c>
-    23e4:	4661      	mov	r1, ip
-    23e6:	4211      	tst	r1, r2
-    23e8:	d100      	bne.n	23ec <__aeabi_fsub+0x24c>
-    23ea:	0033      	movs	r3, r6
-    23ec:	24ff      	movs	r4, #255	; 0xff
-    23ee:	e71d      	b.n	222c <__aeabi_fsub+0x8c>
-    23f0:	24ff      	movs	r4, #255	; 0xff
-    23f2:	2300      	movs	r3, #0
-    23f4:	e72c      	b.n	2250 <__aeabi_fsub+0xb0>
-    23f6:	2c00      	cmp	r4, #0
-    23f8:	d1e9      	bne.n	23ce <__aeabi_fsub+0x22e>
-    23fa:	2b00      	cmp	r3, #0
-    23fc:	d063      	beq.n	24c6 <__aeabi_fsub+0x326>
-    23fe:	2e00      	cmp	r6, #0
-    2400:	d100      	bne.n	2404 <__aeabi_fsub+0x264>
-    2402:	e713      	b.n	222c <__aeabi_fsub+0x8c>
-    2404:	199b      	adds	r3, r3, r6
-    2406:	015a      	lsls	r2, r3, #5
-    2408:	d400      	bmi.n	240c <__aeabi_fsub+0x26c>
-    240a:	e73e      	b.n	228a <__aeabi_fsub+0xea>
-    240c:	4a31      	ldr	r2, [pc, #196]	; (24d4 <__aeabi_fsub+0x334>)
-    240e:	000c      	movs	r4, r1
-    2410:	4013      	ands	r3, r2
-    2412:	e70b      	b.n	222c <__aeabi_fsub+0x8c>
-    2414:	2c00      	cmp	r4, #0
-    2416:	d11e      	bne.n	2456 <__aeabi_fsub+0x2b6>
-    2418:	2b00      	cmp	r3, #0
-    241a:	d12f      	bne.n	247c <__aeabi_fsub+0x2dc>
-    241c:	2e00      	cmp	r6, #0
-    241e:	d04f      	beq.n	24c0 <__aeabi_fsub+0x320>
-    2420:	0033      	movs	r3, r6
-    2422:	000d      	movs	r5, r1
-    2424:	e702      	b.n	222c <__aeabi_fsub+0x8c>
-    2426:	2601      	movs	r6, #1
-    2428:	e755      	b.n	22d6 <__aeabi_fsub+0x136>
-    242a:	2c00      	cmp	r4, #0
-    242c:	d11f      	bne.n	246e <__aeabi_fsub+0x2ce>
-    242e:	2b00      	cmp	r3, #0
-    2430:	d043      	beq.n	24ba <__aeabi_fsub+0x31a>
-    2432:	43c9      	mvns	r1, r1
-    2434:	2900      	cmp	r1, #0
-    2436:	d00b      	beq.n	2450 <__aeabi_fsub+0x2b0>
-    2438:	28ff      	cmp	r0, #255	; 0xff
-    243a:	d039      	beq.n	24b0 <__aeabi_fsub+0x310>
-    243c:	291b      	cmp	r1, #27
-    243e:	dc44      	bgt.n	24ca <__aeabi_fsub+0x32a>
-    2440:	001c      	movs	r4, r3
-    2442:	2720      	movs	r7, #32
-    2444:	40cc      	lsrs	r4, r1
-    2446:	1a79      	subs	r1, r7, r1
-    2448:	408b      	lsls	r3, r1
-    244a:	1e59      	subs	r1, r3, #1
-    244c:	418b      	sbcs	r3, r1
-    244e:	4323      	orrs	r3, r4
-    2450:	199b      	adds	r3, r3, r6
-    2452:	0004      	movs	r4, r0
-    2454:	e740      	b.n	22d8 <__aeabi_fsub+0x138>
-    2456:	2b00      	cmp	r3, #0
-    2458:	d11a      	bne.n	2490 <__aeabi_fsub+0x2f0>
-    245a:	2e00      	cmp	r6, #0
-    245c:	d124      	bne.n	24a8 <__aeabi_fsub+0x308>
-    245e:	2780      	movs	r7, #128	; 0x80
-    2460:	2200      	movs	r2, #0
-    2462:	03ff      	lsls	r7, r7, #15
-    2464:	e71b      	b.n	229e <__aeabi_fsub+0xfe>
-    2466:	0033      	movs	r3, r6
-    2468:	0004      	movs	r4, r0
-    246a:	000d      	movs	r5, r1
-    246c:	e6de      	b.n	222c <__aeabi_fsub+0x8c>
-    246e:	28ff      	cmp	r0, #255	; 0xff
-    2470:	d01e      	beq.n	24b0 <__aeabi_fsub+0x310>
-    2472:	2480      	movs	r4, #128	; 0x80
-    2474:	04e4      	lsls	r4, r4, #19
-    2476:	4249      	negs	r1, r1
-    2478:	4323      	orrs	r3, r4
-    247a:	e7df      	b.n	243c <__aeabi_fsub+0x29c>
-    247c:	2e00      	cmp	r6, #0
-    247e:	d100      	bne.n	2482 <__aeabi_fsub+0x2e2>
-    2480:	e6d4      	b.n	222c <__aeabi_fsub+0x8c>
-    2482:	1b9f      	subs	r7, r3, r6
-    2484:	017a      	lsls	r2, r7, #5
-    2486:	d400      	bmi.n	248a <__aeabi_fsub+0x2ea>
-    2488:	e737      	b.n	22fa <__aeabi_fsub+0x15a>
-    248a:	1af3      	subs	r3, r6, r3
-    248c:	000d      	movs	r5, r1
-    248e:	e6cd      	b.n	222c <__aeabi_fsub+0x8c>
-    2490:	24ff      	movs	r4, #255	; 0xff
-    2492:	2e00      	cmp	r6, #0
-    2494:	d100      	bne.n	2498 <__aeabi_fsub+0x2f8>
-    2496:	e6c9      	b.n	222c <__aeabi_fsub+0x8c>
-    2498:	2280      	movs	r2, #128	; 0x80
-    249a:	4650      	mov	r0, sl
-    249c:	03d2      	lsls	r2, r2, #15
-    249e:	4210      	tst	r0, r2
-    24a0:	d0a4      	beq.n	23ec <__aeabi_fsub+0x24c>
-    24a2:	4660      	mov	r0, ip
-    24a4:	4210      	tst	r0, r2
-    24a6:	d1a1      	bne.n	23ec <__aeabi_fsub+0x24c>
-    24a8:	0033      	movs	r3, r6
-    24aa:	000d      	movs	r5, r1
-    24ac:	24ff      	movs	r4, #255	; 0xff
-    24ae:	e6bd      	b.n	222c <__aeabi_fsub+0x8c>
-    24b0:	0033      	movs	r3, r6
-    24b2:	24ff      	movs	r4, #255	; 0xff
-    24b4:	e6ba      	b.n	222c <__aeabi_fsub+0x8c>
-    24b6:	2301      	movs	r3, #1
-    24b8:	e76e      	b.n	2398 <__aeabi_fsub+0x1f8>
-    24ba:	0033      	movs	r3, r6
-    24bc:	0004      	movs	r4, r0
-    24be:	e6b5      	b.n	222c <__aeabi_fsub+0x8c>
-    24c0:	2700      	movs	r7, #0
-    24c2:	2200      	movs	r2, #0
-    24c4:	e71c      	b.n	2300 <__aeabi_fsub+0x160>
-    24c6:	0033      	movs	r3, r6
-    24c8:	e6b0      	b.n	222c <__aeabi_fsub+0x8c>
-    24ca:	2301      	movs	r3, #1
-    24cc:	e7c0      	b.n	2450 <__aeabi_fsub+0x2b0>
-    24ce:	46c0      	nop			; (mov r8, r8)
-    24d0:	7dffffff 	.word	0x7dffffff
-    24d4:	fbffffff 	.word	0xfbffffff
-
-000024d8 <__aeabi_f2iz>:
-    24d8:	0241      	lsls	r1, r0, #9
-    24da:	0043      	lsls	r3, r0, #1
-    24dc:	0fc2      	lsrs	r2, r0, #31
-    24de:	0a49      	lsrs	r1, r1, #9
-    24e0:	0e1b      	lsrs	r3, r3, #24
-    24e2:	2000      	movs	r0, #0
-    24e4:	2b7e      	cmp	r3, #126	; 0x7e
-    24e6:	dd0d      	ble.n	2504 <__aeabi_f2iz+0x2c>
-    24e8:	2b9d      	cmp	r3, #157	; 0x9d
-    24ea:	dc0c      	bgt.n	2506 <__aeabi_f2iz+0x2e>
-    24ec:	2080      	movs	r0, #128	; 0x80
-    24ee:	0400      	lsls	r0, r0, #16
-    24f0:	4301      	orrs	r1, r0
-    24f2:	2b95      	cmp	r3, #149	; 0x95
-    24f4:	dc0a      	bgt.n	250c <__aeabi_f2iz+0x34>
-    24f6:	2096      	movs	r0, #150	; 0x96
-    24f8:	1ac3      	subs	r3, r0, r3
-    24fa:	40d9      	lsrs	r1, r3
-    24fc:	4248      	negs	r0, r1
-    24fe:	2a00      	cmp	r2, #0
-    2500:	d100      	bne.n	2504 <__aeabi_f2iz+0x2c>
-    2502:	0008      	movs	r0, r1
-    2504:	4770      	bx	lr
-    2506:	4b03      	ldr	r3, [pc, #12]	; (2514 <__aeabi_f2iz+0x3c>)
-    2508:	18d0      	adds	r0, r2, r3
-    250a:	e7fb      	b.n	2504 <__aeabi_f2iz+0x2c>
-    250c:	3b96      	subs	r3, #150	; 0x96
-    250e:	4099      	lsls	r1, r3
-    2510:	e7f4      	b.n	24fc <__aeabi_f2iz+0x24>
-    2512:	46c0      	nop			; (mov r8, r8)
-    2514:	7fffffff 	.word	0x7fffffff
-
-00002518 <__aeabi_i2f>:
-    2518:	b570      	push	{r4, r5, r6, lr}
-    251a:	2800      	cmp	r0, #0
-    251c:	d030      	beq.n	2580 <__aeabi_i2f+0x68>
-    251e:	17c3      	asrs	r3, r0, #31
-    2520:	18c4      	adds	r4, r0, r3
-    2522:	405c      	eors	r4, r3
-    2524:	0fc5      	lsrs	r5, r0, #31
-    2526:	0020      	movs	r0, r4
-    2528:	f000 f88c 	bl	2644 <__clzsi2>
-    252c:	239e      	movs	r3, #158	; 0x9e
-    252e:	1a1b      	subs	r3, r3, r0
-    2530:	2b96      	cmp	r3, #150	; 0x96
-    2532:	dc0d      	bgt.n	2550 <__aeabi_i2f+0x38>
-    2534:	2296      	movs	r2, #150	; 0x96
-    2536:	1ad2      	subs	r2, r2, r3
-    2538:	4094      	lsls	r4, r2
-    253a:	002a      	movs	r2, r5
-    253c:	0264      	lsls	r4, r4, #9
-    253e:	0a64      	lsrs	r4, r4, #9
-    2540:	b2db      	uxtb	r3, r3
-    2542:	0264      	lsls	r4, r4, #9
-    2544:	05db      	lsls	r3, r3, #23
-    2546:	0a60      	lsrs	r0, r4, #9
-    2548:	07d2      	lsls	r2, r2, #31
-    254a:	4318      	orrs	r0, r3
-    254c:	4310      	orrs	r0, r2
-    254e:	bd70      	pop	{r4, r5, r6, pc}
-    2550:	2b99      	cmp	r3, #153	; 0x99
-    2552:	dc19      	bgt.n	2588 <__aeabi_i2f+0x70>
-    2554:	2299      	movs	r2, #153	; 0x99
-    2556:	1ad2      	subs	r2, r2, r3
-    2558:	2a00      	cmp	r2, #0
-    255a:	dd29      	ble.n	25b0 <__aeabi_i2f+0x98>
-    255c:	4094      	lsls	r4, r2
-    255e:	0022      	movs	r2, r4
-    2560:	4c14      	ldr	r4, [pc, #80]	; (25b4 <__aeabi_i2f+0x9c>)
-    2562:	4014      	ands	r4, r2
-    2564:	0751      	lsls	r1, r2, #29
-    2566:	d004      	beq.n	2572 <__aeabi_i2f+0x5a>
-    2568:	210f      	movs	r1, #15
-    256a:	400a      	ands	r2, r1
-    256c:	2a04      	cmp	r2, #4
-    256e:	d000      	beq.n	2572 <__aeabi_i2f+0x5a>
-    2570:	3404      	adds	r4, #4
-    2572:	0162      	lsls	r2, r4, #5
-    2574:	d413      	bmi.n	259e <__aeabi_i2f+0x86>
-    2576:	01a4      	lsls	r4, r4, #6
-    2578:	0a64      	lsrs	r4, r4, #9
-    257a:	b2db      	uxtb	r3, r3
-    257c:	002a      	movs	r2, r5
-    257e:	e7e0      	b.n	2542 <__aeabi_i2f+0x2a>
-    2580:	2200      	movs	r2, #0
-    2582:	2300      	movs	r3, #0
-    2584:	2400      	movs	r4, #0
-    2586:	e7dc      	b.n	2542 <__aeabi_i2f+0x2a>
-    2588:	2205      	movs	r2, #5
-    258a:	0021      	movs	r1, r4
-    258c:	1a12      	subs	r2, r2, r0
-    258e:	40d1      	lsrs	r1, r2
-    2590:	22b9      	movs	r2, #185	; 0xb9
-    2592:	1ad2      	subs	r2, r2, r3
-    2594:	4094      	lsls	r4, r2
-    2596:	1e62      	subs	r2, r4, #1
-    2598:	4194      	sbcs	r4, r2
-    259a:	430c      	orrs	r4, r1
-    259c:	e7da      	b.n	2554 <__aeabi_i2f+0x3c>
-    259e:	4b05      	ldr	r3, [pc, #20]	; (25b4 <__aeabi_i2f+0x9c>)
-    25a0:	002a      	movs	r2, r5
-    25a2:	401c      	ands	r4, r3
-    25a4:	239f      	movs	r3, #159	; 0x9f
-    25a6:	01a4      	lsls	r4, r4, #6
-    25a8:	1a1b      	subs	r3, r3, r0
-    25aa:	0a64      	lsrs	r4, r4, #9
-    25ac:	b2db      	uxtb	r3, r3
-    25ae:	e7c8      	b.n	2542 <__aeabi_i2f+0x2a>
-    25b0:	0022      	movs	r2, r4
-    25b2:	e7d5      	b.n	2560 <__aeabi_i2f+0x48>
-    25b4:	fbffffff 	.word	0xfbffffff
-
-000025b8 <__aeabi_ui2f>:
-    25b8:	b510      	push	{r4, lr}
-    25ba:	1e04      	subs	r4, r0, #0
-    25bc:	d027      	beq.n	260e <__aeabi_ui2f+0x56>
-    25be:	f000 f841 	bl	2644 <__clzsi2>
-    25c2:	239e      	movs	r3, #158	; 0x9e
-    25c4:	1a1b      	subs	r3, r3, r0
-    25c6:	2b96      	cmp	r3, #150	; 0x96
-    25c8:	dc0a      	bgt.n	25e0 <__aeabi_ui2f+0x28>
-    25ca:	2296      	movs	r2, #150	; 0x96
-    25cc:	1ad2      	subs	r2, r2, r3
-    25ce:	4094      	lsls	r4, r2
-    25d0:	0264      	lsls	r4, r4, #9
-    25d2:	0a64      	lsrs	r4, r4, #9
-    25d4:	b2db      	uxtb	r3, r3
-    25d6:	0264      	lsls	r4, r4, #9
-    25d8:	05db      	lsls	r3, r3, #23
-    25da:	0a60      	lsrs	r0, r4, #9
-    25dc:	4318      	orrs	r0, r3
-    25de:	bd10      	pop	{r4, pc}
-    25e0:	2b99      	cmp	r3, #153	; 0x99
-    25e2:	dc17      	bgt.n	2614 <__aeabi_ui2f+0x5c>
-    25e4:	2299      	movs	r2, #153	; 0x99
-    25e6:	1ad2      	subs	r2, r2, r3
-    25e8:	2a00      	cmp	r2, #0
-    25ea:	dd27      	ble.n	263c <__aeabi_ui2f+0x84>
-    25ec:	4094      	lsls	r4, r2
-    25ee:	0022      	movs	r2, r4
-    25f0:	4c13      	ldr	r4, [pc, #76]	; (2640 <__aeabi_ui2f+0x88>)
-    25f2:	4014      	ands	r4, r2
-    25f4:	0751      	lsls	r1, r2, #29
-    25f6:	d004      	beq.n	2602 <__aeabi_ui2f+0x4a>
-    25f8:	210f      	movs	r1, #15
-    25fa:	400a      	ands	r2, r1
-    25fc:	2a04      	cmp	r2, #4
-    25fe:	d000      	beq.n	2602 <__aeabi_ui2f+0x4a>
-    2600:	3404      	adds	r4, #4
-    2602:	0162      	lsls	r2, r4, #5
-    2604:	d412      	bmi.n	262c <__aeabi_ui2f+0x74>
-    2606:	01a4      	lsls	r4, r4, #6
-    2608:	0a64      	lsrs	r4, r4, #9
-    260a:	b2db      	uxtb	r3, r3
-    260c:	e7e3      	b.n	25d6 <__aeabi_ui2f+0x1e>
-    260e:	2300      	movs	r3, #0
-    2610:	2400      	movs	r4, #0
-    2612:	e7e0      	b.n	25d6 <__aeabi_ui2f+0x1e>
-    2614:	22b9      	movs	r2, #185	; 0xb9
-    2616:	0021      	movs	r1, r4
-    2618:	1ad2      	subs	r2, r2, r3
-    261a:	4091      	lsls	r1, r2
-    261c:	000a      	movs	r2, r1
-    261e:	1e51      	subs	r1, r2, #1
-    2620:	418a      	sbcs	r2, r1
-    2622:	2105      	movs	r1, #5
-    2624:	1a09      	subs	r1, r1, r0
-    2626:	40cc      	lsrs	r4, r1
-    2628:	4314      	orrs	r4, r2
-    262a:	e7db      	b.n	25e4 <__aeabi_ui2f+0x2c>
-    262c:	4b04      	ldr	r3, [pc, #16]	; (2640 <__aeabi_ui2f+0x88>)
-    262e:	401c      	ands	r4, r3
-    2630:	239f      	movs	r3, #159	; 0x9f
-    2632:	01a4      	lsls	r4, r4, #6
-    2634:	1a1b      	subs	r3, r3, r0
-    2636:	0a64      	lsrs	r4, r4, #9
-    2638:	b2db      	uxtb	r3, r3
-    263a:	e7cc      	b.n	25d6 <__aeabi_ui2f+0x1e>
-    263c:	0022      	movs	r2, r4
-    263e:	e7d7      	b.n	25f0 <__aeabi_ui2f+0x38>
-    2640:	fbffffff 	.word	0xfbffffff
-
-00002644 <__clzsi2>:
-    2644:	211c      	movs	r1, #28
-    2646:	2301      	movs	r3, #1
-    2648:	041b      	lsls	r3, r3, #16
-    264a:	4298      	cmp	r0, r3
-    264c:	d301      	bcc.n	2652 <__clzsi2+0xe>
-    264e:	0c00      	lsrs	r0, r0, #16
-    2650:	3910      	subs	r1, #16
-    2652:	0a1b      	lsrs	r3, r3, #8
-    2654:	4298      	cmp	r0, r3
-    2656:	d301      	bcc.n	265c <__clzsi2+0x18>
-    2658:	0a00      	lsrs	r0, r0, #8
-    265a:	3908      	subs	r1, #8
-    265c:	091b      	lsrs	r3, r3, #4
-    265e:	4298      	cmp	r0, r3
-    2660:	d301      	bcc.n	2666 <__clzsi2+0x22>
-    2662:	0900      	lsrs	r0, r0, #4
-    2664:	3904      	subs	r1, #4
-    2666:	a202      	add	r2, pc, #8	; (adr r2, 2670 <__clzsi2+0x2c>)
-    2668:	5c10      	ldrb	r0, [r2, r0]
-    266a:	1840      	adds	r0, r0, r1
-    266c:	4770      	bx	lr
-    266e:	46c0      	nop			; (mov r8, r8)
-    2670:	02020304 	.word	0x02020304
-    2674:	01010101 	.word	0x01010101
-	...
-
-00002680 <__libc_init_array>:
-    2680:	b570      	push	{r4, r5, r6, lr}
-    2682:	2600      	movs	r6, #0
-    2684:	4d0c      	ldr	r5, [pc, #48]	; (26b8 <__libc_init_array+0x38>)
-    2686:	4c0d      	ldr	r4, [pc, #52]	; (26bc <__libc_init_array+0x3c>)
-    2688:	1b64      	subs	r4, r4, r5
-    268a:	10a4      	asrs	r4, r4, #2
-    268c:	42a6      	cmp	r6, r4
-    268e:	d109      	bne.n	26a4 <__libc_init_array+0x24>
-    2690:	2600      	movs	r6, #0
-    2692:	f001 f955 	bl	3940 <_init>
-    2696:	4d0a      	ldr	r5, [pc, #40]	; (26c0 <__libc_init_array+0x40>)
-    2698:	4c0a      	ldr	r4, [pc, #40]	; (26c4 <__libc_init_array+0x44>)
-    269a:	1b64      	subs	r4, r4, r5
-    269c:	10a4      	asrs	r4, r4, #2
-    269e:	42a6      	cmp	r6, r4
-    26a0:	d105      	bne.n	26ae <__libc_init_array+0x2e>
-    26a2:	bd70      	pop	{r4, r5, r6, pc}
-    26a4:	00b3      	lsls	r3, r6, #2
-    26a6:	58eb      	ldr	r3, [r5, r3]
-    26a8:	4798      	blx	r3
-    26aa:	3601      	adds	r6, #1
-    26ac:	e7ee      	b.n	268c <__libc_init_array+0xc>
-    26ae:	00b3      	lsls	r3, r6, #2
-    26b0:	58eb      	ldr	r3, [r5, r3]
-    26b2:	4798      	blx	r3
-    26b4:	3601      	adds	r6, #1
-    26b6:	e7f2      	b.n	269e <__libc_init_array+0x1e>
-    26b8:	0000394c 	.word	0x0000394c
-    26bc:	0000394c 	.word	0x0000394c
-    26c0:	0000394c 	.word	0x0000394c
-    26c4:	00003950 	.word	0x00003950
-
-000026c8 <memcpy>:
-    26c8:	2300      	movs	r3, #0
-    26ca:	b510      	push	{r4, lr}
-    26cc:	429a      	cmp	r2, r3
-    26ce:	d100      	bne.n	26d2 <memcpy+0xa>
-    26d0:	bd10      	pop	{r4, pc}
-    26d2:	5ccc      	ldrb	r4, [r1, r3]
-    26d4:	54c4      	strb	r4, [r0, r3]
-    26d6:	3301      	adds	r3, #1
-    26d8:	e7f8      	b.n	26cc <memcpy+0x4>
-
-000026da <memset>:
-    26da:	0003      	movs	r3, r0
-    26dc:	1882      	adds	r2, r0, r2
-    26de:	4293      	cmp	r3, r2
-    26e0:	d100      	bne.n	26e4 <memset+0xa>
-    26e2:	4770      	bx	lr
-    26e4:	7019      	strb	r1, [r3, #0]
-    26e6:	3301      	adds	r3, #1
-    26e8:	e7f9      	b.n	26de <memset+0x4>
-	...
-
-000026ec <iprintf>:
-    26ec:	b40f      	push	{r0, r1, r2, r3}
-    26ee:	4b0b      	ldr	r3, [pc, #44]	; (271c <iprintf+0x30>)
-    26f0:	b513      	push	{r0, r1, r4, lr}
-    26f2:	681c      	ldr	r4, [r3, #0]
-    26f4:	2c00      	cmp	r4, #0
-    26f6:	d005      	beq.n	2704 <iprintf+0x18>
-    26f8:	69a3      	ldr	r3, [r4, #24]
-    26fa:	2b00      	cmp	r3, #0
-    26fc:	d102      	bne.n	2704 <iprintf+0x18>
-    26fe:	0020      	movs	r0, r4
-    2700:	f000 f9bc 	bl	2a7c <__sinit>
-    2704:	ab05      	add	r3, sp, #20
-    2706:	9a04      	ldr	r2, [sp, #16]
-    2708:	68a1      	ldr	r1, [r4, #8]
-    270a:	0020      	movs	r0, r4
-    270c:	9301      	str	r3, [sp, #4]
-    270e:	f000 fb91 	bl	2e34 <_vfiprintf_r>
-    2712:	bc16      	pop	{r1, r2, r4}
-    2714:	bc08      	pop	{r3}
-    2716:	b004      	add	sp, #16
-    2718:	4718      	bx	r3
-    271a:	46c0      	nop			; (mov r8, r8)
-    271c:	20000018 	.word	0x20000018
-
-00002720 <setbuf>:
-    2720:	424a      	negs	r2, r1
-    2722:	414a      	adcs	r2, r1
-    2724:	2380      	movs	r3, #128	; 0x80
-    2726:	b510      	push	{r4, lr}
-    2728:	0052      	lsls	r2, r2, #1
-    272a:	00db      	lsls	r3, r3, #3
-    272c:	f000 f802 	bl	2734 <setvbuf>
-    2730:	bd10      	pop	{r4, pc}
-	...
-
-00002734 <setvbuf>:
-    2734:	b5f0      	push	{r4, r5, r6, r7, lr}
-    2736:	001d      	movs	r5, r3
-    2738:	4b4f      	ldr	r3, [pc, #316]	; (2878 <setvbuf+0x144>)
-    273a:	b085      	sub	sp, #20
-    273c:	681e      	ldr	r6, [r3, #0]
-    273e:	0004      	movs	r4, r0
-    2740:	000f      	movs	r7, r1
-    2742:	9200      	str	r2, [sp, #0]
-    2744:	2e00      	cmp	r6, #0
-    2746:	d005      	beq.n	2754 <setvbuf+0x20>
-    2748:	69b3      	ldr	r3, [r6, #24]
-    274a:	2b00      	cmp	r3, #0
-    274c:	d102      	bne.n	2754 <setvbuf+0x20>
-    274e:	0030      	movs	r0, r6
-    2750:	f000 f994 	bl	2a7c <__sinit>
-    2754:	4b49      	ldr	r3, [pc, #292]	; (287c <setvbuf+0x148>)
-    2756:	429c      	cmp	r4, r3
-    2758:	d150      	bne.n	27fc <setvbuf+0xc8>
-    275a:	6874      	ldr	r4, [r6, #4]
-    275c:	9b00      	ldr	r3, [sp, #0]
-    275e:	2b02      	cmp	r3, #2
-    2760:	d005      	beq.n	276e <setvbuf+0x3a>
-    2762:	2b01      	cmp	r3, #1
-    2764:	d900      	bls.n	2768 <setvbuf+0x34>
-    2766:	e084      	b.n	2872 <setvbuf+0x13e>
-    2768:	2d00      	cmp	r5, #0
-    276a:	da00      	bge.n	276e <setvbuf+0x3a>
-    276c:	e081      	b.n	2872 <setvbuf+0x13e>
-    276e:	0021      	movs	r1, r4
-    2770:	0030      	movs	r0, r6
-    2772:	f000 f915 	bl	29a0 <_fflush_r>
-    2776:	6b61      	ldr	r1, [r4, #52]	; 0x34
-    2778:	2900      	cmp	r1, #0
-    277a:	d008      	beq.n	278e <setvbuf+0x5a>
-    277c:	0023      	movs	r3, r4
-    277e:	3344      	adds	r3, #68	; 0x44
-    2780:	4299      	cmp	r1, r3
-    2782:	d002      	beq.n	278a <setvbuf+0x56>
-    2784:	0030      	movs	r0, r6
-    2786:	f000 fa85 	bl	2c94 <_free_r>
-    278a:	2300      	movs	r3, #0
-    278c:	6363      	str	r3, [r4, #52]	; 0x34
-    278e:	2300      	movs	r3, #0
-    2790:	61a3      	str	r3, [r4, #24]
-    2792:	6063      	str	r3, [r4, #4]
-    2794:	89a3      	ldrh	r3, [r4, #12]
-    2796:	061b      	lsls	r3, r3, #24
-    2798:	d503      	bpl.n	27a2 <setvbuf+0x6e>
-    279a:	6921      	ldr	r1, [r4, #16]
-    279c:	0030      	movs	r0, r6
-    279e:	f000 fa79 	bl	2c94 <_free_r>
-    27a2:	89a3      	ldrh	r3, [r4, #12]
-    27a4:	4a36      	ldr	r2, [pc, #216]	; (2880 <setvbuf+0x14c>)
-    27a6:	4013      	ands	r3, r2
-    27a8:	81a3      	strh	r3, [r4, #12]
-    27aa:	9b00      	ldr	r3, [sp, #0]
-    27ac:	2b02      	cmp	r3, #2
-    27ae:	d05a      	beq.n	2866 <setvbuf+0x132>
-    27b0:	ab03      	add	r3, sp, #12
-    27b2:	aa02      	add	r2, sp, #8
-    27b4:	0021      	movs	r1, r4
-    27b6:	0030      	movs	r0, r6
-    27b8:	f000 f9f6 	bl	2ba8 <__swhatbuf_r>
-    27bc:	89a3      	ldrh	r3, [r4, #12]
-    27be:	4318      	orrs	r0, r3
-    27c0:	81a0      	strh	r0, [r4, #12]
-    27c2:	2d00      	cmp	r5, #0
-    27c4:	d124      	bne.n	2810 <setvbuf+0xdc>
-    27c6:	9d02      	ldr	r5, [sp, #8]
-    27c8:	0028      	movs	r0, r5
-    27ca:	f000 fa59 	bl	2c80 <malloc>
-    27ce:	9501      	str	r5, [sp, #4]
-    27d0:	1e07      	subs	r7, r0, #0
-    27d2:	d142      	bne.n	285a <setvbuf+0x126>
-    27d4:	9b02      	ldr	r3, [sp, #8]
-    27d6:	9301      	str	r3, [sp, #4]
-    27d8:	42ab      	cmp	r3, r5
-    27da:	d139      	bne.n	2850 <setvbuf+0x11c>
-    27dc:	2001      	movs	r0, #1
-    27de:	4240      	negs	r0, r0
-    27e0:	2302      	movs	r3, #2
-    27e2:	89a2      	ldrh	r2, [r4, #12]
-    27e4:	4313      	orrs	r3, r2
-    27e6:	81a3      	strh	r3, [r4, #12]
-    27e8:	2300      	movs	r3, #0
-    27ea:	60a3      	str	r3, [r4, #8]
-    27ec:	0023      	movs	r3, r4
-    27ee:	3347      	adds	r3, #71	; 0x47
-    27f0:	6023      	str	r3, [r4, #0]
-    27f2:	6123      	str	r3, [r4, #16]
-    27f4:	2301      	movs	r3, #1
-    27f6:	6163      	str	r3, [r4, #20]
-    27f8:	b005      	add	sp, #20
-    27fa:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    27fc:	4b21      	ldr	r3, [pc, #132]	; (2884 <setvbuf+0x150>)
-    27fe:	429c      	cmp	r4, r3
-    2800:	d101      	bne.n	2806 <setvbuf+0xd2>
-    2802:	68b4      	ldr	r4, [r6, #8]
-    2804:	e7aa      	b.n	275c <setvbuf+0x28>
-    2806:	4b20      	ldr	r3, [pc, #128]	; (2888 <setvbuf+0x154>)
-    2808:	429c      	cmp	r4, r3
-    280a:	d1a7      	bne.n	275c <setvbuf+0x28>
-    280c:	68f4      	ldr	r4, [r6, #12]
-    280e:	e7a5      	b.n	275c <setvbuf+0x28>
-    2810:	2f00      	cmp	r7, #0
-    2812:	d0d9      	beq.n	27c8 <setvbuf+0x94>
-    2814:	69b3      	ldr	r3, [r6, #24]
-    2816:	2b00      	cmp	r3, #0
-    2818:	d102      	bne.n	2820 <setvbuf+0xec>
-    281a:	0030      	movs	r0, r6
-    281c:	f000 f92e 	bl	2a7c <__sinit>
-    2820:	9b00      	ldr	r3, [sp, #0]
-    2822:	2b01      	cmp	r3, #1
-    2824:	d103      	bne.n	282e <setvbuf+0xfa>
-    2826:	89a3      	ldrh	r3, [r4, #12]
-    2828:	9a00      	ldr	r2, [sp, #0]
-    282a:	431a      	orrs	r2, r3
-    282c:	81a2      	strh	r2, [r4, #12]
-    282e:	2008      	movs	r0, #8
-    2830:	89a3      	ldrh	r3, [r4, #12]
-    2832:	6027      	str	r7, [r4, #0]
-    2834:	6127      	str	r7, [r4, #16]
-    2836:	6165      	str	r5, [r4, #20]
-    2838:	4018      	ands	r0, r3
-    283a:	d018      	beq.n	286e <setvbuf+0x13a>
-    283c:	2001      	movs	r0, #1
-    283e:	4018      	ands	r0, r3
-    2840:	2300      	movs	r3, #0
-    2842:	4298      	cmp	r0, r3
-    2844:	d011      	beq.n	286a <setvbuf+0x136>
-    2846:	426d      	negs	r5, r5
-    2848:	60a3      	str	r3, [r4, #8]
-    284a:	61a5      	str	r5, [r4, #24]
-    284c:	0018      	movs	r0, r3
-    284e:	e7d3      	b.n	27f8 <setvbuf+0xc4>
-    2850:	9801      	ldr	r0, [sp, #4]
-    2852:	f000 fa15 	bl	2c80 <malloc>
-    2856:	1e07      	subs	r7, r0, #0
-    2858:	d0c0      	beq.n	27dc <setvbuf+0xa8>
-    285a:	2380      	movs	r3, #128	; 0x80
-    285c:	89a2      	ldrh	r2, [r4, #12]
-    285e:	9d01      	ldr	r5, [sp, #4]
-    2860:	4313      	orrs	r3, r2
-    2862:	81a3      	strh	r3, [r4, #12]
-    2864:	e7d6      	b.n	2814 <setvbuf+0xe0>
-    2866:	2000      	movs	r0, #0
-    2868:	e7ba      	b.n	27e0 <setvbuf+0xac>
-    286a:	60a5      	str	r5, [r4, #8]
-    286c:	e7c4      	b.n	27f8 <setvbuf+0xc4>
-    286e:	60a0      	str	r0, [r4, #8]
-    2870:	e7c2      	b.n	27f8 <setvbuf+0xc4>
-    2872:	2001      	movs	r0, #1
-    2874:	4240      	negs	r0, r0
-    2876:	e7bf      	b.n	27f8 <setvbuf+0xc4>
-    2878:	20000018 	.word	0x20000018
-    287c:	000038cc 	.word	0x000038cc
-    2880:	fffff35c 	.word	0xfffff35c
-    2884:	000038ec 	.word	0x000038ec
-    2888:	000038ac 	.word	0x000038ac
-
-0000288c <__sflush_r>:
-    288c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    288e:	898a      	ldrh	r2, [r1, #12]
-    2890:	0005      	movs	r5, r0
-    2892:	000c      	movs	r4, r1
-    2894:	0713      	lsls	r3, r2, #28
-    2896:	d460      	bmi.n	295a <__sflush_r+0xce>
-    2898:	684b      	ldr	r3, [r1, #4]
-    289a:	2b00      	cmp	r3, #0
-    289c:	dc04      	bgt.n	28a8 <__sflush_r+0x1c>
-    289e:	6c0b      	ldr	r3, [r1, #64]	; 0x40
-    28a0:	2b00      	cmp	r3, #0
-    28a2:	dc01      	bgt.n	28a8 <__sflush_r+0x1c>
-    28a4:	2000      	movs	r0, #0
-    28a6:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    28a8:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
-    28aa:	2f00      	cmp	r7, #0
-    28ac:	d0fa      	beq.n	28a4 <__sflush_r+0x18>
-    28ae:	2300      	movs	r3, #0
-    28b0:	682e      	ldr	r6, [r5, #0]
-    28b2:	602b      	str	r3, [r5, #0]
-    28b4:	2380      	movs	r3, #128	; 0x80
-    28b6:	015b      	lsls	r3, r3, #5
-    28b8:	401a      	ands	r2, r3
-    28ba:	d034      	beq.n	2926 <__sflush_r+0x9a>
-    28bc:	6d60      	ldr	r0, [r4, #84]	; 0x54
-    28be:	89a3      	ldrh	r3, [r4, #12]
-    28c0:	075b      	lsls	r3, r3, #29
-    28c2:	d506      	bpl.n	28d2 <__sflush_r+0x46>
-    28c4:	6863      	ldr	r3, [r4, #4]
-    28c6:	1ac0      	subs	r0, r0, r3
-    28c8:	6b63      	ldr	r3, [r4, #52]	; 0x34
-    28ca:	2b00      	cmp	r3, #0
-    28cc:	d001      	beq.n	28d2 <__sflush_r+0x46>
-    28ce:	6c23      	ldr	r3, [r4, #64]	; 0x40
-    28d0:	1ac0      	subs	r0, r0, r3
-    28d2:	0002      	movs	r2, r0
-    28d4:	6a21      	ldr	r1, [r4, #32]
-    28d6:	2300      	movs	r3, #0
-    28d8:	0028      	movs	r0, r5
-    28da:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
-    28dc:	47b8      	blx	r7
-    28de:	89a1      	ldrh	r1, [r4, #12]
-    28e0:	1c43      	adds	r3, r0, #1
-    28e2:	d106      	bne.n	28f2 <__sflush_r+0x66>
-    28e4:	682b      	ldr	r3, [r5, #0]
-    28e6:	2b1d      	cmp	r3, #29
-    28e8:	d831      	bhi.n	294e <__sflush_r+0xc2>
-    28ea:	4a2c      	ldr	r2, [pc, #176]	; (299c <__sflush_r+0x110>)
-    28ec:	40da      	lsrs	r2, r3
-    28ee:	07d3      	lsls	r3, r2, #31
-    28f0:	d52d      	bpl.n	294e <__sflush_r+0xc2>
-    28f2:	2300      	movs	r3, #0
-    28f4:	6063      	str	r3, [r4, #4]
-    28f6:	6923      	ldr	r3, [r4, #16]
-    28f8:	6023      	str	r3, [r4, #0]
-    28fa:	04cb      	lsls	r3, r1, #19
-    28fc:	d505      	bpl.n	290a <__sflush_r+0x7e>
-    28fe:	1c43      	adds	r3, r0, #1
-    2900:	d102      	bne.n	2908 <__sflush_r+0x7c>
-    2902:	682b      	ldr	r3, [r5, #0]
-    2904:	2b00      	cmp	r3, #0
-    2906:	d100      	bne.n	290a <__sflush_r+0x7e>
-    2908:	6560      	str	r0, [r4, #84]	; 0x54
-    290a:	6b61      	ldr	r1, [r4, #52]	; 0x34
-    290c:	602e      	str	r6, [r5, #0]
-    290e:	2900      	cmp	r1, #0
-    2910:	d0c8      	beq.n	28a4 <__sflush_r+0x18>
-    2912:	0023      	movs	r3, r4
-    2914:	3344      	adds	r3, #68	; 0x44
-    2916:	4299      	cmp	r1, r3
-    2918:	d002      	beq.n	2920 <__sflush_r+0x94>
-    291a:	0028      	movs	r0, r5
-    291c:	f000 f9ba 	bl	2c94 <_free_r>
-    2920:	2000      	movs	r0, #0
-    2922:	6360      	str	r0, [r4, #52]	; 0x34
-    2924:	e7bf      	b.n	28a6 <__sflush_r+0x1a>
-    2926:	2301      	movs	r3, #1
-    2928:	6a21      	ldr	r1, [r4, #32]
-    292a:	0028      	movs	r0, r5
-    292c:	47b8      	blx	r7
-    292e:	1c43      	adds	r3, r0, #1
-    2930:	d1c5      	bne.n	28be <__sflush_r+0x32>
-    2932:	682b      	ldr	r3, [r5, #0]
-    2934:	2b00      	cmp	r3, #0
-    2936:	d0c2      	beq.n	28be <__sflush_r+0x32>
-    2938:	2b1d      	cmp	r3, #29
-    293a:	d001      	beq.n	2940 <__sflush_r+0xb4>
-    293c:	2b16      	cmp	r3, #22
-    293e:	d101      	bne.n	2944 <__sflush_r+0xb8>
-    2940:	602e      	str	r6, [r5, #0]
-    2942:	e7af      	b.n	28a4 <__sflush_r+0x18>
-    2944:	2340      	movs	r3, #64	; 0x40
-    2946:	89a2      	ldrh	r2, [r4, #12]
-    2948:	4313      	orrs	r3, r2
-    294a:	81a3      	strh	r3, [r4, #12]
-    294c:	e7ab      	b.n	28a6 <__sflush_r+0x1a>
-    294e:	2340      	movs	r3, #64	; 0x40
-    2950:	430b      	orrs	r3, r1
-    2952:	2001      	movs	r0, #1
-    2954:	81a3      	strh	r3, [r4, #12]
-    2956:	4240      	negs	r0, r0
-    2958:	e7a5      	b.n	28a6 <__sflush_r+0x1a>
-    295a:	690f      	ldr	r7, [r1, #16]
-    295c:	2f00      	cmp	r7, #0
-    295e:	d0a1      	beq.n	28a4 <__sflush_r+0x18>
-    2960:	680b      	ldr	r3, [r1, #0]
-    2962:	600f      	str	r7, [r1, #0]
-    2964:	1bdb      	subs	r3, r3, r7
-    2966:	9301      	str	r3, [sp, #4]
-    2968:	2300      	movs	r3, #0
-    296a:	0792      	lsls	r2, r2, #30
-    296c:	d100      	bne.n	2970 <__sflush_r+0xe4>
-    296e:	694b      	ldr	r3, [r1, #20]
-    2970:	60a3      	str	r3, [r4, #8]
-    2972:	9b01      	ldr	r3, [sp, #4]
-    2974:	2b00      	cmp	r3, #0
-    2976:	dc00      	bgt.n	297a <__sflush_r+0xee>
-    2978:	e794      	b.n	28a4 <__sflush_r+0x18>
-    297a:	9b01      	ldr	r3, [sp, #4]
-    297c:	003a      	movs	r2, r7
-    297e:	6a21      	ldr	r1, [r4, #32]
-    2980:	0028      	movs	r0, r5
-    2982:	6aa6      	ldr	r6, [r4, #40]	; 0x28
-    2984:	47b0      	blx	r6
-    2986:	2800      	cmp	r0, #0
-    2988:	dc03      	bgt.n	2992 <__sflush_r+0x106>
-    298a:	2340      	movs	r3, #64	; 0x40
-    298c:	89a2      	ldrh	r2, [r4, #12]
-    298e:	4313      	orrs	r3, r2
-    2990:	e7df      	b.n	2952 <__sflush_r+0xc6>
-    2992:	9b01      	ldr	r3, [sp, #4]
-    2994:	183f      	adds	r7, r7, r0
-    2996:	1a1b      	subs	r3, r3, r0
-    2998:	9301      	str	r3, [sp, #4]
-    299a:	e7ea      	b.n	2972 <__sflush_r+0xe6>
-    299c:	20400001 	.word	0x20400001
-
-000029a0 <_fflush_r>:
-    29a0:	690b      	ldr	r3, [r1, #16]
-    29a2:	b570      	push	{r4, r5, r6, lr}
-    29a4:	0005      	movs	r5, r0
-    29a6:	000c      	movs	r4, r1
-    29a8:	2b00      	cmp	r3, #0
-    29aa:	d101      	bne.n	29b0 <_fflush_r+0x10>
-    29ac:	2000      	movs	r0, #0
-    29ae:	bd70      	pop	{r4, r5, r6, pc}
-    29b0:	2800      	cmp	r0, #0
-    29b2:	d004      	beq.n	29be <_fflush_r+0x1e>
-    29b4:	6983      	ldr	r3, [r0, #24]
-    29b6:	2b00      	cmp	r3, #0
-    29b8:	d101      	bne.n	29be <_fflush_r+0x1e>
-    29ba:	f000 f85f 	bl	2a7c <__sinit>
-    29be:	4b0b      	ldr	r3, [pc, #44]	; (29ec <_fflush_r+0x4c>)
-    29c0:	429c      	cmp	r4, r3
-    29c2:	d109      	bne.n	29d8 <_fflush_r+0x38>
-    29c4:	686c      	ldr	r4, [r5, #4]
-    29c6:	220c      	movs	r2, #12
-    29c8:	5ea3      	ldrsh	r3, [r4, r2]
-    29ca:	2b00      	cmp	r3, #0
-    29cc:	d0ee      	beq.n	29ac <_fflush_r+0xc>
-    29ce:	0021      	movs	r1, r4
-    29d0:	0028      	movs	r0, r5
-    29d2:	f7ff ff5b 	bl	288c <__sflush_r>
-    29d6:	e7ea      	b.n	29ae <_fflush_r+0xe>
-    29d8:	4b05      	ldr	r3, [pc, #20]	; (29f0 <_fflush_r+0x50>)
-    29da:	429c      	cmp	r4, r3
-    29dc:	d101      	bne.n	29e2 <_fflush_r+0x42>
-    29de:	68ac      	ldr	r4, [r5, #8]
-    29e0:	e7f1      	b.n	29c6 <_fflush_r+0x26>
-    29e2:	4b04      	ldr	r3, [pc, #16]	; (29f4 <_fflush_r+0x54>)
-    29e4:	429c      	cmp	r4, r3
-    29e6:	d1ee      	bne.n	29c6 <_fflush_r+0x26>
-    29e8:	68ec      	ldr	r4, [r5, #12]
-    29ea:	e7ec      	b.n	29c6 <_fflush_r+0x26>
-    29ec:	000038cc 	.word	0x000038cc
-    29f0:	000038ec 	.word	0x000038ec
-    29f4:	000038ac 	.word	0x000038ac
-
-000029f8 <_cleanup_r>:
-    29f8:	b510      	push	{r4, lr}
-    29fa:	4902      	ldr	r1, [pc, #8]	; (2a04 <_cleanup_r+0xc>)
-    29fc:	f000 f8b2 	bl	2b64 <_fwalk_reent>
-    2a00:	bd10      	pop	{r4, pc}
-    2a02:	46c0      	nop			; (mov r8, r8)
-    2a04:	000029a1 	.word	0x000029a1
-
-00002a08 <std.isra.0>:
-    2a08:	2300      	movs	r3, #0
-    2a0a:	b510      	push	{r4, lr}
-    2a0c:	0004      	movs	r4, r0
-    2a0e:	6003      	str	r3, [r0, #0]
-    2a10:	6043      	str	r3, [r0, #4]
-    2a12:	6083      	str	r3, [r0, #8]
-    2a14:	8181      	strh	r1, [r0, #12]
-    2a16:	6643      	str	r3, [r0, #100]	; 0x64
-    2a18:	81c2      	strh	r2, [r0, #14]
-    2a1a:	6103      	str	r3, [r0, #16]
-    2a1c:	6143      	str	r3, [r0, #20]
-    2a1e:	6183      	str	r3, [r0, #24]
-    2a20:	0019      	movs	r1, r3
-    2a22:	2208      	movs	r2, #8
-    2a24:	305c      	adds	r0, #92	; 0x5c
-    2a26:	f7ff fe58 	bl	26da <memset>
-    2a2a:	4b05      	ldr	r3, [pc, #20]	; (2a40 <std.isra.0+0x38>)
-    2a2c:	6224      	str	r4, [r4, #32]
-    2a2e:	6263      	str	r3, [r4, #36]	; 0x24
-    2a30:	4b04      	ldr	r3, [pc, #16]	; (2a44 <std.isra.0+0x3c>)
-    2a32:	62a3      	str	r3, [r4, #40]	; 0x28
-    2a34:	4b04      	ldr	r3, [pc, #16]	; (2a48 <std.isra.0+0x40>)
-    2a36:	62e3      	str	r3, [r4, #44]	; 0x2c
-    2a38:	4b04      	ldr	r3, [pc, #16]	; (2a4c <std.isra.0+0x44>)
-    2a3a:	6323      	str	r3, [r4, #48]	; 0x30
-    2a3c:	bd10      	pop	{r4, pc}
-    2a3e:	46c0      	nop			; (mov r8, r8)
-    2a40:	000033a1 	.word	0x000033a1
-    2a44:	000033c9 	.word	0x000033c9
-    2a48:	00003401 	.word	0x00003401
-    2a4c:	0000342d 	.word	0x0000342d
-
-00002a50 <__sfmoreglue>:
-    2a50:	b570      	push	{r4, r5, r6, lr}
-    2a52:	2568      	movs	r5, #104	; 0x68
-    2a54:	1e4a      	subs	r2, r1, #1
-    2a56:	4355      	muls	r5, r2
-    2a58:	000e      	movs	r6, r1
-    2a5a:	0029      	movs	r1, r5
-    2a5c:	3174      	adds	r1, #116	; 0x74
-    2a5e:	f000 f963 	bl	2d28 <_malloc_r>
-    2a62:	1e04      	subs	r4, r0, #0
-    2a64:	d008      	beq.n	2a78 <__sfmoreglue+0x28>
-    2a66:	2100      	movs	r1, #0
-    2a68:	002a      	movs	r2, r5
-    2a6a:	6001      	str	r1, [r0, #0]
-    2a6c:	6046      	str	r6, [r0, #4]
-    2a6e:	300c      	adds	r0, #12
-    2a70:	60a0      	str	r0, [r4, #8]
-    2a72:	3268      	adds	r2, #104	; 0x68
-    2a74:	f7ff fe31 	bl	26da <memset>
-    2a78:	0020      	movs	r0, r4
-    2a7a:	bd70      	pop	{r4, r5, r6, pc}
-
-00002a7c <__sinit>:
-    2a7c:	6983      	ldr	r3, [r0, #24]
-    2a7e:	b513      	push	{r0, r1, r4, lr}
-    2a80:	0004      	movs	r4, r0
-    2a82:	2b00      	cmp	r3, #0
-    2a84:	d128      	bne.n	2ad8 <__sinit+0x5c>
-    2a86:	6483      	str	r3, [r0, #72]	; 0x48
-    2a88:	64c3      	str	r3, [r0, #76]	; 0x4c
-    2a8a:	6503      	str	r3, [r0, #80]	; 0x50
-    2a8c:	4b13      	ldr	r3, [pc, #76]	; (2adc <__sinit+0x60>)
-    2a8e:	4a14      	ldr	r2, [pc, #80]	; (2ae0 <__sinit+0x64>)
-    2a90:	681b      	ldr	r3, [r3, #0]
-    2a92:	6282      	str	r2, [r0, #40]	; 0x28
-    2a94:	9301      	str	r3, [sp, #4]
-    2a96:	4298      	cmp	r0, r3
-    2a98:	d101      	bne.n	2a9e <__sinit+0x22>
-    2a9a:	2301      	movs	r3, #1
-    2a9c:	6183      	str	r3, [r0, #24]
-    2a9e:	0020      	movs	r0, r4
-    2aa0:	f000 f820 	bl	2ae4 <__sfp>
-    2aa4:	6060      	str	r0, [r4, #4]
-    2aa6:	0020      	movs	r0, r4
-    2aa8:	f000 f81c 	bl	2ae4 <__sfp>
-    2aac:	60a0      	str	r0, [r4, #8]
-    2aae:	0020      	movs	r0, r4
-    2ab0:	f000 f818 	bl	2ae4 <__sfp>
-    2ab4:	2200      	movs	r2, #0
-    2ab6:	60e0      	str	r0, [r4, #12]
-    2ab8:	2104      	movs	r1, #4
-    2aba:	6860      	ldr	r0, [r4, #4]
-    2abc:	f7ff ffa4 	bl	2a08 <std.isra.0>
-    2ac0:	2201      	movs	r2, #1
-    2ac2:	2109      	movs	r1, #9
-    2ac4:	68a0      	ldr	r0, [r4, #8]
-    2ac6:	f7ff ff9f 	bl	2a08 <std.isra.0>
-    2aca:	2202      	movs	r2, #2
-    2acc:	2112      	movs	r1, #18
-    2ace:	68e0      	ldr	r0, [r4, #12]
-    2ad0:	f7ff ff9a 	bl	2a08 <std.isra.0>
-    2ad4:	2301      	movs	r3, #1
-    2ad6:	61a3      	str	r3, [r4, #24]
-    2ad8:	bd13      	pop	{r0, r1, r4, pc}
-    2ada:	46c0      	nop			; (mov r8, r8)
-    2adc:	000038a8 	.word	0x000038a8
-    2ae0:	000029f9 	.word	0x000029f9
-
-00002ae4 <__sfp>:
-    2ae4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    2ae6:	4b1e      	ldr	r3, [pc, #120]	; (2b60 <__sfp+0x7c>)
-    2ae8:	0007      	movs	r7, r0
-    2aea:	681e      	ldr	r6, [r3, #0]
-    2aec:	69b3      	ldr	r3, [r6, #24]
-    2aee:	2b00      	cmp	r3, #0
-    2af0:	d102      	bne.n	2af8 <__sfp+0x14>
-    2af2:	0030      	movs	r0, r6
-    2af4:	f7ff ffc2 	bl	2a7c <__sinit>
-    2af8:	3648      	adds	r6, #72	; 0x48
-    2afa:	68b4      	ldr	r4, [r6, #8]
-    2afc:	6873      	ldr	r3, [r6, #4]
-    2afe:	3b01      	subs	r3, #1
-    2b00:	d504      	bpl.n	2b0c <__sfp+0x28>
-    2b02:	6833      	ldr	r3, [r6, #0]
-    2b04:	2b00      	cmp	r3, #0
-    2b06:	d007      	beq.n	2b18 <__sfp+0x34>
-    2b08:	6836      	ldr	r6, [r6, #0]
-    2b0a:	e7f6      	b.n	2afa <__sfp+0x16>
-    2b0c:	220c      	movs	r2, #12
-    2b0e:	5ea5      	ldrsh	r5, [r4, r2]
-    2b10:	2d00      	cmp	r5, #0
-    2b12:	d00d      	beq.n	2b30 <__sfp+0x4c>
-    2b14:	3468      	adds	r4, #104	; 0x68
-    2b16:	e7f2      	b.n	2afe <__sfp+0x1a>
-    2b18:	2104      	movs	r1, #4
-    2b1a:	0038      	movs	r0, r7
-    2b1c:	f7ff ff98 	bl	2a50 <__sfmoreglue>
-    2b20:	6030      	str	r0, [r6, #0]
-    2b22:	2800      	cmp	r0, #0
-    2b24:	d1f0      	bne.n	2b08 <__sfp+0x24>
-    2b26:	230c      	movs	r3, #12
-    2b28:	0004      	movs	r4, r0
-    2b2a:	603b      	str	r3, [r7, #0]
-    2b2c:	0020      	movs	r0, r4
-    2b2e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    2b30:	2301      	movs	r3, #1
-    2b32:	0020      	movs	r0, r4
-    2b34:	425b      	negs	r3, r3
-    2b36:	81e3      	strh	r3, [r4, #14]
-    2b38:	3302      	adds	r3, #2
-    2b3a:	81a3      	strh	r3, [r4, #12]
-    2b3c:	6665      	str	r5, [r4, #100]	; 0x64
-    2b3e:	6025      	str	r5, [r4, #0]
-    2b40:	60a5      	str	r5, [r4, #8]
-    2b42:	6065      	str	r5, [r4, #4]
-    2b44:	6125      	str	r5, [r4, #16]
-    2b46:	6165      	str	r5, [r4, #20]
-    2b48:	61a5      	str	r5, [r4, #24]
-    2b4a:	2208      	movs	r2, #8
-    2b4c:	0029      	movs	r1, r5
-    2b4e:	305c      	adds	r0, #92	; 0x5c
-    2b50:	f7ff fdc3 	bl	26da <memset>
-    2b54:	6365      	str	r5, [r4, #52]	; 0x34
-    2b56:	63a5      	str	r5, [r4, #56]	; 0x38
-    2b58:	64a5      	str	r5, [r4, #72]	; 0x48
-    2b5a:	64e5      	str	r5, [r4, #76]	; 0x4c
-    2b5c:	e7e6      	b.n	2b2c <__sfp+0x48>
-    2b5e:	46c0      	nop			; (mov r8, r8)
-    2b60:	000038a8 	.word	0x000038a8
-
-00002b64 <_fwalk_reent>:
-    2b64:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    2b66:	0004      	movs	r4, r0
-    2b68:	0007      	movs	r7, r0
-    2b6a:	2600      	movs	r6, #0
-    2b6c:	9101      	str	r1, [sp, #4]
-    2b6e:	3448      	adds	r4, #72	; 0x48
-    2b70:	2c00      	cmp	r4, #0
-    2b72:	d101      	bne.n	2b78 <_fwalk_reent+0x14>
-    2b74:	0030      	movs	r0, r6
-    2b76:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    2b78:	6863      	ldr	r3, [r4, #4]
-    2b7a:	68a5      	ldr	r5, [r4, #8]
-    2b7c:	9300      	str	r3, [sp, #0]
-    2b7e:	9b00      	ldr	r3, [sp, #0]
-    2b80:	3b01      	subs	r3, #1
-    2b82:	9300      	str	r3, [sp, #0]
-    2b84:	d501      	bpl.n	2b8a <_fwalk_reent+0x26>
-    2b86:	6824      	ldr	r4, [r4, #0]
-    2b88:	e7f2      	b.n	2b70 <_fwalk_reent+0xc>
-    2b8a:	89ab      	ldrh	r3, [r5, #12]
-    2b8c:	2b01      	cmp	r3, #1
-    2b8e:	d908      	bls.n	2ba2 <_fwalk_reent+0x3e>
-    2b90:	220e      	movs	r2, #14
-    2b92:	5eab      	ldrsh	r3, [r5, r2]
-    2b94:	3301      	adds	r3, #1
-    2b96:	d004      	beq.n	2ba2 <_fwalk_reent+0x3e>
-    2b98:	0029      	movs	r1, r5
-    2b9a:	0038      	movs	r0, r7
-    2b9c:	9b01      	ldr	r3, [sp, #4]
-    2b9e:	4798      	blx	r3
-    2ba0:	4306      	orrs	r6, r0
-    2ba2:	3568      	adds	r5, #104	; 0x68
-    2ba4:	e7eb      	b.n	2b7e <_fwalk_reent+0x1a>
-	...
-
-00002ba8 <__swhatbuf_r>:
-    2ba8:	b570      	push	{r4, r5, r6, lr}
-    2baa:	000e      	movs	r6, r1
-    2bac:	001d      	movs	r5, r3
-    2bae:	230e      	movs	r3, #14
-    2bb0:	5ec9      	ldrsh	r1, [r1, r3]
-    2bb2:	b090      	sub	sp, #64	; 0x40
-    2bb4:	0014      	movs	r4, r2
-    2bb6:	2900      	cmp	r1, #0
-    2bb8:	da07      	bge.n	2bca <__swhatbuf_r+0x22>
-    2bba:	2300      	movs	r3, #0
-    2bbc:	602b      	str	r3, [r5, #0]
-    2bbe:	89b3      	ldrh	r3, [r6, #12]
-    2bc0:	061b      	lsls	r3, r3, #24
-    2bc2:	d411      	bmi.n	2be8 <__swhatbuf_r+0x40>
-    2bc4:	2380      	movs	r3, #128	; 0x80
-    2bc6:	00db      	lsls	r3, r3, #3
-    2bc8:	e00f      	b.n	2bea <__swhatbuf_r+0x42>
-    2bca:	aa01      	add	r2, sp, #4
-    2bcc:	f000 fd26 	bl	361c <_fstat_r>
-    2bd0:	2800      	cmp	r0, #0
-    2bd2:	dbf2      	blt.n	2bba <__swhatbuf_r+0x12>
-    2bd4:	22f0      	movs	r2, #240	; 0xf0
-    2bd6:	9b02      	ldr	r3, [sp, #8]
-    2bd8:	0212      	lsls	r2, r2, #8
-    2bda:	4013      	ands	r3, r2
-    2bdc:	4a05      	ldr	r2, [pc, #20]	; (2bf4 <__swhatbuf_r+0x4c>)
-    2bde:	189b      	adds	r3, r3, r2
-    2be0:	425a      	negs	r2, r3
-    2be2:	4153      	adcs	r3, r2
-    2be4:	602b      	str	r3, [r5, #0]
-    2be6:	e7ed      	b.n	2bc4 <__swhatbuf_r+0x1c>
-    2be8:	2340      	movs	r3, #64	; 0x40
-    2bea:	2000      	movs	r0, #0
-    2bec:	6023      	str	r3, [r4, #0]
-    2bee:	b010      	add	sp, #64	; 0x40
-    2bf0:	bd70      	pop	{r4, r5, r6, pc}
-    2bf2:	46c0      	nop			; (mov r8, r8)
-    2bf4:	ffffe000 	.word	0xffffe000
-
-00002bf8 <__smakebuf_r>:
-    2bf8:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    2bfa:	2602      	movs	r6, #2
-    2bfc:	898b      	ldrh	r3, [r1, #12]
-    2bfe:	0005      	movs	r5, r0
-    2c00:	000c      	movs	r4, r1
-    2c02:	4233      	tst	r3, r6
-    2c04:	d006      	beq.n	2c14 <__smakebuf_r+0x1c>
-    2c06:	0023      	movs	r3, r4
-    2c08:	3347      	adds	r3, #71	; 0x47
-    2c0a:	6023      	str	r3, [r4, #0]
-    2c0c:	6123      	str	r3, [r4, #16]
-    2c0e:	2301      	movs	r3, #1
-    2c10:	6163      	str	r3, [r4, #20]
-    2c12:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
-    2c14:	ab01      	add	r3, sp, #4
-    2c16:	466a      	mov	r2, sp
-    2c18:	f7ff ffc6 	bl	2ba8 <__swhatbuf_r>
-    2c1c:	9900      	ldr	r1, [sp, #0]
-    2c1e:	0007      	movs	r7, r0
-    2c20:	0028      	movs	r0, r5
-    2c22:	f000 f881 	bl	2d28 <_malloc_r>
-    2c26:	2800      	cmp	r0, #0
-    2c28:	d108      	bne.n	2c3c <__smakebuf_r+0x44>
-    2c2a:	220c      	movs	r2, #12
-    2c2c:	5ea3      	ldrsh	r3, [r4, r2]
-    2c2e:	059a      	lsls	r2, r3, #22
-    2c30:	d4ef      	bmi.n	2c12 <__smakebuf_r+0x1a>
-    2c32:	2203      	movs	r2, #3
-    2c34:	4393      	bics	r3, r2
-    2c36:	431e      	orrs	r6, r3
-    2c38:	81a6      	strh	r6, [r4, #12]
-    2c3a:	e7e4      	b.n	2c06 <__smakebuf_r+0xe>
-    2c3c:	4b0f      	ldr	r3, [pc, #60]	; (2c7c <__smakebuf_r+0x84>)
-    2c3e:	62ab      	str	r3, [r5, #40]	; 0x28
-    2c40:	2380      	movs	r3, #128	; 0x80
-    2c42:	89a2      	ldrh	r2, [r4, #12]
-    2c44:	6020      	str	r0, [r4, #0]
-    2c46:	4313      	orrs	r3, r2
-    2c48:	81a3      	strh	r3, [r4, #12]
-    2c4a:	9b00      	ldr	r3, [sp, #0]
-    2c4c:	6120      	str	r0, [r4, #16]
-    2c4e:	6163      	str	r3, [r4, #20]
-    2c50:	9b01      	ldr	r3, [sp, #4]
-    2c52:	2b00      	cmp	r3, #0
-    2c54:	d00d      	beq.n	2c72 <__smakebuf_r+0x7a>
-    2c56:	230e      	movs	r3, #14
-    2c58:	5ee1      	ldrsh	r1, [r4, r3]
-    2c5a:	0028      	movs	r0, r5
-    2c5c:	f000 fcf0 	bl	3640 <_isatty_r>
-    2c60:	2800      	cmp	r0, #0
-    2c62:	d006      	beq.n	2c72 <__smakebuf_r+0x7a>
-    2c64:	2203      	movs	r2, #3
-    2c66:	89a3      	ldrh	r3, [r4, #12]
-    2c68:	4393      	bics	r3, r2
-    2c6a:	001a      	movs	r2, r3
-    2c6c:	2301      	movs	r3, #1
-    2c6e:	4313      	orrs	r3, r2
-    2c70:	81a3      	strh	r3, [r4, #12]
-    2c72:	89a0      	ldrh	r0, [r4, #12]
-    2c74:	4338      	orrs	r0, r7
-    2c76:	81a0      	strh	r0, [r4, #12]
-    2c78:	e7cb      	b.n	2c12 <__smakebuf_r+0x1a>
-    2c7a:	46c0      	nop			; (mov r8, r8)
-    2c7c:	000029f9 	.word	0x000029f9
-
-00002c80 <malloc>:
-    2c80:	b510      	push	{r4, lr}
-    2c82:	4b03      	ldr	r3, [pc, #12]	; (2c90 <malloc+0x10>)
-    2c84:	0001      	movs	r1, r0
-    2c86:	6818      	ldr	r0, [r3, #0]
-    2c88:	f000 f84e 	bl	2d28 <_malloc_r>
-    2c8c:	bd10      	pop	{r4, pc}
-    2c8e:	46c0      	nop			; (mov r8, r8)
-    2c90:	20000018 	.word	0x20000018
-
-00002c94 <_free_r>:
-    2c94:	b570      	push	{r4, r5, r6, lr}
-    2c96:	0005      	movs	r5, r0
-    2c98:	2900      	cmp	r1, #0
-    2c9a:	d010      	beq.n	2cbe <_free_r+0x2a>
-    2c9c:	1f0c      	subs	r4, r1, #4
-    2c9e:	6823      	ldr	r3, [r4, #0]
-    2ca0:	2b00      	cmp	r3, #0
-    2ca2:	da00      	bge.n	2ca6 <_free_r+0x12>
-    2ca4:	18e4      	adds	r4, r4, r3
-    2ca6:	0028      	movs	r0, r5
-    2ca8:	f000 fcfb 	bl	36a2 <__malloc_lock>
-    2cac:	4a1d      	ldr	r2, [pc, #116]	; (2d24 <_free_r+0x90>)
-    2cae:	6813      	ldr	r3, [r2, #0]
-    2cb0:	2b00      	cmp	r3, #0
-    2cb2:	d105      	bne.n	2cc0 <_free_r+0x2c>
-    2cb4:	6063      	str	r3, [r4, #4]
-    2cb6:	6014      	str	r4, [r2, #0]
-    2cb8:	0028      	movs	r0, r5
-    2cba:	f000 fcf3 	bl	36a4 <__malloc_unlock>
-    2cbe:	bd70      	pop	{r4, r5, r6, pc}
-    2cc0:	42a3      	cmp	r3, r4
-    2cc2:	d909      	bls.n	2cd8 <_free_r+0x44>
-    2cc4:	6821      	ldr	r1, [r4, #0]
-    2cc6:	1860      	adds	r0, r4, r1
-    2cc8:	4283      	cmp	r3, r0
-    2cca:	d1f3      	bne.n	2cb4 <_free_r+0x20>
-    2ccc:	6818      	ldr	r0, [r3, #0]
-    2cce:	685b      	ldr	r3, [r3, #4]
-    2cd0:	1841      	adds	r1, r0, r1
-    2cd2:	6021      	str	r1, [r4, #0]
-    2cd4:	e7ee      	b.n	2cb4 <_free_r+0x20>
-    2cd6:	0013      	movs	r3, r2
-    2cd8:	685a      	ldr	r2, [r3, #4]
-    2cda:	2a00      	cmp	r2, #0
-    2cdc:	d001      	beq.n	2ce2 <_free_r+0x4e>
-    2cde:	42a2      	cmp	r2, r4
-    2ce0:	d9f9      	bls.n	2cd6 <_free_r+0x42>
-    2ce2:	6819      	ldr	r1, [r3, #0]
-    2ce4:	1858      	adds	r0, r3, r1
-    2ce6:	42a0      	cmp	r0, r4
-    2ce8:	d10b      	bne.n	2d02 <_free_r+0x6e>
-    2cea:	6820      	ldr	r0, [r4, #0]
-    2cec:	1809      	adds	r1, r1, r0
-    2cee:	1858      	adds	r0, r3, r1
-    2cf0:	6019      	str	r1, [r3, #0]
-    2cf2:	4282      	cmp	r2, r0
-    2cf4:	d1e0      	bne.n	2cb8 <_free_r+0x24>
-    2cf6:	6810      	ldr	r0, [r2, #0]
-    2cf8:	6852      	ldr	r2, [r2, #4]
-    2cfa:	1841      	adds	r1, r0, r1
-    2cfc:	6019      	str	r1, [r3, #0]
-    2cfe:	605a      	str	r2, [r3, #4]
-    2d00:	e7da      	b.n	2cb8 <_free_r+0x24>
-    2d02:	42a0      	cmp	r0, r4
-    2d04:	d902      	bls.n	2d0c <_free_r+0x78>
-    2d06:	230c      	movs	r3, #12
-    2d08:	602b      	str	r3, [r5, #0]
-    2d0a:	e7d5      	b.n	2cb8 <_free_r+0x24>
-    2d0c:	6821      	ldr	r1, [r4, #0]
-    2d0e:	1860      	adds	r0, r4, r1
-    2d10:	4282      	cmp	r2, r0
-    2d12:	d103      	bne.n	2d1c <_free_r+0x88>
-    2d14:	6810      	ldr	r0, [r2, #0]
-    2d16:	6852      	ldr	r2, [r2, #4]
-    2d18:	1841      	adds	r1, r0, r1
-    2d1a:	6021      	str	r1, [r4, #0]
-    2d1c:	6062      	str	r2, [r4, #4]
-    2d1e:	605c      	str	r4, [r3, #4]
-    2d20:	e7ca      	b.n	2cb8 <_free_r+0x24>
-    2d22:	46c0      	nop			; (mov r8, r8)
-    2d24:	200001d0 	.word	0x200001d0
-
-00002d28 <_malloc_r>:
-    2d28:	2303      	movs	r3, #3
-    2d2a:	b570      	push	{r4, r5, r6, lr}
-    2d2c:	1ccd      	adds	r5, r1, #3
-    2d2e:	439d      	bics	r5, r3
-    2d30:	3508      	adds	r5, #8
-    2d32:	0006      	movs	r6, r0
-    2d34:	2d0c      	cmp	r5, #12
-    2d36:	d21e      	bcs.n	2d76 <_malloc_r+0x4e>
-    2d38:	250c      	movs	r5, #12
-    2d3a:	42a9      	cmp	r1, r5
-    2d3c:	d81d      	bhi.n	2d7a <_malloc_r+0x52>
-    2d3e:	0030      	movs	r0, r6
-    2d40:	f000 fcaf 	bl	36a2 <__malloc_lock>
-    2d44:	4a25      	ldr	r2, [pc, #148]	; (2ddc <_malloc_r+0xb4>)
-    2d46:	6814      	ldr	r4, [r2, #0]
-    2d48:	0021      	movs	r1, r4
-    2d4a:	2900      	cmp	r1, #0
-    2d4c:	d119      	bne.n	2d82 <_malloc_r+0x5a>
-    2d4e:	4c24      	ldr	r4, [pc, #144]	; (2de0 <_malloc_r+0xb8>)
-    2d50:	6823      	ldr	r3, [r4, #0]
-    2d52:	2b00      	cmp	r3, #0
-    2d54:	d103      	bne.n	2d5e <_malloc_r+0x36>
-    2d56:	0030      	movs	r0, r6
-    2d58:	f000 fb10 	bl	337c <_sbrk_r>
-    2d5c:	6020      	str	r0, [r4, #0]
-    2d5e:	0029      	movs	r1, r5
-    2d60:	0030      	movs	r0, r6
-    2d62:	f000 fb0b 	bl	337c <_sbrk_r>
-    2d66:	1c43      	adds	r3, r0, #1
-    2d68:	d12c      	bne.n	2dc4 <_malloc_r+0x9c>
-    2d6a:	230c      	movs	r3, #12
-    2d6c:	0030      	movs	r0, r6
-    2d6e:	6033      	str	r3, [r6, #0]
-    2d70:	f000 fc98 	bl	36a4 <__malloc_unlock>
-    2d74:	e003      	b.n	2d7e <_malloc_r+0x56>
-    2d76:	2d00      	cmp	r5, #0
-    2d78:	dadf      	bge.n	2d3a <_malloc_r+0x12>
-    2d7a:	230c      	movs	r3, #12
-    2d7c:	6033      	str	r3, [r6, #0]
-    2d7e:	2000      	movs	r0, #0
-    2d80:	bd70      	pop	{r4, r5, r6, pc}
-    2d82:	680b      	ldr	r3, [r1, #0]
-    2d84:	1b5b      	subs	r3, r3, r5
-    2d86:	d41a      	bmi.n	2dbe <_malloc_r+0x96>
-    2d88:	2b0b      	cmp	r3, #11
-    2d8a:	d903      	bls.n	2d94 <_malloc_r+0x6c>
-    2d8c:	600b      	str	r3, [r1, #0]
-    2d8e:	18cc      	adds	r4, r1, r3
-    2d90:	6025      	str	r5, [r4, #0]
-    2d92:	e003      	b.n	2d9c <_malloc_r+0x74>
-    2d94:	428c      	cmp	r4, r1
-    2d96:	d10e      	bne.n	2db6 <_malloc_r+0x8e>
-    2d98:	6863      	ldr	r3, [r4, #4]
-    2d9a:	6013      	str	r3, [r2, #0]
-    2d9c:	0030      	movs	r0, r6
-    2d9e:	f000 fc81 	bl	36a4 <__malloc_unlock>
-    2da2:	0020      	movs	r0, r4
-    2da4:	2207      	movs	r2, #7
-    2da6:	300b      	adds	r0, #11
-    2da8:	1d23      	adds	r3, r4, #4
-    2daa:	4390      	bics	r0, r2
-    2dac:	1ac3      	subs	r3, r0, r3
-    2dae:	d0e7      	beq.n	2d80 <_malloc_r+0x58>
-    2db0:	425a      	negs	r2, r3
-    2db2:	50e2      	str	r2, [r4, r3]
-    2db4:	e7e4      	b.n	2d80 <_malloc_r+0x58>
-    2db6:	684b      	ldr	r3, [r1, #4]
-    2db8:	6063      	str	r3, [r4, #4]
-    2dba:	000c      	movs	r4, r1
-    2dbc:	e7ee      	b.n	2d9c <_malloc_r+0x74>
-    2dbe:	000c      	movs	r4, r1
-    2dc0:	6849      	ldr	r1, [r1, #4]
-    2dc2:	e7c2      	b.n	2d4a <_malloc_r+0x22>
-    2dc4:	2303      	movs	r3, #3
-    2dc6:	1cc4      	adds	r4, r0, #3
-    2dc8:	439c      	bics	r4, r3
-    2dca:	42a0      	cmp	r0, r4
-    2dcc:	d0e0      	beq.n	2d90 <_malloc_r+0x68>
-    2dce:	1a21      	subs	r1, r4, r0
-    2dd0:	0030      	movs	r0, r6
-    2dd2:	f000 fad3 	bl	337c <_sbrk_r>
-    2dd6:	1c43      	adds	r3, r0, #1
-    2dd8:	d1da      	bne.n	2d90 <_malloc_r+0x68>
-    2dda:	e7c6      	b.n	2d6a <_malloc_r+0x42>
-    2ddc:	200001d0 	.word	0x200001d0
-    2de0:	200001d4 	.word	0x200001d4
-
-00002de4 <__sfputc_r>:
-    2de4:	6893      	ldr	r3, [r2, #8]
-    2de6:	b510      	push	{r4, lr}
-    2de8:	3b01      	subs	r3, #1
-    2dea:	6093      	str	r3, [r2, #8]
-    2dec:	2b00      	cmp	r3, #0
-    2dee:	da05      	bge.n	2dfc <__sfputc_r+0x18>
-    2df0:	6994      	ldr	r4, [r2, #24]
-    2df2:	42a3      	cmp	r3, r4
-    2df4:	db08      	blt.n	2e08 <__sfputc_r+0x24>
-    2df6:	b2cb      	uxtb	r3, r1
-    2df8:	2b0a      	cmp	r3, #10
-    2dfa:	d005      	beq.n	2e08 <__sfputc_r+0x24>
-    2dfc:	6813      	ldr	r3, [r2, #0]
-    2dfe:	1c58      	adds	r0, r3, #1
-    2e00:	6010      	str	r0, [r2, #0]
-    2e02:	7019      	strb	r1, [r3, #0]
-    2e04:	b2c8      	uxtb	r0, r1
-    2e06:	bd10      	pop	{r4, pc}
-    2e08:	f000 fb16 	bl	3438 <__swbuf_r>
-    2e0c:	e7fb      	b.n	2e06 <__sfputc_r+0x22>
-
-00002e0e <__sfputs_r>:
-    2e0e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    2e10:	0006      	movs	r6, r0
-    2e12:	000f      	movs	r7, r1
-    2e14:	0014      	movs	r4, r2
-    2e16:	18d5      	adds	r5, r2, r3
-    2e18:	42ac      	cmp	r4, r5
-    2e1a:	d101      	bne.n	2e20 <__sfputs_r+0x12>
-    2e1c:	2000      	movs	r0, #0
-    2e1e:	e007      	b.n	2e30 <__sfputs_r+0x22>
-    2e20:	7821      	ldrb	r1, [r4, #0]
-    2e22:	003a      	movs	r2, r7
-    2e24:	0030      	movs	r0, r6
-    2e26:	f7ff ffdd 	bl	2de4 <__sfputc_r>
-    2e2a:	3401      	adds	r4, #1
-    2e2c:	1c43      	adds	r3, r0, #1
-    2e2e:	d1f3      	bne.n	2e18 <__sfputs_r+0xa>
-    2e30:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-	...
-
-00002e34 <_vfiprintf_r>:
-    2e34:	b5f0      	push	{r4, r5, r6, r7, lr}
-    2e36:	b09f      	sub	sp, #124	; 0x7c
-    2e38:	0006      	movs	r6, r0
-    2e3a:	000f      	movs	r7, r1
-    2e3c:	0014      	movs	r4, r2
-    2e3e:	9305      	str	r3, [sp, #20]
-    2e40:	2800      	cmp	r0, #0
-    2e42:	d004      	beq.n	2e4e <_vfiprintf_r+0x1a>
-    2e44:	6983      	ldr	r3, [r0, #24]
-    2e46:	2b00      	cmp	r3, #0
-    2e48:	d101      	bne.n	2e4e <_vfiprintf_r+0x1a>
-    2e4a:	f7ff fe17 	bl	2a7c <__sinit>
-    2e4e:	4b7f      	ldr	r3, [pc, #508]	; (304c <_vfiprintf_r+0x218>)
-    2e50:	429f      	cmp	r7, r3
-    2e52:	d15c      	bne.n	2f0e <_vfiprintf_r+0xda>
-    2e54:	6877      	ldr	r7, [r6, #4]
-    2e56:	89bb      	ldrh	r3, [r7, #12]
-    2e58:	071b      	lsls	r3, r3, #28
-    2e5a:	d562      	bpl.n	2f22 <_vfiprintf_r+0xee>
-    2e5c:	693b      	ldr	r3, [r7, #16]
-    2e5e:	2b00      	cmp	r3, #0
-    2e60:	d05f      	beq.n	2f22 <_vfiprintf_r+0xee>
-    2e62:	2300      	movs	r3, #0
-    2e64:	ad06      	add	r5, sp, #24
-    2e66:	616b      	str	r3, [r5, #20]
-    2e68:	3320      	adds	r3, #32
-    2e6a:	766b      	strb	r3, [r5, #25]
-    2e6c:	3310      	adds	r3, #16
-    2e6e:	76ab      	strb	r3, [r5, #26]
-    2e70:	9402      	str	r4, [sp, #8]
-    2e72:	9c02      	ldr	r4, [sp, #8]
-    2e74:	7823      	ldrb	r3, [r4, #0]
-    2e76:	2b00      	cmp	r3, #0
-    2e78:	d15d      	bne.n	2f36 <_vfiprintf_r+0x102>
-    2e7a:	9b02      	ldr	r3, [sp, #8]
-    2e7c:	1ae3      	subs	r3, r4, r3
-    2e7e:	9304      	str	r3, [sp, #16]
-    2e80:	d00d      	beq.n	2e9e <_vfiprintf_r+0x6a>
-    2e82:	9b04      	ldr	r3, [sp, #16]
-    2e84:	9a02      	ldr	r2, [sp, #8]
-    2e86:	0039      	movs	r1, r7
-    2e88:	0030      	movs	r0, r6
-    2e8a:	f7ff ffc0 	bl	2e0e <__sfputs_r>
-    2e8e:	1c43      	adds	r3, r0, #1
-    2e90:	d100      	bne.n	2e94 <_vfiprintf_r+0x60>
-    2e92:	e0cc      	b.n	302e <_vfiprintf_r+0x1fa>
-    2e94:	696a      	ldr	r2, [r5, #20]
-    2e96:	9b04      	ldr	r3, [sp, #16]
-    2e98:	4694      	mov	ip, r2
-    2e9a:	4463      	add	r3, ip
-    2e9c:	616b      	str	r3, [r5, #20]
-    2e9e:	7823      	ldrb	r3, [r4, #0]
-    2ea0:	2b00      	cmp	r3, #0
-    2ea2:	d100      	bne.n	2ea6 <_vfiprintf_r+0x72>
-    2ea4:	e0c3      	b.n	302e <_vfiprintf_r+0x1fa>
-    2ea6:	2201      	movs	r2, #1
-    2ea8:	2300      	movs	r3, #0
-    2eaa:	4252      	negs	r2, r2
-    2eac:	606a      	str	r2, [r5, #4]
-    2eae:	a902      	add	r1, sp, #8
-    2eb0:	3254      	adds	r2, #84	; 0x54
-    2eb2:	1852      	adds	r2, r2, r1
-    2eb4:	3401      	adds	r4, #1
-    2eb6:	602b      	str	r3, [r5, #0]
-    2eb8:	60eb      	str	r3, [r5, #12]
-    2eba:	60ab      	str	r3, [r5, #8]
-    2ebc:	7013      	strb	r3, [r2, #0]
-    2ebe:	65ab      	str	r3, [r5, #88]	; 0x58
-    2ec0:	7821      	ldrb	r1, [r4, #0]
-    2ec2:	2205      	movs	r2, #5
-    2ec4:	4862      	ldr	r0, [pc, #392]	; (3050 <_vfiprintf_r+0x21c>)
-    2ec6:	f000 fbe1 	bl	368c <memchr>
-    2eca:	1c63      	adds	r3, r4, #1
-    2ecc:	469c      	mov	ip, r3
-    2ece:	2800      	cmp	r0, #0
-    2ed0:	d135      	bne.n	2f3e <_vfiprintf_r+0x10a>
-    2ed2:	6829      	ldr	r1, [r5, #0]
-    2ed4:	06cb      	lsls	r3, r1, #27
-    2ed6:	d504      	bpl.n	2ee2 <_vfiprintf_r+0xae>
-    2ed8:	2353      	movs	r3, #83	; 0x53
-    2eda:	aa02      	add	r2, sp, #8
-    2edc:	3020      	adds	r0, #32
-    2ede:	189b      	adds	r3, r3, r2
-    2ee0:	7018      	strb	r0, [r3, #0]
-    2ee2:	070b      	lsls	r3, r1, #28
-    2ee4:	d504      	bpl.n	2ef0 <_vfiprintf_r+0xbc>
-    2ee6:	2353      	movs	r3, #83	; 0x53
-    2ee8:	202b      	movs	r0, #43	; 0x2b
-    2eea:	aa02      	add	r2, sp, #8
-    2eec:	189b      	adds	r3, r3, r2
-    2eee:	7018      	strb	r0, [r3, #0]
-    2ef0:	7823      	ldrb	r3, [r4, #0]
-    2ef2:	2b2a      	cmp	r3, #42	; 0x2a
-    2ef4:	d02c      	beq.n	2f50 <_vfiprintf_r+0x11c>
-    2ef6:	2000      	movs	r0, #0
-    2ef8:	210a      	movs	r1, #10
-    2efa:	9b09      	ldr	r3, [sp, #36]	; 0x24
-    2efc:	7822      	ldrb	r2, [r4, #0]
-    2efe:	3a30      	subs	r2, #48	; 0x30
-    2f00:	2a09      	cmp	r2, #9
-    2f02:	d800      	bhi.n	2f06 <_vfiprintf_r+0xd2>
-    2f04:	e06b      	b.n	2fde <_vfiprintf_r+0x1aa>
-    2f06:	2800      	cmp	r0, #0
-    2f08:	d02a      	beq.n	2f60 <_vfiprintf_r+0x12c>
-    2f0a:	9309      	str	r3, [sp, #36]	; 0x24
-    2f0c:	e028      	b.n	2f60 <_vfiprintf_r+0x12c>
-    2f0e:	4b51      	ldr	r3, [pc, #324]	; (3054 <_vfiprintf_r+0x220>)
-    2f10:	429f      	cmp	r7, r3
-    2f12:	d101      	bne.n	2f18 <_vfiprintf_r+0xe4>
-    2f14:	68b7      	ldr	r7, [r6, #8]
-    2f16:	e79e      	b.n	2e56 <_vfiprintf_r+0x22>
-    2f18:	4b4f      	ldr	r3, [pc, #316]	; (3058 <_vfiprintf_r+0x224>)
-    2f1a:	429f      	cmp	r7, r3
-    2f1c:	d19b      	bne.n	2e56 <_vfiprintf_r+0x22>
-    2f1e:	68f7      	ldr	r7, [r6, #12]
-    2f20:	e799      	b.n	2e56 <_vfiprintf_r+0x22>
-    2f22:	0039      	movs	r1, r7
-    2f24:	0030      	movs	r0, r6
-    2f26:	f000 faf1 	bl	350c <__swsetup_r>
-    2f2a:	2800      	cmp	r0, #0
-    2f2c:	d099      	beq.n	2e62 <_vfiprintf_r+0x2e>
-    2f2e:	2001      	movs	r0, #1
-    2f30:	4240      	negs	r0, r0
-    2f32:	b01f      	add	sp, #124	; 0x7c
-    2f34:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    2f36:	2b25      	cmp	r3, #37	; 0x25
-    2f38:	d09f      	beq.n	2e7a <_vfiprintf_r+0x46>
-    2f3a:	3401      	adds	r4, #1
-    2f3c:	e79a      	b.n	2e74 <_vfiprintf_r+0x40>
-    2f3e:	4b44      	ldr	r3, [pc, #272]	; (3050 <_vfiprintf_r+0x21c>)
-    2f40:	6829      	ldr	r1, [r5, #0]
-    2f42:	1ac0      	subs	r0, r0, r3
-    2f44:	2301      	movs	r3, #1
-    2f46:	4083      	lsls	r3, r0
-    2f48:	430b      	orrs	r3, r1
-    2f4a:	602b      	str	r3, [r5, #0]
-    2f4c:	4664      	mov	r4, ip
-    2f4e:	e7b7      	b.n	2ec0 <_vfiprintf_r+0x8c>
-    2f50:	9b05      	ldr	r3, [sp, #20]
-    2f52:	1d18      	adds	r0, r3, #4
-    2f54:	681b      	ldr	r3, [r3, #0]
-    2f56:	9005      	str	r0, [sp, #20]
-    2f58:	2b00      	cmp	r3, #0
-    2f5a:	db3a      	blt.n	2fd2 <_vfiprintf_r+0x19e>
-    2f5c:	9309      	str	r3, [sp, #36]	; 0x24
-    2f5e:	4664      	mov	r4, ip
-    2f60:	7823      	ldrb	r3, [r4, #0]
-    2f62:	2b2e      	cmp	r3, #46	; 0x2e
-    2f64:	d10b      	bne.n	2f7e <_vfiprintf_r+0x14a>
-    2f66:	7863      	ldrb	r3, [r4, #1]
-    2f68:	1c62      	adds	r2, r4, #1
-    2f6a:	2b2a      	cmp	r3, #42	; 0x2a
-    2f6c:	d13f      	bne.n	2fee <_vfiprintf_r+0x1ba>
-    2f6e:	9b05      	ldr	r3, [sp, #20]
-    2f70:	3402      	adds	r4, #2
-    2f72:	1d1a      	adds	r2, r3, #4
-    2f74:	681b      	ldr	r3, [r3, #0]
-    2f76:	9205      	str	r2, [sp, #20]
-    2f78:	2b00      	cmp	r3, #0
-    2f7a:	db35      	blt.n	2fe8 <_vfiprintf_r+0x1b4>
-    2f7c:	9307      	str	r3, [sp, #28]
-    2f7e:	7821      	ldrb	r1, [r4, #0]
-    2f80:	2203      	movs	r2, #3
-    2f82:	4836      	ldr	r0, [pc, #216]	; (305c <_vfiprintf_r+0x228>)
-    2f84:	f000 fb82 	bl	368c <memchr>
-    2f88:	2800      	cmp	r0, #0
-    2f8a:	d007      	beq.n	2f9c <_vfiprintf_r+0x168>
-    2f8c:	4b33      	ldr	r3, [pc, #204]	; (305c <_vfiprintf_r+0x228>)
-    2f8e:	682a      	ldr	r2, [r5, #0]
-    2f90:	1ac0      	subs	r0, r0, r3
-    2f92:	2340      	movs	r3, #64	; 0x40
-    2f94:	4083      	lsls	r3, r0
-    2f96:	4313      	orrs	r3, r2
-    2f98:	602b      	str	r3, [r5, #0]
-    2f9a:	3401      	adds	r4, #1
-    2f9c:	7821      	ldrb	r1, [r4, #0]
-    2f9e:	1c63      	adds	r3, r4, #1
-    2fa0:	2206      	movs	r2, #6
-    2fa2:	482f      	ldr	r0, [pc, #188]	; (3060 <_vfiprintf_r+0x22c>)
-    2fa4:	9302      	str	r3, [sp, #8]
-    2fa6:	7629      	strb	r1, [r5, #24]
-    2fa8:	f000 fb70 	bl	368c <memchr>
-    2fac:	2800      	cmp	r0, #0
-    2fae:	d044      	beq.n	303a <_vfiprintf_r+0x206>
-    2fb0:	4b2c      	ldr	r3, [pc, #176]	; (3064 <_vfiprintf_r+0x230>)
-    2fb2:	2b00      	cmp	r3, #0
-    2fb4:	d12f      	bne.n	3016 <_vfiprintf_r+0x1e2>
-    2fb6:	6829      	ldr	r1, [r5, #0]
-    2fb8:	9b05      	ldr	r3, [sp, #20]
-    2fba:	2207      	movs	r2, #7
-    2fbc:	05c9      	lsls	r1, r1, #23
-    2fbe:	d528      	bpl.n	3012 <_vfiprintf_r+0x1de>
-    2fc0:	189b      	adds	r3, r3, r2
-    2fc2:	4393      	bics	r3, r2
-    2fc4:	3308      	adds	r3, #8
-    2fc6:	9305      	str	r3, [sp, #20]
-    2fc8:	696b      	ldr	r3, [r5, #20]
-    2fca:	9a03      	ldr	r2, [sp, #12]
-    2fcc:	189b      	adds	r3, r3, r2
-    2fce:	616b      	str	r3, [r5, #20]
-    2fd0:	e74f      	b.n	2e72 <_vfiprintf_r+0x3e>
-    2fd2:	425b      	negs	r3, r3
-    2fd4:	60eb      	str	r3, [r5, #12]
-    2fd6:	2302      	movs	r3, #2
-    2fd8:	430b      	orrs	r3, r1
-    2fda:	602b      	str	r3, [r5, #0]
-    2fdc:	e7bf      	b.n	2f5e <_vfiprintf_r+0x12a>
-    2fde:	434b      	muls	r3, r1
-    2fe0:	3401      	adds	r4, #1
-    2fe2:	189b      	adds	r3, r3, r2
-    2fe4:	2001      	movs	r0, #1
-    2fe6:	e789      	b.n	2efc <_vfiprintf_r+0xc8>
-    2fe8:	2301      	movs	r3, #1
-    2fea:	425b      	negs	r3, r3
-    2fec:	e7c6      	b.n	2f7c <_vfiprintf_r+0x148>
-    2fee:	2300      	movs	r3, #0
-    2ff0:	0014      	movs	r4, r2
-    2ff2:	200a      	movs	r0, #10
-    2ff4:	001a      	movs	r2, r3
-    2ff6:	606b      	str	r3, [r5, #4]
-    2ff8:	7821      	ldrb	r1, [r4, #0]
-    2ffa:	3930      	subs	r1, #48	; 0x30
-    2ffc:	2909      	cmp	r1, #9
-    2ffe:	d903      	bls.n	3008 <_vfiprintf_r+0x1d4>
-    3000:	2b00      	cmp	r3, #0
-    3002:	d0bc      	beq.n	2f7e <_vfiprintf_r+0x14a>
-    3004:	9207      	str	r2, [sp, #28]
-    3006:	e7ba      	b.n	2f7e <_vfiprintf_r+0x14a>
-    3008:	4342      	muls	r2, r0
-    300a:	3401      	adds	r4, #1
-    300c:	1852      	adds	r2, r2, r1
-    300e:	2301      	movs	r3, #1
-    3010:	e7f2      	b.n	2ff8 <_vfiprintf_r+0x1c4>
-    3012:	3307      	adds	r3, #7
-    3014:	e7d5      	b.n	2fc2 <_vfiprintf_r+0x18e>
-    3016:	ab05      	add	r3, sp, #20
-    3018:	9300      	str	r3, [sp, #0]
-    301a:	003a      	movs	r2, r7
-    301c:	4b12      	ldr	r3, [pc, #72]	; (3068 <_vfiprintf_r+0x234>)
-    301e:	0029      	movs	r1, r5
-    3020:	0030      	movs	r0, r6
-    3022:	e000      	b.n	3026 <_vfiprintf_r+0x1f2>
-    3024:	bf00      	nop
-    3026:	9003      	str	r0, [sp, #12]
-    3028:	9b03      	ldr	r3, [sp, #12]
-    302a:	3301      	adds	r3, #1
-    302c:	d1cc      	bne.n	2fc8 <_vfiprintf_r+0x194>
-    302e:	89bb      	ldrh	r3, [r7, #12]
-    3030:	065b      	lsls	r3, r3, #25
-    3032:	d500      	bpl.n	3036 <_vfiprintf_r+0x202>
-    3034:	e77b      	b.n	2f2e <_vfiprintf_r+0xfa>
-    3036:	980b      	ldr	r0, [sp, #44]	; 0x2c
-    3038:	e77b      	b.n	2f32 <_vfiprintf_r+0xfe>
-    303a:	ab05      	add	r3, sp, #20
-    303c:	9300      	str	r3, [sp, #0]
-    303e:	003a      	movs	r2, r7
-    3040:	4b09      	ldr	r3, [pc, #36]	; (3068 <_vfiprintf_r+0x234>)
-    3042:	0029      	movs	r1, r5
-    3044:	0030      	movs	r0, r6
-    3046:	f000 f87f 	bl	3148 <_printf_i>
-    304a:	e7ec      	b.n	3026 <_vfiprintf_r+0x1f2>
-    304c:	000038cc 	.word	0x000038cc
-    3050:	0000390c 	.word	0x0000390c
-    3054:	000038ec 	.word	0x000038ec
-    3058:	000038ac 	.word	0x000038ac
-    305c:	00003912 	.word	0x00003912
-    3060:	00003916 	.word	0x00003916
-    3064:	00000000 	.word	0x00000000
-    3068:	00002e0f 	.word	0x00002e0f
-
-0000306c <_printf_common>:
-    306c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    306e:	0015      	movs	r5, r2
-    3070:	9301      	str	r3, [sp, #4]
-    3072:	688a      	ldr	r2, [r1, #8]
-    3074:	690b      	ldr	r3, [r1, #16]
-    3076:	9000      	str	r0, [sp, #0]
-    3078:	000c      	movs	r4, r1
-    307a:	4293      	cmp	r3, r2
-    307c:	da00      	bge.n	3080 <_printf_common+0x14>
-    307e:	0013      	movs	r3, r2
-    3080:	0022      	movs	r2, r4
-    3082:	602b      	str	r3, [r5, #0]
-    3084:	3243      	adds	r2, #67	; 0x43
-    3086:	7812      	ldrb	r2, [r2, #0]
-    3088:	2a00      	cmp	r2, #0
-    308a:	d001      	beq.n	3090 <_printf_common+0x24>
-    308c:	3301      	adds	r3, #1
-    308e:	602b      	str	r3, [r5, #0]
-    3090:	6823      	ldr	r3, [r4, #0]
-    3092:	069b      	lsls	r3, r3, #26
-    3094:	d502      	bpl.n	309c <_printf_common+0x30>
-    3096:	682b      	ldr	r3, [r5, #0]
-    3098:	3302      	adds	r3, #2
-    309a:	602b      	str	r3, [r5, #0]
-    309c:	2706      	movs	r7, #6
-    309e:	6823      	ldr	r3, [r4, #0]
-    30a0:	401f      	ands	r7, r3
-    30a2:	d027      	beq.n	30f4 <_printf_common+0x88>
-    30a4:	0023      	movs	r3, r4
-    30a6:	3343      	adds	r3, #67	; 0x43
-    30a8:	781b      	ldrb	r3, [r3, #0]
-    30aa:	1e5a      	subs	r2, r3, #1
-    30ac:	4193      	sbcs	r3, r2
-    30ae:	6822      	ldr	r2, [r4, #0]
-    30b0:	0692      	lsls	r2, r2, #26
-    30b2:	d430      	bmi.n	3116 <_printf_common+0xaa>
-    30b4:	0022      	movs	r2, r4
-    30b6:	9901      	ldr	r1, [sp, #4]
-    30b8:	3243      	adds	r2, #67	; 0x43
-    30ba:	9800      	ldr	r0, [sp, #0]
-    30bc:	9e08      	ldr	r6, [sp, #32]
-    30be:	47b0      	blx	r6
-    30c0:	1c43      	adds	r3, r0, #1
-    30c2:	d025      	beq.n	3110 <_printf_common+0xa4>
-    30c4:	2306      	movs	r3, #6
-    30c6:	6820      	ldr	r0, [r4, #0]
-    30c8:	682a      	ldr	r2, [r5, #0]
-    30ca:	68e1      	ldr	r1, [r4, #12]
-    30cc:	4003      	ands	r3, r0
-    30ce:	2500      	movs	r5, #0
-    30d0:	2b04      	cmp	r3, #4
-    30d2:	d103      	bne.n	30dc <_printf_common+0x70>
-    30d4:	1a8d      	subs	r5, r1, r2
-    30d6:	43eb      	mvns	r3, r5
-    30d8:	17db      	asrs	r3, r3, #31
-    30da:	401d      	ands	r5, r3
-    30dc:	68a3      	ldr	r3, [r4, #8]
-    30de:	6922      	ldr	r2, [r4, #16]
-    30e0:	4293      	cmp	r3, r2
-    30e2:	dd01      	ble.n	30e8 <_printf_common+0x7c>
-    30e4:	1a9b      	subs	r3, r3, r2
-    30e6:	18ed      	adds	r5, r5, r3
-    30e8:	2700      	movs	r7, #0
-    30ea:	42bd      	cmp	r5, r7
-    30ec:	d120      	bne.n	3130 <_printf_common+0xc4>
-    30ee:	2000      	movs	r0, #0
-    30f0:	e010      	b.n	3114 <_printf_common+0xa8>
-    30f2:	3701      	adds	r7, #1
-    30f4:	68e3      	ldr	r3, [r4, #12]
-    30f6:	682a      	ldr	r2, [r5, #0]
-    30f8:	1a9b      	subs	r3, r3, r2
-    30fa:	429f      	cmp	r7, r3
-    30fc:	dad2      	bge.n	30a4 <_printf_common+0x38>
-    30fe:	0022      	movs	r2, r4
-    3100:	2301      	movs	r3, #1
-    3102:	3219      	adds	r2, #25
-    3104:	9901      	ldr	r1, [sp, #4]
-    3106:	9800      	ldr	r0, [sp, #0]
-    3108:	9e08      	ldr	r6, [sp, #32]
-    310a:	47b0      	blx	r6
-    310c:	1c43      	adds	r3, r0, #1
-    310e:	d1f0      	bne.n	30f2 <_printf_common+0x86>
-    3110:	2001      	movs	r0, #1
-    3112:	4240      	negs	r0, r0
-    3114:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    3116:	2030      	movs	r0, #48	; 0x30
-    3118:	18e1      	adds	r1, r4, r3
-    311a:	3143      	adds	r1, #67	; 0x43
-    311c:	7008      	strb	r0, [r1, #0]
-    311e:	0021      	movs	r1, r4
-    3120:	1c5a      	adds	r2, r3, #1
-    3122:	3145      	adds	r1, #69	; 0x45
-    3124:	7809      	ldrb	r1, [r1, #0]
-    3126:	18a2      	adds	r2, r4, r2
-    3128:	3243      	adds	r2, #67	; 0x43
-    312a:	3302      	adds	r3, #2
-    312c:	7011      	strb	r1, [r2, #0]
-    312e:	e7c1      	b.n	30b4 <_printf_common+0x48>
-    3130:	0022      	movs	r2, r4
-    3132:	2301      	movs	r3, #1
-    3134:	321a      	adds	r2, #26
-    3136:	9901      	ldr	r1, [sp, #4]
-    3138:	9800      	ldr	r0, [sp, #0]
-    313a:	9e08      	ldr	r6, [sp, #32]
-    313c:	47b0      	blx	r6
-    313e:	1c43      	adds	r3, r0, #1
-    3140:	d0e6      	beq.n	3110 <_printf_common+0xa4>
-    3142:	3701      	adds	r7, #1
-    3144:	e7d1      	b.n	30ea <_printf_common+0x7e>
-	...
-
-00003148 <_printf_i>:
-    3148:	b5f0      	push	{r4, r5, r6, r7, lr}
-    314a:	b08b      	sub	sp, #44	; 0x2c
-    314c:	9206      	str	r2, [sp, #24]
-    314e:	000a      	movs	r2, r1
-    3150:	3243      	adds	r2, #67	; 0x43
-    3152:	9307      	str	r3, [sp, #28]
-    3154:	9005      	str	r0, [sp, #20]
-    3156:	9204      	str	r2, [sp, #16]
-    3158:	7e0a      	ldrb	r2, [r1, #24]
-    315a:	000c      	movs	r4, r1
-    315c:	9b10      	ldr	r3, [sp, #64]	; 0x40
-    315e:	2a6e      	cmp	r2, #110	; 0x6e
-    3160:	d100      	bne.n	3164 <_printf_i+0x1c>
-    3162:	e08f      	b.n	3284 <_printf_i+0x13c>
-    3164:	d817      	bhi.n	3196 <_printf_i+0x4e>
-    3166:	2a63      	cmp	r2, #99	; 0x63
-    3168:	d02c      	beq.n	31c4 <_printf_i+0x7c>
-    316a:	d808      	bhi.n	317e <_printf_i+0x36>
-    316c:	2a00      	cmp	r2, #0
-    316e:	d100      	bne.n	3172 <_printf_i+0x2a>
-    3170:	e099      	b.n	32a6 <_printf_i+0x15e>
-    3172:	2a58      	cmp	r2, #88	; 0x58
-    3174:	d054      	beq.n	3220 <_printf_i+0xd8>
-    3176:	0026      	movs	r6, r4
-    3178:	3642      	adds	r6, #66	; 0x42
-    317a:	7032      	strb	r2, [r6, #0]
-    317c:	e029      	b.n	31d2 <_printf_i+0x8a>
-    317e:	2a64      	cmp	r2, #100	; 0x64
-    3180:	d001      	beq.n	3186 <_printf_i+0x3e>
-    3182:	2a69      	cmp	r2, #105	; 0x69
-    3184:	d1f7      	bne.n	3176 <_printf_i+0x2e>
-    3186:	6821      	ldr	r1, [r4, #0]
-    3188:	681a      	ldr	r2, [r3, #0]
-    318a:	0608      	lsls	r0, r1, #24
-    318c:	d523      	bpl.n	31d6 <_printf_i+0x8e>
-    318e:	1d11      	adds	r1, r2, #4
-    3190:	6019      	str	r1, [r3, #0]
-    3192:	6815      	ldr	r5, [r2, #0]
-    3194:	e025      	b.n	31e2 <_printf_i+0x9a>
-    3196:	2a73      	cmp	r2, #115	; 0x73
-    3198:	d100      	bne.n	319c <_printf_i+0x54>
-    319a:	e088      	b.n	32ae <_printf_i+0x166>
-    319c:	d808      	bhi.n	31b0 <_printf_i+0x68>
-    319e:	2a6f      	cmp	r2, #111	; 0x6f
-    31a0:	d029      	beq.n	31f6 <_printf_i+0xae>
-    31a2:	2a70      	cmp	r2, #112	; 0x70
-    31a4:	d1e7      	bne.n	3176 <_printf_i+0x2e>
-    31a6:	2220      	movs	r2, #32
-    31a8:	6809      	ldr	r1, [r1, #0]
-    31aa:	430a      	orrs	r2, r1
-    31ac:	6022      	str	r2, [r4, #0]
-    31ae:	e003      	b.n	31b8 <_printf_i+0x70>
-    31b0:	2a75      	cmp	r2, #117	; 0x75
-    31b2:	d020      	beq.n	31f6 <_printf_i+0xae>
-    31b4:	2a78      	cmp	r2, #120	; 0x78
-    31b6:	d1de      	bne.n	3176 <_printf_i+0x2e>
-    31b8:	0022      	movs	r2, r4
-    31ba:	2178      	movs	r1, #120	; 0x78
-    31bc:	3245      	adds	r2, #69	; 0x45
-    31be:	7011      	strb	r1, [r2, #0]
-    31c0:	4a6c      	ldr	r2, [pc, #432]	; (3374 <_printf_i+0x22c>)
-    31c2:	e030      	b.n	3226 <_printf_i+0xde>
-    31c4:	000e      	movs	r6, r1
-    31c6:	681a      	ldr	r2, [r3, #0]
-    31c8:	3642      	adds	r6, #66	; 0x42
-    31ca:	1d11      	adds	r1, r2, #4
-    31cc:	6019      	str	r1, [r3, #0]
-    31ce:	6813      	ldr	r3, [r2, #0]
-    31d0:	7033      	strb	r3, [r6, #0]
-    31d2:	2301      	movs	r3, #1
-    31d4:	e079      	b.n	32ca <_printf_i+0x182>
-    31d6:	0649      	lsls	r1, r1, #25
-    31d8:	d5d9      	bpl.n	318e <_printf_i+0x46>
-    31da:	1d11      	adds	r1, r2, #4
-    31dc:	6019      	str	r1, [r3, #0]
-    31de:	2300      	movs	r3, #0
-    31e0:	5ed5      	ldrsh	r5, [r2, r3]
-    31e2:	2d00      	cmp	r5, #0
-    31e4:	da03      	bge.n	31ee <_printf_i+0xa6>
-    31e6:	232d      	movs	r3, #45	; 0x2d
-    31e8:	9a04      	ldr	r2, [sp, #16]
-    31ea:	426d      	negs	r5, r5
-    31ec:	7013      	strb	r3, [r2, #0]
-    31ee:	4b62      	ldr	r3, [pc, #392]	; (3378 <_printf_i+0x230>)
-    31f0:	270a      	movs	r7, #10
-    31f2:	9303      	str	r3, [sp, #12]
-    31f4:	e02f      	b.n	3256 <_printf_i+0x10e>
-    31f6:	6820      	ldr	r0, [r4, #0]
-    31f8:	6819      	ldr	r1, [r3, #0]
-    31fa:	0605      	lsls	r5, r0, #24
-    31fc:	d503      	bpl.n	3206 <_printf_i+0xbe>
-    31fe:	1d08      	adds	r0, r1, #4
-    3200:	6018      	str	r0, [r3, #0]
-    3202:	680d      	ldr	r5, [r1, #0]
-    3204:	e005      	b.n	3212 <_printf_i+0xca>
-    3206:	0640      	lsls	r0, r0, #25
-    3208:	d5f9      	bpl.n	31fe <_printf_i+0xb6>
-    320a:	680d      	ldr	r5, [r1, #0]
-    320c:	1d08      	adds	r0, r1, #4
-    320e:	6018      	str	r0, [r3, #0]
-    3210:	b2ad      	uxth	r5, r5
-    3212:	4b59      	ldr	r3, [pc, #356]	; (3378 <_printf_i+0x230>)
-    3214:	2708      	movs	r7, #8
-    3216:	9303      	str	r3, [sp, #12]
-    3218:	2a6f      	cmp	r2, #111	; 0x6f
-    321a:	d018      	beq.n	324e <_printf_i+0x106>
-    321c:	270a      	movs	r7, #10
-    321e:	e016      	b.n	324e <_printf_i+0x106>
-    3220:	3145      	adds	r1, #69	; 0x45
-    3222:	700a      	strb	r2, [r1, #0]
-    3224:	4a54      	ldr	r2, [pc, #336]	; (3378 <_printf_i+0x230>)
-    3226:	9203      	str	r2, [sp, #12]
-    3228:	681a      	ldr	r2, [r3, #0]
-    322a:	6821      	ldr	r1, [r4, #0]
-    322c:	1d10      	adds	r0, r2, #4
-    322e:	6018      	str	r0, [r3, #0]
-    3230:	6815      	ldr	r5, [r2, #0]
-    3232:	0608      	lsls	r0, r1, #24
-    3234:	d522      	bpl.n	327c <_printf_i+0x134>
-    3236:	07cb      	lsls	r3, r1, #31
-    3238:	d502      	bpl.n	3240 <_printf_i+0xf8>
-    323a:	2320      	movs	r3, #32
-    323c:	4319      	orrs	r1, r3
-    323e:	6021      	str	r1, [r4, #0]
-    3240:	2710      	movs	r7, #16
-    3242:	2d00      	cmp	r5, #0
-    3244:	d103      	bne.n	324e <_printf_i+0x106>
-    3246:	2320      	movs	r3, #32
-    3248:	6822      	ldr	r2, [r4, #0]
-    324a:	439a      	bics	r2, r3
-    324c:	6022      	str	r2, [r4, #0]
-    324e:	0023      	movs	r3, r4
-    3250:	2200      	movs	r2, #0
-    3252:	3343      	adds	r3, #67	; 0x43
-    3254:	701a      	strb	r2, [r3, #0]
-    3256:	6863      	ldr	r3, [r4, #4]
-    3258:	60a3      	str	r3, [r4, #8]
-    325a:	2b00      	cmp	r3, #0
-    325c:	db5c      	blt.n	3318 <_printf_i+0x1d0>
-    325e:	2204      	movs	r2, #4
-    3260:	6821      	ldr	r1, [r4, #0]
-    3262:	4391      	bics	r1, r2
-    3264:	6021      	str	r1, [r4, #0]
-    3266:	2d00      	cmp	r5, #0
-    3268:	d158      	bne.n	331c <_printf_i+0x1d4>
-    326a:	9e04      	ldr	r6, [sp, #16]
-    326c:	2b00      	cmp	r3, #0
-    326e:	d064      	beq.n	333a <_printf_i+0x1f2>
-    3270:	0026      	movs	r6, r4
-    3272:	9b03      	ldr	r3, [sp, #12]
-    3274:	3642      	adds	r6, #66	; 0x42
-    3276:	781b      	ldrb	r3, [r3, #0]
-    3278:	7033      	strb	r3, [r6, #0]
-    327a:	e05e      	b.n	333a <_printf_i+0x1f2>
-    327c:	0648      	lsls	r0, r1, #25
-    327e:	d5da      	bpl.n	3236 <_printf_i+0xee>
-    3280:	b2ad      	uxth	r5, r5
-    3282:	e7d8      	b.n	3236 <_printf_i+0xee>
-    3284:	6809      	ldr	r1, [r1, #0]
-    3286:	681a      	ldr	r2, [r3, #0]
-    3288:	0608      	lsls	r0, r1, #24
-    328a:	d505      	bpl.n	3298 <_printf_i+0x150>
-    328c:	1d11      	adds	r1, r2, #4
-    328e:	6019      	str	r1, [r3, #0]
-    3290:	6813      	ldr	r3, [r2, #0]
-    3292:	6962      	ldr	r2, [r4, #20]
-    3294:	601a      	str	r2, [r3, #0]
-    3296:	e006      	b.n	32a6 <_printf_i+0x15e>
-    3298:	0649      	lsls	r1, r1, #25
-    329a:	d5f7      	bpl.n	328c <_printf_i+0x144>
-    329c:	1d11      	adds	r1, r2, #4
-    329e:	6019      	str	r1, [r3, #0]
-    32a0:	6813      	ldr	r3, [r2, #0]
-    32a2:	8aa2      	ldrh	r2, [r4, #20]
-    32a4:	801a      	strh	r2, [r3, #0]
-    32a6:	2300      	movs	r3, #0
-    32a8:	9e04      	ldr	r6, [sp, #16]
-    32aa:	6123      	str	r3, [r4, #16]
-    32ac:	e054      	b.n	3358 <_printf_i+0x210>
-    32ae:	681a      	ldr	r2, [r3, #0]
-    32b0:	1d11      	adds	r1, r2, #4
-    32b2:	6019      	str	r1, [r3, #0]
-    32b4:	6816      	ldr	r6, [r2, #0]
-    32b6:	2100      	movs	r1, #0
-    32b8:	6862      	ldr	r2, [r4, #4]
-    32ba:	0030      	movs	r0, r6
-    32bc:	f000 f9e6 	bl	368c <memchr>
-    32c0:	2800      	cmp	r0, #0
-    32c2:	d001      	beq.n	32c8 <_printf_i+0x180>
-    32c4:	1b80      	subs	r0, r0, r6
-    32c6:	6060      	str	r0, [r4, #4]
-    32c8:	6863      	ldr	r3, [r4, #4]
-    32ca:	6123      	str	r3, [r4, #16]
-    32cc:	2300      	movs	r3, #0
-    32ce:	9a04      	ldr	r2, [sp, #16]
-    32d0:	7013      	strb	r3, [r2, #0]
-    32d2:	e041      	b.n	3358 <_printf_i+0x210>
-    32d4:	6923      	ldr	r3, [r4, #16]
-    32d6:	0032      	movs	r2, r6
-    32d8:	9906      	ldr	r1, [sp, #24]
-    32da:	9805      	ldr	r0, [sp, #20]
-    32dc:	9d07      	ldr	r5, [sp, #28]
-    32de:	47a8      	blx	r5
-    32e0:	1c43      	adds	r3, r0, #1
-    32e2:	d043      	beq.n	336c <_printf_i+0x224>
-    32e4:	6823      	ldr	r3, [r4, #0]
-    32e6:	2500      	movs	r5, #0
-    32e8:	079b      	lsls	r3, r3, #30
-    32ea:	d40f      	bmi.n	330c <_printf_i+0x1c4>
-    32ec:	9b09      	ldr	r3, [sp, #36]	; 0x24
-    32ee:	68e0      	ldr	r0, [r4, #12]
-    32f0:	4298      	cmp	r0, r3
-    32f2:	da3d      	bge.n	3370 <_printf_i+0x228>
-    32f4:	0018      	movs	r0, r3
-    32f6:	e03b      	b.n	3370 <_printf_i+0x228>
-    32f8:	0022      	movs	r2, r4
-    32fa:	2301      	movs	r3, #1
-    32fc:	3219      	adds	r2, #25
-    32fe:	9906      	ldr	r1, [sp, #24]
-    3300:	9805      	ldr	r0, [sp, #20]
-    3302:	9e07      	ldr	r6, [sp, #28]
-    3304:	47b0      	blx	r6
-    3306:	1c43      	adds	r3, r0, #1
-    3308:	d030      	beq.n	336c <_printf_i+0x224>
-    330a:	3501      	adds	r5, #1
-    330c:	68e3      	ldr	r3, [r4, #12]
-    330e:	9a09      	ldr	r2, [sp, #36]	; 0x24
-    3310:	1a9b      	subs	r3, r3, r2
-    3312:	429d      	cmp	r5, r3
-    3314:	dbf0      	blt.n	32f8 <_printf_i+0x1b0>
-    3316:	e7e9      	b.n	32ec <_printf_i+0x1a4>
-    3318:	2d00      	cmp	r5, #0
-    331a:	d0a9      	beq.n	3270 <_printf_i+0x128>
-    331c:	9e04      	ldr	r6, [sp, #16]
-    331e:	0028      	movs	r0, r5
-    3320:	0039      	movs	r1, r7
-    3322:	f7fe fded 	bl	1f00 <__aeabi_uidivmod>
-    3326:	9b03      	ldr	r3, [sp, #12]
-    3328:	3e01      	subs	r6, #1
-    332a:	5c5b      	ldrb	r3, [r3, r1]
-    332c:	0028      	movs	r0, r5
-    332e:	7033      	strb	r3, [r6, #0]
-    3330:	0039      	movs	r1, r7
-    3332:	f7fe fd5f 	bl	1df4 <__udivsi3>
-    3336:	1e05      	subs	r5, r0, #0
-    3338:	d1f1      	bne.n	331e <_printf_i+0x1d6>
-    333a:	2f08      	cmp	r7, #8
-    333c:	d109      	bne.n	3352 <_printf_i+0x20a>
-    333e:	6823      	ldr	r3, [r4, #0]
-    3340:	07db      	lsls	r3, r3, #31
-    3342:	d506      	bpl.n	3352 <_printf_i+0x20a>
-    3344:	6863      	ldr	r3, [r4, #4]
-    3346:	6922      	ldr	r2, [r4, #16]
-    3348:	4293      	cmp	r3, r2
-    334a:	dc02      	bgt.n	3352 <_printf_i+0x20a>
-    334c:	2330      	movs	r3, #48	; 0x30
-    334e:	3e01      	subs	r6, #1
-    3350:	7033      	strb	r3, [r6, #0]
-    3352:	9b04      	ldr	r3, [sp, #16]
-    3354:	1b9b      	subs	r3, r3, r6
-    3356:	6123      	str	r3, [r4, #16]
-    3358:	9b07      	ldr	r3, [sp, #28]
-    335a:	aa09      	add	r2, sp, #36	; 0x24
-    335c:	9300      	str	r3, [sp, #0]
-    335e:	0021      	movs	r1, r4
-    3360:	9b06      	ldr	r3, [sp, #24]
-    3362:	9805      	ldr	r0, [sp, #20]
-    3364:	f7ff fe82 	bl	306c <_printf_common>
-    3368:	1c43      	adds	r3, r0, #1
-    336a:	d1b3      	bne.n	32d4 <_printf_i+0x18c>
-    336c:	2001      	movs	r0, #1
-    336e:	4240      	negs	r0, r0
-    3370:	b00b      	add	sp, #44	; 0x2c
-    3372:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    3374:	0000392e 	.word	0x0000392e
-    3378:	0000391d 	.word	0x0000391d
-
-0000337c <_sbrk_r>:
-    337c:	2300      	movs	r3, #0
-    337e:	b570      	push	{r4, r5, r6, lr}
-    3380:	4c06      	ldr	r4, [pc, #24]	; (339c <_sbrk_r+0x20>)
-    3382:	0005      	movs	r5, r0
-    3384:	0008      	movs	r0, r1
-    3386:	6023      	str	r3, [r4, #0]
-    3388:	f7fe fcd4 	bl	1d34 <_sbrk>
-    338c:	1c43      	adds	r3, r0, #1
-    338e:	d103      	bne.n	3398 <_sbrk_r+0x1c>
-    3390:	6823      	ldr	r3, [r4, #0]
-    3392:	2b00      	cmp	r3, #0
-    3394:	d000      	beq.n	3398 <_sbrk_r+0x1c>
-    3396:	602b      	str	r3, [r5, #0]
-    3398:	bd70      	pop	{r4, r5, r6, pc}
-    339a:	46c0      	nop			; (mov r8, r8)
-    339c:	2000029c 	.word	0x2000029c
-
-000033a0 <__sread>:
-    33a0:	b570      	push	{r4, r5, r6, lr}
-    33a2:	000c      	movs	r4, r1
-    33a4:	250e      	movs	r5, #14
-    33a6:	5f49      	ldrsh	r1, [r1, r5]
-    33a8:	f000 f97e 	bl	36a8 <_read_r>
-    33ac:	2800      	cmp	r0, #0
-    33ae:	db03      	blt.n	33b8 <__sread+0x18>
-    33b0:	6d63      	ldr	r3, [r4, #84]	; 0x54
-    33b2:	181b      	adds	r3, r3, r0
-    33b4:	6563      	str	r3, [r4, #84]	; 0x54
-    33b6:	bd70      	pop	{r4, r5, r6, pc}
-    33b8:	89a3      	ldrh	r3, [r4, #12]
-    33ba:	4a02      	ldr	r2, [pc, #8]	; (33c4 <__sread+0x24>)
-    33bc:	4013      	ands	r3, r2
-    33be:	81a3      	strh	r3, [r4, #12]
-    33c0:	e7f9      	b.n	33b6 <__sread+0x16>
-    33c2:	46c0      	nop			; (mov r8, r8)
-    33c4:	ffffefff 	.word	0xffffefff
-
-000033c8 <__swrite>:
-    33c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    33ca:	001f      	movs	r7, r3
-    33cc:	898b      	ldrh	r3, [r1, #12]
-    33ce:	0005      	movs	r5, r0
-    33d0:	000c      	movs	r4, r1
-    33d2:	0016      	movs	r6, r2
-    33d4:	05db      	lsls	r3, r3, #23
-    33d6:	d505      	bpl.n	33e4 <__swrite+0x1c>
-    33d8:	230e      	movs	r3, #14
-    33da:	5ec9      	ldrsh	r1, [r1, r3]
-    33dc:	2200      	movs	r2, #0
-    33de:	2302      	movs	r3, #2
-    33e0:	f000 f940 	bl	3664 <_lseek_r>
-    33e4:	89a3      	ldrh	r3, [r4, #12]
-    33e6:	4a05      	ldr	r2, [pc, #20]	; (33fc <__swrite+0x34>)
-    33e8:	0028      	movs	r0, r5
-    33ea:	4013      	ands	r3, r2
-    33ec:	81a3      	strh	r3, [r4, #12]
-    33ee:	0032      	movs	r2, r6
-    33f0:	230e      	movs	r3, #14
-    33f2:	5ee1      	ldrsh	r1, [r4, r3]
-    33f4:	003b      	movs	r3, r7
-    33f6:	f000 f875 	bl	34e4 <_write_r>
-    33fa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    33fc:	ffffefff 	.word	0xffffefff
-
-00003400 <__sseek>:
-    3400:	b570      	push	{r4, r5, r6, lr}
-    3402:	000c      	movs	r4, r1
-    3404:	250e      	movs	r5, #14
-    3406:	5f49      	ldrsh	r1, [r1, r5]
-    3408:	f000 f92c 	bl	3664 <_lseek_r>
-    340c:	89a3      	ldrh	r3, [r4, #12]
-    340e:	1c42      	adds	r2, r0, #1
-    3410:	d103      	bne.n	341a <__sseek+0x1a>
-    3412:	4a05      	ldr	r2, [pc, #20]	; (3428 <__sseek+0x28>)
-    3414:	4013      	ands	r3, r2
-    3416:	81a3      	strh	r3, [r4, #12]
-    3418:	bd70      	pop	{r4, r5, r6, pc}
-    341a:	2280      	movs	r2, #128	; 0x80
-    341c:	0152      	lsls	r2, r2, #5
-    341e:	4313      	orrs	r3, r2
-    3420:	81a3      	strh	r3, [r4, #12]
-    3422:	6560      	str	r0, [r4, #84]	; 0x54
-    3424:	e7f8      	b.n	3418 <__sseek+0x18>
-    3426:	46c0      	nop			; (mov r8, r8)
-    3428:	ffffefff 	.word	0xffffefff
-
-0000342c <__sclose>:
-    342c:	b510      	push	{r4, lr}
-    342e:	230e      	movs	r3, #14
-    3430:	5ec9      	ldrsh	r1, [r1, r3]
-    3432:	f000 f8e1 	bl	35f8 <_close_r>
-    3436:	bd10      	pop	{r4, pc}
-
-00003438 <__swbuf_r>:
-    3438:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    343a:	0005      	movs	r5, r0
-    343c:	000e      	movs	r6, r1
-    343e:	0014      	movs	r4, r2
-    3440:	2800      	cmp	r0, #0
-    3442:	d004      	beq.n	344e <__swbuf_r+0x16>
-    3444:	6983      	ldr	r3, [r0, #24]
-    3446:	2b00      	cmp	r3, #0
-    3448:	d101      	bne.n	344e <__swbuf_r+0x16>
-    344a:	f7ff fb17 	bl	2a7c <__sinit>
-    344e:	4b22      	ldr	r3, [pc, #136]	; (34d8 <__swbuf_r+0xa0>)
-    3450:	429c      	cmp	r4, r3
-    3452:	d12d      	bne.n	34b0 <__swbuf_r+0x78>
-    3454:	686c      	ldr	r4, [r5, #4]
-    3456:	69a3      	ldr	r3, [r4, #24]
-    3458:	60a3      	str	r3, [r4, #8]
-    345a:	89a3      	ldrh	r3, [r4, #12]
-    345c:	071b      	lsls	r3, r3, #28
-    345e:	d531      	bpl.n	34c4 <__swbuf_r+0x8c>
-    3460:	6923      	ldr	r3, [r4, #16]
-    3462:	2b00      	cmp	r3, #0
-    3464:	d02e      	beq.n	34c4 <__swbuf_r+0x8c>
-    3466:	6823      	ldr	r3, [r4, #0]
-    3468:	6922      	ldr	r2, [r4, #16]
-    346a:	b2f7      	uxtb	r7, r6
-    346c:	1a98      	subs	r0, r3, r2
-    346e:	6963      	ldr	r3, [r4, #20]
-    3470:	b2f6      	uxtb	r6, r6
-    3472:	4298      	cmp	r0, r3
-    3474:	db05      	blt.n	3482 <__swbuf_r+0x4a>
-    3476:	0021      	movs	r1, r4
-    3478:	0028      	movs	r0, r5
-    347a:	f7ff fa91 	bl	29a0 <_fflush_r>
-    347e:	2800      	cmp	r0, #0
-    3480:	d126      	bne.n	34d0 <__swbuf_r+0x98>
-    3482:	68a3      	ldr	r3, [r4, #8]
-    3484:	3001      	adds	r0, #1
-    3486:	3b01      	subs	r3, #1
-    3488:	60a3      	str	r3, [r4, #8]
-    348a:	6823      	ldr	r3, [r4, #0]
-    348c:	1c5a      	adds	r2, r3, #1
-    348e:	6022      	str	r2, [r4, #0]
-    3490:	701f      	strb	r7, [r3, #0]
-    3492:	6963      	ldr	r3, [r4, #20]
-    3494:	4298      	cmp	r0, r3
-    3496:	d004      	beq.n	34a2 <__swbuf_r+0x6a>
-    3498:	89a3      	ldrh	r3, [r4, #12]
-    349a:	07db      	lsls	r3, r3, #31
-    349c:	d51a      	bpl.n	34d4 <__swbuf_r+0x9c>
-    349e:	2e0a      	cmp	r6, #10
-    34a0:	d118      	bne.n	34d4 <__swbuf_r+0x9c>
-    34a2:	0021      	movs	r1, r4
-    34a4:	0028      	movs	r0, r5
-    34a6:	f7ff fa7b 	bl	29a0 <_fflush_r>
-    34aa:	2800      	cmp	r0, #0
-    34ac:	d012      	beq.n	34d4 <__swbuf_r+0x9c>
-    34ae:	e00f      	b.n	34d0 <__swbuf_r+0x98>
-    34b0:	4b0a      	ldr	r3, [pc, #40]	; (34dc <__swbuf_r+0xa4>)
-    34b2:	429c      	cmp	r4, r3
-    34b4:	d101      	bne.n	34ba <__swbuf_r+0x82>
-    34b6:	68ac      	ldr	r4, [r5, #8]
-    34b8:	e7cd      	b.n	3456 <__swbuf_r+0x1e>
-    34ba:	4b09      	ldr	r3, [pc, #36]	; (34e0 <__swbuf_r+0xa8>)
-    34bc:	429c      	cmp	r4, r3
-    34be:	d1ca      	bne.n	3456 <__swbuf_r+0x1e>
-    34c0:	68ec      	ldr	r4, [r5, #12]
-    34c2:	e7c8      	b.n	3456 <__swbuf_r+0x1e>
-    34c4:	0021      	movs	r1, r4
-    34c6:	0028      	movs	r0, r5
-    34c8:	f000 f820 	bl	350c <__swsetup_r>
-    34cc:	2800      	cmp	r0, #0
-    34ce:	d0ca      	beq.n	3466 <__swbuf_r+0x2e>
-    34d0:	2601      	movs	r6, #1
-    34d2:	4276      	negs	r6, r6
-    34d4:	0030      	movs	r0, r6
-    34d6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    34d8:	000038cc 	.word	0x000038cc
-    34dc:	000038ec 	.word	0x000038ec
-    34e0:	000038ac 	.word	0x000038ac
-
-000034e4 <_write_r>:
-    34e4:	b570      	push	{r4, r5, r6, lr}
-    34e6:	0005      	movs	r5, r0
-    34e8:	0008      	movs	r0, r1
-    34ea:	0011      	movs	r1, r2
-    34ec:	2200      	movs	r2, #0
-    34ee:	4c06      	ldr	r4, [pc, #24]	; (3508 <_write_r+0x24>)
-    34f0:	6022      	str	r2, [r4, #0]
-    34f2:	001a      	movs	r2, r3
-    34f4:	f7fd fbb8 	bl	c68 <_write>
-    34f8:	1c43      	adds	r3, r0, #1
-    34fa:	d103      	bne.n	3504 <_write_r+0x20>
-    34fc:	6823      	ldr	r3, [r4, #0]
-    34fe:	2b00      	cmp	r3, #0
-    3500:	d000      	beq.n	3504 <_write_r+0x20>
-    3502:	602b      	str	r3, [r5, #0]
-    3504:	bd70      	pop	{r4, r5, r6, pc}
-    3506:	46c0      	nop			; (mov r8, r8)
-    3508:	2000029c 	.word	0x2000029c
-
-0000350c <__swsetup_r>:
-    350c:	4b36      	ldr	r3, [pc, #216]	; (35e8 <__swsetup_r+0xdc>)
-    350e:	b570      	push	{r4, r5, r6, lr}
-    3510:	681d      	ldr	r5, [r3, #0]
-    3512:	0006      	movs	r6, r0
-    3514:	000c      	movs	r4, r1
-    3516:	2d00      	cmp	r5, #0
-    3518:	d005      	beq.n	3526 <__swsetup_r+0x1a>
-    351a:	69ab      	ldr	r3, [r5, #24]
-    351c:	2b00      	cmp	r3, #0
-    351e:	d102      	bne.n	3526 <__swsetup_r+0x1a>
-    3520:	0028      	movs	r0, r5
-    3522:	f7ff faab 	bl	2a7c <__sinit>
-    3526:	4b31      	ldr	r3, [pc, #196]	; (35ec <__swsetup_r+0xe0>)
-    3528:	429c      	cmp	r4, r3
-    352a:	d10f      	bne.n	354c <__swsetup_r+0x40>
-    352c:	686c      	ldr	r4, [r5, #4]
-    352e:	230c      	movs	r3, #12
-    3530:	5ee2      	ldrsh	r2, [r4, r3]
-    3532:	b293      	uxth	r3, r2
-    3534:	0719      	lsls	r1, r3, #28
-    3536:	d42d      	bmi.n	3594 <__swsetup_r+0x88>
-    3538:	06d9      	lsls	r1, r3, #27
-    353a:	d411      	bmi.n	3560 <__swsetup_r+0x54>
-    353c:	2309      	movs	r3, #9
-    353e:	2001      	movs	r0, #1
-    3540:	6033      	str	r3, [r6, #0]
-    3542:	3337      	adds	r3, #55	; 0x37
-    3544:	4313      	orrs	r3, r2
-    3546:	81a3      	strh	r3, [r4, #12]
-    3548:	4240      	negs	r0, r0
-    354a:	bd70      	pop	{r4, r5, r6, pc}
-    354c:	4b28      	ldr	r3, [pc, #160]	; (35f0 <__swsetup_r+0xe4>)
-    354e:	429c      	cmp	r4, r3
-    3550:	d101      	bne.n	3556 <__swsetup_r+0x4a>
-    3552:	68ac      	ldr	r4, [r5, #8]
-    3554:	e7eb      	b.n	352e <__swsetup_r+0x22>
-    3556:	4b27      	ldr	r3, [pc, #156]	; (35f4 <__swsetup_r+0xe8>)
-    3558:	429c      	cmp	r4, r3
-    355a:	d1e8      	bne.n	352e <__swsetup_r+0x22>
-    355c:	68ec      	ldr	r4, [r5, #12]
-    355e:	e7e6      	b.n	352e <__swsetup_r+0x22>
-    3560:	075b      	lsls	r3, r3, #29
-    3562:	d513      	bpl.n	358c <__swsetup_r+0x80>
-    3564:	6b61      	ldr	r1, [r4, #52]	; 0x34
-    3566:	2900      	cmp	r1, #0
-    3568:	d008      	beq.n	357c <__swsetup_r+0x70>
-    356a:	0023      	movs	r3, r4
-    356c:	3344      	adds	r3, #68	; 0x44
-    356e:	4299      	cmp	r1, r3
-    3570:	d002      	beq.n	3578 <__swsetup_r+0x6c>
-    3572:	0030      	movs	r0, r6
-    3574:	f7ff fb8e 	bl	2c94 <_free_r>
-    3578:	2300      	movs	r3, #0
-    357a:	6363      	str	r3, [r4, #52]	; 0x34
-    357c:	2224      	movs	r2, #36	; 0x24
-    357e:	89a3      	ldrh	r3, [r4, #12]
-    3580:	4393      	bics	r3, r2
-    3582:	81a3      	strh	r3, [r4, #12]
-    3584:	2300      	movs	r3, #0
-    3586:	6063      	str	r3, [r4, #4]
-    3588:	6923      	ldr	r3, [r4, #16]
-    358a:	6023      	str	r3, [r4, #0]
-    358c:	2308      	movs	r3, #8
-    358e:	89a2      	ldrh	r2, [r4, #12]
-    3590:	4313      	orrs	r3, r2
-    3592:	81a3      	strh	r3, [r4, #12]
-    3594:	6923      	ldr	r3, [r4, #16]
-    3596:	2b00      	cmp	r3, #0
-    3598:	d10b      	bne.n	35b2 <__swsetup_r+0xa6>
-    359a:	21a0      	movs	r1, #160	; 0xa0
-    359c:	2280      	movs	r2, #128	; 0x80
-    359e:	89a3      	ldrh	r3, [r4, #12]
-    35a0:	0089      	lsls	r1, r1, #2
-    35a2:	0092      	lsls	r2, r2, #2
-    35a4:	400b      	ands	r3, r1
-    35a6:	4293      	cmp	r3, r2
-    35a8:	d003      	beq.n	35b2 <__swsetup_r+0xa6>
-    35aa:	0021      	movs	r1, r4
-    35ac:	0030      	movs	r0, r6
-    35ae:	f7ff fb23 	bl	2bf8 <__smakebuf_r>
-    35b2:	2301      	movs	r3, #1
-    35b4:	89a2      	ldrh	r2, [r4, #12]
-    35b6:	4013      	ands	r3, r2
-    35b8:	d011      	beq.n	35de <__swsetup_r+0xd2>
-    35ba:	2300      	movs	r3, #0
-    35bc:	60a3      	str	r3, [r4, #8]
-    35be:	6963      	ldr	r3, [r4, #20]
-    35c0:	425b      	negs	r3, r3
-    35c2:	61a3      	str	r3, [r4, #24]
-    35c4:	2000      	movs	r0, #0
-    35c6:	6923      	ldr	r3, [r4, #16]
-    35c8:	4283      	cmp	r3, r0
-    35ca:	d1be      	bne.n	354a <__swsetup_r+0x3e>
-    35cc:	230c      	movs	r3, #12
-    35ce:	5ee2      	ldrsh	r2, [r4, r3]
-    35d0:	0613      	lsls	r3, r2, #24
-    35d2:	d5ba      	bpl.n	354a <__swsetup_r+0x3e>
-    35d4:	2340      	movs	r3, #64	; 0x40
-    35d6:	4313      	orrs	r3, r2
-    35d8:	81a3      	strh	r3, [r4, #12]
-    35da:	3801      	subs	r0, #1
-    35dc:	e7b5      	b.n	354a <__swsetup_r+0x3e>
-    35de:	0792      	lsls	r2, r2, #30
-    35e0:	d400      	bmi.n	35e4 <__swsetup_r+0xd8>
-    35e2:	6963      	ldr	r3, [r4, #20]
-    35e4:	60a3      	str	r3, [r4, #8]
-    35e6:	e7ed      	b.n	35c4 <__swsetup_r+0xb8>
-    35e8:	20000018 	.word	0x20000018
-    35ec:	000038cc 	.word	0x000038cc
-    35f0:	000038ec 	.word	0x000038ec
-    35f4:	000038ac 	.word	0x000038ac
-
-000035f8 <_close_r>:
-    35f8:	2300      	movs	r3, #0
-    35fa:	b570      	push	{r4, r5, r6, lr}
-    35fc:	4c06      	ldr	r4, [pc, #24]	; (3618 <_close_r+0x20>)
-    35fe:	0005      	movs	r5, r0
-    3600:	0008      	movs	r0, r1
-    3602:	6023      	str	r3, [r4, #0]
-    3604:	f7fe fba8 	bl	1d58 <_close>
-    3608:	1c43      	adds	r3, r0, #1
-    360a:	d103      	bne.n	3614 <_close_r+0x1c>
-    360c:	6823      	ldr	r3, [r4, #0]
-    360e:	2b00      	cmp	r3, #0
-    3610:	d000      	beq.n	3614 <_close_r+0x1c>
-    3612:	602b      	str	r3, [r5, #0]
-    3614:	bd70      	pop	{r4, r5, r6, pc}
-    3616:	46c0      	nop			; (mov r8, r8)
-    3618:	2000029c 	.word	0x2000029c
-
-0000361c <_fstat_r>:
-    361c:	2300      	movs	r3, #0
-    361e:	b570      	push	{r4, r5, r6, lr}
-    3620:	4c06      	ldr	r4, [pc, #24]	; (363c <_fstat_r+0x20>)
-    3622:	0005      	movs	r5, r0
-    3624:	0008      	movs	r0, r1
-    3626:	0011      	movs	r1, r2
-    3628:	6023      	str	r3, [r4, #0]
-    362a:	f7fe fb98 	bl	1d5e <_fstat>
-    362e:	1c43      	adds	r3, r0, #1
-    3630:	d103      	bne.n	363a <_fstat_r+0x1e>
-    3632:	6823      	ldr	r3, [r4, #0]
-    3634:	2b00      	cmp	r3, #0
-    3636:	d000      	beq.n	363a <_fstat_r+0x1e>
-    3638:	602b      	str	r3, [r5, #0]
-    363a:	bd70      	pop	{r4, r5, r6, pc}
-    363c:	2000029c 	.word	0x2000029c
-
-00003640 <_isatty_r>:
-    3640:	2300      	movs	r3, #0
-    3642:	b570      	push	{r4, r5, r6, lr}
-    3644:	4c06      	ldr	r4, [pc, #24]	; (3660 <_isatty_r+0x20>)
-    3646:	0005      	movs	r5, r0
-    3648:	0008      	movs	r0, r1
-    364a:	6023      	str	r3, [r4, #0]
-    364c:	f7fe fb8c 	bl	1d68 <_isatty>
-    3650:	1c43      	adds	r3, r0, #1
-    3652:	d103      	bne.n	365c <_isatty_r+0x1c>
-    3654:	6823      	ldr	r3, [r4, #0]
-    3656:	2b00      	cmp	r3, #0
-    3658:	d000      	beq.n	365c <_isatty_r+0x1c>
-    365a:	602b      	str	r3, [r5, #0]
-    365c:	bd70      	pop	{r4, r5, r6, pc}
-    365e:	46c0      	nop			; (mov r8, r8)
-    3660:	2000029c 	.word	0x2000029c
-
-00003664 <_lseek_r>:
-    3664:	b570      	push	{r4, r5, r6, lr}
-    3666:	0005      	movs	r5, r0
-    3668:	0008      	movs	r0, r1
-    366a:	0011      	movs	r1, r2
-    366c:	2200      	movs	r2, #0
-    366e:	4c06      	ldr	r4, [pc, #24]	; (3688 <_lseek_r+0x24>)
-    3670:	6022      	str	r2, [r4, #0]
-    3672:	001a      	movs	r2, r3
-    3674:	f7fe fb7a 	bl	1d6c <_lseek>
-    3678:	1c43      	adds	r3, r0, #1
-    367a:	d103      	bne.n	3684 <_lseek_r+0x20>
-    367c:	6823      	ldr	r3, [r4, #0]
-    367e:	2b00      	cmp	r3, #0
-    3680:	d000      	beq.n	3684 <_lseek_r+0x20>
-    3682:	602b      	str	r3, [r5, #0]
-    3684:	bd70      	pop	{r4, r5, r6, pc}
-    3686:	46c0      	nop			; (mov r8, r8)
-    3688:	2000029c 	.word	0x2000029c
-
-0000368c <memchr>:
-    368c:	b2c9      	uxtb	r1, r1
-    368e:	1882      	adds	r2, r0, r2
-    3690:	4290      	cmp	r0, r2
-    3692:	d101      	bne.n	3698 <memchr+0xc>
-    3694:	2000      	movs	r0, #0
-    3696:	4770      	bx	lr
-    3698:	7803      	ldrb	r3, [r0, #0]
-    369a:	428b      	cmp	r3, r1
-    369c:	d0fb      	beq.n	3696 <memchr+0xa>
-    369e:	3001      	adds	r0, #1
-    36a0:	e7f6      	b.n	3690 <memchr+0x4>
-
-000036a2 <__malloc_lock>:
-    36a2:	4770      	bx	lr
-
-000036a4 <__malloc_unlock>:
-    36a4:	4770      	bx	lr
-	...
-
-000036a8 <_read_r>:
-    36a8:	b570      	push	{r4, r5, r6, lr}
-    36aa:	0005      	movs	r5, r0
-    36ac:	0008      	movs	r0, r1
-    36ae:	0011      	movs	r1, r2
-    36b0:	2200      	movs	r2, #0
-    36b2:	4c06      	ldr	r4, [pc, #24]	; (36cc <_read_r+0x24>)
-    36b4:	6022      	str	r2, [r4, #0]
-    36b6:	001a      	movs	r2, r3
-    36b8:	f7fd fab4 	bl	c24 <_read>
-    36bc:	1c43      	adds	r3, r0, #1
-    36be:	d103      	bne.n	36c8 <_read_r+0x20>
-    36c0:	6823      	ldr	r3, [r4, #0]
-    36c2:	2b00      	cmp	r3, #0
-    36c4:	d000      	beq.n	36c8 <_read_r+0x20>
-    36c6:	602b      	str	r3, [r5, #0]
-    36c8:	bd70      	pop	{r4, r5, r6, pc}
-    36ca:	46c0      	nop			; (mov r8, r8)
-    36cc:	2000029c 	.word	0x2000029c
-    36d0:	000002fa 	.word	0x000002fa
-    36d4:	00000540 	.word	0x00000540
-    36d8:	00000540 	.word	0x00000540
-    36dc:	00000540 	.word	0x00000540
-    36e0:	00000540 	.word	0x00000540
-    36e4:	00000540 	.word	0x00000540
-    36e8:	00000540 	.word	0x00000540
-    36ec:	00000540 	.word	0x00000540
-    36f0:	00000540 	.word	0x00000540
-    36f4:	00000540 	.word	0x00000540
-    36f8:	00000540 	.word	0x00000540
-    36fc:	00000540 	.word	0x00000540
-    3700:	00000540 	.word	0x00000540
-    3704:	00000540 	.word	0x00000540
-    3708:	00000540 	.word	0x00000540
-    370c:	00000540 	.word	0x00000540
-    3710:	000002e2 	.word	0x000002e2
-    3714:	00000540 	.word	0x00000540
-    3718:	00000540 	.word	0x00000540
-    371c:	00000540 	.word	0x00000540
-    3720:	00000540 	.word	0x00000540
-    3724:	00000540 	.word	0x00000540
-    3728:	00000540 	.word	0x00000540
-    372c:	00000540 	.word	0x00000540
-    3730:	00000540 	.word	0x00000540
-    3734:	00000540 	.word	0x00000540
-    3738:	00000540 	.word	0x00000540
-    373c:	00000540 	.word	0x00000540
-    3740:	00000540 	.word	0x00000540
-    3744:	00000540 	.word	0x00000540
-    3748:	00000540 	.word	0x00000540
-    374c:	00000540 	.word	0x00000540
-    3750:	000002f2 	.word	0x000002f2
-    3754:	00000540 	.word	0x00000540
-    3758:	00000540 	.word	0x00000540
-    375c:	00000540 	.word	0x00000540
-    3760:	00000540 	.word	0x00000540
-    3764:	00000540 	.word	0x00000540
-    3768:	00000540 	.word	0x00000540
-    376c:	00000540 	.word	0x00000540
-    3770:	00000540 	.word	0x00000540
-    3774:	00000540 	.word	0x00000540
-    3778:	00000540 	.word	0x00000540
-    377c:	00000540 	.word	0x00000540
-    3780:	00000540 	.word	0x00000540
-    3784:	00000540 	.word	0x00000540
-    3788:	00000540 	.word	0x00000540
-    378c:	00000540 	.word	0x00000540
-    3790:	000002ea 	.word	0x000002ea
-    3794:	00000302 	.word	0x00000302
-    3798:	000002ca 	.word	0x000002ca
-    379c:	000002da 	.word	0x000002da
-    37a0:	000002d2 	.word	0x000002d2
-    37a4:	00000002 	.word	0x00000002
-    37a8:	00000003 	.word	0x00000003
-    37ac:	00000028 	.word	0x00000028
-    37b0:	00000029 	.word	0x00000029
-    37b4:	00000004 	.word	0x00000004
-    37b8:	00000005 	.word	0x00000005
-    37bc:	00000006 	.word	0x00000006
-    37c0:	00000007 	.word	0x00000007
-    37c4:	00000020 	.word	0x00000020
-    37c8:	00000021 	.word	0x00000021
-    37cc:	00000022 	.word	0x00000022
-    37d0:	00000023 	.word	0x00000023
-    37d4:	00000024 	.word	0x00000024
-    37d8:	00000025 	.word	0x00000025
-    37dc:	00000026 	.word	0x00000026
-    37e0:	00000027 	.word	0x00000027
-    37e4:	00000008 	.word	0x00000008
-    37e8:	00000009 	.word	0x00000009
-    37ec:	0000000a 	.word	0x0000000a
-    37f0:	0000000b 	.word	0x0000000b
-    37f4:	42000800 	.word	0x42000800
-    37f8:	42000c00 	.word	0x42000c00
-    37fc:	42001000 	.word	0x42001000
-    3800:	42001400 	.word	0x42001400
-    3804:	42001800 	.word	0x42001800
-    3808:	42001c00 	.word	0x42001c00
-    380c:	000016be 	.word	0x000016be
-    3810:	000016ba 	.word	0x000016ba
-    3814:	000016ba 	.word	0x000016ba
-    3818:	00001720 	.word	0x00001720
-    381c:	00001720 	.word	0x00001720
-    3820:	000016d2 	.word	0x000016d2
-    3824:	000016c4 	.word	0x000016c4
-    3828:	000016d8 	.word	0x000016d8
-    382c:	0000170e 	.word	0x0000170e
-    3830:	000017a8 	.word	0x000017a8
-    3834:	00001788 	.word	0x00001788
-    3838:	00001788 	.word	0x00001788
-    383c:	00001814 	.word	0x00001814
-    3840:	0000179a 	.word	0x0000179a
-    3844:	000017b6 	.word	0x000017b6
-    3848:	0000178c 	.word	0x0000178c
-    384c:	000017c4 	.word	0x000017c4
-    3850:	00001804 	.word	0x00001804
-    3854:	746c6f56 	.word	0x746c6f56
-    3858:	3a656761 	.word	0x3a656761
-    385c:	2e642520 	.word	0x2e642520
-    3860:	64333025 	.word	0x64333025
-    3864:	00000a0d 	.word	0x00000a0d
-    3868:	0000208c 	.word	0x0000208c
-    386c:	00001fdc 	.word	0x00001fdc
-    3870:	00001fdc 	.word	0x00001fdc
-    3874:	00001fda 	.word	0x00001fda
-    3878:	0000207e 	.word	0x0000207e
-    387c:	0000207e 	.word	0x0000207e
-    3880:	00002074 	.word	0x00002074
-    3884:	00001fda 	.word	0x00001fda
-    3888:	0000207e 	.word	0x0000207e
-    388c:	00002074 	.word	0x00002074
-    3890:	0000207e 	.word	0x0000207e
-    3894:	00001fda 	.word	0x00001fda
-    3898:	00002084 	.word	0x00002084
-    389c:	00002084 	.word	0x00002084
-    38a0:	00002084 	.word	0x00002084
-    38a4:	00002114 	.word	0x00002114
-
-000038a8 <_global_impure_ptr>:
-    38a8:	2000001c                                ... 
-
-000038ac <__sf_fake_stderr>:
-	...
-
-000038cc <__sf_fake_stdin>:
-	...
-
-000038ec <__sf_fake_stdout>:
-	...
-    390c:	2b302d23 6c680020 6665004c 47464567     #-0+ .hlL.efgEFG
-    391c:	32313000 36353433 41393837 45444342     .0123456789ABCDE
-    392c:	31300046 35343332 39383736 64636261     F.0123456789abcd
-    393c:	00006665                                ef..
-
-00003940 <_init>:
-    3940:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    3942:	46c0      	nop			; (mov r8, r8)
-    3944:	bcf8      	pop	{r3, r4, r5, r6, r7}
-    3946:	bc08      	pop	{r3}
-    3948:	469e      	mov	lr, r3
-    394a:	4770      	bx	lr
-
-0000394c <__init_array_start>:
-    394c:	000000dd 	.word	0x000000dd
-
-00003950 <_fini>:
-    3950:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    3952:	46c0      	nop			; (mov r8, r8)
-    3954:	bcf8      	pop	{r3, r4, r5, r6, r7}
-    3956:	bc08      	pop	{r3}
-    3958:	469e      	mov	lr, r3
-    395a:	4770      	bx	lr
-
-0000395c <__fini_array_start>:
-    395c:	000000b5 	.word	0x000000b5
+
+D21_ADC_with_DMA.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00003960  00000000  00000000  00010000  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .relocate     0000007c  20000000  00003960  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000220  20000080  000039e0  0002007c  2**4
+                  ALLOC
+  3 .stack        00002000  200002a0  00003c00  0002007c  2**0
+                  ALLOC
+  4 .ARM.attributes 00000028  00000000  00000000  0002007c  2**0
+                  CONTENTS, READONLY
+  5 .comment      00000059  00000000  00000000  000200a4  2**0
+                  CONTENTS, READONLY
+  6 .debug_info   0002e296  00000000  00000000  000200fd  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  7 .debug_abbrev 00004281  00000000  00000000  0004e393  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  8 .debug_loc    00004e91  00000000  00000000  00052614  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  9 .debug_aranges 00000548  00000000  00000000  000574a5  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 10 .debug_ranges 00000610  00000000  00000000  000579ed  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 11 .debug_macro  0001ca44  00000000  00000000  00057ffd  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_line   0000e317  00000000  00000000  00074a41  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_str    00090169  00000000  00000000  00082d58  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_frame  000014c8  00000000  00000000  00112ec4  2**2
+                  CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <exception_table>:
+       0:	a0 22 00 20 51 1c 00 00 4d 1c 00 00 4d 1c 00 00     .". Q...M...M...
+	...
+      2c:	4d 1c 00 00 00 00 00 00 00 00 00 00 4d 1c 00 00     M...........M...
+      3c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
+      4c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 05 00 00     M...M...M...M...
+      5c:	4d 1c 00 00 4d 1c 00 00 15 15 00 00 25 15 00 00     M...M.......%...
+      6c:	35 15 00 00 45 15 00 00 55 15 00 00 65 15 00 00     5...E...U...e...
+      7c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
+      8c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
+      9c:	4d 1c 00 00 4d 1c 00 00 4d 1c 00 00 4d 1c 00 00     M...M...M...M...
+      ac:	4d 1c 00 00 00 00 00 00                             M.......
+
+000000b4 <__do_global_dtors_aux>:
+      b4:	b510      	push	{r4, lr}
+      b6:	4c06      	ldr	r4, [pc, #24]	; (d0 <__do_global_dtors_aux+0x1c>)
+      b8:	7823      	ldrb	r3, [r4, #0]
+      ba:	2b00      	cmp	r3, #0
+      bc:	d107      	bne.n	ce <__do_global_dtors_aux+0x1a>
+      be:	4b05      	ldr	r3, [pc, #20]	; (d4 <__do_global_dtors_aux+0x20>)
+      c0:	2b00      	cmp	r3, #0
+      c2:	d002      	beq.n	ca <__do_global_dtors_aux+0x16>
+      c4:	4804      	ldr	r0, [pc, #16]	; (d8 <__do_global_dtors_aux+0x24>)
+      c6:	e000      	b.n	ca <__do_global_dtors_aux+0x16>
+      c8:	bf00      	nop
+      ca:	2301      	movs	r3, #1
+      cc:	7023      	strb	r3, [r4, #0]
+      ce:	bd10      	pop	{r4, pc}
+      d0:	20000080 	.word	0x20000080
+      d4:	00000000 	.word	0x00000000
+      d8:	00003960 	.word	0x00003960
+
+000000dc <frame_dummy>:
+      dc:	4b08      	ldr	r3, [pc, #32]	; (100 <frame_dummy+0x24>)
+      de:	b510      	push	{r4, lr}
+      e0:	2b00      	cmp	r3, #0
+      e2:	d003      	beq.n	ec <frame_dummy+0x10>
+      e4:	4907      	ldr	r1, [pc, #28]	; (104 <frame_dummy+0x28>)
+      e6:	4808      	ldr	r0, [pc, #32]	; (108 <frame_dummy+0x2c>)
+      e8:	e000      	b.n	ec <frame_dummy+0x10>
+      ea:	bf00      	nop
+      ec:	4807      	ldr	r0, [pc, #28]	; (10c <frame_dummy+0x30>)
+      ee:	6803      	ldr	r3, [r0, #0]
+      f0:	2b00      	cmp	r3, #0
+      f2:	d100      	bne.n	f6 <frame_dummy+0x1a>
+      f4:	bd10      	pop	{r4, pc}
+      f6:	4b06      	ldr	r3, [pc, #24]	; (110 <frame_dummy+0x34>)
+      f8:	2b00      	cmp	r3, #0
+      fa:	d0fb      	beq.n	f4 <frame_dummy+0x18>
+      fc:	4798      	blx	r3
+      fe:	e7f9      	b.n	f4 <frame_dummy+0x18>
+     100:	00000000 	.word	0x00000000
+     104:	20000084 	.word	0x20000084
+     108:	00003960 	.word	0x00003960
+     10c:	00003960 	.word	0x00003960
+     110:	00000000 	.word	0x00000000
+
+00000114 <adc_get_config_defaults>:
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+     114:	b510      	push	{r4, lr}
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+     116:	2200      	movs	r2, #0
+     118:	2300      	movs	r3, #0
+     11a:	7002      	strb	r2, [r0, #0]
+	config->reference                     = ADC_REFERENCE_INT1V;
+     11c:	7042      	strb	r2, [r0, #1]
+	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
+     11e:	2100      	movs	r1, #0
+     120:	8042      	strh	r2, [r0, #2]
+	config->resolution                    = ADC_RESOLUTION_12BIT;
+     122:	7101      	strb	r1, [r0, #4]
+	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+     124:	7603      	strb	r3, [r0, #24]
+	config->window.window_upper_value     = 0;
+     126:	6202      	str	r2, [r0, #32]
+	config->window.window_lower_value     = 0;
+     128:	61c2      	str	r2, [r0, #28]
+	config->gain_factor                   = ADC_GAIN_FACTOR_1X;
+     12a:	6082      	str	r2, [r0, #8]
+#if SAMR21
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
+#else
+ 	config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
+     12c:	7303      	strb	r3, [r0, #12]
+#endif
+	config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
+     12e:	24c0      	movs	r4, #192	; 0xc0
+     130:	0164      	lsls	r4, r4, #5
+     132:	81c4      	strh	r4, [r0, #14]
+	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+     134:	7403      	strb	r3, [r0, #16]
+	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+     136:	7443      	strb	r3, [r0, #17]
+	config->left_adjust                   = false;
+     138:	7483      	strb	r3, [r0, #18]
+	config->differential_mode             = false;
+     13a:	74c3      	strb	r3, [r0, #19]
+	config->freerunning                   = false;
+     13c:	7503      	strb	r3, [r0, #20]
+	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+     13e:	242a      	movs	r4, #42	; 0x2a
+     140:	5503      	strb	r3, [r0, r4]
+	config->run_in_standby                = false;
+     142:	7543      	strb	r3, [r0, #21]
+	config->reference_compensation_enable = false;
+     144:	7583      	strb	r3, [r0, #22]
+	config->correction.correction_enable  = false;
+     146:	3c06      	subs	r4, #6
+     148:	5503      	strb	r3, [r0, r4]
+	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+     14a:	84c2      	strh	r2, [r0, #38]	; 0x26
+	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+     14c:	8502      	strh	r2, [r0, #40]	; 0x28
+	config->sample_length                 = 0;
+     14e:	75c1      	strb	r1, [r0, #23]
+	config->pin_scan.offset_start_scan    = 0;
+     150:	232b      	movs	r3, #43	; 0x2b
+     152:	54c1      	strb	r1, [r0, r3]
+	config->pin_scan.inputs_to_scan       = 0;
+     154:	3301      	adds	r3, #1
+     156:	54c1      	strb	r1, [r0, r3]
+}
+     158:	bd10      	pop	{r4, pc}
+	...
+
+0000015c <adc_init>:
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config)
+{
+     15c:	b5f0      	push	{r4, r5, r6, r7, lr}
+     15e:	46d6      	mov	lr, sl
+     160:	464f      	mov	r7, r9
+     162:	4646      	mov	r6, r8
+     164:	b5c0      	push	{r6, r7, lr}
+     166:	b096      	sub	sp, #88	; 0x58
+     168:	0007      	movs	r7, r0
+     16a:	0016      	movs	r6, r2
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+     16c:	6001      	str	r1, [r0, #0]
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg |= mask;
+     16e:	4acb      	ldr	r2, [pc, #812]	; (49c <adc_init+0x340>)
+     170:	6a10      	ldr	r0, [r2, #32]
+     172:	2380      	movs	r3, #128	; 0x80
+     174:	025b      	lsls	r3, r3, #9
+     176:	4303      	orrs	r3, r0
+     178:	6213      	str	r3, [r2, #32]
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
+
+	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+     17a:	780b      	ldrb	r3, [r1, #0]
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+     17c:	2005      	movs	r0, #5
+	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+     17e:	07db      	lsls	r3, r3, #31
+     180:	d505      	bpl.n	18e <adc_init+0x32>
+	}
+#endif
+
+	/* Write configuration to module */
+	return _adc_set_config(module_inst, config);
+}
+     182:	b016      	add	sp, #88	; 0x58
+     184:	bc1c      	pop	{r2, r3, r4}
+     186:	4690      	mov	r8, r2
+     188:	4699      	mov	r9, r3
+     18a:	46a2      	mov	sl, r4
+     18c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+     18e:	780b      	ldrb	r3, [r1, #0]
+		return STATUS_ERR_DENIED;
+     190:	3017      	adds	r0, #23
+	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+     192:	079b      	lsls	r3, r3, #30
+     194:	d4f5      	bmi.n	182 <adc_init+0x26>
+	module_inst->reference = config->reference;
+     196:	7873      	ldrb	r3, [r6, #1]
+     198:	713b      	strb	r3, [r7, #4]
+	if (module_inst->reference == ADC_REFERENCE_INT1V) {
+     19a:	2b00      	cmp	r3, #0
+     19c:	d104      	bne.n	1a8 <adc_init+0x4c>
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+     19e:	4ac0      	ldr	r2, [pc, #768]	; (4a0 <adc_init+0x344>)
+     1a0:	6c13      	ldr	r3, [r2, #64]	; 0x40
+     1a2:	2104      	movs	r1, #4
+     1a4:	430b      	orrs	r3, r1
+     1a6:	6413      	str	r3, [r2, #64]	; 0x40
+	Adc *const adc_module = module_inst->hw;
+     1a8:	683b      	ldr	r3, [r7, #0]
+     1aa:	4698      	mov	r8, r3
+	gclk_chan_conf.source_generator = config->clock_source;
+     1ac:	7833      	ldrb	r3, [r6, #0]
+     1ae:	466a      	mov	r2, sp
+     1b0:	7013      	strb	r3, [r2, #0]
+	system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
+     1b2:	4669      	mov	r1, sp
+     1b4:	201e      	movs	r0, #30
+     1b6:	4bbb      	ldr	r3, [pc, #748]	; (4a4 <adc_init+0x348>)
+     1b8:	4798      	blx	r3
+	system_gclk_chan_enable(ADC_GCLK_ID);
+     1ba:	201e      	movs	r0, #30
+     1bc:	4bba      	ldr	r3, [pc, #744]	; (4a8 <adc_init+0x34c>)
+     1be:	4798      	blx	r3
+	if (config->pin_scan.inputs_to_scan != 0) {
+     1c0:	232c      	movs	r3, #44	; 0x2c
+     1c2:	5cf2      	ldrb	r2, [r6, r3]
+     1c4:	2a00      	cmp	r2, #0
+     1c6:	d054      	beq.n	272 <adc_init+0x116>
+		uint8_t offset = config->pin_scan.offset_start_scan;
+     1c8:	3b01      	subs	r3, #1
+     1ca:	5cf5      	ldrb	r5, [r6, r3]
+		uint8_t start_pin =
+     1cc:	7b33      	ldrb	r3, [r6, #12]
+     1ce:	18eb      	adds	r3, r5, r3
+     1d0:	b2db      	uxtb	r3, r3
+		uint8_t end_pin =
+     1d2:	18d1      	adds	r1, r2, r3
+		while (start_pin < end_pin) {
+     1d4:	b2c9      	uxtb	r1, r1
+     1d6:	428b      	cmp	r3, r1
+     1d8:	d221      	bcs.n	21e <adc_init+0xc2>
+     1da:	1952      	adds	r2, r2, r5
+     1dc:	b2d3      	uxtb	r3, r2
+     1de:	4699      	mov	r9, r3
+	const uint32_t pinmapping[] = {
+     1e0:	4bb2      	ldr	r3, [pc, #712]	; (4ac <adc_init+0x350>)
+     1e2:	469a      	mov	sl, r3
+     1e4:	e003      	b.n	1ee <adc_init+0x92>
+			offset++;
+     1e6:	3501      	adds	r5, #1
+     1e8:	b2ed      	uxtb	r5, r5
+		while (start_pin < end_pin) {
+     1ea:	45a9      	cmp	r9, r5
+     1ec:	d017      	beq.n	21e <adc_init+0xc2>
+			_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
+     1ee:	240f      	movs	r4, #15
+     1f0:	402c      	ands	r4, r5
+     1f2:	7b33      	ldrb	r3, [r6, #12]
+     1f4:	18e4      	adds	r4, r4, r3
+	const uint32_t pinmapping[] = {
+     1f6:	2250      	movs	r2, #80	; 0x50
+     1f8:	49ad      	ldr	r1, [pc, #692]	; (4b0 <adc_init+0x354>)
+     1fa:	a802      	add	r0, sp, #8
+     1fc:	47d0      	blx	sl
+	if (pin <= ADC_EXTCHANNEL_MSB) {
+     1fe:	2c13      	cmp	r4, #19
+     200:	d8f1      	bhi.n	1e6 <adc_init+0x8a>
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+     202:	00a4      	lsls	r4, r4, #2
+     204:	ab02      	add	r3, sp, #8
+     206:	58e0      	ldr	r0, [r4, r3]
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+     208:	a901      	add	r1, sp, #4
+     20a:	2300      	movs	r3, #0
+     20c:	704b      	strb	r3, [r1, #1]
+	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	config->powersave    = false;
+     20e:	70cb      	strb	r3, [r1, #3]
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+     210:	708b      	strb	r3, [r1, #2]
+		config.mux_position = 1;
+     212:	3301      	adds	r3, #1
+     214:	700b      	strb	r3, [r1, #0]
+		system_pinmux_pin_set_config(pin_map_result, &config);
+     216:	b2c0      	uxtb	r0, r0
+     218:	4ba6      	ldr	r3, [pc, #664]	; (4b4 <adc_init+0x358>)
+     21a:	4798      	blx	r3
+     21c:	e7e3      	b.n	1e6 <adc_init+0x8a>
+		_adc_configure_ain_pin(config->negative_input);
+     21e:	89f4      	ldrh	r4, [r6, #14]
+	const uint32_t pinmapping[] = {
+     220:	2250      	movs	r2, #80	; 0x50
+     222:	49a3      	ldr	r1, [pc, #652]	; (4b0 <adc_init+0x354>)
+     224:	a802      	add	r0, sp, #8
+     226:	4ba1      	ldr	r3, [pc, #644]	; (4ac <adc_init+0x350>)
+     228:	4798      	blx	r3
+	if (pin <= ADC_EXTCHANNEL_MSB) {
+     22a:	2c13      	cmp	r4, #19
+     22c:	d913      	bls.n	256 <adc_init+0xfa>
+	adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
+     22e:	7d73      	ldrb	r3, [r6, #21]
+     230:	009b      	lsls	r3, r3, #2
+     232:	b2db      	uxtb	r3, r3
+     234:	4642      	mov	r2, r8
+     236:	7013      	strb	r3, [r2, #0]
+			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
+     238:	7db3      	ldrb	r3, [r6, #22]
+     23a:	01db      	lsls	r3, r3, #7
+     23c:	7872      	ldrb	r2, [r6, #1]
+     23e:	4313      	orrs	r3, r2
+     240:	b2db      	uxtb	r3, r3
+	adc_module->REFCTRL.reg =
+     242:	4642      	mov	r2, r8
+     244:	7053      	strb	r3, [r2, #1]
+	switch (config->resolution) {
+     246:	7933      	ldrb	r3, [r6, #4]
+     248:	2b34      	cmp	r3, #52	; 0x34
+     24a:	d900      	bls.n	24e <adc_init+0xf2>
+     24c:	e178      	b.n	540 <adc_init+0x3e4>
+     24e:	009b      	lsls	r3, r3, #2
+     250:	4a99      	ldr	r2, [pc, #612]	; (4b8 <adc_init+0x35c>)
+     252:	58d3      	ldr	r3, [r2, r3]
+     254:	469f      	mov	pc, r3
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+     256:	00a4      	lsls	r4, r4, #2
+     258:	ab02      	add	r3, sp, #8
+     25a:	58e0      	ldr	r0, [r4, r3]
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+     25c:	a901      	add	r1, sp, #4
+     25e:	2300      	movs	r3, #0
+     260:	704b      	strb	r3, [r1, #1]
+	config->powersave    = false;
+     262:	70cb      	strb	r3, [r1, #3]
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+     264:	708b      	strb	r3, [r1, #2]
+		config.mux_position = 1;
+     266:	3301      	adds	r3, #1
+     268:	700b      	strb	r3, [r1, #0]
+		system_pinmux_pin_set_config(pin_map_result, &config);
+     26a:	b2c0      	uxtb	r0, r0
+     26c:	4b91      	ldr	r3, [pc, #580]	; (4b4 <adc_init+0x358>)
+     26e:	4798      	blx	r3
+     270:	e7dd      	b.n	22e <adc_init+0xd2>
+		_adc_configure_ain_pin(config->positive_input);
+     272:	7b34      	ldrb	r4, [r6, #12]
+	const uint32_t pinmapping[] = {
+     274:	2250      	movs	r2, #80	; 0x50
+     276:	498e      	ldr	r1, [pc, #568]	; (4b0 <adc_init+0x354>)
+     278:	a802      	add	r0, sp, #8
+     27a:	4b8c      	ldr	r3, [pc, #560]	; (4ac <adc_init+0x350>)
+     27c:	4798      	blx	r3
+	if (pin <= ADC_EXTCHANNEL_MSB) {
+     27e:	2c13      	cmp	r4, #19
+     280:	d915      	bls.n	2ae <adc_init+0x152>
+		_adc_configure_ain_pin(config->negative_input);
+     282:	89f4      	ldrh	r4, [r6, #14]
+	const uint32_t pinmapping[] = {
+     284:	2250      	movs	r2, #80	; 0x50
+     286:	498a      	ldr	r1, [pc, #552]	; (4b0 <adc_init+0x354>)
+     288:	a802      	add	r0, sp, #8
+     28a:	4b88      	ldr	r3, [pc, #544]	; (4ac <adc_init+0x350>)
+     28c:	4798      	blx	r3
+	if (pin <= ADC_EXTCHANNEL_MSB) {
+     28e:	2c13      	cmp	r4, #19
+     290:	d8cd      	bhi.n	22e <adc_init+0xd2>
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+     292:	00a4      	lsls	r4, r4, #2
+     294:	ab02      	add	r3, sp, #8
+     296:	58e0      	ldr	r0, [r4, r3]
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+     298:	a901      	add	r1, sp, #4
+     29a:	2300      	movs	r3, #0
+     29c:	704b      	strb	r3, [r1, #1]
+	config->powersave    = false;
+     29e:	70cb      	strb	r3, [r1, #3]
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+     2a0:	708b      	strb	r3, [r1, #2]
+		config.mux_position = 1;
+     2a2:	3301      	adds	r3, #1
+     2a4:	700b      	strb	r3, [r1, #0]
+		system_pinmux_pin_set_config(pin_map_result, &config);
+     2a6:	b2c0      	uxtb	r0, r0
+     2a8:	4b82      	ldr	r3, [pc, #520]	; (4b4 <adc_init+0x358>)
+     2aa:	4798      	blx	r3
+     2ac:	e7bf      	b.n	22e <adc_init+0xd2>
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+     2ae:	00a4      	lsls	r4, r4, #2
+     2b0:	ab02      	add	r3, sp, #8
+     2b2:	58e0      	ldr	r0, [r4, r3]
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+     2b4:	a901      	add	r1, sp, #4
+     2b6:	2300      	movs	r3, #0
+     2b8:	704b      	strb	r3, [r1, #1]
+	config->powersave    = false;
+     2ba:	70cb      	strb	r3, [r1, #3]
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+     2bc:	708b      	strb	r3, [r1, #2]
+		config.mux_position = 1;
+     2be:	3301      	adds	r3, #1
+     2c0:	700b      	strb	r3, [r1, #0]
+		system_pinmux_pin_set_config(pin_map_result, &config);
+     2c2:	b2c0      	uxtb	r0, r0
+     2c4:	4b7b      	ldr	r3, [pc, #492]	; (4b4 <adc_init+0x358>)
+     2c6:	4798      	blx	r3
+     2c8:	e7db      	b.n	282 <adc_init+0x126>
+		accumulate = ADC_ACCUMULATE_SAMPLES_16;
+     2ca:	2304      	movs	r3, #4
+		resolution = ADC_RESOLUTION_16BIT;
+     2cc:	2410      	movs	r4, #16
+		adjres = ADC_DIVIDE_RESULT_4;
+     2ce:	2102      	movs	r1, #2
+     2d0:	e01a      	b.n	308 <adc_init+0x1ac>
+		adjres = config->divide_result;
+     2d2:	7c71      	ldrb	r1, [r6, #17]
+		accumulate = config->accumulate_samples;
+     2d4:	7c33      	ldrb	r3, [r6, #16]
+		resolution = ADC_RESOLUTION_16BIT;
+     2d6:	2410      	movs	r4, #16
+     2d8:	e016      	b.n	308 <adc_init+0x1ac>
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+     2da:	2306      	movs	r3, #6
+		resolution = ADC_RESOLUTION_16BIT;
+     2dc:	2410      	movs	r4, #16
+		adjres = ADC_DIVIDE_RESULT_2;
+     2de:	2101      	movs	r1, #1
+     2e0:	e012      	b.n	308 <adc_init+0x1ac>
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+     2e2:	2308      	movs	r3, #8
+		resolution = ADC_RESOLUTION_16BIT;
+     2e4:	2410      	movs	r4, #16
+		adjres = ADC_DIVIDE_RESULT_DISABLE;
+     2e6:	2100      	movs	r1, #0
+     2e8:	e00e      	b.n	308 <adc_init+0x1ac>
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+     2ea:	2300      	movs	r3, #0
+		resolution = ADC_RESOLUTION_8BIT;
+     2ec:	2430      	movs	r4, #48	; 0x30
+	uint8_t adjres = 0;
+     2ee:	2100      	movs	r1, #0
+     2f0:	e00a      	b.n	308 <adc_init+0x1ac>
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+     2f2:	2300      	movs	r3, #0
+		resolution = ADC_RESOLUTION_10BIT;
+     2f4:	2420      	movs	r4, #32
+	uint8_t adjres = 0;
+     2f6:	2100      	movs	r1, #0
+     2f8:	e006      	b.n	308 <adc_init+0x1ac>
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+     2fa:	2300      	movs	r3, #0
+		resolution = ADC_RESOLUTION_12BIT;
+     2fc:	2400      	movs	r4, #0
+	uint8_t adjres = 0;
+     2fe:	2100      	movs	r1, #0
+     300:	e002      	b.n	308 <adc_init+0x1ac>
+		accumulate = ADC_ACCUMULATE_SAMPLES_4;
+     302:	2302      	movs	r3, #2
+		resolution = ADC_RESOLUTION_16BIT;
+     304:	2410      	movs	r4, #16
+		adjres = ADC_DIVIDE_RESULT_2;
+     306:	2101      	movs	r1, #1
+	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+     308:	0109      	lsls	r1, r1, #4
+     30a:	2270      	movs	r2, #112	; 0x70
+     30c:	400a      	ands	r2, r1
+     30e:	4313      	orrs	r3, r2
+     310:	4642      	mov	r2, r8
+     312:	7093      	strb	r3, [r2, #2]
+	if (config->sample_length > 63) {
+     314:	7df3      	ldrb	r3, [r6, #23]
+		return STATUS_ERR_INVALID_ARG;
+     316:	2017      	movs	r0, #23
+	if (config->sample_length > 63) {
+     318:	2b3f      	cmp	r3, #63	; 0x3f
+     31a:	d900      	bls.n	31e <adc_init+0x1c2>
+     31c:	e731      	b.n	182 <adc_init+0x26>
+		adc_module->SAMPCTRL.reg =
+     31e:	70d3      	strb	r3, [r2, #3]
+	struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+     320:	683a      	ldr	r2, [r7, #0]
+
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+     322:	7e53      	ldrb	r3, [r2, #25]
+	while (adc_is_syncing(module_inst)) {
+     324:	b25b      	sxtb	r3, r3
+     326:	2b00      	cmp	r3, #0
+     328:	dbfb      	blt.n	322 <adc_init+0x1c6>
+			(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
+     32a:	7cf3      	ldrb	r3, [r6, #19]
+			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+     32c:	8872      	ldrh	r2, [r6, #2]
+     32e:	4313      	orrs	r3, r2
+			(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
+     330:	2224      	movs	r2, #36	; 0x24
+     332:	5cb2      	ldrb	r2, [r6, r2]
+     334:	00d2      	lsls	r2, r2, #3
+			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+     336:	4313      	orrs	r3, r2
+			(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
+     338:	7d32      	ldrb	r2, [r6, #20]
+     33a:	0092      	lsls	r2, r2, #2
+			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+     33c:	4313      	orrs	r3, r2
+     33e:	7cb2      	ldrb	r2, [r6, #18]
+     340:	0052      	lsls	r2, r2, #1
+     342:	4313      	orrs	r3, r2
+     344:	4323      	orrs	r3, r4
+	adc_module->CTRLB.reg =
+     346:	4642      	mov	r2, r8
+     348:	8093      	strh	r3, [r2, #4]
+	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
+     34a:	7e33      	ldrb	r3, [r6, #24]
+     34c:	2b00      	cmp	r3, #0
+     34e:	d020      	beq.n	392 <adc_init+0x236>
+		switch (resolution) {
+     350:	2c10      	cmp	r4, #16
+     352:	d100      	bne.n	356 <adc_init+0x1fa>
+     354:	e0d6      	b.n	504 <adc_init+0x3a8>
+     356:	d800      	bhi.n	35a <adc_init+0x1fe>
+     358:	e080      	b.n	45c <adc_init+0x300>
+     35a:	2c20      	cmp	r4, #32
+     35c:	d100      	bne.n	360 <adc_init+0x204>
+     35e:	e0b3      	b.n	4c8 <adc_init+0x36c>
+     360:	2c30      	cmp	r4, #48	; 0x30
+     362:	d116      	bne.n	392 <adc_init+0x236>
+			if (config->differential_mode &&
+     364:	7cf2      	ldrb	r2, [r6, #19]
+     366:	2a00      	cmp	r2, #0
+     368:	d00a      	beq.n	380 <adc_init+0x224>
+					(config->window.window_lower_value > 127 ||
+     36a:	69f2      	ldr	r2, [r6, #28]
+     36c:	3280      	adds	r2, #128	; 0x80
+				return STATUS_ERR_INVALID_ARG;
+     36e:	2017      	movs	r0, #23
+			if (config->differential_mode &&
+     370:	2aff      	cmp	r2, #255	; 0xff
+     372:	d900      	bls.n	376 <adc_init+0x21a>
+     374:	e705      	b.n	182 <adc_init+0x26>
+					config->window.window_lower_value < -128 ||
+     376:	6a32      	ldr	r2, [r6, #32]
+     378:	3280      	adds	r2, #128	; 0x80
+     37a:	2aff      	cmp	r2, #255	; 0xff
+     37c:	d900      	bls.n	380 <adc_init+0x224>
+     37e:	e700      	b.n	182 <adc_init+0x26>
+				return STATUS_ERR_INVALID_ARG;
+     380:	2017      	movs	r0, #23
+			} else if (config->window.window_lower_value > 255 ||
+     382:	69f2      	ldr	r2, [r6, #28]
+     384:	2aff      	cmp	r2, #255	; 0xff
+     386:	dd00      	ble.n	38a <adc_init+0x22e>
+     388:	e6fb      	b.n	182 <adc_init+0x26>
+     38a:	6a32      	ldr	r2, [r6, #32]
+     38c:	2aff      	cmp	r2, #255	; 0xff
+     38e:	dd00      	ble.n	392 <adc_init+0x236>
+     390:	e6f7      	b.n	182 <adc_init+0x26>
+	Adc *const adc_module = module_inst->hw;
+     392:	6839      	ldr	r1, [r7, #0]
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+     394:	7e4a      	ldrb	r2, [r1, #25]
+	while (adc_is_syncing(module_inst)) {
+     396:	b252      	sxtb	r2, r2
+     398:	2a00      	cmp	r2, #0
+     39a:	dbfb      	blt.n	394 <adc_init+0x238>
+	adc_module->WINCTRL.reg = config->window.window_mode;
+     39c:	4642      	mov	r2, r8
+     39e:	7213      	strb	r3, [r2, #8]
+	Adc *const adc_module = module_inst->hw;
+     3a0:	683a      	ldr	r2, [r7, #0]
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+     3a2:	7e53      	ldrb	r3, [r2, #25]
+	while (adc_is_syncing(module_inst)) {
+     3a4:	b25b      	sxtb	r3, r3
+     3a6:	2b00      	cmp	r3, #0
+     3a8:	dbfb      	blt.n	3a2 <adc_init+0x246>
+	adc_module->WINLT.reg =
+     3aa:	8bb3      	ldrh	r3, [r6, #28]
+     3ac:	4642      	mov	r2, r8
+     3ae:	8393      	strh	r3, [r2, #28]
+	Adc *const adc_module = module_inst->hw;
+     3b0:	683a      	ldr	r2, [r7, #0]
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+     3b2:	7e53      	ldrb	r3, [r2, #25]
+	while (adc_is_syncing(module_inst)) {
+     3b4:	b25b      	sxtb	r3, r3
+     3b6:	2b00      	cmp	r3, #0
+     3b8:	dbfb      	blt.n	3b2 <adc_init+0x256>
+	adc_module->WINUT.reg = config->window.window_upper_value <<
+     3ba:	8c33      	ldrh	r3, [r6, #32]
+     3bc:	4642      	mov	r2, r8
+     3be:	8413      	strh	r3, [r2, #32]
+	uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
+     3c0:	232c      	movs	r3, #44	; 0x2c
+     3c2:	5cf3      	ldrb	r3, [r6, r3]
+	if (inputs_to_scan > 0) {
+     3c4:	2b00      	cmp	r3, #0
+     3c6:	d005      	beq.n	3d4 <adc_init+0x278>
+		inputs_to_scan--;
+     3c8:	3b01      	subs	r3, #1
+     3ca:	b2db      	uxtb	r3, r3
+		return STATUS_ERR_INVALID_ARG;
+     3cc:	2017      	movs	r0, #23
+	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+     3ce:	2b0f      	cmp	r3, #15
+     3d0:	d900      	bls.n	3d4 <adc_init+0x278>
+     3d2:	e6d6      	b.n	182 <adc_init+0x26>
+			config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+     3d4:	222b      	movs	r2, #43	; 0x2b
+     3d6:	5cb1      	ldrb	r1, [r6, r2]
+		return STATUS_ERR_INVALID_ARG;
+     3d8:	2017      	movs	r0, #23
+	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+     3da:	290f      	cmp	r1, #15
+     3dc:	d900      	bls.n	3e0 <adc_init+0x284>
+     3de:	e6d0      	b.n	182 <adc_init+0x26>
+	Adc *const adc_module = module_inst->hw;
+     3e0:	6838      	ldr	r0, [r7, #0]
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+     3e2:	7e42      	ldrb	r2, [r0, #25]
+	while (adc_is_syncing(module_inst)) {
+     3e4:	b252      	sxtb	r2, r2
+     3e6:	2a00      	cmp	r2, #0
+     3e8:	dbfb      	blt.n	3e2 <adc_init+0x286>
+			config->negative_input |
+     3ea:	89f2      	ldrh	r2, [r6, #14]
+			config->positive_input;
+     3ec:	7b30      	ldrb	r0, [r6, #12]
+			config->negative_input |
+     3ee:	4302      	orrs	r2, r0
+     3f0:	68b0      	ldr	r0, [r6, #8]
+     3f2:	4302      	orrs	r2, r0
+			(config->pin_scan.offset_start_scan <<
+     3f4:	0509      	lsls	r1, r1, #20
+			config->negative_input |
+     3f6:	430a      	orrs	r2, r1
+			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
+     3f8:	041b      	lsls	r3, r3, #16
+			config->negative_input |
+     3fa:	4313      	orrs	r3, r2
+	adc_module->INPUTCTRL.reg =
+     3fc:	4642      	mov	r2, r8
+     3fe:	6113      	str	r3, [r2, #16]
+	adc_module->EVCTRL.reg = config->event_action;
+     400:	232a      	movs	r3, #42	; 0x2a
+     402:	5cf3      	ldrb	r3, [r6, r3]
+     404:	7513      	strb	r3, [r2, #20]
+	adc_module->INTENCLR.reg =
+     406:	230f      	movs	r3, #15
+     408:	7593      	strb	r3, [r2, #22]
+	if (config->correction.correction_enable){
+     40a:	3315      	adds	r3, #21
+     40c:	5cf3      	ldrb	r3, [r6, r3]
+     40e:	2b00      	cmp	r3, #0
+     410:	d012      	beq.n	438 <adc_init+0x2dc>
+		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+     412:	8cf3      	ldrh	r3, [r6, #38]	; 0x26
+     414:	4a29      	ldr	r2, [pc, #164]	; (4bc <adc_init+0x360>)
+			return STATUS_ERR_INVALID_ARG;
+     416:	2017      	movs	r0, #23
+		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+     418:	4293      	cmp	r3, r2
+     41a:	d900      	bls.n	41e <adc_init+0x2c2>
+     41c:	e6b1      	b.n	182 <adc_init+0x26>
+			adc_module->GAINCORR.reg = config->correction.gain_correction <<
+     41e:	4642      	mov	r2, r8
+     420:	8493      	strh	r3, [r2, #36]	; 0x24
+		if (config->correction.offset_correction > 2047 ||
+     422:	8d32      	ldrh	r2, [r6, #40]	; 0x28
+     424:	2380      	movs	r3, #128	; 0x80
+     426:	011b      	lsls	r3, r3, #4
+     428:	18d3      	adds	r3, r2, r3
+     42a:	4924      	ldr	r1, [pc, #144]	; (4bc <adc_init+0x360>)
+     42c:	b29b      	uxth	r3, r3
+     42e:	428b      	cmp	r3, r1
+     430:	d900      	bls.n	434 <adc_init+0x2d8>
+     432:	e6a6      	b.n	182 <adc_init+0x26>
+			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+     434:	4643      	mov	r3, r8
+     436:	84da      	strh	r2, [r3, #38]	; 0x26
+			ADC_CALIB_BIAS_CAL(
+     438:	4b21      	ldr	r3, [pc, #132]	; (4c0 <adc_init+0x364>)
+     43a:	681b      	ldr	r3, [r3, #0]
+     43c:	015b      	lsls	r3, r3, #5
+     43e:	22e0      	movs	r2, #224	; 0xe0
+     440:	00d2      	lsls	r2, r2, #3
+     442:	4013      	ands	r3, r2
+			ADC_CALIB_LINEARITY_CAL(
+     444:	4a1f      	ldr	r2, [pc, #124]	; (4c4 <adc_init+0x368>)
+     446:	6851      	ldr	r1, [r2, #4]
+     448:	0149      	lsls	r1, r1, #5
+     44a:	6812      	ldr	r2, [r2, #0]
+     44c:	0ed2      	lsrs	r2, r2, #27
+     44e:	430a      	orrs	r2, r1
+     450:	b2d2      	uxtb	r2, r2
+			) |
+     452:	4313      	orrs	r3, r2
+	adc_module->CALIB.reg =
+     454:	4642      	mov	r2, r8
+     456:	8513      	strh	r3, [r2, #40]	; 0x28
+	return STATUS_OK;
+     458:	2000      	movs	r0, #0
+     45a:	e692      	b.n	182 <adc_init+0x26>
+		switch (resolution) {
+     45c:	2c00      	cmp	r4, #0
+     45e:	d198      	bne.n	392 <adc_init+0x236>
+			if (config->differential_mode &&
+     460:	7cf2      	ldrb	r2, [r6, #19]
+     462:	2a00      	cmp	r2, #0
+     464:	d00f      	beq.n	486 <adc_init+0x32a>
+					(config->window.window_lower_value > 2047 ||
+     466:	69f2      	ldr	r2, [r6, #28]
+     468:	2180      	movs	r1, #128	; 0x80
+     46a:	0109      	lsls	r1, r1, #4
+     46c:	468c      	mov	ip, r1
+     46e:	4462      	add	r2, ip
+			if (config->differential_mode &&
+     470:	4912      	ldr	r1, [pc, #72]	; (4bc <adc_init+0x360>)
+				return STATUS_ERR_INVALID_ARG;
+     472:	2017      	movs	r0, #23
+			if (config->differential_mode &&
+     474:	428a      	cmp	r2, r1
+     476:	d900      	bls.n	47a <adc_init+0x31e>
+     478:	e683      	b.n	182 <adc_init+0x26>
+					config->window.window_lower_value < -2048 ||
+     47a:	6a32      	ldr	r2, [r6, #32]
+     47c:	4462      	add	r2, ip
+     47e:	490f      	ldr	r1, [pc, #60]	; (4bc <adc_init+0x360>)
+     480:	428a      	cmp	r2, r1
+     482:	d900      	bls.n	486 <adc_init+0x32a>
+     484:	e67d      	b.n	182 <adc_init+0x26>
+			} else if (config->window.window_lower_value > 4095 ||
+     486:	4a0d      	ldr	r2, [pc, #52]	; (4bc <adc_init+0x360>)
+				return STATUS_ERR_INVALID_ARG;
+     488:	2017      	movs	r0, #23
+			} else if (config->window.window_lower_value > 4095 ||
+     48a:	69f1      	ldr	r1, [r6, #28]
+     48c:	4291      	cmp	r1, r2
+     48e:	dd00      	ble.n	492 <adc_init+0x336>
+     490:	e677      	b.n	182 <adc_init+0x26>
+     492:	6a31      	ldr	r1, [r6, #32]
+     494:	4291      	cmp	r1, r2
+     496:	dd00      	ble.n	49a <adc_init+0x33e>
+     498:	e673      	b.n	182 <adc_init+0x26>
+     49a:	e77a      	b.n	392 <adc_init+0x236>
+     49c:	40000400 	.word	0x40000400
+     4a0:	40000800 	.word	0x40000800
+     4a4:	00001af5 	.word	0x00001af5
+     4a8:	00001a69 	.word	0x00001a69
+     4ac:	000026c9 	.word	0x000026c9
+     4b0:	000037a4 	.word	0x000037a4
+     4b4:	00001bed 	.word	0x00001bed
+     4b8:	000036d0 	.word	0x000036d0
+     4bc:	00000fff 	.word	0x00000fff
+     4c0:	00806024 	.word	0x00806024
+     4c4:	00806020 	.word	0x00806020
+			if (config->differential_mode &&
+     4c8:	7cf2      	ldrb	r2, [r6, #19]
+     4ca:	2a00      	cmp	r2, #0
+     4cc:	d00f      	beq.n	4ee <adc_init+0x392>
+					(config->window.window_lower_value > 511 ||
+     4ce:	69f2      	ldr	r2, [r6, #28]
+     4d0:	2180      	movs	r1, #128	; 0x80
+     4d2:	0089      	lsls	r1, r1, #2
+     4d4:	468c      	mov	ip, r1
+     4d6:	4462      	add	r2, ip
+			if (config->differential_mode &&
+     4d8:	491a      	ldr	r1, [pc, #104]	; (544 <adc_init+0x3e8>)
+				return STATUS_ERR_INVALID_ARG;
+     4da:	2017      	movs	r0, #23
+			if (config->differential_mode &&
+     4dc:	428a      	cmp	r2, r1
+     4de:	d900      	bls.n	4e2 <adc_init+0x386>
+     4e0:	e64f      	b.n	182 <adc_init+0x26>
+					config->window.window_lower_value < -512 ||
+     4e2:	6a32      	ldr	r2, [r6, #32]
+     4e4:	4462      	add	r2, ip
+     4e6:	4917      	ldr	r1, [pc, #92]	; (544 <adc_init+0x3e8>)
+     4e8:	428a      	cmp	r2, r1
+     4ea:	d900      	bls.n	4ee <adc_init+0x392>
+     4ec:	e649      	b.n	182 <adc_init+0x26>
+			} else if (config->window.window_lower_value > 1023 ||
+     4ee:	4a15      	ldr	r2, [pc, #84]	; (544 <adc_init+0x3e8>)
+				return STATUS_ERR_INVALID_ARG;
+     4f0:	2017      	movs	r0, #23
+			} else if (config->window.window_lower_value > 1023 ||
+     4f2:	69f1      	ldr	r1, [r6, #28]
+     4f4:	4291      	cmp	r1, r2
+     4f6:	dd00      	ble.n	4fa <adc_init+0x39e>
+     4f8:	e643      	b.n	182 <adc_init+0x26>
+     4fa:	6a31      	ldr	r1, [r6, #32]
+     4fc:	4291      	cmp	r1, r2
+     4fe:	dd00      	ble.n	502 <adc_init+0x3a6>
+     500:	e63f      	b.n	182 <adc_init+0x26>
+     502:	e746      	b.n	392 <adc_init+0x236>
+			if (config->differential_mode &&
+     504:	7cf2      	ldrb	r2, [r6, #19]
+     506:	2a00      	cmp	r2, #0
+     508:	d00f      	beq.n	52a <adc_init+0x3ce>
+					(config->window.window_lower_value > 32767 ||
+     50a:	69f2      	ldr	r2, [r6, #28]
+     50c:	2180      	movs	r1, #128	; 0x80
+     50e:	0209      	lsls	r1, r1, #8
+     510:	468c      	mov	ip, r1
+     512:	4462      	add	r2, ip
+			if (config->differential_mode &&
+     514:	490c      	ldr	r1, [pc, #48]	; (548 <adc_init+0x3ec>)
+				return STATUS_ERR_INVALID_ARG;
+     516:	2017      	movs	r0, #23
+			if (config->differential_mode &&
+     518:	428a      	cmp	r2, r1
+     51a:	d900      	bls.n	51e <adc_init+0x3c2>
+     51c:	e631      	b.n	182 <adc_init+0x26>
+					config->window.window_lower_value < -32768 ||
+     51e:	6a32      	ldr	r2, [r6, #32]
+     520:	4462      	add	r2, ip
+     522:	4909      	ldr	r1, [pc, #36]	; (548 <adc_init+0x3ec>)
+     524:	428a      	cmp	r2, r1
+     526:	d900      	bls.n	52a <adc_init+0x3ce>
+     528:	e62b      	b.n	182 <adc_init+0x26>
+			} else if (config->window.window_lower_value > 65535 ||
+     52a:	4a07      	ldr	r2, [pc, #28]	; (548 <adc_init+0x3ec>)
+				return STATUS_ERR_INVALID_ARG;
+     52c:	2017      	movs	r0, #23
+			} else if (config->window.window_lower_value > 65535 ||
+     52e:	69f1      	ldr	r1, [r6, #28]
+     530:	4291      	cmp	r1, r2
+     532:	dd00      	ble.n	536 <adc_init+0x3da>
+     534:	e625      	b.n	182 <adc_init+0x26>
+     536:	6a31      	ldr	r1, [r6, #32]
+     538:	4291      	cmp	r1, r2
+     53a:	dd00      	ble.n	53e <adc_init+0x3e2>
+     53c:	e621      	b.n	182 <adc_init+0x26>
+     53e:	e728      	b.n	392 <adc_init+0x236>
+		return STATUS_ERR_INVALID_ARG;
+     540:	2017      	movs	r0, #23
+     542:	e61e      	b.n	182 <adc_init+0x26>
+     544:	000003ff 	.word	0x000003ff
+     548:	0000ffff 	.word	0x0000ffff
+
+0000054c <DMAC_Handler>:
+/**
+ * \brief DMA interrupt service routine.
+ *
+ */
+void DMAC_Handler( void )
+{
+     54c:	b510      	push	{r4, lr}
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+	cpu_irq_enter_critical();
+     54e:	4b26      	ldr	r3, [pc, #152]	; (5e8 <DMAC_Handler+0x9c>)
+     550:	4798      	blx	r3
+	uint32_t total_size;
+
+	system_interrupt_enter_critical_section();
+
+	/* Get Pending channel */
+	active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
+     552:	4926      	ldr	r1, [pc, #152]	; (5ec <DMAC_Handler+0xa0>)
+     554:	8c0b      	ldrh	r3, [r1, #32]
+     556:	220f      	movs	r2, #15
+
+	Assert(_dma_active_resource[active_channel]);
+
+	/* Get active DMA resource based on channel */
+	resource = _dma_active_resource[active_channel];
+     558:	4013      	ands	r3, r2
+     55a:	009b      	lsls	r3, r3, #2
+     55c:	4824      	ldr	r0, [pc, #144]	; (5f0 <DMAC_Handler+0xa4>)
+     55e:	5818      	ldr	r0, [r3, r0]
+
+	/* Select the active channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+     560:	7803      	ldrb	r3, [r0, #0]
+     562:	401a      	ands	r2, r3
+     564:	233f      	movs	r3, #63	; 0x3f
+     566:	54ca      	strb	r2, [r1, r3]
+	isr = DMAC->CHINTFLAG.reg;
+     568:	330f      	adds	r3, #15
+     56a:	5cca      	ldrb	r2, [r1, r3]
+     56c:	b2d2      	uxtb	r2, r2
+
+	/* Calculate block transfer size of the DMA transfer */
+	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+     56e:	7803      	ldrb	r3, [r0, #0]
+     570:	011b      	lsls	r3, r3, #4
+     572:	4920      	ldr	r1, [pc, #128]	; (5f4 <DMAC_Handler+0xa8>)
+     574:	18c9      	adds	r1, r1, r3
+     576:	8849      	ldrh	r1, [r1, #2]
+	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+     578:	4c1f      	ldr	r4, [pc, #124]	; (5f8 <DMAC_Handler+0xac>)
+     57a:	18e3      	adds	r3, r4, r3
+     57c:	885b      	ldrh	r3, [r3, #2]
+	resource->transfered_size = total_size - write_size;
+     57e:	1acb      	subs	r3, r1, r3
+     580:	6143      	str	r3, [r0, #20]
+
+	/* DMA channel interrupt handler */
+	if (isr & DMAC_CHINTENCLR_TERR) {
+     582:	07d3      	lsls	r3, r2, #31
+     584:	d50f      	bpl.n	5a6 <DMAC_Handler+0x5a>
+		/* Clear transfer error flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
+     586:	2101      	movs	r1, #1
+     588:	234e      	movs	r3, #78	; 0x4e
+     58a:	4a18      	ldr	r2, [pc, #96]	; (5ec <DMAC_Handler+0xa0>)
+     58c:	54d1      	strb	r1, [r2, r3]
+
+		/* Set I/O ERROR status */
+		resource->job_status = STATUS_ERR_IO;
+     58e:	3b3e      	subs	r3, #62	; 0x3e
+     590:	7443      	strb	r3, [r0, #17]
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
+     592:	7c03      	ldrb	r3, [r0, #16]
+     594:	07db      	lsls	r3, r3, #31
+     596:	d503      	bpl.n	5a0 <DMAC_Handler+0x54>
+				(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
+     598:	6843      	ldr	r3, [r0, #4]
+		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
+     59a:	2b00      	cmp	r3, #0
+     59c:	d000      	beq.n	5a0 <DMAC_Handler+0x54>
+			resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
+     59e:	4798      	blx	r3
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+	cpu_irq_leave_critical();
+     5a0:	4b16      	ldr	r3, [pc, #88]	; (5fc <DMAC_Handler+0xb0>)
+     5a2:	4798      	blx	r3
+			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
+		}
+	}
+
+	system_interrupt_leave_critical_section();
+}
+     5a4:	bd10      	pop	{r4, pc}
+	} else if (isr & DMAC_CHINTENCLR_TCMPL) {
+     5a6:	0793      	lsls	r3, r2, #30
+     5a8:	d50d      	bpl.n	5c6 <DMAC_Handler+0x7a>
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
+     5aa:	2102      	movs	r1, #2
+     5ac:	234e      	movs	r3, #78	; 0x4e
+     5ae:	4a0f      	ldr	r2, [pc, #60]	; (5ec <DMAC_Handler+0xa0>)
+     5b0:	54d1      	strb	r1, [r2, r3]
+		resource->job_status = STATUS_OK;
+     5b2:	2300      	movs	r3, #0
+     5b4:	7443      	strb	r3, [r0, #17]
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
+     5b6:	7c03      	ldrb	r3, [r0, #16]
+     5b8:	079b      	lsls	r3, r3, #30
+     5ba:	d5f1      	bpl.n	5a0 <DMAC_Handler+0x54>
+				(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
+     5bc:	6883      	ldr	r3, [r0, #8]
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
+     5be:	2b00      	cmp	r3, #0
+     5c0:	d0ee      	beq.n	5a0 <DMAC_Handler+0x54>
+			resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
+     5c2:	4798      	blx	r3
+     5c4:	e7ec      	b.n	5a0 <DMAC_Handler+0x54>
+	} else if (isr & DMAC_CHINTENCLR_SUSP) {
+     5c6:	0753      	lsls	r3, r2, #29
+     5c8:	d5ea      	bpl.n	5a0 <DMAC_Handler+0x54>
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
+     5ca:	2104      	movs	r1, #4
+     5cc:	234e      	movs	r3, #78	; 0x4e
+     5ce:	4a07      	ldr	r2, [pc, #28]	; (5ec <DMAC_Handler+0xa0>)
+     5d0:	54d1      	strb	r1, [r2, r3]
+		resource->job_status = STATUS_SUSPEND;
+     5d2:	3b48      	subs	r3, #72	; 0x48
+     5d4:	7443      	strb	r3, [r0, #17]
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
+     5d6:	7c03      	ldrb	r3, [r0, #16]
+     5d8:	075b      	lsls	r3, r3, #29
+     5da:	d5e1      	bpl.n	5a0 <DMAC_Handler+0x54>
+			(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
+     5dc:	68c3      	ldr	r3, [r0, #12]
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
+     5de:	2b00      	cmp	r3, #0
+     5e0:	d0de      	beq.n	5a0 <DMAC_Handler+0x54>
+			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
+     5e2:	4798      	blx	r3
+     5e4:	e7dc      	b.n	5a0 <DMAC_Handler+0x54>
+     5e6:	46c0      	nop			; (mov r8, r8)
+     5e8:	000015e1 	.word	0x000015e1
+     5ec:	41004800 	.word	0x41004800
+     5f0:	2000009c 	.word	0x2000009c
+     5f4:	200001e0 	.word	0x200001e0
+     5f8:	200000b0 	.word	0x200000b0
+     5fc:	00001621 	.word	0x00001621
+
+00000600 <dma_get_config_defaults>:
+ */
+void dma_get_config_defaults(struct dma_resource_config *config)
+{
+	Assert(config);
+	/* Set as priority 0 */
+	config->priority = DMA_PRIORITY_LEVEL_0;
+     600:	2300      	movs	r3, #0
+     602:	7003      	strb	r3, [r0, #0]
+	/* Only software/event trigger */
+	config->peripheral_trigger = 0;
+     604:	7043      	strb	r3, [r0, #1]
+	/* Transaction trigger */
+	config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
+     606:	2203      	movs	r2, #3
+     608:	7082      	strb	r2, [r0, #2]
+
+	/* Event configurations, no event input/output */
+	config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
+     60a:	70c3      	strb	r3, [r0, #3]
+	config->event_config.event_output_enable = false;
+     60c:	7103      	strb	r3, [r0, #4]
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	config->run_in_standby = false;
+#endif
+}
+     60e:	4770      	bx	lr
+
+00000610 <dma_allocate>:
+ * \retval STATUS_OK The DMA resource was allocated successfully
+ * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
+ */
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config)
+{
+     610:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+     612:	46ce      	mov	lr, r9
+     614:	4647      	mov	r7, r8
+     616:	b580      	push	{r7, lr}
+     618:	0005      	movs	r5, r0
+     61a:	000e      	movs	r6, r1
+	cpu_irq_enter_critical();
+     61c:	4b45      	ldr	r3, [pc, #276]	; (734 <dma_allocate+0x124>)
+     61e:	4798      	blx	r3
+
+	Assert(resource);
+
+	system_interrupt_enter_critical_section();
+
+	if (!_dma_inst._dma_init) {
+     620:	4b45      	ldr	r3, [pc, #276]	; (738 <dma_allocate+0x128>)
+     622:	781b      	ldrb	r3, [r3, #0]
+     624:	2b00      	cmp	r3, #0
+     626:	d118      	bne.n	65a <dma_allocate+0x4a>
+	PM->AHBMASK.reg |= ahb_mask;
+     628:	4b44      	ldr	r3, [pc, #272]	; (73c <dma_allocate+0x12c>)
+     62a:	695a      	ldr	r2, [r3, #20]
+     62c:	2120      	movs	r1, #32
+     62e:	430a      	orrs	r2, r1
+     630:	615a      	str	r2, [r3, #20]
+			PM->APBBMASK.reg |= mask;
+     632:	69da      	ldr	r2, [r3, #28]
+     634:	3910      	subs	r1, #16
+     636:	430a      	orrs	r2, r1
+     638:	61da      	str	r2, [r3, #28]
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
+				PM_APBBMASK_DMAC);
+#endif
+
+		/* Perform a software reset before enable DMA controller */
+		DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+     63a:	4b41      	ldr	r3, [pc, #260]	; (740 <dma_allocate+0x130>)
+     63c:	881a      	ldrh	r2, [r3, #0]
+     63e:	390e      	subs	r1, #14
+     640:	438a      	bics	r2, r1
+     642:	801a      	strh	r2, [r3, #0]
+		DMAC->CTRL.reg = DMAC_CTRL_SWRST;
+     644:	2201      	movs	r2, #1
+     646:	801a      	strh	r2, [r3, #0]
+
+		/* Setup descriptor base address and write back section base
+		 * address */
+		DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
+     648:	4a3e      	ldr	r2, [pc, #248]	; (744 <dma_allocate+0x134>)
+     64a:	635a      	str	r2, [r3, #52]	; 0x34
+		DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
+     64c:	4a3e      	ldr	r2, [pc, #248]	; (748 <dma_allocate+0x138>)
+     64e:	639a      	str	r2, [r3, #56]	; 0x38
+
+		/* Enable all priority level at the same time */
+		DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
+     650:	4a3e      	ldr	r2, [pc, #248]	; (74c <dma_allocate+0x13c>)
+     652:	801a      	strh	r2, [r3, #0]
+
+		_dma_inst._dma_init = true;
+     654:	4b38      	ldr	r3, [pc, #224]	; (738 <dma_allocate+0x128>)
+     656:	2201      	movs	r2, #1
+     658:	701a      	strb	r2, [r3, #0]
+     65a:	4b36      	ldr	r3, [pc, #216]	; (734 <dma_allocate+0x124>)
+     65c:	4798      	blx	r3
+	tmp = _dma_inst.allocated_channels;
+     65e:	4b36      	ldr	r3, [pc, #216]	; (738 <dma_allocate+0x128>)
+     660:	685b      	ldr	r3, [r3, #4]
+		if (!(tmp & 0x00000001)) {
+     662:	07da      	lsls	r2, r3, #31
+     664:	d50f      	bpl.n	686 <dma_allocate+0x76>
+		tmp = tmp >> 1;
+     666:	085b      	lsrs	r3, r3, #1
+	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+     668:	2401      	movs	r4, #1
+		if (!(tmp & 0x00000001)) {
+     66a:	2201      	movs	r2, #1
+     66c:	421a      	tst	r2, r3
+     66e:	d00b      	beq.n	688 <dma_allocate+0x78>
+		tmp = tmp >> 1;
+     670:	085b      	lsrs	r3, r3, #1
+	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+     672:	3401      	adds	r4, #1
+     674:	b2e4      	uxtb	r4, r4
+     676:	2c05      	cmp	r4, #5
+     678:	d1f8      	bne.n	66c <dma_allocate+0x5c>
+	cpu_irq_leave_critical();
+     67a:	4b35      	ldr	r3, [pc, #212]	; (750 <dma_allocate+0x140>)
+     67c:	4798      	blx	r3
+     67e:	4b34      	ldr	r3, [pc, #208]	; (750 <dma_allocate+0x140>)
+     680:	4798      	blx	r3
+
+	/* If no channel available, return not found */
+	if (new_channel == DMA_INVALID_CHANNEL) {
+		system_interrupt_leave_critical_section();
+
+		return STATUS_ERR_NOT_FOUND;
+     682:	2014      	movs	r0, #20
+     684:	e051      	b.n	72a <dma_allocate+0x11a>
+	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+     686:	2400      	movs	r4, #0
+			_dma_inst.allocated_channels |= 1 << count;
+     688:	4a2b      	ldr	r2, [pc, #172]	; (738 <dma_allocate+0x128>)
+     68a:	6851      	ldr	r1, [r2, #4]
+     68c:	2301      	movs	r3, #1
+     68e:	40a3      	lsls	r3, r4
+     690:	430b      	orrs	r3, r1
+     692:	6053      	str	r3, [r2, #4]
+			_dma_inst.free_channels--;
+     694:	7a13      	ldrb	r3, [r2, #8]
+     696:	3b01      	subs	r3, #1
+     698:	7213      	strb	r3, [r2, #8]
+     69a:	4b2d      	ldr	r3, [pc, #180]	; (750 <dma_allocate+0x140>)
+     69c:	4798      	blx	r3
+	if (new_channel == DMA_INVALID_CHANNEL) {
+     69e:	2cff      	cmp	r4, #255	; 0xff
+     6a0:	d0ed      	beq.n	67e <dma_allocate+0x6e>
+	}
+
+	/* Set the channel */
+	resource->channel_id = new_channel;
+     6a2:	702c      	strb	r4, [r5, #0]
+
+	/** Perform a reset for the allocated channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+     6a4:	230f      	movs	r3, #15
+     6a6:	4698      	mov	r8, r3
+     6a8:	401c      	ands	r4, r3
+     6aa:	4f25      	ldr	r7, [pc, #148]	; (740 <dma_allocate+0x130>)
+     6ac:	3330      	adds	r3, #48	; 0x30
+     6ae:	4699      	mov	r9, r3
+     6b0:	54fc      	strb	r4, [r7, r3]
+	DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+     6b2:	3301      	adds	r3, #1
+     6b4:	5cfa      	ldrb	r2, [r7, r3]
+     6b6:	2102      	movs	r1, #2
+     6b8:	438a      	bics	r2, r1
+     6ba:	54fa      	strb	r2, [r7, r3]
+	DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+     6bc:	2401      	movs	r4, #1
+     6be:	54fc      	strb	r4, [r7, r3]
+	cpu_irq_enter_critical();
+     6c0:	4b1c      	ldr	r3, [pc, #112]	; (734 <dma_allocate+0x124>)
+     6c2:	4798      	blx	r3
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+     6c4:	782b      	ldrb	r3, [r5, #0]
+     6c6:	4642      	mov	r2, r8
+     6c8:	4013      	ands	r3, r2
+     6ca:	464a      	mov	r2, r9
+     6cc:	54bb      	strb	r3, [r7, r2]
+	DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
+     6ce:	693b      	ldr	r3, [r7, #16]
+     6d0:	782a      	ldrb	r2, [r5, #0]
+     6d2:	4094      	lsls	r4, r2
+     6d4:	43a3      	bics	r3, r4
+     6d6:	613b      	str	r3, [r7, #16]
+	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+     6d8:	7832      	ldrb	r2, [r6, #0]
+     6da:	0152      	lsls	r2, r2, #5
+     6dc:	2360      	movs	r3, #96	; 0x60
+     6de:	4013      	ands	r3, r2
+			DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
+     6e0:	7872      	ldrb	r2, [r6, #1]
+     6e2:	0212      	lsls	r2, r2, #8
+     6e4:	21fc      	movs	r1, #252	; 0xfc
+     6e6:	0189      	lsls	r1, r1, #6
+     6e8:	400a      	ands	r2, r1
+	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+     6ea:	4313      	orrs	r3, r2
+			DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
+     6ec:	78b2      	ldrb	r2, [r6, #2]
+     6ee:	0592      	lsls	r2, r2, #22
+     6f0:	21c0      	movs	r1, #192	; 0xc0
+     6f2:	0409      	lsls	r1, r1, #16
+     6f4:	400a      	ands	r2, r1
+	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+     6f6:	4313      	orrs	r3, r2
+	if(resource_config->event_config.input_action){
+     6f8:	78f1      	ldrb	r1, [r6, #3]
+     6fa:	2900      	cmp	r1, #0
+     6fc:	d004      	beq.n	708 <dma_allocate+0xf8>
+	temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
+     6fe:	2207      	movs	r2, #7
+     700:	400a      	ands	r2, r1
+     702:	2108      	movs	r1, #8
+     704:	430a      	orrs	r2, r1
+     706:	4313      	orrs	r3, r2
+	if (resource_config->event_config.event_output_enable) {
+     708:	7932      	ldrb	r2, [r6, #4]
+     70a:	2a00      	cmp	r2, #0
+     70c:	d001      	beq.n	712 <dma_allocate+0x102>
+		temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
+     70e:	2210      	movs	r2, #16
+     710:	4313      	orrs	r3, r2
+	DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
+     712:	4a0b      	ldr	r2, [pc, #44]	; (740 <dma_allocate+0x130>)
+     714:	6453      	str	r3, [r2, #68]	; 0x44
+	cpu_irq_leave_critical();
+     716:	4c0e      	ldr	r4, [pc, #56]	; (750 <dma_allocate+0x140>)
+     718:	47a0      	blx	r4
+#endif
+
+	/** Configure the DMA control,channel registers and descriptors here */
+	_dma_set_config(resource, config);
+
+	resource->descriptor = NULL;
+     71a:	2300      	movs	r3, #0
+     71c:	61ab      	str	r3, [r5, #24]
+
+	/* Log the DMA resource into the internal DMA resource pool */
+	_dma_active_resource[resource->channel_id] = resource;
+     71e:	782b      	ldrb	r3, [r5, #0]
+     720:	009b      	lsls	r3, r3, #2
+     722:	4a0c      	ldr	r2, [pc, #48]	; (754 <dma_allocate+0x144>)
+     724:	509d      	str	r5, [r3, r2]
+     726:	47a0      	blx	r4
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+     728:	2000      	movs	r0, #0
+}
+     72a:	bc0c      	pop	{r2, r3}
+     72c:	4690      	mov	r8, r2
+     72e:	4699      	mov	r9, r3
+     730:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+     732:	46c0      	nop			; (mov r8, r8)
+     734:	000015e1 	.word	0x000015e1
+     738:	20000000 	.word	0x20000000
+     73c:	40000400 	.word	0x40000400
+     740:	41004800 	.word	0x41004800
+     744:	200001e0 	.word	0x200001e0
+     748:	200000b0 	.word	0x200000b0
+     74c:	00000f02 	.word	0x00000f02
+     750:	00001621 	.word	0x00001621
+     754:	2000009c 	.word	0x2000009c
+
+00000758 <dma_start_transfer_job>:
+ * \retval STATUS_OK The transfer was started successfully
+ * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
+ * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
+ */
+enum status_code dma_start_transfer_job(struct dma_resource *resource)
+{
+     758:	b570      	push	{r4, r5, r6, lr}
+     75a:	0004      	movs	r4, r0
+	cpu_irq_enter_critical();
+     75c:	4b19      	ldr	r3, [pc, #100]	; (7c4 <dma_start_transfer_job+0x6c>)
+     75e:	4798      	blx	r3
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if resource was busy */
+	if (resource->job_status == STATUS_BUSY) {
+     760:	7c63      	ldrb	r3, [r4, #17]
+     762:	2b05      	cmp	r3, #5
+     764:	d008      	beq.n	778 <dma_start_transfer_job+0x20>
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Check if transfer size is valid */
+	if (resource->descriptor->BTCNT.reg == 0) {
+     766:	69a3      	ldr	r3, [r4, #24]
+     768:	885b      	ldrh	r3, [r3, #2]
+     76a:	b29b      	uxth	r3, r3
+     76c:	2b00      	cmp	r3, #0
+     76e:	d107      	bne.n	780 <dma_start_transfer_job+0x28>
+	cpu_irq_leave_critical();
+     770:	4b15      	ldr	r3, [pc, #84]	; (7c8 <dma_start_transfer_job+0x70>)
+     772:	4798      	blx	r3
+		system_interrupt_leave_critical_section();
+		return STATUS_ERR_INVALID_ARG;
+     774:	2017      	movs	r0, #23
+	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+     776:	bd70      	pop	{r4, r5, r6, pc}
+     778:	4b13      	ldr	r3, [pc, #76]	; (7c8 <dma_start_transfer_job+0x70>)
+     77a:	4798      	blx	r3
+		return STATUS_BUSY;
+     77c:	2005      	movs	r0, #5
+     77e:	e7fa      	b.n	776 <dma_start_transfer_job+0x1e>
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+     780:	2640      	movs	r6, #64	; 0x40
+     782:	4b12      	ldr	r3, [pc, #72]	; (7cc <dma_start_transfer_job+0x74>)
+     784:	601e      	str	r6, [r3, #0]
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+     786:	7822      	ldrb	r2, [r4, #0]
+     788:	230f      	movs	r3, #15
+     78a:	4013      	ands	r3, r2
+     78c:	4d10      	ldr	r5, [pc, #64]	; (7d0 <dma_start_transfer_job+0x78>)
+     78e:	223f      	movs	r2, #63	; 0x3f
+     790:	54ab      	strb	r3, [r5, r2]
+	DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
+     792:	7823      	ldrb	r3, [r4, #0]
+     794:	4a0f      	ldr	r2, [pc, #60]	; (7d4 <dma_start_transfer_job+0x7c>)
+     796:	5cd2      	ldrb	r2, [r2, r3]
+     798:	2307      	movs	r3, #7
+     79a:	4013      	ands	r3, r2
+     79c:	224d      	movs	r2, #77	; 0x4d
+     79e:	54ab      	strb	r3, [r5, r2]
+	resource->job_status = STATUS_BUSY;
+     7a0:	2305      	movs	r3, #5
+     7a2:	7463      	strb	r3, [r4, #17]
+	memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
+     7a4:	7820      	ldrb	r0, [r4, #0]
+     7a6:	0100      	lsls	r0, r0, #4
+     7a8:	4b0b      	ldr	r3, [pc, #44]	; (7d8 <dma_start_transfer_job+0x80>)
+     7aa:	18c0      	adds	r0, r0, r3
+     7ac:	69a1      	ldr	r1, [r4, #24]
+     7ae:	3a3d      	subs	r2, #61	; 0x3d
+     7b0:	4b0a      	ldr	r3, [pc, #40]	; (7dc <dma_start_transfer_job+0x84>)
+     7b2:	4798      	blx	r3
+	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+     7b4:	5dab      	ldrb	r3, [r5, r6]
+     7b6:	2202      	movs	r2, #2
+     7b8:	4313      	orrs	r3, r2
+     7ba:	55ab      	strb	r3, [r5, r6]
+	cpu_irq_leave_critical();
+     7bc:	4b02      	ldr	r3, [pc, #8]	; (7c8 <dma_start_transfer_job+0x70>)
+     7be:	4798      	blx	r3
+	return STATUS_OK;
+     7c0:	2000      	movs	r0, #0
+     7c2:	e7d8      	b.n	776 <dma_start_transfer_job+0x1e>
+     7c4:	000015e1 	.word	0x000015e1
+     7c8:	00001621 	.word	0x00001621
+     7cc:	e000e100 	.word	0xe000e100
+     7d0:	41004800 	.word	0x41004800
+     7d4:	20000100 	.word	0x20000100
+     7d8:	200001e0 	.word	0x200001e0
+     7dc:	000026c9 	.word	0x000026c9
+
+000007e0 <dma_descriptor_create>:
+ * \param[in] config Pointer to the descriptor configuration structure
+ *
+ */
+void dma_descriptor_create(DmacDescriptor* descriptor,
+	struct dma_descriptor_config *config)
+{
+     7e0:	b5f0      	push	{r4, r5, r6, r7, lr}
+	/* Set block transfer control */
+	descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
+     7e2:	780a      	ldrb	r2, [r1, #0]
+     7e4:	8803      	ldrh	r3, [r0, #0]
+     7e6:	2601      	movs	r6, #1
+     7e8:	4032      	ands	r2, r6
+     7ea:	2401      	movs	r4, #1
+     7ec:	43a3      	bics	r3, r4
+     7ee:	4313      	orrs	r3, r2
+     7f0:	8003      	strh	r3, [r0, #0]
+	descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
+     7f2:	784b      	ldrb	r3, [r1, #1]
+     7f4:	8804      	ldrh	r4, [r0, #0]
+     7f6:	2703      	movs	r7, #3
+     7f8:	403b      	ands	r3, r7
+     7fa:	005b      	lsls	r3, r3, #1
+     7fc:	2206      	movs	r2, #6
+     7fe:	4394      	bics	r4, r2
+     800:	431c      	orrs	r4, r3
+     802:	8004      	strh	r4, [r0, #0]
+	descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
+     804:	788d      	ldrb	r5, [r1, #2]
+     806:	8804      	ldrh	r4, [r0, #0]
+     808:	403d      	ands	r5, r7
+     80a:	00ed      	lsls	r5, r5, #3
+     80c:	2318      	movs	r3, #24
+     80e:	439c      	bics	r4, r3
+     810:	432c      	orrs	r4, r5
+     812:	8004      	strh	r4, [r0, #0]
+	descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
+     814:	78ca      	ldrb	r2, [r1, #3]
+     816:	8803      	ldrh	r3, [r0, #0]
+     818:	403a      	ands	r2, r7
+     81a:	0212      	lsls	r2, r2, #8
+     81c:	4c16      	ldr	r4, [pc, #88]	; (878 <dma_descriptor_create+0x98>)
+     81e:	4023      	ands	r3, r4
+     820:	4313      	orrs	r3, r2
+     822:	8003      	strh	r3, [r0, #0]
+	descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
+     824:	790b      	ldrb	r3, [r1, #4]
+     826:	8804      	ldrh	r4, [r0, #0]
+     828:	4033      	ands	r3, r6
+     82a:	029b      	lsls	r3, r3, #10
+     82c:	4a13      	ldr	r2, [pc, #76]	; (87c <dma_descriptor_create+0x9c>)
+     82e:	4014      	ands	r4, r2
+     830:	431c      	orrs	r4, r3
+     832:	8004      	strh	r4, [r0, #0]
+	descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
+     834:	794d      	ldrb	r5, [r1, #5]
+     836:	8804      	ldrh	r4, [r0, #0]
+     838:	4035      	ands	r5, r6
+     83a:	02ed      	lsls	r5, r5, #11
+     83c:	4b10      	ldr	r3, [pc, #64]	; (880 <dma_descriptor_create+0xa0>)
+     83e:	401c      	ands	r4, r3
+     840:	432c      	orrs	r4, r5
+     842:	8004      	strh	r4, [r0, #0]
+	descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
+     844:	798a      	ldrb	r2, [r1, #6]
+     846:	8803      	ldrh	r3, [r0, #0]
+     848:	4032      	ands	r2, r6
+     84a:	0312      	lsls	r2, r2, #12
+     84c:	4c0d      	ldr	r4, [pc, #52]	; (884 <dma_descriptor_create+0xa4>)
+     84e:	4023      	ands	r3, r4
+     850:	4313      	orrs	r3, r2
+     852:	8003      	strh	r3, [r0, #0]
+	descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
+     854:	79cb      	ldrb	r3, [r1, #7]
+     856:	2207      	movs	r2, #7
+     858:	401a      	ands	r2, r3
+     85a:	8803      	ldrh	r3, [r0, #0]
+     85c:	0352      	lsls	r2, r2, #13
+     85e:	04db      	lsls	r3, r3, #19
+     860:	0cdb      	lsrs	r3, r3, #19
+     862:	4313      	orrs	r3, r2
+     864:	8003      	strh	r3, [r0, #0]
+
+	/* Set transfer size, source address and destination address */
+	descriptor->BTCNT.reg = config->block_transfer_count;
+     866:	890b      	ldrh	r3, [r1, #8]
+     868:	8043      	strh	r3, [r0, #2]
+	descriptor->SRCADDR.reg = config->source_address;
+     86a:	68cb      	ldr	r3, [r1, #12]
+     86c:	6043      	str	r3, [r0, #4]
+	descriptor->DSTADDR.reg = config->destination_address;
+     86e:	690b      	ldr	r3, [r1, #16]
+     870:	6083      	str	r3, [r0, #8]
+
+	/* Set next transfer descriptor address */
+	descriptor->DESCADDR.reg = config->next_descriptor_address;
+     872:	694b      	ldr	r3, [r1, #20]
+     874:	60c3      	str	r3, [r0, #12]
+}
+     876:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     878:	fffffcff 	.word	0xfffffcff
+     87c:	fffffbff 	.word	0xfffffbff
+     880:	fffff7ff 	.word	0xfffff7ff
+     884:	ffffefff 	.word	0xffffefff
+
+00000888 <dma_add_descriptor>:
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor)
+{
+	DmacDescriptor* desc = resource->descriptor;
+
+	if (resource->job_status == STATUS_BUSY) {
+     888:	7c42      	ldrb	r2, [r0, #17]
+		return STATUS_BUSY;
+     88a:	2305      	movs	r3, #5
+	if (resource->job_status == STATUS_BUSY) {
+     88c:	2a05      	cmp	r2, #5
+     88e:	d00b      	beq.n	8a8 <dma_add_descriptor+0x20>
+	DmacDescriptor* desc = resource->descriptor;
+     890:	6983      	ldr	r3, [r0, #24]
+	}
+
+	/* Look up for an empty space for the descriptor */
+	if (desc == NULL) {
+     892:	2b00      	cmp	r3, #0
+     894:	d00a      	beq.n	8ac <dma_add_descriptor+0x24>
+		resource->descriptor = descriptor;
+	} else {
+		/* Looking for end of descriptor link */
+		while(desc->DESCADDR.reg != 0) {
+     896:	68da      	ldr	r2, [r3, #12]
+     898:	2a00      	cmp	r2, #0
+     89a:	d003      	beq.n	8a4 <dma_add_descriptor+0x1c>
+			desc = (DmacDescriptor*)(desc->DESCADDR.reg);
+     89c:	68db      	ldr	r3, [r3, #12]
+		while(desc->DESCADDR.reg != 0) {
+     89e:	68da      	ldr	r2, [r3, #12]
+     8a0:	2a00      	cmp	r2, #0
+     8a2:	d1fb      	bne.n	89c <dma_add_descriptor+0x14>
+		}
+
+		/* Set to the end of descriptor list */
+		desc->DESCADDR.reg = (uint32_t)descriptor;
+     8a4:	60d9      	str	r1, [r3, #12]
+	}
+
+	return STATUS_OK;
+     8a6:	2300      	movs	r3, #0
+}
+     8a8:	0018      	movs	r0, r3
+     8aa:	4770      	bx	lr
+		resource->descriptor = descriptor;
+     8ac:	6181      	str	r1, [r0, #24]
+	return STATUS_OK;
+     8ae:	2300      	movs	r3, #0
+     8b0:	e7fa      	b.n	8a8 <dma_add_descriptor+0x20>
+
+000008b2 <long_division>:
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+     8b2:	b5f0      	push	{r4, r5, r6, r7, lr}
+     8b4:	46de      	mov	lr, fp
+     8b6:	4657      	mov	r7, sl
+     8b8:	464e      	mov	r6, r9
+     8ba:	4645      	mov	r5, r8
+     8bc:	b5e0      	push	{r5, r6, r7, lr}
+     8be:	b087      	sub	sp, #28
+     8c0:	4680      	mov	r8, r0
+     8c2:	9104      	str	r1, [sp, #16]
+     8c4:	0016      	movs	r6, r2
+     8c6:	001f      	movs	r7, r3
+	int32_t i;
+	uint64_t q = 0, r = 0, bit_shift;
+     8c8:	2200      	movs	r2, #0
+     8ca:	2300      	movs	r3, #0
+     8cc:	2100      	movs	r1, #0
+     8ce:	468b      	mov	fp, r1
+	for (i = 63; i >= 0; i--) {
+     8d0:	243f      	movs	r4, #63	; 0x3f
+		bit_shift = (uint64_t)1 << i;
+     8d2:	2001      	movs	r0, #1
+     8d4:	0021      	movs	r1, r4
+     8d6:	9600      	str	r6, [sp, #0]
+     8d8:	9701      	str	r7, [sp, #4]
+     8da:	465c      	mov	r4, fp
+     8dc:	9403      	str	r4, [sp, #12]
+     8de:	4644      	mov	r4, r8
+     8e0:	9405      	str	r4, [sp, #20]
+     8e2:	e013      	b.n	90c <long_division+0x5a>
+     8e4:	2420      	movs	r4, #32
+     8e6:	1a64      	subs	r4, r4, r1
+     8e8:	0005      	movs	r5, r0
+     8ea:	40e5      	lsrs	r5, r4
+     8ec:	46a8      	mov	r8, r5
+     8ee:	e014      	b.n	91a <long_division+0x68>
+		if (n & bit_shift) {
+			r |= 0x01;
+		}
+
+		if (r >= d) {
+			r = r - d;
+     8f0:	9c00      	ldr	r4, [sp, #0]
+     8f2:	9d01      	ldr	r5, [sp, #4]
+     8f4:	1b12      	subs	r2, r2, r4
+     8f6:	41ab      	sbcs	r3, r5
+			q |= bit_shift;
+     8f8:	465c      	mov	r4, fp
+     8fa:	464d      	mov	r5, r9
+     8fc:	432c      	orrs	r4, r5
+     8fe:	46a3      	mov	fp, r4
+     900:	9c03      	ldr	r4, [sp, #12]
+     902:	4645      	mov	r5, r8
+     904:	432c      	orrs	r4, r5
+     906:	9403      	str	r4, [sp, #12]
+	for (i = 63; i >= 0; i--) {
+     908:	3901      	subs	r1, #1
+     90a:	d325      	bcc.n	958 <long_division+0xa6>
+		bit_shift = (uint64_t)1 << i;
+     90c:	2420      	movs	r4, #32
+     90e:	4264      	negs	r4, r4
+     910:	190c      	adds	r4, r1, r4
+     912:	d4e7      	bmi.n	8e4 <long_division+0x32>
+     914:	0005      	movs	r5, r0
+     916:	40a5      	lsls	r5, r4
+     918:	46a8      	mov	r8, r5
+     91a:	0004      	movs	r4, r0
+     91c:	408c      	lsls	r4, r1
+     91e:	46a1      	mov	r9, r4
+		r = r << 1;
+     920:	1892      	adds	r2, r2, r2
+     922:	415b      	adcs	r3, r3
+     924:	0014      	movs	r4, r2
+     926:	001d      	movs	r5, r3
+		if (n & bit_shift) {
+     928:	9e05      	ldr	r6, [sp, #20]
+     92a:	464f      	mov	r7, r9
+     92c:	403e      	ands	r6, r7
+     92e:	46b4      	mov	ip, r6
+     930:	9e04      	ldr	r6, [sp, #16]
+     932:	4647      	mov	r7, r8
+     934:	403e      	ands	r6, r7
+     936:	46b2      	mov	sl, r6
+     938:	4666      	mov	r6, ip
+     93a:	4657      	mov	r7, sl
+     93c:	433e      	orrs	r6, r7
+     93e:	d003      	beq.n	948 <long_division+0x96>
+			r |= 0x01;
+     940:	0006      	movs	r6, r0
+     942:	4326      	orrs	r6, r4
+     944:	0032      	movs	r2, r6
+     946:	002b      	movs	r3, r5
+		if (r >= d) {
+     948:	9c00      	ldr	r4, [sp, #0]
+     94a:	9d01      	ldr	r5, [sp, #4]
+     94c:	429d      	cmp	r5, r3
+     94e:	d8db      	bhi.n	908 <long_division+0x56>
+     950:	d1ce      	bne.n	8f0 <long_division+0x3e>
+     952:	4294      	cmp	r4, r2
+     954:	d8d8      	bhi.n	908 <long_division+0x56>
+     956:	e7cb      	b.n	8f0 <long_division+0x3e>
+     958:	9b03      	ldr	r3, [sp, #12]
+		}
+	}
+
+	return q;
+}
+     95a:	4658      	mov	r0, fp
+     95c:	0019      	movs	r1, r3
+     95e:	b007      	add	sp, #28
+     960:	bc3c      	pop	{r2, r3, r4, r5}
+     962:	4690      	mov	r8, r2
+     964:	4699      	mov	r9, r3
+     966:	46a2      	mov	sl, r4
+     968:	46ab      	mov	fp, r5
+     96a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+
+0000096c <_sercom_get_sync_baud_val>:
+ */
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudvalue)
+{
+     96c:	b510      	push	{r4, lr}
+	uint16_t baud_calculated = 0;
+	uint32_t clock_value = external_clock;
+
+
+	/* Check if baudrate is outside of valid range */
+	if (baudrate > (external_clock / 2)) {
+     96e:	0849      	lsrs	r1, r1, #1
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+     970:	2340      	movs	r3, #64	; 0x40
+     972:	2400      	movs	r4, #0
+	if (baudrate > (external_clock / 2)) {
+     974:	4281      	cmp	r1, r0
+     976:	d202      	bcs.n	97e <_sercom_get_sync_baud_val+0x12>
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	} else {
+		*baudvalue = baud_calculated;
+		return STATUS_OK;
+	}
+}
+     978:	0018      	movs	r0, r3
+     97a:	bd10      	pop	{r4, pc}
+		baud_calculated++;
+     97c:	001c      	movs	r4, r3
+		clock_value = clock_value - baudrate;
+     97e:	1a09      	subs	r1, r1, r0
+		baud_calculated++;
+     980:	1c63      	adds	r3, r4, #1
+     982:	b29b      	uxth	r3, r3
+	while (clock_value >= baudrate) {
+     984:	4288      	cmp	r0, r1
+     986:	d9f9      	bls.n	97c <_sercom_get_sync_baud_val+0x10>
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+     988:	2340      	movs	r3, #64	; 0x40
+	if (baud_calculated > 0xFF) {
+     98a:	2cff      	cmp	r4, #255	; 0xff
+     98c:	d8f4      	bhi.n	978 <_sercom_get_sync_baud_val+0xc>
+		*baudvalue = baud_calculated;
+     98e:	8014      	strh	r4, [r2, #0]
+		return STATUS_OK;
+     990:	2300      	movs	r3, #0
+     992:	e7f1      	b.n	978 <_sercom_get_sync_baud_val+0xc>
+
+00000994 <_sercom_get_async_baud_val>:
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num)
+{
+     994:	b5f0      	push	{r4, r5, r6, r7, lr}
+     996:	b083      	sub	sp, #12
+     998:	000f      	movs	r7, r1
+     99a:	0016      	movs	r6, r2
+     99c:	aa08      	add	r2, sp, #32
+     99e:	7811      	ldrb	r1, [r2, #0]
+	uint8_t baud_fp;
+	uint32_t baud_int = 0;
+	uint64_t temp1;
+
+	/* Check if the baudrate is outside of valid range */
+	if ((baudrate * sample_num) > peripheral_clock) {
+     9a0:	0004      	movs	r4, r0
+     9a2:	434c      	muls	r4, r1
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+     9a4:	2240      	movs	r2, #64	; 0x40
+	if ((baudrate * sample_num) > peripheral_clock) {
+     9a6:	42bc      	cmp	r4, r7
+     9a8:	d902      	bls.n	9b0 <_sercom_get_async_baud_val+0x1c>
+		baud_calculated = baud_int | (baud_fp << 13);
+	}
+
+	*baudval = baud_calculated;
+	return STATUS_OK;
+}
+     9aa:	0010      	movs	r0, r2
+     9ac:	b003      	add	sp, #12
+     9ae:	bdf0      	pop	{r4, r5, r6, r7, pc}
+	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+     9b0:	2b00      	cmp	r3, #0
+     9b2:	d114      	bne.n	9de <_sercom_get_async_baud_val+0x4a>
+		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+     9b4:	0002      	movs	r2, r0
+     9b6:	0008      	movs	r0, r1
+     9b8:	2100      	movs	r1, #0
+     9ba:	4c19      	ldr	r4, [pc, #100]	; (a20 <_sercom_get_async_baud_val+0x8c>)
+     9bc:	47a0      	blx	r4
+     9be:	0001      	movs	r1, r0
+		ratio = long_division(temp1, peripheral_clock);
+     9c0:	003a      	movs	r2, r7
+     9c2:	2300      	movs	r3, #0
+     9c4:	2000      	movs	r0, #0
+     9c6:	4c17      	ldr	r4, [pc, #92]	; (a24 <_sercom_get_async_baud_val+0x90>)
+     9c8:	47a0      	blx	r4
+		scale = ((uint64_t)1 << SHIFT) - ratio;
+     9ca:	2200      	movs	r2, #0
+     9cc:	2301      	movs	r3, #1
+     9ce:	1a12      	subs	r2, r2, r0
+     9d0:	418b      	sbcs	r3, r1
+		baud_calculated = (65536 * scale) >> SHIFT;
+     9d2:	0c12      	lsrs	r2, r2, #16
+     9d4:	041b      	lsls	r3, r3, #16
+     9d6:	431a      	orrs	r2, r3
+	*baudval = baud_calculated;
+     9d8:	8032      	strh	r2, [r6, #0]
+	return STATUS_OK;
+     9da:	2200      	movs	r2, #0
+     9dc:	e7e5      	b.n	9aa <_sercom_get_async_baud_val+0x16>
+	uint64_t baud_calculated = 0;
+     9de:	2200      	movs	r2, #0
+	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+     9e0:	2b01      	cmp	r3, #1
+     9e2:	d1f9      	bne.n	9d8 <_sercom_get_async_baud_val+0x44>
+		temp1 = ((uint64_t)baudrate * sample_num);
+     9e4:	000a      	movs	r2, r1
+     9e6:	2300      	movs	r3, #0
+     9e8:	2100      	movs	r1, #0
+     9ea:	4c0d      	ldr	r4, [pc, #52]	; (a20 <_sercom_get_async_baud_val+0x8c>)
+     9ec:	47a0      	blx	r4
+     9ee:	0002      	movs	r2, r0
+     9f0:	000b      	movs	r3, r1
+     9f2:	9200      	str	r2, [sp, #0]
+     9f4:	9301      	str	r3, [sp, #4]
+		baud_int = long_division( peripheral_clock, temp1);
+     9f6:	0038      	movs	r0, r7
+     9f8:	2100      	movs	r1, #0
+     9fa:	4c0a      	ldr	r4, [pc, #40]	; (a24 <_sercom_get_async_baud_val+0x90>)
+     9fc:	47a0      	blx	r4
+     9fe:	0005      	movs	r5, r0
+		if(baud_int > BAUD_INT_MAX) {
+     a00:	2380      	movs	r3, #128	; 0x80
+     a02:	019b      	lsls	r3, r3, #6
+				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+     a04:	2240      	movs	r2, #64	; 0x40
+		if(baud_int > BAUD_INT_MAX) {
+     a06:	4298      	cmp	r0, r3
+     a08:	d8cf      	bhi.n	9aa <_sercom_get_async_baud_val+0x16>
+		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
+     a0a:	0f79      	lsrs	r1, r7, #29
+     a0c:	00f8      	lsls	r0, r7, #3
+     a0e:	9a00      	ldr	r2, [sp, #0]
+     a10:	9b01      	ldr	r3, [sp, #4]
+     a12:	47a0      	blx	r4
+		baud_fp = temp1 - 8 * baud_int;
+     a14:	00ea      	lsls	r2, r5, #3
+     a16:	1a82      	subs	r2, r0, r2
+		baud_calculated = baud_int | (baud_fp << 13);
+     a18:	b2d2      	uxtb	r2, r2
+     a1a:	0352      	lsls	r2, r2, #13
+     a1c:	432a      	orrs	r2, r5
+     a1e:	e7db      	b.n	9d8 <_sercom_get_async_baud_val+0x44>
+     a20:	00001f0d 	.word	0x00001f0d
+     a24:	000008b3 	.word	0x000008b3
+
+00000a28 <sercom_set_gclk_generator>:
+ *                                         forced.
+ */
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change)
+{
+     a28:	b510      	push	{r4, lr}
+     a2a:	b082      	sub	sp, #8
+     a2c:	0004      	movs	r4, r0
+	/* Check if valid option */
+	if (!_sercom_config.generator_is_set || force_change) {
+     a2e:	4b0e      	ldr	r3, [pc, #56]	; (a68 <sercom_set_gclk_generator+0x40>)
+     a30:	781b      	ldrb	r3, [r3, #0]
+     a32:	2b00      	cmp	r3, #0
+     a34:	d007      	beq.n	a46 <sercom_set_gclk_generator+0x1e>
+     a36:	2900      	cmp	r1, #0
+     a38:	d105      	bne.n	a46 <sercom_set_gclk_generator+0x1e>
+		/* Save config */
+		_sercom_config.generator_source = generator_source;
+		_sercom_config.generator_is_set = true;
+
+		return STATUS_OK;
+	} else if (generator_source == _sercom_config.generator_source) {
+     a3a:	4b0b      	ldr	r3, [pc, #44]	; (a68 <sercom_set_gclk_generator+0x40>)
+     a3c:	785b      	ldrb	r3, [r3, #1]
+     a3e:	4283      	cmp	r3, r0
+     a40:	d010      	beq.n	a64 <sercom_set_gclk_generator+0x3c>
+		/* Return status OK if same config */
+		return STATUS_OK;
+	}
+
+	/* Return invalid config to already initialized GCLK */
+	return STATUS_ERR_ALREADY_INITIALIZED;
+     a42:	201d      	movs	r0, #29
+     a44:	e00c      	b.n	a60 <sercom_set_gclk_generator+0x38>
+		gclk_chan_conf.source_generator = generator_source;
+     a46:	a901      	add	r1, sp, #4
+     a48:	700c      	strb	r4, [r1, #0]
+		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+     a4a:	2013      	movs	r0, #19
+     a4c:	4b07      	ldr	r3, [pc, #28]	; (a6c <sercom_set_gclk_generator+0x44>)
+     a4e:	4798      	blx	r3
+		system_gclk_chan_enable(SERCOM_GCLK_ID);
+     a50:	2013      	movs	r0, #19
+     a52:	4b07      	ldr	r3, [pc, #28]	; (a70 <sercom_set_gclk_generator+0x48>)
+     a54:	4798      	blx	r3
+		_sercom_config.generator_source = generator_source;
+     a56:	4b04      	ldr	r3, [pc, #16]	; (a68 <sercom_set_gclk_generator+0x40>)
+     a58:	705c      	strb	r4, [r3, #1]
+		_sercom_config.generator_is_set = true;
+     a5a:	2201      	movs	r2, #1
+     a5c:	701a      	strb	r2, [r3, #0]
+		return STATUS_OK;
+     a5e:	2000      	movs	r0, #0
+}
+     a60:	b002      	add	sp, #8
+     a62:	bd10      	pop	{r4, pc}
+		return STATUS_OK;
+     a64:	2000      	movs	r0, #0
+     a66:	e7fb      	b.n	a60 <sercom_set_gclk_generator+0x38>
+     a68:	20000108 	.word	0x20000108
+     a6c:	00001af5 	.word	0x00001af5
+     a70:	00001a69 	.word	0x00001a69
+
+00000a74 <_sercom_get_default_pad>:
+ */
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad)
+{
+	switch ((uintptr_t)sercom_module) {
+     a74:	4b40      	ldr	r3, [pc, #256]	; (b78 <_sercom_get_default_pad+0x104>)
+     a76:	4298      	cmp	r0, r3
+     a78:	d031      	beq.n	ade <_sercom_get_default_pad+0x6a>
+     a7a:	d90a      	bls.n	a92 <_sercom_get_default_pad+0x1e>
+     a7c:	4b3f      	ldr	r3, [pc, #252]	; (b7c <_sercom_get_default_pad+0x108>)
+     a7e:	4298      	cmp	r0, r3
+     a80:	d04d      	beq.n	b1e <_sercom_get_default_pad+0xaa>
+     a82:	4b3f      	ldr	r3, [pc, #252]	; (b80 <_sercom_get_default_pad+0x10c>)
+     a84:	4298      	cmp	r0, r3
+     a86:	d05a      	beq.n	b3e <_sercom_get_default_pad+0xca>
+     a88:	4b3e      	ldr	r3, [pc, #248]	; (b84 <_sercom_get_default_pad+0x110>)
+     a8a:	4298      	cmp	r0, r3
+     a8c:	d037      	beq.n	afe <_sercom_get_default_pad+0x8a>
+		/* Auto-generate a lookup table for the default SERCOM pad defaults */
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+	}
+
+	Assert(false);
+	return 0;
+     a8e:	2000      	movs	r0, #0
+}
+     a90:	4770      	bx	lr
+	switch ((uintptr_t)sercom_module) {
+     a92:	4b3d      	ldr	r3, [pc, #244]	; (b88 <_sercom_get_default_pad+0x114>)
+     a94:	4298      	cmp	r0, r3
+     a96:	d00c      	beq.n	ab2 <_sercom_get_default_pad+0x3e>
+     a98:	4b3c      	ldr	r3, [pc, #240]	; (b8c <_sercom_get_default_pad+0x118>)
+     a9a:	4298      	cmp	r0, r3
+     a9c:	d1f7      	bne.n	a8e <_sercom_get_default_pad+0x1a>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     a9e:	2901      	cmp	r1, #1
+     aa0:	d017      	beq.n	ad2 <_sercom_get_default_pad+0x5e>
+     aa2:	2900      	cmp	r1, #0
+     aa4:	d05d      	beq.n	b62 <_sercom_get_default_pad+0xee>
+     aa6:	2902      	cmp	r1, #2
+     aa8:	d015      	beq.n	ad6 <_sercom_get_default_pad+0x62>
+     aaa:	2903      	cmp	r1, #3
+     aac:	d015      	beq.n	ada <_sercom_get_default_pad+0x66>
+	return 0;
+     aae:	2000      	movs	r0, #0
+     ab0:	e7ee      	b.n	a90 <_sercom_get_default_pad+0x1c>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     ab2:	2901      	cmp	r1, #1
+     ab4:	d007      	beq.n	ac6 <_sercom_get_default_pad+0x52>
+     ab6:	2900      	cmp	r1, #0
+     ab8:	d051      	beq.n	b5e <_sercom_get_default_pad+0xea>
+     aba:	2902      	cmp	r1, #2
+     abc:	d005      	beq.n	aca <_sercom_get_default_pad+0x56>
+     abe:	2903      	cmp	r1, #3
+     ac0:	d005      	beq.n	ace <_sercom_get_default_pad+0x5a>
+	return 0;
+     ac2:	2000      	movs	r0, #0
+     ac4:	e7e4      	b.n	a90 <_sercom_get_default_pad+0x1c>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     ac6:	4832      	ldr	r0, [pc, #200]	; (b90 <_sercom_get_default_pad+0x11c>)
+     ac8:	e7e2      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     aca:	4832      	ldr	r0, [pc, #200]	; (b94 <_sercom_get_default_pad+0x120>)
+     acc:	e7e0      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     ace:	4832      	ldr	r0, [pc, #200]	; (b98 <_sercom_get_default_pad+0x124>)
+     ad0:	e7de      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     ad2:	4832      	ldr	r0, [pc, #200]	; (b9c <_sercom_get_default_pad+0x128>)
+     ad4:	e7dc      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     ad6:	4832      	ldr	r0, [pc, #200]	; (ba0 <_sercom_get_default_pad+0x12c>)
+     ad8:	e7da      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     ada:	4832      	ldr	r0, [pc, #200]	; (ba4 <_sercom_get_default_pad+0x130>)
+     adc:	e7d8      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     ade:	2901      	cmp	r1, #1
+     ae0:	d007      	beq.n	af2 <_sercom_get_default_pad+0x7e>
+     ae2:	2900      	cmp	r1, #0
+     ae4:	d03f      	beq.n	b66 <_sercom_get_default_pad+0xf2>
+     ae6:	2902      	cmp	r1, #2
+     ae8:	d005      	beq.n	af6 <_sercom_get_default_pad+0x82>
+     aea:	2903      	cmp	r1, #3
+     aec:	d005      	beq.n	afa <_sercom_get_default_pad+0x86>
+	return 0;
+     aee:	2000      	movs	r0, #0
+     af0:	e7ce      	b.n	a90 <_sercom_get_default_pad+0x1c>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     af2:	482d      	ldr	r0, [pc, #180]	; (ba8 <_sercom_get_default_pad+0x134>)
+     af4:	e7cc      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     af6:	482d      	ldr	r0, [pc, #180]	; (bac <_sercom_get_default_pad+0x138>)
+     af8:	e7ca      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     afa:	482d      	ldr	r0, [pc, #180]	; (bb0 <_sercom_get_default_pad+0x13c>)
+     afc:	e7c8      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     afe:	2901      	cmp	r1, #1
+     b00:	d007      	beq.n	b12 <_sercom_get_default_pad+0x9e>
+     b02:	2900      	cmp	r1, #0
+     b04:	d031      	beq.n	b6a <_sercom_get_default_pad+0xf6>
+     b06:	2902      	cmp	r1, #2
+     b08:	d005      	beq.n	b16 <_sercom_get_default_pad+0xa2>
+     b0a:	2903      	cmp	r1, #3
+     b0c:	d005      	beq.n	b1a <_sercom_get_default_pad+0xa6>
+	return 0;
+     b0e:	2000      	movs	r0, #0
+     b10:	e7be      	b.n	a90 <_sercom_get_default_pad+0x1c>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     b12:	4828      	ldr	r0, [pc, #160]	; (bb4 <_sercom_get_default_pad+0x140>)
+     b14:	e7bc      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b16:	4828      	ldr	r0, [pc, #160]	; (bb8 <_sercom_get_default_pad+0x144>)
+     b18:	e7ba      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b1a:	4828      	ldr	r0, [pc, #160]	; (bbc <_sercom_get_default_pad+0x148>)
+     b1c:	e7b8      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b1e:	2901      	cmp	r1, #1
+     b20:	d007      	beq.n	b32 <_sercom_get_default_pad+0xbe>
+     b22:	2900      	cmp	r1, #0
+     b24:	d023      	beq.n	b6e <_sercom_get_default_pad+0xfa>
+     b26:	2902      	cmp	r1, #2
+     b28:	d005      	beq.n	b36 <_sercom_get_default_pad+0xc2>
+     b2a:	2903      	cmp	r1, #3
+     b2c:	d005      	beq.n	b3a <_sercom_get_default_pad+0xc6>
+	return 0;
+     b2e:	2000      	movs	r0, #0
+     b30:	e7ae      	b.n	a90 <_sercom_get_default_pad+0x1c>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     b32:	4823      	ldr	r0, [pc, #140]	; (bc0 <_sercom_get_default_pad+0x14c>)
+     b34:	e7ac      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b36:	4823      	ldr	r0, [pc, #140]	; (bc4 <_sercom_get_default_pad+0x150>)
+     b38:	e7aa      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b3a:	4823      	ldr	r0, [pc, #140]	; (bc8 <_sercom_get_default_pad+0x154>)
+     b3c:	e7a8      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b3e:	2901      	cmp	r1, #1
+     b40:	d007      	beq.n	b52 <_sercom_get_default_pad+0xde>
+     b42:	2900      	cmp	r1, #0
+     b44:	d015      	beq.n	b72 <_sercom_get_default_pad+0xfe>
+     b46:	2902      	cmp	r1, #2
+     b48:	d005      	beq.n	b56 <_sercom_get_default_pad+0xe2>
+     b4a:	2903      	cmp	r1, #3
+     b4c:	d005      	beq.n	b5a <_sercom_get_default_pad+0xe6>
+	return 0;
+     b4e:	2000      	movs	r0, #0
+     b50:	e79e      	b.n	a90 <_sercom_get_default_pad+0x1c>
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+     b52:	481e      	ldr	r0, [pc, #120]	; (bcc <_sercom_get_default_pad+0x158>)
+     b54:	e79c      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b56:	481e      	ldr	r0, [pc, #120]	; (bd0 <_sercom_get_default_pad+0x15c>)
+     b58:	e79a      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b5a:	481e      	ldr	r0, [pc, #120]	; (bd4 <_sercom_get_default_pad+0x160>)
+     b5c:	e798      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b5e:	481e      	ldr	r0, [pc, #120]	; (bd8 <_sercom_get_default_pad+0x164>)
+     b60:	e796      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b62:	2003      	movs	r0, #3
+     b64:	e794      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b66:	481d      	ldr	r0, [pc, #116]	; (bdc <_sercom_get_default_pad+0x168>)
+     b68:	e792      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b6a:	481d      	ldr	r0, [pc, #116]	; (be0 <_sercom_get_default_pad+0x16c>)
+     b6c:	e790      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b6e:	481d      	ldr	r0, [pc, #116]	; (be4 <_sercom_get_default_pad+0x170>)
+     b70:	e78e      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b72:	481d      	ldr	r0, [pc, #116]	; (be8 <_sercom_get_default_pad+0x174>)
+     b74:	e78c      	b.n	a90 <_sercom_get_default_pad+0x1c>
+     b76:	46c0      	nop			; (mov r8, r8)
+     b78:	42001000 	.word	0x42001000
+     b7c:	42001800 	.word	0x42001800
+     b80:	42001c00 	.word	0x42001c00
+     b84:	42001400 	.word	0x42001400
+     b88:	42000800 	.word	0x42000800
+     b8c:	42000c00 	.word	0x42000c00
+     b90:	00050003 	.word	0x00050003
+     b94:	00060003 	.word	0x00060003
+     b98:	00070003 	.word	0x00070003
+     b9c:	00010003 	.word	0x00010003
+     ba0:	001e0003 	.word	0x001e0003
+     ba4:	001f0003 	.word	0x001f0003
+     ba8:	00090003 	.word	0x00090003
+     bac:	000a0003 	.word	0x000a0003
+     bb0:	000b0003 	.word	0x000b0003
+     bb4:	00110003 	.word	0x00110003
+     bb8:	00120003 	.word	0x00120003
+     bbc:	00130003 	.word	0x00130003
+     bc0:	000d0003 	.word	0x000d0003
+     bc4:	000e0003 	.word	0x000e0003
+     bc8:	000f0003 	.word	0x000f0003
+     bcc:	00170003 	.word	0x00170003
+     bd0:	00180003 	.word	0x00180003
+     bd4:	00190003 	.word	0x00190003
+     bd8:	00040003 	.word	0x00040003
+     bdc:	00080003 	.word	0x00080003
+     be0:	00100003 	.word	0x00100003
+     be4:	000c0003 	.word	0x000c0003
+     be8:	00160003 	.word	0x00160003
+
+00000bec <_sercom_get_sercom_inst_index>:
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance)
+{
+     bec:	b530      	push	{r4, r5, lr}
+     bee:	b087      	sub	sp, #28
+	/* Save all available SERCOM instances for compare */
+	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+     bf0:	4b0b      	ldr	r3, [pc, #44]	; (c20 <_sercom_get_sercom_inst_index+0x34>)
+     bf2:	466a      	mov	r2, sp
+     bf4:	cb32      	ldmia	r3!, {r1, r4, r5}
+     bf6:	c232      	stmia	r2!, {r1, r4, r5}
+     bf8:	cb32      	ldmia	r3!, {r1, r4, r5}
+     bfa:	c232      	stmia	r2!, {r1, r4, r5}
+
+	/* Find index for sercom instance */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+     bfc:	9b00      	ldr	r3, [sp, #0]
+     bfe:	4283      	cmp	r3, r0
+     c00:	d00b      	beq.n	c1a <_sercom_get_sercom_inst_index+0x2e>
+     c02:	2301      	movs	r3, #1
+     c04:	009a      	lsls	r2, r3, #2
+     c06:	4669      	mov	r1, sp
+     c08:	5852      	ldr	r2, [r2, r1]
+     c0a:	4282      	cmp	r2, r0
+     c0c:	d006      	beq.n	c1c <_sercom_get_sercom_inst_index+0x30>
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+     c0e:	3301      	adds	r3, #1
+     c10:	2b06      	cmp	r3, #6
+     c12:	d1f7      	bne.n	c04 <_sercom_get_sercom_inst_index+0x18>
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+     c14:	2000      	movs	r0, #0
+}
+     c16:	b007      	add	sp, #28
+     c18:	bd30      	pop	{r4, r5, pc}
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+     c1a:	2300      	movs	r3, #0
+			return i;
+     c1c:	b2d8      	uxtb	r0, r3
+     c1e:	e7fa      	b.n	c16 <_sercom_get_sercom_inst_index+0x2a>
+     c20:	000037f4 	.word	0x000037f4
+
+00000c24 <_read>:
+int __attribute__((weak))
+_read (int file, char * ptr, int len); // Remove GCC compiler warning
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len)
+{
+     c24:	b5f0      	push	{r4, r5, r6, r7, lr}
+     c26:	46c6      	mov	lr, r8
+     c28:	b500      	push	{lr}
+     c2a:	000c      	movs	r4, r1
+     c2c:	4690      	mov	r8, r2
+	int nChars = 0;
+
+	if (file != 0) {
+     c2e:	2800      	cmp	r0, #0
+     c30:	d10f      	bne.n	c52 <_read+0x2e>
+		return -1;
+	}
+
+	for (; len > 0; --len) {
+     c32:	2a00      	cmp	r2, #0
+     c34:	dd11      	ble.n	c5a <_read+0x36>
+     c36:	188f      	adds	r7, r1, r2
+		ptr_get(stdio_base, ptr);
+     c38:	4e09      	ldr	r6, [pc, #36]	; (c60 <_read+0x3c>)
+     c3a:	4d0a      	ldr	r5, [pc, #40]	; (c64 <_read+0x40>)
+     c3c:	6830      	ldr	r0, [r6, #0]
+     c3e:	0021      	movs	r1, r4
+     c40:	682b      	ldr	r3, [r5, #0]
+     c42:	4798      	blx	r3
+		ptr++;
+     c44:	3401      	adds	r4, #1
+	for (; len > 0; --len) {
+     c46:	42bc      	cmp	r4, r7
+     c48:	d1f8      	bne.n	c3c <_read+0x18>
+		nChars++;
+	}
+	return nChars;
+}
+     c4a:	4640      	mov	r0, r8
+     c4c:	bc04      	pop	{r2}
+     c4e:	4690      	mov	r8, r2
+     c50:	bdf0      	pop	{r4, r5, r6, r7, pc}
+		return -1;
+     c52:	2301      	movs	r3, #1
+     c54:	425b      	negs	r3, r3
+     c56:	4698      	mov	r8, r3
+     c58:	e7f7      	b.n	c4a <_read+0x26>
+	for (; len > 0; --len) {
+     c5a:	4680      	mov	r8, r0
+     c5c:	e7f5      	b.n	c4a <_read+0x26>
+     c5e:	46c0      	nop			; (mov r8, r8)
+     c60:	20000238 	.word	0x20000238
+     c64:	20000230 	.word	0x20000230
+
+00000c68 <_write>:
+int __attribute__((weak))
+_write (int file, char * ptr, int len);
+
+int __attribute__((weak))
+_write (int file, char * ptr, int len)
+{
+     c68:	b5f0      	push	{r4, r5, r6, r7, lr}
+     c6a:	46c6      	mov	lr, r8
+     c6c:	b500      	push	{lr}
+     c6e:	000e      	movs	r6, r1
+     c70:	0015      	movs	r5, r2
+	int nChars = 0;
+
+	if ((file != 1) && (file != 2) && (file!=3)) {
+     c72:	3801      	subs	r0, #1
+     c74:	2802      	cmp	r0, #2
+     c76:	d810      	bhi.n	c9a <_write+0x32>
+		return -1;
+	}
+
+	for (; len != 0; --len) {
+     c78:	2a00      	cmp	r2, #0
+     c7a:	d011      	beq.n	ca0 <_write+0x38>
+     c7c:	2400      	movs	r4, #0
+		if (ptr_put(stdio_base, *ptr++) < 0) {
+     c7e:	4b0c      	ldr	r3, [pc, #48]	; (cb0 <_write+0x48>)
+     c80:	4698      	mov	r8, r3
+     c82:	4f0c      	ldr	r7, [pc, #48]	; (cb4 <_write+0x4c>)
+     c84:	4643      	mov	r3, r8
+     c86:	6818      	ldr	r0, [r3, #0]
+     c88:	5d31      	ldrb	r1, [r6, r4]
+     c8a:	683b      	ldr	r3, [r7, #0]
+     c8c:	4798      	blx	r3
+     c8e:	2800      	cmp	r0, #0
+     c90:	db08      	blt.n	ca4 <_write+0x3c>
+			return -1;
+		}
+		++nChars;
+     c92:	3401      	adds	r4, #1
+	for (; len != 0; --len) {
+     c94:	42a5      	cmp	r5, r4
+     c96:	d1f5      	bne.n	c84 <_write+0x1c>
+     c98:	e006      	b.n	ca8 <_write+0x40>
+		return -1;
+     c9a:	2401      	movs	r4, #1
+     c9c:	4264      	negs	r4, r4
+     c9e:	e003      	b.n	ca8 <_write+0x40>
+	for (; len != 0; --len) {
+     ca0:	0014      	movs	r4, r2
+     ca2:	e001      	b.n	ca8 <_write+0x40>
+			return -1;
+     ca4:	2401      	movs	r4, #1
+     ca6:	4264      	negs	r4, r4
+	}
+	return nChars;
+}
+     ca8:	0020      	movs	r0, r4
+     caa:	bc04      	pop	{r2}
+     cac:	4690      	mov	r8, r2
+     cae:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     cb0:	20000238 	.word	0x20000238
+     cb4:	20000234 	.word	0x20000234
+
+00000cb8 <padc_init>:
+
+COMPILER_ALIGNED(16)
+DmacDescriptor adc_descriptor SECTION_DMAC_DESCRIPTOR;
+
+void padc_init(void)
+{
+     cb8:	b530      	push	{r4, r5, lr}
+     cba:	b095      	sub	sp, #84	; 0x54
+	// configure adc
+	struct adc_config adc_conf;
+	adc_get_config_defaults(&adc_conf);
+     cbc:	ac08      	add	r4, sp, #32
+     cbe:	0020      	movs	r0, r4
+     cc0:	4b2a      	ldr	r3, [pc, #168]	; (d6c <padc_init+0xb4>)
+     cc2:	4798      	blx	r3
+	adc_conf.gain_factor = P_ADC_GAIN_FACTOR;
+     cc4:	2300      	movs	r3, #0
+     cc6:	60a3      	str	r3, [r4, #8]
+	adc_conf.resolution = P_ADC_RESOLUTION;
+     cc8:	7123      	strb	r3, [r4, #4]
+	adc_conf.clock_prescaler = P_ADC_CLOCK_PRESCALAR;
+     cca:	2280      	movs	r2, #128	; 0x80
+     ccc:	0092      	lsls	r2, r2, #2
+     cce:	8062      	strh	r2, [r4, #2]
+	adc_conf.reference = P_ADC_VREF;
+     cd0:	2201      	movs	r2, #1
+     cd2:	7062      	strb	r2, [r4, #1]
+	adc_conf.positive_input = P_ADC_POSITIVE_INPUT_PIN;
+     cd4:	2104      	movs	r1, #4
+     cd6:	7321      	strb	r1, [r4, #12]
+	adc_conf.negative_input = P_ADC_NEGATIVE_INPUT_PIN;
+     cd8:	21c0      	movs	r1, #192	; 0xc0
+     cda:	0149      	lsls	r1, r1, #5
+     cdc:	81e1      	strh	r1, [r4, #14]
+	adc_conf.freerunning = true;
+     cde:	7522      	strb	r2, [r4, #20]
+	adc_conf.left_adjust = false;
+     ce0:	74a3      	strb	r3, [r4, #18]
+	
+	adc_init(&adc_mod, ADC, &adc_conf);
+     ce2:	4d23      	ldr	r5, [pc, #140]	; (d70 <padc_init+0xb8>)
+     ce4:	0022      	movs	r2, r4
+     ce6:	4923      	ldr	r1, [pc, #140]	; (d74 <padc_init+0xbc>)
+     ce8:	0028      	movs	r0, r5
+     cea:	4b23      	ldr	r3, [pc, #140]	; (d78 <padc_init+0xc0>)
+     cec:	4798      	blx	r3
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+     cee:	682a      	ldr	r2, [r5, #0]
+     cf0:	7e53      	ldrb	r3, [r2, #25]
+
+	while (adc_is_syncing(module_inst)) {
+     cf2:	b25b      	sxtb	r3, r3
+     cf4:	2b00      	cmp	r3, #0
+     cf6:	dbfb      	blt.n	cf0 <padc_init+0x38>
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
+#   endif
+#endif
+
+	/* Disbale interrupt */
+	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+     cf8:	230f      	movs	r3, #15
+     cfa:	7593      	strb	r3, [r2, #22]
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+     cfc:	7613      	strb	r3, [r2, #24]
+
+	adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
+     cfe:	7813      	ldrb	r3, [r2, #0]
+     d00:	2102      	movs	r1, #2
+     d02:	430b      	orrs	r3, r1
+     d04:	7013      	strb	r3, [r2, #0]
+	Adc *const adc_module = module_inst->hw;
+     d06:	4b1a      	ldr	r3, [pc, #104]	; (d70 <padc_init+0xb8>)
+     d08:	681a      	ldr	r2, [r3, #0]
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+     d0a:	7e53      	ldrb	r3, [r2, #25]
+
+	while (adc_is_syncing(module_inst)) {
+     d0c:	b25b      	sxtb	r3, r3
+     d0e:	2b00      	cmp	r3, #0
+     d10:	dbfb      	blt.n	d0a <padc_init+0x52>
+	adc_enable(&adc_mod);
+	
+	// configure dma resource
+	struct dma_resource_config dma_resource_conf;
+	dma_get_config_defaults(&dma_resource_conf);
+     d12:	ac06      	add	r4, sp, #24
+     d14:	0020      	movs	r0, r4
+     d16:	4b19      	ldr	r3, [pc, #100]	; (d7c <padc_init+0xc4>)
+     d18:	4798      	blx	r3
+	dma_resource_conf.peripheral_trigger = ADC_DMAC_ID_RESRDY;
+     d1a:	2327      	movs	r3, #39	; 0x27
+     d1c:	7063      	strb	r3, [r4, #1]
+	dma_resource_conf.trigger_action = DMA_TRIGGER_ACTION_BEAT;
+     d1e:	3b25      	subs	r3, #37	; 0x25
+     d20:	70a3      	strb	r3, [r4, #2]
+	// allocate dma resource
+	dma_allocate(&adc_resource, &dma_resource_conf);
+     d22:	4d17      	ldr	r5, [pc, #92]	; (d80 <padc_init+0xc8>)
+     d24:	0021      	movs	r1, r4
+     d26:	0028      	movs	r0, r5
+     d28:	4b16      	ldr	r3, [pc, #88]	; (d84 <padc_init+0xcc>)
+     d2a:	4798      	blx	r3
+static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
+{
+	Assert(config);
+
+	/* Set descriptor as valid */
+	config->descriptor_valid = true;
+     d2c:	2201      	movs	r2, #1
+     d2e:	466b      	mov	r3, sp
+     d30:	701a      	strb	r2, [r3, #0]
+	/* Disable event output */
+	config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
+     d32:	2300      	movs	r3, #0
+     d34:	4669      	mov	r1, sp
+     d36:	704b      	strb	r3, [r1, #1]
+	/* No block action */
+	config->block_action = DMA_BLOCK_ACTION_NOACT;
+     d38:	708b      	strb	r3, [r1, #2]
+	/* Set beat size to one byte */
+	config->beat_size = DMA_BEAT_SIZE_BYTE;
+	/* Enable source increment */
+	config->src_increment_enable = true;
+	/* Enable destination increment */
+	config->dst_increment_enable = true;
+     d3a:	714a      	strb	r2, [r1, #5]
+	/* Step size is applied to the destination address */
+	config->step_selection = DMA_STEPSEL_DST;
+     d3c:	718b      	strb	r3, [r1, #6]
+	/* Address increment is beat size multiplied by 1*/
+	config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
+     d3e:	71cb      	strb	r3, [r1, #7]
+	// setup transfer descriptor
+	struct dma_descriptor_config dma_desc_conf;
+	dma_descriptor_get_config_defaults(&dma_desc_conf);
+	dma_desc_conf.beat_size = DMA_BEAT_SIZE_HWORD;	// 16 bit
+     d40:	70ca      	strb	r2, [r1, #3]
+	dma_desc_conf.dst_increment_enable = true;
+	dma_desc_conf.src_increment_enable = false;
+     d42:	710b      	strb	r3, [r1, #4]
+	dma_desc_conf.block_transfer_count = sizeof(raw_adc_values) / 2;
+     d44:	3310      	adds	r3, #16
+     d46:	810b      	strh	r3, [r1, #8]
+	dma_desc_conf.source_address = (uint32_t)(&adc_mod.hw->RESULT.reg);
+     d48:	4b09      	ldr	r3, [pc, #36]	; (d70 <padc_init+0xb8>)
+     d4a:	681b      	ldr	r3, [r3, #0]
+     d4c:	331a      	adds	r3, #26
+     d4e:	9303      	str	r3, [sp, #12]
+	dma_desc_conf.destination_address = (uint32_t)(raw_adc_values + (sizeof(raw_adc_values) / 2));
+     d50:	4b0d      	ldr	r3, [pc, #52]	; (d88 <padc_init+0xd0>)
+     d52:	3320      	adds	r3, #32
+     d54:	9304      	str	r3, [sp, #16]
+	dma_desc_conf.next_descriptor_address = (uint32_t)&adc_descriptor;
+     d56:	4c0d      	ldr	r4, [pc, #52]	; (d8c <padc_init+0xd4>)
+     d58:	9405      	str	r4, [sp, #20]
+	dma_descriptor_create(&adc_descriptor, &dma_desc_conf);
+     d5a:	0020      	movs	r0, r4
+     d5c:	4b0c      	ldr	r3, [pc, #48]	; (d90 <padc_init+0xd8>)
+     d5e:	4798      	blx	r3
+	dma_add_descriptor(&adc_resource, &adc_descriptor);
+     d60:	0021      	movs	r1, r4
+     d62:	0028      	movs	r0, r5
+     d64:	4b0b      	ldr	r3, [pc, #44]	; (d94 <padc_init+0xdc>)
+     d66:	4798      	blx	r3
+}
+     d68:	b015      	add	sp, #84	; 0x54
+     d6a:	bd30      	pop	{r4, r5, pc}
+     d6c:	00000115 	.word	0x00000115
+     d70:	2000010c 	.word	0x2000010c
+     d74:	42004000 	.word	0x42004000
+     d78:	0000015d 	.word	0x0000015d
+     d7c:	00000601 	.word	0x00000601
+     d80:	20000114 	.word	0x20000114
+     d84:	00000611 	.word	0x00000611
+     d88:	20000130 	.word	0x20000130
+     d8c:	20000240 	.word	0x20000240
+     d90:	000007e1 	.word	0x000007e1
+     d94:	00000889 	.word	0x00000889
+
+00000d98 <padc_start>:
+
+void padc_start(void)
+{
+     d98:	b510      	push	{r4, lr}
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+     d9a:	4b09      	ldr	r3, [pc, #36]	; (dc0 <padc_start+0x28>)
+     d9c:	681a      	ldr	r2, [r3, #0]
+     d9e:	7e53      	ldrb	r3, [r2, #25]
+
+	while (adc_is_syncing(module_inst)) {
+     da0:	b25b      	sxtb	r3, r3
+     da2:	2b00      	cmp	r3, #0
+     da4:	dbfb      	blt.n	d9e <padc_start+0x6>
+		/* Wait for synchronization */
+	}
+
+	adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
+     da6:	7b13      	ldrb	r3, [r2, #12]
+     da8:	2102      	movs	r1, #2
+     daa:	430b      	orrs	r3, r1
+     dac:	7313      	strb	r3, [r2, #12]
+     dae:	7e53      	ldrb	r3, [r2, #25]
+
+	while (adc_is_syncing(module_inst)) {
+     db0:	b25b      	sxtb	r3, r3
+     db2:	2b00      	cmp	r3, #0
+     db4:	dbfb      	blt.n	dae <padc_start+0x16>
+	adc_start_conversion(&adc_mod);
+	dma_start_transfer_job(&adc_resource);
+     db6:	4803      	ldr	r0, [pc, #12]	; (dc4 <padc_start+0x2c>)
+     db8:	4b03      	ldr	r3, [pc, #12]	; (dc8 <padc_start+0x30>)
+     dba:	4798      	blx	r3
+}
+     dbc:	bd10      	pop	{r4, pc}
+     dbe:	46c0      	nop			; (mov r8, r8)
+     dc0:	2000010c 	.word	0x2000010c
+     dc4:	20000114 	.word	0x20000114
+     dc8:	00000759 	.word	0x00000759
+
+00000dcc <padc_get_raw>:
+	uint16_t raw = padc_get_raw();
+	return (float)((float)raw / 4096.0f * P_ADC_VREF_VAL);
+}
+
+uint16_t padc_get_raw(void)
+{
+     dcc:	4b05      	ldr	r3, [pc, #20]	; (de4 <padc_get_raw+0x18>)
+     dce:	0019      	movs	r1, r3
+     dd0:	3120      	adds	r1, #32
+	uint32_t sum = 0;
+     dd2:	2000      	movs	r0, #0
+	for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
+	{
+		sum += (uint32_t)raw_adc_values[ind];
+     dd4:	881a      	ldrh	r2, [r3, #0]
+     dd6:	1880      	adds	r0, r0, r2
+     dd8:	3302      	adds	r3, #2
+	for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
+     dda:	428b      	cmp	r3, r1
+     ddc:	d1fa      	bne.n	dd4 <padc_get_raw+0x8>
+	}
+	sum /= P_ADC_OVERSAMPLE_RATE;
+     dde:	0900      	lsrs	r0, r0, #4
+	return (uint16_t)sum;
+     de0:	b280      	uxth	r0, r0
+     de2:	4770      	bx	lr
+     de4:	20000130 	.word	0x20000130
+
+00000de8 <padc_get_voltage>:
+{
+     de8:	b510      	push	{r4, lr}
+	uint16_t raw = padc_get_raw();
+     dea:	4b05      	ldr	r3, [pc, #20]	; (e00 <padc_get_voltage+0x18>)
+     dec:	4798      	blx	r3
+	return (float)((float)raw / 4096.0f * P_ADC_VREF_VAL);
+     dee:	4b05      	ldr	r3, [pc, #20]	; (e04 <padc_get_voltage+0x1c>)
+     df0:	4798      	blx	r3
+     df2:	4c05      	ldr	r4, [pc, #20]	; (e08 <padc_get_voltage+0x20>)
+     df4:	21e6      	movs	r1, #230	; 0xe6
+     df6:	0589      	lsls	r1, r1, #22
+     df8:	47a0      	blx	r4
+     dfa:	4904      	ldr	r1, [pc, #16]	; (e0c <padc_get_voltage+0x24>)
+     dfc:	47a0      	blx	r4
+}
+     dfe:	bd10      	pop	{r4, pc}
+     e00:	00000dcd 	.word	0x00000dcd
+     e04:	000025b9 	.word	0x000025b9
+     e08:	00001f61 	.word	0x00001f61
+     e0c:	400eb368 	.word	0x400eb368
+
+00000e10 <usart_serial_getchar>:
+ * \param[out]    c       Destination for the read character.
+ */
+static inline void usart_serial_getchar(
+		struct usart_module *const module,
+		uint8_t *c)
+{
+     e10:	b570      	push	{r4, r5, r6, lr}
+     e12:	b082      	sub	sp, #8
+     e14:	0005      	movs	r5, r0
+     e16:	000e      	movs	r6, r1
+	uint16_t temp = 0;
+     e18:	2200      	movs	r2, #0
+     e1a:	466b      	mov	r3, sp
+     e1c:	80da      	strh	r2, [r3, #6]
+
+	while(STATUS_OK != usart_read_wait(module, &temp));
+     e1e:	4c06      	ldr	r4, [pc, #24]	; (e38 <usart_serial_getchar+0x28>)
+     e20:	466b      	mov	r3, sp
+     e22:	1d99      	adds	r1, r3, #6
+     e24:	0028      	movs	r0, r5
+     e26:	47a0      	blx	r4
+     e28:	2800      	cmp	r0, #0
+     e2a:	d1f9      	bne.n	e20 <usart_serial_getchar+0x10>
+
+	*c = temp;
+     e2c:	466b      	mov	r3, sp
+     e2e:	3306      	adds	r3, #6
+     e30:	881b      	ldrh	r3, [r3, #0]
+     e32:	7033      	strb	r3, [r6, #0]
+}
+     e34:	b002      	add	sp, #8
+     e36:	bd70      	pop	{r4, r5, r6, pc}
+     e38:	000012a7 	.word	0x000012a7
+
+00000e3c <usart_serial_putchar>:
+{
+     e3c:	b570      	push	{r4, r5, r6, lr}
+     e3e:	0005      	movs	r5, r0
+	while(STATUS_OK !=usart_write_wait(module, c));
+     e40:	b28c      	uxth	r4, r1
+     e42:	4e03      	ldr	r6, [pc, #12]	; (e50 <usart_serial_putchar+0x14>)
+     e44:	0021      	movs	r1, r4
+     e46:	0028      	movs	r0, r5
+     e48:	47b0      	blx	r6
+     e4a:	2800      	cmp	r0, #0
+     e4c:	d1fa      	bne.n	e44 <usart_serial_putchar+0x8>
+}
+     e4e:	bd70      	pop	{r4, r5, r6, pc}
+     e50:	00001281 	.word	0x00001281
+
+00000e54 <pusart_init>:
+#include "pusart.h"
+
+void pusart_init(void)
+{
+     e54:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Set default config in the config struct */
+	config->data_order       = USART_DATAORDER_LSB;
+     e56:	4a2c      	ldr	r2, [pc, #176]	; (f08 <pusart_init+0xb4>)
+     e58:	2380      	movs	r3, #128	; 0x80
+     e5a:	05db      	lsls	r3, r3, #23
+     e5c:	6013      	str	r3, [r2, #0]
+	config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
+     e5e:	2300      	movs	r3, #0
+     e60:	6053      	str	r3, [r2, #4]
+	config->parity           = USART_PARITY_NONE;
+     e62:	21ff      	movs	r1, #255	; 0xff
+     e64:	8111      	strh	r1, [r2, #8]
+	config->stopbits         = USART_STOPBITS_1;
+     e66:	2100      	movs	r1, #0
+     e68:	7293      	strb	r3, [r2, #10]
+	config->character_size   = USART_CHARACTER_SIZE_8BIT;
+     e6a:	72d3      	strb	r3, [r2, #11]
+	config->baudrate         = 9600;
+	config->receiver_enable  = true;
+     e6c:	2401      	movs	r4, #1
+     e6e:	2024      	movs	r0, #36	; 0x24
+     e70:	5414      	strb	r4, [r2, r0]
+	config->transmitter_enable = true;
+     e72:	3001      	adds	r0, #1
+     e74:	5414      	strb	r4, [r2, r0]
+	config->clock_polarity_inverted = false;
+     e76:	3001      	adds	r0, #1
+     e78:	5413      	strb	r3, [r2, r0]
+	config->use_external_clock = false;
+     e7a:	3001      	adds	r0, #1
+     e7c:	5413      	strb	r3, [r2, r0]
+	config->ext_clock_freq   = 0;
+     e7e:	6293      	str	r3, [r2, #40]	; 0x28
+	config->mux_setting      = USART_RX_1_TX_2_XCK_3;
+	config->run_in_standby   = false;
+     e80:	3005      	adds	r0, #5
+     e82:	5413      	strb	r3, [r2, r0]
+	config->generator_source = GCLK_GENERATOR_0;
+     e84:	3001      	adds	r0, #1
+     e86:	5413      	strb	r3, [r2, r0]
+	config->pinmux_pad0      = PINMUX_DEFAULT;
+	config->pinmux_pad1      = PINMUX_DEFAULT;
+	config->pinmux_pad2      = PINMUX_DEFAULT;
+	config->pinmux_pad3      = PINMUX_DEFAULT;
+#ifdef FEATURE_USART_OVER_SAMPLE
+	config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
+     e88:	6153      	str	r3, [r2, #20]
+	config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
+     e8a:	8213      	strh	r3, [r2, #16]
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+	config->lin_slave_enable      = false;
+     e8c:	76d3      	strb	r3, [r2, #27]
+	config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
+	config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
+#endif
+
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+	config->immediate_buffer_overflow_notification  = false;
+     e8e:	7611      	strb	r1, [r2, #24]
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	config->start_frame_detection_enable            = false;
+     e90:	7711      	strb	r1, [r2, #28]
+#endif
+#ifdef FEATURE_USART_IRDA
+	config->encoding_format_enable                  = false;
+     e92:	7651      	strb	r1, [r2, #25]
+	config->receive_pulse_length                    = 19;
+     e94:	2313      	movs	r3, #19
+     e96:	7693      	strb	r3, [r2, #26]
+	config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
+	config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
+	config->iso7816_config.max_iterations           = 7;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+	config->collision_detection_enable              = false;
+     e98:	7751      	strb	r1, [r2, #29]
+	static struct usart_config uconf;
+	usart_get_config_defaults(&uconf);
+	uconf.pinmux_pad0 = DEBUG_USART_PINMUX_PAD0;
+     e9a:	4b1c      	ldr	r3, [pc, #112]	; (f0c <pusart_init+0xb8>)
+     e9c:	6313      	str	r3, [r2, #48]	; 0x30
+	uconf.pinmux_pad1 = DEBUG_USART_PINMUX_PAD1;
+     e9e:	4b1c      	ldr	r3, [pc, #112]	; (f10 <pusart_init+0xbc>)
+     ea0:	6353      	str	r3, [r2, #52]	; 0x34
+	uconf.pinmux_pad2 = DEBUG_USART_PINMUX_PAD2;
+     ea2:	2301      	movs	r3, #1
+     ea4:	425b      	negs	r3, r3
+     ea6:	6393      	str	r3, [r2, #56]	; 0x38
+	uconf.pinmux_pad3 = DEBUG_USART_PINMUX_PAD3;
+     ea8:	63d3      	str	r3, [r2, #60]	; 0x3c
+	uconf.mux_setting = DEBUG_USART_MUX_SETTING;
+     eaa:	2380      	movs	r3, #128	; 0x80
+     eac:	035b      	lsls	r3, r3, #13
+     eae:	60d3      	str	r3, [r2, #12]
+	uconf.baudrate = DEBUG_USART_BAUDRATE;
+     eb0:	23e1      	movs	r3, #225	; 0xe1
+     eb2:	025b      	lsls	r3, r3, #9
+     eb4:	6213      	str	r3, [r2, #32]
+static inline void stdio_serial_init(
+		struct usart_module *const module,
+		usart_inst_t const hw,
+		const struct usart_config *const config)
+{
+	stdio_base = (void *)module;
+     eb6:	4d17      	ldr	r5, [pc, #92]	; (f14 <pusart_init+0xc0>)
+     eb8:	4b17      	ldr	r3, [pc, #92]	; (f18 <pusart_init+0xc4>)
+     eba:	601d      	str	r5, [r3, #0]
+	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+     ebc:	4917      	ldr	r1, [pc, #92]	; (f1c <pusart_init+0xc8>)
+     ebe:	4b18      	ldr	r3, [pc, #96]	; (f20 <pusart_init+0xcc>)
+     ec0:	6019      	str	r1, [r3, #0]
+	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+     ec2:	4918      	ldr	r1, [pc, #96]	; (f24 <pusart_init+0xd0>)
+     ec4:	4b18      	ldr	r3, [pc, #96]	; (f28 <pusart_init+0xd4>)
+     ec6:	6019      	str	r1, [r3, #0]
+	if (usart_init(module, hw, config) == STATUS_OK) {
+     ec8:	4918      	ldr	r1, [pc, #96]	; (f2c <pusart_init+0xd8>)
+     eca:	0028      	movs	r0, r5
+     ecc:	4b18      	ldr	r3, [pc, #96]	; (f30 <pusart_init+0xdc>)
+     ece:	4798      	blx	r3
+
+	usart_serial_init(module, hw, config);
+# if defined(__GNUC__)
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+     ed0:	4f18      	ldr	r7, [pc, #96]	; (f34 <pusart_init+0xe0>)
+     ed2:	683b      	ldr	r3, [r7, #0]
+     ed4:	6898      	ldr	r0, [r3, #8]
+     ed6:	2100      	movs	r1, #0
+     ed8:	4e17      	ldr	r6, [pc, #92]	; (f38 <pusart_init+0xe4>)
+     eda:	47b0      	blx	r6
+	setbuf(stdin, NULL);
+     edc:	683b      	ldr	r3, [r7, #0]
+     ede:	6858      	ldr	r0, [r3, #4]
+     ee0:	2100      	movs	r1, #0
+     ee2:	47b0      	blx	r6
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+     ee4:	682e      	ldr	r6, [r5, #0]
+
+#if USART_CALLBACK_MODE == true
+	/* Enable Global interrupt for module */
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+     ee6:	0030      	movs	r0, r6
+     ee8:	4b14      	ldr	r3, [pc, #80]	; (f3c <pusart_init+0xe8>)
+     eea:	4798      	blx	r3
+	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+     eec:	231f      	movs	r3, #31
+     eee:	4018      	ands	r0, r3
+     ef0:	4084      	lsls	r4, r0
+     ef2:	4b13      	ldr	r3, [pc, #76]	; (f40 <pusart_init+0xec>)
+     ef4:	601c      	str	r4, [r3, #0]
+	SercomUsart *const usart_hw = &(module->hw->USART);
+     ef6:	682a      	ldr	r2, [r5, #0]
+	return (usart_hw->SYNCBUSY.reg);
+     ef8:	69d3      	ldr	r3, [r2, #28]
+	while (usart_is_syncing(module)) {
+     efa:	2b00      	cmp	r3, #0
+     efc:	d1fc      	bne.n	ef8 <pusart_init+0xa4>
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Enable USART module */
+	usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+     efe:	6833      	ldr	r3, [r6, #0]
+     f00:	2202      	movs	r2, #2
+     f02:	4313      	orrs	r3, r2
+     f04:	6033      	str	r3, [r6, #0]
+	stdio_serial_init(&umod, DEBUG_USART_MODULE, &uconf);
+	usart_enable(&umod);
+}
+     f06:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+     f08:	20000150 	.word	0x20000150
+     f0c:	00160002 	.word	0x00160002
+     f10:	00170002 	.word	0x00170002
+     f14:	20000250 	.word	0x20000250
+     f18:	20000238 	.word	0x20000238
+     f1c:	00000e3d 	.word	0x00000e3d
+     f20:	20000234 	.word	0x20000234
+     f24:	00000e11 	.word	0x00000e11
+     f28:	20000230 	.word	0x20000230
+     f2c:	42001400 	.word	0x42001400
+     f30:	00000f45 	.word	0x00000f45
+     f34:	20000018 	.word	0x20000018
+     f38:	00002721 	.word	0x00002721
+     f3c:	000014e5 	.word	0x000014e5
+     f40:	e000e100 	.word	0xe000e100
+
+00000f44 <usart_init>:
+ */
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config)
+{
+     f44:	b5f0      	push	{r4, r5, r6, r7, lr}
+     f46:	46de      	mov	lr, fp
+     f48:	4657      	mov	r7, sl
+     f4a:	464e      	mov	r6, r9
+     f4c:	4645      	mov	r5, r8
+     f4e:	b5e0      	push	{r5, r6, r7, lr}
+     f50:	b091      	sub	sp, #68	; 0x44
+     f52:	0005      	movs	r5, r0
+     f54:	000c      	movs	r4, r1
+     f56:	0016      	movs	r6, r2
+	Assert(config);
+
+	enum status_code status_code = STATUS_OK;
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+     f58:	6029      	str	r1, [r5, #0]
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+     f5a:	0008      	movs	r0, r1
+     f5c:	4bba      	ldr	r3, [pc, #744]	; (1248 <usart_init+0x304>)
+     f5e:	4798      	blx	r3
+     f60:	0002      	movs	r2, r0
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+     f62:	6823      	ldr	r3, [r4, #0]
+		/* The module is busy resetting itself */
+		return STATUS_BUSY;
+     f64:	2005      	movs	r0, #5
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+     f66:	07db      	lsls	r3, r3, #31
+     f68:	d506      	bpl.n	f78 <usart_init+0x34>
+	_sercom_set_handler(instance_index, _usart_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+#endif
+
+	return status_code;
+}
+     f6a:	b011      	add	sp, #68	; 0x44
+     f6c:	bc3c      	pop	{r2, r3, r4, r5}
+     f6e:	4690      	mov	r8, r2
+     f70:	4699      	mov	r9, r3
+     f72:	46a2      	mov	sl, r4
+     f74:	46ab      	mov	fp, r5
+     f76:	bdf0      	pop	{r4, r5, r6, r7, pc}
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+     f78:	6823      	ldr	r3, [r4, #0]
+		return STATUS_ERR_DENIED;
+     f7a:	3017      	adds	r0, #23
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+     f7c:	079b      	lsls	r3, r3, #30
+     f7e:	d4f4      	bmi.n	f6a <usart_init+0x26>
+			PM->APBCMASK.reg |= mask;
+     f80:	49b2      	ldr	r1, [pc, #712]	; (124c <usart_init+0x308>)
+     f82:	6a08      	ldr	r0, [r1, #32]
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+     f84:	1c97      	adds	r7, r2, #2
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+     f86:	2301      	movs	r3, #1
+     f88:	40bb      	lsls	r3, r7
+     f8a:	4303      	orrs	r3, r0
+     f8c:	620b      	str	r3, [r1, #32]
+	gclk_chan_conf.source_generator = config->generator_source;
+     f8e:	a90f      	add	r1, sp, #60	; 0x3c
+     f90:	272d      	movs	r7, #45	; 0x2d
+     f92:	5df3      	ldrb	r3, [r6, r7]
+     f94:	700b      	strb	r3, [r1, #0]
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+     f96:	3214      	adds	r2, #20
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+     f98:	b2d3      	uxtb	r3, r2
+     f9a:	9302      	str	r3, [sp, #8]
+     f9c:	0018      	movs	r0, r3
+     f9e:	4bac      	ldr	r3, [pc, #688]	; (1250 <usart_init+0x30c>)
+     fa0:	4798      	blx	r3
+	system_gclk_chan_enable(gclk_index);
+     fa2:	9802      	ldr	r0, [sp, #8]
+     fa4:	4bab      	ldr	r3, [pc, #684]	; (1254 <usart_init+0x310>)
+     fa6:	4798      	blx	r3
+	sercom_set_gclk_generator(config->generator_source, false);
+     fa8:	5df0      	ldrb	r0, [r6, r7]
+     faa:	2100      	movs	r1, #0
+     fac:	4baa      	ldr	r3, [pc, #680]	; (1258 <usart_init+0x314>)
+     fae:	4798      	blx	r3
+	module->character_size = config->character_size;
+     fb0:	7af3      	ldrb	r3, [r6, #11]
+     fb2:	716b      	strb	r3, [r5, #5]
+	module->receiver_enabled = config->receiver_enable;
+     fb4:	2324      	movs	r3, #36	; 0x24
+     fb6:	5cf3      	ldrb	r3, [r6, r3]
+     fb8:	71ab      	strb	r3, [r5, #6]
+	module->transmitter_enabled = config->transmitter_enable;
+     fba:	2325      	movs	r3, #37	; 0x25
+     fbc:	5cf3      	ldrb	r3, [r6, r3]
+     fbe:	71eb      	strb	r3, [r5, #7]
+	module->lin_slave_enabled = config->lin_slave_enable;
+     fc0:	7ef3      	ldrb	r3, [r6, #27]
+     fc2:	722b      	strb	r3, [r5, #8]
+	module->start_frame_detection_enabled = config->start_frame_detection_enable;
+     fc4:	7f33      	ldrb	r3, [r6, #28]
+     fc6:	726b      	strb	r3, [r5, #9]
+	SercomUsart *const usart_hw = &(module->hw->USART);
+     fc8:	682b      	ldr	r3, [r5, #0]
+     fca:	4698      	mov	r8, r3
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+     fcc:	0018      	movs	r0, r3
+     fce:	4b9e      	ldr	r3, [pc, #632]	; (1248 <usart_init+0x304>)
+     fd0:	4798      	blx	r3
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+     fd2:	3014      	adds	r0, #20
+	uint16_t baud  = 0;
+     fd4:	2200      	movs	r2, #0
+     fd6:	230e      	movs	r3, #14
+     fd8:	a906      	add	r1, sp, #24
+     fda:	468c      	mov	ip, r1
+     fdc:	4463      	add	r3, ip
+     fde:	801a      	strh	r2, [r3, #0]
+	switch (config->sample_rate) {
+     fe0:	8a32      	ldrh	r2, [r6, #16]
+     fe2:	9202      	str	r2, [sp, #8]
+     fe4:	2380      	movs	r3, #128	; 0x80
+     fe6:	01db      	lsls	r3, r3, #7
+     fe8:	429a      	cmp	r2, r3
+     fea:	d100      	bne.n	fee <usart_init+0xaa>
+     fec:	e09a      	b.n	1124 <usart_init+0x1e0>
+     fee:	d90f      	bls.n	1010 <usart_init+0xcc>
+     ff0:	23c0      	movs	r3, #192	; 0xc0
+     ff2:	01db      	lsls	r3, r3, #7
+     ff4:	9a02      	ldr	r2, [sp, #8]
+     ff6:	429a      	cmp	r2, r3
+     ff8:	d100      	bne.n	ffc <usart_init+0xb8>
+     ffa:	e08e      	b.n	111a <usart_init+0x1d6>
+     ffc:	2380      	movs	r3, #128	; 0x80
+     ffe:	021b      	lsls	r3, r3, #8
+    1000:	429a      	cmp	r2, r3
+    1002:	d000      	beq.n	1006 <usart_init+0xc2>
+    1004:	e11b      	b.n	123e <usart_init+0x2fa>
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+    1006:	2303      	movs	r3, #3
+    1008:	9306      	str	r3, [sp, #24]
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+    100a:	2300      	movs	r3, #0
+    100c:	9307      	str	r3, [sp, #28]
+    100e:	e008      	b.n	1022 <usart_init+0xde>
+	switch (config->sample_rate) {
+    1010:	2380      	movs	r3, #128	; 0x80
+    1012:	019b      	lsls	r3, r3, #6
+    1014:	429a      	cmp	r2, r3
+    1016:	d000      	beq.n	101a <usart_init+0xd6>
+    1018:	e111      	b.n	123e <usart_init+0x2fa>
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+    101a:	2310      	movs	r3, #16
+    101c:	9306      	str	r3, [sp, #24]
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+    101e:	3b0f      	subs	r3, #15
+    1020:	9307      	str	r3, [sp, #28]
+	ctrla = (uint32_t)config->data_order |
+    1022:	6833      	ldr	r3, [r6, #0]
+    1024:	9305      	str	r3, [sp, #20]
+		(uint32_t)config->mux_setting |
+    1026:	68f3      	ldr	r3, [r6, #12]
+    1028:	469b      	mov	fp, r3
+		config->sample_adjustment |
+    102a:	6973      	ldr	r3, [r6, #20]
+    102c:	9303      	str	r3, [sp, #12]
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+    102e:	7e33      	ldrb	r3, [r6, #24]
+    1030:	9304      	str	r3, [sp, #16]
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+    1032:	2326      	movs	r3, #38	; 0x26
+    1034:	5cf3      	ldrb	r3, [r6, r3]
+    1036:	469a      	mov	sl, r3
+	transfer_mode = (uint32_t)config->transfer_mode;
+    1038:	6873      	ldr	r3, [r6, #4]
+    103a:	4699      	mov	r9, r3
+	switch (transfer_mode)
+    103c:	2b00      	cmp	r3, #0
+    103e:	d100      	bne.n	1042 <usart_init+0xfe>
+    1040:	e09c      	b.n	117c <usart_init+0x238>
+    1042:	2380      	movs	r3, #128	; 0x80
+    1044:	055b      	lsls	r3, r3, #21
+    1046:	4599      	cmp	r9, r3
+    1048:	d100      	bne.n	104c <usart_init+0x108>
+    104a:	e080      	b.n	114e <usart_init+0x20a>
+	if(config->encoding_format_enable) {
+    104c:	7e73      	ldrb	r3, [r6, #25]
+    104e:	2b00      	cmp	r3, #0
+    1050:	d002      	beq.n	1058 <usart_init+0x114>
+		usart_hw->RXPL.reg = config->receive_pulse_length;
+    1052:	7eb3      	ldrb	r3, [r6, #26]
+    1054:	4642      	mov	r2, r8
+    1056:	7393      	strb	r3, [r2, #14]
+	usart_hw->BAUD.reg = baud;
+    1058:	230e      	movs	r3, #14
+    105a:	aa06      	add	r2, sp, #24
+    105c:	4694      	mov	ip, r2
+    105e:	4463      	add	r3, ip
+    1060:	881b      	ldrh	r3, [r3, #0]
+    1062:	4642      	mov	r2, r8
+    1064:	8193      	strh	r3, [r2, #12]
+	ctrla |= transfer_mode;
+    1066:	9b05      	ldr	r3, [sp, #20]
+    1068:	465a      	mov	r2, fp
+    106a:	4313      	orrs	r3, r2
+    106c:	9a03      	ldr	r2, [sp, #12]
+    106e:	4313      	orrs	r3, r2
+    1070:	464a      	mov	r2, r9
+    1072:	4313      	orrs	r3, r2
+    1074:	9f02      	ldr	r7, [sp, #8]
+    1076:	431f      	orrs	r7, r3
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+    1078:	9b04      	ldr	r3, [sp, #16]
+    107a:	021b      	lsls	r3, r3, #8
+	ctrla |= transfer_mode;
+    107c:	431f      	orrs	r7, r3
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+    107e:	4653      	mov	r3, sl
+    1080:	075b      	lsls	r3, r3, #29
+	ctrla |= transfer_mode;
+    1082:	431f      	orrs	r7, r3
+	if (config->use_external_clock == false) {
+    1084:	2327      	movs	r3, #39	; 0x27
+    1086:	5cf3      	ldrb	r3, [r6, r3]
+    1088:	2b00      	cmp	r3, #0
+    108a:	d101      	bne.n	1090 <usart_init+0x14c>
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+    108c:	3304      	adds	r3, #4
+    108e:	431f      	orrs	r7, r3
+			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+    1090:	7e73      	ldrb	r3, [r6, #25]
+    1092:	029b      	lsls	r3, r3, #10
+			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+    1094:	7f32      	ldrb	r2, [r6, #28]
+    1096:	0252      	lsls	r2, r2, #9
+			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+    1098:	4313      	orrs	r3, r2
+			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+    109a:	7f72      	ldrb	r2, [r6, #29]
+    109c:	0212      	lsls	r2, r2, #8
+			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+    109e:	4313      	orrs	r3, r2
+			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+    10a0:	2224      	movs	r2, #36	; 0x24
+    10a2:	5cb2      	ldrb	r2, [r6, r2]
+    10a4:	0452      	lsls	r2, r2, #17
+			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+    10a6:	4313      	orrs	r3, r2
+			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+    10a8:	2225      	movs	r2, #37	; 0x25
+    10aa:	5cb2      	ldrb	r2, [r6, r2]
+    10ac:	0412      	lsls	r2, r2, #16
+			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+    10ae:	4313      	orrs	r3, r2
+	ctrlb |= (uint32_t)config->character_size;
+    10b0:	7ab1      	ldrb	r1, [r6, #10]
+    10b2:	7af2      	ldrb	r2, [r6, #11]
+    10b4:	4311      	orrs	r1, r2
+    10b6:	4319      	orrs	r1, r3
+	if (config->parity != USART_PARITY_NONE) {
+    10b8:	8933      	ldrh	r3, [r6, #8]
+    10ba:	2bff      	cmp	r3, #255	; 0xff
+    10bc:	d100      	bne.n	10c0 <usart_init+0x17c>
+    10be:	e081      	b.n	11c4 <usart_init+0x280>
+		ctrla |= SERCOM_USART_CTRLA_FORM(1);
+    10c0:	2280      	movs	r2, #128	; 0x80
+    10c2:	0452      	lsls	r2, r2, #17
+    10c4:	4317      	orrs	r7, r2
+		ctrlb |= config->parity;
+    10c6:	4319      	orrs	r1, r3
+	if (config->run_in_standby || system_is_debugger_present()) {
+    10c8:	232c      	movs	r3, #44	; 0x2c
+    10ca:	5cf3      	ldrb	r3, [r6, r3]
+    10cc:	2b00      	cmp	r3, #0
+    10ce:	d103      	bne.n	10d8 <usart_init+0x194>
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+    10d0:	4b62      	ldr	r3, [pc, #392]	; (125c <usart_init+0x318>)
+    10d2:	789b      	ldrb	r3, [r3, #2]
+    10d4:	079b      	lsls	r3, r3, #30
+    10d6:	d501      	bpl.n	10dc <usart_init+0x198>
+		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+    10d8:	2380      	movs	r3, #128	; 0x80
+    10da:	431f      	orrs	r7, r3
+	SercomUsart *const usart_hw = &(module->hw->USART);
+    10dc:	682a      	ldr	r2, [r5, #0]
+	return (usart_hw->SYNCBUSY.reg);
+    10de:	69d3      	ldr	r3, [r2, #28]
+	while (usart_is_syncing(module)) {
+    10e0:	2b00      	cmp	r3, #0
+    10e2:	d1fc      	bne.n	10de <usart_init+0x19a>
+	usart_hw->CTRLB.reg = ctrlb;
+    10e4:	4643      	mov	r3, r8
+    10e6:	6059      	str	r1, [r3, #4]
+	SercomUsart *const usart_hw = &(module->hw->USART);
+    10e8:	682a      	ldr	r2, [r5, #0]
+	return (usart_hw->SYNCBUSY.reg);
+    10ea:	69d3      	ldr	r3, [r2, #28]
+	while (usart_is_syncing(module)) {
+    10ec:	2b00      	cmp	r3, #0
+    10ee:	d1fc      	bne.n	10ea <usart_init+0x1a6>
+	usart_hw->CTRLA.reg = ctrla;
+    10f0:	4643      	mov	r3, r8
+    10f2:	601f      	str	r7, [r3, #0]
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+    10f4:	ab0e      	add	r3, sp, #56	; 0x38
+    10f6:	2280      	movs	r2, #128	; 0x80
+    10f8:	701a      	strb	r2, [r3, #0]
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    10fa:	2200      	movs	r2, #0
+    10fc:	705a      	strb	r2, [r3, #1]
+	config->powersave    = false;
+    10fe:	70da      	strb	r2, [r3, #3]
+	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+    1100:	709a      	strb	r2, [r3, #2]
+	uint32_t pad_pinmuxes[] = {
+    1102:	6b33      	ldr	r3, [r6, #48]	; 0x30
+    1104:	930a      	str	r3, [sp, #40]	; 0x28
+    1106:	6b73      	ldr	r3, [r6, #52]	; 0x34
+    1108:	930b      	str	r3, [sp, #44]	; 0x2c
+    110a:	6bb3      	ldr	r3, [r6, #56]	; 0x38
+    110c:	930c      	str	r3, [sp, #48]	; 0x30
+    110e:	6bf3      	ldr	r3, [r6, #60]	; 0x3c
+    1110:	9302      	str	r3, [sp, #8]
+    1112:	930d      	str	r3, [sp, #52]	; 0x34
+    1114:	2700      	movs	r7, #0
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+    1116:	ae0a      	add	r6, sp, #40	; 0x28
+    1118:	e063      	b.n	11e2 <usart_init+0x29e>
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+    111a:	2308      	movs	r3, #8
+    111c:	9306      	str	r3, [sp, #24]
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+    111e:	3b07      	subs	r3, #7
+    1120:	9307      	str	r3, [sp, #28]
+    1122:	e77e      	b.n	1022 <usart_init+0xde>
+	ctrla = (uint32_t)config->data_order |
+    1124:	6833      	ldr	r3, [r6, #0]
+    1126:	9305      	str	r3, [sp, #20]
+		(uint32_t)config->mux_setting |
+    1128:	68f3      	ldr	r3, [r6, #12]
+    112a:	469b      	mov	fp, r3
+		config->sample_adjustment |
+    112c:	6973      	ldr	r3, [r6, #20]
+    112e:	9303      	str	r3, [sp, #12]
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+    1130:	7e33      	ldrb	r3, [r6, #24]
+    1132:	9304      	str	r3, [sp, #16]
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+    1134:	2326      	movs	r3, #38	; 0x26
+    1136:	5cf3      	ldrb	r3, [r6, r3]
+    1138:	469a      	mov	sl, r3
+	transfer_mode = (uint32_t)config->transfer_mode;
+    113a:	6873      	ldr	r3, [r6, #4]
+    113c:	4699      	mov	r9, r3
+	switch (transfer_mode)
+    113e:	2b00      	cmp	r3, #0
+    1140:	d018      	beq.n	1174 <usart_init+0x230>
+    1142:	2380      	movs	r3, #128	; 0x80
+    1144:	055b      	lsls	r3, r3, #21
+    1146:	4599      	cmp	r9, r3
+    1148:	d001      	beq.n	114e <usart_init+0x20a>
+	enum status_code status_code = STATUS_OK;
+    114a:	2000      	movs	r0, #0
+    114c:	e025      	b.n	119a <usart_init+0x256>
+			if (!config->use_external_clock) {
+    114e:	2327      	movs	r3, #39	; 0x27
+    1150:	5cf3      	ldrb	r3, [r6, r3]
+    1152:	2b00      	cmp	r3, #0
+    1154:	d000      	beq.n	1158 <usart_init+0x214>
+    1156:	e779      	b.n	104c <usart_init+0x108>
+				status_code = _sercom_get_sync_baud_val(config->baudrate,
+    1158:	6a33      	ldr	r3, [r6, #32]
+    115a:	001f      	movs	r7, r3
+    115c:	b2c0      	uxtb	r0, r0
+    115e:	4b40      	ldr	r3, [pc, #256]	; (1260 <usart_init+0x31c>)
+    1160:	4798      	blx	r3
+    1162:	0001      	movs	r1, r0
+    1164:	220e      	movs	r2, #14
+    1166:	ab06      	add	r3, sp, #24
+    1168:	469c      	mov	ip, r3
+    116a:	4462      	add	r2, ip
+    116c:	0038      	movs	r0, r7
+    116e:	4b3d      	ldr	r3, [pc, #244]	; (1264 <usart_init+0x320>)
+    1170:	4798      	blx	r3
+    1172:	e012      	b.n	119a <usart_init+0x256>
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+    1174:	2308      	movs	r3, #8
+    1176:	9306      	str	r3, [sp, #24]
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+    1178:	2300      	movs	r3, #0
+    117a:	9307      	str	r3, [sp, #28]
+			if (config->use_external_clock) {
+    117c:	2327      	movs	r3, #39	; 0x27
+    117e:	5cf3      	ldrb	r3, [r6, r3]
+    1180:	2b00      	cmp	r3, #0
+    1182:	d00e      	beq.n	11a2 <usart_init+0x25e>
+				status_code =
+    1184:	9b06      	ldr	r3, [sp, #24]
+    1186:	9300      	str	r3, [sp, #0]
+    1188:	9b07      	ldr	r3, [sp, #28]
+    118a:	220e      	movs	r2, #14
+    118c:	a906      	add	r1, sp, #24
+    118e:	468c      	mov	ip, r1
+    1190:	4462      	add	r2, ip
+    1192:	6ab1      	ldr	r1, [r6, #40]	; 0x28
+    1194:	6a30      	ldr	r0, [r6, #32]
+    1196:	4f34      	ldr	r7, [pc, #208]	; (1268 <usart_init+0x324>)
+    1198:	47b8      	blx	r7
+	if (status_code != STATUS_OK) {
+    119a:	2800      	cmp	r0, #0
+    119c:	d000      	beq.n	11a0 <usart_init+0x25c>
+    119e:	e6e4      	b.n	f6a <usart_init+0x26>
+    11a0:	e754      	b.n	104c <usart_init+0x108>
+						_sercom_get_async_baud_val(config->baudrate,
+    11a2:	6a33      	ldr	r3, [r6, #32]
+    11a4:	001f      	movs	r7, r3
+    11a6:	b2c0      	uxtb	r0, r0
+    11a8:	4b2d      	ldr	r3, [pc, #180]	; (1260 <usart_init+0x31c>)
+    11aa:	4798      	blx	r3
+    11ac:	0001      	movs	r1, r0
+				status_code =
+    11ae:	9b06      	ldr	r3, [sp, #24]
+    11b0:	9300      	str	r3, [sp, #0]
+    11b2:	9b07      	ldr	r3, [sp, #28]
+    11b4:	220e      	movs	r2, #14
+    11b6:	a806      	add	r0, sp, #24
+    11b8:	4684      	mov	ip, r0
+    11ba:	4462      	add	r2, ip
+    11bc:	0038      	movs	r0, r7
+    11be:	4f2a      	ldr	r7, [pc, #168]	; (1268 <usart_init+0x324>)
+    11c0:	47b8      	blx	r7
+    11c2:	e7ea      	b.n	119a <usart_init+0x256>
+		if(config->lin_slave_enable) {
+    11c4:	7ef3      	ldrb	r3, [r6, #27]
+    11c6:	2b00      	cmp	r3, #0
+    11c8:	d100      	bne.n	11cc <usart_init+0x288>
+    11ca:	e77d      	b.n	10c8 <usart_init+0x184>
+			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+    11cc:	2380      	movs	r3, #128	; 0x80
+    11ce:	04db      	lsls	r3, r3, #19
+    11d0:	431f      	orrs	r7, r3
+    11d2:	e779      	b.n	10c8 <usart_init+0x184>
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+    11d4:	0020      	movs	r0, r4
+    11d6:	4b25      	ldr	r3, [pc, #148]	; (126c <usart_init+0x328>)
+    11d8:	4798      	blx	r3
+    11da:	e007      	b.n	11ec <usart_init+0x2a8>
+    11dc:	3701      	adds	r7, #1
+	for (uint8_t pad = 0; pad < 4; pad++) {
+    11de:	2f04      	cmp	r7, #4
+    11e0:	d00d      	beq.n	11fe <usart_init+0x2ba>
+    11e2:	b2f9      	uxtb	r1, r7
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+    11e4:	00bb      	lsls	r3, r7, #2
+    11e6:	5998      	ldr	r0, [r3, r6]
+		if (current_pinmux == PINMUX_DEFAULT) {
+    11e8:	2800      	cmp	r0, #0
+    11ea:	d0f3      	beq.n	11d4 <usart_init+0x290>
+		if (current_pinmux != PINMUX_UNUSED) {
+    11ec:	1c43      	adds	r3, r0, #1
+    11ee:	d0f5      	beq.n	11dc <usart_init+0x298>
+			pin_conf.mux_position = current_pinmux & 0xFFFF;
+    11f0:	a90e      	add	r1, sp, #56	; 0x38
+    11f2:	7008      	strb	r0, [r1, #0]
+			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+    11f4:	0c00      	lsrs	r0, r0, #16
+    11f6:	b2c0      	uxtb	r0, r0
+    11f8:	4b1d      	ldr	r3, [pc, #116]	; (1270 <usart_init+0x32c>)
+    11fa:	4798      	blx	r3
+    11fc:	e7ee      	b.n	11dc <usart_init+0x298>
+		module->callback[i]            = NULL;
+    11fe:	2300      	movs	r3, #0
+    1200:	60eb      	str	r3, [r5, #12]
+    1202:	612b      	str	r3, [r5, #16]
+    1204:	616b      	str	r3, [r5, #20]
+    1206:	61ab      	str	r3, [r5, #24]
+    1208:	61eb      	str	r3, [r5, #28]
+    120a:	622b      	str	r3, [r5, #32]
+	module->tx_buffer_ptr              = NULL;
+    120c:	62ab      	str	r3, [r5, #40]	; 0x28
+	module->rx_buffer_ptr              = NULL;
+    120e:	626b      	str	r3, [r5, #36]	; 0x24
+	module->remaining_tx_buffer_length = 0x0000;
+    1210:	2200      	movs	r2, #0
+    1212:	85eb      	strh	r3, [r5, #46]	; 0x2e
+	module->remaining_rx_buffer_length = 0x0000;
+    1214:	85ab      	strh	r3, [r5, #44]	; 0x2c
+	module->callback_reg_mask          = 0x00;
+    1216:	3330      	adds	r3, #48	; 0x30
+    1218:	54ea      	strb	r2, [r5, r3]
+	module->callback_enable_mask       = 0x00;
+    121a:	3301      	adds	r3, #1
+    121c:	54ea      	strb	r2, [r5, r3]
+	module->rx_status                  = STATUS_OK;
+    121e:	3301      	adds	r3, #1
+    1220:	54ea      	strb	r2, [r5, r3]
+	module->tx_status                  = STATUS_OK;
+    1222:	3301      	adds	r3, #1
+    1224:	54ea      	strb	r2, [r5, r3]
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+    1226:	6828      	ldr	r0, [r5, #0]
+    1228:	4b07      	ldr	r3, [pc, #28]	; (1248 <usart_init+0x304>)
+    122a:	4798      	blx	r3
+    122c:	0004      	movs	r4, r0
+	_sercom_set_handler(instance_index, _usart_interrupt_handler);
+    122e:	4911      	ldr	r1, [pc, #68]	; (1274 <usart_init+0x330>)
+    1230:	4b11      	ldr	r3, [pc, #68]	; (1278 <usart_init+0x334>)
+    1232:	4798      	blx	r3
+	_sercom_instances[instance_index] = module;
+    1234:	00a4      	lsls	r4, r4, #2
+    1236:	4b11      	ldr	r3, [pc, #68]	; (127c <usart_init+0x338>)
+    1238:	50e5      	str	r5, [r4, r3]
+	return status_code;
+    123a:	2000      	movs	r0, #0
+    123c:	e695      	b.n	f6a <usart_init+0x26>
+	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+    123e:	2310      	movs	r3, #16
+    1240:	9306      	str	r3, [sp, #24]
+	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+    1242:	2300      	movs	r3, #0
+    1244:	9307      	str	r3, [sp, #28]
+    1246:	e6ec      	b.n	1022 <usart_init+0xde>
+    1248:	00000bed 	.word	0x00000bed
+    124c:	40000400 	.word	0x40000400
+    1250:	00001af5 	.word	0x00001af5
+    1254:	00001a69 	.word	0x00001a69
+    1258:	00000a29 	.word	0x00000a29
+    125c:	41002000 	.word	0x41002000
+    1260:	00001b11 	.word	0x00001b11
+    1264:	0000096d 	.word	0x0000096d
+    1268:	00000995 	.word	0x00000995
+    126c:	00000a75 	.word	0x00000a75
+    1270:	00001bed 	.word	0x00001bed
+    1274:	00001311 	.word	0x00001311
+    1278:	000014a9 	.word	0x000014a9
+    127c:	20000284 	.word	0x20000284
+
+00001280 <usart_write_wait>:
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+    1280:	79c2      	ldrb	r2, [r0, #7]
+		return STATUS_ERR_DENIED;
+    1282:	231c      	movs	r3, #28
+	if (!(module->transmitter_enabled)) {
+    1284:	2a00      	cmp	r2, #0
+    1286:	d101      	bne.n	128c <usart_write_wait+0xc>
+	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+	}
+
+	return STATUS_OK;
+}
+    1288:	0018      	movs	r0, r3
+    128a:	4770      	bx	lr
+	if (module->remaining_tx_buffer_length > 0) {
+    128c:	8dc2      	ldrh	r2, [r0, #46]	; 0x2e
+    128e:	b292      	uxth	r2, r2
+		return STATUS_BUSY;
+    1290:	3b17      	subs	r3, #23
+	if (module->remaining_tx_buffer_length > 0) {
+    1292:	2a00      	cmp	r2, #0
+    1294:	d1f8      	bne.n	1288 <usart_write_wait+0x8>
+	SercomUsart *const usart_hw = &(module->hw->USART);
+    1296:	6802      	ldr	r2, [r0, #0]
+	usart_hw->DATA.reg = tx_data;
+    1298:	8511      	strh	r1, [r2, #40]	; 0x28
+	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+    129a:	2102      	movs	r1, #2
+    129c:	7e13      	ldrb	r3, [r2, #24]
+    129e:	420b      	tst	r3, r1
+    12a0:	d0fc      	beq.n	129c <usart_write_wait+0x1c>
+	return STATUS_OK;
+    12a2:	2300      	movs	r3, #0
+    12a4:	e7f0      	b.n	1288 <usart_write_wait+0x8>
+
+000012a6 <usart_read_wait>:
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+    12a6:	7982      	ldrb	r2, [r0, #6]
+		return STATUS_ERR_DENIED;
+    12a8:	231c      	movs	r3, #28
+	if (!(module->receiver_enabled)) {
+    12aa:	2a00      	cmp	r2, #0
+    12ac:	d101      	bne.n	12b2 <usart_read_wait+0xc>
+
+	/* Read data from USART module */
+	*rx_data = usart_hw->DATA.reg;
+
+	return STATUS_OK;
+}
+    12ae:	0018      	movs	r0, r3
+    12b0:	4770      	bx	lr
+	if (module->remaining_rx_buffer_length > 0) {
+    12b2:	8d82      	ldrh	r2, [r0, #44]	; 0x2c
+    12b4:	b292      	uxth	r2, r2
+		return STATUS_BUSY;
+    12b6:	3b17      	subs	r3, #23
+	if (module->remaining_rx_buffer_length > 0) {
+    12b8:	2a00      	cmp	r2, #0
+    12ba:	d1f8      	bne.n	12ae <usart_read_wait+0x8>
+	SercomUsart *const usart_hw = &(module->hw->USART);
+    12bc:	6802      	ldr	r2, [r0, #0]
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+    12be:	7e10      	ldrb	r0, [r2, #24]
+    12c0:	0740      	lsls	r0, r0, #29
+    12c2:	d5f4      	bpl.n	12ae <usart_read_wait+0x8>
+	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+    12c4:	8b53      	ldrh	r3, [r2, #26]
+    12c6:	b2db      	uxtb	r3, r3
+	if (error_code) {
+    12c8:	0698      	lsls	r0, r3, #26
+    12ca:	d01d      	beq.n	1308 <usart_read_wait+0x62>
+		if (error_code & SERCOM_USART_STATUS_FERR) {
+    12cc:	0798      	lsls	r0, r3, #30
+    12ce:	d503      	bpl.n	12d8 <usart_read_wait+0x32>
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+    12d0:	2302      	movs	r3, #2
+    12d2:	8353      	strh	r3, [r2, #26]
+			return STATUS_ERR_BAD_FORMAT;
+    12d4:	3318      	adds	r3, #24
+    12d6:	e7ea      	b.n	12ae <usart_read_wait+0x8>
+		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+    12d8:	0758      	lsls	r0, r3, #29
+    12da:	d503      	bpl.n	12e4 <usart_read_wait+0x3e>
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+    12dc:	2304      	movs	r3, #4
+    12de:	8353      	strh	r3, [r2, #26]
+			return STATUS_ERR_OVERFLOW;
+    12e0:	331a      	adds	r3, #26
+    12e2:	e7e4      	b.n	12ae <usart_read_wait+0x8>
+		} else if (error_code & SERCOM_USART_STATUS_PERR) {
+    12e4:	07d8      	lsls	r0, r3, #31
+    12e6:	d503      	bpl.n	12f0 <usart_read_wait+0x4a>
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+    12e8:	2301      	movs	r3, #1
+    12ea:	8353      	strh	r3, [r2, #26]
+			return STATUS_ERR_BAD_DATA;
+    12ec:	3312      	adds	r3, #18
+    12ee:	e7de      	b.n	12ae <usart_read_wait+0x8>
+		else if (error_code & SERCOM_USART_STATUS_ISF) {
+    12f0:	06d8      	lsls	r0, r3, #27
+    12f2:	d503      	bpl.n	12fc <usart_read_wait+0x56>
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+    12f4:	2310      	movs	r3, #16
+    12f6:	8353      	strh	r3, [r2, #26]
+			return STATUS_ERR_PROTOCOL;
+    12f8:	3332      	adds	r3, #50	; 0x32
+    12fa:	e7d8      	b.n	12ae <usart_read_wait+0x8>
+		else if (error_code & SERCOM_USART_STATUS_COLL) {
+    12fc:	069b      	lsls	r3, r3, #26
+    12fe:	d503      	bpl.n	1308 <usart_read_wait+0x62>
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+    1300:	2320      	movs	r3, #32
+    1302:	8353      	strh	r3, [r2, #26]
+			return STATUS_ERR_PACKET_COLLISION;
+    1304:	3321      	adds	r3, #33	; 0x21
+    1306:	e7d2      	b.n	12ae <usart_read_wait+0x8>
+	*rx_data = usart_hw->DATA.reg;
+    1308:	8d13      	ldrh	r3, [r2, #40]	; 0x28
+    130a:	800b      	strh	r3, [r1, #0]
+	return STATUS_OK;
+    130c:	2300      	movs	r3, #0
+    130e:	e7ce      	b.n	12ae <usart_read_wait+0x8>
+
+00001310 <_usart_interrupt_handler>:
+ * \param[in]  instance  ID of the SERCOM instance calling the interrupt
+ *                       handler.
+ */
+void _usart_interrupt_handler(
+		uint8_t instance)
+{
+    1310:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+	uint16_t callback_status;
+	uint8_t error_code;
+
+
+	/* Get device instance from the look-up table */
+	struct usart_module *module
+    1312:	0080      	lsls	r0, r0, #2
+    1314:	4b62      	ldr	r3, [pc, #392]	; (14a0 <_usart_interrupt_handler+0x190>)
+    1316:	58c5      	ldr	r5, [r0, r3]
+		= (struct usart_module *)_sercom_instances[instance];
+
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw
+		= &(module->hw->USART);
+    1318:	682c      	ldr	r4, [r5, #0]
+	return (usart_hw->SYNCBUSY.reg);
+    131a:	69e3      	ldr	r3, [r4, #28]
+	while (usart_is_syncing(module)) {
+    131c:	2b00      	cmp	r3, #0
+    131e:	d1fc      	bne.n	131a <_usart_interrupt_handler+0xa>
+
+	/* Wait for the synchronization to complete */
+	_usart_wait_for_sync(module);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+    1320:	7e23      	ldrb	r3, [r4, #24]
+	interrupt_status &= usart_hw->INTENSET.reg;
+    1322:	7da6      	ldrb	r6, [r4, #22]
+    1324:	401e      	ands	r6, r3
+	callback_status = module->callback_reg_mask &
+    1326:	2330      	movs	r3, #48	; 0x30
+    1328:	5ceb      	ldrb	r3, [r5, r3]
+    132a:	2231      	movs	r2, #49	; 0x31
+    132c:	5caf      	ldrb	r7, [r5, r2]
+    132e:	401f      	ands	r7, r3
+			module->callback_enable_mask;
+
+	/* Check if a DATA READY interrupt has occurred,
+	 * and if there is more to transfer */
+	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+    1330:	07f3      	lsls	r3, r6, #31
+    1332:	d522      	bpl.n	137a <_usart_interrupt_handler+0x6a>
+		if (module->remaining_tx_buffer_length) {
+    1334:	8deb      	ldrh	r3, [r5, #46]	; 0x2e
+    1336:	b29b      	uxth	r3, r3
+    1338:	2b00      	cmp	r3, #0
+    133a:	d01c      	beq.n	1376 <_usart_interrupt_handler+0x66>
+			/* Write value will be at least 8-bits long */
+			uint16_t data_to_send = *(module->tx_buffer_ptr);
+    133c:	6aaa      	ldr	r2, [r5, #40]	; 0x28
+    133e:	7813      	ldrb	r3, [r2, #0]
+    1340:	b2db      	uxtb	r3, r3
+			/* Increment 8-bit pointer */
+			(module->tx_buffer_ptr)++;
+    1342:	1c51      	adds	r1, r2, #1
+    1344:	62a9      	str	r1, [r5, #40]	; 0x28
+
+			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+    1346:	7969      	ldrb	r1, [r5, #5]
+    1348:	2901      	cmp	r1, #1
+    134a:	d00e      	beq.n	136a <_usart_interrupt_handler+0x5a>
+			uint16_t data_to_send = *(module->tx_buffer_ptr);
+    134c:	b29b      	uxth	r3, r3
+				data_to_send |= (*(module->tx_buffer_ptr) << 8);
+				/* Increment 8-bit pointer */
+				(module->tx_buffer_ptr)++;
+			}
+			/* Write the data to send */
+			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+    134e:	05db      	lsls	r3, r3, #23
+    1350:	0ddb      	lsrs	r3, r3, #23
+    1352:	8523      	strh	r3, [r4, #40]	; 0x28
+
+			if (--(module->remaining_tx_buffer_length) == 0) {
+    1354:	8deb      	ldrh	r3, [r5, #46]	; 0x2e
+    1356:	3b01      	subs	r3, #1
+    1358:	b29b      	uxth	r3, r3
+    135a:	85eb      	strh	r3, [r5, #46]	; 0x2e
+    135c:	2b00      	cmp	r3, #0
+    135e:	d10c      	bne.n	137a <_usart_interrupt_handler+0x6a>
+				/* Disable the Data Register Empty Interrupt */
+				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+    1360:	3301      	adds	r3, #1
+    1362:	7523      	strb	r3, [r4, #20]
+				/* Enable Transmission Complete interrupt */
+				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+    1364:	3301      	adds	r3, #1
+    1366:	75a3      	strb	r3, [r4, #22]
+    1368:	e007      	b.n	137a <_usart_interrupt_handler+0x6a>
+				data_to_send |= (*(module->tx_buffer_ptr) << 8);
+    136a:	7851      	ldrb	r1, [r2, #1]
+    136c:	0209      	lsls	r1, r1, #8
+    136e:	430b      	orrs	r3, r1
+				(module->tx_buffer_ptr)++;
+    1370:	3202      	adds	r2, #2
+    1372:	62aa      	str	r2, [r5, #40]	; 0x28
+    1374:	e7eb      	b.n	134e <_usart_interrupt_handler+0x3e>
+
+			}
+		} else {
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+    1376:	2301      	movs	r3, #1
+    1378:	7523      	strb	r3, [r4, #20]
+		}
+	}
+
+	/* Check if the Transmission Complete interrupt has occurred and
+	 * that the transmit buffer is empty */
+	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+    137a:	07b3      	lsls	r3, r6, #30
+    137c:	d506      	bpl.n	138c <_usart_interrupt_handler+0x7c>
+
+		/* Disable TX Complete Interrupt, and set STATUS_OK */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+    137e:	2302      	movs	r3, #2
+    1380:	7523      	strb	r3, [r4, #20]
+		module->tx_status = STATUS_OK;
+    1382:	2200      	movs	r2, #0
+    1384:	3331      	adds	r3, #49	; 0x31
+    1386:	54ea      	strb	r2, [r5, r3]
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
+    1388:	07fb      	lsls	r3, r7, #31
+    138a:	d41a      	bmi.n	13c2 <_usart_interrupt_handler+0xb2>
+		}
+	}
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+    138c:	0773      	lsls	r3, r6, #29
+    138e:	d565      	bpl.n	145c <_usart_interrupt_handler+0x14c>
+
+		if (module->remaining_rx_buffer_length) {
+    1390:	8dab      	ldrh	r3, [r5, #44]	; 0x2c
+    1392:	b29b      	uxth	r3, r3
+    1394:	2b00      	cmp	r3, #0
+    1396:	d05f      	beq.n	1458 <_usart_interrupt_handler+0x148>
+			/* Read out the status code and mask away all but the 4 LSBs*/
+			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+    1398:	8b63      	ldrh	r3, [r4, #26]
+    139a:	b2db      	uxtb	r3, r3
+#if !SAMD20
+			/* CTS status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_CTS) {
+    139c:	071a      	lsls	r2, r3, #28
+    139e:	d414      	bmi.n	13ca <_usart_interrupt_handler+0xba>
+			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+    13a0:	223f      	movs	r2, #63	; 0x3f
+    13a2:	4013      	ands	r3, r2
+			if(error_code & SERCOM_USART_STATUS_TXE) {
+				error_code &= ~SERCOM_USART_STATUS_TXE;
+			}
+#endif
+			/* Check if an error has occurred during the receiving */
+			if (error_code) {
+    13a4:	2b00      	cmp	r3, #0
+    13a6:	d034      	beq.n	1412 <_usart_interrupt_handler+0x102>
+				/* Check which error occurred */
+				if (error_code & SERCOM_USART_STATUS_FERR) {
+    13a8:	079a      	lsls	r2, r3, #30
+    13aa:	d511      	bpl.n	13d0 <_usart_interrupt_handler+0xc0>
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_FORMAT;
+    13ac:	221a      	movs	r2, #26
+    13ae:	2332      	movs	r3, #50	; 0x32
+    13b0:	54ea      	strb	r2, [r5, r3]
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+    13b2:	3b30      	subs	r3, #48	; 0x30
+    13b4:	8363      	strh	r3, [r4, #26]
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+				}
+#endif
+
+				/* Run callback if registered and enabled */
+				if (callback_status
+    13b6:	077b      	lsls	r3, r7, #29
+    13b8:	d550      	bpl.n	145c <_usart_interrupt_handler+0x14c>
+						& (1 << USART_CALLBACK_ERROR)) {
+					(*(module->callback[USART_CALLBACK_ERROR]))(module);
+    13ba:	0028      	movs	r0, r5
+    13bc:	696b      	ldr	r3, [r5, #20]
+    13be:	4798      	blx	r3
+    13c0:	e04c      	b.n	145c <_usart_interrupt_handler+0x14c>
+			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+    13c2:	0028      	movs	r0, r5
+    13c4:	68eb      	ldr	r3, [r5, #12]
+    13c6:	4798      	blx	r3
+    13c8:	e7e0      	b.n	138c <_usart_interrupt_handler+0x7c>
+				error_code &= ~SERCOM_USART_STATUS_CTS;
+    13ca:	2237      	movs	r2, #55	; 0x37
+    13cc:	4013      	ands	r3, r2
+    13ce:	e7e9      	b.n	13a4 <_usart_interrupt_handler+0x94>
+				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+    13d0:	075a      	lsls	r2, r3, #29
+    13d2:	d505      	bpl.n	13e0 <_usart_interrupt_handler+0xd0>
+					module->rx_status = STATUS_ERR_OVERFLOW;
+    13d4:	221e      	movs	r2, #30
+    13d6:	2332      	movs	r3, #50	; 0x32
+    13d8:	54ea      	strb	r2, [r5, r3]
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+    13da:	3b2e      	subs	r3, #46	; 0x2e
+    13dc:	8363      	strh	r3, [r4, #26]
+    13de:	e7ea      	b.n	13b6 <_usart_interrupt_handler+0xa6>
+				} else if (error_code & SERCOM_USART_STATUS_PERR) {
+    13e0:	07da      	lsls	r2, r3, #31
+    13e2:	d505      	bpl.n	13f0 <_usart_interrupt_handler+0xe0>
+					module->rx_status = STATUS_ERR_BAD_DATA;
+    13e4:	2213      	movs	r2, #19
+    13e6:	2332      	movs	r3, #50	; 0x32
+    13e8:	54ea      	strb	r2, [r5, r3]
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+    13ea:	3b31      	subs	r3, #49	; 0x31
+    13ec:	8363      	strh	r3, [r4, #26]
+    13ee:	e7e2      	b.n	13b6 <_usart_interrupt_handler+0xa6>
+				else if (error_code & SERCOM_USART_STATUS_ISF) {
+    13f0:	06da      	lsls	r2, r3, #27
+    13f2:	d505      	bpl.n	1400 <_usart_interrupt_handler+0xf0>
+					module->rx_status = STATUS_ERR_PROTOCOL;
+    13f4:	2242      	movs	r2, #66	; 0x42
+    13f6:	2332      	movs	r3, #50	; 0x32
+    13f8:	54ea      	strb	r2, [r5, r3]
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+    13fa:	3b22      	subs	r3, #34	; 0x22
+    13fc:	8363      	strh	r3, [r4, #26]
+    13fe:	e7da      	b.n	13b6 <_usart_interrupt_handler+0xa6>
+				else if (error_code & SERCOM_USART_STATUS_COLL) {
+    1400:	2220      	movs	r2, #32
+    1402:	421a      	tst	r2, r3
+    1404:	d0d7      	beq.n	13b6 <_usart_interrupt_handler+0xa6>
+					module->rx_status = STATUS_ERR_PACKET_COLLISION;
+    1406:	3221      	adds	r2, #33	; 0x21
+    1408:	2332      	movs	r3, #50	; 0x32
+    140a:	54ea      	strb	r2, [r5, r3]
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+    140c:	3b12      	subs	r3, #18
+    140e:	8363      	strh	r3, [r4, #26]
+    1410:	e7d1      	b.n	13b6 <_usart_interrupt_handler+0xa6>
+
+			} else {
+
+				/* Read current packet from DATA register,
+				 * increment buffer pointer and decrement buffer length */
+				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+    1412:	8d23      	ldrh	r3, [r4, #40]	; 0x28
+    1414:	05db      	lsls	r3, r3, #23
+    1416:	0ddb      	lsrs	r3, r3, #23
+
+				/* Read value will be at least 8-bits long */
+				*(module->rx_buffer_ptr) = received_data;
+    1418:	b2da      	uxtb	r2, r3
+    141a:	6a69      	ldr	r1, [r5, #36]	; 0x24
+    141c:	700a      	strb	r2, [r1, #0]
+				/* Increment 8-bit pointer */
+				module->rx_buffer_ptr += 1;
+    141e:	6a6a      	ldr	r2, [r5, #36]	; 0x24
+    1420:	1c51      	adds	r1, r2, #1
+    1422:	6269      	str	r1, [r5, #36]	; 0x24
+
+				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+    1424:	7969      	ldrb	r1, [r5, #5]
+    1426:	2901      	cmp	r1, #1
+    1428:	d010      	beq.n	144c <_usart_interrupt_handler+0x13c>
+					/* Increment 8-bit pointer */
+					module->rx_buffer_ptr += 1;
+				}
+
+				/* Check if the last character have been received */
+				if(--(module->remaining_rx_buffer_length) == 0) {
+    142a:	8dab      	ldrh	r3, [r5, #44]	; 0x2c
+    142c:	3b01      	subs	r3, #1
+    142e:	b29b      	uxth	r3, r3
+    1430:	85ab      	strh	r3, [r5, #44]	; 0x2c
+    1432:	2b00      	cmp	r3, #0
+    1434:	d112      	bne.n	145c <_usart_interrupt_handler+0x14c>
+					/* Disable RX Complete Interrupt,
+					 * and set STATUS_OK */
+					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+    1436:	3304      	adds	r3, #4
+    1438:	7523      	strb	r3, [r4, #20]
+					module->rx_status = STATUS_OK;
+    143a:	2200      	movs	r2, #0
+    143c:	332e      	adds	r3, #46	; 0x2e
+    143e:	54ea      	strb	r2, [r5, r3]
+
+					/* Run callback if registered and enabled */
+					if (callback_status
+    1440:	07bb      	lsls	r3, r7, #30
+    1442:	d50b      	bpl.n	145c <_usart_interrupt_handler+0x14c>
+							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
+						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+    1444:	0028      	movs	r0, r5
+    1446:	692b      	ldr	r3, [r5, #16]
+    1448:	4798      	blx	r3
+    144a:	e007      	b.n	145c <_usart_interrupt_handler+0x14c>
+					*(module->rx_buffer_ptr) = (received_data >> 8);
+    144c:	0a1b      	lsrs	r3, r3, #8
+    144e:	7053      	strb	r3, [r2, #1]
+					module->rx_buffer_ptr += 1;
+    1450:	6a6b      	ldr	r3, [r5, #36]	; 0x24
+    1452:	3301      	adds	r3, #1
+    1454:	626b      	str	r3, [r5, #36]	; 0x24
+    1456:	e7e8      	b.n	142a <_usart_interrupt_handler+0x11a>
+					}
+				}
+			}
+		} else {
+			/* This should not happen. Disable Receive Complete interrupt. */
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+    1458:	2304      	movs	r3, #4
+    145a:	7523      	strb	r3, [r4, #20]
+		}
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+    145c:	06f3      	lsls	r3, r6, #27
+    145e:	d504      	bpl.n	146a <_usart_interrupt_handler+0x15a>
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+    1460:	2310      	movs	r3, #16
+    1462:	7523      	strb	r3, [r4, #20]
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+    1464:	7623      	strb	r3, [r4, #24]
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
+    1466:	06fb      	lsls	r3, r7, #27
+    1468:	d40e      	bmi.n	1488 <_usart_interrupt_handler+0x178>
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+    146a:	06b3      	lsls	r3, r6, #26
+    146c:	d504      	bpl.n	1478 <_usart_interrupt_handler+0x168>
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+    146e:	2320      	movs	r3, #32
+    1470:	7523      	strb	r3, [r4, #20]
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+    1472:	7623      	strb	r3, [r4, #24]
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
+    1474:	073b      	lsls	r3, r7, #28
+    1476:	d40b      	bmi.n	1490 <_usart_interrupt_handler+0x180>
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+    1478:	0733      	lsls	r3, r6, #28
+    147a:	d504      	bpl.n	1486 <_usart_interrupt_handler+0x176>
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+    147c:	2308      	movs	r3, #8
+    147e:	7523      	strb	r3, [r4, #20]
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+    1480:	7623      	strb	r3, [r4, #24]
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
+    1482:	06bb      	lsls	r3, r7, #26
+    1484:	d408      	bmi.n	1498 <_usart_interrupt_handler+0x188>
+			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+		}
+	}
+#endif
+}
+    1486:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+    1488:	0028      	movs	r0, r5
+    148a:	69eb      	ldr	r3, [r5, #28]
+    148c:	4798      	blx	r3
+    148e:	e7ec      	b.n	146a <_usart_interrupt_handler+0x15a>
+			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+    1490:	0028      	movs	r0, r5
+    1492:	69ab      	ldr	r3, [r5, #24]
+    1494:	4798      	blx	r3
+    1496:	e7ef      	b.n	1478 <_usart_interrupt_handler+0x168>
+			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+    1498:	6a2b      	ldr	r3, [r5, #32]
+    149a:	0028      	movs	r0, r5
+    149c:	4798      	blx	r3
+}
+    149e:	e7f2      	b.n	1486 <_usart_interrupt_handler+0x176>
+    14a0:	20000284 	.word	0x20000284
+
+000014a4 <_sercom_default_handler>:
+ */
+static void _sercom_default_handler(
+		const uint8_t instance)
+{
+	Assert(false);
+}
+    14a4:	4770      	bx	lr
+	...
+
+000014a8 <_sercom_set_handler>:
+ * \param[in]  interrupt_handler  Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler)
+{
+    14a8:	b5f0      	push	{r4, r5, r6, r7, lr}
+	/* Initialize handlers with default handler and device instances with 0 */
+	if (_handler_table_initialized == false) {
+    14aa:	4b0a      	ldr	r3, [pc, #40]	; (14d4 <_sercom_set_handler+0x2c>)
+    14ac:	781b      	ldrb	r3, [r3, #0]
+    14ae:	2b00      	cmp	r3, #0
+    14b0:	d10c      	bne.n	14cc <_sercom_set_handler+0x24>
+		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
+    14b2:	4f09      	ldr	r7, [pc, #36]	; (14d8 <_sercom_set_handler+0x30>)
+    14b4:	4e09      	ldr	r6, [pc, #36]	; (14dc <_sercom_set_handler+0x34>)
+			_sercom_instances[i] = NULL;
+    14b6:	4d0a      	ldr	r5, [pc, #40]	; (14e0 <_sercom_set_handler+0x38>)
+    14b8:	2400      	movs	r4, #0
+			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
+    14ba:	51de      	str	r6, [r3, r7]
+			_sercom_instances[i] = NULL;
+    14bc:	195a      	adds	r2, r3, r5
+    14be:	6014      	str	r4, [r2, #0]
+    14c0:	3304      	adds	r3, #4
+		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+    14c2:	2b18      	cmp	r3, #24
+    14c4:	d1f9      	bne.n	14ba <_sercom_set_handler+0x12>
+		}
+
+		_handler_table_initialized = true;
+    14c6:	2201      	movs	r2, #1
+    14c8:	4b02      	ldr	r3, [pc, #8]	; (14d4 <_sercom_set_handler+0x2c>)
+    14ca:	701a      	strb	r2, [r3, #0]
+	}
+
+	/* Save interrupt handler */
+	_sercom_interrupt_handlers[instance] = interrupt_handler;
+    14cc:	0080      	lsls	r0, r0, #2
+    14ce:	4b02      	ldr	r3, [pc, #8]	; (14d8 <_sercom_set_handler+0x30>)
+    14d0:	50c1      	str	r1, [r0, r3]
+}
+    14d2:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    14d4:	20000190 	.word	0x20000190
+    14d8:	20000194 	.word	0x20000194
+    14dc:	000014a5 	.word	0x000014a5
+    14e0:	20000284 	.word	0x20000284
+
+000014e4 <_sercom_get_interrupt_vector>:
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance)
+{
+    14e4:	b500      	push	{lr}
+    14e6:	b083      	sub	sp, #12
+	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+    14e8:	2309      	movs	r3, #9
+    14ea:	466a      	mov	r2, sp
+    14ec:	7013      	strb	r3, [r2, #0]
+    14ee:	3301      	adds	r3, #1
+    14f0:	7053      	strb	r3, [r2, #1]
+    14f2:	3301      	adds	r3, #1
+    14f4:	7093      	strb	r3, [r2, #2]
+    14f6:	3301      	adds	r3, #1
+    14f8:	70d3      	strb	r3, [r2, #3]
+    14fa:	3301      	adds	r3, #1
+    14fc:	7113      	strb	r3, [r2, #4]
+    14fe:	3301      	adds	r3, #1
+    1500:	7153      	strb	r3, [r2, #5]
+		{
+			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+		};
+
+	/* Retrieve the index of the SERCOM being requested */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+    1502:	4b03      	ldr	r3, [pc, #12]	; (1510 <_sercom_get_interrupt_vector+0x2c>)
+    1504:	4798      	blx	r3
+
+	/* Get the vector number from the lookup table for the requested SERCOM */
+	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+    1506:	466b      	mov	r3, sp
+    1508:	5618      	ldrsb	r0, [r3, r0]
+}
+    150a:	b003      	add	sp, #12
+    150c:	bd00      	pop	{pc}
+    150e:	46c0      	nop			; (mov r8, r8)
+    1510:	00000bed 	.word	0x00000bed
+
+00001514 <SERCOM0_Handler>:
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
+    1514:	b510      	push	{r4, lr}
+    1516:	4b02      	ldr	r3, [pc, #8]	; (1520 <SERCOM0_Handler+0xc>)
+    1518:	681b      	ldr	r3, [r3, #0]
+    151a:	2000      	movs	r0, #0
+    151c:	4798      	blx	r3
+    151e:	bd10      	pop	{r4, pc}
+    1520:	20000194 	.word	0x20000194
+
+00001524 <SERCOM1_Handler>:
+    1524:	b510      	push	{r4, lr}
+    1526:	4b02      	ldr	r3, [pc, #8]	; (1530 <SERCOM1_Handler+0xc>)
+    1528:	685b      	ldr	r3, [r3, #4]
+    152a:	2001      	movs	r0, #1
+    152c:	4798      	blx	r3
+    152e:	bd10      	pop	{r4, pc}
+    1530:	20000194 	.word	0x20000194
+
+00001534 <SERCOM2_Handler>:
+    1534:	b510      	push	{r4, lr}
+    1536:	4b02      	ldr	r3, [pc, #8]	; (1540 <SERCOM2_Handler+0xc>)
+    1538:	689b      	ldr	r3, [r3, #8]
+    153a:	2002      	movs	r0, #2
+    153c:	4798      	blx	r3
+    153e:	bd10      	pop	{r4, pc}
+    1540:	20000194 	.word	0x20000194
+
+00001544 <SERCOM3_Handler>:
+    1544:	b510      	push	{r4, lr}
+    1546:	4b02      	ldr	r3, [pc, #8]	; (1550 <SERCOM3_Handler+0xc>)
+    1548:	68db      	ldr	r3, [r3, #12]
+    154a:	2003      	movs	r0, #3
+    154c:	4798      	blx	r3
+    154e:	bd10      	pop	{r4, pc}
+    1550:	20000194 	.word	0x20000194
+
+00001554 <SERCOM4_Handler>:
+    1554:	b510      	push	{r4, lr}
+    1556:	4b02      	ldr	r3, [pc, #8]	; (1560 <SERCOM4_Handler+0xc>)
+    1558:	691b      	ldr	r3, [r3, #16]
+    155a:	2004      	movs	r0, #4
+    155c:	4798      	blx	r3
+    155e:	bd10      	pop	{r4, pc}
+    1560:	20000194 	.word	0x20000194
+
+00001564 <SERCOM5_Handler>:
+    1564:	b510      	push	{r4, lr}
+    1566:	4b02      	ldr	r3, [pc, #8]	; (1570 <SERCOM5_Handler+0xc>)
+    1568:	695b      	ldr	r3, [r3, #20]
+    156a:	2005      	movs	r0, #5
+    156c:	4798      	blx	r3
+    156e:	bd10      	pop	{r4, pc}
+    1570:	20000194 	.word	0x20000194
+
+00001574 <delay_init>:
+ *
+ * This must be called during start up to initialize the delay routine with
+ * the current used main clock. It must run any time the main CPU clock is changed.
+ */
+void delay_init(void)
+{
+    1574:	b570      	push	{r4, r5, r6, lr}
+	cycles_per_ms = system_gclk_gen_get_hz(0);
+    1576:	2000      	movs	r0, #0
+    1578:	4b08      	ldr	r3, [pc, #32]	; (159c <delay_init+0x28>)
+    157a:	4798      	blx	r3
+    157c:	0005      	movs	r5, r0
+	cycles_per_ms /= 1000;
+    157e:	4c08      	ldr	r4, [pc, #32]	; (15a0 <delay_init+0x2c>)
+    1580:	21fa      	movs	r1, #250	; 0xfa
+    1582:	0089      	lsls	r1, r1, #2
+    1584:	47a0      	blx	r4
+    1586:	4b07      	ldr	r3, [pc, #28]	; (15a4 <delay_init+0x30>)
+    1588:	6018      	str	r0, [r3, #0]
+	cycles_per_us = cycles_per_ms / 1000;
+    158a:	4907      	ldr	r1, [pc, #28]	; (15a8 <delay_init+0x34>)
+    158c:	0028      	movs	r0, r5
+    158e:	47a0      	blx	r4
+    1590:	4b06      	ldr	r3, [pc, #24]	; (15ac <delay_init+0x38>)
+    1592:	6018      	str	r0, [r3, #0]
+
+	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+    1594:	2205      	movs	r2, #5
+    1596:	4b06      	ldr	r3, [pc, #24]	; (15b0 <delay_init+0x3c>)
+    1598:	601a      	str	r2, [r3, #0]
+}
+    159a:	bd70      	pop	{r4, r5, r6, pc}
+    159c:	000019dd 	.word	0x000019dd
+    15a0:	00001df5 	.word	0x00001df5
+    15a4:	2000000c 	.word	0x2000000c
+    15a8:	000f4240 	.word	0x000f4240
+    15ac:	20000010 	.word	0x20000010
+    15b0:	e000e010 	.word	0xe000e010
+
+000015b4 <delay_cycles_ms>:
+ *
+ * \param n  Number of milliseconds to wait
+ */
+void delay_cycles_ms(
+		uint32_t n)
+{
+    15b4:	b530      	push	{r4, r5, lr}
+	while (n--) {
+		/* Devide up to blocks of 1ms */
+		delay_cycles(cycles_per_ms);
+    15b6:	4b08      	ldr	r3, [pc, #32]	; (15d8 <delay_cycles_ms+0x24>)
+    15b8:	681c      	ldr	r4, [r3, #0]
+ */
+static inline void delay_cycles(
+		const uint32_t n)
+{
+	if (n > 0) {
+		SysTick->LOAD = n;
+    15ba:	4a08      	ldr	r2, [pc, #32]	; (15dc <delay_cycles_ms+0x28>)
+		SysTick->VAL = 0;
+    15bc:	2500      	movs	r5, #0
+
+		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
+    15be:	2180      	movs	r1, #128	; 0x80
+    15c0:	0249      	lsls	r1, r1, #9
+	while (n--) {
+    15c2:	3801      	subs	r0, #1
+    15c4:	d307      	bcc.n	15d6 <delay_cycles_ms+0x22>
+	if (n > 0) {
+    15c6:	2c00      	cmp	r4, #0
+    15c8:	d0fb      	beq.n	15c2 <delay_cycles_ms+0xe>
+		SysTick->LOAD = n;
+    15ca:	6054      	str	r4, [r2, #4]
+		SysTick->VAL = 0;
+    15cc:	6095      	str	r5, [r2, #8]
+		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
+    15ce:	6813      	ldr	r3, [r2, #0]
+    15d0:	420b      	tst	r3, r1
+    15d2:	d0fc      	beq.n	15ce <delay_cycles_ms+0x1a>
+    15d4:	e7f5      	b.n	15c2 <delay_cycles_ms+0xe>
+	}
+}
+    15d6:	bd30      	pop	{r4, r5, pc}
+    15d8:	2000000c 	.word	0x2000000c
+    15dc:	e000e010 	.word	0xe000e010
+
+000015e0 <cpu_irq_enter_critical>:
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+	if (cpu_irq_critical_section_counter == 0) {
+    15e0:	4b0c      	ldr	r3, [pc, #48]	; (1614 <cpu_irq_enter_critical+0x34>)
+    15e2:	681b      	ldr	r3, [r3, #0]
+    15e4:	2b00      	cmp	r3, #0
+    15e6:	d106      	bne.n	15f6 <cpu_irq_enter_critical+0x16>
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+    15e8:	f3ef 8310 	mrs	r3, PRIMASK
+		if (cpu_irq_is_enabled()) {
+    15ec:	2b00      	cmp	r3, #0
+    15ee:	d007      	beq.n	1600 <cpu_irq_enter_critical+0x20>
+			cpu_irq_disable();
+			cpu_irq_prev_interrupt_state = true;
+		} else {
+			/* Make sure the to save the prev state as false */
+			cpu_irq_prev_interrupt_state = false;
+    15f0:	2200      	movs	r2, #0
+    15f2:	4b09      	ldr	r3, [pc, #36]	; (1618 <cpu_irq_enter_critical+0x38>)
+    15f4:	701a      	strb	r2, [r3, #0]
+		}
+
+	}
+
+	cpu_irq_critical_section_counter++;
+    15f6:	4a07      	ldr	r2, [pc, #28]	; (1614 <cpu_irq_enter_critical+0x34>)
+    15f8:	6813      	ldr	r3, [r2, #0]
+    15fa:	3301      	adds	r3, #1
+    15fc:	6013      	str	r3, [r2, #0]
+}
+    15fe:	4770      	bx	lr
+  __ASM volatile ("cpsid i" : : : "memory");
+    1600:	b672      	cpsid	i
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+    1602:	f3bf 8f5f 	dmb	sy
+			cpu_irq_disable();
+    1606:	2200      	movs	r2, #0
+    1608:	4b04      	ldr	r3, [pc, #16]	; (161c <cpu_irq_enter_critical+0x3c>)
+    160a:	701a      	strb	r2, [r3, #0]
+			cpu_irq_prev_interrupt_state = true;
+    160c:	3201      	adds	r2, #1
+    160e:	4b02      	ldr	r3, [pc, #8]	; (1618 <cpu_irq_enter_critical+0x38>)
+    1610:	701a      	strb	r2, [r3, #0]
+    1612:	e7f0      	b.n	15f6 <cpu_irq_enter_critical+0x16>
+    1614:	200001ac 	.word	0x200001ac
+    1618:	200001b0 	.word	0x200001b0
+    161c:	20000014 	.word	0x20000014
+
+00001620 <cpu_irq_leave_critical>:
+void cpu_irq_leave_critical(void)
+{
+	/* Check if the user is trying to leave a critical section when not in a critical section */
+	Assert(cpu_irq_critical_section_counter > 0);
+
+	cpu_irq_critical_section_counter--;
+    1620:	4b08      	ldr	r3, [pc, #32]	; (1644 <cpu_irq_leave_critical+0x24>)
+    1622:	681a      	ldr	r2, [r3, #0]
+    1624:	3a01      	subs	r2, #1
+    1626:	601a      	str	r2, [r3, #0]
+
+	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+	   was enabled when entering critical state */
+	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+    1628:	681b      	ldr	r3, [r3, #0]
+    162a:	2b00      	cmp	r3, #0
+    162c:	d109      	bne.n	1642 <cpu_irq_leave_critical+0x22>
+    162e:	4b06      	ldr	r3, [pc, #24]	; (1648 <cpu_irq_leave_critical+0x28>)
+    1630:	781b      	ldrb	r3, [r3, #0]
+    1632:	2b00      	cmp	r3, #0
+    1634:	d005      	beq.n	1642 <cpu_irq_leave_critical+0x22>
+		cpu_irq_enable();
+    1636:	2201      	movs	r2, #1
+    1638:	4b04      	ldr	r3, [pc, #16]	; (164c <cpu_irq_leave_critical+0x2c>)
+    163a:	701a      	strb	r2, [r3, #0]
+    163c:	f3bf 8f5f 	dmb	sy
+  __ASM volatile ("cpsie i" : : : "memory");
+    1640:	b662      	cpsie	i
+	}
+}
+    1642:	4770      	bx	lr
+    1644:	200001ac 	.word	0x200001ac
+    1648:	200001b0 	.word	0x200001b0
+    164c:	20000014 	.word	0x20000014
+
+00001650 <system_board_init>:
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+    1650:	b5f0      	push	{r4, r5, r6, r7, lr}
+    1652:	b083      	sub	sp, #12
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->direction  = PORT_PIN_DIR_INPUT;
+	config->input_pull = PORT_PIN_PULL_UP;
+    1654:	ac01      	add	r4, sp, #4
+    1656:	2501      	movs	r5, #1
+    1658:	7065      	strb	r5, [r4, #1]
+	config->powersave  = false;
+    165a:	2700      	movs	r7, #0
+    165c:	70a7      	strb	r7, [r4, #2]
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    165e:	7025      	strb	r5, [r4, #0]
+	port_pin_set_config(LED_0_PIN, &pin_conf);
+    1660:	0021      	movs	r1, r4
+    1662:	203e      	movs	r0, #62	; 0x3e
+    1664:	4e06      	ldr	r6, [pc, #24]	; (1680 <system_board_init+0x30>)
+    1666:	47b0      	blx	r6
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Set the pin to high or low atomically based on the requested level */
+	if (level) {
+		port_base->OUTSET.reg = pin_mask;
+    1668:	2280      	movs	r2, #128	; 0x80
+    166a:	05d2      	lsls	r2, r2, #23
+    166c:	4b05      	ldr	r3, [pc, #20]	; (1684 <system_board_init+0x34>)
+    166e:	619a      	str	r2, [r3, #24]
+	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+	/* Set buttons as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    1670:	7027      	strb	r7, [r4, #0]
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+    1672:	7065      	strb	r5, [r4, #1]
+	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+    1674:	0021      	movs	r1, r4
+    1676:	200f      	movs	r0, #15
+    1678:	47b0      	blx	r6
+	port_pin_set_output_level(AT86RFX_RST_PIN, true);
+	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+#endif	
+}
+    167a:	b003      	add	sp, #12
+    167c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    167e:	46c0      	nop			; (mov r8, r8)
+    1680:	00001689 	.word	0x00001689
+    1684:	41004480 	.word	0x41004480
+
+00001688 <port_pin_set_config>:
+ *  \param[in] config    Configuration settings for the pin
+ */
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config)
+{
+    1688:	b500      	push	{lr}
+    168a:	b083      	sub	sp, #12
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+    168c:	ab01      	add	r3, sp, #4
+    168e:	2280      	movs	r2, #128	; 0x80
+    1690:	701a      	strb	r2, [r3, #0]
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+    1692:	780a      	ldrb	r2, [r1, #0]
+    1694:	705a      	strb	r2, [r3, #1]
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+    1696:	784a      	ldrb	r2, [r1, #1]
+    1698:	709a      	strb	r2, [r3, #2]
+	pinmux_config.powersave    = config->powersave;
+    169a:	788a      	ldrb	r2, [r1, #2]
+    169c:	70da      	strb	r2, [r3, #3]
+
+	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+    169e:	0019      	movs	r1, r3
+    16a0:	4b01      	ldr	r3, [pc, #4]	; (16a8 <port_pin_set_config+0x20>)
+    16a2:	4798      	blx	r3
+}
+    16a4:	b003      	add	sp, #12
+    16a6:	bd00      	pop	{pc}
+    16a8:	00001bed 	.word	0x00001bed
+
+000016ac <system_clock_source_get_hz>:
+ *
+ * \returns Frequency of the given clock source, in Hz.
+ */
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clock_source)
+{
+    16ac:	b510      	push	{r4, lr}
+	switch (clock_source) {
+    16ae:	2808      	cmp	r0, #8
+    16b0:	d803      	bhi.n	16ba <system_clock_source_get_hz+0xe>
+    16b2:	0080      	lsls	r0, r0, #2
+    16b4:	4b1c      	ldr	r3, [pc, #112]	; (1728 <system_clock_source_get_hz+0x7c>)
+    16b6:	581b      	ldr	r3, [r3, r0]
+    16b8:	469f      	mov	pc, r3
+
+		return _system_clock_inst.dpll.frequency;
+#endif
+
+	default:
+		return 0;
+    16ba:	2000      	movs	r0, #0
+    16bc:	e032      	b.n	1724 <system_clock_source_get_hz+0x78>
+		return _system_clock_inst.xosc.frequency;
+    16be:	4b1b      	ldr	r3, [pc, #108]	; (172c <system_clock_source_get_hz+0x80>)
+    16c0:	6918      	ldr	r0, [r3, #16]
+    16c2:	e02f      	b.n	1724 <system_clock_source_get_hz+0x78>
+		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+    16c4:	4b1a      	ldr	r3, [pc, #104]	; (1730 <system_clock_source_get_hz+0x84>)
+    16c6:	6a1b      	ldr	r3, [r3, #32]
+    16c8:	059b      	lsls	r3, r3, #22
+    16ca:	0f9b      	lsrs	r3, r3, #30
+    16cc:	4819      	ldr	r0, [pc, #100]	; (1734 <system_clock_source_get_hz+0x88>)
+    16ce:	40d8      	lsrs	r0, r3
+    16d0:	e028      	b.n	1724 <system_clock_source_get_hz+0x78>
+		return _system_clock_inst.xosc32k.frequency;
+    16d2:	4b16      	ldr	r3, [pc, #88]	; (172c <system_clock_source_get_hz+0x80>)
+    16d4:	6958      	ldr	r0, [r3, #20]
+    16d6:	e025      	b.n	1724 <system_clock_source_get_hz+0x78>
+		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+    16d8:	4b14      	ldr	r3, [pc, #80]	; (172c <system_clock_source_get_hz+0x80>)
+    16da:	681b      	ldr	r3, [r3, #0]
+			return 0;
+    16dc:	2000      	movs	r0, #0
+		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+    16de:	079b      	lsls	r3, r3, #30
+    16e0:	d520      	bpl.n	1724 <system_clock_source_get_hz+0x78>
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+    16e2:	4913      	ldr	r1, [pc, #76]	; (1730 <system_clock_source_get_hz+0x84>)
+    16e4:	2210      	movs	r2, #16
+    16e6:	68cb      	ldr	r3, [r1, #12]
+    16e8:	421a      	tst	r2, r3
+    16ea:	d0fc      	beq.n	16e6 <system_clock_source_get_hz+0x3a>
+		switch(_system_clock_inst.dfll.control &
+    16ec:	4b0f      	ldr	r3, [pc, #60]	; (172c <system_clock_source_get_hz+0x80>)
+    16ee:	681a      	ldr	r2, [r3, #0]
+    16f0:	2324      	movs	r3, #36	; 0x24
+    16f2:	4013      	ands	r3, r2
+    16f4:	2b04      	cmp	r3, #4
+    16f6:	d001      	beq.n	16fc <system_clock_source_get_hz+0x50>
+			return 48000000UL;
+    16f8:	480f      	ldr	r0, [pc, #60]	; (1738 <system_clock_source_get_hz+0x8c>)
+    16fa:	e013      	b.n	1724 <system_clock_source_get_hz+0x78>
+			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+    16fc:	2000      	movs	r0, #0
+    16fe:	4b0f      	ldr	r3, [pc, #60]	; (173c <system_clock_source_get_hz+0x90>)
+    1700:	4798      	blx	r3
+					(_system_clock_inst.dfll.mul & 0xffff);
+    1702:	4b0a      	ldr	r3, [pc, #40]	; (172c <system_clock_source_get_hz+0x80>)
+    1704:	689b      	ldr	r3, [r3, #8]
+    1706:	041b      	lsls	r3, r3, #16
+    1708:	0c1b      	lsrs	r3, r3, #16
+			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+    170a:	4358      	muls	r0, r3
+    170c:	e00a      	b.n	1724 <system_clock_source_get_hz+0x78>
+		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
+    170e:	2350      	movs	r3, #80	; 0x50
+    1710:	4a07      	ldr	r2, [pc, #28]	; (1730 <system_clock_source_get_hz+0x84>)
+    1712:	5cd3      	ldrb	r3, [r2, r3]
+			return 0;
+    1714:	2000      	movs	r0, #0
+		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
+    1716:	075b      	lsls	r3, r3, #29
+    1718:	d504      	bpl.n	1724 <system_clock_source_get_hz+0x78>
+		return _system_clock_inst.dpll.frequency;
+    171a:	4b04      	ldr	r3, [pc, #16]	; (172c <system_clock_source_get_hz+0x80>)
+    171c:	68d8      	ldr	r0, [r3, #12]
+    171e:	e001      	b.n	1724 <system_clock_source_get_hz+0x78>
+		return 32768UL;
+    1720:	2080      	movs	r0, #128	; 0x80
+    1722:	0200      	lsls	r0, r0, #8
+	}
+}
+    1724:	bd10      	pop	{r4, pc}
+    1726:	46c0      	nop			; (mov r8, r8)
+    1728:	0000380c 	.word	0x0000380c
+    172c:	200001b4 	.word	0x200001b4
+    1730:	40000800 	.word	0x40000800
+    1734:	007a1200 	.word	0x007a1200
+    1738:	02dc6c00 	.word	0x02dc6c00
+    173c:	00001b11 	.word	0x00001b11
+
+00001740 <system_clock_source_osc8m_set_config>:
+ *
+ * \param[in] config  OSC8M configuration structure containing the new config
+ */
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config)
+{
+    1740:	b570      	push	{r4, r5, r6, lr}
+	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+    1742:	490c      	ldr	r1, [pc, #48]	; (1774 <system_clock_source_osc8m_set_config+0x34>)
+    1744:	6a0b      	ldr	r3, [r1, #32]
+
+	/* Use temporary struct to reduce register access */
+	temp.bit.PRESC    = config->prescaler;
+    1746:	7804      	ldrb	r4, [r0, #0]
+	temp.bit.ONDEMAND = config->on_demand;
+    1748:	7885      	ldrb	r5, [r0, #2]
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	SYSCTRL->OSC8M = temp;
+    174a:	7840      	ldrb	r0, [r0, #1]
+    174c:	2201      	movs	r2, #1
+    174e:	4010      	ands	r0, r2
+    1750:	0180      	lsls	r0, r0, #6
+    1752:	2640      	movs	r6, #64	; 0x40
+    1754:	43b3      	bics	r3, r6
+    1756:	4303      	orrs	r3, r0
+    1758:	402a      	ands	r2, r5
+    175a:	01d2      	lsls	r2, r2, #7
+    175c:	2080      	movs	r0, #128	; 0x80
+    175e:	4383      	bics	r3, r0
+    1760:	4313      	orrs	r3, r2
+    1762:	2203      	movs	r2, #3
+    1764:	4022      	ands	r2, r4
+    1766:	0212      	lsls	r2, r2, #8
+    1768:	4803      	ldr	r0, [pc, #12]	; (1778 <system_clock_source_osc8m_set_config+0x38>)
+    176a:	4003      	ands	r3, r0
+    176c:	4313      	orrs	r3, r2
+    176e:	620b      	str	r3, [r1, #32]
+}
+    1770:	bd70      	pop	{r4, r5, r6, pc}
+    1772:	46c0      	nop			; (mov r8, r8)
+    1774:	40000800 	.word	0x40000800
+    1778:	fffffcff 	.word	0xfffffcff
+
+0000177c <system_clock_source_enable>:
+ *                                 device
+ */
+enum status_code system_clock_source_enable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+    177c:	2808      	cmp	r0, #8
+    177e:	d803      	bhi.n	1788 <system_clock_source_enable+0xc>
+    1780:	0080      	lsls	r0, r0, #2
+    1782:	4b25      	ldr	r3, [pc, #148]	; (1818 <system_clock_source_enable+0x9c>)
+    1784:	581b      	ldr	r3, [r3, r0]
+    1786:	469f      	mov	pc, r3
+		/* Always enabled */
+		return STATUS_OK;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+    1788:	2017      	movs	r0, #23
+    178a:	e044      	b.n	1816 <system_clock_source_enable+0x9a>
+		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+    178c:	4a23      	ldr	r2, [pc, #140]	; (181c <system_clock_source_enable+0xa0>)
+    178e:	6a13      	ldr	r3, [r2, #32]
+    1790:	2102      	movs	r1, #2
+    1792:	430b      	orrs	r3, r1
+    1794:	6213      	str	r3, [r2, #32]
+		return STATUS_OK;
+    1796:	2000      	movs	r0, #0
+    1798:	e03d      	b.n	1816 <system_clock_source_enable+0x9a>
+		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+    179a:	4a20      	ldr	r2, [pc, #128]	; (181c <system_clock_source_enable+0xa0>)
+    179c:	6993      	ldr	r3, [r2, #24]
+    179e:	2102      	movs	r1, #2
+    17a0:	430b      	orrs	r3, r1
+    17a2:	6193      	str	r3, [r2, #24]
+	}
+
+	return STATUS_OK;
+    17a4:	2000      	movs	r0, #0
+		break;
+    17a6:	e036      	b.n	1816 <system_clock_source_enable+0x9a>
+		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+    17a8:	4a1c      	ldr	r2, [pc, #112]	; (181c <system_clock_source_enable+0xa0>)
+    17aa:	8a13      	ldrh	r3, [r2, #16]
+    17ac:	2102      	movs	r1, #2
+    17ae:	430b      	orrs	r3, r1
+    17b0:	8213      	strh	r3, [r2, #16]
+	return STATUS_OK;
+    17b2:	2000      	movs	r0, #0
+		break;
+    17b4:	e02f      	b.n	1816 <system_clock_source_enable+0x9a>
+		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+    17b6:	4a19      	ldr	r2, [pc, #100]	; (181c <system_clock_source_enable+0xa0>)
+    17b8:	8a93      	ldrh	r3, [r2, #20]
+    17ba:	2102      	movs	r1, #2
+    17bc:	430b      	orrs	r3, r1
+    17be:	8293      	strh	r3, [r2, #20]
+	return STATUS_OK;
+    17c0:	2000      	movs	r0, #0
+		break;
+    17c2:	e028      	b.n	1816 <system_clock_source_enable+0x9a>
+		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+    17c4:	4916      	ldr	r1, [pc, #88]	; (1820 <system_clock_source_enable+0xa4>)
+    17c6:	680b      	ldr	r3, [r1, #0]
+    17c8:	2202      	movs	r2, #2
+    17ca:	4313      	orrs	r3, r2
+    17cc:	600b      	str	r3, [r1, #0]
+	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+    17ce:	4b13      	ldr	r3, [pc, #76]	; (181c <system_clock_source_enable+0xa0>)
+    17d0:	849a      	strh	r2, [r3, #36]	; 0x24
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+    17d2:	0019      	movs	r1, r3
+    17d4:	320e      	adds	r2, #14
+    17d6:	68cb      	ldr	r3, [r1, #12]
+    17d8:	421a      	tst	r2, r3
+    17da:	d0fc      	beq.n	17d6 <system_clock_source_enable+0x5a>
+	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+    17dc:	4a10      	ldr	r2, [pc, #64]	; (1820 <system_clock_source_enable+0xa4>)
+    17de:	6891      	ldr	r1, [r2, #8]
+    17e0:	4b0e      	ldr	r3, [pc, #56]	; (181c <system_clock_source_enable+0xa0>)
+    17e2:	62d9      	str	r1, [r3, #44]	; 0x2c
+	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+    17e4:	6852      	ldr	r2, [r2, #4]
+    17e6:	629a      	str	r2, [r3, #40]	; 0x28
+	SYSCTRL->DFLLCTRL.reg = 0;
+    17e8:	2200      	movs	r2, #0
+    17ea:	849a      	strh	r2, [r3, #36]	; 0x24
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+    17ec:	0019      	movs	r1, r3
+    17ee:	3210      	adds	r2, #16
+    17f0:	68cb      	ldr	r3, [r1, #12]
+    17f2:	421a      	tst	r2, r3
+    17f4:	d0fc      	beq.n	17f0 <system_clock_source_enable+0x74>
+	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+    17f6:	4b0a      	ldr	r3, [pc, #40]	; (1820 <system_clock_source_enable+0xa4>)
+    17f8:	681b      	ldr	r3, [r3, #0]
+    17fa:	b29b      	uxth	r3, r3
+    17fc:	4a07      	ldr	r2, [pc, #28]	; (181c <system_clock_source_enable+0xa0>)
+    17fe:	8493      	strh	r3, [r2, #36]	; 0x24
+	return STATUS_OK;
+    1800:	2000      	movs	r0, #0
+    1802:	e008      	b.n	1816 <system_clock_source_enable+0x9a>
+		SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+    1804:	4905      	ldr	r1, [pc, #20]	; (181c <system_clock_source_enable+0xa0>)
+    1806:	2244      	movs	r2, #68	; 0x44
+    1808:	5c8b      	ldrb	r3, [r1, r2]
+    180a:	2002      	movs	r0, #2
+    180c:	4303      	orrs	r3, r0
+    180e:	548b      	strb	r3, [r1, r2]
+	return STATUS_OK;
+    1810:	2000      	movs	r0, #0
+		break;
+    1812:	e000      	b.n	1816 <system_clock_source_enable+0x9a>
+		return STATUS_OK;
+    1814:	2000      	movs	r0, #0
+}
+    1816:	4770      	bx	lr
+    1818:	00003830 	.word	0x00003830
+    181c:	40000800 	.word	0x40000800
+    1820:	200001b4 	.word	0x200001b4
+
+00001824 <system_clock_init>:
+ * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
+ * the OSC8M default enable can be disabled after system_clock_init. Make sure the
+ * clock switch successfully before disabling OSC8M.
+ */
+void system_clock_init(void)
+{
+    1824:	b530      	push	{r4, r5, lr}
+    1826:	b085      	sub	sp, #20
+	/* Various bits in the INTFLAG register can be set to one at startup.
+	   This will ensure that these bits are cleared */
+	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+    1828:	22c2      	movs	r2, #194	; 0xc2
+    182a:	00d2      	lsls	r2, r2, #3
+    182c:	4b1a      	ldr	r3, [pc, #104]	; (1898 <system_clock_init+0x74>)
+    182e:	609a      	str	r2, [r3, #8]
+static inline void system_flash_set_waitstates(uint8_t wait_states)
+{
+	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+
+	NVMCTRL->CTRLB.bit.RWS = wait_states;
+    1830:	4a1a      	ldr	r2, [pc, #104]	; (189c <system_clock_init+0x78>)
+    1832:	6853      	ldr	r3, [r2, #4]
+    1834:	211e      	movs	r1, #30
+    1836:	438b      	bics	r3, r1
+    1838:	6053      	str	r3, [r2, #4]
+	gclk_conf.source_generator = GCLK_GENERATOR_1;
+    183a:	2301      	movs	r3, #1
+    183c:	466a      	mov	r2, sp
+    183e:	7013      	strb	r3, [r2, #0]
+	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
+    1840:	2400      	movs	r4, #0
+		system_gclk_chan_set_config(gclk_id, &gclk_conf);
+    1842:	4d17      	ldr	r5, [pc, #92]	; (18a0 <system_clock_init+0x7c>)
+    1844:	b2e0      	uxtb	r0, r4
+    1846:	4669      	mov	r1, sp
+    1848:	47a8      	blx	r5
+	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
+    184a:	3401      	adds	r4, #1
+    184c:	2c25      	cmp	r4, #37	; 0x25
+    184e:	d1f9      	bne.n	1844 <system_clock_init+0x20>
+	config->run_in_standby  = false;
+    1850:	a803      	add	r0, sp, #12
+    1852:	2400      	movs	r4, #0
+    1854:	7044      	strb	r4, [r0, #1]
+	config->on_demand       = true;
+    1856:	2501      	movs	r5, #1
+    1858:	7085      	strb	r5, [r0, #2]
+
+	/* OSC8M */
+	struct system_clock_source_osc8m_config osc8m_conf;
+	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+
+	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
+    185a:	7004      	strb	r4, [r0, #0]
+	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
+	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+
+	system_clock_source_osc8m_set_config(&osc8m_conf);
+    185c:	4b11      	ldr	r3, [pc, #68]	; (18a4 <system_clock_init+0x80>)
+    185e:	4798      	blx	r3
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+    1860:	2006      	movs	r0, #6
+    1862:	4b11      	ldr	r3, [pc, #68]	; (18a8 <system_clock_init+0x84>)
+    1864:	4798      	blx	r3
+
+
+	/* GCLK */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	system_gclk_init();
+    1866:	4b11      	ldr	r3, [pc, #68]	; (18ac <system_clock_init+0x88>)
+    1868:	4798      	blx	r3
+	PM->CPUSEL.reg = (uint32_t)divider;
+    186a:	4b11      	ldr	r3, [pc, #68]	; (18b0 <system_clock_init+0x8c>)
+    186c:	721c      	strb	r4, [r3, #8]
+			PM->APBASEL.reg = (uint32_t)divider;
+    186e:	725c      	strb	r4, [r3, #9]
+			PM->APBBSEL.reg = (uint32_t)divider;
+    1870:	729c      	strb	r4, [r3, #10]
+			PM->APBCSEL.reg = (uint32_t)divider;
+    1872:	72dc      	strb	r4, [r3, #11]
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->division_factor    = 1;
+    1874:	9501      	str	r5, [sp, #4]
+	config->high_when_disabled = false;
+    1876:	466b      	mov	r3, sp
+    1878:	705c      	strb	r4, [r3, #1]
+#if SAML21 || SAML22  || SAMR30 || SAMR34 || SAMR35
+	config->source_clock       = GCLK_SOURCE_OSC16M;
+#elif (SAMC20) || (SAMC21)
+	config->source_clock       = GCLK_SOURCE_OSC48M;
+#else
+	config->source_clock       = GCLK_SOURCE_OSC8M;
+    187a:	2306      	movs	r3, #6
+    187c:	466a      	mov	r2, sp
+    187e:	7013      	strb	r3, [r2, #0]
+#endif
+	config->run_in_standby     = false;
+    1880:	7214      	strb	r4, [r2, #8]
+	config->output_enable      = false;
+    1882:	7254      	strb	r4, [r2, #9]
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
+
+	/* GCLK 0 */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	/* Configure the main GCLK last as it might depend on other generators */
+	_CONF_CLOCK_GCLK_CONFIG(0, ~);
+    1884:	4669      	mov	r1, sp
+    1886:	2000      	movs	r0, #0
+    1888:	4b0a      	ldr	r3, [pc, #40]	; (18b4 <system_clock_init+0x90>)
+    188a:	4798      	blx	r3
+    188c:	2000      	movs	r0, #0
+    188e:	4b0a      	ldr	r3, [pc, #40]	; (18b8 <system_clock_init+0x94>)
+    1890:	4798      	blx	r3
+#endif
+}
+    1892:	b005      	add	sp, #20
+    1894:	bd30      	pop	{r4, r5, pc}
+    1896:	46c0      	nop			; (mov r8, r8)
+    1898:	40000800 	.word	0x40000800
+    189c:	41004000 	.word	0x41004000
+    18a0:	00001af5 	.word	0x00001af5
+    18a4:	00001741 	.word	0x00001741
+    18a8:	0000177d 	.word	0x0000177d
+    18ac:	000018bd 	.word	0x000018bd
+    18b0:	40000400 	.word	0x40000400
+    18b4:	000018e1 	.word	0x000018e1
+    18b8:	00001999 	.word	0x00001999
+
+000018bc <system_gclk_init>:
+			PM->APBAMASK.reg |= mask;
+    18bc:	4a06      	ldr	r2, [pc, #24]	; (18d8 <system_gclk_init+0x1c>)
+    18be:	6993      	ldr	r3, [r2, #24]
+    18c0:	2108      	movs	r1, #8
+    18c2:	430b      	orrs	r3, r1
+    18c4:	6193      	str	r3, [r2, #24]
+{
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+	/* Software reset the module to ensure it is re-initialized correctly */
+	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+    18c6:	2201      	movs	r2, #1
+    18c8:	4b04      	ldr	r3, [pc, #16]	; (18dc <system_gclk_init+0x20>)
+    18ca:	701a      	strb	r2, [r3, #0]
+	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+    18cc:	0019      	movs	r1, r3
+    18ce:	780b      	ldrb	r3, [r1, #0]
+    18d0:	4213      	tst	r3, r2
+    18d2:	d1fc      	bne.n	18ce <system_gclk_init+0x12>
+		/* Wait for reset to complete */
+	}
+}
+    18d4:	4770      	bx	lr
+    18d6:	46c0      	nop			; (mov r8, r8)
+    18d8:	40000400 	.word	0x40000400
+    18dc:	40000c00 	.word	0x40000c00
+
+000018e0 <system_gclk_gen_set_config>:
+ * \param[in] config     Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config)
+{
+    18e0:	b570      	push	{r4, r5, r6, lr}
+    18e2:	0006      	movs	r6, r0
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache new register configurations to minimize sync requirements. */
+	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+    18e4:	0004      	movs	r4, r0
+	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+	/* Select the requested source clock for the generator */
+	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+    18e6:	780d      	ldrb	r5, [r1, #0]
+    18e8:	022d      	lsls	r5, r5, #8
+    18ea:	4305      	orrs	r5, r0
+
+	/* Configure the clock to be either high or low when disabled */
+	if (config->high_when_disabled) {
+    18ec:	784b      	ldrb	r3, [r1, #1]
+    18ee:	2b00      	cmp	r3, #0
+    18f0:	d002      	beq.n	18f8 <system_gclk_gen_set_config+0x18>
+		new_genctrl_config |= GCLK_GENCTRL_OOV;
+    18f2:	2380      	movs	r3, #128	; 0x80
+    18f4:	02db      	lsls	r3, r3, #11
+    18f6:	431d      	orrs	r5, r3
+	}
+
+	/* Configure if the clock output to I/O pin should be enabled. */
+	if (config->output_enable) {
+    18f8:	7a4b      	ldrb	r3, [r1, #9]
+    18fa:	2b00      	cmp	r3, #0
+    18fc:	d002      	beq.n	1904 <system_gclk_gen_set_config+0x24>
+		new_genctrl_config |= GCLK_GENCTRL_OE;
+    18fe:	2380      	movs	r3, #128	; 0x80
+    1900:	031b      	lsls	r3, r3, #12
+    1902:	431d      	orrs	r5, r3
+	}
+
+	/* Set division factor */
+	if (config->division_factor > 1) {
+    1904:	6848      	ldr	r0, [r1, #4]
+    1906:	2801      	cmp	r0, #1
+    1908:	d910      	bls.n	192c <system_gclk_gen_set_config+0x4c>
+		/* Check if division is a power of two */
+		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+    190a:	1e43      	subs	r3, r0, #1
+    190c:	4218      	tst	r0, r3
+    190e:	d134      	bne.n	197a <system_gclk_gen_set_config+0x9a>
+			 * register */
+
+			uint32_t div2_count = 0;
+
+			uint32_t mask;
+			for (mask = (1UL << 1); mask < config->division_factor;
+    1910:	2802      	cmp	r0, #2
+    1912:	d930      	bls.n	1976 <system_gclk_gen_set_config+0x96>
+    1914:	2302      	movs	r3, #2
+    1916:	2200      	movs	r2, #0
+						mask <<= 1) {
+				div2_count++;
+    1918:	3201      	adds	r2, #1
+						mask <<= 1) {
+    191a:	005b      	lsls	r3, r3, #1
+			for (mask = (1UL << 1); mask < config->division_factor;
+    191c:	4298      	cmp	r0, r3
+    191e:	d8fb      	bhi.n	1918 <system_gclk_gen_set_config+0x38>
+			}
+
+			/* Set binary divider power of 2 division factor */
+			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+    1920:	0212      	lsls	r2, r2, #8
+    1922:	4332      	orrs	r2, r6
+    1924:	0014      	movs	r4, r2
+			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+    1926:	2380      	movs	r3, #128	; 0x80
+    1928:	035b      	lsls	r3, r3, #13
+    192a:	431d      	orrs	r5, r3
+		}
+
+	}
+
+	/* Enable or disable the clock in standby mode */
+	if (config->run_in_standby) {
+    192c:	7a0b      	ldrb	r3, [r1, #8]
+    192e:	2b00      	cmp	r3, #0
+    1930:	d002      	beq.n	1938 <system_gclk_gen_set_config+0x58>
+		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+    1932:	2380      	movs	r3, #128	; 0x80
+    1934:	039b      	lsls	r3, r3, #14
+    1936:	431d      	orrs	r5, r3
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    1938:	4a13      	ldr	r2, [pc, #76]	; (1988 <system_gclk_gen_set_config+0xa8>)
+    193a:	7853      	ldrb	r3, [r2, #1]
+	}
+
+	while (system_gclk_is_syncing()) {
+    193c:	b25b      	sxtb	r3, r3
+    193e:	2b00      	cmp	r3, #0
+    1940:	dbfb      	blt.n	193a <system_gclk_gen_set_config+0x5a>
+	cpu_irq_enter_critical();
+    1942:	4b12      	ldr	r3, [pc, #72]	; (198c <system_gclk_gen_set_config+0xac>)
+    1944:	4798      	blx	r3
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the correct generator */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+    1946:	4b12      	ldr	r3, [pc, #72]	; (1990 <system_gclk_gen_set_config+0xb0>)
+    1948:	701e      	strb	r6, [r3, #0]
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    194a:	4a0f      	ldr	r2, [pc, #60]	; (1988 <system_gclk_gen_set_config+0xa8>)
+    194c:	7853      	ldrb	r3, [r2, #1]
+
+	/* Write the new generator configuration */
+	while (system_gclk_is_syncing()) {
+    194e:	b25b      	sxtb	r3, r3
+    1950:	2b00      	cmp	r3, #0
+    1952:	dbfb      	blt.n	194c <system_gclk_gen_set_config+0x6c>
+		/* Wait for synchronization */
+	};
+	GCLK->GENDIV.reg  = new_gendiv_config;
+    1954:	4b0c      	ldr	r3, [pc, #48]	; (1988 <system_gclk_gen_set_config+0xa8>)
+    1956:	609c      	str	r4, [r3, #8]
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    1958:	001a      	movs	r2, r3
+    195a:	7853      	ldrb	r3, [r2, #1]
+
+	while (system_gclk_is_syncing()) {
+    195c:	b25b      	sxtb	r3, r3
+    195e:	2b00      	cmp	r3, #0
+    1960:	dbfb      	blt.n	195a <system_gclk_gen_set_config+0x7a>
+		/* Wait for synchronization */
+	};
+	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+    1962:	4a09      	ldr	r2, [pc, #36]	; (1988 <system_gclk_gen_set_config+0xa8>)
+    1964:	6853      	ldr	r3, [r2, #4]
+    1966:	2180      	movs	r1, #128	; 0x80
+    1968:	0249      	lsls	r1, r1, #9
+    196a:	400b      	ands	r3, r1
+    196c:	431d      	orrs	r5, r3
+    196e:	6055      	str	r5, [r2, #4]
+	cpu_irq_leave_critical();
+    1970:	4b08      	ldr	r3, [pc, #32]	; (1994 <system_gclk_gen_set_config+0xb4>)
+    1972:	4798      	blx	r3
+
+	system_interrupt_leave_critical_section();
+}
+    1974:	bd70      	pop	{r4, r5, r6, pc}
+			for (mask = (1UL << 1); mask < config->division_factor;
+    1976:	2200      	movs	r2, #0
+    1978:	e7d2      	b.n	1920 <system_gclk_gen_set_config+0x40>
+					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
+    197a:	0204      	lsls	r4, r0, #8
+			new_gendiv_config  |=
+    197c:	4334      	orrs	r4, r6
+			new_genctrl_config |= GCLK_GENCTRL_IDC;
+    197e:	2380      	movs	r3, #128	; 0x80
+    1980:	029b      	lsls	r3, r3, #10
+    1982:	431d      	orrs	r5, r3
+    1984:	e7d2      	b.n	192c <system_gclk_gen_set_config+0x4c>
+    1986:	46c0      	nop			; (mov r8, r8)
+    1988:	40000c00 	.word	0x40000c00
+    198c:	000015e1 	.word	0x000015e1
+    1990:	40000c08 	.word	0x40000c08
+    1994:	00001621 	.word	0x00001621
+
+00001998 <system_gclk_gen_enable>:
+ *
+ * \param[in] generator  Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+		const uint8_t generator)
+{
+    1998:	b510      	push	{r4, lr}
+    199a:	0004      	movs	r4, r0
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    199c:	4a0b      	ldr	r2, [pc, #44]	; (19cc <system_gclk_gen_enable+0x34>)
+    199e:	7853      	ldrb	r3, [r2, #1]
+	while (system_gclk_is_syncing()) {
+    19a0:	b25b      	sxtb	r3, r3
+    19a2:	2b00      	cmp	r3, #0
+    19a4:	dbfb      	blt.n	199e <system_gclk_gen_enable+0x6>
+	cpu_irq_enter_critical();
+    19a6:	4b0a      	ldr	r3, [pc, #40]	; (19d0 <system_gclk_gen_enable+0x38>)
+    19a8:	4798      	blx	r3
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    19aa:	4b0a      	ldr	r3, [pc, #40]	; (19d4 <system_gclk_gen_enable+0x3c>)
+    19ac:	701c      	strb	r4, [r3, #0]
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    19ae:	4a07      	ldr	r2, [pc, #28]	; (19cc <system_gclk_gen_enable+0x34>)
+    19b0:	7853      	ldrb	r3, [r2, #1]
+	while (system_gclk_is_syncing()) {
+    19b2:	b25b      	sxtb	r3, r3
+    19b4:	2b00      	cmp	r3, #0
+    19b6:	dbfb      	blt.n	19b0 <system_gclk_gen_enable+0x18>
+		/* Wait for synchronization */
+	};
+
+	/* Enable generator */
+	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+    19b8:	4a04      	ldr	r2, [pc, #16]	; (19cc <system_gclk_gen_enable+0x34>)
+    19ba:	6851      	ldr	r1, [r2, #4]
+    19bc:	2380      	movs	r3, #128	; 0x80
+    19be:	025b      	lsls	r3, r3, #9
+    19c0:	430b      	orrs	r3, r1
+    19c2:	6053      	str	r3, [r2, #4]
+	cpu_irq_leave_critical();
+    19c4:	4b04      	ldr	r3, [pc, #16]	; (19d8 <system_gclk_gen_enable+0x40>)
+    19c6:	4798      	blx	r3
+
+	system_interrupt_leave_critical_section();
+}
+    19c8:	bd10      	pop	{r4, pc}
+    19ca:	46c0      	nop			; (mov r8, r8)
+    19cc:	40000c00 	.word	0x40000c00
+    19d0:	000015e1 	.word	0x000015e1
+    19d4:	40000c04 	.word	0x40000c04
+    19d8:	00001621 	.word	0x00001621
+
+000019dc <system_gclk_gen_get_hz>:
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator)
+{
+    19dc:	b570      	push	{r4, r5, r6, lr}
+    19de:	0004      	movs	r4, r0
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    19e0:	4a1a      	ldr	r2, [pc, #104]	; (1a4c <system_gclk_gen_get_hz+0x70>)
+    19e2:	7853      	ldrb	r3, [r2, #1]
+	while (system_gclk_is_syncing()) {
+    19e4:	b25b      	sxtb	r3, r3
+    19e6:	2b00      	cmp	r3, #0
+    19e8:	dbfb      	blt.n	19e2 <system_gclk_gen_get_hz+0x6>
+	cpu_irq_enter_critical();
+    19ea:	4b19      	ldr	r3, [pc, #100]	; (1a50 <system_gclk_gen_get_hz+0x74>)
+    19ec:	4798      	blx	r3
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the appropriate generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    19ee:	4b19      	ldr	r3, [pc, #100]	; (1a54 <system_gclk_gen_get_hz+0x78>)
+    19f0:	701c      	strb	r4, [r3, #0]
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    19f2:	4a16      	ldr	r2, [pc, #88]	; (1a4c <system_gclk_gen_get_hz+0x70>)
+    19f4:	7853      	ldrb	r3, [r2, #1]
+	while (system_gclk_is_syncing()) {
+    19f6:	b25b      	sxtb	r3, r3
+    19f8:	2b00      	cmp	r3, #0
+    19fa:	dbfb      	blt.n	19f4 <system_gclk_gen_get_hz+0x18>
+		/* Wait for synchronization */
+	};
+
+	/* Get the frequency of the source connected to the GCLK generator */
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+    19fc:	4e13      	ldr	r6, [pc, #76]	; (1a4c <system_gclk_gen_get_hz+0x70>)
+    19fe:	6870      	ldr	r0, [r6, #4]
+    1a00:	04c0      	lsls	r0, r0, #19
+    1a02:	0ec0      	lsrs	r0, r0, #27
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+    1a04:	4b14      	ldr	r3, [pc, #80]	; (1a58 <system_gclk_gen_get_hz+0x7c>)
+    1a06:	4798      	blx	r3
+    1a08:	0005      	movs	r5, r0
+
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    1a0a:	4b12      	ldr	r3, [pc, #72]	; (1a54 <system_gclk_gen_get_hz+0x78>)
+    1a0c:	701c      	strb	r4, [r3, #0]
+
+	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+    1a0e:	6876      	ldr	r6, [r6, #4]
+    1a10:	02f6      	lsls	r6, r6, #11
+    1a12:	0ff6      	lsrs	r6, r6, #31
+
+	/* Select the appropriate generator division register */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+    1a14:	4b11      	ldr	r3, [pc, #68]	; (1a5c <system_gclk_gen_get_hz+0x80>)
+    1a16:	701c      	strb	r4, [r3, #0]
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+    1a18:	4a0c      	ldr	r2, [pc, #48]	; (1a4c <system_gclk_gen_get_hz+0x70>)
+    1a1a:	7853      	ldrb	r3, [r2, #1]
+	while (system_gclk_is_syncing()) {
+    1a1c:	b25b      	sxtb	r3, r3
+    1a1e:	2b00      	cmp	r3, #0
+    1a20:	dbfb      	blt.n	1a1a <system_gclk_gen_get_hz+0x3e>
+		/* Wait for synchronization */
+	};
+
+	uint32_t divider = GCLK->GENDIV.bit.DIV;
+    1a22:	4b0a      	ldr	r3, [pc, #40]	; (1a4c <system_gclk_gen_get_hz+0x70>)
+    1a24:	689c      	ldr	r4, [r3, #8]
+    1a26:	0224      	lsls	r4, r4, #8
+    1a28:	0c24      	lsrs	r4, r4, #16
+	cpu_irq_leave_critical();
+    1a2a:	4b0d      	ldr	r3, [pc, #52]	; (1a60 <system_gclk_gen_get_hz+0x84>)
+    1a2c:	4798      	blx	r3
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if the generator is using fractional or binary division */
+	if (!divsel && divider > 1) {
+    1a2e:	2e00      	cmp	r6, #0
+    1a30:	d107      	bne.n	1a42 <system_gclk_gen_get_hz+0x66>
+    1a32:	2c01      	cmp	r4, #1
+    1a34:	d907      	bls.n	1a46 <system_gclk_gen_get_hz+0x6a>
+		gen_input_hz /= divider;
+    1a36:	0021      	movs	r1, r4
+    1a38:	0028      	movs	r0, r5
+    1a3a:	4b0a      	ldr	r3, [pc, #40]	; (1a64 <system_gclk_gen_get_hz+0x88>)
+    1a3c:	4798      	blx	r3
+    1a3e:	0005      	movs	r5, r0
+    1a40:	e001      	b.n	1a46 <system_gclk_gen_get_hz+0x6a>
+	} else if (divsel) {
+		gen_input_hz >>= (divider+1);
+    1a42:	3401      	adds	r4, #1
+    1a44:	40e5      	lsrs	r5, r4
+	}
+
+	return gen_input_hz;
+}
+    1a46:	0028      	movs	r0, r5
+    1a48:	bd70      	pop	{r4, r5, r6, pc}
+    1a4a:	46c0      	nop			; (mov r8, r8)
+    1a4c:	40000c00 	.word	0x40000c00
+    1a50:	000015e1 	.word	0x000015e1
+    1a54:	40000c04 	.word	0x40000c04
+    1a58:	000016ad 	.word	0x000016ad
+    1a5c:	40000c08 	.word	0x40000c08
+    1a60:	00001621 	.word	0x00001621
+    1a64:	00001df5 	.word	0x00001df5
+
+00001a68 <system_gclk_chan_enable>:
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+		const uint8_t channel)
+{
+    1a68:	b510      	push	{r4, lr}
+    1a6a:	0004      	movs	r4, r0
+	cpu_irq_enter_critical();
+    1a6c:	4b06      	ldr	r3, [pc, #24]	; (1a88 <system_gclk_chan_enable+0x20>)
+    1a6e:	4798      	blx	r3
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    1a70:	4b06      	ldr	r3, [pc, #24]	; (1a8c <system_gclk_chan_enable+0x24>)
+    1a72:	701c      	strb	r4, [r3, #0]
+
+	/* Enable the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+    1a74:	4a06      	ldr	r2, [pc, #24]	; (1a90 <system_gclk_chan_enable+0x28>)
+    1a76:	8853      	ldrh	r3, [r2, #2]
+    1a78:	2180      	movs	r1, #128	; 0x80
+    1a7a:	01c9      	lsls	r1, r1, #7
+    1a7c:	430b      	orrs	r3, r1
+    1a7e:	8053      	strh	r3, [r2, #2]
+	cpu_irq_leave_critical();
+    1a80:	4b04      	ldr	r3, [pc, #16]	; (1a94 <system_gclk_chan_enable+0x2c>)
+    1a82:	4798      	blx	r3
+
+	system_interrupt_leave_critical_section();
+}
+    1a84:	bd10      	pop	{r4, pc}
+    1a86:	46c0      	nop			; (mov r8, r8)
+    1a88:	000015e1 	.word	0x000015e1
+    1a8c:	40000c02 	.word	0x40000c02
+    1a90:	40000c00 	.word	0x40000c00
+    1a94:	00001621 	.word	0x00001621
+
+00001a98 <system_gclk_chan_disable>:
+ *
+ * \param[in] channel  Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+		const uint8_t channel)
+{
+    1a98:	b510      	push	{r4, lr}
+    1a9a:	0004      	movs	r4, r0
+	cpu_irq_enter_critical();
+    1a9c:	4b0f      	ldr	r3, [pc, #60]	; (1adc <system_gclk_chan_disable+0x44>)
+    1a9e:	4798      	blx	r3
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    1aa0:	4b0f      	ldr	r3, [pc, #60]	; (1ae0 <system_gclk_chan_disable+0x48>)
+    1aa2:	701c      	strb	r4, [r3, #0]
+
+	/* Sanity check WRTLOCK */
+	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+	/* Switch to known-working source so that the channel can be disabled */
+	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+    1aa4:	4a0f      	ldr	r2, [pc, #60]	; (1ae4 <system_gclk_chan_disable+0x4c>)
+    1aa6:	8853      	ldrh	r3, [r2, #2]
+    1aa8:	051b      	lsls	r3, r3, #20
+    1aaa:	0f18      	lsrs	r0, r3, #28
+	GCLK->CLKCTRL.bit.GEN = 0;
+    1aac:	8853      	ldrh	r3, [r2, #2]
+    1aae:	490e      	ldr	r1, [pc, #56]	; (1ae8 <system_gclk_chan_disable+0x50>)
+    1ab0:	400b      	ands	r3, r1
+    1ab2:	8053      	strh	r3, [r2, #2]
+
+	/* Disable the generic clock */
+	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+    1ab4:	8853      	ldrh	r3, [r2, #2]
+    1ab6:	490d      	ldr	r1, [pc, #52]	; (1aec <system_gclk_chan_disable+0x54>)
+    1ab8:	400b      	ands	r3, r1
+    1aba:	8053      	strh	r3, [r2, #2]
+	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+    1abc:	0011      	movs	r1, r2
+    1abe:	2280      	movs	r2, #128	; 0x80
+    1ac0:	01d2      	lsls	r2, r2, #7
+    1ac2:	884b      	ldrh	r3, [r1, #2]
+    1ac4:	4213      	tst	r3, r2
+    1ac6:	d1fc      	bne.n	1ac2 <system_gclk_chan_disable+0x2a>
+		/* Wait for clock to become disabled */
+	}
+
+	/* Restore previous configured clock generator */
+	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+    1ac8:	4906      	ldr	r1, [pc, #24]	; (1ae4 <system_gclk_chan_disable+0x4c>)
+    1aca:	884a      	ldrh	r2, [r1, #2]
+    1acc:	0203      	lsls	r3, r0, #8
+    1ace:	4806      	ldr	r0, [pc, #24]	; (1ae8 <system_gclk_chan_disable+0x50>)
+    1ad0:	4002      	ands	r2, r0
+    1ad2:	4313      	orrs	r3, r2
+    1ad4:	804b      	strh	r3, [r1, #2]
+	cpu_irq_leave_critical();
+    1ad6:	4b06      	ldr	r3, [pc, #24]	; (1af0 <system_gclk_chan_disable+0x58>)
+    1ad8:	4798      	blx	r3
+
+	system_interrupt_leave_critical_section();
+}
+    1ada:	bd10      	pop	{r4, pc}
+    1adc:	000015e1 	.word	0x000015e1
+    1ae0:	40000c02 	.word	0x40000c02
+    1ae4:	40000c00 	.word	0x40000c00
+    1ae8:	fffff0ff 	.word	0xfffff0ff
+    1aec:	ffffbfff 	.word	0xffffbfff
+    1af0:	00001621 	.word	0x00001621
+
+00001af4 <system_gclk_chan_set_config>:
+{
+    1af4:	b510      	push	{r4, lr}
+	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+    1af6:	780c      	ldrb	r4, [r1, #0]
+    1af8:	0224      	lsls	r4, r4, #8
+    1afa:	4304      	orrs	r4, r0
+	system_gclk_chan_disable(channel);
+    1afc:	4b02      	ldr	r3, [pc, #8]	; (1b08 <system_gclk_chan_set_config+0x14>)
+    1afe:	4798      	blx	r3
+	GCLK->CLKCTRL.reg = new_clkctrl_config;
+    1b00:	b2a4      	uxth	r4, r4
+    1b02:	4b02      	ldr	r3, [pc, #8]	; (1b0c <system_gclk_chan_set_config+0x18>)
+    1b04:	805c      	strh	r4, [r3, #2]
+}
+    1b06:	bd10      	pop	{r4, pc}
+    1b08:	00001a99 	.word	0x00001a99
+    1b0c:	40000c00 	.word	0x40000c00
+
+00001b10 <system_gclk_chan_get_hz>:
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel)
+{
+    1b10:	b510      	push	{r4, lr}
+    1b12:	0004      	movs	r4, r0
+	cpu_irq_enter_critical();
+    1b14:	4b06      	ldr	r3, [pc, #24]	; (1b30 <system_gclk_chan_get_hz+0x20>)
+    1b16:	4798      	blx	r3
+	uint8_t gen_id;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    1b18:	4b06      	ldr	r3, [pc, #24]	; (1b34 <system_gclk_chan_get_hz+0x24>)
+    1b1a:	701c      	strb	r4, [r3, #0]
+	gen_id = GCLK->CLKCTRL.bit.GEN;
+    1b1c:	4b06      	ldr	r3, [pc, #24]	; (1b38 <system_gclk_chan_get_hz+0x28>)
+    1b1e:	885c      	ldrh	r4, [r3, #2]
+    1b20:	0524      	lsls	r4, r4, #20
+    1b22:	0f24      	lsrs	r4, r4, #28
+	cpu_irq_leave_critical();
+    1b24:	4b05      	ldr	r3, [pc, #20]	; (1b3c <system_gclk_chan_get_hz+0x2c>)
+    1b26:	4798      	blx	r3
+
+	system_interrupt_leave_critical_section();
+
+	/* Return the clock speed of the associated GCLK generator */
+	return system_gclk_gen_get_hz(gen_id);
+    1b28:	0020      	movs	r0, r4
+    1b2a:	4b05      	ldr	r3, [pc, #20]	; (1b40 <system_gclk_chan_get_hz+0x30>)
+    1b2c:	4798      	blx	r3
+}
+    1b2e:	bd10      	pop	{r4, pc}
+    1b30:	000015e1 	.word	0x000015e1
+    1b34:	40000c02 	.word	0x40000c02
+    1b38:	40000c00 	.word	0x40000c00
+    1b3c:	00001621 	.word	0x00001621
+    1b40:	000019dd 	.word	0x000019dd
+
+00001b44 <_system_pinmux_config>:
+ */
+static void _system_pinmux_config(
+		PortGroup *const port,
+		const uint32_t pin_mask,
+		const struct system_pinmux_config *const config)
+{
+    1b44:	b530      	push	{r4, r5, lr}
+
+	/* Track the configuration bits into a temporary variable before writing */
+	uint32_t pin_cfg = 0;
+
+	/* Enabled powersave mode, don't create configuration */
+	if (!config->powersave) {
+    1b46:	78d3      	ldrb	r3, [r2, #3]
+    1b48:	2b00      	cmp	r3, #0
+    1b4a:	d135      	bne.n	1bb8 <_system_pinmux_config+0x74>
+		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+		 * be written later) and store the new MUX mask */
+		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+    1b4c:	7813      	ldrb	r3, [r2, #0]
+    1b4e:	2b80      	cmp	r3, #128	; 0x80
+    1b50:	d029      	beq.n	1ba6 <_system_pinmux_config+0x62>
+			pin_cfg |= PORT_WRCONFIG_PMUXEN;
+			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+    1b52:	061b      	lsls	r3, r3, #24
+    1b54:	2480      	movs	r4, #128	; 0x80
+    1b56:	0264      	lsls	r4, r4, #9
+    1b58:	4323      	orrs	r3, r4
+		}
+
+		/* Check if the user has requested that the input buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+    1b5a:	7854      	ldrb	r4, [r2, #1]
+    1b5c:	2502      	movs	r5, #2
+    1b5e:	43ac      	bics	r4, r5
+    1b60:	d106      	bne.n	1b70 <_system_pinmux_config+0x2c>
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Enable input buffer flag */
+			pin_cfg |= PORT_WRCONFIG_INEN;
+
+			/* Enable pull-up/pull-down control flag if requested */
+			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+    1b62:	7894      	ldrb	r4, [r2, #2]
+    1b64:	2c00      	cmp	r4, #0
+    1b66:	d120      	bne.n	1baa <_system_pinmux_config+0x66>
+			pin_cfg |= PORT_WRCONFIG_INEN;
+    1b68:	2480      	movs	r4, #128	; 0x80
+    1b6a:	02a4      	lsls	r4, r4, #10
+    1b6c:	4323      	orrs	r3, r4
+				pin_cfg |= PORT_WRCONFIG_PULLEN;
+			}
+
+			/* Clear the port DIR bits to disable the output buffer */
+			port->DIRCLR.reg = pin_mask;
+    1b6e:	6041      	str	r1, [r0, #4]
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+    1b70:	7854      	ldrb	r4, [r2, #1]
+    1b72:	3c01      	subs	r4, #1
+    1b74:	2c01      	cmp	r4, #1
+    1b76:	d91c      	bls.n	1bb2 <_system_pinmux_config+0x6e>
+		port->DIRCLR.reg = pin_mask;
+	}
+
+	/* The Write Configuration register (WRCONFIG) requires the
+	 * pins to to grouped into two 16-bit half-words - split them out here */
+	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+    1b78:	040d      	lsls	r5, r1, #16
+    1b7a:	0c2d      	lsrs	r5, r5, #16
+
+	/* Configure the lower 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+    1b7c:	24a0      	movs	r4, #160	; 0xa0
+    1b7e:	05e4      	lsls	r4, r4, #23
+    1b80:	432c      	orrs	r4, r5
+    1b82:	431c      	orrs	r4, r3
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+    1b84:	6284      	str	r4, [r0, #40]	; 0x28
+	uint32_t upper_pin_mask = (pin_mask >> 16);
+    1b86:	0c0d      	lsrs	r5, r1, #16
+
+	/* Configure the upper 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+    1b88:	24d0      	movs	r4, #208	; 0xd0
+    1b8a:	0624      	lsls	r4, r4, #24
+    1b8c:	432c      	orrs	r4, r5
+    1b8e:	431c      	orrs	r4, r3
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+    1b90:	6284      	str	r4, [r0, #40]	; 0x28
+			PORT_WRCONFIG_HWSEL;
+
+	if(!config->powersave) {
+    1b92:	78d4      	ldrb	r4, [r2, #3]
+    1b94:	2c00      	cmp	r4, #0
+    1b96:	d122      	bne.n	1bde <_system_pinmux_config+0x9a>
+		/* Set the pull-up state once the port pins are configured if one was
+		 * requested and it does not violate the valid set of port
+		 * configurations */
+		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+    1b98:	035b      	lsls	r3, r3, #13
+    1b9a:	d51c      	bpl.n	1bd6 <_system_pinmux_config+0x92>
+			/* Set the OUT register bits to enable the pull-up if requested,
+			 * clear to enable pull-down */
+			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+    1b9c:	7893      	ldrb	r3, [r2, #2]
+    1b9e:	2b01      	cmp	r3, #1
+    1ba0:	d01e      	beq.n	1be0 <_system_pinmux_config+0x9c>
+				port->OUTSET.reg = pin_mask;
+			} else {
+				port->OUTCLR.reg = pin_mask;
+    1ba2:	6141      	str	r1, [r0, #20]
+    1ba4:	e017      	b.n	1bd6 <_system_pinmux_config+0x92>
+	uint32_t pin_cfg = 0;
+    1ba6:	2300      	movs	r3, #0
+    1ba8:	e7d7      	b.n	1b5a <_system_pinmux_config+0x16>
+				pin_cfg |= PORT_WRCONFIG_PULLEN;
+    1baa:	24c0      	movs	r4, #192	; 0xc0
+    1bac:	02e4      	lsls	r4, r4, #11
+    1bae:	4323      	orrs	r3, r4
+    1bb0:	e7dd      	b.n	1b6e <_system_pinmux_config+0x2a>
+			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+    1bb2:	4c0d      	ldr	r4, [pc, #52]	; (1be8 <_system_pinmux_config+0xa4>)
+    1bb4:	4023      	ands	r3, r4
+    1bb6:	e7df      	b.n	1b78 <_system_pinmux_config+0x34>
+		port->DIRCLR.reg = pin_mask;
+    1bb8:	6041      	str	r1, [r0, #4]
+	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+    1bba:	040c      	lsls	r4, r1, #16
+    1bbc:	0c24      	lsrs	r4, r4, #16
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+    1bbe:	23a0      	movs	r3, #160	; 0xa0
+    1bc0:	05db      	lsls	r3, r3, #23
+    1bc2:	4323      	orrs	r3, r4
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+    1bc4:	6283      	str	r3, [r0, #40]	; 0x28
+	uint32_t upper_pin_mask = (pin_mask >> 16);
+    1bc6:	0c0c      	lsrs	r4, r1, #16
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+    1bc8:	23d0      	movs	r3, #208	; 0xd0
+    1bca:	061b      	lsls	r3, r3, #24
+    1bcc:	4323      	orrs	r3, r4
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+    1bce:	6283      	str	r3, [r0, #40]	; 0x28
+	if(!config->powersave) {
+    1bd0:	78d3      	ldrb	r3, [r2, #3]
+    1bd2:	2b00      	cmp	r3, #0
+    1bd4:	d103      	bne.n	1bde <_system_pinmux_config+0x9a>
+			}
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+    1bd6:	7853      	ldrb	r3, [r2, #1]
+    1bd8:	3b01      	subs	r3, #1
+    1bda:	2b01      	cmp	r3, #1
+    1bdc:	d902      	bls.n	1be4 <_system_pinmux_config+0xa0>
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Set the port DIR bits to enable the output buffer */
+			port->DIRSET.reg = pin_mask;
+		}
+	}
+}
+    1bde:	bd30      	pop	{r4, r5, pc}
+				port->OUTSET.reg = pin_mask;
+    1be0:	6181      	str	r1, [r0, #24]
+    1be2:	e7f8      	b.n	1bd6 <_system_pinmux_config+0x92>
+			port->DIRSET.reg = pin_mask;
+    1be4:	6081      	str	r1, [r0, #8]
+}
+    1be6:	e7fa      	b.n	1bde <_system_pinmux_config+0x9a>
+    1be8:	fffbffff 	.word	0xfffbffff
+
+00001bec <system_pinmux_pin_set_config>:
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config)
+{
+    1bec:	b510      	push	{r4, lr}
+    1bee:	000a      	movs	r2, r1
+	uint8_t group_index = (gpio_pin / 32);
+
+	/* Array of available ports */
+	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+	if (port_index < PORT_INST_NUM) {
+    1bf0:	09c1      	lsrs	r1, r0, #7
+		return &(ports[port_index]->Group[group_index]);
+	} else {
+		Assert(false);
+		return NULL;
+    1bf2:	2300      	movs	r3, #0
+	if (port_index < PORT_INST_NUM) {
+    1bf4:	2900      	cmp	r1, #0
+    1bf6:	d104      	bne.n	1c02 <system_pinmux_pin_set_config+0x16>
+		return &(ports[port_index]->Group[group_index]);
+    1bf8:	0943      	lsrs	r3, r0, #5
+    1bfa:	01db      	lsls	r3, r3, #7
+    1bfc:	4905      	ldr	r1, [pc, #20]	; (1c14 <system_pinmux_pin_set_config+0x28>)
+    1bfe:	468c      	mov	ip, r1
+    1c00:	4463      	add	r3, ip
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask = (1UL << (gpio_pin % 32));
+    1c02:	241f      	movs	r4, #31
+    1c04:	4020      	ands	r0, r4
+    1c06:	2101      	movs	r1, #1
+    1c08:	4081      	lsls	r1, r0
+
+	_system_pinmux_config(port, pin_mask, config);
+    1c0a:	0018      	movs	r0, r3
+    1c0c:	4b02      	ldr	r3, [pc, #8]	; (1c18 <system_pinmux_pin_set_config+0x2c>)
+    1c0e:	4798      	blx	r3
+}
+    1c10:	bd10      	pop	{r4, pc}
+    1c12:	46c0      	nop			; (mov r8, r8)
+    1c14:	41004400 	.word	0x41004400
+    1c18:	00001b45 	.word	0x00001b45
+
+00001c1c <_system_dummy_init>:
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+	return;
+}
+    1c1c:	4770      	bx	lr
+	...
+
+00001c20 <system_init>:
+ *  - Board hardware initialization (via the Board module)
+ *  - Event system driver initialization (via the EVSYS module)
+ *  - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+    1c20:	b510      	push	{r4, lr}
+	/* Configure GCLK and clock sources according to conf_clocks.h */
+	system_clock_init();
+    1c22:	4b05      	ldr	r3, [pc, #20]	; (1c38 <system_init+0x18>)
+    1c24:	4798      	blx	r3
+
+	/* Initialize board hardware */
+	system_board_init();
+    1c26:	4b05      	ldr	r3, [pc, #20]	; (1c3c <system_init+0x1c>)
+    1c28:	4798      	blx	r3
+
+	/* Initialize EVSYS hardware */
+	_system_events_init();
+    1c2a:	4b05      	ldr	r3, [pc, #20]	; (1c40 <system_init+0x20>)
+    1c2c:	4798      	blx	r3
+
+	/* Initialize External hardware */
+	_system_extint_init();
+    1c2e:	4b05      	ldr	r3, [pc, #20]	; (1c44 <system_init+0x24>)
+    1c30:	4798      	blx	r3
+	
+	/* Initialize DIVAS hardware */
+	_system_divas_init();
+    1c32:	4b05      	ldr	r3, [pc, #20]	; (1c48 <system_init+0x28>)
+    1c34:	4798      	blx	r3
+}
+    1c36:	bd10      	pop	{r4, pc}
+    1c38:	00001825 	.word	0x00001825
+    1c3c:	00001651 	.word	0x00001651
+    1c40:	00001c1d 	.word	0x00001c1d
+    1c44:	00001c1d 	.word	0x00001c1d
+    1c48:	00001c1d 	.word	0x00001c1d
+
+00001c4c <Dummy_Handler>:
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+    1c4c:	e7fe      	b.n	1c4c <Dummy_Handler>
+	...
+
+00001c50 <Reset_Handler>:
+{
+    1c50:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+        if (pSrc != pDest) {
+    1c52:	4a2a      	ldr	r2, [pc, #168]	; (1cfc <Reset_Handler+0xac>)
+    1c54:	4b2a      	ldr	r3, [pc, #168]	; (1d00 <Reset_Handler+0xb0>)
+    1c56:	429a      	cmp	r2, r3
+    1c58:	d011      	beq.n	1c7e <Reset_Handler+0x2e>
+                for (; pDest < &_erelocate;) {
+    1c5a:	001a      	movs	r2, r3
+    1c5c:	4b29      	ldr	r3, [pc, #164]	; (1d04 <Reset_Handler+0xb4>)
+    1c5e:	429a      	cmp	r2, r3
+    1c60:	d20d      	bcs.n	1c7e <Reset_Handler+0x2e>
+    1c62:	4a29      	ldr	r2, [pc, #164]	; (1d08 <Reset_Handler+0xb8>)
+    1c64:	3303      	adds	r3, #3
+    1c66:	1a9b      	subs	r3, r3, r2
+    1c68:	089b      	lsrs	r3, r3, #2
+    1c6a:	3301      	adds	r3, #1
+    1c6c:	009b      	lsls	r3, r3, #2
+    1c6e:	2200      	movs	r2, #0
+                        *pDest++ = *pSrc++;
+    1c70:	4823      	ldr	r0, [pc, #140]	; (1d00 <Reset_Handler+0xb0>)
+    1c72:	4922      	ldr	r1, [pc, #136]	; (1cfc <Reset_Handler+0xac>)
+    1c74:	588c      	ldr	r4, [r1, r2]
+    1c76:	5084      	str	r4, [r0, r2]
+    1c78:	3204      	adds	r2, #4
+                for (; pDest < &_erelocate;) {
+    1c7a:	429a      	cmp	r2, r3
+    1c7c:	d1fa      	bne.n	1c74 <Reset_Handler+0x24>
+        for (pDest = &_szero; pDest < &_ezero;) {
+    1c7e:	4a23      	ldr	r2, [pc, #140]	; (1d0c <Reset_Handler+0xbc>)
+    1c80:	4b23      	ldr	r3, [pc, #140]	; (1d10 <Reset_Handler+0xc0>)
+    1c82:	429a      	cmp	r2, r3
+    1c84:	d20a      	bcs.n	1c9c <Reset_Handler+0x4c>
+    1c86:	43d3      	mvns	r3, r2
+    1c88:	4921      	ldr	r1, [pc, #132]	; (1d10 <Reset_Handler+0xc0>)
+    1c8a:	185b      	adds	r3, r3, r1
+    1c8c:	2103      	movs	r1, #3
+    1c8e:	438b      	bics	r3, r1
+    1c90:	3304      	adds	r3, #4
+    1c92:	189b      	adds	r3, r3, r2
+                *pDest++ = 0;
+    1c94:	2100      	movs	r1, #0
+    1c96:	c202      	stmia	r2!, {r1}
+        for (pDest = &_szero; pDest < &_ezero;) {
+    1c98:	4293      	cmp	r3, r2
+    1c9a:	d1fc      	bne.n	1c96 <Reset_Handler+0x46>
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+    1c9c:	4a1d      	ldr	r2, [pc, #116]	; (1d14 <Reset_Handler+0xc4>)
+    1c9e:	21ff      	movs	r1, #255	; 0xff
+    1ca0:	4b1d      	ldr	r3, [pc, #116]	; (1d18 <Reset_Handler+0xc8>)
+    1ca2:	438b      	bics	r3, r1
+    1ca4:	6093      	str	r3, [r2, #8]
+        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+    1ca6:	39fd      	subs	r1, #253	; 0xfd
+    1ca8:	2390      	movs	r3, #144	; 0x90
+    1caa:	005b      	lsls	r3, r3, #1
+    1cac:	4a1b      	ldr	r2, [pc, #108]	; (1d1c <Reset_Handler+0xcc>)
+    1cae:	50d1      	str	r1, [r2, r3]
+        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+    1cb0:	4a1b      	ldr	r2, [pc, #108]	; (1d20 <Reset_Handler+0xd0>)
+    1cb2:	78d3      	ldrb	r3, [r2, #3]
+    1cb4:	2503      	movs	r5, #3
+    1cb6:	43ab      	bics	r3, r5
+    1cb8:	2402      	movs	r4, #2
+    1cba:	4323      	orrs	r3, r4
+    1cbc:	70d3      	strb	r3, [r2, #3]
+        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+    1cbe:	78d3      	ldrb	r3, [r2, #3]
+    1cc0:	270c      	movs	r7, #12
+    1cc2:	43bb      	bics	r3, r7
+    1cc4:	2608      	movs	r6, #8
+    1cc6:	4333      	orrs	r3, r6
+    1cc8:	70d3      	strb	r3, [r2, #3]
+        DMAC->QOSCTRL.bit.DQOS = 2;
+    1cca:	4b16      	ldr	r3, [pc, #88]	; (1d24 <Reset_Handler+0xd4>)
+    1ccc:	7b98      	ldrb	r0, [r3, #14]
+    1cce:	2230      	movs	r2, #48	; 0x30
+    1cd0:	4390      	bics	r0, r2
+    1cd2:	2220      	movs	r2, #32
+    1cd4:	4310      	orrs	r0, r2
+    1cd6:	7398      	strb	r0, [r3, #14]
+        DMAC->QOSCTRL.bit.FQOS = 2;
+    1cd8:	7b99      	ldrb	r1, [r3, #14]
+    1cda:	43b9      	bics	r1, r7
+    1cdc:	4331      	orrs	r1, r6
+    1cde:	7399      	strb	r1, [r3, #14]
+        DMAC->QOSCTRL.bit.WRBQOS = 2;
+    1ce0:	7b9a      	ldrb	r2, [r3, #14]
+    1ce2:	43aa      	bics	r2, r5
+    1ce4:	4322      	orrs	r2, r4
+    1ce6:	739a      	strb	r2, [r3, #14]
+        NVMCTRL->CTRLB.bit.MANW = 1;
+    1ce8:	4a0f      	ldr	r2, [pc, #60]	; (1d28 <Reset_Handler+0xd8>)
+    1cea:	6853      	ldr	r3, [r2, #4]
+    1cec:	2180      	movs	r1, #128	; 0x80
+    1cee:	430b      	orrs	r3, r1
+    1cf0:	6053      	str	r3, [r2, #4]
+        __libc_init_array();
+    1cf2:	4b0e      	ldr	r3, [pc, #56]	; (1d2c <Reset_Handler+0xdc>)
+    1cf4:	4798      	blx	r3
+        main();
+    1cf6:	4b0e      	ldr	r3, [pc, #56]	; (1d30 <Reset_Handler+0xe0>)
+    1cf8:	4798      	blx	r3
+    1cfa:	e7fe      	b.n	1cfa <Reset_Handler+0xaa>
+    1cfc:	00003960 	.word	0x00003960
+    1d00:	20000000 	.word	0x20000000
+    1d04:	2000007c 	.word	0x2000007c
+    1d08:	20000004 	.word	0x20000004
+    1d0c:	20000080 	.word	0x20000080
+    1d10:	200002a0 	.word	0x200002a0
+    1d14:	e000ed00 	.word	0xe000ed00
+    1d18:	00000000 	.word	0x00000000
+    1d1c:	41007000 	.word	0x41007000
+    1d20:	41005000 	.word	0x41005000
+    1d24:	41004800 	.word	0x41004800
+    1d28:	41004000 	.word	0x41004000
+    1d2c:	00002681 	.word	0x00002681
+    1d30:	00001d71 	.word	0x00001d71
+
+00001d34 <_sbrk>:
+extern void _exit(int status);
+extern void _kill(int pid, int sig);
+extern int _getpid(void);
+
+extern caddr_t _sbrk(int incr)
+{
+    1d34:	0003      	movs	r3, r0
+	static unsigned char *heap = NULL;
+	unsigned char *prev_heap;
+
+	if (heap == NULL) {
+    1d36:	4a06      	ldr	r2, [pc, #24]	; (1d50 <_sbrk+0x1c>)
+    1d38:	6812      	ldr	r2, [r2, #0]
+    1d3a:	2a00      	cmp	r2, #0
+    1d3c:	d004      	beq.n	1d48 <_sbrk+0x14>
+		heap = (unsigned char *)&_end;
+	}
+	prev_heap = heap;
+    1d3e:	4a04      	ldr	r2, [pc, #16]	; (1d50 <_sbrk+0x1c>)
+    1d40:	6810      	ldr	r0, [r2, #0]
+
+	heap += incr;
+    1d42:	18c3      	adds	r3, r0, r3
+    1d44:	6013      	str	r3, [r2, #0]
+
+	return (caddr_t) prev_heap;
+}
+    1d46:	4770      	bx	lr
+		heap = (unsigned char *)&_end;
+    1d48:	4902      	ldr	r1, [pc, #8]	; (1d54 <_sbrk+0x20>)
+    1d4a:	4a01      	ldr	r2, [pc, #4]	; (1d50 <_sbrk+0x1c>)
+    1d4c:	6011      	str	r1, [r2, #0]
+    1d4e:	e7f6      	b.n	1d3e <_sbrk+0xa>
+    1d50:	200001cc 	.word	0x200001cc
+    1d54:	200022a0 	.word	0x200022a0
+
+00001d58 <_close>:
+}
+
+extern int _close(int file)
+{
+	return -1;
+}
+    1d58:	2001      	movs	r0, #1
+    1d5a:	4240      	negs	r0, r0
+    1d5c:	4770      	bx	lr
+
+00001d5e <_fstat>:
+
+extern int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+    1d5e:	2380      	movs	r3, #128	; 0x80
+    1d60:	019b      	lsls	r3, r3, #6
+    1d62:	604b      	str	r3, [r1, #4]
+
+	return 0;
+}
+    1d64:	2000      	movs	r0, #0
+    1d66:	4770      	bx	lr
+
+00001d68 <_isatty>:
+
+extern int _isatty(int file)
+{
+	return 1;
+}
+    1d68:	2001      	movs	r0, #1
+    1d6a:	4770      	bx	lr
+
+00001d6c <_lseek>:
+
+extern int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+    1d6c:	2000      	movs	r0, #0
+    1d6e:	4770      	bx	lr
+
+00001d70 <main>:
+ */
+#include <asf.h>
+#include "pusart.h"
+#include "padc.h"
+int main (void)
+{
+    1d70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+	system_init();
+    1d72:	4b12      	ldr	r3, [pc, #72]	; (1dbc <main+0x4c>)
+    1d74:	4798      	blx	r3
+	delay_init();
+    1d76:	4b12      	ldr	r3, [pc, #72]	; (1dc0 <main+0x50>)
+    1d78:	4798      	blx	r3
+	
+	pusart_init();
+    1d7a:	4b12      	ldr	r3, [pc, #72]	; (1dc4 <main+0x54>)
+    1d7c:	4798      	blx	r3
+	padc_init();
+    1d7e:	4b12      	ldr	r3, [pc, #72]	; (1dc8 <main+0x58>)
+    1d80:	4798      	blx	r3
+	padc_start();
+    1d82:	4b12      	ldr	r3, [pc, #72]	; (1dcc <main+0x5c>)
+    1d84:	4798      	blx	r3
+	
+	for (;;)
+	{
+		float voltage = padc_get_voltage();
+    1d86:	4f12      	ldr	r7, [pc, #72]	; (1dd0 <main+0x60>)
+		printf("Voltage: %d.%03d\r\n", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
+    1d88:	4e12      	ldr	r6, [pc, #72]	; (1dd4 <main+0x64>)
+		float voltage = padc_get_voltage();
+    1d8a:	47b8      	blx	r7
+    1d8c:	1c05      	adds	r5, r0, #0
+		printf("Voltage: %d.%03d\r\n", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
+    1d8e:	47b0      	blx	r6
+    1d90:	0004      	movs	r4, r0
+    1d92:	4b11      	ldr	r3, [pc, #68]	; (1dd8 <main+0x68>)
+    1d94:	4798      	blx	r3
+    1d96:	1c01      	adds	r1, r0, #0
+    1d98:	1c28      	adds	r0, r5, #0
+    1d9a:	4b10      	ldr	r3, [pc, #64]	; (1ddc <main+0x6c>)
+    1d9c:	4798      	blx	r3
+    1d9e:	4910      	ldr	r1, [pc, #64]	; (1de0 <main+0x70>)
+    1da0:	4b10      	ldr	r3, [pc, #64]	; (1de4 <main+0x74>)
+    1da2:	4798      	blx	r3
+    1da4:	47b0      	blx	r6
+    1da6:	0002      	movs	r2, r0
+    1da8:	0021      	movs	r1, r4
+    1daa:	480f      	ldr	r0, [pc, #60]	; (1de8 <main+0x78>)
+    1dac:	4b0f      	ldr	r3, [pc, #60]	; (1dec <main+0x7c>)
+    1dae:	4798      	blx	r3
+		delay_ms(500);
+    1db0:	20fa      	movs	r0, #250	; 0xfa
+    1db2:	0040      	lsls	r0, r0, #1
+    1db4:	4b0e      	ldr	r3, [pc, #56]	; (1df0 <main+0x80>)
+    1db6:	4798      	blx	r3
+    1db8:	e7e7      	b.n	1d8a <main+0x1a>
+    1dba:	46c0      	nop			; (mov r8, r8)
+    1dbc:	00001c21 	.word	0x00001c21
+    1dc0:	00001575 	.word	0x00001575
+    1dc4:	00000e55 	.word	0x00000e55
+    1dc8:	00000cb9 	.word	0x00000cb9
+    1dcc:	00000d99 	.word	0x00000d99
+    1dd0:	00000de9 	.word	0x00000de9
+    1dd4:	000024d9 	.word	0x000024d9
+    1dd8:	00002519 	.word	0x00002519
+    1ddc:	000021a1 	.word	0x000021a1
+    1de0:	447a0000 	.word	0x447a0000
+    1de4:	00001f61 	.word	0x00001f61
+    1de8:	00003854 	.word	0x00003854
+    1dec:	000026ed 	.word	0x000026ed
+    1df0:	000015b5 	.word	0x000015b5
+
+00001df4 <__udivsi3>:
+    1df4:	2200      	movs	r2, #0
+    1df6:	0843      	lsrs	r3, r0, #1
+    1df8:	428b      	cmp	r3, r1
+    1dfa:	d374      	bcc.n	1ee6 <__udivsi3+0xf2>
+    1dfc:	0903      	lsrs	r3, r0, #4
+    1dfe:	428b      	cmp	r3, r1
+    1e00:	d35f      	bcc.n	1ec2 <__udivsi3+0xce>
+    1e02:	0a03      	lsrs	r3, r0, #8
+    1e04:	428b      	cmp	r3, r1
+    1e06:	d344      	bcc.n	1e92 <__udivsi3+0x9e>
+    1e08:	0b03      	lsrs	r3, r0, #12
+    1e0a:	428b      	cmp	r3, r1
+    1e0c:	d328      	bcc.n	1e60 <__udivsi3+0x6c>
+    1e0e:	0c03      	lsrs	r3, r0, #16
+    1e10:	428b      	cmp	r3, r1
+    1e12:	d30d      	bcc.n	1e30 <__udivsi3+0x3c>
+    1e14:	22ff      	movs	r2, #255	; 0xff
+    1e16:	0209      	lsls	r1, r1, #8
+    1e18:	ba12      	rev	r2, r2
+    1e1a:	0c03      	lsrs	r3, r0, #16
+    1e1c:	428b      	cmp	r3, r1
+    1e1e:	d302      	bcc.n	1e26 <__udivsi3+0x32>
+    1e20:	1212      	asrs	r2, r2, #8
+    1e22:	0209      	lsls	r1, r1, #8
+    1e24:	d065      	beq.n	1ef2 <__udivsi3+0xfe>
+    1e26:	0b03      	lsrs	r3, r0, #12
+    1e28:	428b      	cmp	r3, r1
+    1e2a:	d319      	bcc.n	1e60 <__udivsi3+0x6c>
+    1e2c:	e000      	b.n	1e30 <__udivsi3+0x3c>
+    1e2e:	0a09      	lsrs	r1, r1, #8
+    1e30:	0bc3      	lsrs	r3, r0, #15
+    1e32:	428b      	cmp	r3, r1
+    1e34:	d301      	bcc.n	1e3a <__udivsi3+0x46>
+    1e36:	03cb      	lsls	r3, r1, #15
+    1e38:	1ac0      	subs	r0, r0, r3
+    1e3a:	4152      	adcs	r2, r2
+    1e3c:	0b83      	lsrs	r3, r0, #14
+    1e3e:	428b      	cmp	r3, r1
+    1e40:	d301      	bcc.n	1e46 <__udivsi3+0x52>
+    1e42:	038b      	lsls	r3, r1, #14
+    1e44:	1ac0      	subs	r0, r0, r3
+    1e46:	4152      	adcs	r2, r2
+    1e48:	0b43      	lsrs	r3, r0, #13
+    1e4a:	428b      	cmp	r3, r1
+    1e4c:	d301      	bcc.n	1e52 <__udivsi3+0x5e>
+    1e4e:	034b      	lsls	r3, r1, #13
+    1e50:	1ac0      	subs	r0, r0, r3
+    1e52:	4152      	adcs	r2, r2
+    1e54:	0b03      	lsrs	r3, r0, #12
+    1e56:	428b      	cmp	r3, r1
+    1e58:	d301      	bcc.n	1e5e <__udivsi3+0x6a>
+    1e5a:	030b      	lsls	r3, r1, #12
+    1e5c:	1ac0      	subs	r0, r0, r3
+    1e5e:	4152      	adcs	r2, r2
+    1e60:	0ac3      	lsrs	r3, r0, #11
+    1e62:	428b      	cmp	r3, r1
+    1e64:	d301      	bcc.n	1e6a <__udivsi3+0x76>
+    1e66:	02cb      	lsls	r3, r1, #11
+    1e68:	1ac0      	subs	r0, r0, r3
+    1e6a:	4152      	adcs	r2, r2
+    1e6c:	0a83      	lsrs	r3, r0, #10
+    1e6e:	428b      	cmp	r3, r1
+    1e70:	d301      	bcc.n	1e76 <__udivsi3+0x82>
+    1e72:	028b      	lsls	r3, r1, #10
+    1e74:	1ac0      	subs	r0, r0, r3
+    1e76:	4152      	adcs	r2, r2
+    1e78:	0a43      	lsrs	r3, r0, #9
+    1e7a:	428b      	cmp	r3, r1
+    1e7c:	d301      	bcc.n	1e82 <__udivsi3+0x8e>
+    1e7e:	024b      	lsls	r3, r1, #9
+    1e80:	1ac0      	subs	r0, r0, r3
+    1e82:	4152      	adcs	r2, r2
+    1e84:	0a03      	lsrs	r3, r0, #8
+    1e86:	428b      	cmp	r3, r1
+    1e88:	d301      	bcc.n	1e8e <__udivsi3+0x9a>
+    1e8a:	020b      	lsls	r3, r1, #8
+    1e8c:	1ac0      	subs	r0, r0, r3
+    1e8e:	4152      	adcs	r2, r2
+    1e90:	d2cd      	bcs.n	1e2e <__udivsi3+0x3a>
+    1e92:	09c3      	lsrs	r3, r0, #7
+    1e94:	428b      	cmp	r3, r1
+    1e96:	d301      	bcc.n	1e9c <__udivsi3+0xa8>
+    1e98:	01cb      	lsls	r3, r1, #7
+    1e9a:	1ac0      	subs	r0, r0, r3
+    1e9c:	4152      	adcs	r2, r2
+    1e9e:	0983      	lsrs	r3, r0, #6
+    1ea0:	428b      	cmp	r3, r1
+    1ea2:	d301      	bcc.n	1ea8 <__udivsi3+0xb4>
+    1ea4:	018b      	lsls	r3, r1, #6
+    1ea6:	1ac0      	subs	r0, r0, r3
+    1ea8:	4152      	adcs	r2, r2
+    1eaa:	0943      	lsrs	r3, r0, #5
+    1eac:	428b      	cmp	r3, r1
+    1eae:	d301      	bcc.n	1eb4 <__udivsi3+0xc0>
+    1eb0:	014b      	lsls	r3, r1, #5
+    1eb2:	1ac0      	subs	r0, r0, r3
+    1eb4:	4152      	adcs	r2, r2
+    1eb6:	0903      	lsrs	r3, r0, #4
+    1eb8:	428b      	cmp	r3, r1
+    1eba:	d301      	bcc.n	1ec0 <__udivsi3+0xcc>
+    1ebc:	010b      	lsls	r3, r1, #4
+    1ebe:	1ac0      	subs	r0, r0, r3
+    1ec0:	4152      	adcs	r2, r2
+    1ec2:	08c3      	lsrs	r3, r0, #3
+    1ec4:	428b      	cmp	r3, r1
+    1ec6:	d301      	bcc.n	1ecc <__udivsi3+0xd8>
+    1ec8:	00cb      	lsls	r3, r1, #3
+    1eca:	1ac0      	subs	r0, r0, r3
+    1ecc:	4152      	adcs	r2, r2
+    1ece:	0883      	lsrs	r3, r0, #2
+    1ed0:	428b      	cmp	r3, r1
+    1ed2:	d301      	bcc.n	1ed8 <__udivsi3+0xe4>
+    1ed4:	008b      	lsls	r3, r1, #2
+    1ed6:	1ac0      	subs	r0, r0, r3
+    1ed8:	4152      	adcs	r2, r2
+    1eda:	0843      	lsrs	r3, r0, #1
+    1edc:	428b      	cmp	r3, r1
+    1ede:	d301      	bcc.n	1ee4 <__udivsi3+0xf0>
+    1ee0:	004b      	lsls	r3, r1, #1
+    1ee2:	1ac0      	subs	r0, r0, r3
+    1ee4:	4152      	adcs	r2, r2
+    1ee6:	1a41      	subs	r1, r0, r1
+    1ee8:	d200      	bcs.n	1eec <__udivsi3+0xf8>
+    1eea:	4601      	mov	r1, r0
+    1eec:	4152      	adcs	r2, r2
+    1eee:	4610      	mov	r0, r2
+    1ef0:	4770      	bx	lr
+    1ef2:	e7ff      	b.n	1ef4 <__udivsi3+0x100>
+    1ef4:	b501      	push	{r0, lr}
+    1ef6:	2000      	movs	r0, #0
+    1ef8:	f000 f806 	bl	1f08 <__aeabi_idiv0>
+    1efc:	bd02      	pop	{r1, pc}
+    1efe:	46c0      	nop			; (mov r8, r8)
+
+00001f00 <__aeabi_uidivmod>:
+    1f00:	2900      	cmp	r1, #0
+    1f02:	d0f7      	beq.n	1ef4 <__udivsi3+0x100>
+    1f04:	e776      	b.n	1df4 <__udivsi3>
+    1f06:	4770      	bx	lr
+
+00001f08 <__aeabi_idiv0>:
+    1f08:	4770      	bx	lr
+    1f0a:	46c0      	nop			; (mov r8, r8)
+
+00001f0c <__aeabi_lmul>:
+    1f0c:	b5f0      	push	{r4, r5, r6, r7, lr}
+    1f0e:	46ce      	mov	lr, r9
+    1f10:	4647      	mov	r7, r8
+    1f12:	0415      	lsls	r5, r2, #16
+    1f14:	0c2d      	lsrs	r5, r5, #16
+    1f16:	002e      	movs	r6, r5
+    1f18:	b580      	push	{r7, lr}
+    1f1a:	0407      	lsls	r7, r0, #16
+    1f1c:	0c14      	lsrs	r4, r2, #16
+    1f1e:	0c3f      	lsrs	r7, r7, #16
+    1f20:	4699      	mov	r9, r3
+    1f22:	0c03      	lsrs	r3, r0, #16
+    1f24:	437e      	muls	r6, r7
+    1f26:	435d      	muls	r5, r3
+    1f28:	4367      	muls	r7, r4
+    1f2a:	4363      	muls	r3, r4
+    1f2c:	197f      	adds	r7, r7, r5
+    1f2e:	0c34      	lsrs	r4, r6, #16
+    1f30:	19e4      	adds	r4, r4, r7
+    1f32:	469c      	mov	ip, r3
+    1f34:	42a5      	cmp	r5, r4
+    1f36:	d903      	bls.n	1f40 <__aeabi_lmul+0x34>
+    1f38:	2380      	movs	r3, #128	; 0x80
+    1f3a:	025b      	lsls	r3, r3, #9
+    1f3c:	4698      	mov	r8, r3
+    1f3e:	44c4      	add	ip, r8
+    1f40:	464b      	mov	r3, r9
+    1f42:	4351      	muls	r1, r2
+    1f44:	4343      	muls	r3, r0
+    1f46:	0436      	lsls	r6, r6, #16
+    1f48:	0c36      	lsrs	r6, r6, #16
+    1f4a:	0c25      	lsrs	r5, r4, #16
+    1f4c:	0424      	lsls	r4, r4, #16
+    1f4e:	4465      	add	r5, ip
+    1f50:	19a4      	adds	r4, r4, r6
+    1f52:	1859      	adds	r1, r3, r1
+    1f54:	1949      	adds	r1, r1, r5
+    1f56:	0020      	movs	r0, r4
+    1f58:	bc0c      	pop	{r2, r3}
+    1f5a:	4690      	mov	r8, r2
+    1f5c:	4699      	mov	r9, r3
+    1f5e:	bdf0      	pop	{r4, r5, r6, r7, pc}
+
+00001f60 <__aeabi_fmul>:
+    1f60:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    1f62:	4657      	mov	r7, sl
+    1f64:	464e      	mov	r6, r9
+    1f66:	4645      	mov	r5, r8
+    1f68:	46de      	mov	lr, fp
+    1f6a:	b5e0      	push	{r5, r6, r7, lr}
+    1f6c:	0247      	lsls	r7, r0, #9
+    1f6e:	0046      	lsls	r6, r0, #1
+    1f70:	4688      	mov	r8, r1
+    1f72:	0a7f      	lsrs	r7, r7, #9
+    1f74:	0e36      	lsrs	r6, r6, #24
+    1f76:	0fc4      	lsrs	r4, r0, #31
+    1f78:	2e00      	cmp	r6, #0
+    1f7a:	d047      	beq.n	200c <STACK_SIZE+0xc>
+    1f7c:	2eff      	cmp	r6, #255	; 0xff
+    1f7e:	d024      	beq.n	1fca <__aeabi_fmul+0x6a>
+    1f80:	00fb      	lsls	r3, r7, #3
+    1f82:	2780      	movs	r7, #128	; 0x80
+    1f84:	04ff      	lsls	r7, r7, #19
+    1f86:	431f      	orrs	r7, r3
+    1f88:	2300      	movs	r3, #0
+    1f8a:	4699      	mov	r9, r3
+    1f8c:	469a      	mov	sl, r3
+    1f8e:	3e7f      	subs	r6, #127	; 0x7f
+    1f90:	4643      	mov	r3, r8
+    1f92:	025d      	lsls	r5, r3, #9
+    1f94:	0058      	lsls	r0, r3, #1
+    1f96:	0fdb      	lsrs	r3, r3, #31
+    1f98:	0a6d      	lsrs	r5, r5, #9
+    1f9a:	0e00      	lsrs	r0, r0, #24
+    1f9c:	4698      	mov	r8, r3
+    1f9e:	d043      	beq.n	2028 <STACK_SIZE+0x28>
+    1fa0:	28ff      	cmp	r0, #255	; 0xff
+    1fa2:	d03b      	beq.n	201c <STACK_SIZE+0x1c>
+    1fa4:	00eb      	lsls	r3, r5, #3
+    1fa6:	2580      	movs	r5, #128	; 0x80
+    1fa8:	2200      	movs	r2, #0
+    1faa:	04ed      	lsls	r5, r5, #19
+    1fac:	431d      	orrs	r5, r3
+    1fae:	387f      	subs	r0, #127	; 0x7f
+    1fb0:	1836      	adds	r6, r6, r0
+    1fb2:	1c73      	adds	r3, r6, #1
+    1fb4:	4641      	mov	r1, r8
+    1fb6:	469b      	mov	fp, r3
+    1fb8:	464b      	mov	r3, r9
+    1fba:	4061      	eors	r1, r4
+    1fbc:	4313      	orrs	r3, r2
+    1fbe:	2b0f      	cmp	r3, #15
+    1fc0:	d864      	bhi.n	208c <STACK_SIZE+0x8c>
+    1fc2:	4875      	ldr	r0, [pc, #468]	; (2198 <STACK_SIZE+0x198>)
+    1fc4:	009b      	lsls	r3, r3, #2
+    1fc6:	58c3      	ldr	r3, [r0, r3]
+    1fc8:	469f      	mov	pc, r3
+    1fca:	2f00      	cmp	r7, #0
+    1fcc:	d142      	bne.n	2054 <STACK_SIZE+0x54>
+    1fce:	2308      	movs	r3, #8
+    1fd0:	4699      	mov	r9, r3
+    1fd2:	3b06      	subs	r3, #6
+    1fd4:	26ff      	movs	r6, #255	; 0xff
+    1fd6:	469a      	mov	sl, r3
+    1fd8:	e7da      	b.n	1f90 <__aeabi_fmul+0x30>
+    1fda:	4641      	mov	r1, r8
+    1fdc:	2a02      	cmp	r2, #2
+    1fde:	d028      	beq.n	2032 <STACK_SIZE+0x32>
+    1fe0:	2a03      	cmp	r2, #3
+    1fe2:	d100      	bne.n	1fe6 <__aeabi_fmul+0x86>
+    1fe4:	e0ce      	b.n	2184 <STACK_SIZE+0x184>
+    1fe6:	2a01      	cmp	r2, #1
+    1fe8:	d000      	beq.n	1fec <__aeabi_fmul+0x8c>
+    1fea:	e0ac      	b.n	2146 <STACK_SIZE+0x146>
+    1fec:	4011      	ands	r1, r2
+    1fee:	2000      	movs	r0, #0
+    1ff0:	2200      	movs	r2, #0
+    1ff2:	b2cc      	uxtb	r4, r1
+    1ff4:	0240      	lsls	r0, r0, #9
+    1ff6:	05d2      	lsls	r2, r2, #23
+    1ff8:	0a40      	lsrs	r0, r0, #9
+    1ffa:	07e4      	lsls	r4, r4, #31
+    1ffc:	4310      	orrs	r0, r2
+    1ffe:	4320      	orrs	r0, r4
+    2000:	bc3c      	pop	{r2, r3, r4, r5}
+    2002:	4690      	mov	r8, r2
+    2004:	4699      	mov	r9, r3
+    2006:	46a2      	mov	sl, r4
+    2008:	46ab      	mov	fp, r5
+    200a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    200c:	2f00      	cmp	r7, #0
+    200e:	d115      	bne.n	203c <STACK_SIZE+0x3c>
+    2010:	2304      	movs	r3, #4
+    2012:	4699      	mov	r9, r3
+    2014:	3b03      	subs	r3, #3
+    2016:	2600      	movs	r6, #0
+    2018:	469a      	mov	sl, r3
+    201a:	e7b9      	b.n	1f90 <__aeabi_fmul+0x30>
+    201c:	20ff      	movs	r0, #255	; 0xff
+    201e:	2202      	movs	r2, #2
+    2020:	2d00      	cmp	r5, #0
+    2022:	d0c5      	beq.n	1fb0 <__aeabi_fmul+0x50>
+    2024:	2203      	movs	r2, #3
+    2026:	e7c3      	b.n	1fb0 <__aeabi_fmul+0x50>
+    2028:	2d00      	cmp	r5, #0
+    202a:	d119      	bne.n	2060 <STACK_SIZE+0x60>
+    202c:	2000      	movs	r0, #0
+    202e:	2201      	movs	r2, #1
+    2030:	e7be      	b.n	1fb0 <__aeabi_fmul+0x50>
+    2032:	2401      	movs	r4, #1
+    2034:	22ff      	movs	r2, #255	; 0xff
+    2036:	400c      	ands	r4, r1
+    2038:	2000      	movs	r0, #0
+    203a:	e7db      	b.n	1ff4 <__aeabi_fmul+0x94>
+    203c:	0038      	movs	r0, r7
+    203e:	f000 fb01 	bl	2644 <__clzsi2>
+    2042:	2676      	movs	r6, #118	; 0x76
+    2044:	1f43      	subs	r3, r0, #5
+    2046:	409f      	lsls	r7, r3
+    2048:	2300      	movs	r3, #0
+    204a:	4276      	negs	r6, r6
+    204c:	1a36      	subs	r6, r6, r0
+    204e:	4699      	mov	r9, r3
+    2050:	469a      	mov	sl, r3
+    2052:	e79d      	b.n	1f90 <__aeabi_fmul+0x30>
+    2054:	230c      	movs	r3, #12
+    2056:	4699      	mov	r9, r3
+    2058:	3b09      	subs	r3, #9
+    205a:	26ff      	movs	r6, #255	; 0xff
+    205c:	469a      	mov	sl, r3
+    205e:	e797      	b.n	1f90 <__aeabi_fmul+0x30>
+    2060:	0028      	movs	r0, r5
+    2062:	f000 faef 	bl	2644 <__clzsi2>
+    2066:	1f43      	subs	r3, r0, #5
+    2068:	409d      	lsls	r5, r3
+    206a:	2376      	movs	r3, #118	; 0x76
+    206c:	425b      	negs	r3, r3
+    206e:	1a18      	subs	r0, r3, r0
+    2070:	2200      	movs	r2, #0
+    2072:	e79d      	b.n	1fb0 <__aeabi_fmul+0x50>
+    2074:	2080      	movs	r0, #128	; 0x80
+    2076:	2400      	movs	r4, #0
+    2078:	03c0      	lsls	r0, r0, #15
+    207a:	22ff      	movs	r2, #255	; 0xff
+    207c:	e7ba      	b.n	1ff4 <__aeabi_fmul+0x94>
+    207e:	003d      	movs	r5, r7
+    2080:	4652      	mov	r2, sl
+    2082:	e7ab      	b.n	1fdc <__aeabi_fmul+0x7c>
+    2084:	003d      	movs	r5, r7
+    2086:	0021      	movs	r1, r4
+    2088:	4652      	mov	r2, sl
+    208a:	e7a7      	b.n	1fdc <__aeabi_fmul+0x7c>
+    208c:	0c3b      	lsrs	r3, r7, #16
+    208e:	469c      	mov	ip, r3
+    2090:	042a      	lsls	r2, r5, #16
+    2092:	0c12      	lsrs	r2, r2, #16
+    2094:	0c2b      	lsrs	r3, r5, #16
+    2096:	0014      	movs	r4, r2
+    2098:	4660      	mov	r0, ip
+    209a:	4665      	mov	r5, ip
+    209c:	043f      	lsls	r7, r7, #16
+    209e:	0c3f      	lsrs	r7, r7, #16
+    20a0:	437c      	muls	r4, r7
+    20a2:	4342      	muls	r2, r0
+    20a4:	435d      	muls	r5, r3
+    20a6:	437b      	muls	r3, r7
+    20a8:	0c27      	lsrs	r7, r4, #16
+    20aa:	189b      	adds	r3, r3, r2
+    20ac:	18ff      	adds	r7, r7, r3
+    20ae:	42ba      	cmp	r2, r7
+    20b0:	d903      	bls.n	20ba <STACK_SIZE+0xba>
+    20b2:	2380      	movs	r3, #128	; 0x80
+    20b4:	025b      	lsls	r3, r3, #9
+    20b6:	469c      	mov	ip, r3
+    20b8:	4465      	add	r5, ip
+    20ba:	0424      	lsls	r4, r4, #16
+    20bc:	043a      	lsls	r2, r7, #16
+    20be:	0c24      	lsrs	r4, r4, #16
+    20c0:	1912      	adds	r2, r2, r4
+    20c2:	0193      	lsls	r3, r2, #6
+    20c4:	1e5c      	subs	r4, r3, #1
+    20c6:	41a3      	sbcs	r3, r4
+    20c8:	0c3f      	lsrs	r7, r7, #16
+    20ca:	0e92      	lsrs	r2, r2, #26
+    20cc:	197d      	adds	r5, r7, r5
+    20ce:	431a      	orrs	r2, r3
+    20d0:	01ad      	lsls	r5, r5, #6
+    20d2:	4315      	orrs	r5, r2
+    20d4:	012b      	lsls	r3, r5, #4
+    20d6:	d504      	bpl.n	20e2 <STACK_SIZE+0xe2>
+    20d8:	2301      	movs	r3, #1
+    20da:	465e      	mov	r6, fp
+    20dc:	086a      	lsrs	r2, r5, #1
+    20de:	401d      	ands	r5, r3
+    20e0:	4315      	orrs	r5, r2
+    20e2:	0032      	movs	r2, r6
+    20e4:	327f      	adds	r2, #127	; 0x7f
+    20e6:	2a00      	cmp	r2, #0
+    20e8:	dd25      	ble.n	2136 <STACK_SIZE+0x136>
+    20ea:	076b      	lsls	r3, r5, #29
+    20ec:	d004      	beq.n	20f8 <STACK_SIZE+0xf8>
+    20ee:	230f      	movs	r3, #15
+    20f0:	402b      	ands	r3, r5
+    20f2:	2b04      	cmp	r3, #4
+    20f4:	d000      	beq.n	20f8 <STACK_SIZE+0xf8>
+    20f6:	3504      	adds	r5, #4
+    20f8:	012b      	lsls	r3, r5, #4
+    20fa:	d503      	bpl.n	2104 <STACK_SIZE+0x104>
+    20fc:	0032      	movs	r2, r6
+    20fe:	4b27      	ldr	r3, [pc, #156]	; (219c <STACK_SIZE+0x19c>)
+    2100:	3280      	adds	r2, #128	; 0x80
+    2102:	401d      	ands	r5, r3
+    2104:	2afe      	cmp	r2, #254	; 0xfe
+    2106:	dc94      	bgt.n	2032 <STACK_SIZE+0x32>
+    2108:	2401      	movs	r4, #1
+    210a:	01a8      	lsls	r0, r5, #6
+    210c:	0a40      	lsrs	r0, r0, #9
+    210e:	b2d2      	uxtb	r2, r2
+    2110:	400c      	ands	r4, r1
+    2112:	e76f      	b.n	1ff4 <__aeabi_fmul+0x94>
+    2114:	2080      	movs	r0, #128	; 0x80
+    2116:	03c0      	lsls	r0, r0, #15
+    2118:	4207      	tst	r7, r0
+    211a:	d007      	beq.n	212c <STACK_SIZE+0x12c>
+    211c:	4205      	tst	r5, r0
+    211e:	d105      	bne.n	212c <STACK_SIZE+0x12c>
+    2120:	4328      	orrs	r0, r5
+    2122:	0240      	lsls	r0, r0, #9
+    2124:	0a40      	lsrs	r0, r0, #9
+    2126:	4644      	mov	r4, r8
+    2128:	22ff      	movs	r2, #255	; 0xff
+    212a:	e763      	b.n	1ff4 <__aeabi_fmul+0x94>
+    212c:	4338      	orrs	r0, r7
+    212e:	0240      	lsls	r0, r0, #9
+    2130:	0a40      	lsrs	r0, r0, #9
+    2132:	22ff      	movs	r2, #255	; 0xff
+    2134:	e75e      	b.n	1ff4 <__aeabi_fmul+0x94>
+    2136:	2401      	movs	r4, #1
+    2138:	1aa3      	subs	r3, r4, r2
+    213a:	2b1b      	cmp	r3, #27
+    213c:	dd05      	ble.n	214a <STACK_SIZE+0x14a>
+    213e:	400c      	ands	r4, r1
+    2140:	2200      	movs	r2, #0
+    2142:	2000      	movs	r0, #0
+    2144:	e756      	b.n	1ff4 <__aeabi_fmul+0x94>
+    2146:	465e      	mov	r6, fp
+    2148:	e7cb      	b.n	20e2 <STACK_SIZE+0xe2>
+    214a:	002a      	movs	r2, r5
+    214c:	2020      	movs	r0, #32
+    214e:	40da      	lsrs	r2, r3
+    2150:	1ac3      	subs	r3, r0, r3
+    2152:	409d      	lsls	r5, r3
+    2154:	002b      	movs	r3, r5
+    2156:	1e5d      	subs	r5, r3, #1
+    2158:	41ab      	sbcs	r3, r5
+    215a:	4313      	orrs	r3, r2
+    215c:	075a      	lsls	r2, r3, #29
+    215e:	d004      	beq.n	216a <STACK_SIZE+0x16a>
+    2160:	220f      	movs	r2, #15
+    2162:	401a      	ands	r2, r3
+    2164:	2a04      	cmp	r2, #4
+    2166:	d000      	beq.n	216a <STACK_SIZE+0x16a>
+    2168:	3304      	adds	r3, #4
+    216a:	015a      	lsls	r2, r3, #5
+    216c:	d504      	bpl.n	2178 <STACK_SIZE+0x178>
+    216e:	2401      	movs	r4, #1
+    2170:	2201      	movs	r2, #1
+    2172:	400c      	ands	r4, r1
+    2174:	2000      	movs	r0, #0
+    2176:	e73d      	b.n	1ff4 <__aeabi_fmul+0x94>
+    2178:	2401      	movs	r4, #1
+    217a:	019b      	lsls	r3, r3, #6
+    217c:	0a58      	lsrs	r0, r3, #9
+    217e:	400c      	ands	r4, r1
+    2180:	2200      	movs	r2, #0
+    2182:	e737      	b.n	1ff4 <__aeabi_fmul+0x94>
+    2184:	2080      	movs	r0, #128	; 0x80
+    2186:	2401      	movs	r4, #1
+    2188:	03c0      	lsls	r0, r0, #15
+    218a:	4328      	orrs	r0, r5
+    218c:	0240      	lsls	r0, r0, #9
+    218e:	0a40      	lsrs	r0, r0, #9
+    2190:	400c      	ands	r4, r1
+    2192:	22ff      	movs	r2, #255	; 0xff
+    2194:	e72e      	b.n	1ff4 <__aeabi_fmul+0x94>
+    2196:	46c0      	nop			; (mov r8, r8)
+    2198:	00003868 	.word	0x00003868
+    219c:	f7ffffff 	.word	0xf7ffffff
+
+000021a0 <__aeabi_fsub>:
+    21a0:	b5f0      	push	{r4, r5, r6, r7, lr}
+    21a2:	464f      	mov	r7, r9
+    21a4:	46d6      	mov	lr, sl
+    21a6:	4646      	mov	r6, r8
+    21a8:	0044      	lsls	r4, r0, #1
+    21aa:	b5c0      	push	{r6, r7, lr}
+    21ac:	0fc2      	lsrs	r2, r0, #31
+    21ae:	0247      	lsls	r7, r0, #9
+    21b0:	0248      	lsls	r0, r1, #9
+    21b2:	0a40      	lsrs	r0, r0, #9
+    21b4:	4684      	mov	ip, r0
+    21b6:	4666      	mov	r6, ip
+    21b8:	0a7b      	lsrs	r3, r7, #9
+    21ba:	0048      	lsls	r0, r1, #1
+    21bc:	0fc9      	lsrs	r1, r1, #31
+    21be:	469a      	mov	sl, r3
+    21c0:	0e24      	lsrs	r4, r4, #24
+    21c2:	0015      	movs	r5, r2
+    21c4:	00db      	lsls	r3, r3, #3
+    21c6:	0e00      	lsrs	r0, r0, #24
+    21c8:	4689      	mov	r9, r1
+    21ca:	00f6      	lsls	r6, r6, #3
+    21cc:	28ff      	cmp	r0, #255	; 0xff
+    21ce:	d100      	bne.n	21d2 <__aeabi_fsub+0x32>
+    21d0:	e08f      	b.n	22f2 <__aeabi_fsub+0x152>
+    21d2:	2101      	movs	r1, #1
+    21d4:	464f      	mov	r7, r9
+    21d6:	404f      	eors	r7, r1
+    21d8:	0039      	movs	r1, r7
+    21da:	4291      	cmp	r1, r2
+    21dc:	d066      	beq.n	22ac <__aeabi_fsub+0x10c>
+    21de:	1a22      	subs	r2, r4, r0
+    21e0:	2a00      	cmp	r2, #0
+    21e2:	dc00      	bgt.n	21e6 <__aeabi_fsub+0x46>
+    21e4:	e09d      	b.n	2322 <__aeabi_fsub+0x182>
+    21e6:	2800      	cmp	r0, #0
+    21e8:	d13d      	bne.n	2266 <__aeabi_fsub+0xc6>
+    21ea:	2e00      	cmp	r6, #0
+    21ec:	d100      	bne.n	21f0 <__aeabi_fsub+0x50>
+    21ee:	e08b      	b.n	2308 <__aeabi_fsub+0x168>
+    21f0:	1e51      	subs	r1, r2, #1
+    21f2:	2900      	cmp	r1, #0
+    21f4:	d000      	beq.n	21f8 <__aeabi_fsub+0x58>
+    21f6:	e0b5      	b.n	2364 <__aeabi_fsub+0x1c4>
+    21f8:	2401      	movs	r4, #1
+    21fa:	1b9b      	subs	r3, r3, r6
+    21fc:	015a      	lsls	r2, r3, #5
+    21fe:	d544      	bpl.n	228a <__aeabi_fsub+0xea>
+    2200:	019b      	lsls	r3, r3, #6
+    2202:	099f      	lsrs	r7, r3, #6
+    2204:	0038      	movs	r0, r7
+    2206:	f000 fa1d 	bl	2644 <__clzsi2>
+    220a:	3805      	subs	r0, #5
+    220c:	4087      	lsls	r7, r0
+    220e:	4284      	cmp	r4, r0
+    2210:	dd00      	ble.n	2214 <__aeabi_fsub+0x74>
+    2212:	e096      	b.n	2342 <__aeabi_fsub+0x1a2>
+    2214:	1b04      	subs	r4, r0, r4
+    2216:	003a      	movs	r2, r7
+    2218:	2020      	movs	r0, #32
+    221a:	3401      	adds	r4, #1
+    221c:	40e2      	lsrs	r2, r4
+    221e:	1b04      	subs	r4, r0, r4
+    2220:	40a7      	lsls	r7, r4
+    2222:	003b      	movs	r3, r7
+    2224:	1e5f      	subs	r7, r3, #1
+    2226:	41bb      	sbcs	r3, r7
+    2228:	2400      	movs	r4, #0
+    222a:	4313      	orrs	r3, r2
+    222c:	075a      	lsls	r2, r3, #29
+    222e:	d004      	beq.n	223a <__aeabi_fsub+0x9a>
+    2230:	220f      	movs	r2, #15
+    2232:	401a      	ands	r2, r3
+    2234:	2a04      	cmp	r2, #4
+    2236:	d000      	beq.n	223a <__aeabi_fsub+0x9a>
+    2238:	3304      	adds	r3, #4
+    223a:	015a      	lsls	r2, r3, #5
+    223c:	d527      	bpl.n	228e <__aeabi_fsub+0xee>
+    223e:	3401      	adds	r4, #1
+    2240:	2cff      	cmp	r4, #255	; 0xff
+    2242:	d100      	bne.n	2246 <__aeabi_fsub+0xa6>
+    2244:	e079      	b.n	233a <__aeabi_fsub+0x19a>
+    2246:	2201      	movs	r2, #1
+    2248:	019b      	lsls	r3, r3, #6
+    224a:	0a5b      	lsrs	r3, r3, #9
+    224c:	b2e4      	uxtb	r4, r4
+    224e:	402a      	ands	r2, r5
+    2250:	025b      	lsls	r3, r3, #9
+    2252:	05e4      	lsls	r4, r4, #23
+    2254:	0a58      	lsrs	r0, r3, #9
+    2256:	07d2      	lsls	r2, r2, #31
+    2258:	4320      	orrs	r0, r4
+    225a:	4310      	orrs	r0, r2
+    225c:	bc1c      	pop	{r2, r3, r4}
+    225e:	4690      	mov	r8, r2
+    2260:	4699      	mov	r9, r3
+    2262:	46a2      	mov	sl, r4
+    2264:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    2266:	2cff      	cmp	r4, #255	; 0xff
+    2268:	d0e0      	beq.n	222c <__aeabi_fsub+0x8c>
+    226a:	2180      	movs	r1, #128	; 0x80
+    226c:	04c9      	lsls	r1, r1, #19
+    226e:	430e      	orrs	r6, r1
+    2270:	2a1b      	cmp	r2, #27
+    2272:	dc7b      	bgt.n	236c <__aeabi_fsub+0x1cc>
+    2274:	0031      	movs	r1, r6
+    2276:	2020      	movs	r0, #32
+    2278:	40d1      	lsrs	r1, r2
+    227a:	1a82      	subs	r2, r0, r2
+    227c:	4096      	lsls	r6, r2
+    227e:	1e72      	subs	r2, r6, #1
+    2280:	4196      	sbcs	r6, r2
+    2282:	430e      	orrs	r6, r1
+    2284:	1b9b      	subs	r3, r3, r6
+    2286:	015a      	lsls	r2, r3, #5
+    2288:	d4ba      	bmi.n	2200 <__aeabi_fsub+0x60>
+    228a:	075a      	lsls	r2, r3, #29
+    228c:	d1d0      	bne.n	2230 <__aeabi_fsub+0x90>
+    228e:	2201      	movs	r2, #1
+    2290:	08df      	lsrs	r7, r3, #3
+    2292:	402a      	ands	r2, r5
+    2294:	2cff      	cmp	r4, #255	; 0xff
+    2296:	d133      	bne.n	2300 <__aeabi_fsub+0x160>
+    2298:	2f00      	cmp	r7, #0
+    229a:	d100      	bne.n	229e <__aeabi_fsub+0xfe>
+    229c:	e0a8      	b.n	23f0 <__aeabi_fsub+0x250>
+    229e:	2380      	movs	r3, #128	; 0x80
+    22a0:	03db      	lsls	r3, r3, #15
+    22a2:	433b      	orrs	r3, r7
+    22a4:	025b      	lsls	r3, r3, #9
+    22a6:	0a5b      	lsrs	r3, r3, #9
+    22a8:	24ff      	movs	r4, #255	; 0xff
+    22aa:	e7d1      	b.n	2250 <__aeabi_fsub+0xb0>
+    22ac:	1a21      	subs	r1, r4, r0
+    22ae:	2900      	cmp	r1, #0
+    22b0:	dd4c      	ble.n	234c <__aeabi_fsub+0x1ac>
+    22b2:	2800      	cmp	r0, #0
+    22b4:	d02a      	beq.n	230c <__aeabi_fsub+0x16c>
+    22b6:	2cff      	cmp	r4, #255	; 0xff
+    22b8:	d0b8      	beq.n	222c <__aeabi_fsub+0x8c>
+    22ba:	2080      	movs	r0, #128	; 0x80
+    22bc:	04c0      	lsls	r0, r0, #19
+    22be:	4306      	orrs	r6, r0
+    22c0:	291b      	cmp	r1, #27
+    22c2:	dd00      	ble.n	22c6 <__aeabi_fsub+0x126>
+    22c4:	e0af      	b.n	2426 <__aeabi_fsub+0x286>
+    22c6:	0030      	movs	r0, r6
+    22c8:	2720      	movs	r7, #32
+    22ca:	40c8      	lsrs	r0, r1
+    22cc:	1a79      	subs	r1, r7, r1
+    22ce:	408e      	lsls	r6, r1
+    22d0:	1e71      	subs	r1, r6, #1
+    22d2:	418e      	sbcs	r6, r1
+    22d4:	4306      	orrs	r6, r0
+    22d6:	199b      	adds	r3, r3, r6
+    22d8:	0159      	lsls	r1, r3, #5
+    22da:	d5d6      	bpl.n	228a <__aeabi_fsub+0xea>
+    22dc:	3401      	adds	r4, #1
+    22de:	2cff      	cmp	r4, #255	; 0xff
+    22e0:	d100      	bne.n	22e4 <__aeabi_fsub+0x144>
+    22e2:	e085      	b.n	23f0 <__aeabi_fsub+0x250>
+    22e4:	2201      	movs	r2, #1
+    22e6:	497a      	ldr	r1, [pc, #488]	; (24d0 <__aeabi_fsub+0x330>)
+    22e8:	401a      	ands	r2, r3
+    22ea:	085b      	lsrs	r3, r3, #1
+    22ec:	400b      	ands	r3, r1
+    22ee:	4313      	orrs	r3, r2
+    22f0:	e79c      	b.n	222c <__aeabi_fsub+0x8c>
+    22f2:	2e00      	cmp	r6, #0
+    22f4:	d000      	beq.n	22f8 <__aeabi_fsub+0x158>
+    22f6:	e770      	b.n	21da <__aeabi_fsub+0x3a>
+    22f8:	e76b      	b.n	21d2 <__aeabi_fsub+0x32>
+    22fa:	1e3b      	subs	r3, r7, #0
+    22fc:	d1c5      	bne.n	228a <__aeabi_fsub+0xea>
+    22fe:	2200      	movs	r2, #0
+    2300:	027b      	lsls	r3, r7, #9
+    2302:	0a5b      	lsrs	r3, r3, #9
+    2304:	b2e4      	uxtb	r4, r4
+    2306:	e7a3      	b.n	2250 <__aeabi_fsub+0xb0>
+    2308:	0014      	movs	r4, r2
+    230a:	e78f      	b.n	222c <__aeabi_fsub+0x8c>
+    230c:	2e00      	cmp	r6, #0
+    230e:	d04d      	beq.n	23ac <__aeabi_fsub+0x20c>
+    2310:	1e48      	subs	r0, r1, #1
+    2312:	2800      	cmp	r0, #0
+    2314:	d157      	bne.n	23c6 <__aeabi_fsub+0x226>
+    2316:	199b      	adds	r3, r3, r6
+    2318:	2401      	movs	r4, #1
+    231a:	015a      	lsls	r2, r3, #5
+    231c:	d5b5      	bpl.n	228a <__aeabi_fsub+0xea>
+    231e:	2402      	movs	r4, #2
+    2320:	e7e0      	b.n	22e4 <__aeabi_fsub+0x144>
+    2322:	2a00      	cmp	r2, #0
+    2324:	d125      	bne.n	2372 <__aeabi_fsub+0x1d2>
+    2326:	1c62      	adds	r2, r4, #1
+    2328:	b2d2      	uxtb	r2, r2
+    232a:	2a01      	cmp	r2, #1
+    232c:	dd72      	ble.n	2414 <__aeabi_fsub+0x274>
+    232e:	1b9f      	subs	r7, r3, r6
+    2330:	017a      	lsls	r2, r7, #5
+    2332:	d535      	bpl.n	23a0 <__aeabi_fsub+0x200>
+    2334:	1af7      	subs	r7, r6, r3
+    2336:	000d      	movs	r5, r1
+    2338:	e764      	b.n	2204 <__aeabi_fsub+0x64>
+    233a:	2201      	movs	r2, #1
+    233c:	2300      	movs	r3, #0
+    233e:	402a      	ands	r2, r5
+    2340:	e786      	b.n	2250 <__aeabi_fsub+0xb0>
+    2342:	003b      	movs	r3, r7
+    2344:	4a63      	ldr	r2, [pc, #396]	; (24d4 <__aeabi_fsub+0x334>)
+    2346:	1a24      	subs	r4, r4, r0
+    2348:	4013      	ands	r3, r2
+    234a:	e76f      	b.n	222c <__aeabi_fsub+0x8c>
+    234c:	2900      	cmp	r1, #0
+    234e:	d16c      	bne.n	242a <__aeabi_fsub+0x28a>
+    2350:	1c61      	adds	r1, r4, #1
+    2352:	b2c8      	uxtb	r0, r1
+    2354:	2801      	cmp	r0, #1
+    2356:	dd4e      	ble.n	23f6 <__aeabi_fsub+0x256>
+    2358:	29ff      	cmp	r1, #255	; 0xff
+    235a:	d049      	beq.n	23f0 <__aeabi_fsub+0x250>
+    235c:	199b      	adds	r3, r3, r6
+    235e:	085b      	lsrs	r3, r3, #1
+    2360:	000c      	movs	r4, r1
+    2362:	e763      	b.n	222c <__aeabi_fsub+0x8c>
+    2364:	2aff      	cmp	r2, #255	; 0xff
+    2366:	d041      	beq.n	23ec <__aeabi_fsub+0x24c>
+    2368:	000a      	movs	r2, r1
+    236a:	e781      	b.n	2270 <__aeabi_fsub+0xd0>
+    236c:	2601      	movs	r6, #1
+    236e:	1b9b      	subs	r3, r3, r6
+    2370:	e789      	b.n	2286 <__aeabi_fsub+0xe6>
+    2372:	2c00      	cmp	r4, #0
+    2374:	d01c      	beq.n	23b0 <__aeabi_fsub+0x210>
+    2376:	28ff      	cmp	r0, #255	; 0xff
+    2378:	d021      	beq.n	23be <__aeabi_fsub+0x21e>
+    237a:	2480      	movs	r4, #128	; 0x80
+    237c:	04e4      	lsls	r4, r4, #19
+    237e:	4252      	negs	r2, r2
+    2380:	4323      	orrs	r3, r4
+    2382:	2a1b      	cmp	r2, #27
+    2384:	dd00      	ble.n	2388 <__aeabi_fsub+0x1e8>
+    2386:	e096      	b.n	24b6 <__aeabi_fsub+0x316>
+    2388:	001c      	movs	r4, r3
+    238a:	2520      	movs	r5, #32
+    238c:	40d4      	lsrs	r4, r2
+    238e:	1aaa      	subs	r2, r5, r2
+    2390:	4093      	lsls	r3, r2
+    2392:	1e5a      	subs	r2, r3, #1
+    2394:	4193      	sbcs	r3, r2
+    2396:	4323      	orrs	r3, r4
+    2398:	1af3      	subs	r3, r6, r3
+    239a:	0004      	movs	r4, r0
+    239c:	000d      	movs	r5, r1
+    239e:	e72d      	b.n	21fc <__aeabi_fsub+0x5c>
+    23a0:	2f00      	cmp	r7, #0
+    23a2:	d000      	beq.n	23a6 <__aeabi_fsub+0x206>
+    23a4:	e72e      	b.n	2204 <__aeabi_fsub+0x64>
+    23a6:	2200      	movs	r2, #0
+    23a8:	2400      	movs	r4, #0
+    23aa:	e7a9      	b.n	2300 <__aeabi_fsub+0x160>
+    23ac:	000c      	movs	r4, r1
+    23ae:	e73d      	b.n	222c <__aeabi_fsub+0x8c>
+    23b0:	2b00      	cmp	r3, #0
+    23b2:	d058      	beq.n	2466 <__aeabi_fsub+0x2c6>
+    23b4:	43d2      	mvns	r2, r2
+    23b6:	2a00      	cmp	r2, #0
+    23b8:	d0ee      	beq.n	2398 <__aeabi_fsub+0x1f8>
+    23ba:	28ff      	cmp	r0, #255	; 0xff
+    23bc:	d1e1      	bne.n	2382 <__aeabi_fsub+0x1e2>
+    23be:	0033      	movs	r3, r6
+    23c0:	24ff      	movs	r4, #255	; 0xff
+    23c2:	000d      	movs	r5, r1
+    23c4:	e732      	b.n	222c <__aeabi_fsub+0x8c>
+    23c6:	29ff      	cmp	r1, #255	; 0xff
+    23c8:	d010      	beq.n	23ec <__aeabi_fsub+0x24c>
+    23ca:	0001      	movs	r1, r0
+    23cc:	e778      	b.n	22c0 <__aeabi_fsub+0x120>
+    23ce:	2b00      	cmp	r3, #0
+    23d0:	d06e      	beq.n	24b0 <__aeabi_fsub+0x310>
+    23d2:	24ff      	movs	r4, #255	; 0xff
+    23d4:	2e00      	cmp	r6, #0
+    23d6:	d100      	bne.n	23da <__aeabi_fsub+0x23a>
+    23d8:	e728      	b.n	222c <__aeabi_fsub+0x8c>
+    23da:	2280      	movs	r2, #128	; 0x80
+    23dc:	4651      	mov	r1, sl
+    23de:	03d2      	lsls	r2, r2, #15
+    23e0:	4211      	tst	r1, r2
+    23e2:	d003      	beq.n	23ec <__aeabi_fsub+0x24c>
+    23e4:	4661      	mov	r1, ip
+    23e6:	4211      	tst	r1, r2
+    23e8:	d100      	bne.n	23ec <__aeabi_fsub+0x24c>
+    23ea:	0033      	movs	r3, r6
+    23ec:	24ff      	movs	r4, #255	; 0xff
+    23ee:	e71d      	b.n	222c <__aeabi_fsub+0x8c>
+    23f0:	24ff      	movs	r4, #255	; 0xff
+    23f2:	2300      	movs	r3, #0
+    23f4:	e72c      	b.n	2250 <__aeabi_fsub+0xb0>
+    23f6:	2c00      	cmp	r4, #0
+    23f8:	d1e9      	bne.n	23ce <__aeabi_fsub+0x22e>
+    23fa:	2b00      	cmp	r3, #0
+    23fc:	d063      	beq.n	24c6 <__aeabi_fsub+0x326>
+    23fe:	2e00      	cmp	r6, #0
+    2400:	d100      	bne.n	2404 <__aeabi_fsub+0x264>
+    2402:	e713      	b.n	222c <__aeabi_fsub+0x8c>
+    2404:	199b      	adds	r3, r3, r6
+    2406:	015a      	lsls	r2, r3, #5
+    2408:	d400      	bmi.n	240c <__aeabi_fsub+0x26c>
+    240a:	e73e      	b.n	228a <__aeabi_fsub+0xea>
+    240c:	4a31      	ldr	r2, [pc, #196]	; (24d4 <__aeabi_fsub+0x334>)
+    240e:	000c      	movs	r4, r1
+    2410:	4013      	ands	r3, r2
+    2412:	e70b      	b.n	222c <__aeabi_fsub+0x8c>
+    2414:	2c00      	cmp	r4, #0
+    2416:	d11e      	bne.n	2456 <__aeabi_fsub+0x2b6>
+    2418:	2b00      	cmp	r3, #0
+    241a:	d12f      	bne.n	247c <__aeabi_fsub+0x2dc>
+    241c:	2e00      	cmp	r6, #0
+    241e:	d04f      	beq.n	24c0 <__aeabi_fsub+0x320>
+    2420:	0033      	movs	r3, r6
+    2422:	000d      	movs	r5, r1
+    2424:	e702      	b.n	222c <__aeabi_fsub+0x8c>
+    2426:	2601      	movs	r6, #1
+    2428:	e755      	b.n	22d6 <__aeabi_fsub+0x136>
+    242a:	2c00      	cmp	r4, #0
+    242c:	d11f      	bne.n	246e <__aeabi_fsub+0x2ce>
+    242e:	2b00      	cmp	r3, #0
+    2430:	d043      	beq.n	24ba <__aeabi_fsub+0x31a>
+    2432:	43c9      	mvns	r1, r1
+    2434:	2900      	cmp	r1, #0
+    2436:	d00b      	beq.n	2450 <__aeabi_fsub+0x2b0>
+    2438:	28ff      	cmp	r0, #255	; 0xff
+    243a:	d039      	beq.n	24b0 <__aeabi_fsub+0x310>
+    243c:	291b      	cmp	r1, #27
+    243e:	dc44      	bgt.n	24ca <__aeabi_fsub+0x32a>
+    2440:	001c      	movs	r4, r3
+    2442:	2720      	movs	r7, #32
+    2444:	40cc      	lsrs	r4, r1
+    2446:	1a79      	subs	r1, r7, r1
+    2448:	408b      	lsls	r3, r1
+    244a:	1e59      	subs	r1, r3, #1
+    244c:	418b      	sbcs	r3, r1
+    244e:	4323      	orrs	r3, r4
+    2450:	199b      	adds	r3, r3, r6
+    2452:	0004      	movs	r4, r0
+    2454:	e740      	b.n	22d8 <__aeabi_fsub+0x138>
+    2456:	2b00      	cmp	r3, #0
+    2458:	d11a      	bne.n	2490 <__aeabi_fsub+0x2f0>
+    245a:	2e00      	cmp	r6, #0
+    245c:	d124      	bne.n	24a8 <__aeabi_fsub+0x308>
+    245e:	2780      	movs	r7, #128	; 0x80
+    2460:	2200      	movs	r2, #0
+    2462:	03ff      	lsls	r7, r7, #15
+    2464:	e71b      	b.n	229e <__aeabi_fsub+0xfe>
+    2466:	0033      	movs	r3, r6
+    2468:	0004      	movs	r4, r0
+    246a:	000d      	movs	r5, r1
+    246c:	e6de      	b.n	222c <__aeabi_fsub+0x8c>
+    246e:	28ff      	cmp	r0, #255	; 0xff
+    2470:	d01e      	beq.n	24b0 <__aeabi_fsub+0x310>
+    2472:	2480      	movs	r4, #128	; 0x80
+    2474:	04e4      	lsls	r4, r4, #19
+    2476:	4249      	negs	r1, r1
+    2478:	4323      	orrs	r3, r4
+    247a:	e7df      	b.n	243c <__aeabi_fsub+0x29c>
+    247c:	2e00      	cmp	r6, #0
+    247e:	d100      	bne.n	2482 <__aeabi_fsub+0x2e2>
+    2480:	e6d4      	b.n	222c <__aeabi_fsub+0x8c>
+    2482:	1b9f      	subs	r7, r3, r6
+    2484:	017a      	lsls	r2, r7, #5
+    2486:	d400      	bmi.n	248a <__aeabi_fsub+0x2ea>
+    2488:	e737      	b.n	22fa <__aeabi_fsub+0x15a>
+    248a:	1af3      	subs	r3, r6, r3
+    248c:	000d      	movs	r5, r1
+    248e:	e6cd      	b.n	222c <__aeabi_fsub+0x8c>
+    2490:	24ff      	movs	r4, #255	; 0xff
+    2492:	2e00      	cmp	r6, #0
+    2494:	d100      	bne.n	2498 <__aeabi_fsub+0x2f8>
+    2496:	e6c9      	b.n	222c <__aeabi_fsub+0x8c>
+    2498:	2280      	movs	r2, #128	; 0x80
+    249a:	4650      	mov	r0, sl
+    249c:	03d2      	lsls	r2, r2, #15
+    249e:	4210      	tst	r0, r2
+    24a0:	d0a4      	beq.n	23ec <__aeabi_fsub+0x24c>
+    24a2:	4660      	mov	r0, ip
+    24a4:	4210      	tst	r0, r2
+    24a6:	d1a1      	bne.n	23ec <__aeabi_fsub+0x24c>
+    24a8:	0033      	movs	r3, r6
+    24aa:	000d      	movs	r5, r1
+    24ac:	24ff      	movs	r4, #255	; 0xff
+    24ae:	e6bd      	b.n	222c <__aeabi_fsub+0x8c>
+    24b0:	0033      	movs	r3, r6
+    24b2:	24ff      	movs	r4, #255	; 0xff
+    24b4:	e6ba      	b.n	222c <__aeabi_fsub+0x8c>
+    24b6:	2301      	movs	r3, #1
+    24b8:	e76e      	b.n	2398 <__aeabi_fsub+0x1f8>
+    24ba:	0033      	movs	r3, r6
+    24bc:	0004      	movs	r4, r0
+    24be:	e6b5      	b.n	222c <__aeabi_fsub+0x8c>
+    24c0:	2700      	movs	r7, #0
+    24c2:	2200      	movs	r2, #0
+    24c4:	e71c      	b.n	2300 <__aeabi_fsub+0x160>
+    24c6:	0033      	movs	r3, r6
+    24c8:	e6b0      	b.n	222c <__aeabi_fsub+0x8c>
+    24ca:	2301      	movs	r3, #1
+    24cc:	e7c0      	b.n	2450 <__aeabi_fsub+0x2b0>
+    24ce:	46c0      	nop			; (mov r8, r8)
+    24d0:	7dffffff 	.word	0x7dffffff
+    24d4:	fbffffff 	.word	0xfbffffff
+
+000024d8 <__aeabi_f2iz>:
+    24d8:	0241      	lsls	r1, r0, #9
+    24da:	0043      	lsls	r3, r0, #1
+    24dc:	0fc2      	lsrs	r2, r0, #31
+    24de:	0a49      	lsrs	r1, r1, #9
+    24e0:	0e1b      	lsrs	r3, r3, #24
+    24e2:	2000      	movs	r0, #0
+    24e4:	2b7e      	cmp	r3, #126	; 0x7e
+    24e6:	dd0d      	ble.n	2504 <__aeabi_f2iz+0x2c>
+    24e8:	2b9d      	cmp	r3, #157	; 0x9d
+    24ea:	dc0c      	bgt.n	2506 <__aeabi_f2iz+0x2e>
+    24ec:	2080      	movs	r0, #128	; 0x80
+    24ee:	0400      	lsls	r0, r0, #16
+    24f0:	4301      	orrs	r1, r0
+    24f2:	2b95      	cmp	r3, #149	; 0x95
+    24f4:	dc0a      	bgt.n	250c <__aeabi_f2iz+0x34>
+    24f6:	2096      	movs	r0, #150	; 0x96
+    24f8:	1ac3      	subs	r3, r0, r3
+    24fa:	40d9      	lsrs	r1, r3
+    24fc:	4248      	negs	r0, r1
+    24fe:	2a00      	cmp	r2, #0
+    2500:	d100      	bne.n	2504 <__aeabi_f2iz+0x2c>
+    2502:	0008      	movs	r0, r1
+    2504:	4770      	bx	lr
+    2506:	4b03      	ldr	r3, [pc, #12]	; (2514 <__aeabi_f2iz+0x3c>)
+    2508:	18d0      	adds	r0, r2, r3
+    250a:	e7fb      	b.n	2504 <__aeabi_f2iz+0x2c>
+    250c:	3b96      	subs	r3, #150	; 0x96
+    250e:	4099      	lsls	r1, r3
+    2510:	e7f4      	b.n	24fc <__aeabi_f2iz+0x24>
+    2512:	46c0      	nop			; (mov r8, r8)
+    2514:	7fffffff 	.word	0x7fffffff
+
+00002518 <__aeabi_i2f>:
+    2518:	b570      	push	{r4, r5, r6, lr}
+    251a:	2800      	cmp	r0, #0
+    251c:	d030      	beq.n	2580 <__aeabi_i2f+0x68>
+    251e:	17c3      	asrs	r3, r0, #31
+    2520:	18c4      	adds	r4, r0, r3
+    2522:	405c      	eors	r4, r3
+    2524:	0fc5      	lsrs	r5, r0, #31
+    2526:	0020      	movs	r0, r4
+    2528:	f000 f88c 	bl	2644 <__clzsi2>
+    252c:	239e      	movs	r3, #158	; 0x9e
+    252e:	1a1b      	subs	r3, r3, r0
+    2530:	2b96      	cmp	r3, #150	; 0x96
+    2532:	dc0d      	bgt.n	2550 <__aeabi_i2f+0x38>
+    2534:	2296      	movs	r2, #150	; 0x96
+    2536:	1ad2      	subs	r2, r2, r3
+    2538:	4094      	lsls	r4, r2
+    253a:	002a      	movs	r2, r5
+    253c:	0264      	lsls	r4, r4, #9
+    253e:	0a64      	lsrs	r4, r4, #9
+    2540:	b2db      	uxtb	r3, r3
+    2542:	0264      	lsls	r4, r4, #9
+    2544:	05db      	lsls	r3, r3, #23
+    2546:	0a60      	lsrs	r0, r4, #9
+    2548:	07d2      	lsls	r2, r2, #31
+    254a:	4318      	orrs	r0, r3
+    254c:	4310      	orrs	r0, r2
+    254e:	bd70      	pop	{r4, r5, r6, pc}
+    2550:	2b99      	cmp	r3, #153	; 0x99
+    2552:	dc19      	bgt.n	2588 <__aeabi_i2f+0x70>
+    2554:	2299      	movs	r2, #153	; 0x99
+    2556:	1ad2      	subs	r2, r2, r3
+    2558:	2a00      	cmp	r2, #0
+    255a:	dd29      	ble.n	25b0 <__aeabi_i2f+0x98>
+    255c:	4094      	lsls	r4, r2
+    255e:	0022      	movs	r2, r4
+    2560:	4c14      	ldr	r4, [pc, #80]	; (25b4 <__aeabi_i2f+0x9c>)
+    2562:	4014      	ands	r4, r2
+    2564:	0751      	lsls	r1, r2, #29
+    2566:	d004      	beq.n	2572 <__aeabi_i2f+0x5a>
+    2568:	210f      	movs	r1, #15
+    256a:	400a      	ands	r2, r1
+    256c:	2a04      	cmp	r2, #4
+    256e:	d000      	beq.n	2572 <__aeabi_i2f+0x5a>
+    2570:	3404      	adds	r4, #4
+    2572:	0162      	lsls	r2, r4, #5
+    2574:	d413      	bmi.n	259e <__aeabi_i2f+0x86>
+    2576:	01a4      	lsls	r4, r4, #6
+    2578:	0a64      	lsrs	r4, r4, #9
+    257a:	b2db      	uxtb	r3, r3
+    257c:	002a      	movs	r2, r5
+    257e:	e7e0      	b.n	2542 <__aeabi_i2f+0x2a>
+    2580:	2200      	movs	r2, #0
+    2582:	2300      	movs	r3, #0
+    2584:	2400      	movs	r4, #0
+    2586:	e7dc      	b.n	2542 <__aeabi_i2f+0x2a>
+    2588:	2205      	movs	r2, #5
+    258a:	0021      	movs	r1, r4
+    258c:	1a12      	subs	r2, r2, r0
+    258e:	40d1      	lsrs	r1, r2
+    2590:	22b9      	movs	r2, #185	; 0xb9
+    2592:	1ad2      	subs	r2, r2, r3
+    2594:	4094      	lsls	r4, r2
+    2596:	1e62      	subs	r2, r4, #1
+    2598:	4194      	sbcs	r4, r2
+    259a:	430c      	orrs	r4, r1
+    259c:	e7da      	b.n	2554 <__aeabi_i2f+0x3c>
+    259e:	4b05      	ldr	r3, [pc, #20]	; (25b4 <__aeabi_i2f+0x9c>)
+    25a0:	002a      	movs	r2, r5
+    25a2:	401c      	ands	r4, r3
+    25a4:	239f      	movs	r3, #159	; 0x9f
+    25a6:	01a4      	lsls	r4, r4, #6
+    25a8:	1a1b      	subs	r3, r3, r0
+    25aa:	0a64      	lsrs	r4, r4, #9
+    25ac:	b2db      	uxtb	r3, r3
+    25ae:	e7c8      	b.n	2542 <__aeabi_i2f+0x2a>
+    25b0:	0022      	movs	r2, r4
+    25b2:	e7d5      	b.n	2560 <__aeabi_i2f+0x48>
+    25b4:	fbffffff 	.word	0xfbffffff
+
+000025b8 <__aeabi_ui2f>:
+    25b8:	b510      	push	{r4, lr}
+    25ba:	1e04      	subs	r4, r0, #0
+    25bc:	d027      	beq.n	260e <__aeabi_ui2f+0x56>
+    25be:	f000 f841 	bl	2644 <__clzsi2>
+    25c2:	239e      	movs	r3, #158	; 0x9e
+    25c4:	1a1b      	subs	r3, r3, r0
+    25c6:	2b96      	cmp	r3, #150	; 0x96
+    25c8:	dc0a      	bgt.n	25e0 <__aeabi_ui2f+0x28>
+    25ca:	2296      	movs	r2, #150	; 0x96
+    25cc:	1ad2      	subs	r2, r2, r3
+    25ce:	4094      	lsls	r4, r2
+    25d0:	0264      	lsls	r4, r4, #9
+    25d2:	0a64      	lsrs	r4, r4, #9
+    25d4:	b2db      	uxtb	r3, r3
+    25d6:	0264      	lsls	r4, r4, #9
+    25d8:	05db      	lsls	r3, r3, #23
+    25da:	0a60      	lsrs	r0, r4, #9
+    25dc:	4318      	orrs	r0, r3
+    25de:	bd10      	pop	{r4, pc}
+    25e0:	2b99      	cmp	r3, #153	; 0x99
+    25e2:	dc17      	bgt.n	2614 <__aeabi_ui2f+0x5c>
+    25e4:	2299      	movs	r2, #153	; 0x99
+    25e6:	1ad2      	subs	r2, r2, r3
+    25e8:	2a00      	cmp	r2, #0
+    25ea:	dd27      	ble.n	263c <__aeabi_ui2f+0x84>
+    25ec:	4094      	lsls	r4, r2
+    25ee:	0022      	movs	r2, r4
+    25f0:	4c13      	ldr	r4, [pc, #76]	; (2640 <__aeabi_ui2f+0x88>)
+    25f2:	4014      	ands	r4, r2
+    25f4:	0751      	lsls	r1, r2, #29
+    25f6:	d004      	beq.n	2602 <__aeabi_ui2f+0x4a>
+    25f8:	210f      	movs	r1, #15
+    25fa:	400a      	ands	r2, r1
+    25fc:	2a04      	cmp	r2, #4
+    25fe:	d000      	beq.n	2602 <__aeabi_ui2f+0x4a>
+    2600:	3404      	adds	r4, #4
+    2602:	0162      	lsls	r2, r4, #5
+    2604:	d412      	bmi.n	262c <__aeabi_ui2f+0x74>
+    2606:	01a4      	lsls	r4, r4, #6
+    2608:	0a64      	lsrs	r4, r4, #9
+    260a:	b2db      	uxtb	r3, r3
+    260c:	e7e3      	b.n	25d6 <__aeabi_ui2f+0x1e>
+    260e:	2300      	movs	r3, #0
+    2610:	2400      	movs	r4, #0
+    2612:	e7e0      	b.n	25d6 <__aeabi_ui2f+0x1e>
+    2614:	22b9      	movs	r2, #185	; 0xb9
+    2616:	0021      	movs	r1, r4
+    2618:	1ad2      	subs	r2, r2, r3
+    261a:	4091      	lsls	r1, r2
+    261c:	000a      	movs	r2, r1
+    261e:	1e51      	subs	r1, r2, #1
+    2620:	418a      	sbcs	r2, r1
+    2622:	2105      	movs	r1, #5
+    2624:	1a09      	subs	r1, r1, r0
+    2626:	40cc      	lsrs	r4, r1
+    2628:	4314      	orrs	r4, r2
+    262a:	e7db      	b.n	25e4 <__aeabi_ui2f+0x2c>
+    262c:	4b04      	ldr	r3, [pc, #16]	; (2640 <__aeabi_ui2f+0x88>)
+    262e:	401c      	ands	r4, r3
+    2630:	239f      	movs	r3, #159	; 0x9f
+    2632:	01a4      	lsls	r4, r4, #6
+    2634:	1a1b      	subs	r3, r3, r0
+    2636:	0a64      	lsrs	r4, r4, #9
+    2638:	b2db      	uxtb	r3, r3
+    263a:	e7cc      	b.n	25d6 <__aeabi_ui2f+0x1e>
+    263c:	0022      	movs	r2, r4
+    263e:	e7d7      	b.n	25f0 <__aeabi_ui2f+0x38>
+    2640:	fbffffff 	.word	0xfbffffff
+
+00002644 <__clzsi2>:
+    2644:	211c      	movs	r1, #28
+    2646:	2301      	movs	r3, #1
+    2648:	041b      	lsls	r3, r3, #16
+    264a:	4298      	cmp	r0, r3
+    264c:	d301      	bcc.n	2652 <__clzsi2+0xe>
+    264e:	0c00      	lsrs	r0, r0, #16
+    2650:	3910      	subs	r1, #16
+    2652:	0a1b      	lsrs	r3, r3, #8
+    2654:	4298      	cmp	r0, r3
+    2656:	d301      	bcc.n	265c <__clzsi2+0x18>
+    2658:	0a00      	lsrs	r0, r0, #8
+    265a:	3908      	subs	r1, #8
+    265c:	091b      	lsrs	r3, r3, #4
+    265e:	4298      	cmp	r0, r3
+    2660:	d301      	bcc.n	2666 <__clzsi2+0x22>
+    2662:	0900      	lsrs	r0, r0, #4
+    2664:	3904      	subs	r1, #4
+    2666:	a202      	add	r2, pc, #8	; (adr r2, 2670 <__clzsi2+0x2c>)
+    2668:	5c10      	ldrb	r0, [r2, r0]
+    266a:	1840      	adds	r0, r0, r1
+    266c:	4770      	bx	lr
+    266e:	46c0      	nop			; (mov r8, r8)
+    2670:	02020304 	.word	0x02020304
+    2674:	01010101 	.word	0x01010101
+	...
+
+00002680 <__libc_init_array>:
+    2680:	b570      	push	{r4, r5, r6, lr}
+    2682:	2600      	movs	r6, #0
+    2684:	4d0c      	ldr	r5, [pc, #48]	; (26b8 <__libc_init_array+0x38>)
+    2686:	4c0d      	ldr	r4, [pc, #52]	; (26bc <__libc_init_array+0x3c>)
+    2688:	1b64      	subs	r4, r4, r5
+    268a:	10a4      	asrs	r4, r4, #2
+    268c:	42a6      	cmp	r6, r4
+    268e:	d109      	bne.n	26a4 <__libc_init_array+0x24>
+    2690:	2600      	movs	r6, #0
+    2692:	f001 f955 	bl	3940 <_init>
+    2696:	4d0a      	ldr	r5, [pc, #40]	; (26c0 <__libc_init_array+0x40>)
+    2698:	4c0a      	ldr	r4, [pc, #40]	; (26c4 <__libc_init_array+0x44>)
+    269a:	1b64      	subs	r4, r4, r5
+    269c:	10a4      	asrs	r4, r4, #2
+    269e:	42a6      	cmp	r6, r4
+    26a0:	d105      	bne.n	26ae <__libc_init_array+0x2e>
+    26a2:	bd70      	pop	{r4, r5, r6, pc}
+    26a4:	00b3      	lsls	r3, r6, #2
+    26a6:	58eb      	ldr	r3, [r5, r3]
+    26a8:	4798      	blx	r3
+    26aa:	3601      	adds	r6, #1
+    26ac:	e7ee      	b.n	268c <__libc_init_array+0xc>
+    26ae:	00b3      	lsls	r3, r6, #2
+    26b0:	58eb      	ldr	r3, [r5, r3]
+    26b2:	4798      	blx	r3
+    26b4:	3601      	adds	r6, #1
+    26b6:	e7f2      	b.n	269e <__libc_init_array+0x1e>
+    26b8:	0000394c 	.word	0x0000394c
+    26bc:	0000394c 	.word	0x0000394c
+    26c0:	0000394c 	.word	0x0000394c
+    26c4:	00003950 	.word	0x00003950
+
+000026c8 <memcpy>:
+    26c8:	2300      	movs	r3, #0
+    26ca:	b510      	push	{r4, lr}
+    26cc:	429a      	cmp	r2, r3
+    26ce:	d100      	bne.n	26d2 <memcpy+0xa>
+    26d0:	bd10      	pop	{r4, pc}
+    26d2:	5ccc      	ldrb	r4, [r1, r3]
+    26d4:	54c4      	strb	r4, [r0, r3]
+    26d6:	3301      	adds	r3, #1
+    26d8:	e7f8      	b.n	26cc <memcpy+0x4>
+
+000026da <memset>:
+    26da:	0003      	movs	r3, r0
+    26dc:	1882      	adds	r2, r0, r2
+    26de:	4293      	cmp	r3, r2
+    26e0:	d100      	bne.n	26e4 <memset+0xa>
+    26e2:	4770      	bx	lr
+    26e4:	7019      	strb	r1, [r3, #0]
+    26e6:	3301      	adds	r3, #1
+    26e8:	e7f9      	b.n	26de <memset+0x4>
+	...
+
+000026ec <iprintf>:
+    26ec:	b40f      	push	{r0, r1, r2, r3}
+    26ee:	4b0b      	ldr	r3, [pc, #44]	; (271c <iprintf+0x30>)
+    26f0:	b513      	push	{r0, r1, r4, lr}
+    26f2:	681c      	ldr	r4, [r3, #0]
+    26f4:	2c00      	cmp	r4, #0
+    26f6:	d005      	beq.n	2704 <iprintf+0x18>
+    26f8:	69a3      	ldr	r3, [r4, #24]
+    26fa:	2b00      	cmp	r3, #0
+    26fc:	d102      	bne.n	2704 <iprintf+0x18>
+    26fe:	0020      	movs	r0, r4
+    2700:	f000 f9bc 	bl	2a7c <__sinit>
+    2704:	ab05      	add	r3, sp, #20
+    2706:	9a04      	ldr	r2, [sp, #16]
+    2708:	68a1      	ldr	r1, [r4, #8]
+    270a:	0020      	movs	r0, r4
+    270c:	9301      	str	r3, [sp, #4]
+    270e:	f000 fb91 	bl	2e34 <_vfiprintf_r>
+    2712:	bc16      	pop	{r1, r2, r4}
+    2714:	bc08      	pop	{r3}
+    2716:	b004      	add	sp, #16
+    2718:	4718      	bx	r3
+    271a:	46c0      	nop			; (mov r8, r8)
+    271c:	20000018 	.word	0x20000018
+
+00002720 <setbuf>:
+    2720:	424a      	negs	r2, r1
+    2722:	414a      	adcs	r2, r1
+    2724:	2380      	movs	r3, #128	; 0x80
+    2726:	b510      	push	{r4, lr}
+    2728:	0052      	lsls	r2, r2, #1
+    272a:	00db      	lsls	r3, r3, #3
+    272c:	f000 f802 	bl	2734 <setvbuf>
+    2730:	bd10      	pop	{r4, pc}
+	...
+
+00002734 <setvbuf>:
+    2734:	b5f0      	push	{r4, r5, r6, r7, lr}
+    2736:	001d      	movs	r5, r3
+    2738:	4b4f      	ldr	r3, [pc, #316]	; (2878 <setvbuf+0x144>)
+    273a:	b085      	sub	sp, #20
+    273c:	681e      	ldr	r6, [r3, #0]
+    273e:	0004      	movs	r4, r0
+    2740:	000f      	movs	r7, r1
+    2742:	9200      	str	r2, [sp, #0]
+    2744:	2e00      	cmp	r6, #0
+    2746:	d005      	beq.n	2754 <setvbuf+0x20>
+    2748:	69b3      	ldr	r3, [r6, #24]
+    274a:	2b00      	cmp	r3, #0
+    274c:	d102      	bne.n	2754 <setvbuf+0x20>
+    274e:	0030      	movs	r0, r6
+    2750:	f000 f994 	bl	2a7c <__sinit>
+    2754:	4b49      	ldr	r3, [pc, #292]	; (287c <setvbuf+0x148>)
+    2756:	429c      	cmp	r4, r3
+    2758:	d150      	bne.n	27fc <setvbuf+0xc8>
+    275a:	6874      	ldr	r4, [r6, #4]
+    275c:	9b00      	ldr	r3, [sp, #0]
+    275e:	2b02      	cmp	r3, #2
+    2760:	d005      	beq.n	276e <setvbuf+0x3a>
+    2762:	2b01      	cmp	r3, #1
+    2764:	d900      	bls.n	2768 <setvbuf+0x34>
+    2766:	e084      	b.n	2872 <setvbuf+0x13e>
+    2768:	2d00      	cmp	r5, #0
+    276a:	da00      	bge.n	276e <setvbuf+0x3a>
+    276c:	e081      	b.n	2872 <setvbuf+0x13e>
+    276e:	0021      	movs	r1, r4
+    2770:	0030      	movs	r0, r6
+    2772:	f000 f915 	bl	29a0 <_fflush_r>
+    2776:	6b61      	ldr	r1, [r4, #52]	; 0x34
+    2778:	2900      	cmp	r1, #0
+    277a:	d008      	beq.n	278e <setvbuf+0x5a>
+    277c:	0023      	movs	r3, r4
+    277e:	3344      	adds	r3, #68	; 0x44
+    2780:	4299      	cmp	r1, r3
+    2782:	d002      	beq.n	278a <setvbuf+0x56>
+    2784:	0030      	movs	r0, r6
+    2786:	f000 fa85 	bl	2c94 <_free_r>
+    278a:	2300      	movs	r3, #0
+    278c:	6363      	str	r3, [r4, #52]	; 0x34
+    278e:	2300      	movs	r3, #0
+    2790:	61a3      	str	r3, [r4, #24]
+    2792:	6063      	str	r3, [r4, #4]
+    2794:	89a3      	ldrh	r3, [r4, #12]
+    2796:	061b      	lsls	r3, r3, #24
+    2798:	d503      	bpl.n	27a2 <setvbuf+0x6e>
+    279a:	6921      	ldr	r1, [r4, #16]
+    279c:	0030      	movs	r0, r6
+    279e:	f000 fa79 	bl	2c94 <_free_r>
+    27a2:	89a3      	ldrh	r3, [r4, #12]
+    27a4:	4a36      	ldr	r2, [pc, #216]	; (2880 <setvbuf+0x14c>)
+    27a6:	4013      	ands	r3, r2
+    27a8:	81a3      	strh	r3, [r4, #12]
+    27aa:	9b00      	ldr	r3, [sp, #0]
+    27ac:	2b02      	cmp	r3, #2
+    27ae:	d05a      	beq.n	2866 <setvbuf+0x132>
+    27b0:	ab03      	add	r3, sp, #12
+    27b2:	aa02      	add	r2, sp, #8
+    27b4:	0021      	movs	r1, r4
+    27b6:	0030      	movs	r0, r6
+    27b8:	f000 f9f6 	bl	2ba8 <__swhatbuf_r>
+    27bc:	89a3      	ldrh	r3, [r4, #12]
+    27be:	4318      	orrs	r0, r3
+    27c0:	81a0      	strh	r0, [r4, #12]
+    27c2:	2d00      	cmp	r5, #0
+    27c4:	d124      	bne.n	2810 <setvbuf+0xdc>
+    27c6:	9d02      	ldr	r5, [sp, #8]
+    27c8:	0028      	movs	r0, r5
+    27ca:	f000 fa59 	bl	2c80 <malloc>
+    27ce:	9501      	str	r5, [sp, #4]
+    27d0:	1e07      	subs	r7, r0, #0
+    27d2:	d142      	bne.n	285a <setvbuf+0x126>
+    27d4:	9b02      	ldr	r3, [sp, #8]
+    27d6:	9301      	str	r3, [sp, #4]
+    27d8:	42ab      	cmp	r3, r5
+    27da:	d139      	bne.n	2850 <setvbuf+0x11c>
+    27dc:	2001      	movs	r0, #1
+    27de:	4240      	negs	r0, r0
+    27e0:	2302      	movs	r3, #2
+    27e2:	89a2      	ldrh	r2, [r4, #12]
+    27e4:	4313      	orrs	r3, r2
+    27e6:	81a3      	strh	r3, [r4, #12]
+    27e8:	2300      	movs	r3, #0
+    27ea:	60a3      	str	r3, [r4, #8]
+    27ec:	0023      	movs	r3, r4
+    27ee:	3347      	adds	r3, #71	; 0x47
+    27f0:	6023      	str	r3, [r4, #0]
+    27f2:	6123      	str	r3, [r4, #16]
+    27f4:	2301      	movs	r3, #1
+    27f6:	6163      	str	r3, [r4, #20]
+    27f8:	b005      	add	sp, #20
+    27fa:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    27fc:	4b21      	ldr	r3, [pc, #132]	; (2884 <setvbuf+0x150>)
+    27fe:	429c      	cmp	r4, r3
+    2800:	d101      	bne.n	2806 <setvbuf+0xd2>
+    2802:	68b4      	ldr	r4, [r6, #8]
+    2804:	e7aa      	b.n	275c <setvbuf+0x28>
+    2806:	4b20      	ldr	r3, [pc, #128]	; (2888 <setvbuf+0x154>)
+    2808:	429c      	cmp	r4, r3
+    280a:	d1a7      	bne.n	275c <setvbuf+0x28>
+    280c:	68f4      	ldr	r4, [r6, #12]
+    280e:	e7a5      	b.n	275c <setvbuf+0x28>
+    2810:	2f00      	cmp	r7, #0
+    2812:	d0d9      	beq.n	27c8 <setvbuf+0x94>
+    2814:	69b3      	ldr	r3, [r6, #24]
+    2816:	2b00      	cmp	r3, #0
+    2818:	d102      	bne.n	2820 <setvbuf+0xec>
+    281a:	0030      	movs	r0, r6
+    281c:	f000 f92e 	bl	2a7c <__sinit>
+    2820:	9b00      	ldr	r3, [sp, #0]
+    2822:	2b01      	cmp	r3, #1
+    2824:	d103      	bne.n	282e <setvbuf+0xfa>
+    2826:	89a3      	ldrh	r3, [r4, #12]
+    2828:	9a00      	ldr	r2, [sp, #0]
+    282a:	431a      	orrs	r2, r3
+    282c:	81a2      	strh	r2, [r4, #12]
+    282e:	2008      	movs	r0, #8
+    2830:	89a3      	ldrh	r3, [r4, #12]
+    2832:	6027      	str	r7, [r4, #0]
+    2834:	6127      	str	r7, [r4, #16]
+    2836:	6165      	str	r5, [r4, #20]
+    2838:	4018      	ands	r0, r3
+    283a:	d018      	beq.n	286e <setvbuf+0x13a>
+    283c:	2001      	movs	r0, #1
+    283e:	4018      	ands	r0, r3
+    2840:	2300      	movs	r3, #0
+    2842:	4298      	cmp	r0, r3
+    2844:	d011      	beq.n	286a <setvbuf+0x136>
+    2846:	426d      	negs	r5, r5
+    2848:	60a3      	str	r3, [r4, #8]
+    284a:	61a5      	str	r5, [r4, #24]
+    284c:	0018      	movs	r0, r3
+    284e:	e7d3      	b.n	27f8 <setvbuf+0xc4>
+    2850:	9801      	ldr	r0, [sp, #4]
+    2852:	f000 fa15 	bl	2c80 <malloc>
+    2856:	1e07      	subs	r7, r0, #0
+    2858:	d0c0      	beq.n	27dc <setvbuf+0xa8>
+    285a:	2380      	movs	r3, #128	; 0x80
+    285c:	89a2      	ldrh	r2, [r4, #12]
+    285e:	9d01      	ldr	r5, [sp, #4]
+    2860:	4313      	orrs	r3, r2
+    2862:	81a3      	strh	r3, [r4, #12]
+    2864:	e7d6      	b.n	2814 <setvbuf+0xe0>
+    2866:	2000      	movs	r0, #0
+    2868:	e7ba      	b.n	27e0 <setvbuf+0xac>
+    286a:	60a5      	str	r5, [r4, #8]
+    286c:	e7c4      	b.n	27f8 <setvbuf+0xc4>
+    286e:	60a0      	str	r0, [r4, #8]
+    2870:	e7c2      	b.n	27f8 <setvbuf+0xc4>
+    2872:	2001      	movs	r0, #1
+    2874:	4240      	negs	r0, r0
+    2876:	e7bf      	b.n	27f8 <setvbuf+0xc4>
+    2878:	20000018 	.word	0x20000018
+    287c:	000038cc 	.word	0x000038cc
+    2880:	fffff35c 	.word	0xfffff35c
+    2884:	000038ec 	.word	0x000038ec
+    2888:	000038ac 	.word	0x000038ac
+
+0000288c <__sflush_r>:
+    288c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    288e:	898a      	ldrh	r2, [r1, #12]
+    2890:	0005      	movs	r5, r0
+    2892:	000c      	movs	r4, r1
+    2894:	0713      	lsls	r3, r2, #28
+    2896:	d460      	bmi.n	295a <__sflush_r+0xce>
+    2898:	684b      	ldr	r3, [r1, #4]
+    289a:	2b00      	cmp	r3, #0
+    289c:	dc04      	bgt.n	28a8 <__sflush_r+0x1c>
+    289e:	6c0b      	ldr	r3, [r1, #64]	; 0x40
+    28a0:	2b00      	cmp	r3, #0
+    28a2:	dc01      	bgt.n	28a8 <__sflush_r+0x1c>
+    28a4:	2000      	movs	r0, #0
+    28a6:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    28a8:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
+    28aa:	2f00      	cmp	r7, #0
+    28ac:	d0fa      	beq.n	28a4 <__sflush_r+0x18>
+    28ae:	2300      	movs	r3, #0
+    28b0:	682e      	ldr	r6, [r5, #0]
+    28b2:	602b      	str	r3, [r5, #0]
+    28b4:	2380      	movs	r3, #128	; 0x80
+    28b6:	015b      	lsls	r3, r3, #5
+    28b8:	401a      	ands	r2, r3
+    28ba:	d034      	beq.n	2926 <__sflush_r+0x9a>
+    28bc:	6d60      	ldr	r0, [r4, #84]	; 0x54
+    28be:	89a3      	ldrh	r3, [r4, #12]
+    28c0:	075b      	lsls	r3, r3, #29
+    28c2:	d506      	bpl.n	28d2 <__sflush_r+0x46>
+    28c4:	6863      	ldr	r3, [r4, #4]
+    28c6:	1ac0      	subs	r0, r0, r3
+    28c8:	6b63      	ldr	r3, [r4, #52]	; 0x34
+    28ca:	2b00      	cmp	r3, #0
+    28cc:	d001      	beq.n	28d2 <__sflush_r+0x46>
+    28ce:	6c23      	ldr	r3, [r4, #64]	; 0x40
+    28d0:	1ac0      	subs	r0, r0, r3
+    28d2:	0002      	movs	r2, r0
+    28d4:	6a21      	ldr	r1, [r4, #32]
+    28d6:	2300      	movs	r3, #0
+    28d8:	0028      	movs	r0, r5
+    28da:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
+    28dc:	47b8      	blx	r7
+    28de:	89a1      	ldrh	r1, [r4, #12]
+    28e0:	1c43      	adds	r3, r0, #1
+    28e2:	d106      	bne.n	28f2 <__sflush_r+0x66>
+    28e4:	682b      	ldr	r3, [r5, #0]
+    28e6:	2b1d      	cmp	r3, #29
+    28e8:	d831      	bhi.n	294e <__sflush_r+0xc2>
+    28ea:	4a2c      	ldr	r2, [pc, #176]	; (299c <__sflush_r+0x110>)
+    28ec:	40da      	lsrs	r2, r3
+    28ee:	07d3      	lsls	r3, r2, #31
+    28f0:	d52d      	bpl.n	294e <__sflush_r+0xc2>
+    28f2:	2300      	movs	r3, #0
+    28f4:	6063      	str	r3, [r4, #4]
+    28f6:	6923      	ldr	r3, [r4, #16]
+    28f8:	6023      	str	r3, [r4, #0]
+    28fa:	04cb      	lsls	r3, r1, #19
+    28fc:	d505      	bpl.n	290a <__sflush_r+0x7e>
+    28fe:	1c43      	adds	r3, r0, #1
+    2900:	d102      	bne.n	2908 <__sflush_r+0x7c>
+    2902:	682b      	ldr	r3, [r5, #0]
+    2904:	2b00      	cmp	r3, #0
+    2906:	d100      	bne.n	290a <__sflush_r+0x7e>
+    2908:	6560      	str	r0, [r4, #84]	; 0x54
+    290a:	6b61      	ldr	r1, [r4, #52]	; 0x34
+    290c:	602e      	str	r6, [r5, #0]
+    290e:	2900      	cmp	r1, #0
+    2910:	d0c8      	beq.n	28a4 <__sflush_r+0x18>
+    2912:	0023      	movs	r3, r4
+    2914:	3344      	adds	r3, #68	; 0x44
+    2916:	4299      	cmp	r1, r3
+    2918:	d002      	beq.n	2920 <__sflush_r+0x94>
+    291a:	0028      	movs	r0, r5
+    291c:	f000 f9ba 	bl	2c94 <_free_r>
+    2920:	2000      	movs	r0, #0
+    2922:	6360      	str	r0, [r4, #52]	; 0x34
+    2924:	e7bf      	b.n	28a6 <__sflush_r+0x1a>
+    2926:	2301      	movs	r3, #1
+    2928:	6a21      	ldr	r1, [r4, #32]
+    292a:	0028      	movs	r0, r5
+    292c:	47b8      	blx	r7
+    292e:	1c43      	adds	r3, r0, #1
+    2930:	d1c5      	bne.n	28be <__sflush_r+0x32>
+    2932:	682b      	ldr	r3, [r5, #0]
+    2934:	2b00      	cmp	r3, #0
+    2936:	d0c2      	beq.n	28be <__sflush_r+0x32>
+    2938:	2b1d      	cmp	r3, #29
+    293a:	d001      	beq.n	2940 <__sflush_r+0xb4>
+    293c:	2b16      	cmp	r3, #22
+    293e:	d101      	bne.n	2944 <__sflush_r+0xb8>
+    2940:	602e      	str	r6, [r5, #0]
+    2942:	e7af      	b.n	28a4 <__sflush_r+0x18>
+    2944:	2340      	movs	r3, #64	; 0x40
+    2946:	89a2      	ldrh	r2, [r4, #12]
+    2948:	4313      	orrs	r3, r2
+    294a:	81a3      	strh	r3, [r4, #12]
+    294c:	e7ab      	b.n	28a6 <__sflush_r+0x1a>
+    294e:	2340      	movs	r3, #64	; 0x40
+    2950:	430b      	orrs	r3, r1
+    2952:	2001      	movs	r0, #1
+    2954:	81a3      	strh	r3, [r4, #12]
+    2956:	4240      	negs	r0, r0
+    2958:	e7a5      	b.n	28a6 <__sflush_r+0x1a>
+    295a:	690f      	ldr	r7, [r1, #16]
+    295c:	2f00      	cmp	r7, #0
+    295e:	d0a1      	beq.n	28a4 <__sflush_r+0x18>
+    2960:	680b      	ldr	r3, [r1, #0]
+    2962:	600f      	str	r7, [r1, #0]
+    2964:	1bdb      	subs	r3, r3, r7
+    2966:	9301      	str	r3, [sp, #4]
+    2968:	2300      	movs	r3, #0
+    296a:	0792      	lsls	r2, r2, #30
+    296c:	d100      	bne.n	2970 <__sflush_r+0xe4>
+    296e:	694b      	ldr	r3, [r1, #20]
+    2970:	60a3      	str	r3, [r4, #8]
+    2972:	9b01      	ldr	r3, [sp, #4]
+    2974:	2b00      	cmp	r3, #0
+    2976:	dc00      	bgt.n	297a <__sflush_r+0xee>
+    2978:	e794      	b.n	28a4 <__sflush_r+0x18>
+    297a:	9b01      	ldr	r3, [sp, #4]
+    297c:	003a      	movs	r2, r7
+    297e:	6a21      	ldr	r1, [r4, #32]
+    2980:	0028      	movs	r0, r5
+    2982:	6aa6      	ldr	r6, [r4, #40]	; 0x28
+    2984:	47b0      	blx	r6
+    2986:	2800      	cmp	r0, #0
+    2988:	dc03      	bgt.n	2992 <__sflush_r+0x106>
+    298a:	2340      	movs	r3, #64	; 0x40
+    298c:	89a2      	ldrh	r2, [r4, #12]
+    298e:	4313      	orrs	r3, r2
+    2990:	e7df      	b.n	2952 <__sflush_r+0xc6>
+    2992:	9b01      	ldr	r3, [sp, #4]
+    2994:	183f      	adds	r7, r7, r0
+    2996:	1a1b      	subs	r3, r3, r0
+    2998:	9301      	str	r3, [sp, #4]
+    299a:	e7ea      	b.n	2972 <__sflush_r+0xe6>
+    299c:	20400001 	.word	0x20400001
+
+000029a0 <_fflush_r>:
+    29a0:	690b      	ldr	r3, [r1, #16]
+    29a2:	b570      	push	{r4, r5, r6, lr}
+    29a4:	0005      	movs	r5, r0
+    29a6:	000c      	movs	r4, r1
+    29a8:	2b00      	cmp	r3, #0
+    29aa:	d101      	bne.n	29b0 <_fflush_r+0x10>
+    29ac:	2000      	movs	r0, #0
+    29ae:	bd70      	pop	{r4, r5, r6, pc}
+    29b0:	2800      	cmp	r0, #0
+    29b2:	d004      	beq.n	29be <_fflush_r+0x1e>
+    29b4:	6983      	ldr	r3, [r0, #24]
+    29b6:	2b00      	cmp	r3, #0
+    29b8:	d101      	bne.n	29be <_fflush_r+0x1e>
+    29ba:	f000 f85f 	bl	2a7c <__sinit>
+    29be:	4b0b      	ldr	r3, [pc, #44]	; (29ec <_fflush_r+0x4c>)
+    29c0:	429c      	cmp	r4, r3
+    29c2:	d109      	bne.n	29d8 <_fflush_r+0x38>
+    29c4:	686c      	ldr	r4, [r5, #4]
+    29c6:	220c      	movs	r2, #12
+    29c8:	5ea3      	ldrsh	r3, [r4, r2]
+    29ca:	2b00      	cmp	r3, #0
+    29cc:	d0ee      	beq.n	29ac <_fflush_r+0xc>
+    29ce:	0021      	movs	r1, r4
+    29d0:	0028      	movs	r0, r5
+    29d2:	f7ff ff5b 	bl	288c <__sflush_r>
+    29d6:	e7ea      	b.n	29ae <_fflush_r+0xe>
+    29d8:	4b05      	ldr	r3, [pc, #20]	; (29f0 <_fflush_r+0x50>)
+    29da:	429c      	cmp	r4, r3
+    29dc:	d101      	bne.n	29e2 <_fflush_r+0x42>
+    29de:	68ac      	ldr	r4, [r5, #8]
+    29e0:	e7f1      	b.n	29c6 <_fflush_r+0x26>
+    29e2:	4b04      	ldr	r3, [pc, #16]	; (29f4 <_fflush_r+0x54>)
+    29e4:	429c      	cmp	r4, r3
+    29e6:	d1ee      	bne.n	29c6 <_fflush_r+0x26>
+    29e8:	68ec      	ldr	r4, [r5, #12]
+    29ea:	e7ec      	b.n	29c6 <_fflush_r+0x26>
+    29ec:	000038cc 	.word	0x000038cc
+    29f0:	000038ec 	.word	0x000038ec
+    29f4:	000038ac 	.word	0x000038ac
+
+000029f8 <_cleanup_r>:
+    29f8:	b510      	push	{r4, lr}
+    29fa:	4902      	ldr	r1, [pc, #8]	; (2a04 <_cleanup_r+0xc>)
+    29fc:	f000 f8b2 	bl	2b64 <_fwalk_reent>
+    2a00:	bd10      	pop	{r4, pc}
+    2a02:	46c0      	nop			; (mov r8, r8)
+    2a04:	000029a1 	.word	0x000029a1
+
+00002a08 <std.isra.0>:
+    2a08:	2300      	movs	r3, #0
+    2a0a:	b510      	push	{r4, lr}
+    2a0c:	0004      	movs	r4, r0
+    2a0e:	6003      	str	r3, [r0, #0]
+    2a10:	6043      	str	r3, [r0, #4]
+    2a12:	6083      	str	r3, [r0, #8]
+    2a14:	8181      	strh	r1, [r0, #12]
+    2a16:	6643      	str	r3, [r0, #100]	; 0x64
+    2a18:	81c2      	strh	r2, [r0, #14]
+    2a1a:	6103      	str	r3, [r0, #16]
+    2a1c:	6143      	str	r3, [r0, #20]
+    2a1e:	6183      	str	r3, [r0, #24]
+    2a20:	0019      	movs	r1, r3
+    2a22:	2208      	movs	r2, #8
+    2a24:	305c      	adds	r0, #92	; 0x5c
+    2a26:	f7ff fe58 	bl	26da <memset>
+    2a2a:	4b05      	ldr	r3, [pc, #20]	; (2a40 <std.isra.0+0x38>)
+    2a2c:	6224      	str	r4, [r4, #32]
+    2a2e:	6263      	str	r3, [r4, #36]	; 0x24
+    2a30:	4b04      	ldr	r3, [pc, #16]	; (2a44 <std.isra.0+0x3c>)
+    2a32:	62a3      	str	r3, [r4, #40]	; 0x28
+    2a34:	4b04      	ldr	r3, [pc, #16]	; (2a48 <std.isra.0+0x40>)
+    2a36:	62e3      	str	r3, [r4, #44]	; 0x2c
+    2a38:	4b04      	ldr	r3, [pc, #16]	; (2a4c <std.isra.0+0x44>)
+    2a3a:	6323      	str	r3, [r4, #48]	; 0x30
+    2a3c:	bd10      	pop	{r4, pc}
+    2a3e:	46c0      	nop			; (mov r8, r8)
+    2a40:	000033a1 	.word	0x000033a1
+    2a44:	000033c9 	.word	0x000033c9
+    2a48:	00003401 	.word	0x00003401
+    2a4c:	0000342d 	.word	0x0000342d
+
+00002a50 <__sfmoreglue>:
+    2a50:	b570      	push	{r4, r5, r6, lr}
+    2a52:	2568      	movs	r5, #104	; 0x68
+    2a54:	1e4a      	subs	r2, r1, #1
+    2a56:	4355      	muls	r5, r2
+    2a58:	000e      	movs	r6, r1
+    2a5a:	0029      	movs	r1, r5
+    2a5c:	3174      	adds	r1, #116	; 0x74
+    2a5e:	f000 f963 	bl	2d28 <_malloc_r>
+    2a62:	1e04      	subs	r4, r0, #0
+    2a64:	d008      	beq.n	2a78 <__sfmoreglue+0x28>
+    2a66:	2100      	movs	r1, #0
+    2a68:	002a      	movs	r2, r5
+    2a6a:	6001      	str	r1, [r0, #0]
+    2a6c:	6046      	str	r6, [r0, #4]
+    2a6e:	300c      	adds	r0, #12
+    2a70:	60a0      	str	r0, [r4, #8]
+    2a72:	3268      	adds	r2, #104	; 0x68
+    2a74:	f7ff fe31 	bl	26da <memset>
+    2a78:	0020      	movs	r0, r4
+    2a7a:	bd70      	pop	{r4, r5, r6, pc}
+
+00002a7c <__sinit>:
+    2a7c:	6983      	ldr	r3, [r0, #24]
+    2a7e:	b513      	push	{r0, r1, r4, lr}
+    2a80:	0004      	movs	r4, r0
+    2a82:	2b00      	cmp	r3, #0
+    2a84:	d128      	bne.n	2ad8 <__sinit+0x5c>
+    2a86:	6483      	str	r3, [r0, #72]	; 0x48
+    2a88:	64c3      	str	r3, [r0, #76]	; 0x4c
+    2a8a:	6503      	str	r3, [r0, #80]	; 0x50
+    2a8c:	4b13      	ldr	r3, [pc, #76]	; (2adc <__sinit+0x60>)
+    2a8e:	4a14      	ldr	r2, [pc, #80]	; (2ae0 <__sinit+0x64>)
+    2a90:	681b      	ldr	r3, [r3, #0]
+    2a92:	6282      	str	r2, [r0, #40]	; 0x28
+    2a94:	9301      	str	r3, [sp, #4]
+    2a96:	4298      	cmp	r0, r3
+    2a98:	d101      	bne.n	2a9e <__sinit+0x22>
+    2a9a:	2301      	movs	r3, #1
+    2a9c:	6183      	str	r3, [r0, #24]
+    2a9e:	0020      	movs	r0, r4
+    2aa0:	f000 f820 	bl	2ae4 <__sfp>
+    2aa4:	6060      	str	r0, [r4, #4]
+    2aa6:	0020      	movs	r0, r4
+    2aa8:	f000 f81c 	bl	2ae4 <__sfp>
+    2aac:	60a0      	str	r0, [r4, #8]
+    2aae:	0020      	movs	r0, r4
+    2ab0:	f000 f818 	bl	2ae4 <__sfp>
+    2ab4:	2200      	movs	r2, #0
+    2ab6:	60e0      	str	r0, [r4, #12]
+    2ab8:	2104      	movs	r1, #4
+    2aba:	6860      	ldr	r0, [r4, #4]
+    2abc:	f7ff ffa4 	bl	2a08 <std.isra.0>
+    2ac0:	2201      	movs	r2, #1
+    2ac2:	2109      	movs	r1, #9
+    2ac4:	68a0      	ldr	r0, [r4, #8]
+    2ac6:	f7ff ff9f 	bl	2a08 <std.isra.0>
+    2aca:	2202      	movs	r2, #2
+    2acc:	2112      	movs	r1, #18
+    2ace:	68e0      	ldr	r0, [r4, #12]
+    2ad0:	f7ff ff9a 	bl	2a08 <std.isra.0>
+    2ad4:	2301      	movs	r3, #1
+    2ad6:	61a3      	str	r3, [r4, #24]
+    2ad8:	bd13      	pop	{r0, r1, r4, pc}
+    2ada:	46c0      	nop			; (mov r8, r8)
+    2adc:	000038a8 	.word	0x000038a8
+    2ae0:	000029f9 	.word	0x000029f9
+
+00002ae4 <__sfp>:
+    2ae4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    2ae6:	4b1e      	ldr	r3, [pc, #120]	; (2b60 <__sfp+0x7c>)
+    2ae8:	0007      	movs	r7, r0
+    2aea:	681e      	ldr	r6, [r3, #0]
+    2aec:	69b3      	ldr	r3, [r6, #24]
+    2aee:	2b00      	cmp	r3, #0
+    2af0:	d102      	bne.n	2af8 <__sfp+0x14>
+    2af2:	0030      	movs	r0, r6
+    2af4:	f7ff ffc2 	bl	2a7c <__sinit>
+    2af8:	3648      	adds	r6, #72	; 0x48
+    2afa:	68b4      	ldr	r4, [r6, #8]
+    2afc:	6873      	ldr	r3, [r6, #4]
+    2afe:	3b01      	subs	r3, #1
+    2b00:	d504      	bpl.n	2b0c <__sfp+0x28>
+    2b02:	6833      	ldr	r3, [r6, #0]
+    2b04:	2b00      	cmp	r3, #0
+    2b06:	d007      	beq.n	2b18 <__sfp+0x34>
+    2b08:	6836      	ldr	r6, [r6, #0]
+    2b0a:	e7f6      	b.n	2afa <__sfp+0x16>
+    2b0c:	220c      	movs	r2, #12
+    2b0e:	5ea5      	ldrsh	r5, [r4, r2]
+    2b10:	2d00      	cmp	r5, #0
+    2b12:	d00d      	beq.n	2b30 <__sfp+0x4c>
+    2b14:	3468      	adds	r4, #104	; 0x68
+    2b16:	e7f2      	b.n	2afe <__sfp+0x1a>
+    2b18:	2104      	movs	r1, #4
+    2b1a:	0038      	movs	r0, r7
+    2b1c:	f7ff ff98 	bl	2a50 <__sfmoreglue>
+    2b20:	6030      	str	r0, [r6, #0]
+    2b22:	2800      	cmp	r0, #0
+    2b24:	d1f0      	bne.n	2b08 <__sfp+0x24>
+    2b26:	230c      	movs	r3, #12
+    2b28:	0004      	movs	r4, r0
+    2b2a:	603b      	str	r3, [r7, #0]
+    2b2c:	0020      	movs	r0, r4
+    2b2e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    2b30:	2301      	movs	r3, #1
+    2b32:	0020      	movs	r0, r4
+    2b34:	425b      	negs	r3, r3
+    2b36:	81e3      	strh	r3, [r4, #14]
+    2b38:	3302      	adds	r3, #2
+    2b3a:	81a3      	strh	r3, [r4, #12]
+    2b3c:	6665      	str	r5, [r4, #100]	; 0x64
+    2b3e:	6025      	str	r5, [r4, #0]
+    2b40:	60a5      	str	r5, [r4, #8]
+    2b42:	6065      	str	r5, [r4, #4]
+    2b44:	6125      	str	r5, [r4, #16]
+    2b46:	6165      	str	r5, [r4, #20]
+    2b48:	61a5      	str	r5, [r4, #24]
+    2b4a:	2208      	movs	r2, #8
+    2b4c:	0029      	movs	r1, r5
+    2b4e:	305c      	adds	r0, #92	; 0x5c
+    2b50:	f7ff fdc3 	bl	26da <memset>
+    2b54:	6365      	str	r5, [r4, #52]	; 0x34
+    2b56:	63a5      	str	r5, [r4, #56]	; 0x38
+    2b58:	64a5      	str	r5, [r4, #72]	; 0x48
+    2b5a:	64e5      	str	r5, [r4, #76]	; 0x4c
+    2b5c:	e7e6      	b.n	2b2c <__sfp+0x48>
+    2b5e:	46c0      	nop			; (mov r8, r8)
+    2b60:	000038a8 	.word	0x000038a8
+
+00002b64 <_fwalk_reent>:
+    2b64:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    2b66:	0004      	movs	r4, r0
+    2b68:	0007      	movs	r7, r0
+    2b6a:	2600      	movs	r6, #0
+    2b6c:	9101      	str	r1, [sp, #4]
+    2b6e:	3448      	adds	r4, #72	; 0x48
+    2b70:	2c00      	cmp	r4, #0
+    2b72:	d101      	bne.n	2b78 <_fwalk_reent+0x14>
+    2b74:	0030      	movs	r0, r6
+    2b76:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    2b78:	6863      	ldr	r3, [r4, #4]
+    2b7a:	68a5      	ldr	r5, [r4, #8]
+    2b7c:	9300      	str	r3, [sp, #0]
+    2b7e:	9b00      	ldr	r3, [sp, #0]
+    2b80:	3b01      	subs	r3, #1
+    2b82:	9300      	str	r3, [sp, #0]
+    2b84:	d501      	bpl.n	2b8a <_fwalk_reent+0x26>
+    2b86:	6824      	ldr	r4, [r4, #0]
+    2b88:	e7f2      	b.n	2b70 <_fwalk_reent+0xc>
+    2b8a:	89ab      	ldrh	r3, [r5, #12]
+    2b8c:	2b01      	cmp	r3, #1
+    2b8e:	d908      	bls.n	2ba2 <_fwalk_reent+0x3e>
+    2b90:	220e      	movs	r2, #14
+    2b92:	5eab      	ldrsh	r3, [r5, r2]
+    2b94:	3301      	adds	r3, #1
+    2b96:	d004      	beq.n	2ba2 <_fwalk_reent+0x3e>
+    2b98:	0029      	movs	r1, r5
+    2b9a:	0038      	movs	r0, r7
+    2b9c:	9b01      	ldr	r3, [sp, #4]
+    2b9e:	4798      	blx	r3
+    2ba0:	4306      	orrs	r6, r0
+    2ba2:	3568      	adds	r5, #104	; 0x68
+    2ba4:	e7eb      	b.n	2b7e <_fwalk_reent+0x1a>
+	...
+
+00002ba8 <__swhatbuf_r>:
+    2ba8:	b570      	push	{r4, r5, r6, lr}
+    2baa:	000e      	movs	r6, r1
+    2bac:	001d      	movs	r5, r3
+    2bae:	230e      	movs	r3, #14
+    2bb0:	5ec9      	ldrsh	r1, [r1, r3]
+    2bb2:	b090      	sub	sp, #64	; 0x40
+    2bb4:	0014      	movs	r4, r2
+    2bb6:	2900      	cmp	r1, #0
+    2bb8:	da07      	bge.n	2bca <__swhatbuf_r+0x22>
+    2bba:	2300      	movs	r3, #0
+    2bbc:	602b      	str	r3, [r5, #0]
+    2bbe:	89b3      	ldrh	r3, [r6, #12]
+    2bc0:	061b      	lsls	r3, r3, #24
+    2bc2:	d411      	bmi.n	2be8 <__swhatbuf_r+0x40>
+    2bc4:	2380      	movs	r3, #128	; 0x80
+    2bc6:	00db      	lsls	r3, r3, #3
+    2bc8:	e00f      	b.n	2bea <__swhatbuf_r+0x42>
+    2bca:	aa01      	add	r2, sp, #4
+    2bcc:	f000 fd26 	bl	361c <_fstat_r>
+    2bd0:	2800      	cmp	r0, #0
+    2bd2:	dbf2      	blt.n	2bba <__swhatbuf_r+0x12>
+    2bd4:	22f0      	movs	r2, #240	; 0xf0
+    2bd6:	9b02      	ldr	r3, [sp, #8]
+    2bd8:	0212      	lsls	r2, r2, #8
+    2bda:	4013      	ands	r3, r2
+    2bdc:	4a05      	ldr	r2, [pc, #20]	; (2bf4 <__swhatbuf_r+0x4c>)
+    2bde:	189b      	adds	r3, r3, r2
+    2be0:	425a      	negs	r2, r3
+    2be2:	4153      	adcs	r3, r2
+    2be4:	602b      	str	r3, [r5, #0]
+    2be6:	e7ed      	b.n	2bc4 <__swhatbuf_r+0x1c>
+    2be8:	2340      	movs	r3, #64	; 0x40
+    2bea:	2000      	movs	r0, #0
+    2bec:	6023      	str	r3, [r4, #0]
+    2bee:	b010      	add	sp, #64	; 0x40
+    2bf0:	bd70      	pop	{r4, r5, r6, pc}
+    2bf2:	46c0      	nop			; (mov r8, r8)
+    2bf4:	ffffe000 	.word	0xffffe000
+
+00002bf8 <__smakebuf_r>:
+    2bf8:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    2bfa:	2602      	movs	r6, #2
+    2bfc:	898b      	ldrh	r3, [r1, #12]
+    2bfe:	0005      	movs	r5, r0
+    2c00:	000c      	movs	r4, r1
+    2c02:	4233      	tst	r3, r6
+    2c04:	d006      	beq.n	2c14 <__smakebuf_r+0x1c>
+    2c06:	0023      	movs	r3, r4
+    2c08:	3347      	adds	r3, #71	; 0x47
+    2c0a:	6023      	str	r3, [r4, #0]
+    2c0c:	6123      	str	r3, [r4, #16]
+    2c0e:	2301      	movs	r3, #1
+    2c10:	6163      	str	r3, [r4, #20]
+    2c12:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
+    2c14:	ab01      	add	r3, sp, #4
+    2c16:	466a      	mov	r2, sp
+    2c18:	f7ff ffc6 	bl	2ba8 <__swhatbuf_r>
+    2c1c:	9900      	ldr	r1, [sp, #0]
+    2c1e:	0007      	movs	r7, r0
+    2c20:	0028      	movs	r0, r5
+    2c22:	f000 f881 	bl	2d28 <_malloc_r>
+    2c26:	2800      	cmp	r0, #0
+    2c28:	d108      	bne.n	2c3c <__smakebuf_r+0x44>
+    2c2a:	220c      	movs	r2, #12
+    2c2c:	5ea3      	ldrsh	r3, [r4, r2]
+    2c2e:	059a      	lsls	r2, r3, #22
+    2c30:	d4ef      	bmi.n	2c12 <__smakebuf_r+0x1a>
+    2c32:	2203      	movs	r2, #3
+    2c34:	4393      	bics	r3, r2
+    2c36:	431e      	orrs	r6, r3
+    2c38:	81a6      	strh	r6, [r4, #12]
+    2c3a:	e7e4      	b.n	2c06 <__smakebuf_r+0xe>
+    2c3c:	4b0f      	ldr	r3, [pc, #60]	; (2c7c <__smakebuf_r+0x84>)
+    2c3e:	62ab      	str	r3, [r5, #40]	; 0x28
+    2c40:	2380      	movs	r3, #128	; 0x80
+    2c42:	89a2      	ldrh	r2, [r4, #12]
+    2c44:	6020      	str	r0, [r4, #0]
+    2c46:	4313      	orrs	r3, r2
+    2c48:	81a3      	strh	r3, [r4, #12]
+    2c4a:	9b00      	ldr	r3, [sp, #0]
+    2c4c:	6120      	str	r0, [r4, #16]
+    2c4e:	6163      	str	r3, [r4, #20]
+    2c50:	9b01      	ldr	r3, [sp, #4]
+    2c52:	2b00      	cmp	r3, #0
+    2c54:	d00d      	beq.n	2c72 <__smakebuf_r+0x7a>
+    2c56:	230e      	movs	r3, #14
+    2c58:	5ee1      	ldrsh	r1, [r4, r3]
+    2c5a:	0028      	movs	r0, r5
+    2c5c:	f000 fcf0 	bl	3640 <_isatty_r>
+    2c60:	2800      	cmp	r0, #0
+    2c62:	d006      	beq.n	2c72 <__smakebuf_r+0x7a>
+    2c64:	2203      	movs	r2, #3
+    2c66:	89a3      	ldrh	r3, [r4, #12]
+    2c68:	4393      	bics	r3, r2
+    2c6a:	001a      	movs	r2, r3
+    2c6c:	2301      	movs	r3, #1
+    2c6e:	4313      	orrs	r3, r2
+    2c70:	81a3      	strh	r3, [r4, #12]
+    2c72:	89a0      	ldrh	r0, [r4, #12]
+    2c74:	4338      	orrs	r0, r7
+    2c76:	81a0      	strh	r0, [r4, #12]
+    2c78:	e7cb      	b.n	2c12 <__smakebuf_r+0x1a>
+    2c7a:	46c0      	nop			; (mov r8, r8)
+    2c7c:	000029f9 	.word	0x000029f9
+
+00002c80 <malloc>:
+    2c80:	b510      	push	{r4, lr}
+    2c82:	4b03      	ldr	r3, [pc, #12]	; (2c90 <malloc+0x10>)
+    2c84:	0001      	movs	r1, r0
+    2c86:	6818      	ldr	r0, [r3, #0]
+    2c88:	f000 f84e 	bl	2d28 <_malloc_r>
+    2c8c:	bd10      	pop	{r4, pc}
+    2c8e:	46c0      	nop			; (mov r8, r8)
+    2c90:	20000018 	.word	0x20000018
+
+00002c94 <_free_r>:
+    2c94:	b570      	push	{r4, r5, r6, lr}
+    2c96:	0005      	movs	r5, r0
+    2c98:	2900      	cmp	r1, #0
+    2c9a:	d010      	beq.n	2cbe <_free_r+0x2a>
+    2c9c:	1f0c      	subs	r4, r1, #4
+    2c9e:	6823      	ldr	r3, [r4, #0]
+    2ca0:	2b00      	cmp	r3, #0
+    2ca2:	da00      	bge.n	2ca6 <_free_r+0x12>
+    2ca4:	18e4      	adds	r4, r4, r3
+    2ca6:	0028      	movs	r0, r5
+    2ca8:	f000 fcfb 	bl	36a2 <__malloc_lock>
+    2cac:	4a1d      	ldr	r2, [pc, #116]	; (2d24 <_free_r+0x90>)
+    2cae:	6813      	ldr	r3, [r2, #0]
+    2cb0:	2b00      	cmp	r3, #0
+    2cb2:	d105      	bne.n	2cc0 <_free_r+0x2c>
+    2cb4:	6063      	str	r3, [r4, #4]
+    2cb6:	6014      	str	r4, [r2, #0]
+    2cb8:	0028      	movs	r0, r5
+    2cba:	f000 fcf3 	bl	36a4 <__malloc_unlock>
+    2cbe:	bd70      	pop	{r4, r5, r6, pc}
+    2cc0:	42a3      	cmp	r3, r4
+    2cc2:	d909      	bls.n	2cd8 <_free_r+0x44>
+    2cc4:	6821      	ldr	r1, [r4, #0]
+    2cc6:	1860      	adds	r0, r4, r1
+    2cc8:	4283      	cmp	r3, r0
+    2cca:	d1f3      	bne.n	2cb4 <_free_r+0x20>
+    2ccc:	6818      	ldr	r0, [r3, #0]
+    2cce:	685b      	ldr	r3, [r3, #4]
+    2cd0:	1841      	adds	r1, r0, r1
+    2cd2:	6021      	str	r1, [r4, #0]
+    2cd4:	e7ee      	b.n	2cb4 <_free_r+0x20>
+    2cd6:	0013      	movs	r3, r2
+    2cd8:	685a      	ldr	r2, [r3, #4]
+    2cda:	2a00      	cmp	r2, #0
+    2cdc:	d001      	beq.n	2ce2 <_free_r+0x4e>
+    2cde:	42a2      	cmp	r2, r4
+    2ce0:	d9f9      	bls.n	2cd6 <_free_r+0x42>
+    2ce2:	6819      	ldr	r1, [r3, #0]
+    2ce4:	1858      	adds	r0, r3, r1
+    2ce6:	42a0      	cmp	r0, r4
+    2ce8:	d10b      	bne.n	2d02 <_free_r+0x6e>
+    2cea:	6820      	ldr	r0, [r4, #0]
+    2cec:	1809      	adds	r1, r1, r0
+    2cee:	1858      	adds	r0, r3, r1
+    2cf0:	6019      	str	r1, [r3, #0]
+    2cf2:	4282      	cmp	r2, r0
+    2cf4:	d1e0      	bne.n	2cb8 <_free_r+0x24>
+    2cf6:	6810      	ldr	r0, [r2, #0]
+    2cf8:	6852      	ldr	r2, [r2, #4]
+    2cfa:	1841      	adds	r1, r0, r1
+    2cfc:	6019      	str	r1, [r3, #0]
+    2cfe:	605a      	str	r2, [r3, #4]
+    2d00:	e7da      	b.n	2cb8 <_free_r+0x24>
+    2d02:	42a0      	cmp	r0, r4
+    2d04:	d902      	bls.n	2d0c <_free_r+0x78>
+    2d06:	230c      	movs	r3, #12
+    2d08:	602b      	str	r3, [r5, #0]
+    2d0a:	e7d5      	b.n	2cb8 <_free_r+0x24>
+    2d0c:	6821      	ldr	r1, [r4, #0]
+    2d0e:	1860      	adds	r0, r4, r1
+    2d10:	4282      	cmp	r2, r0
+    2d12:	d103      	bne.n	2d1c <_free_r+0x88>
+    2d14:	6810      	ldr	r0, [r2, #0]
+    2d16:	6852      	ldr	r2, [r2, #4]
+    2d18:	1841      	adds	r1, r0, r1
+    2d1a:	6021      	str	r1, [r4, #0]
+    2d1c:	6062      	str	r2, [r4, #4]
+    2d1e:	605c      	str	r4, [r3, #4]
+    2d20:	e7ca      	b.n	2cb8 <_free_r+0x24>
+    2d22:	46c0      	nop			; (mov r8, r8)
+    2d24:	200001d0 	.word	0x200001d0
+
+00002d28 <_malloc_r>:
+    2d28:	2303      	movs	r3, #3
+    2d2a:	b570      	push	{r4, r5, r6, lr}
+    2d2c:	1ccd      	adds	r5, r1, #3
+    2d2e:	439d      	bics	r5, r3
+    2d30:	3508      	adds	r5, #8
+    2d32:	0006      	movs	r6, r0
+    2d34:	2d0c      	cmp	r5, #12
+    2d36:	d21e      	bcs.n	2d76 <_malloc_r+0x4e>
+    2d38:	250c      	movs	r5, #12
+    2d3a:	42a9      	cmp	r1, r5
+    2d3c:	d81d      	bhi.n	2d7a <_malloc_r+0x52>
+    2d3e:	0030      	movs	r0, r6
+    2d40:	f000 fcaf 	bl	36a2 <__malloc_lock>
+    2d44:	4a25      	ldr	r2, [pc, #148]	; (2ddc <_malloc_r+0xb4>)
+    2d46:	6814      	ldr	r4, [r2, #0]
+    2d48:	0021      	movs	r1, r4
+    2d4a:	2900      	cmp	r1, #0
+    2d4c:	d119      	bne.n	2d82 <_malloc_r+0x5a>
+    2d4e:	4c24      	ldr	r4, [pc, #144]	; (2de0 <_malloc_r+0xb8>)
+    2d50:	6823      	ldr	r3, [r4, #0]
+    2d52:	2b00      	cmp	r3, #0
+    2d54:	d103      	bne.n	2d5e <_malloc_r+0x36>
+    2d56:	0030      	movs	r0, r6
+    2d58:	f000 fb10 	bl	337c <_sbrk_r>
+    2d5c:	6020      	str	r0, [r4, #0]
+    2d5e:	0029      	movs	r1, r5
+    2d60:	0030      	movs	r0, r6
+    2d62:	f000 fb0b 	bl	337c <_sbrk_r>
+    2d66:	1c43      	adds	r3, r0, #1
+    2d68:	d12c      	bne.n	2dc4 <_malloc_r+0x9c>
+    2d6a:	230c      	movs	r3, #12
+    2d6c:	0030      	movs	r0, r6
+    2d6e:	6033      	str	r3, [r6, #0]
+    2d70:	f000 fc98 	bl	36a4 <__malloc_unlock>
+    2d74:	e003      	b.n	2d7e <_malloc_r+0x56>
+    2d76:	2d00      	cmp	r5, #0
+    2d78:	dadf      	bge.n	2d3a <_malloc_r+0x12>
+    2d7a:	230c      	movs	r3, #12
+    2d7c:	6033      	str	r3, [r6, #0]
+    2d7e:	2000      	movs	r0, #0
+    2d80:	bd70      	pop	{r4, r5, r6, pc}
+    2d82:	680b      	ldr	r3, [r1, #0]
+    2d84:	1b5b      	subs	r3, r3, r5
+    2d86:	d41a      	bmi.n	2dbe <_malloc_r+0x96>
+    2d88:	2b0b      	cmp	r3, #11
+    2d8a:	d903      	bls.n	2d94 <_malloc_r+0x6c>
+    2d8c:	600b      	str	r3, [r1, #0]
+    2d8e:	18cc      	adds	r4, r1, r3
+    2d90:	6025      	str	r5, [r4, #0]
+    2d92:	e003      	b.n	2d9c <_malloc_r+0x74>
+    2d94:	428c      	cmp	r4, r1
+    2d96:	d10e      	bne.n	2db6 <_malloc_r+0x8e>
+    2d98:	6863      	ldr	r3, [r4, #4]
+    2d9a:	6013      	str	r3, [r2, #0]
+    2d9c:	0030      	movs	r0, r6
+    2d9e:	f000 fc81 	bl	36a4 <__malloc_unlock>
+    2da2:	0020      	movs	r0, r4
+    2da4:	2207      	movs	r2, #7
+    2da6:	300b      	adds	r0, #11
+    2da8:	1d23      	adds	r3, r4, #4
+    2daa:	4390      	bics	r0, r2
+    2dac:	1ac3      	subs	r3, r0, r3
+    2dae:	d0e7      	beq.n	2d80 <_malloc_r+0x58>
+    2db0:	425a      	negs	r2, r3
+    2db2:	50e2      	str	r2, [r4, r3]
+    2db4:	e7e4      	b.n	2d80 <_malloc_r+0x58>
+    2db6:	684b      	ldr	r3, [r1, #4]
+    2db8:	6063      	str	r3, [r4, #4]
+    2dba:	000c      	movs	r4, r1
+    2dbc:	e7ee      	b.n	2d9c <_malloc_r+0x74>
+    2dbe:	000c      	movs	r4, r1
+    2dc0:	6849      	ldr	r1, [r1, #4]
+    2dc2:	e7c2      	b.n	2d4a <_malloc_r+0x22>
+    2dc4:	2303      	movs	r3, #3
+    2dc6:	1cc4      	adds	r4, r0, #3
+    2dc8:	439c      	bics	r4, r3
+    2dca:	42a0      	cmp	r0, r4
+    2dcc:	d0e0      	beq.n	2d90 <_malloc_r+0x68>
+    2dce:	1a21      	subs	r1, r4, r0
+    2dd0:	0030      	movs	r0, r6
+    2dd2:	f000 fad3 	bl	337c <_sbrk_r>
+    2dd6:	1c43      	adds	r3, r0, #1
+    2dd8:	d1da      	bne.n	2d90 <_malloc_r+0x68>
+    2dda:	e7c6      	b.n	2d6a <_malloc_r+0x42>
+    2ddc:	200001d0 	.word	0x200001d0
+    2de0:	200001d4 	.word	0x200001d4
+
+00002de4 <__sfputc_r>:
+    2de4:	6893      	ldr	r3, [r2, #8]
+    2de6:	b510      	push	{r4, lr}
+    2de8:	3b01      	subs	r3, #1
+    2dea:	6093      	str	r3, [r2, #8]
+    2dec:	2b00      	cmp	r3, #0
+    2dee:	da05      	bge.n	2dfc <__sfputc_r+0x18>
+    2df0:	6994      	ldr	r4, [r2, #24]
+    2df2:	42a3      	cmp	r3, r4
+    2df4:	db08      	blt.n	2e08 <__sfputc_r+0x24>
+    2df6:	b2cb      	uxtb	r3, r1
+    2df8:	2b0a      	cmp	r3, #10
+    2dfa:	d005      	beq.n	2e08 <__sfputc_r+0x24>
+    2dfc:	6813      	ldr	r3, [r2, #0]
+    2dfe:	1c58      	adds	r0, r3, #1
+    2e00:	6010      	str	r0, [r2, #0]
+    2e02:	7019      	strb	r1, [r3, #0]
+    2e04:	b2c8      	uxtb	r0, r1
+    2e06:	bd10      	pop	{r4, pc}
+    2e08:	f000 fb16 	bl	3438 <__swbuf_r>
+    2e0c:	e7fb      	b.n	2e06 <__sfputc_r+0x22>
+
+00002e0e <__sfputs_r>:
+    2e0e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    2e10:	0006      	movs	r6, r0
+    2e12:	000f      	movs	r7, r1
+    2e14:	0014      	movs	r4, r2
+    2e16:	18d5      	adds	r5, r2, r3
+    2e18:	42ac      	cmp	r4, r5
+    2e1a:	d101      	bne.n	2e20 <__sfputs_r+0x12>
+    2e1c:	2000      	movs	r0, #0
+    2e1e:	e007      	b.n	2e30 <__sfputs_r+0x22>
+    2e20:	7821      	ldrb	r1, [r4, #0]
+    2e22:	003a      	movs	r2, r7
+    2e24:	0030      	movs	r0, r6
+    2e26:	f7ff ffdd 	bl	2de4 <__sfputc_r>
+    2e2a:	3401      	adds	r4, #1
+    2e2c:	1c43      	adds	r3, r0, #1
+    2e2e:	d1f3      	bne.n	2e18 <__sfputs_r+0xa>
+    2e30:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+	...
+
+00002e34 <_vfiprintf_r>:
+    2e34:	b5f0      	push	{r4, r5, r6, r7, lr}
+    2e36:	b09f      	sub	sp, #124	; 0x7c
+    2e38:	0006      	movs	r6, r0
+    2e3a:	000f      	movs	r7, r1
+    2e3c:	0014      	movs	r4, r2
+    2e3e:	9305      	str	r3, [sp, #20]
+    2e40:	2800      	cmp	r0, #0
+    2e42:	d004      	beq.n	2e4e <_vfiprintf_r+0x1a>
+    2e44:	6983      	ldr	r3, [r0, #24]
+    2e46:	2b00      	cmp	r3, #0
+    2e48:	d101      	bne.n	2e4e <_vfiprintf_r+0x1a>
+    2e4a:	f7ff fe17 	bl	2a7c <__sinit>
+    2e4e:	4b7f      	ldr	r3, [pc, #508]	; (304c <_vfiprintf_r+0x218>)
+    2e50:	429f      	cmp	r7, r3
+    2e52:	d15c      	bne.n	2f0e <_vfiprintf_r+0xda>
+    2e54:	6877      	ldr	r7, [r6, #4]
+    2e56:	89bb      	ldrh	r3, [r7, #12]
+    2e58:	071b      	lsls	r3, r3, #28
+    2e5a:	d562      	bpl.n	2f22 <_vfiprintf_r+0xee>
+    2e5c:	693b      	ldr	r3, [r7, #16]
+    2e5e:	2b00      	cmp	r3, #0
+    2e60:	d05f      	beq.n	2f22 <_vfiprintf_r+0xee>
+    2e62:	2300      	movs	r3, #0
+    2e64:	ad06      	add	r5, sp, #24
+    2e66:	616b      	str	r3, [r5, #20]
+    2e68:	3320      	adds	r3, #32
+    2e6a:	766b      	strb	r3, [r5, #25]
+    2e6c:	3310      	adds	r3, #16
+    2e6e:	76ab      	strb	r3, [r5, #26]
+    2e70:	9402      	str	r4, [sp, #8]
+    2e72:	9c02      	ldr	r4, [sp, #8]
+    2e74:	7823      	ldrb	r3, [r4, #0]
+    2e76:	2b00      	cmp	r3, #0
+    2e78:	d15d      	bne.n	2f36 <_vfiprintf_r+0x102>
+    2e7a:	9b02      	ldr	r3, [sp, #8]
+    2e7c:	1ae3      	subs	r3, r4, r3
+    2e7e:	9304      	str	r3, [sp, #16]
+    2e80:	d00d      	beq.n	2e9e <_vfiprintf_r+0x6a>
+    2e82:	9b04      	ldr	r3, [sp, #16]
+    2e84:	9a02      	ldr	r2, [sp, #8]
+    2e86:	0039      	movs	r1, r7
+    2e88:	0030      	movs	r0, r6
+    2e8a:	f7ff ffc0 	bl	2e0e <__sfputs_r>
+    2e8e:	1c43      	adds	r3, r0, #1
+    2e90:	d100      	bne.n	2e94 <_vfiprintf_r+0x60>
+    2e92:	e0cc      	b.n	302e <_vfiprintf_r+0x1fa>
+    2e94:	696a      	ldr	r2, [r5, #20]
+    2e96:	9b04      	ldr	r3, [sp, #16]
+    2e98:	4694      	mov	ip, r2
+    2e9a:	4463      	add	r3, ip
+    2e9c:	616b      	str	r3, [r5, #20]
+    2e9e:	7823      	ldrb	r3, [r4, #0]
+    2ea0:	2b00      	cmp	r3, #0
+    2ea2:	d100      	bne.n	2ea6 <_vfiprintf_r+0x72>
+    2ea4:	e0c3      	b.n	302e <_vfiprintf_r+0x1fa>
+    2ea6:	2201      	movs	r2, #1
+    2ea8:	2300      	movs	r3, #0
+    2eaa:	4252      	negs	r2, r2
+    2eac:	606a      	str	r2, [r5, #4]
+    2eae:	a902      	add	r1, sp, #8
+    2eb0:	3254      	adds	r2, #84	; 0x54
+    2eb2:	1852      	adds	r2, r2, r1
+    2eb4:	3401      	adds	r4, #1
+    2eb6:	602b      	str	r3, [r5, #0]
+    2eb8:	60eb      	str	r3, [r5, #12]
+    2eba:	60ab      	str	r3, [r5, #8]
+    2ebc:	7013      	strb	r3, [r2, #0]
+    2ebe:	65ab      	str	r3, [r5, #88]	; 0x58
+    2ec0:	7821      	ldrb	r1, [r4, #0]
+    2ec2:	2205      	movs	r2, #5
+    2ec4:	4862      	ldr	r0, [pc, #392]	; (3050 <_vfiprintf_r+0x21c>)
+    2ec6:	f000 fbe1 	bl	368c <memchr>
+    2eca:	1c63      	adds	r3, r4, #1
+    2ecc:	469c      	mov	ip, r3
+    2ece:	2800      	cmp	r0, #0
+    2ed0:	d135      	bne.n	2f3e <_vfiprintf_r+0x10a>
+    2ed2:	6829      	ldr	r1, [r5, #0]
+    2ed4:	06cb      	lsls	r3, r1, #27
+    2ed6:	d504      	bpl.n	2ee2 <_vfiprintf_r+0xae>
+    2ed8:	2353      	movs	r3, #83	; 0x53
+    2eda:	aa02      	add	r2, sp, #8
+    2edc:	3020      	adds	r0, #32
+    2ede:	189b      	adds	r3, r3, r2
+    2ee0:	7018      	strb	r0, [r3, #0]
+    2ee2:	070b      	lsls	r3, r1, #28
+    2ee4:	d504      	bpl.n	2ef0 <_vfiprintf_r+0xbc>
+    2ee6:	2353      	movs	r3, #83	; 0x53
+    2ee8:	202b      	movs	r0, #43	; 0x2b
+    2eea:	aa02      	add	r2, sp, #8
+    2eec:	189b      	adds	r3, r3, r2
+    2eee:	7018      	strb	r0, [r3, #0]
+    2ef0:	7823      	ldrb	r3, [r4, #0]
+    2ef2:	2b2a      	cmp	r3, #42	; 0x2a
+    2ef4:	d02c      	beq.n	2f50 <_vfiprintf_r+0x11c>
+    2ef6:	2000      	movs	r0, #0
+    2ef8:	210a      	movs	r1, #10
+    2efa:	9b09      	ldr	r3, [sp, #36]	; 0x24
+    2efc:	7822      	ldrb	r2, [r4, #0]
+    2efe:	3a30      	subs	r2, #48	; 0x30
+    2f00:	2a09      	cmp	r2, #9
+    2f02:	d800      	bhi.n	2f06 <_vfiprintf_r+0xd2>
+    2f04:	e06b      	b.n	2fde <_vfiprintf_r+0x1aa>
+    2f06:	2800      	cmp	r0, #0
+    2f08:	d02a      	beq.n	2f60 <_vfiprintf_r+0x12c>
+    2f0a:	9309      	str	r3, [sp, #36]	; 0x24
+    2f0c:	e028      	b.n	2f60 <_vfiprintf_r+0x12c>
+    2f0e:	4b51      	ldr	r3, [pc, #324]	; (3054 <_vfiprintf_r+0x220>)
+    2f10:	429f      	cmp	r7, r3
+    2f12:	d101      	bne.n	2f18 <_vfiprintf_r+0xe4>
+    2f14:	68b7      	ldr	r7, [r6, #8]
+    2f16:	e79e      	b.n	2e56 <_vfiprintf_r+0x22>
+    2f18:	4b4f      	ldr	r3, [pc, #316]	; (3058 <_vfiprintf_r+0x224>)
+    2f1a:	429f      	cmp	r7, r3
+    2f1c:	d19b      	bne.n	2e56 <_vfiprintf_r+0x22>
+    2f1e:	68f7      	ldr	r7, [r6, #12]
+    2f20:	e799      	b.n	2e56 <_vfiprintf_r+0x22>
+    2f22:	0039      	movs	r1, r7
+    2f24:	0030      	movs	r0, r6
+    2f26:	f000 faf1 	bl	350c <__swsetup_r>
+    2f2a:	2800      	cmp	r0, #0
+    2f2c:	d099      	beq.n	2e62 <_vfiprintf_r+0x2e>
+    2f2e:	2001      	movs	r0, #1
+    2f30:	4240      	negs	r0, r0
+    2f32:	b01f      	add	sp, #124	; 0x7c
+    2f34:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    2f36:	2b25      	cmp	r3, #37	; 0x25
+    2f38:	d09f      	beq.n	2e7a <_vfiprintf_r+0x46>
+    2f3a:	3401      	adds	r4, #1
+    2f3c:	e79a      	b.n	2e74 <_vfiprintf_r+0x40>
+    2f3e:	4b44      	ldr	r3, [pc, #272]	; (3050 <_vfiprintf_r+0x21c>)
+    2f40:	6829      	ldr	r1, [r5, #0]
+    2f42:	1ac0      	subs	r0, r0, r3
+    2f44:	2301      	movs	r3, #1
+    2f46:	4083      	lsls	r3, r0
+    2f48:	430b      	orrs	r3, r1
+    2f4a:	602b      	str	r3, [r5, #0]
+    2f4c:	4664      	mov	r4, ip
+    2f4e:	e7b7      	b.n	2ec0 <_vfiprintf_r+0x8c>
+    2f50:	9b05      	ldr	r3, [sp, #20]
+    2f52:	1d18      	adds	r0, r3, #4
+    2f54:	681b      	ldr	r3, [r3, #0]
+    2f56:	9005      	str	r0, [sp, #20]
+    2f58:	2b00      	cmp	r3, #0
+    2f5a:	db3a      	blt.n	2fd2 <_vfiprintf_r+0x19e>
+    2f5c:	9309      	str	r3, [sp, #36]	; 0x24
+    2f5e:	4664      	mov	r4, ip
+    2f60:	7823      	ldrb	r3, [r4, #0]
+    2f62:	2b2e      	cmp	r3, #46	; 0x2e
+    2f64:	d10b      	bne.n	2f7e <_vfiprintf_r+0x14a>
+    2f66:	7863      	ldrb	r3, [r4, #1]
+    2f68:	1c62      	adds	r2, r4, #1
+    2f6a:	2b2a      	cmp	r3, #42	; 0x2a
+    2f6c:	d13f      	bne.n	2fee <_vfiprintf_r+0x1ba>
+    2f6e:	9b05      	ldr	r3, [sp, #20]
+    2f70:	3402      	adds	r4, #2
+    2f72:	1d1a      	adds	r2, r3, #4
+    2f74:	681b      	ldr	r3, [r3, #0]
+    2f76:	9205      	str	r2, [sp, #20]
+    2f78:	2b00      	cmp	r3, #0
+    2f7a:	db35      	blt.n	2fe8 <_vfiprintf_r+0x1b4>
+    2f7c:	9307      	str	r3, [sp, #28]
+    2f7e:	7821      	ldrb	r1, [r4, #0]
+    2f80:	2203      	movs	r2, #3
+    2f82:	4836      	ldr	r0, [pc, #216]	; (305c <_vfiprintf_r+0x228>)
+    2f84:	f000 fb82 	bl	368c <memchr>
+    2f88:	2800      	cmp	r0, #0
+    2f8a:	d007      	beq.n	2f9c <_vfiprintf_r+0x168>
+    2f8c:	4b33      	ldr	r3, [pc, #204]	; (305c <_vfiprintf_r+0x228>)
+    2f8e:	682a      	ldr	r2, [r5, #0]
+    2f90:	1ac0      	subs	r0, r0, r3
+    2f92:	2340      	movs	r3, #64	; 0x40
+    2f94:	4083      	lsls	r3, r0
+    2f96:	4313      	orrs	r3, r2
+    2f98:	602b      	str	r3, [r5, #0]
+    2f9a:	3401      	adds	r4, #1
+    2f9c:	7821      	ldrb	r1, [r4, #0]
+    2f9e:	1c63      	adds	r3, r4, #1
+    2fa0:	2206      	movs	r2, #6
+    2fa2:	482f      	ldr	r0, [pc, #188]	; (3060 <_vfiprintf_r+0x22c>)
+    2fa4:	9302      	str	r3, [sp, #8]
+    2fa6:	7629      	strb	r1, [r5, #24]
+    2fa8:	f000 fb70 	bl	368c <memchr>
+    2fac:	2800      	cmp	r0, #0
+    2fae:	d044      	beq.n	303a <_vfiprintf_r+0x206>
+    2fb0:	4b2c      	ldr	r3, [pc, #176]	; (3064 <_vfiprintf_r+0x230>)
+    2fb2:	2b00      	cmp	r3, #0
+    2fb4:	d12f      	bne.n	3016 <_vfiprintf_r+0x1e2>
+    2fb6:	6829      	ldr	r1, [r5, #0]
+    2fb8:	9b05      	ldr	r3, [sp, #20]
+    2fba:	2207      	movs	r2, #7
+    2fbc:	05c9      	lsls	r1, r1, #23
+    2fbe:	d528      	bpl.n	3012 <_vfiprintf_r+0x1de>
+    2fc0:	189b      	adds	r3, r3, r2
+    2fc2:	4393      	bics	r3, r2
+    2fc4:	3308      	adds	r3, #8
+    2fc6:	9305      	str	r3, [sp, #20]
+    2fc8:	696b      	ldr	r3, [r5, #20]
+    2fca:	9a03      	ldr	r2, [sp, #12]
+    2fcc:	189b      	adds	r3, r3, r2
+    2fce:	616b      	str	r3, [r5, #20]
+    2fd0:	e74f      	b.n	2e72 <_vfiprintf_r+0x3e>
+    2fd2:	425b      	negs	r3, r3
+    2fd4:	60eb      	str	r3, [r5, #12]
+    2fd6:	2302      	movs	r3, #2
+    2fd8:	430b      	orrs	r3, r1
+    2fda:	602b      	str	r3, [r5, #0]
+    2fdc:	e7bf      	b.n	2f5e <_vfiprintf_r+0x12a>
+    2fde:	434b      	muls	r3, r1
+    2fe0:	3401      	adds	r4, #1
+    2fe2:	189b      	adds	r3, r3, r2
+    2fe4:	2001      	movs	r0, #1
+    2fe6:	e789      	b.n	2efc <_vfiprintf_r+0xc8>
+    2fe8:	2301      	movs	r3, #1
+    2fea:	425b      	negs	r3, r3
+    2fec:	e7c6      	b.n	2f7c <_vfiprintf_r+0x148>
+    2fee:	2300      	movs	r3, #0
+    2ff0:	0014      	movs	r4, r2
+    2ff2:	200a      	movs	r0, #10
+    2ff4:	001a      	movs	r2, r3
+    2ff6:	606b      	str	r3, [r5, #4]
+    2ff8:	7821      	ldrb	r1, [r4, #0]
+    2ffa:	3930      	subs	r1, #48	; 0x30
+    2ffc:	2909      	cmp	r1, #9
+    2ffe:	d903      	bls.n	3008 <_vfiprintf_r+0x1d4>
+    3000:	2b00      	cmp	r3, #0
+    3002:	d0bc      	beq.n	2f7e <_vfiprintf_r+0x14a>
+    3004:	9207      	str	r2, [sp, #28]
+    3006:	e7ba      	b.n	2f7e <_vfiprintf_r+0x14a>
+    3008:	4342      	muls	r2, r0
+    300a:	3401      	adds	r4, #1
+    300c:	1852      	adds	r2, r2, r1
+    300e:	2301      	movs	r3, #1
+    3010:	e7f2      	b.n	2ff8 <_vfiprintf_r+0x1c4>
+    3012:	3307      	adds	r3, #7
+    3014:	e7d5      	b.n	2fc2 <_vfiprintf_r+0x18e>
+    3016:	ab05      	add	r3, sp, #20
+    3018:	9300      	str	r3, [sp, #0]
+    301a:	003a      	movs	r2, r7
+    301c:	4b12      	ldr	r3, [pc, #72]	; (3068 <_vfiprintf_r+0x234>)
+    301e:	0029      	movs	r1, r5
+    3020:	0030      	movs	r0, r6
+    3022:	e000      	b.n	3026 <_vfiprintf_r+0x1f2>
+    3024:	bf00      	nop
+    3026:	9003      	str	r0, [sp, #12]
+    3028:	9b03      	ldr	r3, [sp, #12]
+    302a:	3301      	adds	r3, #1
+    302c:	d1cc      	bne.n	2fc8 <_vfiprintf_r+0x194>
+    302e:	89bb      	ldrh	r3, [r7, #12]
+    3030:	065b      	lsls	r3, r3, #25
+    3032:	d500      	bpl.n	3036 <_vfiprintf_r+0x202>
+    3034:	e77b      	b.n	2f2e <_vfiprintf_r+0xfa>
+    3036:	980b      	ldr	r0, [sp, #44]	; 0x2c
+    3038:	e77b      	b.n	2f32 <_vfiprintf_r+0xfe>
+    303a:	ab05      	add	r3, sp, #20
+    303c:	9300      	str	r3, [sp, #0]
+    303e:	003a      	movs	r2, r7
+    3040:	4b09      	ldr	r3, [pc, #36]	; (3068 <_vfiprintf_r+0x234>)
+    3042:	0029      	movs	r1, r5
+    3044:	0030      	movs	r0, r6
+    3046:	f000 f87f 	bl	3148 <_printf_i>
+    304a:	e7ec      	b.n	3026 <_vfiprintf_r+0x1f2>
+    304c:	000038cc 	.word	0x000038cc
+    3050:	0000390c 	.word	0x0000390c
+    3054:	000038ec 	.word	0x000038ec
+    3058:	000038ac 	.word	0x000038ac
+    305c:	00003912 	.word	0x00003912
+    3060:	00003916 	.word	0x00003916
+    3064:	00000000 	.word	0x00000000
+    3068:	00002e0f 	.word	0x00002e0f
+
+0000306c <_printf_common>:
+    306c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    306e:	0015      	movs	r5, r2
+    3070:	9301      	str	r3, [sp, #4]
+    3072:	688a      	ldr	r2, [r1, #8]
+    3074:	690b      	ldr	r3, [r1, #16]
+    3076:	9000      	str	r0, [sp, #0]
+    3078:	000c      	movs	r4, r1
+    307a:	4293      	cmp	r3, r2
+    307c:	da00      	bge.n	3080 <_printf_common+0x14>
+    307e:	0013      	movs	r3, r2
+    3080:	0022      	movs	r2, r4
+    3082:	602b      	str	r3, [r5, #0]
+    3084:	3243      	adds	r2, #67	; 0x43
+    3086:	7812      	ldrb	r2, [r2, #0]
+    3088:	2a00      	cmp	r2, #0
+    308a:	d001      	beq.n	3090 <_printf_common+0x24>
+    308c:	3301      	adds	r3, #1
+    308e:	602b      	str	r3, [r5, #0]
+    3090:	6823      	ldr	r3, [r4, #0]
+    3092:	069b      	lsls	r3, r3, #26
+    3094:	d502      	bpl.n	309c <_printf_common+0x30>
+    3096:	682b      	ldr	r3, [r5, #0]
+    3098:	3302      	adds	r3, #2
+    309a:	602b      	str	r3, [r5, #0]
+    309c:	2706      	movs	r7, #6
+    309e:	6823      	ldr	r3, [r4, #0]
+    30a0:	401f      	ands	r7, r3
+    30a2:	d027      	beq.n	30f4 <_printf_common+0x88>
+    30a4:	0023      	movs	r3, r4
+    30a6:	3343      	adds	r3, #67	; 0x43
+    30a8:	781b      	ldrb	r3, [r3, #0]
+    30aa:	1e5a      	subs	r2, r3, #1
+    30ac:	4193      	sbcs	r3, r2
+    30ae:	6822      	ldr	r2, [r4, #0]
+    30b0:	0692      	lsls	r2, r2, #26
+    30b2:	d430      	bmi.n	3116 <_printf_common+0xaa>
+    30b4:	0022      	movs	r2, r4
+    30b6:	9901      	ldr	r1, [sp, #4]
+    30b8:	3243      	adds	r2, #67	; 0x43
+    30ba:	9800      	ldr	r0, [sp, #0]
+    30bc:	9e08      	ldr	r6, [sp, #32]
+    30be:	47b0      	blx	r6
+    30c0:	1c43      	adds	r3, r0, #1
+    30c2:	d025      	beq.n	3110 <_printf_common+0xa4>
+    30c4:	2306      	movs	r3, #6
+    30c6:	6820      	ldr	r0, [r4, #0]
+    30c8:	682a      	ldr	r2, [r5, #0]
+    30ca:	68e1      	ldr	r1, [r4, #12]
+    30cc:	4003      	ands	r3, r0
+    30ce:	2500      	movs	r5, #0
+    30d0:	2b04      	cmp	r3, #4
+    30d2:	d103      	bne.n	30dc <_printf_common+0x70>
+    30d4:	1a8d      	subs	r5, r1, r2
+    30d6:	43eb      	mvns	r3, r5
+    30d8:	17db      	asrs	r3, r3, #31
+    30da:	401d      	ands	r5, r3
+    30dc:	68a3      	ldr	r3, [r4, #8]
+    30de:	6922      	ldr	r2, [r4, #16]
+    30e0:	4293      	cmp	r3, r2
+    30e2:	dd01      	ble.n	30e8 <_printf_common+0x7c>
+    30e4:	1a9b      	subs	r3, r3, r2
+    30e6:	18ed      	adds	r5, r5, r3
+    30e8:	2700      	movs	r7, #0
+    30ea:	42bd      	cmp	r5, r7
+    30ec:	d120      	bne.n	3130 <_printf_common+0xc4>
+    30ee:	2000      	movs	r0, #0
+    30f0:	e010      	b.n	3114 <_printf_common+0xa8>
+    30f2:	3701      	adds	r7, #1
+    30f4:	68e3      	ldr	r3, [r4, #12]
+    30f6:	682a      	ldr	r2, [r5, #0]
+    30f8:	1a9b      	subs	r3, r3, r2
+    30fa:	429f      	cmp	r7, r3
+    30fc:	dad2      	bge.n	30a4 <_printf_common+0x38>
+    30fe:	0022      	movs	r2, r4
+    3100:	2301      	movs	r3, #1
+    3102:	3219      	adds	r2, #25
+    3104:	9901      	ldr	r1, [sp, #4]
+    3106:	9800      	ldr	r0, [sp, #0]
+    3108:	9e08      	ldr	r6, [sp, #32]
+    310a:	47b0      	blx	r6
+    310c:	1c43      	adds	r3, r0, #1
+    310e:	d1f0      	bne.n	30f2 <_printf_common+0x86>
+    3110:	2001      	movs	r0, #1
+    3112:	4240      	negs	r0, r0
+    3114:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    3116:	2030      	movs	r0, #48	; 0x30
+    3118:	18e1      	adds	r1, r4, r3
+    311a:	3143      	adds	r1, #67	; 0x43
+    311c:	7008      	strb	r0, [r1, #0]
+    311e:	0021      	movs	r1, r4
+    3120:	1c5a      	adds	r2, r3, #1
+    3122:	3145      	adds	r1, #69	; 0x45
+    3124:	7809      	ldrb	r1, [r1, #0]
+    3126:	18a2      	adds	r2, r4, r2
+    3128:	3243      	adds	r2, #67	; 0x43
+    312a:	3302      	adds	r3, #2
+    312c:	7011      	strb	r1, [r2, #0]
+    312e:	e7c1      	b.n	30b4 <_printf_common+0x48>
+    3130:	0022      	movs	r2, r4
+    3132:	2301      	movs	r3, #1
+    3134:	321a      	adds	r2, #26
+    3136:	9901      	ldr	r1, [sp, #4]
+    3138:	9800      	ldr	r0, [sp, #0]
+    313a:	9e08      	ldr	r6, [sp, #32]
+    313c:	47b0      	blx	r6
+    313e:	1c43      	adds	r3, r0, #1
+    3140:	d0e6      	beq.n	3110 <_printf_common+0xa4>
+    3142:	3701      	adds	r7, #1
+    3144:	e7d1      	b.n	30ea <_printf_common+0x7e>
+	...
+
+00003148 <_printf_i>:
+    3148:	b5f0      	push	{r4, r5, r6, r7, lr}
+    314a:	b08b      	sub	sp, #44	; 0x2c
+    314c:	9206      	str	r2, [sp, #24]
+    314e:	000a      	movs	r2, r1
+    3150:	3243      	adds	r2, #67	; 0x43
+    3152:	9307      	str	r3, [sp, #28]
+    3154:	9005      	str	r0, [sp, #20]
+    3156:	9204      	str	r2, [sp, #16]
+    3158:	7e0a      	ldrb	r2, [r1, #24]
+    315a:	000c      	movs	r4, r1
+    315c:	9b10      	ldr	r3, [sp, #64]	; 0x40
+    315e:	2a6e      	cmp	r2, #110	; 0x6e
+    3160:	d100      	bne.n	3164 <_printf_i+0x1c>
+    3162:	e08f      	b.n	3284 <_printf_i+0x13c>
+    3164:	d817      	bhi.n	3196 <_printf_i+0x4e>
+    3166:	2a63      	cmp	r2, #99	; 0x63
+    3168:	d02c      	beq.n	31c4 <_printf_i+0x7c>
+    316a:	d808      	bhi.n	317e <_printf_i+0x36>
+    316c:	2a00      	cmp	r2, #0
+    316e:	d100      	bne.n	3172 <_printf_i+0x2a>
+    3170:	e099      	b.n	32a6 <_printf_i+0x15e>
+    3172:	2a58      	cmp	r2, #88	; 0x58
+    3174:	d054      	beq.n	3220 <_printf_i+0xd8>
+    3176:	0026      	movs	r6, r4
+    3178:	3642      	adds	r6, #66	; 0x42
+    317a:	7032      	strb	r2, [r6, #0]
+    317c:	e029      	b.n	31d2 <_printf_i+0x8a>
+    317e:	2a64      	cmp	r2, #100	; 0x64
+    3180:	d001      	beq.n	3186 <_printf_i+0x3e>
+    3182:	2a69      	cmp	r2, #105	; 0x69
+    3184:	d1f7      	bne.n	3176 <_printf_i+0x2e>
+    3186:	6821      	ldr	r1, [r4, #0]
+    3188:	681a      	ldr	r2, [r3, #0]
+    318a:	0608      	lsls	r0, r1, #24
+    318c:	d523      	bpl.n	31d6 <_printf_i+0x8e>
+    318e:	1d11      	adds	r1, r2, #4
+    3190:	6019      	str	r1, [r3, #0]
+    3192:	6815      	ldr	r5, [r2, #0]
+    3194:	e025      	b.n	31e2 <_printf_i+0x9a>
+    3196:	2a73      	cmp	r2, #115	; 0x73
+    3198:	d100      	bne.n	319c <_printf_i+0x54>
+    319a:	e088      	b.n	32ae <_printf_i+0x166>
+    319c:	d808      	bhi.n	31b0 <_printf_i+0x68>
+    319e:	2a6f      	cmp	r2, #111	; 0x6f
+    31a0:	d029      	beq.n	31f6 <_printf_i+0xae>
+    31a2:	2a70      	cmp	r2, #112	; 0x70
+    31a4:	d1e7      	bne.n	3176 <_printf_i+0x2e>
+    31a6:	2220      	movs	r2, #32
+    31a8:	6809      	ldr	r1, [r1, #0]
+    31aa:	430a      	orrs	r2, r1
+    31ac:	6022      	str	r2, [r4, #0]
+    31ae:	e003      	b.n	31b8 <_printf_i+0x70>
+    31b0:	2a75      	cmp	r2, #117	; 0x75
+    31b2:	d020      	beq.n	31f6 <_printf_i+0xae>
+    31b4:	2a78      	cmp	r2, #120	; 0x78
+    31b6:	d1de      	bne.n	3176 <_printf_i+0x2e>
+    31b8:	0022      	movs	r2, r4
+    31ba:	2178      	movs	r1, #120	; 0x78
+    31bc:	3245      	adds	r2, #69	; 0x45
+    31be:	7011      	strb	r1, [r2, #0]
+    31c0:	4a6c      	ldr	r2, [pc, #432]	; (3374 <_printf_i+0x22c>)
+    31c2:	e030      	b.n	3226 <_printf_i+0xde>
+    31c4:	000e      	movs	r6, r1
+    31c6:	681a      	ldr	r2, [r3, #0]
+    31c8:	3642      	adds	r6, #66	; 0x42
+    31ca:	1d11      	adds	r1, r2, #4
+    31cc:	6019      	str	r1, [r3, #0]
+    31ce:	6813      	ldr	r3, [r2, #0]
+    31d0:	7033      	strb	r3, [r6, #0]
+    31d2:	2301      	movs	r3, #1
+    31d4:	e079      	b.n	32ca <_printf_i+0x182>
+    31d6:	0649      	lsls	r1, r1, #25
+    31d8:	d5d9      	bpl.n	318e <_printf_i+0x46>
+    31da:	1d11      	adds	r1, r2, #4
+    31dc:	6019      	str	r1, [r3, #0]
+    31de:	2300      	movs	r3, #0
+    31e0:	5ed5      	ldrsh	r5, [r2, r3]
+    31e2:	2d00      	cmp	r5, #0
+    31e4:	da03      	bge.n	31ee <_printf_i+0xa6>
+    31e6:	232d      	movs	r3, #45	; 0x2d
+    31e8:	9a04      	ldr	r2, [sp, #16]
+    31ea:	426d      	negs	r5, r5
+    31ec:	7013      	strb	r3, [r2, #0]
+    31ee:	4b62      	ldr	r3, [pc, #392]	; (3378 <_printf_i+0x230>)
+    31f0:	270a      	movs	r7, #10
+    31f2:	9303      	str	r3, [sp, #12]
+    31f4:	e02f      	b.n	3256 <_printf_i+0x10e>
+    31f6:	6820      	ldr	r0, [r4, #0]
+    31f8:	6819      	ldr	r1, [r3, #0]
+    31fa:	0605      	lsls	r5, r0, #24
+    31fc:	d503      	bpl.n	3206 <_printf_i+0xbe>
+    31fe:	1d08      	adds	r0, r1, #4
+    3200:	6018      	str	r0, [r3, #0]
+    3202:	680d      	ldr	r5, [r1, #0]
+    3204:	e005      	b.n	3212 <_printf_i+0xca>
+    3206:	0640      	lsls	r0, r0, #25
+    3208:	d5f9      	bpl.n	31fe <_printf_i+0xb6>
+    320a:	680d      	ldr	r5, [r1, #0]
+    320c:	1d08      	adds	r0, r1, #4
+    320e:	6018      	str	r0, [r3, #0]
+    3210:	b2ad      	uxth	r5, r5
+    3212:	4b59      	ldr	r3, [pc, #356]	; (3378 <_printf_i+0x230>)
+    3214:	2708      	movs	r7, #8
+    3216:	9303      	str	r3, [sp, #12]
+    3218:	2a6f      	cmp	r2, #111	; 0x6f
+    321a:	d018      	beq.n	324e <_printf_i+0x106>
+    321c:	270a      	movs	r7, #10
+    321e:	e016      	b.n	324e <_printf_i+0x106>
+    3220:	3145      	adds	r1, #69	; 0x45
+    3222:	700a      	strb	r2, [r1, #0]
+    3224:	4a54      	ldr	r2, [pc, #336]	; (3378 <_printf_i+0x230>)
+    3226:	9203      	str	r2, [sp, #12]
+    3228:	681a      	ldr	r2, [r3, #0]
+    322a:	6821      	ldr	r1, [r4, #0]
+    322c:	1d10      	adds	r0, r2, #4
+    322e:	6018      	str	r0, [r3, #0]
+    3230:	6815      	ldr	r5, [r2, #0]
+    3232:	0608      	lsls	r0, r1, #24
+    3234:	d522      	bpl.n	327c <_printf_i+0x134>
+    3236:	07cb      	lsls	r3, r1, #31
+    3238:	d502      	bpl.n	3240 <_printf_i+0xf8>
+    323a:	2320      	movs	r3, #32
+    323c:	4319      	orrs	r1, r3
+    323e:	6021      	str	r1, [r4, #0]
+    3240:	2710      	movs	r7, #16
+    3242:	2d00      	cmp	r5, #0
+    3244:	d103      	bne.n	324e <_printf_i+0x106>
+    3246:	2320      	movs	r3, #32
+    3248:	6822      	ldr	r2, [r4, #0]
+    324a:	439a      	bics	r2, r3
+    324c:	6022      	str	r2, [r4, #0]
+    324e:	0023      	movs	r3, r4
+    3250:	2200      	movs	r2, #0
+    3252:	3343      	adds	r3, #67	; 0x43
+    3254:	701a      	strb	r2, [r3, #0]
+    3256:	6863      	ldr	r3, [r4, #4]
+    3258:	60a3      	str	r3, [r4, #8]
+    325a:	2b00      	cmp	r3, #0
+    325c:	db5c      	blt.n	3318 <_printf_i+0x1d0>
+    325e:	2204      	movs	r2, #4
+    3260:	6821      	ldr	r1, [r4, #0]
+    3262:	4391      	bics	r1, r2
+    3264:	6021      	str	r1, [r4, #0]
+    3266:	2d00      	cmp	r5, #0
+    3268:	d158      	bne.n	331c <_printf_i+0x1d4>
+    326a:	9e04      	ldr	r6, [sp, #16]
+    326c:	2b00      	cmp	r3, #0
+    326e:	d064      	beq.n	333a <_printf_i+0x1f2>
+    3270:	0026      	movs	r6, r4
+    3272:	9b03      	ldr	r3, [sp, #12]
+    3274:	3642      	adds	r6, #66	; 0x42
+    3276:	781b      	ldrb	r3, [r3, #0]
+    3278:	7033      	strb	r3, [r6, #0]
+    327a:	e05e      	b.n	333a <_printf_i+0x1f2>
+    327c:	0648      	lsls	r0, r1, #25
+    327e:	d5da      	bpl.n	3236 <_printf_i+0xee>
+    3280:	b2ad      	uxth	r5, r5
+    3282:	e7d8      	b.n	3236 <_printf_i+0xee>
+    3284:	6809      	ldr	r1, [r1, #0]
+    3286:	681a      	ldr	r2, [r3, #0]
+    3288:	0608      	lsls	r0, r1, #24
+    328a:	d505      	bpl.n	3298 <_printf_i+0x150>
+    328c:	1d11      	adds	r1, r2, #4
+    328e:	6019      	str	r1, [r3, #0]
+    3290:	6813      	ldr	r3, [r2, #0]
+    3292:	6962      	ldr	r2, [r4, #20]
+    3294:	601a      	str	r2, [r3, #0]
+    3296:	e006      	b.n	32a6 <_printf_i+0x15e>
+    3298:	0649      	lsls	r1, r1, #25
+    329a:	d5f7      	bpl.n	328c <_printf_i+0x144>
+    329c:	1d11      	adds	r1, r2, #4
+    329e:	6019      	str	r1, [r3, #0]
+    32a0:	6813      	ldr	r3, [r2, #0]
+    32a2:	8aa2      	ldrh	r2, [r4, #20]
+    32a4:	801a      	strh	r2, [r3, #0]
+    32a6:	2300      	movs	r3, #0
+    32a8:	9e04      	ldr	r6, [sp, #16]
+    32aa:	6123      	str	r3, [r4, #16]
+    32ac:	e054      	b.n	3358 <_printf_i+0x210>
+    32ae:	681a      	ldr	r2, [r3, #0]
+    32b0:	1d11      	adds	r1, r2, #4
+    32b2:	6019      	str	r1, [r3, #0]
+    32b4:	6816      	ldr	r6, [r2, #0]
+    32b6:	2100      	movs	r1, #0
+    32b8:	6862      	ldr	r2, [r4, #4]
+    32ba:	0030      	movs	r0, r6
+    32bc:	f000 f9e6 	bl	368c <memchr>
+    32c0:	2800      	cmp	r0, #0
+    32c2:	d001      	beq.n	32c8 <_printf_i+0x180>
+    32c4:	1b80      	subs	r0, r0, r6
+    32c6:	6060      	str	r0, [r4, #4]
+    32c8:	6863      	ldr	r3, [r4, #4]
+    32ca:	6123      	str	r3, [r4, #16]
+    32cc:	2300      	movs	r3, #0
+    32ce:	9a04      	ldr	r2, [sp, #16]
+    32d0:	7013      	strb	r3, [r2, #0]
+    32d2:	e041      	b.n	3358 <_printf_i+0x210>
+    32d4:	6923      	ldr	r3, [r4, #16]
+    32d6:	0032      	movs	r2, r6
+    32d8:	9906      	ldr	r1, [sp, #24]
+    32da:	9805      	ldr	r0, [sp, #20]
+    32dc:	9d07      	ldr	r5, [sp, #28]
+    32de:	47a8      	blx	r5
+    32e0:	1c43      	adds	r3, r0, #1
+    32e2:	d043      	beq.n	336c <_printf_i+0x224>
+    32e4:	6823      	ldr	r3, [r4, #0]
+    32e6:	2500      	movs	r5, #0
+    32e8:	079b      	lsls	r3, r3, #30
+    32ea:	d40f      	bmi.n	330c <_printf_i+0x1c4>
+    32ec:	9b09      	ldr	r3, [sp, #36]	; 0x24
+    32ee:	68e0      	ldr	r0, [r4, #12]
+    32f0:	4298      	cmp	r0, r3
+    32f2:	da3d      	bge.n	3370 <_printf_i+0x228>
+    32f4:	0018      	movs	r0, r3
+    32f6:	e03b      	b.n	3370 <_printf_i+0x228>
+    32f8:	0022      	movs	r2, r4
+    32fa:	2301      	movs	r3, #1
+    32fc:	3219      	adds	r2, #25
+    32fe:	9906      	ldr	r1, [sp, #24]
+    3300:	9805      	ldr	r0, [sp, #20]
+    3302:	9e07      	ldr	r6, [sp, #28]
+    3304:	47b0      	blx	r6
+    3306:	1c43      	adds	r3, r0, #1
+    3308:	d030      	beq.n	336c <_printf_i+0x224>
+    330a:	3501      	adds	r5, #1
+    330c:	68e3      	ldr	r3, [r4, #12]
+    330e:	9a09      	ldr	r2, [sp, #36]	; 0x24
+    3310:	1a9b      	subs	r3, r3, r2
+    3312:	429d      	cmp	r5, r3
+    3314:	dbf0      	blt.n	32f8 <_printf_i+0x1b0>
+    3316:	e7e9      	b.n	32ec <_printf_i+0x1a4>
+    3318:	2d00      	cmp	r5, #0
+    331a:	d0a9      	beq.n	3270 <_printf_i+0x128>
+    331c:	9e04      	ldr	r6, [sp, #16]
+    331e:	0028      	movs	r0, r5
+    3320:	0039      	movs	r1, r7
+    3322:	f7fe fded 	bl	1f00 <__aeabi_uidivmod>
+    3326:	9b03      	ldr	r3, [sp, #12]
+    3328:	3e01      	subs	r6, #1
+    332a:	5c5b      	ldrb	r3, [r3, r1]
+    332c:	0028      	movs	r0, r5
+    332e:	7033      	strb	r3, [r6, #0]
+    3330:	0039      	movs	r1, r7
+    3332:	f7fe fd5f 	bl	1df4 <__udivsi3>
+    3336:	1e05      	subs	r5, r0, #0
+    3338:	d1f1      	bne.n	331e <_printf_i+0x1d6>
+    333a:	2f08      	cmp	r7, #8
+    333c:	d109      	bne.n	3352 <_printf_i+0x20a>
+    333e:	6823      	ldr	r3, [r4, #0]
+    3340:	07db      	lsls	r3, r3, #31
+    3342:	d506      	bpl.n	3352 <_printf_i+0x20a>
+    3344:	6863      	ldr	r3, [r4, #4]
+    3346:	6922      	ldr	r2, [r4, #16]
+    3348:	4293      	cmp	r3, r2
+    334a:	dc02      	bgt.n	3352 <_printf_i+0x20a>
+    334c:	2330      	movs	r3, #48	; 0x30
+    334e:	3e01      	subs	r6, #1
+    3350:	7033      	strb	r3, [r6, #0]
+    3352:	9b04      	ldr	r3, [sp, #16]
+    3354:	1b9b      	subs	r3, r3, r6
+    3356:	6123      	str	r3, [r4, #16]
+    3358:	9b07      	ldr	r3, [sp, #28]
+    335a:	aa09      	add	r2, sp, #36	; 0x24
+    335c:	9300      	str	r3, [sp, #0]
+    335e:	0021      	movs	r1, r4
+    3360:	9b06      	ldr	r3, [sp, #24]
+    3362:	9805      	ldr	r0, [sp, #20]
+    3364:	f7ff fe82 	bl	306c <_printf_common>
+    3368:	1c43      	adds	r3, r0, #1
+    336a:	d1b3      	bne.n	32d4 <_printf_i+0x18c>
+    336c:	2001      	movs	r0, #1
+    336e:	4240      	negs	r0, r0
+    3370:	b00b      	add	sp, #44	; 0x2c
+    3372:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    3374:	0000392e 	.word	0x0000392e
+    3378:	0000391d 	.word	0x0000391d
+
+0000337c <_sbrk_r>:
+    337c:	2300      	movs	r3, #0
+    337e:	b570      	push	{r4, r5, r6, lr}
+    3380:	4c06      	ldr	r4, [pc, #24]	; (339c <_sbrk_r+0x20>)
+    3382:	0005      	movs	r5, r0
+    3384:	0008      	movs	r0, r1
+    3386:	6023      	str	r3, [r4, #0]
+    3388:	f7fe fcd4 	bl	1d34 <_sbrk>
+    338c:	1c43      	adds	r3, r0, #1
+    338e:	d103      	bne.n	3398 <_sbrk_r+0x1c>
+    3390:	6823      	ldr	r3, [r4, #0]
+    3392:	2b00      	cmp	r3, #0
+    3394:	d000      	beq.n	3398 <_sbrk_r+0x1c>
+    3396:	602b      	str	r3, [r5, #0]
+    3398:	bd70      	pop	{r4, r5, r6, pc}
+    339a:	46c0      	nop			; (mov r8, r8)
+    339c:	2000029c 	.word	0x2000029c
+
+000033a0 <__sread>:
+    33a0:	b570      	push	{r4, r5, r6, lr}
+    33a2:	000c      	movs	r4, r1
+    33a4:	250e      	movs	r5, #14
+    33a6:	5f49      	ldrsh	r1, [r1, r5]
+    33a8:	f000 f97e 	bl	36a8 <_read_r>
+    33ac:	2800      	cmp	r0, #0
+    33ae:	db03      	blt.n	33b8 <__sread+0x18>
+    33b0:	6d63      	ldr	r3, [r4, #84]	; 0x54
+    33b2:	181b      	adds	r3, r3, r0
+    33b4:	6563      	str	r3, [r4, #84]	; 0x54
+    33b6:	bd70      	pop	{r4, r5, r6, pc}
+    33b8:	89a3      	ldrh	r3, [r4, #12]
+    33ba:	4a02      	ldr	r2, [pc, #8]	; (33c4 <__sread+0x24>)
+    33bc:	4013      	ands	r3, r2
+    33be:	81a3      	strh	r3, [r4, #12]
+    33c0:	e7f9      	b.n	33b6 <__sread+0x16>
+    33c2:	46c0      	nop			; (mov r8, r8)
+    33c4:	ffffefff 	.word	0xffffefff
+
+000033c8 <__swrite>:
+    33c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    33ca:	001f      	movs	r7, r3
+    33cc:	898b      	ldrh	r3, [r1, #12]
+    33ce:	0005      	movs	r5, r0
+    33d0:	000c      	movs	r4, r1
+    33d2:	0016      	movs	r6, r2
+    33d4:	05db      	lsls	r3, r3, #23
+    33d6:	d505      	bpl.n	33e4 <__swrite+0x1c>
+    33d8:	230e      	movs	r3, #14
+    33da:	5ec9      	ldrsh	r1, [r1, r3]
+    33dc:	2200      	movs	r2, #0
+    33de:	2302      	movs	r3, #2
+    33e0:	f000 f940 	bl	3664 <_lseek_r>
+    33e4:	89a3      	ldrh	r3, [r4, #12]
+    33e6:	4a05      	ldr	r2, [pc, #20]	; (33fc <__swrite+0x34>)
+    33e8:	0028      	movs	r0, r5
+    33ea:	4013      	ands	r3, r2
+    33ec:	81a3      	strh	r3, [r4, #12]
+    33ee:	0032      	movs	r2, r6
+    33f0:	230e      	movs	r3, #14
+    33f2:	5ee1      	ldrsh	r1, [r4, r3]
+    33f4:	003b      	movs	r3, r7
+    33f6:	f000 f875 	bl	34e4 <_write_r>
+    33fa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    33fc:	ffffefff 	.word	0xffffefff
+
+00003400 <__sseek>:
+    3400:	b570      	push	{r4, r5, r6, lr}
+    3402:	000c      	movs	r4, r1
+    3404:	250e      	movs	r5, #14
+    3406:	5f49      	ldrsh	r1, [r1, r5]
+    3408:	f000 f92c 	bl	3664 <_lseek_r>
+    340c:	89a3      	ldrh	r3, [r4, #12]
+    340e:	1c42      	adds	r2, r0, #1
+    3410:	d103      	bne.n	341a <__sseek+0x1a>
+    3412:	4a05      	ldr	r2, [pc, #20]	; (3428 <__sseek+0x28>)
+    3414:	4013      	ands	r3, r2
+    3416:	81a3      	strh	r3, [r4, #12]
+    3418:	bd70      	pop	{r4, r5, r6, pc}
+    341a:	2280      	movs	r2, #128	; 0x80
+    341c:	0152      	lsls	r2, r2, #5
+    341e:	4313      	orrs	r3, r2
+    3420:	81a3      	strh	r3, [r4, #12]
+    3422:	6560      	str	r0, [r4, #84]	; 0x54
+    3424:	e7f8      	b.n	3418 <__sseek+0x18>
+    3426:	46c0      	nop			; (mov r8, r8)
+    3428:	ffffefff 	.word	0xffffefff
+
+0000342c <__sclose>:
+    342c:	b510      	push	{r4, lr}
+    342e:	230e      	movs	r3, #14
+    3430:	5ec9      	ldrsh	r1, [r1, r3]
+    3432:	f000 f8e1 	bl	35f8 <_close_r>
+    3436:	bd10      	pop	{r4, pc}
+
+00003438 <__swbuf_r>:
+    3438:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    343a:	0005      	movs	r5, r0
+    343c:	000e      	movs	r6, r1
+    343e:	0014      	movs	r4, r2
+    3440:	2800      	cmp	r0, #0
+    3442:	d004      	beq.n	344e <__swbuf_r+0x16>
+    3444:	6983      	ldr	r3, [r0, #24]
+    3446:	2b00      	cmp	r3, #0
+    3448:	d101      	bne.n	344e <__swbuf_r+0x16>
+    344a:	f7ff fb17 	bl	2a7c <__sinit>
+    344e:	4b22      	ldr	r3, [pc, #136]	; (34d8 <__swbuf_r+0xa0>)
+    3450:	429c      	cmp	r4, r3
+    3452:	d12d      	bne.n	34b0 <__swbuf_r+0x78>
+    3454:	686c      	ldr	r4, [r5, #4]
+    3456:	69a3      	ldr	r3, [r4, #24]
+    3458:	60a3      	str	r3, [r4, #8]
+    345a:	89a3      	ldrh	r3, [r4, #12]
+    345c:	071b      	lsls	r3, r3, #28
+    345e:	d531      	bpl.n	34c4 <__swbuf_r+0x8c>
+    3460:	6923      	ldr	r3, [r4, #16]
+    3462:	2b00      	cmp	r3, #0
+    3464:	d02e      	beq.n	34c4 <__swbuf_r+0x8c>
+    3466:	6823      	ldr	r3, [r4, #0]
+    3468:	6922      	ldr	r2, [r4, #16]
+    346a:	b2f7      	uxtb	r7, r6
+    346c:	1a98      	subs	r0, r3, r2
+    346e:	6963      	ldr	r3, [r4, #20]
+    3470:	b2f6      	uxtb	r6, r6
+    3472:	4298      	cmp	r0, r3
+    3474:	db05      	blt.n	3482 <__swbuf_r+0x4a>
+    3476:	0021      	movs	r1, r4
+    3478:	0028      	movs	r0, r5
+    347a:	f7ff fa91 	bl	29a0 <_fflush_r>
+    347e:	2800      	cmp	r0, #0
+    3480:	d126      	bne.n	34d0 <__swbuf_r+0x98>
+    3482:	68a3      	ldr	r3, [r4, #8]
+    3484:	3001      	adds	r0, #1
+    3486:	3b01      	subs	r3, #1
+    3488:	60a3      	str	r3, [r4, #8]
+    348a:	6823      	ldr	r3, [r4, #0]
+    348c:	1c5a      	adds	r2, r3, #1
+    348e:	6022      	str	r2, [r4, #0]
+    3490:	701f      	strb	r7, [r3, #0]
+    3492:	6963      	ldr	r3, [r4, #20]
+    3494:	4298      	cmp	r0, r3
+    3496:	d004      	beq.n	34a2 <__swbuf_r+0x6a>
+    3498:	89a3      	ldrh	r3, [r4, #12]
+    349a:	07db      	lsls	r3, r3, #31
+    349c:	d51a      	bpl.n	34d4 <__swbuf_r+0x9c>
+    349e:	2e0a      	cmp	r6, #10
+    34a0:	d118      	bne.n	34d4 <__swbuf_r+0x9c>
+    34a2:	0021      	movs	r1, r4
+    34a4:	0028      	movs	r0, r5
+    34a6:	f7ff fa7b 	bl	29a0 <_fflush_r>
+    34aa:	2800      	cmp	r0, #0
+    34ac:	d012      	beq.n	34d4 <__swbuf_r+0x9c>
+    34ae:	e00f      	b.n	34d0 <__swbuf_r+0x98>
+    34b0:	4b0a      	ldr	r3, [pc, #40]	; (34dc <__swbuf_r+0xa4>)
+    34b2:	429c      	cmp	r4, r3
+    34b4:	d101      	bne.n	34ba <__swbuf_r+0x82>
+    34b6:	68ac      	ldr	r4, [r5, #8]
+    34b8:	e7cd      	b.n	3456 <__swbuf_r+0x1e>
+    34ba:	4b09      	ldr	r3, [pc, #36]	; (34e0 <__swbuf_r+0xa8>)
+    34bc:	429c      	cmp	r4, r3
+    34be:	d1ca      	bne.n	3456 <__swbuf_r+0x1e>
+    34c0:	68ec      	ldr	r4, [r5, #12]
+    34c2:	e7c8      	b.n	3456 <__swbuf_r+0x1e>
+    34c4:	0021      	movs	r1, r4
+    34c6:	0028      	movs	r0, r5
+    34c8:	f000 f820 	bl	350c <__swsetup_r>
+    34cc:	2800      	cmp	r0, #0
+    34ce:	d0ca      	beq.n	3466 <__swbuf_r+0x2e>
+    34d0:	2601      	movs	r6, #1
+    34d2:	4276      	negs	r6, r6
+    34d4:	0030      	movs	r0, r6
+    34d6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    34d8:	000038cc 	.word	0x000038cc
+    34dc:	000038ec 	.word	0x000038ec
+    34e0:	000038ac 	.word	0x000038ac
+
+000034e4 <_write_r>:
+    34e4:	b570      	push	{r4, r5, r6, lr}
+    34e6:	0005      	movs	r5, r0
+    34e8:	0008      	movs	r0, r1
+    34ea:	0011      	movs	r1, r2
+    34ec:	2200      	movs	r2, #0
+    34ee:	4c06      	ldr	r4, [pc, #24]	; (3508 <_write_r+0x24>)
+    34f0:	6022      	str	r2, [r4, #0]
+    34f2:	001a      	movs	r2, r3
+    34f4:	f7fd fbb8 	bl	c68 <_write>
+    34f8:	1c43      	adds	r3, r0, #1
+    34fa:	d103      	bne.n	3504 <_write_r+0x20>
+    34fc:	6823      	ldr	r3, [r4, #0]
+    34fe:	2b00      	cmp	r3, #0
+    3500:	d000      	beq.n	3504 <_write_r+0x20>
+    3502:	602b      	str	r3, [r5, #0]
+    3504:	bd70      	pop	{r4, r5, r6, pc}
+    3506:	46c0      	nop			; (mov r8, r8)
+    3508:	2000029c 	.word	0x2000029c
+
+0000350c <__swsetup_r>:
+    350c:	4b36      	ldr	r3, [pc, #216]	; (35e8 <__swsetup_r+0xdc>)
+    350e:	b570      	push	{r4, r5, r6, lr}
+    3510:	681d      	ldr	r5, [r3, #0]
+    3512:	0006      	movs	r6, r0
+    3514:	000c      	movs	r4, r1
+    3516:	2d00      	cmp	r5, #0
+    3518:	d005      	beq.n	3526 <__swsetup_r+0x1a>
+    351a:	69ab      	ldr	r3, [r5, #24]
+    351c:	2b00      	cmp	r3, #0
+    351e:	d102      	bne.n	3526 <__swsetup_r+0x1a>
+    3520:	0028      	movs	r0, r5
+    3522:	f7ff faab 	bl	2a7c <__sinit>
+    3526:	4b31      	ldr	r3, [pc, #196]	; (35ec <__swsetup_r+0xe0>)
+    3528:	429c      	cmp	r4, r3
+    352a:	d10f      	bne.n	354c <__swsetup_r+0x40>
+    352c:	686c      	ldr	r4, [r5, #4]
+    352e:	230c      	movs	r3, #12
+    3530:	5ee2      	ldrsh	r2, [r4, r3]
+    3532:	b293      	uxth	r3, r2
+    3534:	0719      	lsls	r1, r3, #28
+    3536:	d42d      	bmi.n	3594 <__swsetup_r+0x88>
+    3538:	06d9      	lsls	r1, r3, #27
+    353a:	d411      	bmi.n	3560 <__swsetup_r+0x54>
+    353c:	2309      	movs	r3, #9
+    353e:	2001      	movs	r0, #1
+    3540:	6033      	str	r3, [r6, #0]
+    3542:	3337      	adds	r3, #55	; 0x37
+    3544:	4313      	orrs	r3, r2
+    3546:	81a3      	strh	r3, [r4, #12]
+    3548:	4240      	negs	r0, r0
+    354a:	bd70      	pop	{r4, r5, r6, pc}
+    354c:	4b28      	ldr	r3, [pc, #160]	; (35f0 <__swsetup_r+0xe4>)
+    354e:	429c      	cmp	r4, r3
+    3550:	d101      	bne.n	3556 <__swsetup_r+0x4a>
+    3552:	68ac      	ldr	r4, [r5, #8]
+    3554:	e7eb      	b.n	352e <__swsetup_r+0x22>
+    3556:	4b27      	ldr	r3, [pc, #156]	; (35f4 <__swsetup_r+0xe8>)
+    3558:	429c      	cmp	r4, r3
+    355a:	d1e8      	bne.n	352e <__swsetup_r+0x22>
+    355c:	68ec      	ldr	r4, [r5, #12]
+    355e:	e7e6      	b.n	352e <__swsetup_r+0x22>
+    3560:	075b      	lsls	r3, r3, #29
+    3562:	d513      	bpl.n	358c <__swsetup_r+0x80>
+    3564:	6b61      	ldr	r1, [r4, #52]	; 0x34
+    3566:	2900      	cmp	r1, #0
+    3568:	d008      	beq.n	357c <__swsetup_r+0x70>
+    356a:	0023      	movs	r3, r4
+    356c:	3344      	adds	r3, #68	; 0x44
+    356e:	4299      	cmp	r1, r3
+    3570:	d002      	beq.n	3578 <__swsetup_r+0x6c>
+    3572:	0030      	movs	r0, r6
+    3574:	f7ff fb8e 	bl	2c94 <_free_r>
+    3578:	2300      	movs	r3, #0
+    357a:	6363      	str	r3, [r4, #52]	; 0x34
+    357c:	2224      	movs	r2, #36	; 0x24
+    357e:	89a3      	ldrh	r3, [r4, #12]
+    3580:	4393      	bics	r3, r2
+    3582:	81a3      	strh	r3, [r4, #12]
+    3584:	2300      	movs	r3, #0
+    3586:	6063      	str	r3, [r4, #4]
+    3588:	6923      	ldr	r3, [r4, #16]
+    358a:	6023      	str	r3, [r4, #0]
+    358c:	2308      	movs	r3, #8
+    358e:	89a2      	ldrh	r2, [r4, #12]
+    3590:	4313      	orrs	r3, r2
+    3592:	81a3      	strh	r3, [r4, #12]
+    3594:	6923      	ldr	r3, [r4, #16]
+    3596:	2b00      	cmp	r3, #0
+    3598:	d10b      	bne.n	35b2 <__swsetup_r+0xa6>
+    359a:	21a0      	movs	r1, #160	; 0xa0
+    359c:	2280      	movs	r2, #128	; 0x80
+    359e:	89a3      	ldrh	r3, [r4, #12]
+    35a0:	0089      	lsls	r1, r1, #2
+    35a2:	0092      	lsls	r2, r2, #2
+    35a4:	400b      	ands	r3, r1
+    35a6:	4293      	cmp	r3, r2
+    35a8:	d003      	beq.n	35b2 <__swsetup_r+0xa6>
+    35aa:	0021      	movs	r1, r4
+    35ac:	0030      	movs	r0, r6
+    35ae:	f7ff fb23 	bl	2bf8 <__smakebuf_r>
+    35b2:	2301      	movs	r3, #1
+    35b4:	89a2      	ldrh	r2, [r4, #12]
+    35b6:	4013      	ands	r3, r2
+    35b8:	d011      	beq.n	35de <__swsetup_r+0xd2>
+    35ba:	2300      	movs	r3, #0
+    35bc:	60a3      	str	r3, [r4, #8]
+    35be:	6963      	ldr	r3, [r4, #20]
+    35c0:	425b      	negs	r3, r3
+    35c2:	61a3      	str	r3, [r4, #24]
+    35c4:	2000      	movs	r0, #0
+    35c6:	6923      	ldr	r3, [r4, #16]
+    35c8:	4283      	cmp	r3, r0
+    35ca:	d1be      	bne.n	354a <__swsetup_r+0x3e>
+    35cc:	230c      	movs	r3, #12
+    35ce:	5ee2      	ldrsh	r2, [r4, r3]
+    35d0:	0613      	lsls	r3, r2, #24
+    35d2:	d5ba      	bpl.n	354a <__swsetup_r+0x3e>
+    35d4:	2340      	movs	r3, #64	; 0x40
+    35d6:	4313      	orrs	r3, r2
+    35d8:	81a3      	strh	r3, [r4, #12]
+    35da:	3801      	subs	r0, #1
+    35dc:	e7b5      	b.n	354a <__swsetup_r+0x3e>
+    35de:	0792      	lsls	r2, r2, #30
+    35e0:	d400      	bmi.n	35e4 <__swsetup_r+0xd8>
+    35e2:	6963      	ldr	r3, [r4, #20]
+    35e4:	60a3      	str	r3, [r4, #8]
+    35e6:	e7ed      	b.n	35c4 <__swsetup_r+0xb8>
+    35e8:	20000018 	.word	0x20000018
+    35ec:	000038cc 	.word	0x000038cc
+    35f0:	000038ec 	.word	0x000038ec
+    35f4:	000038ac 	.word	0x000038ac
+
+000035f8 <_close_r>:
+    35f8:	2300      	movs	r3, #0
+    35fa:	b570      	push	{r4, r5, r6, lr}
+    35fc:	4c06      	ldr	r4, [pc, #24]	; (3618 <_close_r+0x20>)
+    35fe:	0005      	movs	r5, r0
+    3600:	0008      	movs	r0, r1
+    3602:	6023      	str	r3, [r4, #0]
+    3604:	f7fe fba8 	bl	1d58 <_close>
+    3608:	1c43      	adds	r3, r0, #1
+    360a:	d103      	bne.n	3614 <_close_r+0x1c>
+    360c:	6823      	ldr	r3, [r4, #0]
+    360e:	2b00      	cmp	r3, #0
+    3610:	d000      	beq.n	3614 <_close_r+0x1c>
+    3612:	602b      	str	r3, [r5, #0]
+    3614:	bd70      	pop	{r4, r5, r6, pc}
+    3616:	46c0      	nop			; (mov r8, r8)
+    3618:	2000029c 	.word	0x2000029c
+
+0000361c <_fstat_r>:
+    361c:	2300      	movs	r3, #0
+    361e:	b570      	push	{r4, r5, r6, lr}
+    3620:	4c06      	ldr	r4, [pc, #24]	; (363c <_fstat_r+0x20>)
+    3622:	0005      	movs	r5, r0
+    3624:	0008      	movs	r0, r1
+    3626:	0011      	movs	r1, r2
+    3628:	6023      	str	r3, [r4, #0]
+    362a:	f7fe fb98 	bl	1d5e <_fstat>
+    362e:	1c43      	adds	r3, r0, #1
+    3630:	d103      	bne.n	363a <_fstat_r+0x1e>
+    3632:	6823      	ldr	r3, [r4, #0]
+    3634:	2b00      	cmp	r3, #0
+    3636:	d000      	beq.n	363a <_fstat_r+0x1e>
+    3638:	602b      	str	r3, [r5, #0]
+    363a:	bd70      	pop	{r4, r5, r6, pc}
+    363c:	2000029c 	.word	0x2000029c
+
+00003640 <_isatty_r>:
+    3640:	2300      	movs	r3, #0
+    3642:	b570      	push	{r4, r5, r6, lr}
+    3644:	4c06      	ldr	r4, [pc, #24]	; (3660 <_isatty_r+0x20>)
+    3646:	0005      	movs	r5, r0
+    3648:	0008      	movs	r0, r1
+    364a:	6023      	str	r3, [r4, #0]
+    364c:	f7fe fb8c 	bl	1d68 <_isatty>
+    3650:	1c43      	adds	r3, r0, #1
+    3652:	d103      	bne.n	365c <_isatty_r+0x1c>
+    3654:	6823      	ldr	r3, [r4, #0]
+    3656:	2b00      	cmp	r3, #0
+    3658:	d000      	beq.n	365c <_isatty_r+0x1c>
+    365a:	602b      	str	r3, [r5, #0]
+    365c:	bd70      	pop	{r4, r5, r6, pc}
+    365e:	46c0      	nop			; (mov r8, r8)
+    3660:	2000029c 	.word	0x2000029c
+
+00003664 <_lseek_r>:
+    3664:	b570      	push	{r4, r5, r6, lr}
+    3666:	0005      	movs	r5, r0
+    3668:	0008      	movs	r0, r1
+    366a:	0011      	movs	r1, r2
+    366c:	2200      	movs	r2, #0
+    366e:	4c06      	ldr	r4, [pc, #24]	; (3688 <_lseek_r+0x24>)
+    3670:	6022      	str	r2, [r4, #0]
+    3672:	001a      	movs	r2, r3
+    3674:	f7fe fb7a 	bl	1d6c <_lseek>
+    3678:	1c43      	adds	r3, r0, #1
+    367a:	d103      	bne.n	3684 <_lseek_r+0x20>
+    367c:	6823      	ldr	r3, [r4, #0]
+    367e:	2b00      	cmp	r3, #0
+    3680:	d000      	beq.n	3684 <_lseek_r+0x20>
+    3682:	602b      	str	r3, [r5, #0]
+    3684:	bd70      	pop	{r4, r5, r6, pc}
+    3686:	46c0      	nop			; (mov r8, r8)
+    3688:	2000029c 	.word	0x2000029c
+
+0000368c <memchr>:
+    368c:	b2c9      	uxtb	r1, r1
+    368e:	1882      	adds	r2, r0, r2
+    3690:	4290      	cmp	r0, r2
+    3692:	d101      	bne.n	3698 <memchr+0xc>
+    3694:	2000      	movs	r0, #0
+    3696:	4770      	bx	lr
+    3698:	7803      	ldrb	r3, [r0, #0]
+    369a:	428b      	cmp	r3, r1
+    369c:	d0fb      	beq.n	3696 <memchr+0xa>
+    369e:	3001      	adds	r0, #1
+    36a0:	e7f6      	b.n	3690 <memchr+0x4>
+
+000036a2 <__malloc_lock>:
+    36a2:	4770      	bx	lr
+
+000036a4 <__malloc_unlock>:
+    36a4:	4770      	bx	lr
+	...
+
+000036a8 <_read_r>:
+    36a8:	b570      	push	{r4, r5, r6, lr}
+    36aa:	0005      	movs	r5, r0
+    36ac:	0008      	movs	r0, r1
+    36ae:	0011      	movs	r1, r2
+    36b0:	2200      	movs	r2, #0
+    36b2:	4c06      	ldr	r4, [pc, #24]	; (36cc <_read_r+0x24>)
+    36b4:	6022      	str	r2, [r4, #0]
+    36b6:	001a      	movs	r2, r3
+    36b8:	f7fd fab4 	bl	c24 <_read>
+    36bc:	1c43      	adds	r3, r0, #1
+    36be:	d103      	bne.n	36c8 <_read_r+0x20>
+    36c0:	6823      	ldr	r3, [r4, #0]
+    36c2:	2b00      	cmp	r3, #0
+    36c4:	d000      	beq.n	36c8 <_read_r+0x20>
+    36c6:	602b      	str	r3, [r5, #0]
+    36c8:	bd70      	pop	{r4, r5, r6, pc}
+    36ca:	46c0      	nop			; (mov r8, r8)
+    36cc:	2000029c 	.word	0x2000029c
+    36d0:	000002fa 	.word	0x000002fa
+    36d4:	00000540 	.word	0x00000540
+    36d8:	00000540 	.word	0x00000540
+    36dc:	00000540 	.word	0x00000540
+    36e0:	00000540 	.word	0x00000540
+    36e4:	00000540 	.word	0x00000540
+    36e8:	00000540 	.word	0x00000540
+    36ec:	00000540 	.word	0x00000540
+    36f0:	00000540 	.word	0x00000540
+    36f4:	00000540 	.word	0x00000540
+    36f8:	00000540 	.word	0x00000540
+    36fc:	00000540 	.word	0x00000540
+    3700:	00000540 	.word	0x00000540
+    3704:	00000540 	.word	0x00000540
+    3708:	00000540 	.word	0x00000540
+    370c:	00000540 	.word	0x00000540
+    3710:	000002e2 	.word	0x000002e2
+    3714:	00000540 	.word	0x00000540
+    3718:	00000540 	.word	0x00000540
+    371c:	00000540 	.word	0x00000540
+    3720:	00000540 	.word	0x00000540
+    3724:	00000540 	.word	0x00000540
+    3728:	00000540 	.word	0x00000540
+    372c:	00000540 	.word	0x00000540
+    3730:	00000540 	.word	0x00000540
+    3734:	00000540 	.word	0x00000540
+    3738:	00000540 	.word	0x00000540
+    373c:	00000540 	.word	0x00000540
+    3740:	00000540 	.word	0x00000540
+    3744:	00000540 	.word	0x00000540
+    3748:	00000540 	.word	0x00000540
+    374c:	00000540 	.word	0x00000540
+    3750:	000002f2 	.word	0x000002f2
+    3754:	00000540 	.word	0x00000540
+    3758:	00000540 	.word	0x00000540
+    375c:	00000540 	.word	0x00000540
+    3760:	00000540 	.word	0x00000540
+    3764:	00000540 	.word	0x00000540
+    3768:	00000540 	.word	0x00000540
+    376c:	00000540 	.word	0x00000540
+    3770:	00000540 	.word	0x00000540
+    3774:	00000540 	.word	0x00000540
+    3778:	00000540 	.word	0x00000540
+    377c:	00000540 	.word	0x00000540
+    3780:	00000540 	.word	0x00000540
+    3784:	00000540 	.word	0x00000540
+    3788:	00000540 	.word	0x00000540
+    378c:	00000540 	.word	0x00000540
+    3790:	000002ea 	.word	0x000002ea
+    3794:	00000302 	.word	0x00000302
+    3798:	000002ca 	.word	0x000002ca
+    379c:	000002da 	.word	0x000002da
+    37a0:	000002d2 	.word	0x000002d2
+    37a4:	00000002 	.word	0x00000002
+    37a8:	00000003 	.word	0x00000003
+    37ac:	00000028 	.word	0x00000028
+    37b0:	00000029 	.word	0x00000029
+    37b4:	00000004 	.word	0x00000004
+    37b8:	00000005 	.word	0x00000005
+    37bc:	00000006 	.word	0x00000006
+    37c0:	00000007 	.word	0x00000007
+    37c4:	00000020 	.word	0x00000020
+    37c8:	00000021 	.word	0x00000021
+    37cc:	00000022 	.word	0x00000022
+    37d0:	00000023 	.word	0x00000023
+    37d4:	00000024 	.word	0x00000024
+    37d8:	00000025 	.word	0x00000025
+    37dc:	00000026 	.word	0x00000026
+    37e0:	00000027 	.word	0x00000027
+    37e4:	00000008 	.word	0x00000008
+    37e8:	00000009 	.word	0x00000009
+    37ec:	0000000a 	.word	0x0000000a
+    37f0:	0000000b 	.word	0x0000000b
+    37f4:	42000800 	.word	0x42000800
+    37f8:	42000c00 	.word	0x42000c00
+    37fc:	42001000 	.word	0x42001000
+    3800:	42001400 	.word	0x42001400
+    3804:	42001800 	.word	0x42001800
+    3808:	42001c00 	.word	0x42001c00
+    380c:	000016be 	.word	0x000016be
+    3810:	000016ba 	.word	0x000016ba
+    3814:	000016ba 	.word	0x000016ba
+    3818:	00001720 	.word	0x00001720
+    381c:	00001720 	.word	0x00001720
+    3820:	000016d2 	.word	0x000016d2
+    3824:	000016c4 	.word	0x000016c4
+    3828:	000016d8 	.word	0x000016d8
+    382c:	0000170e 	.word	0x0000170e
+    3830:	000017a8 	.word	0x000017a8
+    3834:	00001788 	.word	0x00001788
+    3838:	00001788 	.word	0x00001788
+    383c:	00001814 	.word	0x00001814
+    3840:	0000179a 	.word	0x0000179a
+    3844:	000017b6 	.word	0x000017b6
+    3848:	0000178c 	.word	0x0000178c
+    384c:	000017c4 	.word	0x000017c4
+    3850:	00001804 	.word	0x00001804
+    3854:	746c6f56 	.word	0x746c6f56
+    3858:	3a656761 	.word	0x3a656761
+    385c:	2e642520 	.word	0x2e642520
+    3860:	64333025 	.word	0x64333025
+    3864:	00000a0d 	.word	0x00000a0d
+    3868:	0000208c 	.word	0x0000208c
+    386c:	00001fdc 	.word	0x00001fdc
+    3870:	00001fdc 	.word	0x00001fdc
+    3874:	00001fda 	.word	0x00001fda
+    3878:	0000207e 	.word	0x0000207e
+    387c:	0000207e 	.word	0x0000207e
+    3880:	00002074 	.word	0x00002074
+    3884:	00001fda 	.word	0x00001fda
+    3888:	0000207e 	.word	0x0000207e
+    388c:	00002074 	.word	0x00002074
+    3890:	0000207e 	.word	0x0000207e
+    3894:	00001fda 	.word	0x00001fda
+    3898:	00002084 	.word	0x00002084
+    389c:	00002084 	.word	0x00002084
+    38a0:	00002084 	.word	0x00002084
+    38a4:	00002114 	.word	0x00002114
+
+000038a8 <_global_impure_ptr>:
+    38a8:	2000001c                                ... 
+
+000038ac <__sf_fake_stderr>:
+	...
+
+000038cc <__sf_fake_stdin>:
+	...
+
+000038ec <__sf_fake_stdout>:
+	...
+    390c:	2b302d23 6c680020 6665004c 47464567     #-0+ .hlL.efgEFG
+    391c:	32313000 36353433 41393837 45444342     .0123456789ABCDE
+    392c:	31300046 35343332 39383736 64636261     F.0123456789abcd
+    393c:	00006665                                ef..
+
+00003940 <_init>:
+    3940:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    3942:	46c0      	nop			; (mov r8, r8)
+    3944:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    3946:	bc08      	pop	{r3}
+    3948:	469e      	mov	lr, r3
+    394a:	4770      	bx	lr
+
+0000394c <__init_array_start>:
+    394c:	000000dd 	.word	0x000000dd
+
+00003950 <_fini>:
+    3950:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    3952:	46c0      	nop			; (mov r8, r8)
+    3954:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    3956:	bc08      	pop	{r3}
+    3958:	469e      	mov	lr, r3
+    395a:	4770      	bx	lr
+
+0000395c <__fini_array_start>:
+    395c:	000000b5 	.word	0x000000b5
diff --git a/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.map b/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.map
index 1a46ff4..bee6d7c 100644
--- a/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.map
+++ b/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.map
@@ -1,6932 +1,6932 @@
-Archive member included to satisfy reference by file (symbol)
-
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
-                              src/ASF/common2/services/delay/sam0/systick_counter.o (__aeabi_uidiv)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) (__aeabi_idiv0)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_muldi3.o)
-                              src/ASF/sam0/drivers/sercom/sercom.o (__aeabi_lmul)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
-                              src/drivers/padc.o (__aeabi_fmul)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subsf3.o)
-                              src/main.o (__aeabi_fsub)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixsfsi.o)
-                              src/main.o (__aeabi_f2iz)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
-                              src/main.o (__aeabi_i2f)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsisf.o)
-                              src/drivers/padc.o (__aeabi_ui2f)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o) (__clzsi2)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (exit)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (__libc_init_array)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
-                              src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o (memcpy)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (memset)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
-                              src/main.o (printf)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
-                              src/drivers/pusart.o (setbuf)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o) (setvbuf)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fflush.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (_fflush_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o) (__sinit)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fwalk.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_fwalk)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-makebuf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (__swhatbuf_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (malloc)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (_free_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_malloc_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o) (_vfprintf_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (_printf_i)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o) (_sbrk_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (__sread)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wbuf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (__swbuf_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o) (_write_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wsetup.o)
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-LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
-LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
-LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-LOAD src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
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-LOAD src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
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-START GROUP
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-Cross Reference Table
-
-Symbol                                            File
-AC_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-ADC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-DAC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-DMAC_Handler                                      src/ASF/sam0/drivers/dma/dma.o
-Dummy_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-EIC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-EVSYS_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-HardFault_Handler                                 src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-I2S_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-NMI_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-NVMCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-PM_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-PTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-PendSV_Handler                                    src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-RTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-Reset_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SERCOM0_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM1_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM2_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM3_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM4_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM5_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SVC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SYSCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SysTick_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SystemCoreClock                                   src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
-SystemCoreClockUpdate                             src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
-SystemInit                                        src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
-TC3_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TC4_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TC5_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TC6_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TC7_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TCC0_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TCC1_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TCC2_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-USB_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-WDT_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-                                                  src/ASF/sam0/drivers/dma/dma.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-                                                  src/ASF/sam0/drivers/dma/dma.o
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-                                                  src/main.o
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-                                                  src/main.o
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-main                                              src/main.o
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-                                                  src/ASF/sam0/drivers/dma/dma.o
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-                                                  src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
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-                                                  src/main.o
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-                                                  src/main.o
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-                                                  src/drivers/pusart.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
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-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-                                                  src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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-                                                  src/ASF/sam0/drivers/sercom/sercom.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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-                                                  src/ASF/common2/services/delay/sam0/systick_counter.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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+ .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
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+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+rom              0x00000000         0x00040000         xr
+ram              0x20000000         0x00008000         xrw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+LOAD src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+LOAD src/ASF/sam0/drivers/dma/dma.o
+LOAD src/ASF/sam0/drivers/sercom/sercom.o
+LOAD src/ASF/sam0/utils/stdio/read.o
+LOAD src/ASF/sam0/utils/stdio/write.o
+LOAD src/drivers/padc.o
+LOAD src/drivers/pusart.o
+LOAD src/ASF/sam0/drivers/sercom/usart/usart.o
+LOAD src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+LOAD src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+LOAD src/ASF/common2/services/delay/sam0/systick_counter.o
+LOAD src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+LOAD src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+LOAD src/ASF/sam0/drivers/port/port.o
+LOAD src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+LOAD src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+LOAD src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+LOAD src/ASF/sam0/drivers/system/pinmux/pinmux.o
+LOAD src/ASF/sam0/drivers/system/system.o
+LOAD src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+LOAD src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+LOAD src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+LOAD src/main.o
+START GROUP
+LOAD ../src/ASF/thirdparty/CMSIS/Lib/GCC\libarm_cortexM0l_math.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+                0x00002000                STACK_SIZE = DEFINED (STACK_SIZE)?STACK_SIZE:DEFINED (__stack_size__)?__stack_size__:0x2000
+
+.text           0x00000000     0x3960
+                0x00000000                . = ALIGN (0x4)
+                0x00000000                _sfixed = .
+ *(.vectors .vectors.*)
+ .vectors       0x00000000       0xb4 src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+                0x00000000                exception_table
+ *(.text .text.* .gnu.linkonce.t.*)
+ .text          0x000000b4       0x60 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .text.adc_get_config_defaults
+                0x00000114       0x46 src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                0x00000114                adc_get_config_defaults
+ *fill*         0x0000015a        0x2 
+ .text.adc_init
+                0x0000015c      0x3f0 src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                0x0000015c                adc_init
+ .text.DMAC_Handler
+                0x0000054c       0xb4 src/ASF/sam0/drivers/dma/dma.o
+                0x0000054c                DMAC_Handler
+ .text.dma_get_config_defaults
+                0x00000600       0x10 src/ASF/sam0/drivers/dma/dma.o
+                0x00000600                dma_get_config_defaults
+ .text.dma_allocate
+                0x00000610      0x148 src/ASF/sam0/drivers/dma/dma.o
+                0x00000610                dma_allocate
+ .text.dma_start_transfer_job
+                0x00000758       0x88 src/ASF/sam0/drivers/dma/dma.o
+                0x00000758                dma_start_transfer_job
+ .text.dma_descriptor_create
+                0x000007e0       0xa8 src/ASF/sam0/drivers/dma/dma.o
+                0x000007e0                dma_descriptor_create
+ .text.dma_add_descriptor
+                0x00000888       0x2a src/ASF/sam0/drivers/dma/dma.o
+                0x00000888                dma_add_descriptor
+ .text.long_division
+                0x000008b2       0xba src/ASF/sam0/drivers/sercom/sercom.o
+ .text._sercom_get_sync_baud_val
+                0x0000096c       0x28 src/ASF/sam0/drivers/sercom/sercom.o
+                0x0000096c                _sercom_get_sync_baud_val
+ .text._sercom_get_async_baud_val
+                0x00000994       0x94 src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000994                _sercom_get_async_baud_val
+ .text.sercom_set_gclk_generator
+                0x00000a28       0x4c src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000a28                sercom_set_gclk_generator
+ .text._sercom_get_default_pad
+                0x00000a74      0x178 src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000a74                _sercom_get_default_pad
+ .text._sercom_get_sercom_inst_index
+                0x00000bec       0x38 src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000bec                _sercom_get_sercom_inst_index
+ .text._read    0x00000c24       0x44 src/ASF/sam0/utils/stdio/read.o
+                0x00000c24                _read
+ .text._write   0x00000c68       0x50 src/ASF/sam0/utils/stdio/write.o
+                0x00000c68                _write
+ .text.padc_init
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+                0x00000cb8                padc_init
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+                0x00000d98                padc_start
+ .text.padc_get_raw
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+                0x00000dcc                padc_get_raw
+ .text.padc_get_voltage
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+                0x00000de8                padc_get_voltage
+ .text.usart_serial_getchar
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+ .text.usart_serial_putchar
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+ .text.usart_init
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+                0x00000f44                usart_init
+ .text.usart_write_wait
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+                0x00001280                usart_write_wait
+ .text.usart_read_wait
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+                0x000012a6                usart_read_wait
+ .text._usart_interrupt_handler
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+                0x00001310                _usart_interrupt_handler
+ .text._sercom_default_handler
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+ *fill*         0x000014a6        0x2 
+ .text._sercom_set_handler
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+                0x000014a8                _sercom_set_handler
+ .text._sercom_get_interrupt_vector
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+                0x000014e4                _sercom_get_interrupt_vector
+ .text.SERCOM0_Handler
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+                0x00001514                SERCOM0_Handler
+ .text.SERCOM1_Handler
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+                0x00001524                SERCOM1_Handler
+ .text.SERCOM2_Handler
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+                0x00001534                SERCOM2_Handler
+ .text.SERCOM3_Handler
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+                0x00001544                SERCOM3_Handler
+ .text.SERCOM4_Handler
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+ .text.SERCOM5_Handler
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+                0x00001564                SERCOM5_Handler
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+                0x00001650                system_board_init
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+
+Cross Reference Table
+
+Symbol                                            File
+AC_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+ADC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+DAC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+DMAC_Handler                                      src/ASF/sam0/drivers/dma/dma.o
+Dummy_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+EIC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+EVSYS_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+HardFault_Handler                                 src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+I2S_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+NMI_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+NVMCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+PM_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+PTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+PendSV_Handler                                    src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+RTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+Reset_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SERCOM0_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM1_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM2_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM3_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM4_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM5_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SVC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SYSCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SysTick_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SystemCoreClock                                   src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+SystemCoreClockUpdate                             src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+SystemInit                                        src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+TC3_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC4_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC5_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC6_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC7_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TCC0_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TCC1_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TCC2_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+USB_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+WDT_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_Jv_RegisterClasses                               c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+__aeabi_f2iz                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixsfsi.o)
+                                                  src/main.o
+__aeabi_fmul                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+                                                  src/main.o
+                                                  src/drivers/padc.o
+__aeabi_fsub                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subsf3.o)
+                                                  src/main.o
+__aeabi_i2f                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+                                                  src/main.o
+__aeabi_idiv                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+__aeabi_idiv0                                     c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
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+_realloc_r                                        c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+_reclaim_reent                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+_sbrk                                             src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+_sbrk_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+_sercom_get_async_baud_val                        src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_get_default_pad                           src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_get_interrupt_vector                      src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/drivers/pusart.o
+_sercom_get_sercom_inst_index                     src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_get_sync_baud_val                         src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_instances                                 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_set_handler                               src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sfixed                                           src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_srelocate                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_start                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+_system_divas_init                                src/ASF/sam0/drivers/system/system.o
+_system_dummy_init                                src/ASF/sam0/drivers/system/system.o
+_system_events_init                               src/ASF/sam0/drivers/system/system.o
+_system_extint_init                               src/ASF/sam0/drivers/system/system.o
+_szero                                            src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_usart_interrupt_handler                          src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_usart_read_buffer                                src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+_usart_write_buffer                               src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+_vfiprintf_r                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+_vfprintf_r                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+_write                                            src/ASF/sam0/utils/stdio/write.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+_write_r                                          c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
+adc_descriptor                                    src/drivers/padc.o
+adc_get_config_defaults                           src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                                                  src/drivers/padc.o
+adc_init                                          src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                                                  src/drivers/padc.o
+adc_regular_ain_channel                           src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+adc_set_window_mode                               src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+atexit                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+board_init                                        src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+cleanup_glue                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+cpu_irq_enter_critical                            src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/dma/dma.o
+cpu_irq_leave_critical                            src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/dma/dma.o
+delay_cycles_ms                                   src/ASF/common2/services/delay/sam0/systick_counter.o
+                                                  src/main.o
+delay_cycles_us                                   src/ASF/common2/services/delay/sam0/systick_counter.o
+delay_init                                        src/ASF/common2/services/delay/sam0/systick_counter.o
+                                                  src/main.o
+descriptor_section                                src/ASF/sam0/drivers/dma/dma.o
+dma_abort_job                                     src/ASF/sam0/drivers/dma/dma.o
+dma_add_descriptor                                src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_allocate                                      src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_descriptor_create                             src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_free                                          src/ASF/sam0/drivers/dma/dma.o
+dma_get_config_defaults                           src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_resume_job                                    src/ASF/sam0/drivers/dma/dma.o
+dma_start_transfer_job                            src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_suspend_job                                   src/ASF/sam0/drivers/dma/dma.o
+errno                                             c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-lseekr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isattyr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fstatr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-closer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+exception_table                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+exit                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+fflush                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fflush.o)
+free                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+g_chan_interrupt_flag                             src/ASF/sam0/drivers/dma/dma.o
+g_interrupt_enabled                               src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+hardware_init_hook                                c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+iprintf                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+link                                              src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+main                                              src/main.o
+                                                  src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+malloc                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
+memchr                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+memcpy                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+                                                  src/ASF/sam0/drivers/dma/dma.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+memmove                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+memset                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+padc_get_raw                                      src/drivers/padc.o
+padc_get_voltage                                  src/drivers/padc.o
+                                                  src/main.o
+padc_init                                         src/drivers/padc.o
+                                                  src/main.o
+padc_start                                        src/drivers/padc.o
+                                                  src/main.o
+port_group_set_config                             src/ASF/sam0/drivers/port/port.o
+port_pin_set_config                               src/ASF/sam0/drivers/port/port.o
+                                                  src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+printf                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+                                                  src/main.o
+ptr_get                                           src/ASF/sam0/utils/stdio/read.o
+                                                  src/drivers/pusart.o
+ptr_put                                           src/ASF/sam0/utils/stdio/write.o
+                                                  src/drivers/pusart.o
+pusart_init                                       src/drivers/pusart.o
+                                                  src/main.o
+sercom_set_gclk_generator                         src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+setbuf                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
+                                                  src/drivers/pusart.o
+setvbuf                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
+software_init_hook                                c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+stdio_base                                        src/ASF/sam0/utils/stdio/write.o
+                                                  src/drivers/pusart.o
+                                                  src/ASF/sam0/utils/stdio/read.o
+system_board_init                                 src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+system_clock_init                                 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_dfll_set_config               src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_disable                       src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_dpll_set_config               src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_enable                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_get_hz                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_clock_source_is_ready                      src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_osc32k_set_config             src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_osc8m_set_config              src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_write_calibration             src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_xosc32k_set_config            src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_xosc_set_config               src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_gclk_chan_disable                          src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_enable                           src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+system_gclk_chan_get_hz                           src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+system_gclk_chan_is_enabled                       src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_is_locked                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_lock                             src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_set_config                       src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+system_gclk_gen_disable                           src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_gen_enable                            src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_gclk_gen_get_hz                            src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/common2/services/delay/sam0/systick_counter.o
+system_gclk_gen_is_enabled                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_gen_set_config                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_gclk_init                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_init                                       src/ASF/sam0/drivers/system/system.o
+                                                  src/main.o
+system_interrupt_clear_pending                    src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_get_priority                     src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_is_pending                       src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_set_pending                      src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_set_priority                     src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_pinmux_group_set_config                    src/ASF/sam0/drivers/system/pinmux/pinmux.o
+                                                  src/ASF/sam0/drivers/port/port.o
+system_pinmux_group_set_input_sample_mode         src/ASF/sam0/drivers/system/pinmux/pinmux.o
+system_pinmux_group_set_output_strength           src/ASF/sam0/drivers/system/pinmux/pinmux.o
+system_pinmux_pin_set_config                      src/ASF/sam0/drivers/system/pinmux/pinmux.o
+                                                  src/ASF/sam0/drivers/port/port.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+umod                                              src/main.o
+                                                  src/drivers/pusart.o
+usart_abort_job                                   src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_get_job_status                              src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_init                                        src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/drivers/pusart.o
+usart_read_buffer_job                             src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_read_buffer_wait                            src/ASF/sam0/drivers/sercom/usart/usart.o
+usart_read_job                                    src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_read_wait                                   src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/drivers/pusart.o
+usart_register_callback                           src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_unregister_callback                         src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_write_buffer_job                            src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_write_buffer_wait                           src/ASF/sam0/drivers/sercom/usart/usart.o
+usart_write_job                                   src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_write_wait                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/drivers/pusart.o
+vfiprintf                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+vfprintf                                          c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
diff --git a/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.srec b/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.srec
index 66bff4d..16e0281 100644
--- a/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.srec
+++ b/D21_ADC_with_DMA/Debug/D21_ADC_with_DMA.srec
@@ -1,928 +1,928 @@
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diff --git a/D21_ADC_with_DMA/Debug/Makefile b/D21_ADC_with_DMA/Debug/Makefile
index 57184ae..d8c5163 100644
--- a/D21_ADC_with_DMA/Debug/Makefile
+++ b/D21_ADC_with_DMA/Debug/Makefile
@@ -1,459 +1,459 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-SHELL := cmd.exe
-RM := rm -rf
-
-USER_OBJS :=
-
-LIBS := 
-PROJ := 
-
-O_SRCS := 
-C_SRCS := 
-S_SRCS := 
-S_UPPER_SRCS := 
-OBJ_SRCS := 
-ASM_SRCS := 
-PREPROCESSING_SRCS := 
-OBJS := 
-OBJS_AS_ARGS := 
-C_DEPS := 
-C_DEPS_AS_ARGS := 
-EXECUTABLES := 
-OUTPUT_FILE_PATH :=
-OUTPUT_FILE_PATH_AS_ARGS :=
-AVR_APP_PATH :=$$$AVR_APP_PATH$$$
-QUOTE := "
-ADDITIONAL_DEPENDENCIES:=
-OUTPUT_FILE_DEP:=
-LIB_DEP:=
-LINKER_SCRIPT_DEP:=
-
-# Every subdirectory with source files must be described here
-SUBDIRS :=  \
-../src/ \
-../src/ASF/ \
-../src/ASF/common2/ \
-../src/ASF/common2/services/ \
-../src/ASF/common2/services/delay/ \
-../src/ASF/common2/services/delay/sam0/ \
-../src/ASF/common/ \
-../src/ASF/common/boards/ \
-../src/ASF/common/services/ \
-../src/ASF/common/services/serial/ \
-../src/ASF/common/services/serial/sam0_usart/ \
-../src/ASF/common/utils/ \
-../src/ASF/common/utils/interrupt/ \
-../src/ASF/sam0/ \
-../src/ASF/sam0/boards/ \
-../src/ASF/sam0/boards/samd21_xplained_pro/ \
-../src/ASF/sam0/drivers/ \
-../src/ASF/sam0/drivers/adc/ \
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/ \
-../src/ASF/sam0/drivers/dma/ \
-../src/ASF/sam0/drivers/dma/quick_start/ \
-../src/ASF/sam0/drivers/port/ \
-../src/ASF/sam0/drivers/port/quick_start/ \
-../src/ASF/sam0/drivers/sercom/ \
-../src/ASF/sam0/drivers/sercom/usart/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start_callback/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start_dma/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start_lin/ \
-../src/ASF/sam0/drivers/system/ \
-../src/ASF/sam0/drivers/system/clock/ \
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ \
-../src/ASF/sam0/drivers/system/interrupt/ \
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/ \
-../src/ASF/sam0/drivers/system/pinmux/ \
-../src/ASF/sam0/drivers/system/pinmux/quick_start/ \
-../src/ASF/sam0/drivers/system/power/ \
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/ \
-../src/ASF/sam0/drivers/system/reset/ \
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/ \
-../src/ASF/sam0/utils/ \
-../src/ASF/sam0/utils/cmsis/ \
-../src/ASF/sam0/utils/cmsis/samd21/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/ \
-../src/ASF/sam0/utils/cmsis/samd21/source/ \
-../src/ASF/sam0/utils/cmsis/samd21/source/gcc/ \
-../src/ASF/sam0/utils/header_files/ \
-../src/ASF/sam0/utils/linker_scripts/ \
-../src/ASF/sam0/utils/linker_scripts/samd21/ \
-../src/ASF/sam0/utils/linker_scripts/samd21/gcc/ \
-../src/ASF/sam0/utils/make/ \
-../src/ASF/sam0/utils/preprocessor/ \
-../src/ASF/sam0/utils/stdio/ \
-../src/ASF/sam0/utils/stdio/stdio_serial/ \
-../src/ASF/sam0/utils/syscalls/ \
-../src/ASF/sam0/utils/syscalls/gcc/ \
-../src/ASF/thirdparty/ \
-../src/ASF/thirdparty/CMSIS/ \
-../src/ASF/thirdparty/CMSIS/Include/ \
-../src/ASF/thirdparty/CMSIS/Lib/ \
-../src/ASF/thirdparty/CMSIS/Lib/GCC/ \
-../src/config/ \
-../src/drivers
-
-
-# Add inputs and outputs from these tool invocations to the build variables 
-C_SRCS +=  \
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
-../src/ASF/sam0/drivers/dma/dma.c \
-../src/ASF/sam0/drivers/sercom/sercom.c \
-../src/ASF/sam0/utils/stdio/read.c \
-../src/ASF/sam0/utils/stdio/write.c \
-../src/drivers/padc.c \
-../src/drivers/pusart.c \
-../src/ASF/sam0/drivers/sercom/usart/usart.c \
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
-../src/ASF/common2/services/delay/sam0/systick_counter.c \
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
-../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
-../src/ASF/sam0/drivers/port/port.c \
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
-../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
-../src/ASF/sam0/drivers/system/system.c \
-../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
-../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
-../src/main.c
-
-
-PREPROCESSING_SRCS += 
-
-
-ASM_SRCS += 
-
-
-OBJS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
-src/ASF/sam0/drivers/dma/dma.o \
-src/ASF/sam0/drivers/sercom/sercom.o \
-src/ASF/sam0/utils/stdio/read.o \
-src/ASF/sam0/utils/stdio/write.o \
-src/drivers/padc.o \
-src/drivers/pusart.o \
-src/ASF/sam0/drivers/sercom/usart/usart.o \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
-src/ASF/common2/services/delay/sam0/systick_counter.o \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
-src/ASF/sam0/drivers/port/port.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
-src/ASF/sam0/drivers/system/pinmux/pinmux.o \
-src/ASF/sam0/drivers/system/system.o \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
-src/main.o
-
-OBJS_AS_ARGS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
-src/ASF/sam0/drivers/dma/dma.o \
-src/ASF/sam0/drivers/sercom/sercom.o \
-src/ASF/sam0/utils/stdio/read.o \
-src/ASF/sam0/utils/stdio/write.o \
-src/drivers/padc.o \
-src/drivers/pusart.o \
-src/ASF/sam0/drivers/sercom/usart/usart.o \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
-src/ASF/common2/services/delay/sam0/systick_counter.o \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
-src/ASF/sam0/drivers/port/port.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
-src/ASF/sam0/drivers/system/pinmux/pinmux.o \
-src/ASF/sam0/drivers/system/system.o \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
-src/main.o
-
-C_DEPS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
-src/ASF/sam0/drivers/dma/dma.d \
-src/ASF/sam0/drivers/sercom/sercom.d \
-src/ASF/sam0/utils/stdio/read.d \
-src/ASF/sam0/utils/stdio/write.d \
-src/drivers/padc.d \
-src/drivers/pusart.d \
-src/ASF/sam0/drivers/sercom/usart/usart.d \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
-src/ASF/common2/services/delay/sam0/systick_counter.d \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
-src/ASF/sam0/drivers/port/port.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
-src/ASF/sam0/drivers/system/pinmux/pinmux.d \
-src/ASF/sam0/drivers/system/system.d \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
-src/main.d
-
-C_DEPS_AS_ARGS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
-src/ASF/sam0/drivers/dma/dma.d \
-src/ASF/sam0/drivers/sercom/sercom.d \
-src/ASF/sam0/utils/stdio/read.d \
-src/ASF/sam0/utils/stdio/write.d \
-src/drivers/padc.d \
-src/drivers/pusart.d \
-src/ASF/sam0/drivers/sercom/usart/usart.d \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
-src/ASF/common2/services/delay/sam0/systick_counter.d \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
-src/ASF/sam0/drivers/port/port.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
-src/ASF/sam0/drivers/system/pinmux/pinmux.d \
-src/ASF/sam0/drivers/system/system.d \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
-src/main.d
-
-OUTPUT_FILE_PATH +=D21_ADC_with_DMA.elf
-
-OUTPUT_FILE_PATH_AS_ARGS +=D21_ADC_with_DMA.elf
-
-ADDITIONAL_DEPENDENCIES:=
-
-OUTPUT_FILE_DEP:= ./makedep.mk
-
-LIB_DEP+= 
-
-LINKER_SCRIPT_DEP+=  \
-../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
-
-
-# AVR32/GNU C Compiler
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/drivers/dma/dma.o: ../src/ASF/sam0/drivers/dma/dma.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/drivers/sercom/sercom.o: ../src/ASF/sam0/drivers/sercom/sercom.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/utils/stdio/read.o: ../src/ASF/sam0/utils/stdio/read.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/utils/stdio/write.o: ../src/ASF/sam0/utils/stdio/write.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/drivers/padc.o: ../src/drivers/padc.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
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-src/drivers/pusart.o: ../src/drivers/pusart.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
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-src/ASF/sam0/drivers/sercom/usart/usart.o: ../src/ASF/sam0/drivers/sercom/usart/usart.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
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-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/sercom/sercom_interrupt.o: ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/common2/services/delay/sam0/systick_counter.o: ../src/ASF/common2/services/delay/sam0/systick_counter.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
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-src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/port/port.o: ../src/ASF/sam0/drivers/port/port.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
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-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
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-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/pinmux/pinmux.o: ../src/ASF/sam0/drivers/system/pinmux/pinmux.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/system.o: ../src/ASF/sam0/drivers/system/system.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/main.o: ../src/main.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-
-
-
-# AVR32/GNU Preprocessing Assembler
-
-
-
-# AVR32/GNU Assembler
-
-
-
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-endif
-
-# Add inputs and outputs from these tool invocations to the build variables 
-
-# All Target
-all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
-
-$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
-	@echo Building target: $@
-	@echo Invoking: ARM/GNU Linker : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="D21_ADC_with_DMA.map" --specs=nano.specs -Wl,--start-group -larm_cortexM0l_math -lm  -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC"  -Wl,--gc-sections -mcpu=cortex-m0plus -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld  
-	@echo Finished building target: $@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS := 
+PROJ := 
+
+O_SRCS := 
+C_SRCS := 
+S_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+PREPROCESSING_SRCS := 
+OBJS := 
+OBJS_AS_ARGS := 
+C_DEPS := 
+C_DEPS_AS_ARGS := 
+EXECUTABLES := 
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+LIB_DEP:=
+LINKER_SCRIPT_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS :=  \
+../src/ \
+../src/ASF/ \
+../src/ASF/common2/ \
+../src/ASF/common2/services/ \
+../src/ASF/common2/services/delay/ \
+../src/ASF/common2/services/delay/sam0/ \
+../src/ASF/common/ \
+../src/ASF/common/boards/ \
+../src/ASF/common/services/ \
+../src/ASF/common/services/serial/ \
+../src/ASF/common/services/serial/sam0_usart/ \
+../src/ASF/common/utils/ \
+../src/ASF/common/utils/interrupt/ \
+../src/ASF/sam0/ \
+../src/ASF/sam0/boards/ \
+../src/ASF/sam0/boards/samd21_xplained_pro/ \
+../src/ASF/sam0/drivers/ \
+../src/ASF/sam0/drivers/adc/ \
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/ \
+../src/ASF/sam0/drivers/dma/ \
+../src/ASF/sam0/drivers/dma/quick_start/ \
+../src/ASF/sam0/drivers/port/ \
+../src/ASF/sam0/drivers/port/quick_start/ \
+../src/ASF/sam0/drivers/sercom/ \
+../src/ASF/sam0/drivers/sercom/usart/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start_callback/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start_dma/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start_lin/ \
+../src/ASF/sam0/drivers/system/ \
+../src/ASF/sam0/drivers/system/clock/ \
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ \
+../src/ASF/sam0/drivers/system/interrupt/ \
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/ \
+../src/ASF/sam0/drivers/system/pinmux/ \
+../src/ASF/sam0/drivers/system/pinmux/quick_start/ \
+../src/ASF/sam0/drivers/system/power/ \
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/ \
+../src/ASF/sam0/drivers/system/reset/ \
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/ \
+../src/ASF/sam0/utils/ \
+../src/ASF/sam0/utils/cmsis/ \
+../src/ASF/sam0/utils/cmsis/samd21/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/ \
+../src/ASF/sam0/utils/cmsis/samd21/source/ \
+../src/ASF/sam0/utils/cmsis/samd21/source/gcc/ \
+../src/ASF/sam0/utils/header_files/ \
+../src/ASF/sam0/utils/linker_scripts/ \
+../src/ASF/sam0/utils/linker_scripts/samd21/ \
+../src/ASF/sam0/utils/linker_scripts/samd21/gcc/ \
+../src/ASF/sam0/utils/make/ \
+../src/ASF/sam0/utils/preprocessor/ \
+../src/ASF/sam0/utils/stdio/ \
+../src/ASF/sam0/utils/stdio/stdio_serial/ \
+../src/ASF/sam0/utils/syscalls/ \
+../src/ASF/sam0/utils/syscalls/gcc/ \
+../src/ASF/thirdparty/ \
+../src/ASF/thirdparty/CMSIS/ \
+../src/ASF/thirdparty/CMSIS/Include/ \
+../src/ASF/thirdparty/CMSIS/Lib/ \
+../src/ASF/thirdparty/CMSIS/Lib/GCC/ \
+../src/config/ \
+../src/drivers
+
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS +=  \
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
+../src/ASF/sam0/drivers/dma/dma.c \
+../src/ASF/sam0/drivers/sercom/sercom.c \
+../src/ASF/sam0/utils/stdio/read.c \
+../src/ASF/sam0/utils/stdio/write.c \
+../src/drivers/padc.c \
+../src/drivers/pusart.c \
+../src/ASF/sam0/drivers/sercom/usart/usart.c \
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
+../src/ASF/common2/services/delay/sam0/systick_counter.c \
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
+../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
+../src/ASF/sam0/drivers/port/port.c \
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
+../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
+../src/ASF/sam0/drivers/system/system.c \
+../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
+../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
+../src/main.c
+
+
+PREPROCESSING_SRCS += 
+
+
+ASM_SRCS += 
+
+
+OBJS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
+src/ASF/sam0/drivers/dma/dma.o \
+src/ASF/sam0/drivers/sercom/sercom.o \
+src/ASF/sam0/utils/stdio/read.o \
+src/ASF/sam0/utils/stdio/write.o \
+src/drivers/padc.o \
+src/drivers/pusart.o \
+src/ASF/sam0/drivers/sercom/usart/usart.o \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
+src/ASF/common2/services/delay/sam0/systick_counter.o \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
+src/ASF/sam0/drivers/port/port.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
+src/ASF/sam0/drivers/system/pinmux/pinmux.o \
+src/ASF/sam0/drivers/system/system.o \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
+src/main.o
+
+OBJS_AS_ARGS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
+src/ASF/sam0/drivers/dma/dma.o \
+src/ASF/sam0/drivers/sercom/sercom.o \
+src/ASF/sam0/utils/stdio/read.o \
+src/ASF/sam0/utils/stdio/write.o \
+src/drivers/padc.o \
+src/drivers/pusart.o \
+src/ASF/sam0/drivers/sercom/usart/usart.o \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
+src/ASF/common2/services/delay/sam0/systick_counter.o \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
+src/ASF/sam0/drivers/port/port.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
+src/ASF/sam0/drivers/system/pinmux/pinmux.o \
+src/ASF/sam0/drivers/system/system.o \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
+src/main.o
+
+C_DEPS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
+src/ASF/sam0/drivers/dma/dma.d \
+src/ASF/sam0/drivers/sercom/sercom.d \
+src/ASF/sam0/utils/stdio/read.d \
+src/ASF/sam0/utils/stdio/write.d \
+src/drivers/padc.d \
+src/drivers/pusart.d \
+src/ASF/sam0/drivers/sercom/usart/usart.d \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
+src/ASF/common2/services/delay/sam0/systick_counter.d \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
+src/ASF/sam0/drivers/port/port.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
+src/ASF/sam0/drivers/system/pinmux/pinmux.d \
+src/ASF/sam0/drivers/system/system.d \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
+src/main.d
+
+C_DEPS_AS_ARGS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
+src/ASF/sam0/drivers/dma/dma.d \
+src/ASF/sam0/drivers/sercom/sercom.d \
+src/ASF/sam0/utils/stdio/read.d \
+src/ASF/sam0/utils/stdio/write.d \
+src/drivers/padc.d \
+src/drivers/pusart.d \
+src/ASF/sam0/drivers/sercom/usart/usart.d \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
+src/ASF/common2/services/delay/sam0/systick_counter.d \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
+src/ASF/sam0/drivers/port/port.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
+src/ASF/sam0/drivers/system/pinmux/pinmux.d \
+src/ASF/sam0/drivers/system/system.d \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
+src/main.d
+
+OUTPUT_FILE_PATH +=D21_ADC_with_DMA.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +=D21_ADC_with_DMA.elf
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+LIB_DEP+= 
+
+LINKER_SCRIPT_DEP+=  \
+../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
+
+
+# AVR32/GNU C Compiler
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/dma/dma.o: ../src/ASF/sam0/drivers/dma/dma.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/sercom.o: ../src/ASF/sam0/drivers/sercom/sercom.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/stdio/read.o: ../src/ASF/sam0/utils/stdio/read.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/stdio/write.o: ../src/ASF/sam0/utils/stdio/write.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/drivers/padc.o: ../src/drivers/padc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/drivers/pusart.o: ../src/drivers/pusart.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/usart/usart.o: ../src/ASF/sam0/drivers/sercom/usart/usart.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/sercom_interrupt.o: ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/common2/services/delay/sam0/systick_counter.o: ../src/ASF/common2/services/delay/sam0/systick_counter.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/port/port.o: ../src/ASF/sam0/drivers/port/port.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/pinmux/pinmux.o: ../src/ASF/sam0/drivers/system/pinmux/pinmux.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/system.o: ../src/ASF/sam0/drivers/system/system.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/main.o: ../src/main.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables 
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
+	@echo Building target: $@
+	@echo Invoking: ARM/GNU Linker : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="D21_ADC_with_DMA.map" --specs=nano.specs -Wl,--start-group -larm_cortexM0l_math -lm  -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC"  -Wl,--gc-sections -mcpu=cortex-m0plus -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld  
+	@echo Finished building target: $@
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.bin"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature  "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.hex"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.eep" || exit 0
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "D21_ADC_with_DMA.elf" > "D21_ADC_with_DMA.lss"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature  "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.srec"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "D21_ADC_with_DMA.elf"
-	
-	
-
-
-
-
-
-# Other Targets
-clean:
-	-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)  
-	-$(RM) $(C_DEPS_AS_ARGS)   
+	
+	
+
+
+
+
+
+# Other Targets
+clean:
+	-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)  
+	-$(RM) $(C_DEPS_AS_ARGS)   
 	rm -rf "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.a" "D21_ADC_with_DMA.hex" "D21_ADC_with_DMA.bin" "D21_ADC_with_DMA.lss" "D21_ADC_with_DMA.eep" "D21_ADC_with_DMA.map" "D21_ADC_with_DMA.srec"
 	
\ No newline at end of file
diff --git a/D21_ADC_with_DMA/Debug/makedep.mk b/D21_ADC_with_DMA/Debug/makedep.mk
index 7b7c3e4..fa4e86c 100644
--- a/D21_ADC_with_DMA/Debug/makedep.mk
+++ b/D21_ADC_with_DMA/Debug/makedep.mk
@@ -1,50 +1,50 @@
-################################################################################
-# Automatically-generated file. Do not edit or delete the file
-################################################################################
-
-src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc.c
-
-src\ASF\sam0\drivers\dma\dma.c
-
-src\ASF\sam0\drivers\sercom\sercom.c
-
-src\ASF\sam0\utils\stdio\read.c
-
-src\ASF\sam0\utils\stdio\write.c
-
-src\drivers\padc.c
-
-src\drivers\pusart.c
-
-src\ASF\sam0\drivers\sercom\usart\usart.c
-
-src\ASF\sam0\drivers\sercom\usart\usart_interrupt.c
-
-src\ASF\sam0\drivers\sercom\sercom_interrupt.c
-
-src\ASF\common2\services\delay\sam0\systick_counter.c
-
-src\ASF\common\utils\interrupt\interrupt_sam_nvic.c
-
-src\ASF\sam0\boards\samd21_xplained_pro\board_init.c
-
-src\ASF\sam0\drivers\port\port.c
-
-src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c
-
-src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c
-
-src\ASF\sam0\drivers\system\interrupt\system_interrupt.c
-
-src\ASF\sam0\drivers\system\pinmux\pinmux.c
-
-src\ASF\sam0\drivers\system\system.c
-
-src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c
-
-src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c
-
-src\ASF\sam0\utils\syscalls\gcc\syscalls.c
-
-src\main.c
-
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc.c
+
+src\ASF\sam0\drivers\dma\dma.c
+
+src\ASF\sam0\drivers\sercom\sercom.c
+
+src\ASF\sam0\utils\stdio\read.c
+
+src\ASF\sam0\utils\stdio\write.c
+
+src\drivers\padc.c
+
+src\drivers\pusart.c
+
+src\ASF\sam0\drivers\sercom\usart\usart.c
+
+src\ASF\sam0\drivers\sercom\usart\usart_interrupt.c
+
+src\ASF\sam0\drivers\sercom\sercom_interrupt.c
+
+src\ASF\common2\services\delay\sam0\systick_counter.c
+
+src\ASF\common\utils\interrupt\interrupt_sam_nvic.c
+
+src\ASF\sam0\boards\samd21_xplained_pro\board_init.c
+
+src\ASF\sam0\drivers\port\port.c
+
+src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c
+
+src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c
+
+src\ASF\sam0\drivers\system\interrupt\system_interrupt.c
+
+src\ASF\sam0\drivers\system\pinmux\pinmux.c
+
+src\ASF\sam0\drivers\system\system.c
+
+src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c
+
+src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c
+
+src\ASF\sam0\utils\syscalls\gcc\syscalls.c
+
+src\main.c
+
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d b/D21_ADC_with_DMA/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d
index c53da4c..64e3741 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d
@@ -1,341 +1,341 @@
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
- src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
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-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
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-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
+ src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/common2/services/delay/sam0/systick_counter.d b/D21_ADC_with_DMA/Debug/src/ASF/common2/services/delay/sam0/systick_counter.d
index 328aef8..bf07fed 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/common2/services/delay/sam0/systick_counter.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/common2/services/delay/sam0/systick_counter.d
@@ -1,353 +1,353 @@
-src/ASF/common2/services/delay/sam0/systick_counter.d \
- src/ASF/common2/services/delay/sam0/systick_counter.o: \
- ../src/ASF/common2/services/delay/sam0/systick_counter.c \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
-
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-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
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-../src/ASF/common/utils/interrupt.h:
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-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
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-../src/ASF/sam0/drivers/system/clock/clock.h:
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-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+src/ASF/common2/services/delay/sam0/systick_counter.d \
+ src/ASF/common2/services/delay/sam0/systick_counter.o: \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.c \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
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+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d
index 9542e11..32d28ed 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d
@@ -1,352 +1,352 @@
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
- src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: \
- ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
+ src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d
index 6caa1fe..e5538f2 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d
@@ -1,364 +1,364 @@
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
- src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
- ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
-
-../src/ASF/sam0/drivers/adc/adc.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
+ src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
+ ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/dma/dma.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/dma/dma.d
index 2b6b8cc..df0de98 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/dma/dma.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/dma/dma.d
@@ -1,365 +1,365 @@
-src/ASF/sam0/drivers/dma/dma.d src/ASF/sam0/drivers/dma/dma.o: \
- ../src/ASF/sam0/drivers/dma/dma.c \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/ASF/sam0/utils/compiler.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/config/conf_dma.h ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
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-../src/ASF/sam0/drivers/dma/dma.h:
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-../src/ASF/sam0/utils/compiler.h:
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-../src/ASF/sam0/utils/status_codes.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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-../src/ASF/sam0/utils/header_files/io.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
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-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+src/ASF/sam0/drivers/dma/dma.d src/ASF/sam0/drivers/dma/dma.o: \
+ ../src/ASF/sam0/drivers/dma/dma.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/ASF/sam0/utils/compiler.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/config/conf_dma.h ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/port/port.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/port/port.d
index 73cd629..0729ad9 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/port/port.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/port/port.d
@@ -1,342 +1,342 @@
-src/ASF/sam0/drivers/port/port.d src/ASF/sam0/drivers/port/port.o: \
- ../src/ASF/sam0/drivers/port/port.c ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+src/ASF/sam0/drivers/port/port.d src/ASF/sam0/drivers/port/port.o: \
+ ../src/ASF/sam0/drivers/port/port.c ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom.d
index d4455e7..1346355 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom.d
@@ -1,369 +1,369 @@
-src/ASF/sam0/drivers/sercom/sercom.d src/ASF/sam0/drivers/sercom/sercom.o: \
- ../src/ASF/sam0/drivers/sercom/sercom.c \
- ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+src/ASF/sam0/drivers/sercom/sercom.d src/ASF/sam0/drivers/sercom/sercom.o: \
+ ../src/ASF/sam0/drivers/sercom/sercom.c \
+ ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom_interrupt.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom_interrupt.d
index a97be0c..0985495 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom_interrupt.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/sercom_interrupt.d
@@ -1,373 +1,373 @@
-src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
- src/ASF/sam0/drivers/sercom/sercom_interrupt.o: \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
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-../src/ASF/sam0/drivers/sercom/sercom.h:
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-../src/ASF/sam0/utils/compiler.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
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-../src/ASF/common/utils/parts.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
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-../src/ASF/sam0/utils/header_files/io.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
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-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
+ src/ASF/sam0/drivers/sercom/sercom_interrupt.o: \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart.d
index 0d07ee9..bf5875a 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart.d
@@ -1,383 +1,383 @@
-src/ASF/sam0/drivers/sercom/usart/usart.d \
- src/ASF/sam0/drivers/sercom/usart/usart.o: \
- ../src/ASF/sam0/drivers/sercom/usart/usart.c \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+src/ASF/sam0/drivers/sercom/usart/usart.d \
+ src/ASF/sam0/drivers/sercom/usart/usart.o: \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.c \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d
index 17c9fc9..fdd3779 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d
@@ -1,383 +1,383 @@
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
- src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
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-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
+ src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d
index cc2a874..db4524f 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d
@@ -1,364 +1,364 @@
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
- src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/config/conf_clocks.h ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
-
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-../src/ASF/common/utils/parts.h:
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-../src/ASF/sam0/utils/status_codes.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/header_files/io.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
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-../src/ASF/common/utils/interrupt.h:
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-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
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-../src/ASF/sam0/drivers/system/clock/gclk.h:
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-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
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-../src/config/conf_clocks.h:
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-../src/ASF/sam0/drivers/system/system.h:
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-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
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-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
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-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h:
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
+ src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/config/conf_clocks.h ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/config/conf_clocks.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d
index cfadc8a..49655f4 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d
@@ -1,353 +1,353 @@
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
- src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
+ src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d
index a33accd..a240975 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d
@@ -1,344 +1,344 @@
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
- src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
+ src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/pinmux/pinmux.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/pinmux/pinmux.d
index 6ff3783..d444102 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/pinmux/pinmux.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/pinmux/pinmux.d
@@ -1,341 +1,341 @@
-src/ASF/sam0/drivers/system/pinmux/pinmux.d \
- src/ASF/sam0/drivers/system/pinmux/pinmux.o: \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/sam0/drivers/system/pinmux/pinmux.d \
+ src/ASF/sam0/drivers/system/pinmux/pinmux.o: \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/system.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/system.d
index 467fb4b..136d6ea 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/system.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/drivers/system/system.d
@@ -1,357 +1,357 @@
-src/ASF/sam0/drivers/system/system.d src/ASF/sam0/drivers/system/system.o: \
- ../src/ASF/sam0/drivers/system/system.c \
- ../src/ASF/sam0/drivers/system/system.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
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-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+src/ASF/sam0/drivers/system/system.d src/ASF/sam0/drivers/system/system.o: \
+ ../src/ASF/sam0/drivers/system/system.c \
+ ../src/ASF/sam0/drivers/system/system.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d
index 2765c20..e6d9221 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d
@@ -1,219 +1,219 @@
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
- src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: \
- ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
+ src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d
index 1e3c64c..b19e1e5 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d
@@ -1,219 +1,219 @@
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
- src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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-
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-
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
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-
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-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
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-
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-
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-
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-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
+ src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/read.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/read.d
index c941e1d..bc96833 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/read.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/read.d
@@ -1,336 +1,336 @@
-src/ASF/sam0/utils/stdio/read.d src/ASF/sam0/utils/stdio/read.o: \
- ../src/ASF/sam0/utils/stdio/read.c ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/sam0/utils/stdio/read.d src/ASF/sam0/utils/stdio/read.o: \
+ ../src/ASF/sam0/utils/stdio/read.c ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/write.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/write.d
index 4a1d644..71aea27 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/write.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/stdio/write.d
@@ -1,336 +1,336 @@
-src/ASF/sam0/utils/stdio/write.d src/ASF/sam0/utils/stdio/write.o: \
- ../src/ASF/sam0/utils/stdio/write.c ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/sam0/utils/stdio/write.d src/ASF/sam0/utils/stdio/write.o: \
+ ../src/ASF/sam0/utils/stdio/write.c ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/syscalls/gcc/syscalls.d b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/syscalls/gcc/syscalls.d
index 2ba412a..8c1aa09 100644
--- a/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/syscalls/gcc/syscalls.d
+++ b/D21_ADC_with_DMA/Debug/src/ASF/sam0/utils/syscalls/gcc/syscalls.d
@@ -1,99 +1,99 @@
-src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
- src/ASF/sam0/utils/syscalls/gcc/syscalls.o: \
- ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
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-
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-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
+ src/ASF/sam0/utils/syscalls/gcc/syscalls.o: \
+ ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
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+
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+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
diff --git a/D21_ADC_with_DMA/Debug/src/drivers/padc.d b/D21_ADC_with_DMA/Debug/src/drivers/padc.d
index ef93217..fe3a318 100644
--- a/D21_ADC_with_DMA/Debug/src/drivers/padc.d
+++ b/D21_ADC_with_DMA/Debug/src/drivers/padc.d
@@ -1,428 +1,428 @@
-src/drivers/padc.d src/drivers/padc.o: ../src/drivers/padc.c \
- ../src/drivers/padc.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
- ../src/ASF/sam0/drivers/dma/dma_crc.h \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
- ../src/ASF/common/services/serial/serial.h \
- ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
-
-../src/drivers/padc.h:
-
-../src/asf.h:
-
-../src/ASF/sam0/drivers/adc/adc.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/dma/dma_crc.h:
-
-../src/ASF/common2/services/delay/delay.h:
-
-../src/ASF/common2/services/delay/sam0/systick_counter.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
-
-../src/ASF/common/services/serial/serial.h:
-
-../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
+src/drivers/padc.d src/drivers/padc.o: ../src/drivers/padc.c \
+ ../src/drivers/padc.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
+ ../src/ASF/sam0/drivers/dma/dma_crc.h \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
+ ../src/ASF/common/services/serial/serial.h \
+ ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
+
+../src/drivers/padc.h:
+
+../src/asf.h:
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/dma/dma_crc.h:
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
+
+../src/ASF/common/services/serial/serial.h:
+
+../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
diff --git a/D21_ADC_with_DMA/Debug/src/drivers/pusart.d b/D21_ADC_with_DMA/Debug/src/drivers/pusart.d
index 057b94e..c8504e2 100644
--- a/D21_ADC_with_DMA/Debug/src/drivers/pusart.d
+++ b/D21_ADC_with_DMA/Debug/src/drivers/pusart.d
@@ -1,428 +1,428 @@
-src/drivers/pusart.d src/drivers/pusart.o: ../src/drivers/pusart.c \
- ../src/drivers/pusart.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
- ../src/ASF/sam0/drivers/dma/dma_crc.h \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
- ../src/ASF/common/services/serial/serial.h \
- ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
-
-../src/drivers/pusart.h:
-
-../src/asf.h:
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-../src/ASF/sam0/drivers/adc/adc.h:
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-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/dma/dma_crc.h:
-
-../src/ASF/common2/services/delay/delay.h:
-
-../src/ASF/common2/services/delay/sam0/systick_counter.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
-
-../src/ASF/common/services/serial/serial.h:
-
-../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
+src/drivers/pusart.d src/drivers/pusart.o: ../src/drivers/pusart.c \
+ ../src/drivers/pusart.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
+ ../src/ASF/sam0/drivers/dma/dma_crc.h \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
+ ../src/ASF/common/services/serial/serial.h \
+ ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
+
+../src/drivers/pusart.h:
+
+../src/asf.h:
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/dma/dma_crc.h:
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
+
+../src/ASF/common/services/serial/serial.h:
+
+../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
diff --git a/D21_ADC_with_DMA/Debug/src/main.d b/D21_ADC_with_DMA/Debug/src/main.d
index 61e4018..5868bd8 100644
--- a/D21_ADC_with_DMA/Debug/src/main.d
+++ b/D21_ADC_with_DMA/Debug/src/main.d
@@ -1,430 +1,430 @@
-src/main.d src/main.o: ../src/main.c ../src/asf.h \
- ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
- ../src/ASF/sam0/drivers/dma/dma_crc.h \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
- ../src/ASF/common/services/serial/serial.h \
- ../src/ASF/common/services/serial/sam0_usart/usart_serial.h \
- ../src/drivers/pusart.h ../src/drivers/padc.h
-
-../src/asf.h:
-
-../src/ASF/sam0/drivers/adc/adc.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/dma/dma_crc.h:
-
-../src/ASF/common2/services/delay/delay.h:
-
-../src/ASF/common2/services/delay/sam0/systick_counter.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
-
-../src/ASF/common/services/serial/serial.h:
-
-../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
-
-../src/drivers/pusart.h:
-
-../src/drivers/padc.h:
+src/main.d src/main.o: ../src/main.c ../src/asf.h \
+ ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
+ ../src/ASF/sam0/drivers/dma/dma_crc.h \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
+ ../src/ASF/common/services/serial/serial.h \
+ ../src/ASF/common/services/serial/sam0_usart/usart_serial.h \
+ ../src/drivers/pusart.h ../src/drivers/padc.h
+
+../src/asf.h:
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
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+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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+../src/ASF/sam0/drivers/sercom/sercom.h:
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+../src/ASF/sam0/drivers/sercom/usart/usart.h:
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+../src/drivers/pusart.h:
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diff --git a/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.lss b/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.lss
index d4705a6..b0ae02f 100644
--- a/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.lss
+++ b/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.lss
@@ -1,6653 +1,11109 @@
-
-D21_ADC_with_DMA.elf:     file format elf32-littlearm
-
-Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         000036e8  00000000  00000000  00010000  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, CODE
-  1 .relocate     0000007c  20000000  000036e8  00020000  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  2 .bss          00000220  20000080  00003770  00020080  2**4
-                  ALLOC
-  3 .stack        00002000  200002a0  00003990  00020080  2**0
-                  ALLOC
-  4 .ARM.attributes 00000028  00000000  00000000  0002007c  2**0
-                  CONTENTS, READONLY
-  5 .comment      00000059  00000000  00000000  000200a4  2**0
-                  CONTENTS, READONLY
-  6 .debug_frame  00000948  00000000  00000000  00020100  2**2
-                  CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-00000000 <exception_table>:
-       0:	a0 22 00 20 81 19 00 00 7d 19 00 00 7d 19 00 00     .". ....}...}...
-	...
-      2c:	7d 19 00 00 00 00 00 00 00 00 00 00 7d 19 00 00     }...........}...
-      3c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
-      4c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 79 04 00 00     }...}...}...y...
-      5c:	7d 19 00 00 7d 19 00 00 ad 12 00 00 bd 12 00 00     }...}...........
-      6c:	cd 12 00 00 dd 12 00 00 ed 12 00 00 fd 12 00 00     ................
-      7c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
-      8c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
-      9c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
-      ac:	7d 19 00 00 00 00 00 00                             }.......
-
-000000b4 <__do_global_dtors_aux>:
-      b4:	b510      	push	{r4, lr}
-      b6:	4c06      	ldr	r4, [pc, #24]	; (d0 <__do_global_dtors_aux+0x1c>)
-      b8:	7823      	ldrb	r3, [r4, #0]
-      ba:	2b00      	cmp	r3, #0
-      bc:	d107      	bne.n	ce <__do_global_dtors_aux+0x1a>
-      be:	4b05      	ldr	r3, [pc, #20]	; (d4 <__do_global_dtors_aux+0x20>)
-      c0:	2b00      	cmp	r3, #0
-      c2:	d002      	beq.n	ca <__do_global_dtors_aux+0x16>
-      c4:	4804      	ldr	r0, [pc, #16]	; (d8 <__do_global_dtors_aux+0x24>)
-      c6:	e000      	b.n	ca <__do_global_dtors_aux+0x16>
-      c8:	bf00      	nop
-      ca:	2301      	movs	r3, #1
-      cc:	7023      	strb	r3, [r4, #0]
-      ce:	bd10      	pop	{r4, pc}
-      d0:	20000080 	.word	0x20000080
-      d4:	00000000 	.word	0x00000000
-      d8:	000036e8 	.word	0x000036e8
-
-000000dc <frame_dummy>:
-      dc:	4b08      	ldr	r3, [pc, #32]	; (100 <frame_dummy+0x24>)
-      de:	b510      	push	{r4, lr}
-      e0:	2b00      	cmp	r3, #0
-      e2:	d003      	beq.n	ec <frame_dummy+0x10>
-      e4:	4907      	ldr	r1, [pc, #28]	; (104 <frame_dummy+0x28>)
-      e6:	4808      	ldr	r0, [pc, #32]	; (108 <frame_dummy+0x2c>)
-      e8:	e000      	b.n	ec <frame_dummy+0x10>
-      ea:	bf00      	nop
-      ec:	4807      	ldr	r0, [pc, #28]	; (10c <frame_dummy+0x30>)
-      ee:	6803      	ldr	r3, [r0, #0]
-      f0:	2b00      	cmp	r3, #0
-      f2:	d100      	bne.n	f6 <frame_dummy+0x1a>
-      f4:	bd10      	pop	{r4, pc}
-      f6:	4b06      	ldr	r3, [pc, #24]	; (110 <frame_dummy+0x34>)
-      f8:	2b00      	cmp	r3, #0
-      fa:	d0fb      	beq.n	f4 <frame_dummy+0x18>
-      fc:	4798      	blx	r3
-      fe:	e7f9      	b.n	f4 <frame_dummy+0x18>
-     100:	00000000 	.word	0x00000000
-     104:	20000084 	.word	0x20000084
-     108:	000036e8 	.word	0x000036e8
-     10c:	000036e8 	.word	0x000036e8
-     110:	00000000 	.word	0x00000000
-
-00000114 <_adc_configure_ain_pin>:
-     114:	b530      	push	{r4, r5, lr}
-     116:	b097      	sub	sp, #92	; 0x5c
-     118:	ad02      	add	r5, sp, #8
-     11a:	0004      	movs	r4, r0
-     11c:	2250      	movs	r2, #80	; 0x50
-     11e:	490a      	ldr	r1, [pc, #40]	; (148 <_adc_configure_ain_pin+0x34>)
-     120:	0028      	movs	r0, r5
-     122:	4b0a      	ldr	r3, [pc, #40]	; (14c <_adc_configure_ain_pin+0x38>)
-     124:	4798      	blx	r3
-     126:	2c13      	cmp	r4, #19
-     128:	d80b      	bhi.n	142 <_adc_configure_ain_pin+0x2e>
-     12a:	2300      	movs	r3, #0
-     12c:	00a4      	lsls	r4, r4, #2
-     12e:	a901      	add	r1, sp, #4
-     130:	5960      	ldr	r0, [r4, r5]
-     132:	704b      	strb	r3, [r1, #1]
-     134:	70cb      	strb	r3, [r1, #3]
-     136:	708b      	strb	r3, [r1, #2]
-     138:	3301      	adds	r3, #1
-     13a:	700b      	strb	r3, [r1, #0]
-     13c:	b2c0      	uxtb	r0, r0
-     13e:	4b04      	ldr	r3, [pc, #16]	; (150 <_adc_configure_ain_pin+0x3c>)
-     140:	4798      	blx	r3
-     142:	b017      	add	sp, #92	; 0x5c
-     144:	bd30      	pop	{r4, r5, pc}
-     146:	46c0      	nop			; (mov r8, r8)
-     148:	00003524 	.word	0x00003524
-     14c:	00002449 	.word	0x00002449
-     150:	00001921 	.word	0x00001921
-
-00000154 <adc_get_config_defaults>:
-     154:	22c0      	movs	r2, #192	; 0xc0
-     156:	0152      	lsls	r2, r2, #5
-     158:	81c2      	strh	r2, [r0, #14]
-     15a:	0002      	movs	r2, r0
-     15c:	2300      	movs	r3, #0
-     15e:	322a      	adds	r2, #42	; 0x2a
-     160:	7003      	strb	r3, [r0, #0]
-     162:	7043      	strb	r3, [r0, #1]
-     164:	8043      	strh	r3, [r0, #2]
-     166:	7103      	strb	r3, [r0, #4]
-     168:	7603      	strb	r3, [r0, #24]
-     16a:	6203      	str	r3, [r0, #32]
-     16c:	61c3      	str	r3, [r0, #28]
-     16e:	6083      	str	r3, [r0, #8]
-     170:	7303      	strb	r3, [r0, #12]
-     172:	7403      	strb	r3, [r0, #16]
-     174:	7443      	strb	r3, [r0, #17]
-     176:	7483      	strb	r3, [r0, #18]
-     178:	74c3      	strb	r3, [r0, #19]
-     17a:	7503      	strb	r3, [r0, #20]
-     17c:	7013      	strb	r3, [r2, #0]
-     17e:	1d42      	adds	r2, r0, #5
-     180:	7543      	strb	r3, [r0, #21]
-     182:	7583      	strb	r3, [r0, #22]
-     184:	77d3      	strb	r3, [r2, #31]
-     186:	84c3      	strh	r3, [r0, #38]	; 0x26
-     188:	8503      	strh	r3, [r0, #40]	; 0x28
-     18a:	75c3      	strb	r3, [r0, #23]
-     18c:	3226      	adds	r2, #38	; 0x26
-     18e:	302c      	adds	r0, #44	; 0x2c
-     190:	7013      	strb	r3, [r2, #0]
-     192:	7003      	strb	r3, [r0, #0]
-     194:	4770      	bx	lr
-	...
-
-00000198 <adc_init>:
-     198:	2380      	movs	r3, #128	; 0x80
-     19a:	b5f0      	push	{r4, r5, r6, r7, lr}
-     19c:	0014      	movs	r4, r2
-     19e:	4aac      	ldr	r2, [pc, #688]	; (450 <adc_init+0x2b8>)
-     1a0:	6001      	str	r1, [r0, #0]
-     1a2:	0007      	movs	r7, r0
-     1a4:	6a10      	ldr	r0, [r2, #32]
-     1a6:	025b      	lsls	r3, r3, #9
-     1a8:	4303      	orrs	r3, r0
-     1aa:	6213      	str	r3, [r2, #32]
-     1ac:	780b      	ldrb	r3, [r1, #0]
-     1ae:	b087      	sub	sp, #28
-     1b0:	2005      	movs	r0, #5
-     1b2:	07db      	lsls	r3, r3, #31
-     1b4:	d500      	bpl.n	1b8 <adc_init+0x20>
-     1b6:	e0e7      	b.n	388 <adc_init+0x1f0>
-     1b8:	780b      	ldrb	r3, [r1, #0]
-     1ba:	3017      	adds	r0, #23
-     1bc:	079b      	lsls	r3, r3, #30
-     1be:	d500      	bpl.n	1c2 <adc_init+0x2a>
-     1c0:	e0e2      	b.n	388 <adc_init+0x1f0>
-     1c2:	7863      	ldrb	r3, [r4, #1]
-     1c4:	713b      	strb	r3, [r7, #4]
-     1c6:	2b00      	cmp	r3, #0
-     1c8:	d104      	bne.n	1d4 <adc_init+0x3c>
-     1ca:	4aa2      	ldr	r2, [pc, #648]	; (454 <adc_init+0x2bc>)
-     1cc:	3304      	adds	r3, #4
-     1ce:	6c11      	ldr	r1, [r2, #64]	; 0x40
-     1d0:	430b      	orrs	r3, r1
-     1d2:	6413      	str	r3, [r2, #64]	; 0x40
-     1d4:	7823      	ldrb	r3, [r4, #0]
-     1d6:	a905      	add	r1, sp, #20
-     1d8:	700b      	strb	r3, [r1, #0]
-     1da:	201e      	movs	r0, #30
-     1dc:	4b9e      	ldr	r3, [pc, #632]	; (458 <adc_init+0x2c0>)
-     1de:	683d      	ldr	r5, [r7, #0]
-     1e0:	4798      	blx	r3
-     1e2:	4b9e      	ldr	r3, [pc, #632]	; (45c <adc_init+0x2c4>)
-     1e4:	201e      	movs	r0, #30
-     1e6:	4798      	blx	r3
-     1e8:	0023      	movs	r3, r4
-     1ea:	332c      	adds	r3, #44	; 0x2c
-     1ec:	9302      	str	r3, [sp, #8]
-     1ee:	781b      	ldrb	r3, [r3, #0]
-     1f0:	7b22      	ldrb	r2, [r4, #12]
-     1f2:	9201      	str	r2, [sp, #4]
-     1f4:	2b00      	cmp	r3, #0
-     1f6:	d033      	beq.n	260 <adc_init+0xc8>
-     1f8:	0022      	movs	r2, r4
-     1fa:	322b      	adds	r2, #43	; 0x2b
-     1fc:	7816      	ldrb	r6, [r2, #0]
-     1fe:	9a01      	ldr	r2, [sp, #4]
-     200:	1996      	adds	r6, r2, r6
-     202:	b2f6      	uxtb	r6, r6
-     204:	199b      	adds	r3, r3, r6
-     206:	b2db      	uxtb	r3, r3
-     208:	9303      	str	r3, [sp, #12]
-     20a:	9b01      	ldr	r3, [sp, #4]
-     20c:	1af0      	subs	r0, r6, r3
-     20e:	9b03      	ldr	r3, [sp, #12]
-     210:	b2c0      	uxtb	r0, r0
-     212:	42b3      	cmp	r3, r6
-     214:	d81b      	bhi.n	24e <adc_init+0xb6>
-     216:	89e0      	ldrh	r0, [r4, #14]
-     218:	4b91      	ldr	r3, [pc, #580]	; (460 <adc_init+0x2c8>)
-     21a:	4798      	blx	r3
-     21c:	7d63      	ldrb	r3, [r4, #21]
-     21e:	009b      	lsls	r3, r3, #2
-     220:	b2db      	uxtb	r3, r3
-     222:	702b      	strb	r3, [r5, #0]
-     224:	7da3      	ldrb	r3, [r4, #22]
-     226:	7862      	ldrb	r2, [r4, #1]
-     228:	01db      	lsls	r3, r3, #7
-     22a:	4313      	orrs	r3, r2
-     22c:	b2db      	uxtb	r3, r3
-     22e:	706b      	strb	r3, [r5, #1]
-     230:	7923      	ldrb	r3, [r4, #4]
-     232:	2b30      	cmp	r3, #48	; 0x30
-     234:	d100      	bne.n	238 <adc_init+0xa0>
-     236:	e0b4      	b.n	3a2 <adc_init+0x20a>
-     238:	d818      	bhi.n	26c <adc_init+0xd4>
-     23a:	2b10      	cmp	r3, #16
-     23c:	d100      	bne.n	240 <adc_init+0xa8>
-     23e:	e0ad      	b.n	39c <adc_init+0x204>
-     240:	2b20      	cmp	r3, #32
-     242:	d100      	bne.n	246 <adc_init+0xae>
-     244:	e0ad      	b.n	3a2 <adc_init+0x20a>
-     246:	2b00      	cmp	r3, #0
-     248:	d11a      	bne.n	280 <adc_init+0xe8>
-     24a:	001a      	movs	r2, r3
-     24c:	e0a7      	b.n	39e <adc_init+0x206>
-     24e:	230f      	movs	r3, #15
-     250:	4018      	ands	r0, r3
-     252:	7b23      	ldrb	r3, [r4, #12]
-     254:	3601      	adds	r6, #1
-     256:	18c0      	adds	r0, r0, r3
-     258:	4b81      	ldr	r3, [pc, #516]	; (460 <adc_init+0x2c8>)
-     25a:	4798      	blx	r3
-     25c:	b2f6      	uxtb	r6, r6
-     25e:	e7d4      	b.n	20a <adc_init+0x72>
-     260:	9801      	ldr	r0, [sp, #4]
-     262:	4e7f      	ldr	r6, [pc, #508]	; (460 <adc_init+0x2c8>)
-     264:	47b0      	blx	r6
-     266:	89e0      	ldrh	r0, [r4, #14]
-     268:	47b0      	blx	r6
-     26a:	e7d7      	b.n	21c <adc_init+0x84>
-     26c:	2b32      	cmp	r3, #50	; 0x32
-     26e:	d009      	beq.n	284 <adc_init+0xec>
-     270:	d200      	bcs.n	274 <adc_init+0xdc>
-     272:	e098      	b.n	3a6 <adc_init+0x20e>
-     274:	2b33      	cmp	r3, #51	; 0x33
-     276:	d100      	bne.n	27a <adc_init+0xe2>
-     278:	e08c      	b.n	394 <adc_init+0x1fc>
-     27a:	2b34      	cmp	r3, #52	; 0x34
-     27c:	d100      	bne.n	280 <adc_init+0xe8>
-     27e:	e085      	b.n	38c <adc_init+0x1f4>
-     280:	2017      	movs	r0, #23
-     282:	e081      	b.n	388 <adc_init+0x1f0>
-     284:	2204      	movs	r2, #4
-     286:	2310      	movs	r3, #16
-     288:	2102      	movs	r1, #2
-     28a:	2070      	movs	r0, #112	; 0x70
-     28c:	0109      	lsls	r1, r1, #4
-     28e:	4001      	ands	r1, r0
-     290:	430a      	orrs	r2, r1
-     292:	70aa      	strb	r2, [r5, #2]
-     294:	7de2      	ldrb	r2, [r4, #23]
-     296:	2a3f      	cmp	r2, #63	; 0x3f
-     298:	d8f2      	bhi.n	280 <adc_init+0xe8>
-     29a:	70ea      	strb	r2, [r5, #3]
-     29c:	6839      	ldr	r1, [r7, #0]
-     29e:	7e4a      	ldrb	r2, [r1, #25]
-     2a0:	b252      	sxtb	r2, r2
-     2a2:	2a00      	cmp	r2, #0
-     2a4:	dbfb      	blt.n	29e <adc_init+0x106>
-     2a6:	8861      	ldrh	r1, [r4, #2]
-     2a8:	7ce2      	ldrb	r2, [r4, #19]
-     2aa:	430a      	orrs	r2, r1
-     2ac:	1d61      	adds	r1, r4, #5
-     2ae:	7fc8      	ldrb	r0, [r1, #31]
-     2b0:	00c0      	lsls	r0, r0, #3
-     2b2:	4302      	orrs	r2, r0
-     2b4:	7d20      	ldrb	r0, [r4, #20]
-     2b6:	0080      	lsls	r0, r0, #2
-     2b8:	4302      	orrs	r2, r0
-     2ba:	7ca0      	ldrb	r0, [r4, #18]
-     2bc:	0040      	lsls	r0, r0, #1
-     2be:	4302      	orrs	r2, r0
-     2c0:	431a      	orrs	r2, r3
-     2c2:	80aa      	strh	r2, [r5, #4]
-     2c4:	7e22      	ldrb	r2, [r4, #24]
-     2c6:	4694      	mov	ip, r2
-     2c8:	2a00      	cmp	r2, #0
-     2ca:	d007      	beq.n	2dc <adc_init+0x144>
-     2cc:	2b10      	cmp	r3, #16
-     2ce:	d100      	bne.n	2d2 <adc_init+0x13a>
-     2d0:	e0af      	b.n	432 <adc_init+0x29a>
-     2d2:	d900      	bls.n	2d6 <adc_init+0x13e>
-     2d4:	e069      	b.n	3aa <adc_init+0x212>
-     2d6:	2b00      	cmp	r3, #0
-     2d8:	d100      	bne.n	2dc <adc_init+0x144>
-     2da:	e09b      	b.n	414 <adc_init+0x27c>
-     2dc:	6838      	ldr	r0, [r7, #0]
-     2de:	7e43      	ldrb	r3, [r0, #25]
-     2e0:	b25b      	sxtb	r3, r3
-     2e2:	2b00      	cmp	r3, #0
-     2e4:	dbfb      	blt.n	2de <adc_init+0x146>
-     2e6:	4663      	mov	r3, ip
-     2e8:	722b      	strb	r3, [r5, #8]
-     2ea:	683a      	ldr	r2, [r7, #0]
-     2ec:	7e53      	ldrb	r3, [r2, #25]
-     2ee:	b25b      	sxtb	r3, r3
-     2f0:	2b00      	cmp	r3, #0
-     2f2:	dbfb      	blt.n	2ec <adc_init+0x154>
-     2f4:	8ba3      	ldrh	r3, [r4, #28]
-     2f6:	83ab      	strh	r3, [r5, #28]
-     2f8:	683a      	ldr	r2, [r7, #0]
-     2fa:	7e53      	ldrb	r3, [r2, #25]
-     2fc:	b25b      	sxtb	r3, r3
-     2fe:	2b00      	cmp	r3, #0
-     300:	dbfb      	blt.n	2fa <adc_init+0x162>
-     302:	8c23      	ldrh	r3, [r4, #32]
-     304:	842b      	strh	r3, [r5, #32]
-     306:	9b02      	ldr	r3, [sp, #8]
-     308:	781a      	ldrb	r2, [r3, #0]
-     30a:	2a00      	cmp	r2, #0
-     30c:	d003      	beq.n	316 <adc_init+0x17e>
-     30e:	3a01      	subs	r2, #1
-     310:	b2d2      	uxtb	r2, r2
-     312:	2a0f      	cmp	r2, #15
-     314:	d8b4      	bhi.n	280 <adc_init+0xe8>
-     316:	0023      	movs	r3, r4
-     318:	332b      	adds	r3, #43	; 0x2b
-     31a:	7818      	ldrb	r0, [r3, #0]
-     31c:	280f      	cmp	r0, #15
-     31e:	d8af      	bhi.n	280 <adc_init+0xe8>
-     320:	683e      	ldr	r6, [r7, #0]
-     322:	7e73      	ldrb	r3, [r6, #25]
-     324:	b25b      	sxtb	r3, r3
-     326:	2b00      	cmp	r3, #0
-     328:	dbfb      	blt.n	322 <adc_init+0x18a>
-     32a:	7b26      	ldrb	r6, [r4, #12]
-     32c:	89e3      	ldrh	r3, [r4, #14]
-     32e:	0500      	lsls	r0, r0, #20
-     330:	4333      	orrs	r3, r6
-     332:	68a6      	ldr	r6, [r4, #8]
-     334:	0412      	lsls	r2, r2, #16
-     336:	4333      	orrs	r3, r6
-     338:	4303      	orrs	r3, r0
-     33a:	4313      	orrs	r3, r2
-     33c:	612b      	str	r3, [r5, #16]
-     33e:	0023      	movs	r3, r4
-     340:	332a      	adds	r3, #42	; 0x2a
-     342:	781b      	ldrb	r3, [r3, #0]
-     344:	752b      	strb	r3, [r5, #20]
-     346:	230f      	movs	r3, #15
-     348:	75ab      	strb	r3, [r5, #22]
-     34a:	7fcb      	ldrb	r3, [r1, #31]
-     34c:	2b00      	cmp	r3, #0
-     34e:	d00c      	beq.n	36a <adc_init+0x1d2>
-     350:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
-     352:	4944      	ldr	r1, [pc, #272]	; (464 <adc_init+0x2cc>)
-     354:	428b      	cmp	r3, r1
-     356:	d893      	bhi.n	280 <adc_init+0xe8>
-     358:	84ab      	strh	r3, [r5, #36]	; 0x24
-     35a:	2380      	movs	r3, #128	; 0x80
-     35c:	8d22      	ldrh	r2, [r4, #40]	; 0x28
-     35e:	011b      	lsls	r3, r3, #4
-     360:	18d3      	adds	r3, r2, r3
-     362:	b29b      	uxth	r3, r3
-     364:	428b      	cmp	r3, r1
-     366:	d88b      	bhi.n	280 <adc_init+0xe8>
-     368:	84ea      	strh	r2, [r5, #38]	; 0x26
-     36a:	22e0      	movs	r2, #224	; 0xe0
-     36c:	4b3e      	ldr	r3, [pc, #248]	; (468 <adc_init+0x2d0>)
-     36e:	2000      	movs	r0, #0
-     370:	6819      	ldr	r1, [r3, #0]
-     372:	00d2      	lsls	r2, r2, #3
-     374:	014b      	lsls	r3, r1, #5
-     376:	0019      	movs	r1, r3
-     378:	401a      	ands	r2, r3
-     37a:	4b3c      	ldr	r3, [pc, #240]	; (46c <adc_init+0x2d4>)
-     37c:	681b      	ldr	r3, [r3, #0]
-     37e:	0edb      	lsrs	r3, r3, #27
-     380:	430b      	orrs	r3, r1
-     382:	b2db      	uxtb	r3, r3
-     384:	4313      	orrs	r3, r2
-     386:	852b      	strh	r3, [r5, #40]	; 0x28
-     388:	b007      	add	sp, #28
-     38a:	bdf0      	pop	{r4, r5, r6, r7, pc}
-     38c:	7c61      	ldrb	r1, [r4, #17]
-     38e:	7c22      	ldrb	r2, [r4, #16]
-     390:	2310      	movs	r3, #16
-     392:	e77a      	b.n	28a <adc_init+0xf2>
-     394:	2206      	movs	r2, #6
-     396:	2310      	movs	r3, #16
-     398:	2101      	movs	r1, #1
-     39a:	e776      	b.n	28a <adc_init+0xf2>
-     39c:	2208      	movs	r2, #8
-     39e:	2100      	movs	r1, #0
-     3a0:	e773      	b.n	28a <adc_init+0xf2>
-     3a2:	2200      	movs	r2, #0
-     3a4:	e7fb      	b.n	39e <adc_init+0x206>
-     3a6:	2202      	movs	r2, #2
-     3a8:	e7f5      	b.n	396 <adc_init+0x1fe>
-     3aa:	2b20      	cmp	r3, #32
-     3ac:	d018      	beq.n	3e0 <adc_init+0x248>
-     3ae:	2b30      	cmp	r3, #48	; 0x30
-     3b0:	d000      	beq.n	3b4 <adc_init+0x21c>
-     3b2:	e793      	b.n	2dc <adc_init+0x144>
-     3b4:	7ce3      	ldrb	r3, [r4, #19]
-     3b6:	69e0      	ldr	r0, [r4, #28]
-     3b8:	2b00      	cmp	r3, #0
-     3ba:	d009      	beq.n	3d0 <adc_init+0x238>
-     3bc:	0003      	movs	r3, r0
-     3be:	3380      	adds	r3, #128	; 0x80
-     3c0:	2bff      	cmp	r3, #255	; 0xff
-     3c2:	d900      	bls.n	3c6 <adc_init+0x22e>
-     3c4:	e75c      	b.n	280 <adc_init+0xe8>
-     3c6:	6a23      	ldr	r3, [r4, #32]
-     3c8:	3380      	adds	r3, #128	; 0x80
-     3ca:	2bff      	cmp	r3, #255	; 0xff
-     3cc:	d900      	bls.n	3d0 <adc_init+0x238>
-     3ce:	e757      	b.n	280 <adc_init+0xe8>
-     3d0:	28ff      	cmp	r0, #255	; 0xff
-     3d2:	dd00      	ble.n	3d6 <adc_init+0x23e>
-     3d4:	e754      	b.n	280 <adc_init+0xe8>
-     3d6:	6a23      	ldr	r3, [r4, #32]
-     3d8:	2bff      	cmp	r3, #255	; 0xff
-     3da:	dd00      	ble.n	3de <adc_init+0x246>
-     3dc:	e750      	b.n	280 <adc_init+0xe8>
-     3de:	e77d      	b.n	2dc <adc_init+0x144>
-     3e0:	7ce0      	ldrb	r0, [r4, #19]
-     3e2:	69e6      	ldr	r6, [r4, #28]
-     3e4:	4b22      	ldr	r3, [pc, #136]	; (470 <adc_init+0x2d8>)
-     3e6:	2800      	cmp	r0, #0
-     3e8:	d00c      	beq.n	404 <adc_init+0x26c>
-     3ea:	2080      	movs	r0, #128	; 0x80
-     3ec:	0080      	lsls	r0, r0, #2
-     3ee:	1830      	adds	r0, r6, r0
-     3f0:	4298      	cmp	r0, r3
-     3f2:	d900      	bls.n	3f6 <adc_init+0x25e>
-     3f4:	e744      	b.n	280 <adc_init+0xe8>
-     3f6:	2280      	movs	r2, #128	; 0x80
-     3f8:	6a20      	ldr	r0, [r4, #32]
-     3fa:	0092      	lsls	r2, r2, #2
-     3fc:	1810      	adds	r0, r2, r0
-     3fe:	4298      	cmp	r0, r3
-     400:	d900      	bls.n	404 <adc_init+0x26c>
-     402:	e73d      	b.n	280 <adc_init+0xe8>
-     404:	429e      	cmp	r6, r3
-     406:	dd00      	ble.n	40a <adc_init+0x272>
-     408:	e73a      	b.n	280 <adc_init+0xe8>
-     40a:	6a22      	ldr	r2, [r4, #32]
-     40c:	429a      	cmp	r2, r3
-     40e:	dd00      	ble.n	412 <adc_init+0x27a>
-     410:	e736      	b.n	280 <adc_init+0xe8>
-     412:	e763      	b.n	2dc <adc_init+0x144>
-     414:	7ce0      	ldrb	r0, [r4, #19]
-     416:	69e6      	ldr	r6, [r4, #28]
-     418:	4b12      	ldr	r3, [pc, #72]	; (464 <adc_init+0x2cc>)
-     41a:	2800      	cmp	r0, #0
-     41c:	d0f2      	beq.n	404 <adc_init+0x26c>
-     41e:	2280      	movs	r2, #128	; 0x80
-     420:	0112      	lsls	r2, r2, #4
-     422:	18b0      	adds	r0, r6, r2
-     424:	4298      	cmp	r0, r3
-     426:	d900      	bls.n	42a <adc_init+0x292>
-     428:	e72a      	b.n	280 <adc_init+0xe8>
-     42a:	2080      	movs	r0, #128	; 0x80
-     42c:	6a22      	ldr	r2, [r4, #32]
-     42e:	0100      	lsls	r0, r0, #4
-     430:	e7e4      	b.n	3fc <adc_init+0x264>
-     432:	7ce0      	ldrb	r0, [r4, #19]
-     434:	69e6      	ldr	r6, [r4, #28]
-     436:	4b0f      	ldr	r3, [pc, #60]	; (474 <adc_init+0x2dc>)
-     438:	2800      	cmp	r0, #0
-     43a:	d0e3      	beq.n	404 <adc_init+0x26c>
-     43c:	2280      	movs	r2, #128	; 0x80
-     43e:	0212      	lsls	r2, r2, #8
-     440:	18b0      	adds	r0, r6, r2
-     442:	4298      	cmp	r0, r3
-     444:	d900      	bls.n	448 <adc_init+0x2b0>
-     446:	e71b      	b.n	280 <adc_init+0xe8>
-     448:	2080      	movs	r0, #128	; 0x80
-     44a:	6a22      	ldr	r2, [r4, #32]
-     44c:	0200      	lsls	r0, r0, #8
-     44e:	e7d5      	b.n	3fc <adc_init+0x264>
-     450:	40000400 	.word	0x40000400
-     454:	40000800 	.word	0x40000800
-     458:	0000184d 	.word	0x0000184d
-     45c:	000017c5 	.word	0x000017c5
-     460:	00000115 	.word	0x00000115
-     464:	00000fff 	.word	0x00000fff
-     468:	00806024 	.word	0x00806024
-     46c:	00806020 	.word	0x00806020
-     470:	000003ff 	.word	0x000003ff
-     474:	0000ffff 	.word	0x0000ffff
-
-00000478 <DMAC_Handler>:
-     478:	b570      	push	{r4, r5, r6, lr}
-     47a:	4b20      	ldr	r3, [pc, #128]	; (4fc <DMAC_Handler+0x84>)
-     47c:	4798      	blx	r3
-     47e:	220f      	movs	r2, #15
-     480:	4b1f      	ldr	r3, [pc, #124]	; (500 <DMAC_Handler+0x88>)
-     482:	4920      	ldr	r1, [pc, #128]	; (504 <DMAC_Handler+0x8c>)
-     484:	8c1b      	ldrh	r3, [r3, #32]
-     486:	4c20      	ldr	r4, [pc, #128]	; (508 <DMAC_Handler+0x90>)
-     488:	4013      	ands	r3, r2
-     48a:	009b      	lsls	r3, r3, #2
-     48c:	5858      	ldr	r0, [r3, r1]
-     48e:	4d1f      	ldr	r5, [pc, #124]	; (50c <DMAC_Handler+0x94>)
-     490:	7803      	ldrb	r3, [r0, #0]
-     492:	4013      	ands	r3, r2
-     494:	4a1e      	ldr	r2, [pc, #120]	; (510 <DMAC_Handler+0x98>)
-     496:	7013      	strb	r3, [r2, #0]
-     498:	7801      	ldrb	r1, [r0, #0]
-     49a:	4a1e      	ldr	r2, [pc, #120]	; (514 <DMAC_Handler+0x9c>)
-     49c:	0109      	lsls	r1, r1, #4
-     49e:	1864      	adds	r4, r4, r1
-     4a0:	1869      	adds	r1, r5, r1
-     4a2:	7813      	ldrb	r3, [r2, #0]
-     4a4:	8864      	ldrh	r4, [r4, #2]
-     4a6:	8849      	ldrh	r1, [r1, #2]
-     4a8:	b2db      	uxtb	r3, r3
-     4aa:	1a61      	subs	r1, r4, r1
-     4ac:	6141      	str	r1, [r0, #20]
-     4ae:	001c      	movs	r4, r3
-     4b0:	2101      	movs	r1, #1
-     4b2:	400c      	ands	r4, r1
-     4b4:	d00c      	beq.n	4d0 <DMAC_Handler+0x58>
-     4b6:	2310      	movs	r3, #16
-     4b8:	7011      	strb	r1, [r2, #0]
-     4ba:	7443      	strb	r3, [r0, #17]
-     4bc:	7c03      	ldrb	r3, [r0, #16]
-     4be:	420b      	tst	r3, r1
-     4c0:	d003      	beq.n	4ca <DMAC_Handler+0x52>
-     4c2:	6843      	ldr	r3, [r0, #4]
-     4c4:	2b00      	cmp	r3, #0
-     4c6:	d000      	beq.n	4ca <DMAC_Handler+0x52>
-     4c8:	4798      	blx	r3
-     4ca:	4b13      	ldr	r3, [pc, #76]	; (518 <DMAC_Handler+0xa0>)
-     4cc:	4798      	blx	r3
-     4ce:	bd70      	pop	{r4, r5, r6, pc}
-     4d0:	2102      	movs	r1, #2
-     4d2:	420b      	tst	r3, r1
-     4d4:	d006      	beq.n	4e4 <DMAC_Handler+0x6c>
-     4d6:	7011      	strb	r1, [r2, #0]
-     4d8:	7c03      	ldrb	r3, [r0, #16]
-     4da:	7444      	strb	r4, [r0, #17]
-     4dc:	420b      	tst	r3, r1
-     4de:	d0f4      	beq.n	4ca <DMAC_Handler+0x52>
-     4e0:	6883      	ldr	r3, [r0, #8]
-     4e2:	e7ef      	b.n	4c4 <DMAC_Handler+0x4c>
-     4e4:	2104      	movs	r1, #4
-     4e6:	420b      	tst	r3, r1
-     4e8:	d0ef      	beq.n	4ca <DMAC_Handler+0x52>
-     4ea:	2306      	movs	r3, #6
-     4ec:	7011      	strb	r1, [r2, #0]
-     4ee:	7443      	strb	r3, [r0, #17]
-     4f0:	7c03      	ldrb	r3, [r0, #16]
-     4f2:	420b      	tst	r3, r1
-     4f4:	d0e9      	beq.n	4ca <DMAC_Handler+0x52>
-     4f6:	68c3      	ldr	r3, [r0, #12]
-     4f8:	e7e4      	b.n	4c4 <DMAC_Handler+0x4c>
-     4fa:	46c0      	nop			; (mov r8, r8)
-     4fc:	00001379 	.word	0x00001379
-     500:	41004800 	.word	0x41004800
-     504:	2000009c 	.word	0x2000009c
-     508:	200001e0 	.word	0x200001e0
-     50c:	200000b0 	.word	0x200000b0
-     510:	4100483f 	.word	0x4100483f
-     514:	4100484e 	.word	0x4100484e
-     518:	000013ad 	.word	0x000013ad
-
-0000051c <dma_get_config_defaults>:
-     51c:	2300      	movs	r3, #0
-     51e:	2203      	movs	r2, #3
-     520:	7003      	strb	r3, [r0, #0]
-     522:	7043      	strb	r3, [r0, #1]
-     524:	7082      	strb	r2, [r0, #2]
-     526:	70c3      	strb	r3, [r0, #3]
-     528:	7103      	strb	r3, [r0, #4]
-     52a:	4770      	bx	lr
-
-0000052c <dma_allocate>:
-     52c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-     52e:	4b3f      	ldr	r3, [pc, #252]	; (62c <dma_allocate+0x100>)
-     530:	0005      	movs	r5, r0
-     532:	000e      	movs	r6, r1
-     534:	4798      	blx	r3
-     536:	4f3e      	ldr	r7, [pc, #248]	; (630 <dma_allocate+0x104>)
-     538:	783b      	ldrb	r3, [r7, #0]
-     53a:	2b00      	cmp	r3, #0
-     53c:	d116      	bne.n	56c <dma_allocate+0x40>
-     53e:	2220      	movs	r2, #32
-     540:	4b3c      	ldr	r3, [pc, #240]	; (634 <dma_allocate+0x108>)
-     542:	6959      	ldr	r1, [r3, #20]
-     544:	430a      	orrs	r2, r1
-     546:	615a      	str	r2, [r3, #20]
-     548:	2210      	movs	r2, #16
-     54a:	69d9      	ldr	r1, [r3, #28]
-     54c:	430a      	orrs	r2, r1
-     54e:	2102      	movs	r1, #2
-     550:	61da      	str	r2, [r3, #28]
-     552:	4b39      	ldr	r3, [pc, #228]	; (638 <dma_allocate+0x10c>)
-     554:	881a      	ldrh	r2, [r3, #0]
-     556:	438a      	bics	r2, r1
-     558:	801a      	strh	r2, [r3, #0]
-     55a:	2201      	movs	r2, #1
-     55c:	4937      	ldr	r1, [pc, #220]	; (63c <dma_allocate+0x110>)
-     55e:	801a      	strh	r2, [r3, #0]
-     560:	6359      	str	r1, [r3, #52]	; 0x34
-     562:	4937      	ldr	r1, [pc, #220]	; (640 <dma_allocate+0x114>)
-     564:	6399      	str	r1, [r3, #56]	; 0x38
-     566:	4937      	ldr	r1, [pc, #220]	; (644 <dma_allocate+0x118>)
-     568:	8019      	strh	r1, [r3, #0]
-     56a:	703a      	strb	r2, [r7, #0]
-     56c:	4b2f      	ldr	r3, [pc, #188]	; (62c <dma_allocate+0x100>)
-     56e:	4798      	blx	r3
-     570:	2400      	movs	r4, #0
-     572:	2301      	movs	r3, #1
-     574:	687a      	ldr	r2, [r7, #4]
-     576:	421a      	tst	r2, r3
-     578:	d14c      	bne.n	614 <dma_allocate+0xe8>
-     57a:	40a3      	lsls	r3, r4
-     57c:	687a      	ldr	r2, [r7, #4]
-     57e:	4313      	orrs	r3, r2
-     580:	607b      	str	r3, [r7, #4]
-     582:	7a3b      	ldrb	r3, [r7, #8]
-     584:	3b01      	subs	r3, #1
-     586:	723b      	strb	r3, [r7, #8]
-     588:	2701      	movs	r7, #1
-     58a:	4b2f      	ldr	r3, [pc, #188]	; (648 <dma_allocate+0x11c>)
-     58c:	4798      	blx	r3
-     58e:	2f00      	cmp	r7, #0
-     590:	d047      	beq.n	622 <dma_allocate+0xf6>
-     592:	4b2e      	ldr	r3, [pc, #184]	; (64c <dma_allocate+0x120>)
-     594:	2102      	movs	r1, #2
-     596:	702c      	strb	r4, [r5, #0]
-     598:	701c      	strb	r4, [r3, #0]
-     59a:	2401      	movs	r4, #1
-     59c:	4b2c      	ldr	r3, [pc, #176]	; (650 <dma_allocate+0x124>)
-     59e:	4f26      	ldr	r7, [pc, #152]	; (638 <dma_allocate+0x10c>)
-     5a0:	781a      	ldrb	r2, [r3, #0]
-     5a2:	438a      	bics	r2, r1
-     5a4:	701a      	strb	r2, [r3, #0]
-     5a6:	701c      	strb	r4, [r3, #0]
-     5a8:	4b20      	ldr	r3, [pc, #128]	; (62c <dma_allocate+0x100>)
-     5aa:	4798      	blx	r3
-     5ac:	220f      	movs	r2, #15
-     5ae:	782b      	ldrb	r3, [r5, #0]
-     5b0:	21fc      	movs	r1, #252	; 0xfc
-     5b2:	4013      	ands	r3, r2
-     5b4:	4a25      	ldr	r2, [pc, #148]	; (64c <dma_allocate+0x120>)
-     5b6:	0189      	lsls	r1, r1, #6
-     5b8:	7013      	strb	r3, [r2, #0]
-     5ba:	782a      	ldrb	r2, [r5, #0]
-     5bc:	693b      	ldr	r3, [r7, #16]
-     5be:	4094      	lsls	r4, r2
-     5c0:	2260      	movs	r2, #96	; 0x60
-     5c2:	43a3      	bics	r3, r4
-     5c4:	613b      	str	r3, [r7, #16]
-     5c6:	7833      	ldrb	r3, [r6, #0]
-     5c8:	015b      	lsls	r3, r3, #5
-     5ca:	4013      	ands	r3, r2
-     5cc:	7872      	ldrb	r2, [r6, #1]
-     5ce:	0212      	lsls	r2, r2, #8
-     5d0:	400a      	ands	r2, r1
-     5d2:	21c0      	movs	r1, #192	; 0xc0
-     5d4:	4313      	orrs	r3, r2
-     5d6:	78b2      	ldrb	r2, [r6, #2]
-     5d8:	0409      	lsls	r1, r1, #16
-     5da:	0592      	lsls	r2, r2, #22
-     5dc:	400a      	ands	r2, r1
-     5de:	4313      	orrs	r3, r2
-     5e0:	78f2      	ldrb	r2, [r6, #3]
-     5e2:	2a00      	cmp	r2, #0
-     5e4:	d004      	beq.n	5f0 <dma_allocate+0xc4>
-     5e6:	2107      	movs	r1, #7
-     5e8:	400a      	ands	r2, r1
-     5ea:	3101      	adds	r1, #1
-     5ec:	430a      	orrs	r2, r1
-     5ee:	4313      	orrs	r3, r2
-     5f0:	7932      	ldrb	r2, [r6, #4]
-     5f2:	2a00      	cmp	r2, #0
-     5f4:	d001      	beq.n	5fa <dma_allocate+0xce>
-     5f6:	2210      	movs	r2, #16
-     5f8:	4313      	orrs	r3, r2
-     5fa:	2400      	movs	r4, #0
-     5fc:	647b      	str	r3, [r7, #68]	; 0x44
-     5fe:	4b12      	ldr	r3, [pc, #72]	; (648 <dma_allocate+0x11c>)
-     600:	4798      	blx	r3
-     602:	782b      	ldrb	r3, [r5, #0]
-     604:	4a13      	ldr	r2, [pc, #76]	; (654 <dma_allocate+0x128>)
-     606:	009b      	lsls	r3, r3, #2
-     608:	509d      	str	r5, [r3, r2]
-     60a:	61ac      	str	r4, [r5, #24]
-     60c:	4b0e      	ldr	r3, [pc, #56]	; (648 <dma_allocate+0x11c>)
-     60e:	4798      	blx	r3
-     610:	0020      	movs	r0, r4
-     612:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-     614:	3401      	adds	r4, #1
-     616:	b2e4      	uxtb	r4, r4
-     618:	0852      	lsrs	r2, r2, #1
-     61a:	2c05      	cmp	r4, #5
-     61c:	d1ab      	bne.n	576 <dma_allocate+0x4a>
-     61e:	2700      	movs	r7, #0
-     620:	e7b3      	b.n	58a <dma_allocate+0x5e>
-     622:	4b09      	ldr	r3, [pc, #36]	; (648 <dma_allocate+0x11c>)
-     624:	4798      	blx	r3
-     626:	2014      	movs	r0, #20
-     628:	e7f3      	b.n	612 <dma_allocate+0xe6>
-     62a:	46c0      	nop			; (mov r8, r8)
-     62c:	00001379 	.word	0x00001379
-     630:	20000000 	.word	0x20000000
-     634:	40000400 	.word	0x40000400
-     638:	41004800 	.word	0x41004800
-     63c:	200001e0 	.word	0x200001e0
-     640:	200000b0 	.word	0x200000b0
-     644:	00000f02 	.word	0x00000f02
-     648:	000013ad 	.word	0x000013ad
-     64c:	4100483f 	.word	0x4100483f
-     650:	41004840 	.word	0x41004840
-     654:	2000009c 	.word	0x2000009c
-
-00000658 <dma_start_transfer_job>:
-     658:	b570      	push	{r4, r5, r6, lr}
-     65a:	0005      	movs	r5, r0
-     65c:	4b18      	ldr	r3, [pc, #96]	; (6c0 <dma_start_transfer_job+0x68>)
-     65e:	4798      	blx	r3
-     660:	7c6c      	ldrb	r4, [r5, #17]
-     662:	4e18      	ldr	r6, [pc, #96]	; (6c4 <dma_start_transfer_job+0x6c>)
-     664:	b2e4      	uxtb	r4, r4
-     666:	2c05      	cmp	r4, #5
-     668:	d102      	bne.n	670 <dma_start_transfer_job+0x18>
-     66a:	47b0      	blx	r6
-     66c:	0020      	movs	r0, r4
-     66e:	bd70      	pop	{r4, r5, r6, pc}
-     670:	69ab      	ldr	r3, [r5, #24]
-     672:	885b      	ldrh	r3, [r3, #2]
-     674:	2b00      	cmp	r3, #0
-     676:	d102      	bne.n	67e <dma_start_transfer_job+0x26>
-     678:	47b0      	blx	r6
-     67a:	2017      	movs	r0, #23
-     67c:	e7f7      	b.n	66e <dma_start_transfer_job+0x16>
-     67e:	2240      	movs	r2, #64	; 0x40
-     680:	4b11      	ldr	r3, [pc, #68]	; (6c8 <dma_start_transfer_job+0x70>)
-     682:	601a      	str	r2, [r3, #0]
-     684:	782b      	ldrb	r3, [r5, #0]
-     686:	3a31      	subs	r2, #49	; 0x31
-     688:	4013      	ands	r3, r2
-     68a:	4a10      	ldr	r2, [pc, #64]	; (6cc <dma_start_transfer_job+0x74>)
-     68c:	7013      	strb	r3, [r2, #0]
-     68e:	782b      	ldrb	r3, [r5, #0]
-     690:	4a0f      	ldr	r2, [pc, #60]	; (6d0 <dma_start_transfer_job+0x78>)
-     692:	5cd3      	ldrb	r3, [r2, r3]
-     694:	2207      	movs	r2, #7
-     696:	4013      	ands	r3, r2
-     698:	4a0e      	ldr	r2, [pc, #56]	; (6d4 <dma_start_transfer_job+0x7c>)
-     69a:	7013      	strb	r3, [r2, #0]
-     69c:	2305      	movs	r3, #5
-     69e:	7828      	ldrb	r0, [r5, #0]
-     6a0:	746b      	strb	r3, [r5, #17]
-     6a2:	4b0d      	ldr	r3, [pc, #52]	; (6d8 <dma_start_transfer_job+0x80>)
-     6a4:	0100      	lsls	r0, r0, #4
-     6a6:	18c0      	adds	r0, r0, r3
-     6a8:	69a9      	ldr	r1, [r5, #24]
-     6aa:	2210      	movs	r2, #16
-     6ac:	4b0b      	ldr	r3, [pc, #44]	; (6dc <dma_start_transfer_job+0x84>)
-     6ae:	4798      	blx	r3
-     6b0:	2302      	movs	r3, #2
-     6b2:	4a0b      	ldr	r2, [pc, #44]	; (6e0 <dma_start_transfer_job+0x88>)
-     6b4:	7811      	ldrb	r1, [r2, #0]
-     6b6:	430b      	orrs	r3, r1
-     6b8:	7013      	strb	r3, [r2, #0]
-     6ba:	47b0      	blx	r6
-     6bc:	2000      	movs	r0, #0
-     6be:	e7d6      	b.n	66e <dma_start_transfer_job+0x16>
-     6c0:	00001379 	.word	0x00001379
-     6c4:	000013ad 	.word	0x000013ad
-     6c8:	e000e100 	.word	0xe000e100
-     6cc:	4100483f 	.word	0x4100483f
-     6d0:	20000100 	.word	0x20000100
-     6d4:	4100484d 	.word	0x4100484d
-     6d8:	200001e0 	.word	0x200001e0
-     6dc:	00002449 	.word	0x00002449
-     6e0:	41004840 	.word	0x41004840
-
-000006e4 <dma_descriptor_create>:
-     6e4:	b570      	push	{r4, r5, r6, lr}
-     6e6:	2401      	movs	r4, #1
-     6e8:	2603      	movs	r6, #3
-     6ea:	8803      	ldrh	r3, [r0, #0]
-     6ec:	780a      	ldrb	r2, [r1, #0]
-     6ee:	43a3      	bics	r3, r4
-     6f0:	4022      	ands	r2, r4
-     6f2:	4313      	orrs	r3, r2
-     6f4:	8003      	strh	r3, [r0, #0]
-     6f6:	784a      	ldrb	r2, [r1, #1]
-     6f8:	2506      	movs	r5, #6
-     6fa:	4032      	ands	r2, r6
-     6fc:	40a2      	lsls	r2, r4
-     6fe:	8803      	ldrh	r3, [r0, #0]
-     700:	43ab      	bics	r3, r5
-     702:	4313      	orrs	r3, r2
-     704:	8003      	strh	r3, [r0, #0]
-     706:	788b      	ldrb	r3, [r1, #2]
-     708:	2218      	movs	r2, #24
-     70a:	4033      	ands	r3, r6
-     70c:	40b3      	lsls	r3, r6
-     70e:	8805      	ldrh	r5, [r0, #0]
-     710:	4395      	bics	r5, r2
-     712:	431d      	orrs	r5, r3
-     714:	8005      	strh	r5, [r0, #0]
-     716:	78ca      	ldrb	r2, [r1, #3]
-     718:	8803      	ldrh	r3, [r0, #0]
-     71a:	4d18      	ldr	r5, [pc, #96]	; (77c <dma_descriptor_create+0x98>)
-     71c:	4032      	ands	r2, r6
-     71e:	0212      	lsls	r2, r2, #8
-     720:	402b      	ands	r3, r5
-     722:	4313      	orrs	r3, r2
-     724:	8003      	strh	r3, [r0, #0]
-     726:	790a      	ldrb	r2, [r1, #4]
-     728:	8803      	ldrh	r3, [r0, #0]
-     72a:	4d15      	ldr	r5, [pc, #84]	; (780 <dma_descriptor_create+0x9c>)
-     72c:	4022      	ands	r2, r4
-     72e:	0292      	lsls	r2, r2, #10
-     730:	402b      	ands	r3, r5
-     732:	4313      	orrs	r3, r2
-     734:	8003      	strh	r3, [r0, #0]
-     736:	794a      	ldrb	r2, [r1, #5]
-     738:	8803      	ldrh	r3, [r0, #0]
-     73a:	4d12      	ldr	r5, [pc, #72]	; (784 <dma_descriptor_create+0xa0>)
-     73c:	4022      	ands	r2, r4
-     73e:	402b      	ands	r3, r5
-     740:	02d2      	lsls	r2, r2, #11
-     742:	4313      	orrs	r3, r2
-     744:	8003      	strh	r3, [r0, #0]
-     746:	798a      	ldrb	r2, [r1, #6]
-     748:	8803      	ldrh	r3, [r0, #0]
-     74a:	4022      	ands	r2, r4
-     74c:	4c0e      	ldr	r4, [pc, #56]	; (788 <dma_descriptor_create+0xa4>)
-     74e:	0312      	lsls	r2, r2, #12
-     750:	4023      	ands	r3, r4
-     752:	4313      	orrs	r3, r2
-     754:	8003      	strh	r3, [r0, #0]
-     756:	2307      	movs	r3, #7
-     758:	79ca      	ldrb	r2, [r1, #7]
-     75a:	401a      	ands	r2, r3
-     75c:	8803      	ldrh	r3, [r0, #0]
-     75e:	0352      	lsls	r2, r2, #13
-     760:	04db      	lsls	r3, r3, #19
-     762:	0cdb      	lsrs	r3, r3, #19
-     764:	4313      	orrs	r3, r2
-     766:	8003      	strh	r3, [r0, #0]
-     768:	890b      	ldrh	r3, [r1, #8]
-     76a:	8043      	strh	r3, [r0, #2]
-     76c:	68cb      	ldr	r3, [r1, #12]
-     76e:	6043      	str	r3, [r0, #4]
-     770:	690b      	ldr	r3, [r1, #16]
-     772:	6083      	str	r3, [r0, #8]
-     774:	694b      	ldr	r3, [r1, #20]
-     776:	60c3      	str	r3, [r0, #12]
-     778:	bd70      	pop	{r4, r5, r6, pc}
-     77a:	46c0      	nop			; (mov r8, r8)
-     77c:	fffffcff 	.word	0xfffffcff
-     780:	fffffbff 	.word	0xfffffbff
-     784:	fffff7ff 	.word	0xfffff7ff
-     788:	ffffefff 	.word	0xffffefff
-
-0000078c <dma_add_descriptor>:
-     78c:	0002      	movs	r2, r0
-     78e:	7c43      	ldrb	r3, [r0, #17]
-     790:	2005      	movs	r0, #5
-     792:	4283      	cmp	r3, r0
-     794:	d004      	beq.n	7a0 <dma_add_descriptor+0x14>
-     796:	6993      	ldr	r3, [r2, #24]
-     798:	2b00      	cmp	r3, #0
-     79a:	d103      	bne.n	7a4 <dma_add_descriptor+0x18>
-     79c:	0018      	movs	r0, r3
-     79e:	6191      	str	r1, [r2, #24]
-     7a0:	4770      	bx	lr
-     7a2:	68db      	ldr	r3, [r3, #12]
-     7a4:	68d8      	ldr	r0, [r3, #12]
-     7a6:	2800      	cmp	r0, #0
-     7a8:	d1fb      	bne.n	7a2 <dma_add_descriptor+0x16>
-     7aa:	60d9      	str	r1, [r3, #12]
-     7ac:	e7f8      	b.n	7a0 <dma_add_descriptor+0x14>
-	...
-
-000007b0 <long_division>:
-     7b0:	b5f0      	push	{r4, r5, r6, r7, lr}
-     7b2:	2400      	movs	r4, #0
-     7b4:	b089      	sub	sp, #36	; 0x24
-     7b6:	9200      	str	r2, [sp, #0]
-     7b8:	9301      	str	r3, [sp, #4]
-     7ba:	233f      	movs	r3, #63	; 0x3f
-     7bc:	2600      	movs	r6, #0
-     7be:	2700      	movs	r7, #0
-     7c0:	0025      	movs	r5, r4
-     7c2:	9006      	str	r0, [sp, #24]
-     7c4:	9107      	str	r1, [sp, #28]
-     7c6:	9303      	str	r3, [sp, #12]
-     7c8:	9a03      	ldr	r2, [sp, #12]
-     7ca:	4b13      	ldr	r3, [pc, #76]	; (818 <long_division+0x68>)
-     7cc:	2001      	movs	r0, #1
-     7ce:	2100      	movs	r1, #0
-     7d0:	4798      	blx	r3
-     7d2:	19b6      	adds	r6, r6, r6
-     7d4:	417f      	adcs	r7, r7
-     7d6:	9b06      	ldr	r3, [sp, #24]
-     7d8:	9a07      	ldr	r2, [sp, #28]
-     7da:	4003      	ands	r3, r0
-     7dc:	400a      	ands	r2, r1
-     7de:	9604      	str	r6, [sp, #16]
-     7e0:	9705      	str	r7, [sp, #20]
-     7e2:	4313      	orrs	r3, r2
-     7e4:	d003      	beq.n	7ee <long_division+0x3e>
-     7e6:	2301      	movs	r3, #1
-     7e8:	4333      	orrs	r3, r6
-     7ea:	001e      	movs	r6, r3
-     7ec:	9f05      	ldr	r7, [sp, #20]
-     7ee:	9b01      	ldr	r3, [sp, #4]
-     7f0:	42bb      	cmp	r3, r7
-     7f2:	d809      	bhi.n	808 <long_division+0x58>
-     7f4:	d102      	bne.n	7fc <long_division+0x4c>
-     7f6:	9b00      	ldr	r3, [sp, #0]
-     7f8:	42b3      	cmp	r3, r6
-     7fa:	d805      	bhi.n	808 <long_division+0x58>
-     7fc:	9a00      	ldr	r2, [sp, #0]
-     7fe:	9b01      	ldr	r3, [sp, #4]
-     800:	1ab6      	subs	r6, r6, r2
-     802:	419f      	sbcs	r7, r3
-     804:	4304      	orrs	r4, r0
-     806:	430d      	orrs	r5, r1
-     808:	9b03      	ldr	r3, [sp, #12]
-     80a:	1e5a      	subs	r2, r3, #1
-     80c:	9203      	str	r2, [sp, #12]
-     80e:	d2db      	bcs.n	7c8 <long_division+0x18>
-     810:	0020      	movs	r0, r4
-     812:	0029      	movs	r1, r5
-     814:	b009      	add	sp, #36	; 0x24
-     816:	bdf0      	pop	{r4, r5, r6, r7, pc}
-     818:	00001c75 	.word	0x00001c75
-
-0000081c <_sercom_get_sync_baud_val>:
-     81c:	b510      	push	{r4, lr}
-     81e:	0849      	lsrs	r1, r1, #1
-     820:	0004      	movs	r4, r0
-     822:	2300      	movs	r3, #0
-     824:	2040      	movs	r0, #64	; 0x40
-     826:	42a1      	cmp	r1, r4
-     828:	d201      	bcs.n	82e <_sercom_get_sync_baud_val+0x12>
-     82a:	bd10      	pop	{r4, pc}
-     82c:	0003      	movs	r3, r0
-     82e:	1c58      	adds	r0, r3, #1
-     830:	1b09      	subs	r1, r1, r4
-     832:	b280      	uxth	r0, r0
-     834:	428c      	cmp	r4, r1
-     836:	d9f9      	bls.n	82c <_sercom_get_sync_baud_val+0x10>
-     838:	2040      	movs	r0, #64	; 0x40
-     83a:	2bff      	cmp	r3, #255	; 0xff
-     83c:	d8f5      	bhi.n	82a <_sercom_get_sync_baud_val+0xe>
-     83e:	8013      	strh	r3, [r2, #0]
-     840:	2000      	movs	r0, #0
-     842:	e7f2      	b.n	82a <_sercom_get_sync_baud_val+0xe>
-
-00000844 <_sercom_get_async_baud_val>:
-     844:	b5f0      	push	{r4, r5, r6, r7, lr}
-     846:	b085      	sub	sp, #20
-     848:	001e      	movs	r6, r3
-     84a:	ab0a      	add	r3, sp, #40	; 0x28
-     84c:	000d      	movs	r5, r1
-     84e:	7819      	ldrb	r1, [r3, #0]
-     850:	0003      	movs	r3, r0
-     852:	434b      	muls	r3, r1
-     854:	9203      	str	r2, [sp, #12]
-     856:	2740      	movs	r7, #64	; 0x40
-     858:	42ab      	cmp	r3, r5
-     85a:	d817      	bhi.n	88c <_sercom_get_async_baud_val+0x48>
-     85c:	2e00      	cmp	r6, #0
-     85e:	d118      	bne.n	892 <_sercom_get_async_baud_val+0x4e>
-     860:	0002      	movs	r2, r0
-     862:	0033      	movs	r3, r6
-     864:	0008      	movs	r0, r1
-     866:	4c1b      	ldr	r4, [pc, #108]	; (8d4 <_sercom_get_async_baud_val+0x90>)
-     868:	0031      	movs	r1, r6
-     86a:	47a0      	blx	r4
-     86c:	002a      	movs	r2, r5
-     86e:	0001      	movs	r1, r0
-     870:	0033      	movs	r3, r6
-     872:	4c19      	ldr	r4, [pc, #100]	; (8d8 <_sercom_get_async_baud_val+0x94>)
-     874:	0030      	movs	r0, r6
-     876:	47a0      	blx	r4
-     878:	2200      	movs	r2, #0
-     87a:	2301      	movs	r3, #1
-     87c:	1a12      	subs	r2, r2, r0
-     87e:	418b      	sbcs	r3, r1
-     880:	0c14      	lsrs	r4, r2, #16
-     882:	0418      	lsls	r0, r3, #16
-     884:	4304      	orrs	r4, r0
-     886:	2700      	movs	r7, #0
-     888:	9b03      	ldr	r3, [sp, #12]
-     88a:	801c      	strh	r4, [r3, #0]
-     88c:	0038      	movs	r0, r7
-     88e:	b005      	add	sp, #20
-     890:	bdf0      	pop	{r4, r5, r6, r7, pc}
-     892:	2400      	movs	r4, #0
-     894:	2e01      	cmp	r6, #1
-     896:	d1f6      	bne.n	886 <_sercom_get_async_baud_val+0x42>
-     898:	000a      	movs	r2, r1
-     89a:	0023      	movs	r3, r4
-     89c:	0021      	movs	r1, r4
-     89e:	4e0d      	ldr	r6, [pc, #52]	; (8d4 <_sercom_get_async_baud_val+0x90>)
-     8a0:	47b0      	blx	r6
-     8a2:	9000      	str	r0, [sp, #0]
-     8a4:	9101      	str	r1, [sp, #4]
-     8a6:	000b      	movs	r3, r1
-     8a8:	0002      	movs	r2, r0
-     8aa:	0021      	movs	r1, r4
-     8ac:	0028      	movs	r0, r5
-     8ae:	4c0a      	ldr	r4, [pc, #40]	; (8d8 <_sercom_get_async_baud_val+0x94>)
-     8b0:	47a0      	blx	r4
-     8b2:	2380      	movs	r3, #128	; 0x80
-     8b4:	0006      	movs	r6, r0
-     8b6:	019b      	lsls	r3, r3, #6
-     8b8:	4298      	cmp	r0, r3
-     8ba:	d8e7      	bhi.n	88c <_sercom_get_async_baud_val+0x48>
-     8bc:	9a00      	ldr	r2, [sp, #0]
-     8be:	9b01      	ldr	r3, [sp, #4]
-     8c0:	0f69      	lsrs	r1, r5, #29
-     8c2:	00e8      	lsls	r0, r5, #3
-     8c4:	47a0      	blx	r4
-     8c6:	00f4      	lsls	r4, r6, #3
-     8c8:	1b04      	subs	r4, r0, r4
-     8ca:	b2e4      	uxtb	r4, r4
-     8cc:	0364      	lsls	r4, r4, #13
-     8ce:	4334      	orrs	r4, r6
-     8d0:	e7d9      	b.n	886 <_sercom_get_async_baud_val+0x42>
-     8d2:	46c0      	nop			; (mov r8, r8)
-     8d4:	00001c8d 	.word	0x00001c8d
-     8d8:	000007b1 	.word	0x000007b1
-
-000008dc <sercom_set_gclk_generator>:
-     8dc:	b537      	push	{r0, r1, r2, r4, r5, lr}
-     8de:	4c0d      	ldr	r4, [pc, #52]	; (914 <sercom_set_gclk_generator+0x38>)
-     8e0:	0005      	movs	r5, r0
-     8e2:	7823      	ldrb	r3, [r4, #0]
-     8e4:	2b00      	cmp	r3, #0
-     8e6:	d001      	beq.n	8ec <sercom_set_gclk_generator+0x10>
-     8e8:	2900      	cmp	r1, #0
-     8ea:	d00c      	beq.n	906 <sercom_set_gclk_generator+0x2a>
-     8ec:	a901      	add	r1, sp, #4
-     8ee:	2013      	movs	r0, #19
-     8f0:	4b09      	ldr	r3, [pc, #36]	; (918 <sercom_set_gclk_generator+0x3c>)
-     8f2:	700d      	strb	r5, [r1, #0]
-     8f4:	4798      	blx	r3
-     8f6:	2013      	movs	r0, #19
-     8f8:	4b08      	ldr	r3, [pc, #32]	; (91c <sercom_set_gclk_generator+0x40>)
-     8fa:	4798      	blx	r3
-     8fc:	2301      	movs	r3, #1
-     8fe:	2000      	movs	r0, #0
-     900:	7065      	strb	r5, [r4, #1]
-     902:	7023      	strb	r3, [r4, #0]
-     904:	bd3e      	pop	{r1, r2, r3, r4, r5, pc}
-     906:	7863      	ldrb	r3, [r4, #1]
-     908:	0008      	movs	r0, r1
-     90a:	42ab      	cmp	r3, r5
-     90c:	d0fa      	beq.n	904 <sercom_set_gclk_generator+0x28>
-     90e:	201d      	movs	r0, #29
-     910:	e7f8      	b.n	904 <sercom_set_gclk_generator+0x28>
-     912:	46c0      	nop			; (mov r8, r8)
-     914:	20000105 	.word	0x20000105
-     918:	0000184d 	.word	0x0000184d
-     91c:	000017c5 	.word	0x000017c5
-
-00000920 <_sercom_get_default_pad>:
-     920:	4a39      	ldr	r2, [pc, #228]	; (a08 <_sercom_get_default_pad+0xe8>)
-     922:	0003      	movs	r3, r0
-     924:	b500      	push	{lr}
-     926:	0008      	movs	r0, r1
-     928:	4293      	cmp	r3, r2
-     92a:	d033      	beq.n	994 <_sercom_get_default_pad+0x74>
-     92c:	d807      	bhi.n	93e <_sercom_get_default_pad+0x1e>
-     92e:	4a37      	ldr	r2, [pc, #220]	; (a0c <_sercom_get_default_pad+0xec>)
-     930:	4293      	cmp	r3, r2
-     932:	d014      	beq.n	95e <_sercom_get_default_pad+0x3e>
-     934:	4a36      	ldr	r2, [pc, #216]	; (a10 <_sercom_get_default_pad+0xf0>)
-     936:	4293      	cmp	r3, r2
-     938:	d01f      	beq.n	97a <_sercom_get_default_pad+0x5a>
-     93a:	2300      	movs	r3, #0
-     93c:	e017      	b.n	96e <_sercom_get_default_pad+0x4e>
-     93e:	4a35      	ldr	r2, [pc, #212]	; (a14 <_sercom_get_default_pad+0xf4>)
-     940:	4293      	cmp	r3, r2
-     942:	d03a      	beq.n	9ba <_sercom_get_default_pad+0x9a>
-     944:	4a34      	ldr	r2, [pc, #208]	; (a18 <_sercom_get_default_pad+0xf8>)
-     946:	4293      	cmp	r3, r2
-     948:	d044      	beq.n	9d4 <_sercom_get_default_pad+0xb4>
-     94a:	4a34      	ldr	r2, [pc, #208]	; (a1c <_sercom_get_default_pad+0xfc>)
-     94c:	4293      	cmp	r3, r2
-     94e:	d1f4      	bne.n	93a <_sercom_get_default_pad+0x1a>
-     950:	2300      	movs	r3, #0
-     952:	2903      	cmp	r1, #3
-     954:	d80b      	bhi.n	96e <_sercom_get_default_pad+0x4e>
-     956:	f001 f8f7 	bl	1b48 <__gnu_thumb1_case_uqi>
-     95a:	2a50      	.short	0x2a50
-     95c:	2e2c      	.short	0x2e2c
-     95e:	2300      	movs	r3, #0
-     960:	2903      	cmp	r1, #3
-     962:	d804      	bhi.n	96e <_sercom_get_default_pad+0x4e>
-     964:	f001 f8f0 	bl	1b48 <__gnu_thumb1_case_uqi>
-     968:	07050243 	.word	0x07050243
-     96c:	4b2c      	ldr	r3, [pc, #176]	; (a20 <_sercom_get_default_pad+0x100>)
-     96e:	0018      	movs	r0, r3
-     970:	bd00      	pop	{pc}
-     972:	4b2c      	ldr	r3, [pc, #176]	; (a24 <_sercom_get_default_pad+0x104>)
-     974:	e7fb      	b.n	96e <_sercom_get_default_pad+0x4e>
-     976:	4b2c      	ldr	r3, [pc, #176]	; (a28 <_sercom_get_default_pad+0x108>)
-     978:	e7f9      	b.n	96e <_sercom_get_default_pad+0x4e>
-     97a:	2300      	movs	r3, #0
-     97c:	2903      	cmp	r1, #3
-     97e:	d8f6      	bhi.n	96e <_sercom_get_default_pad+0x4e>
-     980:	f001 f8e2 	bl	1b48 <__gnu_thumb1_case_uqi>
-     984:	06040237 	.word	0x06040237
-     988:	4b28      	ldr	r3, [pc, #160]	; (a2c <_sercom_get_default_pad+0x10c>)
-     98a:	e7f0      	b.n	96e <_sercom_get_default_pad+0x4e>
-     98c:	4b28      	ldr	r3, [pc, #160]	; (a30 <_sercom_get_default_pad+0x110>)
-     98e:	e7ee      	b.n	96e <_sercom_get_default_pad+0x4e>
-     990:	4b28      	ldr	r3, [pc, #160]	; (a34 <_sercom_get_default_pad+0x114>)
-     992:	e7ec      	b.n	96e <_sercom_get_default_pad+0x4e>
-     994:	2300      	movs	r3, #0
-     996:	2903      	cmp	r1, #3
-     998:	d8e9      	bhi.n	96e <_sercom_get_default_pad+0x4e>
-     99a:	f001 f8d5 	bl	1b48 <__gnu_thumb1_case_uqi>
-     99e:	022c      	.short	0x022c
-     9a0:	0604      	.short	0x0604
-     9a2:	4b25      	ldr	r3, [pc, #148]	; (a38 <_sercom_get_default_pad+0x118>)
-     9a4:	e7e3      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9a6:	4b25      	ldr	r3, [pc, #148]	; (a3c <_sercom_get_default_pad+0x11c>)
-     9a8:	e7e1      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9aa:	4b25      	ldr	r3, [pc, #148]	; (a40 <_sercom_get_default_pad+0x120>)
-     9ac:	e7df      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9ae:	4b25      	ldr	r3, [pc, #148]	; (a44 <_sercom_get_default_pad+0x124>)
-     9b0:	e7dd      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9b2:	4b25      	ldr	r3, [pc, #148]	; (a48 <_sercom_get_default_pad+0x128>)
-     9b4:	e7db      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9b6:	4b25      	ldr	r3, [pc, #148]	; (a4c <_sercom_get_default_pad+0x12c>)
-     9b8:	e7d9      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9ba:	2300      	movs	r3, #0
-     9bc:	2903      	cmp	r1, #3
-     9be:	d8d6      	bhi.n	96e <_sercom_get_default_pad+0x4e>
-     9c0:	f001 f8c2 	bl	1b48 <__gnu_thumb1_case_uqi>
-     9c4:	0604021d 	.word	0x0604021d
-     9c8:	4b21      	ldr	r3, [pc, #132]	; (a50 <_sercom_get_default_pad+0x130>)
-     9ca:	e7d0      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9cc:	4b21      	ldr	r3, [pc, #132]	; (a54 <_sercom_get_default_pad+0x134>)
-     9ce:	e7ce      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9d0:	4b21      	ldr	r3, [pc, #132]	; (a58 <_sercom_get_default_pad+0x138>)
-     9d2:	e7cc      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9d4:	2300      	movs	r3, #0
-     9d6:	2903      	cmp	r1, #3
-     9d8:	d8c9      	bhi.n	96e <_sercom_get_default_pad+0x4e>
-     9da:	f001 f8b5 	bl	1b48 <__gnu_thumb1_case_uqi>
-     9de:	0212      	.short	0x0212
-     9e0:	0604      	.short	0x0604
-     9e2:	4b1e      	ldr	r3, [pc, #120]	; (a5c <_sercom_get_default_pad+0x13c>)
-     9e4:	e7c3      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9e6:	4b1e      	ldr	r3, [pc, #120]	; (a60 <_sercom_get_default_pad+0x140>)
-     9e8:	e7c1      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9ea:	4b1e      	ldr	r3, [pc, #120]	; (a64 <_sercom_get_default_pad+0x144>)
-     9ec:	e7bf      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9ee:	4b1e      	ldr	r3, [pc, #120]	; (a68 <_sercom_get_default_pad+0x148>)
-     9f0:	e7bd      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9f2:	2303      	movs	r3, #3
-     9f4:	e7bb      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9f6:	4b1d      	ldr	r3, [pc, #116]	; (a6c <_sercom_get_default_pad+0x14c>)
-     9f8:	e7b9      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9fa:	4b1d      	ldr	r3, [pc, #116]	; (a70 <_sercom_get_default_pad+0x150>)
-     9fc:	e7b7      	b.n	96e <_sercom_get_default_pad+0x4e>
-     9fe:	4b1d      	ldr	r3, [pc, #116]	; (a74 <_sercom_get_default_pad+0x154>)
-     a00:	e7b5      	b.n	96e <_sercom_get_default_pad+0x4e>
-     a02:	4b1d      	ldr	r3, [pc, #116]	; (a78 <_sercom_get_default_pad+0x158>)
-     a04:	e7b3      	b.n	96e <_sercom_get_default_pad+0x4e>
-     a06:	46c0      	nop			; (mov r8, r8)
-     a08:	42001000 	.word	0x42001000
-     a0c:	42000800 	.word	0x42000800
-     a10:	42000c00 	.word	0x42000c00
-     a14:	42001800 	.word	0x42001800
-     a18:	42001c00 	.word	0x42001c00
-     a1c:	42001400 	.word	0x42001400
-     a20:	00050003 	.word	0x00050003
-     a24:	00060003 	.word	0x00060003
-     a28:	00070003 	.word	0x00070003
-     a2c:	00010003 	.word	0x00010003
-     a30:	001e0003 	.word	0x001e0003
-     a34:	001f0003 	.word	0x001f0003
-     a38:	00090003 	.word	0x00090003
-     a3c:	000a0003 	.word	0x000a0003
-     a40:	000b0003 	.word	0x000b0003
-     a44:	00110003 	.word	0x00110003
-     a48:	00120003 	.word	0x00120003
-     a4c:	00130003 	.word	0x00130003
-     a50:	000d0003 	.word	0x000d0003
-     a54:	000e0003 	.word	0x000e0003
-     a58:	000f0003 	.word	0x000f0003
-     a5c:	00170003 	.word	0x00170003
-     a60:	00180003 	.word	0x00180003
-     a64:	00190003 	.word	0x00190003
-     a68:	00040003 	.word	0x00040003
-     a6c:	00080003 	.word	0x00080003
-     a70:	00100003 	.word	0x00100003
-     a74:	000c0003 	.word	0x000c0003
-     a78:	00160003 	.word	0x00160003
-
-00000a7c <_sercom_get_sercom_inst_index>:
-     a7c:	b570      	push	{r4, r5, r6, lr}
-     a7e:	b086      	sub	sp, #24
-     a80:	4669      	mov	r1, sp
-     a82:	4b09      	ldr	r3, [pc, #36]	; (aa8 <_sercom_get_sercom_inst_index+0x2c>)
-     a84:	466a      	mov	r2, sp
-     a86:	cb70      	ldmia	r3!, {r4, r5, r6}
-     a88:	c170      	stmia	r1!, {r4, r5, r6}
-     a8a:	cb70      	ldmia	r3!, {r4, r5, r6}
-     a8c:	c170      	stmia	r1!, {r4, r5, r6}
-     a8e:	2300      	movs	r3, #0
-     a90:	0099      	lsls	r1, r3, #2
-     a92:	5851      	ldr	r1, [r2, r1]
-     a94:	4281      	cmp	r1, r0
-     a96:	d102      	bne.n	a9e <_sercom_get_sercom_inst_index+0x22>
-     a98:	b2d8      	uxtb	r0, r3
-     a9a:	b006      	add	sp, #24
-     a9c:	bd70      	pop	{r4, r5, r6, pc}
-     a9e:	3301      	adds	r3, #1
-     aa0:	2b06      	cmp	r3, #6
-     aa2:	d1f5      	bne.n	a90 <_sercom_get_sercom_inst_index+0x14>
-     aa4:	2000      	movs	r0, #0
-     aa6:	e7f8      	b.n	a9a <_sercom_get_sercom_inst_index+0x1e>
-     aa8:	00003574 	.word	0x00003574
-
-00000aac <_read>:
-     aac:	b570      	push	{r4, r5, r6, lr}
-     aae:	000e      	movs	r6, r1
-     ab0:	0014      	movs	r4, r2
-     ab2:	0015      	movs	r5, r2
-     ab4:	2800      	cmp	r0, #0
-     ab6:	d008      	beq.n	aca <_read+0x1e>
-     ab8:	2001      	movs	r0, #1
-     aba:	4240      	negs	r0, r0
-     abc:	e00c      	b.n	ad8 <_read+0x2c>
-     abe:	4b07      	ldr	r3, [pc, #28]	; (adc <_read+0x30>)
-     ac0:	3d01      	subs	r5, #1
-     ac2:	6818      	ldr	r0, [r3, #0]
-     ac4:	4b06      	ldr	r3, [pc, #24]	; (ae0 <_read+0x34>)
-     ac6:	681b      	ldr	r3, [r3, #0]
-     ac8:	4798      	blx	r3
-     aca:	1b61      	subs	r1, r4, r5
-     acc:	1871      	adds	r1, r6, r1
-     ace:	2d00      	cmp	r5, #0
-     ad0:	dcf5      	bgt.n	abe <_read+0x12>
-     ad2:	43e0      	mvns	r0, r4
-     ad4:	17c0      	asrs	r0, r0, #31
-     ad6:	4020      	ands	r0, r4
-     ad8:	bd70      	pop	{r4, r5, r6, pc}
-     ada:	46c0      	nop			; (mov r8, r8)
-     adc:	20000238 	.word	0x20000238
-     ae0:	20000230 	.word	0x20000230
-
-00000ae4 <_write>:
-     ae4:	3801      	subs	r0, #1
-     ae6:	b570      	push	{r4, r5, r6, lr}
-     ae8:	000e      	movs	r6, r1
-     aea:	2802      	cmp	r0, #2
-     aec:	d80d      	bhi.n	b0a <_write+0x26>
-     aee:	000c      	movs	r4, r1
-     af0:	188d      	adds	r5, r1, r2
-     af2:	1ba0      	subs	r0, r4, r6
-     af4:	42ac      	cmp	r4, r5
-     af6:	d00a      	beq.n	b0e <_write+0x2a>
-     af8:	4b05      	ldr	r3, [pc, #20]	; (b10 <_write+0x2c>)
-     afa:	7821      	ldrb	r1, [r4, #0]
-     afc:	6818      	ldr	r0, [r3, #0]
-     afe:	4b05      	ldr	r3, [pc, #20]	; (b14 <_write+0x30>)
-     b00:	3401      	adds	r4, #1
-     b02:	681b      	ldr	r3, [r3, #0]
-     b04:	4798      	blx	r3
-     b06:	2800      	cmp	r0, #0
-     b08:	daf3      	bge.n	af2 <_write+0xe>
-     b0a:	2001      	movs	r0, #1
-     b0c:	4240      	negs	r0, r0
-     b0e:	bd70      	pop	{r4, r5, r6, pc}
-     b10:	20000238 	.word	0x20000238
-     b14:	20000234 	.word	0x20000234
-
-00000b18 <padc_init>:
-     b18:	b570      	push	{r4, r5, r6, lr}
-     b1a:	b094      	sub	sp, #80	; 0x50
-     b1c:	ac08      	add	r4, sp, #32
-     b1e:	0020      	movs	r0, r4
-     b20:	4b28      	ldr	r3, [pc, #160]	; (bc4 <padc_init+0xac>)
-     b22:	4798      	blx	r3
-     b24:	2104      	movs	r1, #4
-     b26:	2280      	movs	r2, #128	; 0x80
-     b28:	7321      	strb	r1, [r4, #12]
-     b2a:	21c0      	movs	r1, #192	; 0xc0
-     b2c:	2300      	movs	r3, #0
-     b2e:	4d26      	ldr	r5, [pc, #152]	; (bc8 <padc_init+0xb0>)
-     b30:	0052      	lsls	r2, r2, #1
-     b32:	8062      	strh	r2, [r4, #2]
-     b34:	0149      	lsls	r1, r1, #5
-     b36:	3aff      	subs	r2, #255	; 0xff
-     b38:	60a3      	str	r3, [r4, #8]
-     b3a:	7123      	strb	r3, [r4, #4]
-     b3c:	7062      	strb	r2, [r4, #1]
-     b3e:	81e1      	strh	r1, [r4, #14]
-     b40:	7522      	strb	r2, [r4, #20]
-     b42:	74a3      	strb	r3, [r4, #18]
-     b44:	0022      	movs	r2, r4
-     b46:	4b21      	ldr	r3, [pc, #132]	; (bcc <padc_init+0xb4>)
-     b48:	4921      	ldr	r1, [pc, #132]	; (bd0 <padc_init+0xb8>)
-     b4a:	0028      	movs	r0, r5
-     b4c:	4798      	blx	r3
-     b4e:	682b      	ldr	r3, [r5, #0]
-     b50:	7e5a      	ldrb	r2, [r3, #25]
-     b52:	b252      	sxtb	r2, r2
-     b54:	2a00      	cmp	r2, #0
-     b56:	dbfb      	blt.n	b50 <padc_init+0x38>
-     b58:	220f      	movs	r2, #15
-     b5a:	759a      	strb	r2, [r3, #22]
-     b5c:	761a      	strb	r2, [r3, #24]
-     b5e:	7819      	ldrb	r1, [r3, #0]
-     b60:	3a0d      	subs	r2, #13
-     b62:	430a      	orrs	r2, r1
-     b64:	701a      	strb	r2, [r3, #0]
-     b66:	682a      	ldr	r2, [r5, #0]
-     b68:	7e53      	ldrb	r3, [r2, #25]
-     b6a:	b25b      	sxtb	r3, r3
-     b6c:	2b00      	cmp	r3, #0
-     b6e:	dbfb      	blt.n	b68 <padc_init+0x50>
-     b70:	4668      	mov	r0, sp
-     b72:	4b18      	ldr	r3, [pc, #96]	; (bd4 <padc_init+0xbc>)
-     b74:	4798      	blx	r3
-     b76:	466a      	mov	r2, sp
-     b78:	2327      	movs	r3, #39	; 0x27
-     b7a:	2400      	movs	r4, #0
-     b7c:	4e16      	ldr	r6, [pc, #88]	; (bd8 <padc_init+0xc0>)
-     b7e:	4669      	mov	r1, sp
-     b80:	7053      	strb	r3, [r2, #1]
-     b82:	0030      	movs	r0, r6
-     b84:	4b15      	ldr	r3, [pc, #84]	; (bdc <padc_init+0xc4>)
-     b86:	7094      	strb	r4, [r2, #2]
-     b88:	4798      	blx	r3
-     b8a:	2301      	movs	r3, #1
-     b8c:	a902      	add	r1, sp, #8
-     b8e:	700b      	strb	r3, [r1, #0]
-     b90:	714b      	strb	r3, [r1, #5]
-     b92:	70cb      	strb	r3, [r1, #3]
-     b94:	330f      	adds	r3, #15
-     b96:	810b      	strh	r3, [r1, #8]
-     b98:	682b      	ldr	r3, [r5, #0]
-     b9a:	704c      	strb	r4, [r1, #1]
-     b9c:	331a      	adds	r3, #26
-     b9e:	60cb      	str	r3, [r1, #12]
-     ba0:	4b0f      	ldr	r3, [pc, #60]	; (be0 <padc_init+0xc8>)
-     ba2:	708c      	strb	r4, [r1, #2]
-     ba4:	718c      	strb	r4, [r1, #6]
-     ba6:	71cc      	strb	r4, [r1, #7]
-     ba8:	710c      	strb	r4, [r1, #4]
-     baa:	4c0e      	ldr	r4, [pc, #56]	; (be4 <padc_init+0xcc>)
-     bac:	3320      	adds	r3, #32
-     bae:	610b      	str	r3, [r1, #16]
-     bb0:	0020      	movs	r0, r4
-     bb2:	4b0d      	ldr	r3, [pc, #52]	; (be8 <padc_init+0xd0>)
-     bb4:	614c      	str	r4, [r1, #20]
-     bb6:	4798      	blx	r3
-     bb8:	0021      	movs	r1, r4
-     bba:	0030      	movs	r0, r6
-     bbc:	4b0b      	ldr	r3, [pc, #44]	; (bec <padc_init+0xd4>)
-     bbe:	4798      	blx	r3
-     bc0:	b014      	add	sp, #80	; 0x50
-     bc2:	bd70      	pop	{r4, r5, r6, pc}
-     bc4:	00000155 	.word	0x00000155
-     bc8:	20000108 	.word	0x20000108
-     bcc:	00000199 	.word	0x00000199
-     bd0:	42004000 	.word	0x42004000
-     bd4:	0000051d 	.word	0x0000051d
-     bd8:	20000110 	.word	0x20000110
-     bdc:	0000052d 	.word	0x0000052d
-     be0:	2000012c 	.word	0x2000012c
-     be4:	20000240 	.word	0x20000240
-     be8:	000006e5 	.word	0x000006e5
-     bec:	0000078d 	.word	0x0000078d
-
-00000bf0 <padc_start>:
-     bf0:	b510      	push	{r4, lr}
-     bf2:	4b09      	ldr	r3, [pc, #36]	; (c18 <padc_start+0x28>)
-     bf4:	681b      	ldr	r3, [r3, #0]
-     bf6:	7e5a      	ldrb	r2, [r3, #25]
-     bf8:	b252      	sxtb	r2, r2
-     bfa:	2a00      	cmp	r2, #0
-     bfc:	dbfb      	blt.n	bf6 <padc_start+0x6>
-     bfe:	2202      	movs	r2, #2
-     c00:	7b19      	ldrb	r1, [r3, #12]
-     c02:	430a      	orrs	r2, r1
-     c04:	731a      	strb	r2, [r3, #12]
-     c06:	7e5a      	ldrb	r2, [r3, #25]
-     c08:	b252      	sxtb	r2, r2
-     c0a:	2a00      	cmp	r2, #0
-     c0c:	dbfb      	blt.n	c06 <padc_start+0x16>
-     c0e:	4803      	ldr	r0, [pc, #12]	; (c1c <padc_start+0x2c>)
-     c10:	4b03      	ldr	r3, [pc, #12]	; (c20 <padc_start+0x30>)
-     c12:	4798      	blx	r3
-     c14:	bd10      	pop	{r4, pc}
-     c16:	46c0      	nop			; (mov r8, r8)
-     c18:	20000108 	.word	0x20000108
-     c1c:	20000110 	.word	0x20000110
-     c20:	00000659 	.word	0x00000659
-
-00000c24 <padc_get_raw>:
-     c24:	2300      	movs	r3, #0
-     c26:	0018      	movs	r0, r3
-     c28:	4904      	ldr	r1, [pc, #16]	; (c3c <padc_get_raw+0x18>)
-     c2a:	5a5a      	ldrh	r2, [r3, r1]
-     c2c:	3302      	adds	r3, #2
-     c2e:	1880      	adds	r0, r0, r2
-     c30:	2b20      	cmp	r3, #32
-     c32:	d1fa      	bne.n	c2a <padc_get_raw+0x6>
-     c34:	0900      	lsrs	r0, r0, #4
-     c36:	b280      	uxth	r0, r0
-     c38:	4770      	bx	lr
-     c3a:	46c0      	nop			; (mov r8, r8)
-     c3c:	2000012c 	.word	0x2000012c
-
-00000c40 <padc_get_voltage>:
-     c40:	b510      	push	{r4, lr}
-     c42:	4b04      	ldr	r3, [pc, #16]	; (c54 <padc_get_voltage+0x14>)
-     c44:	4798      	blx	r3
-     c46:	4b04      	ldr	r3, [pc, #16]	; (c58 <padc_get_voltage+0x18>)
-     c48:	4798      	blx	r3
-     c4a:	4904      	ldr	r1, [pc, #16]	; (c5c <padc_get_voltage+0x1c>)
-     c4c:	4b04      	ldr	r3, [pc, #16]	; (c60 <padc_get_voltage+0x20>)
-     c4e:	4798      	blx	r3
-     c50:	bd10      	pop	{r4, pc}
-     c52:	46c0      	nop			; (mov r8, r8)
-     c54:	00000c25 	.word	0x00000c25
-     c58:	00002339 	.word	0x00002339
-     c5c:	3a0cf909 	.word	0x3a0cf909
-     c60:	00001ce1 	.word	0x00001ce1
-
-00000c64 <usart_serial_getchar>:
-     c64:	b573      	push	{r0, r1, r4, r5, r6, lr}
-     c66:	466b      	mov	r3, sp
-     c68:	1d9c      	adds	r4, r3, #6
-     c6a:	2300      	movs	r3, #0
-     c6c:	0006      	movs	r6, r0
-     c6e:	000d      	movs	r5, r1
-     c70:	8023      	strh	r3, [r4, #0]
-     c72:	0021      	movs	r1, r4
-     c74:	0030      	movs	r0, r6
-     c76:	4b03      	ldr	r3, [pc, #12]	; (c84 <usart_serial_getchar+0x20>)
-     c78:	4798      	blx	r3
-     c7a:	2800      	cmp	r0, #0
-     c7c:	d1f9      	bne.n	c72 <usart_serial_getchar+0xe>
-     c7e:	8823      	ldrh	r3, [r4, #0]
-     c80:	702b      	strb	r3, [r5, #0]
-     c82:	bd73      	pop	{r0, r1, r4, r5, r6, pc}
-     c84:	00001073 	.word	0x00001073
-
-00000c88 <usart_serial_putchar>:
-     c88:	b570      	push	{r4, r5, r6, lr}
-     c8a:	0004      	movs	r4, r0
-     c8c:	000d      	movs	r5, r1
-     c8e:	b2a9      	uxth	r1, r5
-     c90:	0020      	movs	r0, r4
-     c92:	4b02      	ldr	r3, [pc, #8]	; (c9c <usart_serial_putchar+0x14>)
-     c94:	4798      	blx	r3
-     c96:	2800      	cmp	r0, #0
-     c98:	d1f9      	bne.n	c8e <usart_serial_putchar+0x6>
-     c9a:	bd70      	pop	{r4, r5, r6, pc}
-     c9c:	00001051 	.word	0x00001051
-
-00000ca0 <pusart_init>:
-     ca0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-     ca2:	2380      	movs	r3, #128	; 0x80
-     ca4:	4a2d      	ldr	r2, [pc, #180]	; (d5c <pusart_init+0xbc>)
-     ca6:	05db      	lsls	r3, r3, #23
-     ca8:	6013      	str	r3, [r2, #0]
-     caa:	23ff      	movs	r3, #255	; 0xff
-     cac:	2501      	movs	r5, #1
-     cae:	2400      	movs	r4, #0
-     cb0:	8113      	strh	r3, [r2, #8]
-     cb2:	1d53      	adds	r3, r2, #5
-     cb4:	77dd      	strb	r5, [r3, #31]
-     cb6:	1d93      	adds	r3, r2, #6
-     cb8:	77dd      	strb	r5, [r3, #31]
-     cba:	1dd3      	adds	r3, r2, #7
-     cbc:	77dc      	strb	r4, [r3, #31]
-     cbe:	0013      	movs	r3, r2
-     cc0:	3308      	adds	r3, #8
-     cc2:	77dc      	strb	r4, [r3, #31]
-     cc4:	0013      	movs	r3, r2
-     cc6:	332c      	adds	r3, #44	; 0x2c
-     cc8:	701c      	strb	r4, [r3, #0]
-     cca:	0013      	movs	r3, r2
-     ccc:	332d      	adds	r3, #45	; 0x2d
-     cce:	701c      	strb	r4, [r3, #0]
-     cd0:	2313      	movs	r3, #19
-     cd2:	7693      	strb	r3, [r2, #26]
-     cd4:	4b22      	ldr	r3, [pc, #136]	; (d60 <pusart_init+0xc0>)
-     cd6:	4e23      	ldr	r6, [pc, #140]	; (d64 <pusart_init+0xc4>)
-     cd8:	6313      	str	r3, [r2, #48]	; 0x30
-     cda:	4b23      	ldr	r3, [pc, #140]	; (d68 <pusart_init+0xc8>)
-     cdc:	6054      	str	r4, [r2, #4]
-     cde:	6353      	str	r3, [r2, #52]	; 0x34
-     ce0:	2301      	movs	r3, #1
-     ce2:	425b      	negs	r3, r3
-     ce4:	6393      	str	r3, [r2, #56]	; 0x38
-     ce6:	63d3      	str	r3, [r2, #60]	; 0x3c
-     ce8:	2380      	movs	r3, #128	; 0x80
-     cea:	035b      	lsls	r3, r3, #13
-     cec:	60d3      	str	r3, [r2, #12]
-     cee:	23e1      	movs	r3, #225	; 0xe1
-     cf0:	025b      	lsls	r3, r3, #9
-     cf2:	6213      	str	r3, [r2, #32]
-     cf4:	4b1d      	ldr	r3, [pc, #116]	; (d6c <pusart_init+0xcc>)
-     cf6:	7294      	strb	r4, [r2, #10]
-     cf8:	72d4      	strb	r4, [r2, #11]
-     cfa:	6294      	str	r4, [r2, #40]	; 0x28
-     cfc:	6154      	str	r4, [r2, #20]
-     cfe:	8214      	strh	r4, [r2, #16]
-     d00:	76d4      	strb	r4, [r2, #27]
-     d02:	7614      	strb	r4, [r2, #24]
-     d04:	7714      	strb	r4, [r2, #28]
-     d06:	7654      	strb	r4, [r2, #25]
-     d08:	7754      	strb	r4, [r2, #29]
-     d0a:	4919      	ldr	r1, [pc, #100]	; (d70 <pusart_init+0xd0>)
-     d0c:	601e      	str	r6, [r3, #0]
-     d0e:	4b19      	ldr	r3, [pc, #100]	; (d74 <pusart_init+0xd4>)
-     d10:	0030      	movs	r0, r6
-     d12:	6019      	str	r1, [r3, #0]
-     d14:	4918      	ldr	r1, [pc, #96]	; (d78 <pusart_init+0xd8>)
-     d16:	4b19      	ldr	r3, [pc, #100]	; (d7c <pusart_init+0xdc>)
-     d18:	6019      	str	r1, [r3, #0]
-     d1a:	4919      	ldr	r1, [pc, #100]	; (d80 <pusart_init+0xe0>)
-     d1c:	4b19      	ldr	r3, [pc, #100]	; (d84 <pusart_init+0xe4>)
-     d1e:	4798      	blx	r3
-     d20:	4f19      	ldr	r7, [pc, #100]	; (d88 <pusart_init+0xe8>)
-     d22:	0021      	movs	r1, r4
-     d24:	683b      	ldr	r3, [r7, #0]
-     d26:	6898      	ldr	r0, [r3, #8]
-     d28:	4b18      	ldr	r3, [pc, #96]	; (d8c <pusart_init+0xec>)
-     d2a:	4798      	blx	r3
-     d2c:	683b      	ldr	r3, [r7, #0]
-     d2e:	0021      	movs	r1, r4
-     d30:	6858      	ldr	r0, [r3, #4]
-     d32:	4b16      	ldr	r3, [pc, #88]	; (d8c <pusart_init+0xec>)
-     d34:	4798      	blx	r3
-     d36:	6834      	ldr	r4, [r6, #0]
-     d38:	4b15      	ldr	r3, [pc, #84]	; (d90 <pusart_init+0xf0>)
-     d3a:	0020      	movs	r0, r4
-     d3c:	4798      	blx	r3
-     d3e:	231f      	movs	r3, #31
-     d40:	4018      	ands	r0, r3
-     d42:	4085      	lsls	r5, r0
-     d44:	4b13      	ldr	r3, [pc, #76]	; (d94 <pusart_init+0xf4>)
-     d46:	601d      	str	r5, [r3, #0]
-     d48:	6832      	ldr	r2, [r6, #0]
-     d4a:	69d3      	ldr	r3, [r2, #28]
-     d4c:	2b00      	cmp	r3, #0
-     d4e:	d1fc      	bne.n	d4a <pusart_init+0xaa>
-     d50:	6822      	ldr	r2, [r4, #0]
-     d52:	3302      	adds	r3, #2
-     d54:	4313      	orrs	r3, r2
-     d56:	6023      	str	r3, [r4, #0]
-     d58:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-     d5a:	46c0      	nop			; (mov r8, r8)
-     d5c:	2000014c 	.word	0x2000014c
-     d60:	00160002 	.word	0x00160002
-     d64:	20000250 	.word	0x20000250
-     d68:	00170002 	.word	0x00170002
-     d6c:	20000238 	.word	0x20000238
-     d70:	00000c89 	.word	0x00000c89
-     d74:	20000234 	.word	0x20000234
-     d78:	00000c65 	.word	0x00000c65
-     d7c:	20000230 	.word	0x20000230
-     d80:	42001400 	.word	0x42001400
-     d84:	00000d99 	.word	0x00000d99
-     d88:	20000018 	.word	0x20000018
-     d8c:	00002575 	.word	0x00002575
-     d90:	00001281 	.word	0x00001281
-     d94:	e000e100 	.word	0xe000e100
-
-00000d98 <usart_init>:
-     d98:	b5f0      	push	{r4, r5, r6, r7, lr}
-     d9a:	0007      	movs	r7, r0
-     d9c:	b093      	sub	sp, #76	; 0x4c
-     d9e:	4b9e      	ldr	r3, [pc, #632]	; (1018 <usart_init+0x280>)
-     da0:	6039      	str	r1, [r7, #0]
-     da2:	0008      	movs	r0, r1
-     da4:	0014      	movs	r4, r2
-     da6:	9104      	str	r1, [sp, #16]
-     da8:	4798      	blx	r3
-     daa:	2201      	movs	r2, #1
-     dac:	9b04      	ldr	r3, [sp, #16]
-     dae:	0006      	movs	r6, r0
-     db0:	681b      	ldr	r3, [r3, #0]
-     db2:	2005      	movs	r0, #5
-     db4:	4213      	tst	r3, r2
-     db6:	d000      	beq.n	dba <usart_init+0x22>
-     db8:	e10a      	b.n	fd0 <usart_init+0x238>
-     dba:	9b04      	ldr	r3, [sp, #16]
-     dbc:	3017      	adds	r0, #23
-     dbe:	681d      	ldr	r5, [r3, #0]
-     dc0:	2302      	movs	r3, #2
-     dc2:	401d      	ands	r5, r3
-     dc4:	d000      	beq.n	dc8 <usart_init+0x30>
-     dc6:	e103      	b.n	fd0 <usart_init+0x238>
-     dc8:	18f3      	adds	r3, r6, r3
-     dca:	381b      	subs	r0, #27
-     dcc:	4098      	lsls	r0, r3
-     dce:	0003      	movs	r3, r0
-     dd0:	4a92      	ldr	r2, [pc, #584]	; (101c <usart_init+0x284>)
-     dd2:	3614      	adds	r6, #20
-     dd4:	6a11      	ldr	r1, [r2, #32]
-     dd6:	b2f6      	uxtb	r6, r6
-     dd8:	430b      	orrs	r3, r1
-     dda:	6213      	str	r3, [r2, #32]
-     ddc:	0023      	movs	r3, r4
-     dde:	332d      	adds	r3, #45	; 0x2d
-     de0:	9302      	str	r3, [sp, #8]
-     de2:	781b      	ldrb	r3, [r3, #0]
-     de4:	a90c      	add	r1, sp, #48	; 0x30
-     de6:	700b      	strb	r3, [r1, #0]
-     de8:	0030      	movs	r0, r6
-     dea:	4b8d      	ldr	r3, [pc, #564]	; (1020 <usart_init+0x288>)
-     dec:	4798      	blx	r3
-     dee:	0030      	movs	r0, r6
-     df0:	4b8c      	ldr	r3, [pc, #560]	; (1024 <usart_init+0x28c>)
-     df2:	4798      	blx	r3
-     df4:	9b02      	ldr	r3, [sp, #8]
-     df6:	0029      	movs	r1, r5
-     df8:	7818      	ldrb	r0, [r3, #0]
-     dfa:	4b8b      	ldr	r3, [pc, #556]	; (1028 <usart_init+0x290>)
-     dfc:	4798      	blx	r3
-     dfe:	7ae3      	ldrb	r3, [r4, #11]
-     e00:	2608      	movs	r6, #8
-     e02:	717b      	strb	r3, [r7, #5]
-     e04:	1d63      	adds	r3, r4, #5
-     e06:	7fdb      	ldrb	r3, [r3, #31]
-     e08:	71bb      	strb	r3, [r7, #6]
-     e0a:	1da3      	adds	r3, r4, #6
-     e0c:	7fdb      	ldrb	r3, [r3, #31]
-     e0e:	71fb      	strb	r3, [r7, #7]
-     e10:	7ee3      	ldrb	r3, [r4, #27]
-     e12:	723b      	strb	r3, [r7, #8]
-     e14:	7f23      	ldrb	r3, [r4, #28]
-     e16:	727b      	strb	r3, [r7, #9]
-     e18:	683b      	ldr	r3, [r7, #0]
-     e1a:	9303      	str	r3, [sp, #12]
-     e1c:	0018      	movs	r0, r3
-     e1e:	4b7e      	ldr	r3, [pc, #504]	; (1018 <usart_init+0x280>)
-     e20:	4798      	blx	r3
-     e22:	ab0e      	add	r3, sp, #56	; 0x38
-     e24:	801d      	strh	r5, [r3, #0]
-     e26:	8a23      	ldrh	r3, [r4, #16]
-     e28:	3014      	adds	r0, #20
-     e2a:	9302      	str	r3, [sp, #8]
-     e2c:	2380      	movs	r3, #128	; 0x80
-     e2e:	9a02      	ldr	r2, [sp, #8]
-     e30:	01db      	lsls	r3, r3, #7
-     e32:	429a      	cmp	r2, r3
-     e34:	d014      	beq.n	e60 <usart_init+0xc8>
-     e36:	d808      	bhi.n	e4a <usart_init+0xb2>
-     e38:	2380      	movs	r3, #128	; 0x80
-     e3a:	2610      	movs	r6, #16
-     e3c:	019b      	lsls	r3, r3, #6
-     e3e:	429a      	cmp	r2, r3
-     e40:	d100      	bne.n	e44 <usart_init+0xac>
-     e42:	e0c8      	b.n	fd6 <usart_init+0x23e>
-     e44:	2610      	movs	r6, #16
-     e46:	2500      	movs	r5, #0
-     e48:	e00a      	b.n	e60 <usart_init+0xc8>
-     e4a:	23c0      	movs	r3, #192	; 0xc0
-     e4c:	9a02      	ldr	r2, [sp, #8]
-     e4e:	01db      	lsls	r3, r3, #7
-     e50:	429a      	cmp	r2, r3
-     e52:	d100      	bne.n	e56 <usart_init+0xbe>
-     e54:	e0be      	b.n	fd4 <usart_init+0x23c>
-     e56:	2380      	movs	r3, #128	; 0x80
-     e58:	2603      	movs	r6, #3
-     e5a:	021b      	lsls	r3, r3, #8
-     e5c:	429a      	cmp	r2, r3
-     e5e:	d1f1      	bne.n	e44 <usart_init+0xac>
-     e60:	6823      	ldr	r3, [r4, #0]
-     e62:	9306      	str	r3, [sp, #24]
-     e64:	68e3      	ldr	r3, [r4, #12]
-     e66:	9307      	str	r3, [sp, #28]
-     e68:	6963      	ldr	r3, [r4, #20]
-     e6a:	9308      	str	r3, [sp, #32]
-     e6c:	7e23      	ldrb	r3, [r4, #24]
-     e6e:	9309      	str	r3, [sp, #36]	; 0x24
-     e70:	1de3      	adds	r3, r4, #7
-     e72:	7fdb      	ldrb	r3, [r3, #31]
-     e74:	930a      	str	r3, [sp, #40]	; 0x28
-     e76:	6863      	ldr	r3, [r4, #4]
-     e78:	9305      	str	r3, [sp, #20]
-     e7a:	0023      	movs	r3, r4
-     e7c:	9a05      	ldr	r2, [sp, #20]
-     e7e:	3308      	adds	r3, #8
-     e80:	2a00      	cmp	r2, #0
-     e82:	d100      	bne.n	e86 <usart_init+0xee>
-     e84:	e0a9      	b.n	fda <usart_init+0x242>
-     e86:	2280      	movs	r2, #128	; 0x80
-     e88:	9905      	ldr	r1, [sp, #20]
-     e8a:	0552      	lsls	r2, r2, #21
-     e8c:	4291      	cmp	r1, r2
-     e8e:	d10e      	bne.n	eae <usart_init+0x116>
-     e90:	7fdb      	ldrb	r3, [r3, #31]
-     e92:	2b00      	cmp	r3, #0
-     e94:	d10b      	bne.n	eae <usart_init+0x116>
-     e96:	4b65      	ldr	r3, [pc, #404]	; (102c <usart_init+0x294>)
-     e98:	b2c0      	uxtb	r0, r0
-     e9a:	6a25      	ldr	r5, [r4, #32]
-     e9c:	4798      	blx	r3
-     e9e:	aa0e      	add	r2, sp, #56	; 0x38
-     ea0:	0001      	movs	r1, r0
-     ea2:	4b63      	ldr	r3, [pc, #396]	; (1030 <usart_init+0x298>)
-     ea4:	0028      	movs	r0, r5
-     ea6:	4798      	blx	r3
-     ea8:	2800      	cmp	r0, #0
-     eaa:	d000      	beq.n	eae <usart_init+0x116>
-     eac:	e090      	b.n	fd0 <usart_init+0x238>
-     eae:	7e63      	ldrb	r3, [r4, #25]
-     eb0:	2b00      	cmp	r3, #0
-     eb2:	d002      	beq.n	eba <usart_init+0x122>
-     eb4:	7ea3      	ldrb	r3, [r4, #26]
-     eb6:	9a03      	ldr	r2, [sp, #12]
-     eb8:	7393      	strb	r3, [r2, #14]
-     eba:	ae0e      	add	r6, sp, #56	; 0x38
-     ebc:	8833      	ldrh	r3, [r6, #0]
-     ebe:	9a03      	ldr	r2, [sp, #12]
-     ec0:	8193      	strh	r3, [r2, #12]
-     ec2:	9a07      	ldr	r2, [sp, #28]
-     ec4:	9b06      	ldr	r3, [sp, #24]
-     ec6:	4313      	orrs	r3, r2
-     ec8:	9a08      	ldr	r2, [sp, #32]
-     eca:	4313      	orrs	r3, r2
-     ecc:	9a05      	ldr	r2, [sp, #20]
-     ece:	4313      	orrs	r3, r2
-     ed0:	9a02      	ldr	r2, [sp, #8]
-     ed2:	4313      	orrs	r3, r2
-     ed4:	9a09      	ldr	r2, [sp, #36]	; 0x24
-     ed6:	0212      	lsls	r2, r2, #8
-     ed8:	4313      	orrs	r3, r2
-     eda:	9a0a      	ldr	r2, [sp, #40]	; 0x28
-     edc:	0752      	lsls	r2, r2, #29
-     ede:	4313      	orrs	r3, r2
-     ee0:	0022      	movs	r2, r4
-     ee2:	3208      	adds	r2, #8
-     ee4:	7fd2      	ldrb	r2, [r2, #31]
-     ee6:	2a00      	cmp	r2, #0
-     ee8:	d101      	bne.n	eee <usart_init+0x156>
-     eea:	3204      	adds	r2, #4
-     eec:	4313      	orrs	r3, r2
-     eee:	7e62      	ldrb	r2, [r4, #25]
-     ef0:	7f21      	ldrb	r1, [r4, #28]
-     ef2:	0292      	lsls	r2, r2, #10
-     ef4:	0249      	lsls	r1, r1, #9
-     ef6:	430a      	orrs	r2, r1
-     ef8:	7f61      	ldrb	r1, [r4, #29]
-     efa:	7ae0      	ldrb	r0, [r4, #11]
-     efc:	0209      	lsls	r1, r1, #8
-     efe:	430a      	orrs	r2, r1
-     f00:	1d61      	adds	r1, r4, #5
-     f02:	7fc9      	ldrb	r1, [r1, #31]
-     f04:	0449      	lsls	r1, r1, #17
-     f06:	430a      	orrs	r2, r1
-     f08:	1da1      	adds	r1, r4, #6
-     f0a:	7fc9      	ldrb	r1, [r1, #31]
-     f0c:	0409      	lsls	r1, r1, #16
-     f0e:	430a      	orrs	r2, r1
-     f10:	7aa1      	ldrb	r1, [r4, #10]
-     f12:	4301      	orrs	r1, r0
-     f14:	430a      	orrs	r2, r1
-     f16:	8921      	ldrh	r1, [r4, #8]
-     f18:	29ff      	cmp	r1, #255	; 0xff
-     f1a:	d100      	bne.n	f1e <usart_init+0x186>
-     f1c:	e073      	b.n	1006 <usart_init+0x26e>
-     f1e:	2080      	movs	r0, #128	; 0x80
-     f20:	0440      	lsls	r0, r0, #17
-     f22:	4303      	orrs	r3, r0
-     f24:	430a      	orrs	r2, r1
-     f26:	0021      	movs	r1, r4
-     f28:	312c      	adds	r1, #44	; 0x2c
-     f2a:	7809      	ldrb	r1, [r1, #0]
-     f2c:	2900      	cmp	r1, #0
-     f2e:	d103      	bne.n	f38 <usart_init+0x1a0>
-     f30:	4940      	ldr	r1, [pc, #256]	; (1034 <usart_init+0x29c>)
-     f32:	7889      	ldrb	r1, [r1, #2]
-     f34:	0789      	lsls	r1, r1, #30
-     f36:	d501      	bpl.n	f3c <usart_init+0x1a4>
-     f38:	2180      	movs	r1, #128	; 0x80
-     f3a:	430b      	orrs	r3, r1
-     f3c:	6838      	ldr	r0, [r7, #0]
-     f3e:	69c1      	ldr	r1, [r0, #28]
-     f40:	2900      	cmp	r1, #0
-     f42:	d1fc      	bne.n	f3e <usart_init+0x1a6>
-     f44:	9903      	ldr	r1, [sp, #12]
-     f46:	604a      	str	r2, [r1, #4]
-     f48:	6839      	ldr	r1, [r7, #0]
-     f4a:	69ca      	ldr	r2, [r1, #28]
-     f4c:	2a00      	cmp	r2, #0
-     f4e:	d1fc      	bne.n	f4a <usart_init+0x1b2>
-     f50:	9903      	ldr	r1, [sp, #12]
-     f52:	ad0d      	add	r5, sp, #52	; 0x34
-     f54:	600b      	str	r3, [r1, #0]
-     f56:	2380      	movs	r3, #128	; 0x80
-     f58:	702b      	strb	r3, [r5, #0]
-     f5a:	6b23      	ldr	r3, [r4, #48]	; 0x30
-     f5c:	706a      	strb	r2, [r5, #1]
-     f5e:	930e      	str	r3, [sp, #56]	; 0x38
-     f60:	6b63      	ldr	r3, [r4, #52]	; 0x34
-     f62:	70ea      	strb	r2, [r5, #3]
-     f64:	6073      	str	r3, [r6, #4]
-     f66:	6ba3      	ldr	r3, [r4, #56]	; 0x38
-     f68:	70aa      	strb	r2, [r5, #2]
-     f6a:	60b3      	str	r3, [r6, #8]
-     f6c:	6be3      	ldr	r3, [r4, #60]	; 0x3c
-     f6e:	0014      	movs	r4, r2
-     f70:	60f3      	str	r3, [r6, #12]
-     f72:	00a3      	lsls	r3, r4, #2
-     f74:	58f0      	ldr	r0, [r6, r3]
-     f76:	b2e1      	uxtb	r1, r4
-     f78:	2800      	cmp	r0, #0
-     f7a:	d102      	bne.n	f82 <usart_init+0x1ea>
-     f7c:	9804      	ldr	r0, [sp, #16]
-     f7e:	4b2e      	ldr	r3, [pc, #184]	; (1038 <usart_init+0x2a0>)
-     f80:	4798      	blx	r3
-     f82:	1c43      	adds	r3, r0, #1
-     f84:	d005      	beq.n	f92 <usart_init+0x1fa>
-     f86:	7028      	strb	r0, [r5, #0]
-     f88:	0c00      	lsrs	r0, r0, #16
-     f8a:	b2c0      	uxtb	r0, r0
-     f8c:	0029      	movs	r1, r5
-     f8e:	4b2b      	ldr	r3, [pc, #172]	; (103c <usart_init+0x2a4>)
-     f90:	4798      	blx	r3
-     f92:	3401      	adds	r4, #1
-     f94:	2c04      	cmp	r4, #4
-     f96:	d1ec      	bne.n	f72 <usart_init+0x1da>
-     f98:	003b      	movs	r3, r7
-     f9a:	2400      	movs	r4, #0
-     f9c:	3330      	adds	r3, #48	; 0x30
-     f9e:	85fc      	strh	r4, [r7, #46]	; 0x2e
-     fa0:	60fc      	str	r4, [r7, #12]
-     fa2:	613c      	str	r4, [r7, #16]
-     fa4:	617c      	str	r4, [r7, #20]
-     fa6:	61bc      	str	r4, [r7, #24]
-     fa8:	61fc      	str	r4, [r7, #28]
-     faa:	623c      	str	r4, [r7, #32]
-     fac:	62bc      	str	r4, [r7, #40]	; 0x28
-     fae:	627c      	str	r4, [r7, #36]	; 0x24
-     fb0:	85bc      	strh	r4, [r7, #44]	; 0x2c
-     fb2:	709c      	strb	r4, [r3, #2]
-     fb4:	701c      	strb	r4, [r3, #0]
-     fb6:	705c      	strb	r4, [r3, #1]
-     fb8:	70dc      	strb	r4, [r3, #3]
-     fba:	6838      	ldr	r0, [r7, #0]
-     fbc:	4b16      	ldr	r3, [pc, #88]	; (1018 <usart_init+0x280>)
-     fbe:	4798      	blx	r3
-     fc0:	0005      	movs	r5, r0
-     fc2:	4b1f      	ldr	r3, [pc, #124]	; (1040 <usart_init+0x2a8>)
-     fc4:	491f      	ldr	r1, [pc, #124]	; (1044 <usart_init+0x2ac>)
-     fc6:	4798      	blx	r3
-     fc8:	0020      	movs	r0, r4
-     fca:	4b1f      	ldr	r3, [pc, #124]	; (1048 <usart_init+0x2b0>)
-     fcc:	00ad      	lsls	r5, r5, #2
-     fce:	50ef      	str	r7, [r5, r3]
-     fd0:	b013      	add	sp, #76	; 0x4c
-     fd2:	bdf0      	pop	{r4, r5, r6, r7, pc}
-     fd4:	2608      	movs	r6, #8
-     fd6:	2501      	movs	r5, #1
-     fd8:	e742      	b.n	e60 <usart_init+0xc8>
-     fda:	7fdb      	ldrb	r3, [r3, #31]
-     fdc:	2b00      	cmp	r3, #0
-     fde:	d007      	beq.n	ff0 <usart_init+0x258>
-     fe0:	002b      	movs	r3, r5
-     fe2:	9600      	str	r6, [sp, #0]
-     fe4:	6aa1      	ldr	r1, [r4, #40]	; 0x28
-     fe6:	6a20      	ldr	r0, [r4, #32]
-     fe8:	aa0e      	add	r2, sp, #56	; 0x38
-     fea:	4d18      	ldr	r5, [pc, #96]	; (104c <usart_init+0x2b4>)
-     fec:	47a8      	blx	r5
-     fee:	e75b      	b.n	ea8 <usart_init+0x110>
-     ff0:	6a23      	ldr	r3, [r4, #32]
-     ff2:	b2c0      	uxtb	r0, r0
-     ff4:	930b      	str	r3, [sp, #44]	; 0x2c
-     ff6:	4b0d      	ldr	r3, [pc, #52]	; (102c <usart_init+0x294>)
-     ff8:	4798      	blx	r3
-     ffa:	9600      	str	r6, [sp, #0]
-     ffc:	0001      	movs	r1, r0
-     ffe:	002b      	movs	r3, r5
-    1000:	aa0e      	add	r2, sp, #56	; 0x38
-    1002:	980b      	ldr	r0, [sp, #44]	; 0x2c
-    1004:	e7f1      	b.n	fea <usart_init+0x252>
-    1006:	7ee1      	ldrb	r1, [r4, #27]
-    1008:	2900      	cmp	r1, #0
-    100a:	d100      	bne.n	100e <usart_init+0x276>
-    100c:	e78b      	b.n	f26 <usart_init+0x18e>
-    100e:	2180      	movs	r1, #128	; 0x80
-    1010:	04c9      	lsls	r1, r1, #19
-    1012:	430b      	orrs	r3, r1
-    1014:	e787      	b.n	f26 <usart_init+0x18e>
-    1016:	46c0      	nop			; (mov r8, r8)
-    1018:	00000a7d 	.word	0x00000a7d
-    101c:	40000400 	.word	0x40000400
-    1020:	0000184d 	.word	0x0000184d
-    1024:	000017c5 	.word	0x000017c5
-    1028:	000008dd 	.word	0x000008dd
-    102c:	00001869 	.word	0x00001869
-    1030:	0000081d 	.word	0x0000081d
-    1034:	41002000 	.word	0x41002000
-    1038:	00000921 	.word	0x00000921
-    103c:	00001921 	.word	0x00001921
-    1040:	00001249 	.word	0x00001249
-    1044:	000010dd 	.word	0x000010dd
-    1048:	20000284 	.word	0x20000284
-    104c:	00000845 	.word	0x00000845
-
-00001050 <usart_write_wait>:
-    1050:	79c2      	ldrb	r2, [r0, #7]
-    1052:	231c      	movs	r3, #28
-    1054:	2a00      	cmp	r2, #0
-    1056:	d00a      	beq.n	106e <usart_write_wait+0x1e>
-    1058:	8dc2      	ldrh	r2, [r0, #46]	; 0x2e
-    105a:	3b17      	subs	r3, #23
-    105c:	2a00      	cmp	r2, #0
-    105e:	d106      	bne.n	106e <usart_write_wait+0x1e>
-    1060:	6803      	ldr	r3, [r0, #0]
-    1062:	3202      	adds	r2, #2
-    1064:	8519      	strh	r1, [r3, #40]	; 0x28
-    1066:	7e19      	ldrb	r1, [r3, #24]
-    1068:	4211      	tst	r1, r2
-    106a:	d0fc      	beq.n	1066 <usart_write_wait+0x16>
-    106c:	2300      	movs	r3, #0
-    106e:	0018      	movs	r0, r3
-    1070:	4770      	bx	lr
-
-00001072 <usart_read_wait>:
-    1072:	b510      	push	{r4, lr}
-    1074:	7982      	ldrb	r2, [r0, #6]
-    1076:	231c      	movs	r3, #28
-    1078:	2a00      	cmp	r2, #0
-    107a:	d011      	beq.n	10a0 <usart_read_wait+0x2e>
-    107c:	8d82      	ldrh	r2, [r0, #44]	; 0x2c
-    107e:	3b17      	subs	r3, #23
-    1080:	2a00      	cmp	r2, #0
-    1082:	d10d      	bne.n	10a0 <usart_read_wait+0x2e>
-    1084:	6802      	ldr	r2, [r0, #0]
-    1086:	2004      	movs	r0, #4
-    1088:	7e14      	ldrb	r4, [r2, #24]
-    108a:	4204      	tst	r4, r0
-    108c:	d008      	beq.n	10a0 <usart_read_wait+0x2e>
-    108e:	8b53      	ldrh	r3, [r2, #26]
-    1090:	b2db      	uxtb	r3, r3
-    1092:	069c      	lsls	r4, r3, #26
-    1094:	d01d      	beq.n	10d2 <usart_read_wait+0x60>
-    1096:	2402      	movs	r4, #2
-    1098:	4223      	tst	r3, r4
-    109a:	d003      	beq.n	10a4 <usart_read_wait+0x32>
-    109c:	231a      	movs	r3, #26
-    109e:	8354      	strh	r4, [r2, #26]
-    10a0:	0018      	movs	r0, r3
-    10a2:	bd10      	pop	{r4, pc}
-    10a4:	4203      	tst	r3, r0
-    10a6:	d002      	beq.n	10ae <usart_read_wait+0x3c>
-    10a8:	8350      	strh	r0, [r2, #26]
-    10aa:	231e      	movs	r3, #30
-    10ac:	e7f8      	b.n	10a0 <usart_read_wait+0x2e>
-    10ae:	2001      	movs	r0, #1
-    10b0:	4203      	tst	r3, r0
-    10b2:	d002      	beq.n	10ba <usart_read_wait+0x48>
-    10b4:	8350      	strh	r0, [r2, #26]
-    10b6:	2313      	movs	r3, #19
-    10b8:	e7f2      	b.n	10a0 <usart_read_wait+0x2e>
-    10ba:	2010      	movs	r0, #16
-    10bc:	4203      	tst	r3, r0
-    10be:	d002      	beq.n	10c6 <usart_read_wait+0x54>
-    10c0:	8350      	strh	r0, [r2, #26]
-    10c2:	2342      	movs	r3, #66	; 0x42
-    10c4:	e7ec      	b.n	10a0 <usart_read_wait+0x2e>
-    10c6:	2020      	movs	r0, #32
-    10c8:	4203      	tst	r3, r0
-    10ca:	d002      	beq.n	10d2 <usart_read_wait+0x60>
-    10cc:	8350      	strh	r0, [r2, #26]
-    10ce:	2341      	movs	r3, #65	; 0x41
-    10d0:	e7e6      	b.n	10a0 <usart_read_wait+0x2e>
-    10d2:	8d13      	ldrh	r3, [r2, #40]	; 0x28
-    10d4:	800b      	strh	r3, [r1, #0]
-    10d6:	2300      	movs	r3, #0
-    10d8:	e7e2      	b.n	10a0 <usart_read_wait+0x2e>
-	...
-
-000010dc <_usart_interrupt_handler>:
-    10dc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    10de:	4b58      	ldr	r3, [pc, #352]	; (1240 <_usart_interrupt_handler+0x164>)
-    10e0:	0080      	lsls	r0, r0, #2
-    10e2:	58c4      	ldr	r4, [r0, r3]
-    10e4:	6825      	ldr	r5, [r4, #0]
-    10e6:	69eb      	ldr	r3, [r5, #28]
-    10e8:	2b00      	cmp	r3, #0
-    10ea:	d1fc      	bne.n	10e6 <_usart_interrupt_handler+0xa>
-    10ec:	7e2b      	ldrb	r3, [r5, #24]
-    10ee:	7daf      	ldrb	r7, [r5, #22]
-    10f0:	401f      	ands	r7, r3
-    10f2:	0023      	movs	r3, r4
-    10f4:	3330      	adds	r3, #48	; 0x30
-    10f6:	781a      	ldrb	r2, [r3, #0]
-    10f8:	785e      	ldrb	r6, [r3, #1]
-    10fa:	2301      	movs	r3, #1
-    10fc:	4016      	ands	r6, r2
-    10fe:	421f      	tst	r7, r3
-    1100:	d019      	beq.n	1136 <_usart_interrupt_handler+0x5a>
-    1102:	8de2      	ldrh	r2, [r4, #46]	; 0x2e
-    1104:	2a00      	cmp	r2, #0
-    1106:	d100      	bne.n	110a <_usart_interrupt_handler+0x2e>
-    1108:	e072      	b.n	11f0 <_usart_interrupt_handler+0x114>
-    110a:	6aa2      	ldr	r2, [r4, #40]	; 0x28
-    110c:	1c51      	adds	r1, r2, #1
-    110e:	7813      	ldrb	r3, [r2, #0]
-    1110:	62a1      	str	r1, [r4, #40]	; 0x28
-    1112:	7961      	ldrb	r1, [r4, #5]
-    1114:	b2db      	uxtb	r3, r3
-    1116:	2901      	cmp	r1, #1
-    1118:	d064      	beq.n	11e4 <_usart_interrupt_handler+0x108>
-    111a:	b29b      	uxth	r3, r3
-    111c:	05db      	lsls	r3, r3, #23
-    111e:	0ddb      	lsrs	r3, r3, #23
-    1120:	852b      	strh	r3, [r5, #40]	; 0x28
-    1122:	8de3      	ldrh	r3, [r4, #46]	; 0x2e
-    1124:	3b01      	subs	r3, #1
-    1126:	b29b      	uxth	r3, r3
-    1128:	85e3      	strh	r3, [r4, #46]	; 0x2e
-    112a:	2b00      	cmp	r3, #0
-    112c:	d103      	bne.n	1136 <_usart_interrupt_handler+0x5a>
-    112e:	3301      	adds	r3, #1
-    1130:	752b      	strb	r3, [r5, #20]
-    1132:	3301      	adds	r3, #1
-    1134:	75ab      	strb	r3, [r5, #22]
-    1136:	2302      	movs	r3, #2
-    1138:	421f      	tst	r7, r3
-    113a:	d009      	beq.n	1150 <_usart_interrupt_handler+0x74>
-    113c:	752b      	strb	r3, [r5, #20]
-    113e:	0023      	movs	r3, r4
-    1140:	2200      	movs	r2, #0
-    1142:	3333      	adds	r3, #51	; 0x33
-    1144:	701a      	strb	r2, [r3, #0]
-    1146:	07f3      	lsls	r3, r6, #31
-    1148:	d502      	bpl.n	1150 <_usart_interrupt_handler+0x74>
-    114a:	0020      	movs	r0, r4
-    114c:	68e3      	ldr	r3, [r4, #12]
-    114e:	4798      	blx	r3
-    1150:	2304      	movs	r3, #4
-    1152:	421f      	tst	r7, r3
-    1154:	d027      	beq.n	11a6 <_usart_interrupt_handler+0xca>
-    1156:	8da2      	ldrh	r2, [r4, #44]	; 0x2c
-    1158:	2a00      	cmp	r2, #0
-    115a:	d100      	bne.n	115e <_usart_interrupt_handler+0x82>
-    115c:	e06d      	b.n	123a <_usart_interrupt_handler+0x15e>
-    115e:	8b6b      	ldrh	r3, [r5, #26]
-    1160:	b2db      	uxtb	r3, r3
-    1162:	071a      	lsls	r2, r3, #28
-    1164:	d446      	bmi.n	11f4 <_usart_interrupt_handler+0x118>
-    1166:	223f      	movs	r2, #63	; 0x3f
-    1168:	4013      	ands	r3, r2
-    116a:	d045      	beq.n	11f8 <_usart_interrupt_handler+0x11c>
-    116c:	2202      	movs	r2, #2
-    116e:	211a      	movs	r1, #26
-    1170:	4213      	tst	r3, r2
-    1172:	d10f      	bne.n	1194 <_usart_interrupt_handler+0xb8>
-    1174:	2204      	movs	r2, #4
-    1176:	211e      	movs	r1, #30
-    1178:	4213      	tst	r3, r2
-    117a:	d10b      	bne.n	1194 <_usart_interrupt_handler+0xb8>
-    117c:	2201      	movs	r2, #1
-    117e:	2113      	movs	r1, #19
-    1180:	4213      	tst	r3, r2
-    1182:	d107      	bne.n	1194 <_usart_interrupt_handler+0xb8>
-    1184:	2210      	movs	r2, #16
-    1186:	2142      	movs	r1, #66	; 0x42
-    1188:	4213      	tst	r3, r2
-    118a:	d103      	bne.n	1194 <_usart_interrupt_handler+0xb8>
-    118c:	2220      	movs	r2, #32
-    118e:	4213      	tst	r3, r2
-    1190:	d004      	beq.n	119c <_usart_interrupt_handler+0xc0>
-    1192:	2141      	movs	r1, #65	; 0x41
-    1194:	0023      	movs	r3, r4
-    1196:	3332      	adds	r3, #50	; 0x32
-    1198:	7019      	strb	r1, [r3, #0]
-    119a:	836a      	strh	r2, [r5, #26]
-    119c:	0773      	lsls	r3, r6, #29
-    119e:	d502      	bpl.n	11a6 <_usart_interrupt_handler+0xca>
-    11a0:	0020      	movs	r0, r4
-    11a2:	6963      	ldr	r3, [r4, #20]
-    11a4:	4798      	blx	r3
-    11a6:	2310      	movs	r3, #16
-    11a8:	421f      	tst	r7, r3
-    11aa:	d006      	beq.n	11ba <_usart_interrupt_handler+0xde>
-    11ac:	752b      	strb	r3, [r5, #20]
-    11ae:	762b      	strb	r3, [r5, #24]
-    11b0:	421e      	tst	r6, r3
-    11b2:	d002      	beq.n	11ba <_usart_interrupt_handler+0xde>
-    11b4:	0020      	movs	r0, r4
-    11b6:	69e3      	ldr	r3, [r4, #28]
-    11b8:	4798      	blx	r3
-    11ba:	2320      	movs	r3, #32
-    11bc:	421f      	tst	r7, r3
-    11be:	d006      	beq.n	11ce <_usart_interrupt_handler+0xf2>
-    11c0:	752b      	strb	r3, [r5, #20]
-    11c2:	762b      	strb	r3, [r5, #24]
-    11c4:	0733      	lsls	r3, r6, #28
-    11c6:	d502      	bpl.n	11ce <_usart_interrupt_handler+0xf2>
-    11c8:	0020      	movs	r0, r4
-    11ca:	69a3      	ldr	r3, [r4, #24]
-    11cc:	4798      	blx	r3
-    11ce:	2308      	movs	r3, #8
-    11d0:	421f      	tst	r7, r3
-    11d2:	d006      	beq.n	11e2 <_usart_interrupt_handler+0x106>
-    11d4:	752b      	strb	r3, [r5, #20]
-    11d6:	762b      	strb	r3, [r5, #24]
-    11d8:	06b3      	lsls	r3, r6, #26
-    11da:	d502      	bpl.n	11e2 <_usart_interrupt_handler+0x106>
-    11dc:	6a23      	ldr	r3, [r4, #32]
-    11de:	0020      	movs	r0, r4
-    11e0:	4798      	blx	r3
-    11e2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    11e4:	7851      	ldrb	r1, [r2, #1]
-    11e6:	3202      	adds	r2, #2
-    11e8:	0209      	lsls	r1, r1, #8
-    11ea:	430b      	orrs	r3, r1
-    11ec:	62a2      	str	r2, [r4, #40]	; 0x28
-    11ee:	e795      	b.n	111c <_usart_interrupt_handler+0x40>
-    11f0:	752b      	strb	r3, [r5, #20]
-    11f2:	e7a0      	b.n	1136 <_usart_interrupt_handler+0x5a>
-    11f4:	2237      	movs	r2, #55	; 0x37
-    11f6:	e7b7      	b.n	1168 <_usart_interrupt_handler+0x8c>
-    11f8:	8d2b      	ldrh	r3, [r5, #40]	; 0x28
-    11fa:	6a61      	ldr	r1, [r4, #36]	; 0x24
-    11fc:	05db      	lsls	r3, r3, #23
-    11fe:	0ddb      	lsrs	r3, r3, #23
-    1200:	b2da      	uxtb	r2, r3
-    1202:	700a      	strb	r2, [r1, #0]
-    1204:	6a62      	ldr	r2, [r4, #36]	; 0x24
-    1206:	1c51      	adds	r1, r2, #1
-    1208:	6261      	str	r1, [r4, #36]	; 0x24
-    120a:	7961      	ldrb	r1, [r4, #5]
-    120c:	2901      	cmp	r1, #1
-    120e:	d104      	bne.n	121a <_usart_interrupt_handler+0x13e>
-    1210:	0a1b      	lsrs	r3, r3, #8
-    1212:	7053      	strb	r3, [r2, #1]
-    1214:	6a63      	ldr	r3, [r4, #36]	; 0x24
-    1216:	3301      	adds	r3, #1
-    1218:	6263      	str	r3, [r4, #36]	; 0x24
-    121a:	8da3      	ldrh	r3, [r4, #44]	; 0x2c
-    121c:	3b01      	subs	r3, #1
-    121e:	b29b      	uxth	r3, r3
-    1220:	85a3      	strh	r3, [r4, #44]	; 0x2c
-    1222:	2b00      	cmp	r3, #0
-    1224:	d1bf      	bne.n	11a6 <_usart_interrupt_handler+0xca>
-    1226:	2204      	movs	r2, #4
-    1228:	752a      	strb	r2, [r5, #20]
-    122a:	0022      	movs	r2, r4
-    122c:	3232      	adds	r2, #50	; 0x32
-    122e:	7013      	strb	r3, [r2, #0]
-    1230:	07b3      	lsls	r3, r6, #30
-    1232:	d5b8      	bpl.n	11a6 <_usart_interrupt_handler+0xca>
-    1234:	0020      	movs	r0, r4
-    1236:	6923      	ldr	r3, [r4, #16]
-    1238:	e7b4      	b.n	11a4 <_usart_interrupt_handler+0xc8>
-    123a:	752b      	strb	r3, [r5, #20]
-    123c:	e7b3      	b.n	11a6 <_usart_interrupt_handler+0xca>
-    123e:	46c0      	nop			; (mov r8, r8)
-    1240:	20000284 	.word	0x20000284
-
-00001244 <_sercom_default_handler>:
-    1244:	4770      	bx	lr
-	...
-
-00001248 <_sercom_set_handler>:
-    1248:	b5f0      	push	{r4, r5, r6, r7, lr}
-    124a:	4c09      	ldr	r4, [pc, #36]	; (1270 <_sercom_set_handler+0x28>)
-    124c:	4a09      	ldr	r2, [pc, #36]	; (1274 <_sercom_set_handler+0x2c>)
-    124e:	7823      	ldrb	r3, [r4, #0]
-    1250:	2b00      	cmp	r3, #0
-    1252:	d109      	bne.n	1268 <_sercom_set_handler+0x20>
-    1254:	001e      	movs	r6, r3
-    1256:	4f08      	ldr	r7, [pc, #32]	; (1278 <_sercom_set_handler+0x30>)
-    1258:	4d08      	ldr	r5, [pc, #32]	; (127c <_sercom_set_handler+0x34>)
-    125a:	50d7      	str	r7, [r2, r3]
-    125c:	50ee      	str	r6, [r5, r3]
-    125e:	3304      	adds	r3, #4
-    1260:	2b18      	cmp	r3, #24
-    1262:	d1fa      	bne.n	125a <_sercom_set_handler+0x12>
-    1264:	3b17      	subs	r3, #23
-    1266:	7023      	strb	r3, [r4, #0]
-    1268:	0080      	lsls	r0, r0, #2
-    126a:	5011      	str	r1, [r2, r0]
-    126c:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    126e:	46c0      	nop			; (mov r8, r8)
-    1270:	2000018c 	.word	0x2000018c
-    1274:	20000190 	.word	0x20000190
-    1278:	00001245 	.word	0x00001245
-    127c:	20000284 	.word	0x20000284
-
-00001280 <_sercom_get_interrupt_vector>:
-    1280:	b507      	push	{r0, r1, r2, lr}
-    1282:	2309      	movs	r3, #9
-    1284:	466a      	mov	r2, sp
-    1286:	7013      	strb	r3, [r2, #0]
-    1288:	3301      	adds	r3, #1
-    128a:	7053      	strb	r3, [r2, #1]
-    128c:	3301      	adds	r3, #1
-    128e:	7093      	strb	r3, [r2, #2]
-    1290:	3301      	adds	r3, #1
-    1292:	70d3      	strb	r3, [r2, #3]
-    1294:	3301      	adds	r3, #1
-    1296:	7113      	strb	r3, [r2, #4]
-    1298:	3301      	adds	r3, #1
-    129a:	7153      	strb	r3, [r2, #5]
-    129c:	4b02      	ldr	r3, [pc, #8]	; (12a8 <_sercom_get_interrupt_vector+0x28>)
-    129e:	4798      	blx	r3
-    12a0:	466b      	mov	r3, sp
-    12a2:	5618      	ldrsb	r0, [r3, r0]
-    12a4:	bd0e      	pop	{r1, r2, r3, pc}
-    12a6:	46c0      	nop			; (mov r8, r8)
-    12a8:	00000a7d 	.word	0x00000a7d
-
-000012ac <SERCOM0_Handler>:
-    12ac:	b510      	push	{r4, lr}
-    12ae:	4b02      	ldr	r3, [pc, #8]	; (12b8 <SERCOM0_Handler+0xc>)
-    12b0:	2000      	movs	r0, #0
-    12b2:	681b      	ldr	r3, [r3, #0]
-    12b4:	4798      	blx	r3
-    12b6:	bd10      	pop	{r4, pc}
-    12b8:	20000190 	.word	0x20000190
-
-000012bc <SERCOM1_Handler>:
-    12bc:	b510      	push	{r4, lr}
-    12be:	4b02      	ldr	r3, [pc, #8]	; (12c8 <SERCOM1_Handler+0xc>)
-    12c0:	2001      	movs	r0, #1
-    12c2:	685b      	ldr	r3, [r3, #4]
-    12c4:	4798      	blx	r3
-    12c6:	bd10      	pop	{r4, pc}
-    12c8:	20000190 	.word	0x20000190
-
-000012cc <SERCOM2_Handler>:
-    12cc:	b510      	push	{r4, lr}
-    12ce:	4b02      	ldr	r3, [pc, #8]	; (12d8 <SERCOM2_Handler+0xc>)
-    12d0:	2002      	movs	r0, #2
-    12d2:	689b      	ldr	r3, [r3, #8]
-    12d4:	4798      	blx	r3
-    12d6:	bd10      	pop	{r4, pc}
-    12d8:	20000190 	.word	0x20000190
-
-000012dc <SERCOM3_Handler>:
-    12dc:	b510      	push	{r4, lr}
-    12de:	4b02      	ldr	r3, [pc, #8]	; (12e8 <SERCOM3_Handler+0xc>)
-    12e0:	2003      	movs	r0, #3
-    12e2:	68db      	ldr	r3, [r3, #12]
-    12e4:	4798      	blx	r3
-    12e6:	bd10      	pop	{r4, pc}
-    12e8:	20000190 	.word	0x20000190
-
-000012ec <SERCOM4_Handler>:
-    12ec:	b510      	push	{r4, lr}
-    12ee:	4b02      	ldr	r3, [pc, #8]	; (12f8 <SERCOM4_Handler+0xc>)
-    12f0:	2004      	movs	r0, #4
-    12f2:	691b      	ldr	r3, [r3, #16]
-    12f4:	4798      	blx	r3
-    12f6:	bd10      	pop	{r4, pc}
-    12f8:	20000190 	.word	0x20000190
-
-000012fc <SERCOM5_Handler>:
-    12fc:	b510      	push	{r4, lr}
-    12fe:	4b02      	ldr	r3, [pc, #8]	; (1308 <SERCOM5_Handler+0xc>)
-    1300:	2005      	movs	r0, #5
-    1302:	695b      	ldr	r3, [r3, #20]
-    1304:	4798      	blx	r3
-    1306:	bd10      	pop	{r4, pc}
-    1308:	20000190 	.word	0x20000190
-
-0000130c <delay_init>:
-    130c:	b570      	push	{r4, r5, r6, lr}
-    130e:	4b09      	ldr	r3, [pc, #36]	; (1334 <delay_init+0x28>)
-    1310:	2000      	movs	r0, #0
-    1312:	4798      	blx	r3
-    1314:	21fa      	movs	r1, #250	; 0xfa
-    1316:	4c08      	ldr	r4, [pc, #32]	; (1338 <delay_init+0x2c>)
-    1318:	0089      	lsls	r1, r1, #2
-    131a:	0005      	movs	r5, r0
-    131c:	47a0      	blx	r4
-    131e:	4b07      	ldr	r3, [pc, #28]	; (133c <delay_init+0x30>)
-    1320:	4907      	ldr	r1, [pc, #28]	; (1340 <delay_init+0x34>)
-    1322:	6018      	str	r0, [r3, #0]
-    1324:	0028      	movs	r0, r5
-    1326:	47a0      	blx	r4
-    1328:	2205      	movs	r2, #5
-    132a:	4b06      	ldr	r3, [pc, #24]	; (1344 <delay_init+0x38>)
-    132c:	6018      	str	r0, [r3, #0]
-    132e:	4b06      	ldr	r3, [pc, #24]	; (1348 <delay_init+0x3c>)
-    1330:	601a      	str	r2, [r3, #0]
-    1332:	bd70      	pop	{r4, r5, r6, pc}
-    1334:	0000173d 	.word	0x0000173d
-    1338:	00001b5d 	.word	0x00001b5d
-    133c:	2000000c 	.word	0x2000000c
-    1340:	000f4240 	.word	0x000f4240
-    1344:	20000010 	.word	0x20000010
-    1348:	e000e010 	.word	0xe000e010
-
-0000134c <delay_cycles_ms>:
-    134c:	b530      	push	{r4, r5, lr}
-    134e:	2480      	movs	r4, #128	; 0x80
-    1350:	2100      	movs	r1, #0
-    1352:	4b07      	ldr	r3, [pc, #28]	; (1370 <delay_cycles_ms+0x24>)
-    1354:	0264      	lsls	r4, r4, #9
-    1356:	681a      	ldr	r2, [r3, #0]
-    1358:	4b06      	ldr	r3, [pc, #24]	; (1374 <delay_cycles_ms+0x28>)
-    135a:	3801      	subs	r0, #1
-    135c:	d200      	bcs.n	1360 <delay_cycles_ms+0x14>
-    135e:	bd30      	pop	{r4, r5, pc}
-    1360:	2a00      	cmp	r2, #0
-    1362:	d0fa      	beq.n	135a <delay_cycles_ms+0xe>
-    1364:	605a      	str	r2, [r3, #4]
-    1366:	6099      	str	r1, [r3, #8]
-    1368:	681d      	ldr	r5, [r3, #0]
-    136a:	4225      	tst	r5, r4
-    136c:	d0fc      	beq.n	1368 <delay_cycles_ms+0x1c>
-    136e:	e7f4      	b.n	135a <delay_cycles_ms+0xe>
-    1370:	2000000c 	.word	0x2000000c
-    1374:	e000e010 	.word	0xe000e010
-
-00001378 <cpu_irq_enter_critical>:
-    1378:	4b09      	ldr	r3, [pc, #36]	; (13a0 <cpu_irq_enter_critical+0x28>)
-    137a:	6819      	ldr	r1, [r3, #0]
-    137c:	2900      	cmp	r1, #0
-    137e:	d10b      	bne.n	1398 <cpu_irq_enter_critical+0x20>
-    1380:	f3ef 8010 	mrs	r0, PRIMASK
-    1384:	4a07      	ldr	r2, [pc, #28]	; (13a4 <cpu_irq_enter_critical+0x2c>)
-    1386:	2800      	cmp	r0, #0
-    1388:	d105      	bne.n	1396 <cpu_irq_enter_critical+0x1e>
-    138a:	b672      	cpsid	i
-    138c:	f3bf 8f5f 	dmb	sy
-    1390:	4905      	ldr	r1, [pc, #20]	; (13a8 <cpu_irq_enter_critical+0x30>)
-    1392:	7008      	strb	r0, [r1, #0]
-    1394:	2101      	movs	r1, #1
-    1396:	7011      	strb	r1, [r2, #0]
-    1398:	681a      	ldr	r2, [r3, #0]
-    139a:	3201      	adds	r2, #1
-    139c:	601a      	str	r2, [r3, #0]
-    139e:	4770      	bx	lr
-    13a0:	200001a8 	.word	0x200001a8
-    13a4:	200001ac 	.word	0x200001ac
-    13a8:	20000014 	.word	0x20000014
-
-000013ac <cpu_irq_leave_critical>:
-    13ac:	4b08      	ldr	r3, [pc, #32]	; (13d0 <cpu_irq_leave_critical+0x24>)
-    13ae:	681a      	ldr	r2, [r3, #0]
-    13b0:	3a01      	subs	r2, #1
-    13b2:	601a      	str	r2, [r3, #0]
-    13b4:	681b      	ldr	r3, [r3, #0]
-    13b6:	2b00      	cmp	r3, #0
-    13b8:	d109      	bne.n	13ce <cpu_irq_leave_critical+0x22>
-    13ba:	4b06      	ldr	r3, [pc, #24]	; (13d4 <cpu_irq_leave_critical+0x28>)
-    13bc:	781b      	ldrb	r3, [r3, #0]
-    13be:	2b00      	cmp	r3, #0
-    13c0:	d005      	beq.n	13ce <cpu_irq_leave_critical+0x22>
-    13c2:	2201      	movs	r2, #1
-    13c4:	4b04      	ldr	r3, [pc, #16]	; (13d8 <cpu_irq_leave_critical+0x2c>)
-    13c6:	701a      	strb	r2, [r3, #0]
-    13c8:	f3bf 8f5f 	dmb	sy
-    13cc:	b662      	cpsie	i
-    13ce:	4770      	bx	lr
-    13d0:	200001a8 	.word	0x200001a8
-    13d4:	200001ac 	.word	0x200001ac
-    13d8:	20000014 	.word	0x20000014
-
-000013dc <system_board_init>:
-    13dc:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    13de:	2501      	movs	r5, #1
-    13e0:	2700      	movs	r7, #0
-    13e2:	ac01      	add	r4, sp, #4
-    13e4:	4e08      	ldr	r6, [pc, #32]	; (1408 <system_board_init+0x2c>)
-    13e6:	0021      	movs	r1, r4
-    13e8:	203e      	movs	r0, #62	; 0x3e
-    13ea:	7065      	strb	r5, [r4, #1]
-    13ec:	70a7      	strb	r7, [r4, #2]
-    13ee:	7025      	strb	r5, [r4, #0]
-    13f0:	47b0      	blx	r6
-    13f2:	2280      	movs	r2, #128	; 0x80
-    13f4:	4b05      	ldr	r3, [pc, #20]	; (140c <system_board_init+0x30>)
-    13f6:	05d2      	lsls	r2, r2, #23
-    13f8:	601a      	str	r2, [r3, #0]
-    13fa:	0021      	movs	r1, r4
-    13fc:	200f      	movs	r0, #15
-    13fe:	7027      	strb	r7, [r4, #0]
-    1400:	7065      	strb	r5, [r4, #1]
-    1402:	47b0      	blx	r6
-    1404:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
-    1406:	46c0      	nop			; (mov r8, r8)
-    1408:	00001411 	.word	0x00001411
-    140c:	41004498 	.word	0x41004498
-
-00001410 <port_pin_set_config>:
-    1410:	b507      	push	{r0, r1, r2, lr}
-    1412:	2280      	movs	r2, #128	; 0x80
-    1414:	ab01      	add	r3, sp, #4
-    1416:	701a      	strb	r2, [r3, #0]
-    1418:	780a      	ldrb	r2, [r1, #0]
-    141a:	705a      	strb	r2, [r3, #1]
-    141c:	784a      	ldrb	r2, [r1, #1]
-    141e:	709a      	strb	r2, [r3, #2]
-    1420:	788a      	ldrb	r2, [r1, #2]
-    1422:	0019      	movs	r1, r3
-    1424:	70da      	strb	r2, [r3, #3]
-    1426:	4b01      	ldr	r3, [pc, #4]	; (142c <port_pin_set_config+0x1c>)
-    1428:	4798      	blx	r3
-    142a:	bd07      	pop	{r0, r1, r2, pc}
-    142c:	00001921 	.word	0x00001921
-
-00001430 <_system_dfll_wait_for_sync>:
-    1430:	2310      	movs	r3, #16
-    1432:	4902      	ldr	r1, [pc, #8]	; (143c <_system_dfll_wait_for_sync+0xc>)
-    1434:	68ca      	ldr	r2, [r1, #12]
-    1436:	421a      	tst	r2, r3
-    1438:	d0fc      	beq.n	1434 <_system_dfll_wait_for_sync+0x4>
-    143a:	4770      	bx	lr
-    143c:	40000800 	.word	0x40000800
-
-00001440 <system_clock_source_get_hz>:
-    1440:	b570      	push	{r4, r5, r6, lr}
-    1442:	2808      	cmp	r0, #8
-    1444:	d806      	bhi.n	1454 <system_clock_source_get_hz+0x14>
-    1446:	f000 fb7f 	bl	1b48 <__gnu_thumb1_case_uqi>
-    144a:	0508      	.short	0x0508
-    144c:	12303005 	.word	0x12303005
-    1450:	150b      	.short	0x150b
-    1452:	28          	.byte	0x28
-    1453:	00          	.byte	0x00
-    1454:	2400      	movs	r4, #0
-    1456:	0020      	movs	r0, r4
-    1458:	bd70      	pop	{r4, r5, r6, pc}
-    145a:	4b16      	ldr	r3, [pc, #88]	; (14b4 <system_clock_source_get_hz+0x74>)
-    145c:	691c      	ldr	r4, [r3, #16]
-    145e:	e7fa      	b.n	1456 <system_clock_source_get_hz+0x16>
-    1460:	4b15      	ldr	r3, [pc, #84]	; (14b8 <system_clock_source_get_hz+0x78>)
-    1462:	4c16      	ldr	r4, [pc, #88]	; (14bc <system_clock_source_get_hz+0x7c>)
-    1464:	6a1b      	ldr	r3, [r3, #32]
-    1466:	059b      	lsls	r3, r3, #22
-    1468:	0f9b      	lsrs	r3, r3, #30
-    146a:	40dc      	lsrs	r4, r3
-    146c:	e7f3      	b.n	1456 <system_clock_source_get_hz+0x16>
-    146e:	4b11      	ldr	r3, [pc, #68]	; (14b4 <system_clock_source_get_hz+0x74>)
-    1470:	695c      	ldr	r4, [r3, #20]
-    1472:	e7f0      	b.n	1456 <system_clock_source_get_hz+0x16>
-    1474:	4d0f      	ldr	r5, [pc, #60]	; (14b4 <system_clock_source_get_hz+0x74>)
-    1476:	2400      	movs	r4, #0
-    1478:	682b      	ldr	r3, [r5, #0]
-    147a:	079b      	lsls	r3, r3, #30
-    147c:	d5eb      	bpl.n	1456 <system_clock_source_get_hz+0x16>
-    147e:	4b10      	ldr	r3, [pc, #64]	; (14c0 <system_clock_source_get_hz+0x80>)
-    1480:	4798      	blx	r3
-    1482:	2224      	movs	r2, #36	; 0x24
-    1484:	682b      	ldr	r3, [r5, #0]
-    1486:	4013      	ands	r3, r2
-    1488:	2b04      	cmp	r3, #4
-    148a:	d111      	bne.n	14b0 <system_clock_source_get_hz+0x70>
-    148c:	0020      	movs	r0, r4
-    148e:	4b0d      	ldr	r3, [pc, #52]	; (14c4 <system_clock_source_get_hz+0x84>)
-    1490:	4798      	blx	r3
-    1492:	68ac      	ldr	r4, [r5, #8]
-    1494:	b2a4      	uxth	r4, r4
-    1496:	4344      	muls	r4, r0
-    1498:	e7dd      	b.n	1456 <system_clock_source_get_hz+0x16>
-    149a:	4b0b      	ldr	r3, [pc, #44]	; (14c8 <system_clock_source_get_hz+0x88>)
-    149c:	2400      	movs	r4, #0
-    149e:	781b      	ldrb	r3, [r3, #0]
-    14a0:	075b      	lsls	r3, r3, #29
-    14a2:	d5d8      	bpl.n	1456 <system_clock_source_get_hz+0x16>
-    14a4:	4b03      	ldr	r3, [pc, #12]	; (14b4 <system_clock_source_get_hz+0x74>)
-    14a6:	68dc      	ldr	r4, [r3, #12]
-    14a8:	e7d5      	b.n	1456 <system_clock_source_get_hz+0x16>
-    14aa:	2480      	movs	r4, #128	; 0x80
-    14ac:	0224      	lsls	r4, r4, #8
-    14ae:	e7d2      	b.n	1456 <system_clock_source_get_hz+0x16>
-    14b0:	4c06      	ldr	r4, [pc, #24]	; (14cc <system_clock_source_get_hz+0x8c>)
-    14b2:	e7d0      	b.n	1456 <system_clock_source_get_hz+0x16>
-    14b4:	200001b0 	.word	0x200001b0
-    14b8:	40000800 	.word	0x40000800
-    14bc:	007a1200 	.word	0x007a1200
-    14c0:	00001431 	.word	0x00001431
-    14c4:	00001869 	.word	0x00001869
-    14c8:	40000850 	.word	0x40000850
-    14cc:	02dc6c00 	.word	0x02dc6c00
-
-000014d0 <system_clock_source_osc8m_set_config>:
-    14d0:	b570      	push	{r4, r5, r6, lr}
-    14d2:	7884      	ldrb	r4, [r0, #2]
-    14d4:	7802      	ldrb	r2, [r0, #0]
-    14d6:	7845      	ldrb	r5, [r0, #1]
-    14d8:	2001      	movs	r0, #1
-    14da:	2640      	movs	r6, #64	; 0x40
-    14dc:	4005      	ands	r5, r0
-    14de:	4020      	ands	r0, r4
-    14e0:	2480      	movs	r4, #128	; 0x80
-    14e2:	4908      	ldr	r1, [pc, #32]	; (1504 <system_clock_source_osc8m_set_config+0x34>)
-    14e4:	01ad      	lsls	r5, r5, #6
-    14e6:	6a0b      	ldr	r3, [r1, #32]
-    14e8:	01c0      	lsls	r0, r0, #7
-    14ea:	43b3      	bics	r3, r6
-    14ec:	432b      	orrs	r3, r5
-    14ee:	43a3      	bics	r3, r4
-    14f0:	4303      	orrs	r3, r0
-    14f2:	2003      	movs	r0, #3
-    14f4:	4002      	ands	r2, r0
-    14f6:	4804      	ldr	r0, [pc, #16]	; (1508 <system_clock_source_osc8m_set_config+0x38>)
-    14f8:	0212      	lsls	r2, r2, #8
-    14fa:	4003      	ands	r3, r0
-    14fc:	4313      	orrs	r3, r2
-    14fe:	620b      	str	r3, [r1, #32]
-    1500:	bd70      	pop	{r4, r5, r6, pc}
-    1502:	46c0      	nop			; (mov r8, r8)
-    1504:	40000800 	.word	0x40000800
-    1508:	fffffcff 	.word	0xfffffcff
-
-0000150c <system_clock_source_enable>:
-    150c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    150e:	2808      	cmp	r0, #8
-    1510:	d806      	bhi.n	1520 <system_clock_source_enable+0x14>
-    1512:	f000 fb19 	bl	1b48 <__gnu_thumb1_case_uqi>
-    1516:	0514      	.short	0x0514
-    1518:	1a0e0c05 	.word	0x1a0e0c05
-    151c:	2007      	.short	0x2007
-    151e:	34          	.byte	0x34
-    151f:	00          	.byte	0x00
-    1520:	2017      	movs	r0, #23
-    1522:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    1524:	2302      	movs	r3, #2
-    1526:	4a19      	ldr	r2, [pc, #100]	; (158c <system_clock_source_enable+0x80>)
-    1528:	6a11      	ldr	r1, [r2, #32]
-    152a:	430b      	orrs	r3, r1
-    152c:	6213      	str	r3, [r2, #32]
-    152e:	2000      	movs	r0, #0
-    1530:	e7f7      	b.n	1522 <system_clock_source_enable+0x16>
-    1532:	2302      	movs	r3, #2
-    1534:	4a15      	ldr	r2, [pc, #84]	; (158c <system_clock_source_enable+0x80>)
-    1536:	6991      	ldr	r1, [r2, #24]
-    1538:	430b      	orrs	r3, r1
-    153a:	6193      	str	r3, [r2, #24]
-    153c:	e7f7      	b.n	152e <system_clock_source_enable+0x22>
-    153e:	2302      	movs	r3, #2
-    1540:	4a12      	ldr	r2, [pc, #72]	; (158c <system_clock_source_enable+0x80>)
-    1542:	8a11      	ldrh	r1, [r2, #16]
-    1544:	430b      	orrs	r3, r1
-    1546:	8213      	strh	r3, [r2, #16]
-    1548:	e7f1      	b.n	152e <system_clock_source_enable+0x22>
-    154a:	2302      	movs	r3, #2
-    154c:	4a0f      	ldr	r2, [pc, #60]	; (158c <system_clock_source_enable+0x80>)
-    154e:	8a91      	ldrh	r1, [r2, #20]
-    1550:	430b      	orrs	r3, r1
-    1552:	8293      	strh	r3, [r2, #20]
-    1554:	e7eb      	b.n	152e <system_clock_source_enable+0x22>
-    1556:	2202      	movs	r2, #2
-    1558:	2400      	movs	r4, #0
-    155a:	4e0d      	ldr	r6, [pc, #52]	; (1590 <system_clock_source_enable+0x84>)
-    155c:	4d0b      	ldr	r5, [pc, #44]	; (158c <system_clock_source_enable+0x80>)
-    155e:	6833      	ldr	r3, [r6, #0]
-    1560:	4f0c      	ldr	r7, [pc, #48]	; (1594 <system_clock_source_enable+0x88>)
-    1562:	4313      	orrs	r3, r2
-    1564:	6033      	str	r3, [r6, #0]
-    1566:	84aa      	strh	r2, [r5, #36]	; 0x24
-    1568:	47b8      	blx	r7
-    156a:	68b3      	ldr	r3, [r6, #8]
-    156c:	62eb      	str	r3, [r5, #44]	; 0x2c
-    156e:	6873      	ldr	r3, [r6, #4]
-    1570:	62ab      	str	r3, [r5, #40]	; 0x28
-    1572:	84ac      	strh	r4, [r5, #36]	; 0x24
-    1574:	47b8      	blx	r7
-    1576:	6833      	ldr	r3, [r6, #0]
-    1578:	b29b      	uxth	r3, r3
-    157a:	84ab      	strh	r3, [r5, #36]	; 0x24
-    157c:	e7d7      	b.n	152e <system_clock_source_enable+0x22>
-    157e:	2302      	movs	r3, #2
-    1580:	4a05      	ldr	r2, [pc, #20]	; (1598 <system_clock_source_enable+0x8c>)
-    1582:	7811      	ldrb	r1, [r2, #0]
-    1584:	430b      	orrs	r3, r1
-    1586:	7013      	strb	r3, [r2, #0]
-    1588:	e7d1      	b.n	152e <system_clock_source_enable+0x22>
-    158a:	46c0      	nop			; (mov r8, r8)
-    158c:	40000800 	.word	0x40000800
-    1590:	200001b0 	.word	0x200001b0
-    1594:	00001431 	.word	0x00001431
-    1598:	40000844 	.word	0x40000844
-
-0000159c <system_clock_init>:
-    159c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
-    159e:	22c2      	movs	r2, #194	; 0xc2
-    15a0:	211e      	movs	r1, #30
-    15a2:	4b19      	ldr	r3, [pc, #100]	; (1608 <system_clock_init+0x6c>)
-    15a4:	00d2      	lsls	r2, r2, #3
-    15a6:	609a      	str	r2, [r3, #8]
-    15a8:	4a18      	ldr	r2, [pc, #96]	; (160c <system_clock_init+0x70>)
-    15aa:	2400      	movs	r4, #0
-    15ac:	6853      	ldr	r3, [r2, #4]
-    15ae:	ad01      	add	r5, sp, #4
-    15b0:	438b      	bics	r3, r1
-    15b2:	6053      	str	r3, [r2, #4]
-    15b4:	2301      	movs	r3, #1
-    15b6:	702b      	strb	r3, [r5, #0]
-    15b8:	b2e0      	uxtb	r0, r4
-    15ba:	0029      	movs	r1, r5
-    15bc:	4b14      	ldr	r3, [pc, #80]	; (1610 <system_clock_init+0x74>)
-    15be:	3401      	adds	r4, #1
-    15c0:	4798      	blx	r3
-    15c2:	2c25      	cmp	r4, #37	; 0x25
-    15c4:	d1f8      	bne.n	15b8 <system_clock_init+0x1c>
-    15c6:	2400      	movs	r4, #0
-    15c8:	466b      	mov	r3, sp
-    15ca:	2601      	movs	r6, #1
-    15cc:	705c      	strb	r4, [r3, #1]
-    15ce:	709e      	strb	r6, [r3, #2]
-    15d0:	701c      	strb	r4, [r3, #0]
-    15d2:	4668      	mov	r0, sp
-    15d4:	4b0f      	ldr	r3, [pc, #60]	; (1614 <system_clock_init+0x78>)
-    15d6:	4798      	blx	r3
-    15d8:	4b0f      	ldr	r3, [pc, #60]	; (1618 <system_clock_init+0x7c>)
-    15da:	2006      	movs	r0, #6
-    15dc:	4798      	blx	r3
-    15de:	4b0f      	ldr	r3, [pc, #60]	; (161c <system_clock_init+0x80>)
-    15e0:	4798      	blx	r3
-    15e2:	4b0f      	ldr	r3, [pc, #60]	; (1620 <system_clock_init+0x84>)
-    15e4:	0029      	movs	r1, r5
-    15e6:	721c      	strb	r4, [r3, #8]
-    15e8:	725c      	strb	r4, [r3, #9]
-    15ea:	729c      	strb	r4, [r3, #10]
-    15ec:	72dc      	strb	r4, [r3, #11]
-    15ee:	2306      	movs	r3, #6
-    15f0:	0020      	movs	r0, r4
-    15f2:	702b      	strb	r3, [r5, #0]
-    15f4:	4b0b      	ldr	r3, [pc, #44]	; (1624 <system_clock_init+0x88>)
-    15f6:	606e      	str	r6, [r5, #4]
-    15f8:	706c      	strb	r4, [r5, #1]
-    15fa:	722c      	strb	r4, [r5, #8]
-    15fc:	726c      	strb	r4, [r5, #9]
-    15fe:	4798      	blx	r3
-    1600:	0020      	movs	r0, r4
-    1602:	4b09      	ldr	r3, [pc, #36]	; (1628 <system_clock_init+0x8c>)
-    1604:	4798      	blx	r3
-    1606:	bd7f      	pop	{r0, r1, r2, r3, r4, r5, r6, pc}
-    1608:	40000800 	.word	0x40000800
-    160c:	41004000 	.word	0x41004000
-    1610:	0000184d 	.word	0x0000184d
-    1614:	000014d1 	.word	0x000014d1
-    1618:	0000150d 	.word	0x0000150d
-    161c:	00001639 	.word	0x00001639
-    1620:	40000400 	.word	0x40000400
-    1624:	00001659 	.word	0x00001659
-    1628:	000016fd 	.word	0x000016fd
-
-0000162c <system_gclk_is_syncing>:
-    162c:	4b01      	ldr	r3, [pc, #4]	; (1634 <system_gclk_is_syncing+0x8>)
-    162e:	7858      	ldrb	r0, [r3, #1]
-    1630:	09c0      	lsrs	r0, r0, #7
-    1632:	4770      	bx	lr
-    1634:	40000c00 	.word	0x40000c00
-
-00001638 <system_gclk_init>:
-    1638:	2308      	movs	r3, #8
-    163a:	4a05      	ldr	r2, [pc, #20]	; (1650 <system_gclk_init+0x18>)
-    163c:	6991      	ldr	r1, [r2, #24]
-    163e:	430b      	orrs	r3, r1
-    1640:	6193      	str	r3, [r2, #24]
-    1642:	2301      	movs	r3, #1
-    1644:	4a03      	ldr	r2, [pc, #12]	; (1654 <system_gclk_init+0x1c>)
-    1646:	7013      	strb	r3, [r2, #0]
-    1648:	7811      	ldrb	r1, [r2, #0]
-    164a:	4219      	tst	r1, r3
-    164c:	d1fc      	bne.n	1648 <system_gclk_init+0x10>
-    164e:	4770      	bx	lr
-    1650:	40000400 	.word	0x40000400
-    1654:	40000c00 	.word	0x40000c00
-
-00001658 <system_gclk_gen_set_config>:
-    1658:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    165a:	780c      	ldrb	r4, [r1, #0]
-    165c:	784b      	ldrb	r3, [r1, #1]
-    165e:	0224      	lsls	r4, r4, #8
-    1660:	0006      	movs	r6, r0
-    1662:	0005      	movs	r5, r0
-    1664:	4304      	orrs	r4, r0
-    1666:	2b00      	cmp	r3, #0
-    1668:	d002      	beq.n	1670 <system_gclk_gen_set_config+0x18>
-    166a:	2380      	movs	r3, #128	; 0x80
-    166c:	02db      	lsls	r3, r3, #11
-    166e:	431c      	orrs	r4, r3
-    1670:	7a4b      	ldrb	r3, [r1, #9]
-    1672:	2b00      	cmp	r3, #0
-    1674:	d002      	beq.n	167c <system_gclk_gen_set_config+0x24>
-    1676:	2380      	movs	r3, #128	; 0x80
-    1678:	031b      	lsls	r3, r3, #12
-    167a:	431c      	orrs	r4, r3
-    167c:	684b      	ldr	r3, [r1, #4]
-    167e:	2b01      	cmp	r3, #1
-    1680:	d912      	bls.n	16a8 <system_gclk_gen_set_config+0x50>
-    1682:	1e5d      	subs	r5, r3, #1
-    1684:	401d      	ands	r5, r3
-    1686:	2202      	movs	r2, #2
-    1688:	2d00      	cmp	r5, #0
-    168a:	d006      	beq.n	169a <system_gclk_gen_set_config+0x42>
-    168c:	021d      	lsls	r5, r3, #8
-    168e:	2380      	movs	r3, #128	; 0x80
-    1690:	4335      	orrs	r5, r6
-    1692:	029b      	lsls	r3, r3, #10
-    1694:	e007      	b.n	16a6 <system_gclk_gen_set_config+0x4e>
-    1696:	3501      	adds	r5, #1
-    1698:	0052      	lsls	r2, r2, #1
-    169a:	429a      	cmp	r2, r3
-    169c:	d3fb      	bcc.n	1696 <system_gclk_gen_set_config+0x3e>
-    169e:	2380      	movs	r3, #128	; 0x80
-    16a0:	022d      	lsls	r5, r5, #8
-    16a2:	4335      	orrs	r5, r6
-    16a4:	035b      	lsls	r3, r3, #13
-    16a6:	431c      	orrs	r4, r3
-    16a8:	7a0b      	ldrb	r3, [r1, #8]
-    16aa:	2b00      	cmp	r3, #0
-    16ac:	d002      	beq.n	16b4 <system_gclk_gen_set_config+0x5c>
-    16ae:	2380      	movs	r3, #128	; 0x80
-    16b0:	039b      	lsls	r3, r3, #14
-    16b2:	431c      	orrs	r4, r3
-    16b4:	4f0c      	ldr	r7, [pc, #48]	; (16e8 <system_gclk_gen_set_config+0x90>)
-    16b6:	47b8      	blx	r7
-    16b8:	2800      	cmp	r0, #0
-    16ba:	d1fb      	bne.n	16b4 <system_gclk_gen_set_config+0x5c>
-    16bc:	4b0b      	ldr	r3, [pc, #44]	; (16ec <system_gclk_gen_set_config+0x94>)
-    16be:	4798      	blx	r3
-    16c0:	4b0b      	ldr	r3, [pc, #44]	; (16f0 <system_gclk_gen_set_config+0x98>)
-    16c2:	701e      	strb	r6, [r3, #0]
-    16c4:	47b8      	blx	r7
-    16c6:	2800      	cmp	r0, #0
-    16c8:	d1fc      	bne.n	16c4 <system_gclk_gen_set_config+0x6c>
-    16ca:	4b0a      	ldr	r3, [pc, #40]	; (16f4 <system_gclk_gen_set_config+0x9c>)
-    16cc:	609d      	str	r5, [r3, #8]
-    16ce:	001d      	movs	r5, r3
-    16d0:	47b8      	blx	r7
-    16d2:	2800      	cmp	r0, #0
-    16d4:	d1fc      	bne.n	16d0 <system_gclk_gen_set_config+0x78>
-    16d6:	2280      	movs	r2, #128	; 0x80
-    16d8:	686b      	ldr	r3, [r5, #4]
-    16da:	0252      	lsls	r2, r2, #9
-    16dc:	4013      	ands	r3, r2
-    16de:	431c      	orrs	r4, r3
-    16e0:	606c      	str	r4, [r5, #4]
-    16e2:	4b05      	ldr	r3, [pc, #20]	; (16f8 <system_gclk_gen_set_config+0xa0>)
-    16e4:	4798      	blx	r3
-    16e6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    16e8:	0000162d 	.word	0x0000162d
-    16ec:	00001379 	.word	0x00001379
-    16f0:	40000c08 	.word	0x40000c08
-    16f4:	40000c00 	.word	0x40000c00
-    16f8:	000013ad 	.word	0x000013ad
-
-000016fc <system_gclk_gen_enable>:
-    16fc:	b570      	push	{r4, r5, r6, lr}
-    16fe:	0005      	movs	r5, r0
-    1700:	4c09      	ldr	r4, [pc, #36]	; (1728 <system_gclk_gen_enable+0x2c>)
-    1702:	47a0      	blx	r4
-    1704:	2800      	cmp	r0, #0
-    1706:	d1fb      	bne.n	1700 <system_gclk_gen_enable+0x4>
-    1708:	4b08      	ldr	r3, [pc, #32]	; (172c <system_gclk_gen_enable+0x30>)
-    170a:	4798      	blx	r3
-    170c:	4b08      	ldr	r3, [pc, #32]	; (1730 <system_gclk_gen_enable+0x34>)
-    170e:	701d      	strb	r5, [r3, #0]
-    1710:	47a0      	blx	r4
-    1712:	2800      	cmp	r0, #0
-    1714:	d1fc      	bne.n	1710 <system_gclk_gen_enable+0x14>
-    1716:	2380      	movs	r3, #128	; 0x80
-    1718:	4a06      	ldr	r2, [pc, #24]	; (1734 <system_gclk_gen_enable+0x38>)
-    171a:	025b      	lsls	r3, r3, #9
-    171c:	6851      	ldr	r1, [r2, #4]
-    171e:	430b      	orrs	r3, r1
-    1720:	6053      	str	r3, [r2, #4]
-    1722:	4b05      	ldr	r3, [pc, #20]	; (1738 <system_gclk_gen_enable+0x3c>)
-    1724:	4798      	blx	r3
-    1726:	bd70      	pop	{r4, r5, r6, pc}
-    1728:	0000162d 	.word	0x0000162d
-    172c:	00001379 	.word	0x00001379
-    1730:	40000c04 	.word	0x40000c04
-    1734:	40000c00 	.word	0x40000c00
-    1738:	000013ad 	.word	0x000013ad
-
-0000173c <system_gclk_gen_get_hz>:
-    173c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    173e:	0007      	movs	r7, r0
-    1740:	4e18      	ldr	r6, [pc, #96]	; (17a4 <system_gclk_gen_get_hz+0x68>)
-    1742:	47b0      	blx	r6
-    1744:	2800      	cmp	r0, #0
-    1746:	d1fb      	bne.n	1740 <system_gclk_gen_get_hz+0x4>
-    1748:	4b17      	ldr	r3, [pc, #92]	; (17a8 <system_gclk_gen_get_hz+0x6c>)
-    174a:	4798      	blx	r3
-    174c:	4b17      	ldr	r3, [pc, #92]	; (17ac <system_gclk_gen_get_hz+0x70>)
-    174e:	701f      	strb	r7, [r3, #0]
-    1750:	9301      	str	r3, [sp, #4]
-    1752:	47b0      	blx	r6
-    1754:	2800      	cmp	r0, #0
-    1756:	d1fc      	bne.n	1752 <system_gclk_gen_get_hz+0x16>
-    1758:	4d15      	ldr	r5, [pc, #84]	; (17b0 <system_gclk_gen_get_hz+0x74>)
-    175a:	4b16      	ldr	r3, [pc, #88]	; (17b4 <system_gclk_gen_get_hz+0x78>)
-    175c:	6868      	ldr	r0, [r5, #4]
-    175e:	04c0      	lsls	r0, r0, #19
-    1760:	0ec0      	lsrs	r0, r0, #27
-    1762:	4798      	blx	r3
-    1764:	0004      	movs	r4, r0
-    1766:	9b01      	ldr	r3, [sp, #4]
-    1768:	701f      	strb	r7, [r3, #0]
-    176a:	686b      	ldr	r3, [r5, #4]
-    176c:	02db      	lsls	r3, r3, #11
-    176e:	0fdb      	lsrs	r3, r3, #31
-    1770:	9301      	str	r3, [sp, #4]
-    1772:	4b11      	ldr	r3, [pc, #68]	; (17b8 <system_gclk_gen_get_hz+0x7c>)
-    1774:	701f      	strb	r7, [r3, #0]
-    1776:	47b0      	blx	r6
-    1778:	2800      	cmp	r0, #0
-    177a:	d1fc      	bne.n	1776 <system_gclk_gen_get_hz+0x3a>
-    177c:	68ad      	ldr	r5, [r5, #8]
-    177e:	4b0f      	ldr	r3, [pc, #60]	; (17bc <system_gclk_gen_get_hz+0x80>)
-    1780:	4798      	blx	r3
-    1782:	9b01      	ldr	r3, [sp, #4]
-    1784:	022d      	lsls	r5, r5, #8
-    1786:	0c2d      	lsrs	r5, r5, #16
-    1788:	2b00      	cmp	r3, #0
-    178a:	d108      	bne.n	179e <system_gclk_gen_get_hz+0x62>
-    178c:	2d01      	cmp	r5, #1
-    178e:	d904      	bls.n	179a <system_gclk_gen_get_hz+0x5e>
-    1790:	0020      	movs	r0, r4
-    1792:	0029      	movs	r1, r5
-    1794:	4b0a      	ldr	r3, [pc, #40]	; (17c0 <system_gclk_gen_get_hz+0x84>)
-    1796:	4798      	blx	r3
-    1798:	0004      	movs	r4, r0
-    179a:	0020      	movs	r0, r4
-    179c:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    179e:	3501      	adds	r5, #1
-    17a0:	40ec      	lsrs	r4, r5
-    17a2:	e7fa      	b.n	179a <system_gclk_gen_get_hz+0x5e>
-    17a4:	0000162d 	.word	0x0000162d
-    17a8:	00001379 	.word	0x00001379
-    17ac:	40000c04 	.word	0x40000c04
-    17b0:	40000c00 	.word	0x40000c00
-    17b4:	00001441 	.word	0x00001441
-    17b8:	40000c08 	.word	0x40000c08
-    17bc:	000013ad 	.word	0x000013ad
-    17c0:	00001b5d 	.word	0x00001b5d
-
-000017c4 <system_gclk_chan_enable>:
-    17c4:	b510      	push	{r4, lr}
-    17c6:	0004      	movs	r4, r0
-    17c8:	4b06      	ldr	r3, [pc, #24]	; (17e4 <system_gclk_chan_enable+0x20>)
-    17ca:	4798      	blx	r3
-    17cc:	4b06      	ldr	r3, [pc, #24]	; (17e8 <system_gclk_chan_enable+0x24>)
-    17ce:	4a07      	ldr	r2, [pc, #28]	; (17ec <system_gclk_chan_enable+0x28>)
-    17d0:	701c      	strb	r4, [r3, #0]
-    17d2:	2380      	movs	r3, #128	; 0x80
-    17d4:	8851      	ldrh	r1, [r2, #2]
-    17d6:	01db      	lsls	r3, r3, #7
-    17d8:	430b      	orrs	r3, r1
-    17da:	8053      	strh	r3, [r2, #2]
-    17dc:	4b04      	ldr	r3, [pc, #16]	; (17f0 <system_gclk_chan_enable+0x2c>)
-    17de:	4798      	blx	r3
-    17e0:	bd10      	pop	{r4, pc}
-    17e2:	46c0      	nop			; (mov r8, r8)
-    17e4:	00001379 	.word	0x00001379
-    17e8:	40000c02 	.word	0x40000c02
-    17ec:	40000c00 	.word	0x40000c00
-    17f0:	000013ad 	.word	0x000013ad
-
-000017f4 <system_gclk_chan_disable>:
-    17f4:	b510      	push	{r4, lr}
-    17f6:	0004      	movs	r4, r0
-    17f8:	4b0e      	ldr	r3, [pc, #56]	; (1834 <system_gclk_chan_disable+0x40>)
-    17fa:	4798      	blx	r3
-    17fc:	4b0e      	ldr	r3, [pc, #56]	; (1838 <system_gclk_chan_disable+0x44>)
-    17fe:	4a0f      	ldr	r2, [pc, #60]	; (183c <system_gclk_chan_disable+0x48>)
-    1800:	701c      	strb	r4, [r3, #0]
-    1802:	4b0f      	ldr	r3, [pc, #60]	; (1840 <system_gclk_chan_disable+0x4c>)
-    1804:	4c0f      	ldr	r4, [pc, #60]	; (1844 <system_gclk_chan_disable+0x50>)
-    1806:	8858      	ldrh	r0, [r3, #2]
-    1808:	8859      	ldrh	r1, [r3, #2]
-    180a:	0500      	lsls	r0, r0, #20
-    180c:	4011      	ands	r1, r2
-    180e:	8059      	strh	r1, [r3, #2]
-    1810:	8859      	ldrh	r1, [r3, #2]
-    1812:	0f00      	lsrs	r0, r0, #28
-    1814:	4021      	ands	r1, r4
-    1816:	8059      	strh	r1, [r3, #2]
-    1818:	0011      	movs	r1, r2
-    181a:	2280      	movs	r2, #128	; 0x80
-    181c:	01d2      	lsls	r2, r2, #7
-    181e:	885c      	ldrh	r4, [r3, #2]
-    1820:	4214      	tst	r4, r2
-    1822:	d1fc      	bne.n	181e <system_gclk_chan_disable+0x2a>
-    1824:	885a      	ldrh	r2, [r3, #2]
-    1826:	0200      	lsls	r0, r0, #8
-    1828:	400a      	ands	r2, r1
-    182a:	4302      	orrs	r2, r0
-    182c:	805a      	strh	r2, [r3, #2]
-    182e:	4b06      	ldr	r3, [pc, #24]	; (1848 <system_gclk_chan_disable+0x54>)
-    1830:	4798      	blx	r3
-    1832:	bd10      	pop	{r4, pc}
-    1834:	00001379 	.word	0x00001379
-    1838:	40000c02 	.word	0x40000c02
-    183c:	fffff0ff 	.word	0xfffff0ff
-    1840:	40000c00 	.word	0x40000c00
-    1844:	ffffbfff 	.word	0xffffbfff
-    1848:	000013ad 	.word	0x000013ad
-
-0000184c <system_gclk_chan_set_config>:
-    184c:	b510      	push	{r4, lr}
-    184e:	780c      	ldrb	r4, [r1, #0]
-    1850:	4b03      	ldr	r3, [pc, #12]	; (1860 <system_gclk_chan_set_config+0x14>)
-    1852:	0224      	lsls	r4, r4, #8
-    1854:	4304      	orrs	r4, r0
-    1856:	4798      	blx	r3
-    1858:	4b02      	ldr	r3, [pc, #8]	; (1864 <system_gclk_chan_set_config+0x18>)
-    185a:	b2a4      	uxth	r4, r4
-    185c:	805c      	strh	r4, [r3, #2]
-    185e:	bd10      	pop	{r4, pc}
-    1860:	000017f5 	.word	0x000017f5
-    1864:	40000c00 	.word	0x40000c00
-
-00001868 <system_gclk_chan_get_hz>:
-    1868:	b510      	push	{r4, lr}
-    186a:	0004      	movs	r4, r0
-    186c:	4b06      	ldr	r3, [pc, #24]	; (1888 <system_gclk_chan_get_hz+0x20>)
-    186e:	4798      	blx	r3
-    1870:	4b06      	ldr	r3, [pc, #24]	; (188c <system_gclk_chan_get_hz+0x24>)
-    1872:	701c      	strb	r4, [r3, #0]
-    1874:	4b06      	ldr	r3, [pc, #24]	; (1890 <system_gclk_chan_get_hz+0x28>)
-    1876:	885c      	ldrh	r4, [r3, #2]
-    1878:	4b06      	ldr	r3, [pc, #24]	; (1894 <system_gclk_chan_get_hz+0x2c>)
-    187a:	0524      	lsls	r4, r4, #20
-    187c:	0f24      	lsrs	r4, r4, #28
-    187e:	4798      	blx	r3
-    1880:	0020      	movs	r0, r4
-    1882:	4b05      	ldr	r3, [pc, #20]	; (1898 <system_gclk_chan_get_hz+0x30>)
-    1884:	4798      	blx	r3
-    1886:	bd10      	pop	{r4, pc}
-    1888:	00001379 	.word	0x00001379
-    188c:	40000c02 	.word	0x40000c02
-    1890:	40000c00 	.word	0x40000c00
-    1894:	000013ad 	.word	0x000013ad
-    1898:	0000173d 	.word	0x0000173d
-
-0000189c <_system_pinmux_config>:
-    189c:	78d3      	ldrb	r3, [r2, #3]
-    189e:	b530      	push	{r4, r5, lr}
-    18a0:	2b00      	cmp	r3, #0
-    18a2:	d135      	bne.n	1910 <_system_pinmux_config+0x74>
-    18a4:	7814      	ldrb	r4, [r2, #0]
-    18a6:	2c80      	cmp	r4, #128	; 0x80
-    18a8:	d003      	beq.n	18b2 <_system_pinmux_config+0x16>
-    18aa:	2380      	movs	r3, #128	; 0x80
-    18ac:	0624      	lsls	r4, r4, #24
-    18ae:	025b      	lsls	r3, r3, #9
-    18b0:	4323      	orrs	r3, r4
-    18b2:	2502      	movs	r5, #2
-    18b4:	7854      	ldrb	r4, [r2, #1]
-    18b6:	43ac      	bics	r4, r5
-    18b8:	d106      	bne.n	18c8 <_system_pinmux_config+0x2c>
-    18ba:	7894      	ldrb	r4, [r2, #2]
-    18bc:	2c00      	cmp	r4, #0
-    18be:	d124      	bne.n	190a <_system_pinmux_config+0x6e>
-    18c0:	2480      	movs	r4, #128	; 0x80
-    18c2:	02a4      	lsls	r4, r4, #10
-    18c4:	4323      	orrs	r3, r4
-    18c6:	6041      	str	r1, [r0, #4]
-    18c8:	7854      	ldrb	r4, [r2, #1]
-    18ca:	3c01      	subs	r4, #1
-    18cc:	2c01      	cmp	r4, #1
-    18ce:	d801      	bhi.n	18d4 <_system_pinmux_config+0x38>
-    18d0:	4c12      	ldr	r4, [pc, #72]	; (191c <_system_pinmux_config+0x80>)
-    18d2:	4023      	ands	r3, r4
-    18d4:	24a0      	movs	r4, #160	; 0xa0
-    18d6:	b28d      	uxth	r5, r1
-    18d8:	05e4      	lsls	r4, r4, #23
-    18da:	432c      	orrs	r4, r5
-    18dc:	431c      	orrs	r4, r3
-    18de:	6284      	str	r4, [r0, #40]	; 0x28
-    18e0:	24d0      	movs	r4, #208	; 0xd0
-    18e2:	0c0d      	lsrs	r5, r1, #16
-    18e4:	0624      	lsls	r4, r4, #24
-    18e6:	432c      	orrs	r4, r5
-    18e8:	431c      	orrs	r4, r3
-    18ea:	6284      	str	r4, [r0, #40]	; 0x28
-    18ec:	78d4      	ldrb	r4, [r2, #3]
-    18ee:	2c00      	cmp	r4, #0
-    18f0:	d10a      	bne.n	1908 <_system_pinmux_config+0x6c>
-    18f2:	035b      	lsls	r3, r3, #13
-    18f4:	d503      	bpl.n	18fe <_system_pinmux_config+0x62>
-    18f6:	7893      	ldrb	r3, [r2, #2]
-    18f8:	2b01      	cmp	r3, #1
-    18fa:	d10c      	bne.n	1916 <_system_pinmux_config+0x7a>
-    18fc:	6181      	str	r1, [r0, #24]
-    18fe:	7853      	ldrb	r3, [r2, #1]
-    1900:	3b01      	subs	r3, #1
-    1902:	2b01      	cmp	r3, #1
-    1904:	d800      	bhi.n	1908 <_system_pinmux_config+0x6c>
-    1906:	6081      	str	r1, [r0, #8]
-    1908:	bd30      	pop	{r4, r5, pc}
-    190a:	24c0      	movs	r4, #192	; 0xc0
-    190c:	02e4      	lsls	r4, r4, #11
-    190e:	e7d9      	b.n	18c4 <_system_pinmux_config+0x28>
-    1910:	6041      	str	r1, [r0, #4]
-    1912:	2300      	movs	r3, #0
-    1914:	e7de      	b.n	18d4 <_system_pinmux_config+0x38>
-    1916:	6141      	str	r1, [r0, #20]
-    1918:	e7f1      	b.n	18fe <_system_pinmux_config+0x62>
-    191a:	46c0      	nop			; (mov r8, r8)
-    191c:	fffbffff 	.word	0xfffbffff
-
-00001920 <system_pinmux_pin_set_config>:
-    1920:	b510      	push	{r4, lr}
-    1922:	0003      	movs	r3, r0
-    1924:	000a      	movs	r2, r1
-    1926:	0944      	lsrs	r4, r0, #5
-    1928:	09c1      	lsrs	r1, r0, #7
-    192a:	2000      	movs	r0, #0
-    192c:	4281      	cmp	r1, r0
-    192e:	d102      	bne.n	1936 <system_pinmux_pin_set_config+0x16>
-    1930:	4904      	ldr	r1, [pc, #16]	; (1944 <system_pinmux_pin_set_config+0x24>)
-    1932:	01e0      	lsls	r0, r4, #7
-    1934:	1840      	adds	r0, r0, r1
-    1936:	211f      	movs	r1, #31
-    1938:	400b      	ands	r3, r1
-    193a:	391e      	subs	r1, #30
-    193c:	4099      	lsls	r1, r3
-    193e:	4b02      	ldr	r3, [pc, #8]	; (1948 <system_pinmux_pin_set_config+0x28>)
-    1940:	4798      	blx	r3
-    1942:	bd10      	pop	{r4, pc}
-    1944:	41004400 	.word	0x41004400
-    1948:	0000189d 	.word	0x0000189d
-
-0000194c <_system_dummy_init>:
-    194c:	4770      	bx	lr
-	...
-
-00001950 <system_init>:
-    1950:	b510      	push	{r4, lr}
-    1952:	4b05      	ldr	r3, [pc, #20]	; (1968 <system_init+0x18>)
-    1954:	4798      	blx	r3
-    1956:	4b05      	ldr	r3, [pc, #20]	; (196c <system_init+0x1c>)
-    1958:	4798      	blx	r3
-    195a:	4b05      	ldr	r3, [pc, #20]	; (1970 <system_init+0x20>)
-    195c:	4798      	blx	r3
-    195e:	4b05      	ldr	r3, [pc, #20]	; (1974 <system_init+0x24>)
-    1960:	4798      	blx	r3
-    1962:	4b05      	ldr	r3, [pc, #20]	; (1978 <system_init+0x28>)
-    1964:	4798      	blx	r3
-    1966:	bd10      	pop	{r4, pc}
-    1968:	0000159d 	.word	0x0000159d
-    196c:	000013dd 	.word	0x000013dd
-    1970:	0000194d 	.word	0x0000194d
-    1974:	0000194d 	.word	0x0000194d
-    1978:	0000194d 	.word	0x0000194d
-
-0000197c <Dummy_Handler>:
-    197c:	e7fe      	b.n	197c <Dummy_Handler>
-	...
-
-00001980 <Reset_Handler>:
-    1980:	4821      	ldr	r0, [pc, #132]	; (1a08 <Reset_Handler+0x88>)
-    1982:	4922      	ldr	r1, [pc, #136]	; (1a0c <Reset_Handler+0x8c>)
-    1984:	b570      	push	{r4, r5, r6, lr}
-    1986:	4288      	cmp	r0, r1
-    1988:	d004      	beq.n	1994 <Reset_Handler+0x14>
-    198a:	2300      	movs	r3, #0
-    198c:	4c20      	ldr	r4, [pc, #128]	; (1a10 <Reset_Handler+0x90>)
-    198e:	18ca      	adds	r2, r1, r3
-    1990:	42a2      	cmp	r2, r4
-    1992:	d332      	bcc.n	19fa <Reset_Handler+0x7a>
-    1994:	2100      	movs	r1, #0
-    1996:	4b1f      	ldr	r3, [pc, #124]	; (1a14 <Reset_Handler+0x94>)
-    1998:	4a1f      	ldr	r2, [pc, #124]	; (1a18 <Reset_Handler+0x98>)
-    199a:	4293      	cmp	r3, r2
-    199c:	d331      	bcc.n	1a02 <Reset_Handler+0x82>
-    199e:	21ff      	movs	r1, #255	; 0xff
-    19a0:	4b1e      	ldr	r3, [pc, #120]	; (1a1c <Reset_Handler+0x9c>)
-    19a2:	4a1f      	ldr	r2, [pc, #124]	; (1a20 <Reset_Handler+0xa0>)
-    19a4:	438b      	bics	r3, r1
-    19a6:	6093      	str	r3, [r2, #8]
-    19a8:	2202      	movs	r2, #2
-    19aa:	250c      	movs	r5, #12
-    19ac:	2408      	movs	r4, #8
-    19ae:	2630      	movs	r6, #48	; 0x30
-    19b0:	4b1c      	ldr	r3, [pc, #112]	; (1a24 <Reset_Handler+0xa4>)
-    19b2:	481d      	ldr	r0, [pc, #116]	; (1a28 <Reset_Handler+0xa8>)
-    19b4:	625a      	str	r2, [r3, #36]	; 0x24
-    19b6:	78c3      	ldrb	r3, [r0, #3]
-    19b8:	39fc      	subs	r1, #252	; 0xfc
-    19ba:	438b      	bics	r3, r1
-    19bc:	4313      	orrs	r3, r2
-    19be:	70c3      	strb	r3, [r0, #3]
-    19c0:	78c3      	ldrb	r3, [r0, #3]
-    19c2:	43ab      	bics	r3, r5
-    19c4:	4323      	orrs	r3, r4
-    19c6:	70c3      	strb	r3, [r0, #3]
-    19c8:	4b18      	ldr	r3, [pc, #96]	; (1a2c <Reset_Handler+0xac>)
-    19ca:	7b98      	ldrb	r0, [r3, #14]
-    19cc:	43b0      	bics	r0, r6
-    19ce:	0006      	movs	r6, r0
-    19d0:	2020      	movs	r0, #32
-    19d2:	4330      	orrs	r0, r6
-    19d4:	7398      	strb	r0, [r3, #14]
-    19d6:	7b98      	ldrb	r0, [r3, #14]
-    19d8:	43a8      	bics	r0, r5
-    19da:	4304      	orrs	r4, r0
-    19dc:	739c      	strb	r4, [r3, #14]
-    19de:	7b98      	ldrb	r0, [r3, #14]
-    19e0:	4388      	bics	r0, r1
-    19e2:	4302      	orrs	r2, r0
-    19e4:	739a      	strb	r2, [r3, #14]
-    19e6:	2380      	movs	r3, #128	; 0x80
-    19e8:	4a11      	ldr	r2, [pc, #68]	; (1a30 <Reset_Handler+0xb0>)
-    19ea:	6851      	ldr	r1, [r2, #4]
-    19ec:	430b      	orrs	r3, r1
-    19ee:	6053      	str	r3, [r2, #4]
-    19f0:	4b10      	ldr	r3, [pc, #64]	; (1a34 <Reset_Handler+0xb4>)
-    19f2:	4798      	blx	r3
-    19f4:	4b10      	ldr	r3, [pc, #64]	; (1a38 <Reset_Handler+0xb8>)
-    19f6:	4798      	blx	r3
-    19f8:	e7fe      	b.n	19f8 <Reset_Handler+0x78>
-    19fa:	58c5      	ldr	r5, [r0, r3]
-    19fc:	3304      	adds	r3, #4
-    19fe:	6015      	str	r5, [r2, #0]
-    1a00:	e7c5      	b.n	198e <Reset_Handler+0xe>
-    1a02:	c302      	stmia	r3!, {r1}
-    1a04:	e7c9      	b.n	199a <Reset_Handler+0x1a>
-    1a06:	46c0      	nop			; (mov r8, r8)
-    1a08:	000036e8 	.word	0x000036e8
-    1a0c:	20000000 	.word	0x20000000
-    1a10:	2000007c 	.word	0x2000007c
-    1a14:	20000080 	.word	0x20000080
-    1a18:	200002a0 	.word	0x200002a0
-    1a1c:	00000000 	.word	0x00000000
-    1a20:	e000ed00 	.word	0xe000ed00
-    1a24:	410070fc 	.word	0x410070fc
-    1a28:	41005000 	.word	0x41005000
-    1a2c:	41004800 	.word	0x41004800
-    1a30:	41004000 	.word	0x41004000
-    1a34:	00002401 	.word	0x00002401
-    1a38:	00001a75 	.word	0x00001a75
-
-00001a3c <_sbrk>:
-    1a3c:	4b05      	ldr	r3, [pc, #20]	; (1a54 <_sbrk+0x18>)
-    1a3e:	0002      	movs	r2, r0
-    1a40:	6819      	ldr	r1, [r3, #0]
-    1a42:	2900      	cmp	r1, #0
-    1a44:	d101      	bne.n	1a4a <_sbrk+0xe>
-    1a46:	4904      	ldr	r1, [pc, #16]	; (1a58 <_sbrk+0x1c>)
-    1a48:	6019      	str	r1, [r3, #0]
-    1a4a:	6818      	ldr	r0, [r3, #0]
-    1a4c:	1882      	adds	r2, r0, r2
-    1a4e:	601a      	str	r2, [r3, #0]
-    1a50:	4770      	bx	lr
-    1a52:	46c0      	nop			; (mov r8, r8)
-    1a54:	200001c8 	.word	0x200001c8
-    1a58:	200022a0 	.word	0x200022a0
-
-00001a5c <_close>:
-    1a5c:	2001      	movs	r0, #1
-    1a5e:	4240      	negs	r0, r0
-    1a60:	4770      	bx	lr
-
-00001a62 <_fstat>:
-    1a62:	2380      	movs	r3, #128	; 0x80
-    1a64:	019b      	lsls	r3, r3, #6
-    1a66:	2000      	movs	r0, #0
-    1a68:	604b      	str	r3, [r1, #4]
-    1a6a:	4770      	bx	lr
-
-00001a6c <_isatty>:
-    1a6c:	2001      	movs	r0, #1
-    1a6e:	4770      	bx	lr
-
-00001a70 <_lseek>:
-    1a70:	2000      	movs	r0, #0
-    1a72:	4770      	bx	lr
-
-00001a74 <main>:
-    1a74:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    1a76:	4b1f      	ldr	r3, [pc, #124]	; (1af4 <main+0x80>)
-    1a78:	4798      	blx	r3
-    1a7a:	4b1f      	ldr	r3, [pc, #124]	; (1af8 <main+0x84>)
-    1a7c:	4798      	blx	r3
-    1a7e:	2201      	movs	r2, #1
-    1a80:	4b1e      	ldr	r3, [pc, #120]	; (1afc <main+0x88>)
-    1a82:	701a      	strb	r2, [r3, #0]
-    1a84:	f3bf 8f5f 	dmb	sy
-    1a88:	b662      	cpsie	i
-    1a8a:	4b1d      	ldr	r3, [pc, #116]	; (1b00 <main+0x8c>)
-    1a8c:	4798      	blx	r3
-    1a8e:	4b1d      	ldr	r3, [pc, #116]	; (1b04 <main+0x90>)
-    1a90:	4798      	blx	r3
-    1a92:	4b1d      	ldr	r3, [pc, #116]	; (1b08 <main+0x94>)
-    1a94:	4798      	blx	r3
-    1a96:	211b      	movs	r1, #27
-    1a98:	4c1c      	ldr	r4, [pc, #112]	; (1b0c <main+0x98>)
-    1a9a:	481d      	ldr	r0, [pc, #116]	; (1b10 <main+0x9c>)
-    1a9c:	47a0      	blx	r4
-    1a9e:	211b      	movs	r1, #27
-    1aa0:	481c      	ldr	r0, [pc, #112]	; (1b14 <main+0xa0>)
-    1aa2:	47a0      	blx	r4
-    1aa4:	481c      	ldr	r0, [pc, #112]	; (1b18 <main+0xa4>)
-    1aa6:	4b1d      	ldr	r3, [pc, #116]	; (1b1c <main+0xa8>)
-    1aa8:	4798      	blx	r3
-    1aaa:	251b      	movs	r5, #27
-    1aac:	4b1c      	ldr	r3, [pc, #112]	; (1b20 <main+0xac>)
-    1aae:	4798      	blx	r3
-    1ab0:	4b1c      	ldr	r3, [pc, #112]	; (1b24 <main+0xb0>)
-    1ab2:	1c07      	adds	r7, r0, #0
-    1ab4:	4798      	blx	r3
-    1ab6:	4b1c      	ldr	r3, [pc, #112]	; (1b28 <main+0xb4>)
-    1ab8:	0006      	movs	r6, r0
-    1aba:	4798      	blx	r3
-    1abc:	4b1b      	ldr	r3, [pc, #108]	; (1b2c <main+0xb8>)
-    1abe:	1c01      	adds	r1, r0, #0
-    1ac0:	1c38      	adds	r0, r7, #0
-    1ac2:	4798      	blx	r3
-    1ac4:	491a      	ldr	r1, [pc, #104]	; (1b30 <main+0xbc>)
-    1ac6:	4b1b      	ldr	r3, [pc, #108]	; (1b34 <main+0xc0>)
-    1ac8:	4798      	blx	r3
-    1aca:	4b16      	ldr	r3, [pc, #88]	; (1b24 <main+0xb0>)
-    1acc:	4798      	blx	r3
-    1ace:	0031      	movs	r1, r6
-    1ad0:	0002      	movs	r2, r0
-    1ad2:	4819      	ldr	r0, [pc, #100]	; (1b38 <main+0xc4>)
-    1ad4:	47a0      	blx	r4
-    1ad6:	20fa      	movs	r0, #250	; 0xfa
-    1ad8:	4b18      	ldr	r3, [pc, #96]	; (1b3c <main+0xc8>)
-    1ada:	0040      	lsls	r0, r0, #1
-    1adc:	4798      	blx	r3
-    1ade:	0029      	movs	r1, r5
-    1ae0:	4817      	ldr	r0, [pc, #92]	; (1b40 <main+0xcc>)
-    1ae2:	47a0      	blx	r4
-    1ae4:	0029      	movs	r1, r5
-    1ae6:	480b      	ldr	r0, [pc, #44]	; (1b14 <main+0xa0>)
-    1ae8:	47a0      	blx	r4
-    1aea:	0029      	movs	r1, r5
-    1aec:	4815      	ldr	r0, [pc, #84]	; (1b44 <main+0xd0>)
-    1aee:	47a0      	blx	r4
-    1af0:	e7dc      	b.n	1aac <main+0x38>
-    1af2:	46c0      	nop			; (mov r8, r8)
-    1af4:	00001951 	.word	0x00001951
-    1af8:	0000130d 	.word	0x0000130d
-    1afc:	20000014 	.word	0x20000014
-    1b00:	00000ca1 	.word	0x00000ca1
-    1b04:	00000b19 	.word	0x00000b19
-    1b08:	00000bf1 	.word	0x00000bf1
-    1b0c:	0000246d 	.word	0x0000246d
-    1b10:	0000358c 	.word	0x0000358c
-    1b14:	00003592 	.word	0x00003592
-    1b18:	00003597 	.word	0x00003597
-    1b1c:	00002561 	.word	0x00002561
-    1b20:	00000c41 	.word	0x00000c41
-    1b24:	00002259 	.word	0x00002259
-    1b28:	00002299 	.word	0x00002299
-    1b2c:	00001f21 	.word	0x00001f21
-    1b30:	447a0000 	.word	0x447a0000
-    1b34:	00001ce1 	.word	0x00001ce1
-    1b38:	000035d3 	.word	0x000035d3
-    1b3c:	0000134d 	.word	0x0000134d
-    1b40:	000035e4 	.word	0x000035e4
-    1b44:	000035ea 	.word	0x000035ea
-
-00001b48 <__gnu_thumb1_case_uqi>:
-    1b48:	b402      	push	{r1}
-    1b4a:	4671      	mov	r1, lr
-    1b4c:	0849      	lsrs	r1, r1, #1
-    1b4e:	0049      	lsls	r1, r1, #1
-    1b50:	5c09      	ldrb	r1, [r1, r0]
-    1b52:	0049      	lsls	r1, r1, #1
-    1b54:	448e      	add	lr, r1
-    1b56:	bc02      	pop	{r1}
-    1b58:	4770      	bx	lr
-    1b5a:	46c0      	nop			; (mov r8, r8)
-
-00001b5c <__udivsi3>:
-    1b5c:	2200      	movs	r2, #0
-    1b5e:	0843      	lsrs	r3, r0, #1
-    1b60:	428b      	cmp	r3, r1
-    1b62:	d374      	bcc.n	1c4e <__udivsi3+0xf2>
-    1b64:	0903      	lsrs	r3, r0, #4
-    1b66:	428b      	cmp	r3, r1
-    1b68:	d35f      	bcc.n	1c2a <__udivsi3+0xce>
-    1b6a:	0a03      	lsrs	r3, r0, #8
-    1b6c:	428b      	cmp	r3, r1
-    1b6e:	d344      	bcc.n	1bfa <__udivsi3+0x9e>
-    1b70:	0b03      	lsrs	r3, r0, #12
-    1b72:	428b      	cmp	r3, r1
-    1b74:	d328      	bcc.n	1bc8 <__udivsi3+0x6c>
-    1b76:	0c03      	lsrs	r3, r0, #16
-    1b78:	428b      	cmp	r3, r1
-    1b7a:	d30d      	bcc.n	1b98 <__udivsi3+0x3c>
-    1b7c:	22ff      	movs	r2, #255	; 0xff
-    1b7e:	0209      	lsls	r1, r1, #8
-    1b80:	ba12      	rev	r2, r2
-    1b82:	0c03      	lsrs	r3, r0, #16
-    1b84:	428b      	cmp	r3, r1
-    1b86:	d302      	bcc.n	1b8e <__udivsi3+0x32>
-    1b88:	1212      	asrs	r2, r2, #8
-    1b8a:	0209      	lsls	r1, r1, #8
-    1b8c:	d065      	beq.n	1c5a <__udivsi3+0xfe>
-    1b8e:	0b03      	lsrs	r3, r0, #12
-    1b90:	428b      	cmp	r3, r1
-    1b92:	d319      	bcc.n	1bc8 <__udivsi3+0x6c>
-    1b94:	e000      	b.n	1b98 <__udivsi3+0x3c>
-    1b96:	0a09      	lsrs	r1, r1, #8
-    1b98:	0bc3      	lsrs	r3, r0, #15
-    1b9a:	428b      	cmp	r3, r1
-    1b9c:	d301      	bcc.n	1ba2 <__udivsi3+0x46>
-    1b9e:	03cb      	lsls	r3, r1, #15
-    1ba0:	1ac0      	subs	r0, r0, r3
-    1ba2:	4152      	adcs	r2, r2
-    1ba4:	0b83      	lsrs	r3, r0, #14
-    1ba6:	428b      	cmp	r3, r1
-    1ba8:	d301      	bcc.n	1bae <__udivsi3+0x52>
-    1baa:	038b      	lsls	r3, r1, #14
-    1bac:	1ac0      	subs	r0, r0, r3
-    1bae:	4152      	adcs	r2, r2
-    1bb0:	0b43      	lsrs	r3, r0, #13
-    1bb2:	428b      	cmp	r3, r1
-    1bb4:	d301      	bcc.n	1bba <__udivsi3+0x5e>
-    1bb6:	034b      	lsls	r3, r1, #13
-    1bb8:	1ac0      	subs	r0, r0, r3
-    1bba:	4152      	adcs	r2, r2
-    1bbc:	0b03      	lsrs	r3, r0, #12
-    1bbe:	428b      	cmp	r3, r1
-    1bc0:	d301      	bcc.n	1bc6 <__udivsi3+0x6a>
-    1bc2:	030b      	lsls	r3, r1, #12
-    1bc4:	1ac0      	subs	r0, r0, r3
-    1bc6:	4152      	adcs	r2, r2
-    1bc8:	0ac3      	lsrs	r3, r0, #11
-    1bca:	428b      	cmp	r3, r1
-    1bcc:	d301      	bcc.n	1bd2 <__udivsi3+0x76>
-    1bce:	02cb      	lsls	r3, r1, #11
-    1bd0:	1ac0      	subs	r0, r0, r3
-    1bd2:	4152      	adcs	r2, r2
-    1bd4:	0a83      	lsrs	r3, r0, #10
-    1bd6:	428b      	cmp	r3, r1
-    1bd8:	d301      	bcc.n	1bde <__udivsi3+0x82>
-    1bda:	028b      	lsls	r3, r1, #10
-    1bdc:	1ac0      	subs	r0, r0, r3
-    1bde:	4152      	adcs	r2, r2
-    1be0:	0a43      	lsrs	r3, r0, #9
-    1be2:	428b      	cmp	r3, r1
-    1be4:	d301      	bcc.n	1bea <__udivsi3+0x8e>
-    1be6:	024b      	lsls	r3, r1, #9
-    1be8:	1ac0      	subs	r0, r0, r3
-    1bea:	4152      	adcs	r2, r2
-    1bec:	0a03      	lsrs	r3, r0, #8
-    1bee:	428b      	cmp	r3, r1
-    1bf0:	d301      	bcc.n	1bf6 <__udivsi3+0x9a>
-    1bf2:	020b      	lsls	r3, r1, #8
-    1bf4:	1ac0      	subs	r0, r0, r3
-    1bf6:	4152      	adcs	r2, r2
-    1bf8:	d2cd      	bcs.n	1b96 <__udivsi3+0x3a>
-    1bfa:	09c3      	lsrs	r3, r0, #7
-    1bfc:	428b      	cmp	r3, r1
-    1bfe:	d301      	bcc.n	1c04 <__udivsi3+0xa8>
-    1c00:	01cb      	lsls	r3, r1, #7
-    1c02:	1ac0      	subs	r0, r0, r3
-    1c04:	4152      	adcs	r2, r2
-    1c06:	0983      	lsrs	r3, r0, #6
-    1c08:	428b      	cmp	r3, r1
-    1c0a:	d301      	bcc.n	1c10 <__udivsi3+0xb4>
-    1c0c:	018b      	lsls	r3, r1, #6
-    1c0e:	1ac0      	subs	r0, r0, r3
-    1c10:	4152      	adcs	r2, r2
-    1c12:	0943      	lsrs	r3, r0, #5
-    1c14:	428b      	cmp	r3, r1
-    1c16:	d301      	bcc.n	1c1c <__udivsi3+0xc0>
-    1c18:	014b      	lsls	r3, r1, #5
-    1c1a:	1ac0      	subs	r0, r0, r3
-    1c1c:	4152      	adcs	r2, r2
-    1c1e:	0903      	lsrs	r3, r0, #4
-    1c20:	428b      	cmp	r3, r1
-    1c22:	d301      	bcc.n	1c28 <__udivsi3+0xcc>
-    1c24:	010b      	lsls	r3, r1, #4
-    1c26:	1ac0      	subs	r0, r0, r3
-    1c28:	4152      	adcs	r2, r2
-    1c2a:	08c3      	lsrs	r3, r0, #3
-    1c2c:	428b      	cmp	r3, r1
-    1c2e:	d301      	bcc.n	1c34 <__udivsi3+0xd8>
-    1c30:	00cb      	lsls	r3, r1, #3
-    1c32:	1ac0      	subs	r0, r0, r3
-    1c34:	4152      	adcs	r2, r2
-    1c36:	0883      	lsrs	r3, r0, #2
-    1c38:	428b      	cmp	r3, r1
-    1c3a:	d301      	bcc.n	1c40 <__udivsi3+0xe4>
-    1c3c:	008b      	lsls	r3, r1, #2
-    1c3e:	1ac0      	subs	r0, r0, r3
-    1c40:	4152      	adcs	r2, r2
-    1c42:	0843      	lsrs	r3, r0, #1
-    1c44:	428b      	cmp	r3, r1
-    1c46:	d301      	bcc.n	1c4c <__udivsi3+0xf0>
-    1c48:	004b      	lsls	r3, r1, #1
-    1c4a:	1ac0      	subs	r0, r0, r3
-    1c4c:	4152      	adcs	r2, r2
-    1c4e:	1a41      	subs	r1, r0, r1
-    1c50:	d200      	bcs.n	1c54 <__udivsi3+0xf8>
-    1c52:	4601      	mov	r1, r0
-    1c54:	4152      	adcs	r2, r2
-    1c56:	4610      	mov	r0, r2
-    1c58:	4770      	bx	lr
-    1c5a:	e7ff      	b.n	1c5c <__udivsi3+0x100>
-    1c5c:	b501      	push	{r0, lr}
-    1c5e:	2000      	movs	r0, #0
-    1c60:	f000 f806 	bl	1c70 <__aeabi_idiv0>
-    1c64:	bd02      	pop	{r1, pc}
-    1c66:	46c0      	nop			; (mov r8, r8)
-
-00001c68 <__aeabi_uidivmod>:
-    1c68:	2900      	cmp	r1, #0
-    1c6a:	d0f7      	beq.n	1c5c <__udivsi3+0x100>
-    1c6c:	e776      	b.n	1b5c <__udivsi3>
-    1c6e:	4770      	bx	lr
-
-00001c70 <__aeabi_idiv0>:
-    1c70:	4770      	bx	lr
-    1c72:	46c0      	nop			; (mov r8, r8)
-
-00001c74 <__aeabi_llsl>:
-    1c74:	4091      	lsls	r1, r2
-    1c76:	1c03      	adds	r3, r0, #0
-    1c78:	4090      	lsls	r0, r2
-    1c7a:	469c      	mov	ip, r3
-    1c7c:	3a20      	subs	r2, #32
-    1c7e:	4093      	lsls	r3, r2
-    1c80:	4319      	orrs	r1, r3
-    1c82:	4252      	negs	r2, r2
-    1c84:	4663      	mov	r3, ip
-    1c86:	40d3      	lsrs	r3, r2
-    1c88:	4319      	orrs	r1, r3
-    1c8a:	4770      	bx	lr
-
-00001c8c <__aeabi_lmul>:
-    1c8c:	b5f0      	push	{r4, r5, r6, r7, lr}
-    1c8e:	46ce      	mov	lr, r9
-    1c90:	4647      	mov	r7, r8
-    1c92:	0415      	lsls	r5, r2, #16
-    1c94:	0c2d      	lsrs	r5, r5, #16
-    1c96:	002e      	movs	r6, r5
-    1c98:	b580      	push	{r7, lr}
-    1c9a:	0407      	lsls	r7, r0, #16
-    1c9c:	0c14      	lsrs	r4, r2, #16
-    1c9e:	0c3f      	lsrs	r7, r7, #16
-    1ca0:	4699      	mov	r9, r3
-    1ca2:	0c03      	lsrs	r3, r0, #16
-    1ca4:	437e      	muls	r6, r7
-    1ca6:	435d      	muls	r5, r3
-    1ca8:	4367      	muls	r7, r4
-    1caa:	4363      	muls	r3, r4
-    1cac:	197f      	adds	r7, r7, r5
-    1cae:	0c34      	lsrs	r4, r6, #16
-    1cb0:	19e4      	adds	r4, r4, r7
-    1cb2:	469c      	mov	ip, r3
-    1cb4:	42a5      	cmp	r5, r4
-    1cb6:	d903      	bls.n	1cc0 <__aeabi_lmul+0x34>
-    1cb8:	2380      	movs	r3, #128	; 0x80
-    1cba:	025b      	lsls	r3, r3, #9
-    1cbc:	4698      	mov	r8, r3
-    1cbe:	44c4      	add	ip, r8
-    1cc0:	464b      	mov	r3, r9
-    1cc2:	4351      	muls	r1, r2
-    1cc4:	4343      	muls	r3, r0
-    1cc6:	0436      	lsls	r6, r6, #16
-    1cc8:	0c36      	lsrs	r6, r6, #16
-    1cca:	0c25      	lsrs	r5, r4, #16
-    1ccc:	0424      	lsls	r4, r4, #16
-    1cce:	4465      	add	r5, ip
-    1cd0:	19a4      	adds	r4, r4, r6
-    1cd2:	1859      	adds	r1, r3, r1
-    1cd4:	1949      	adds	r1, r1, r5
-    1cd6:	0020      	movs	r0, r4
-    1cd8:	bc0c      	pop	{r2, r3}
-    1cda:	4690      	mov	r8, r2
-    1cdc:	4699      	mov	r9, r3
-    1cde:	bdf0      	pop	{r4, r5, r6, r7, pc}
-
-00001ce0 <__aeabi_fmul>:
-    1ce0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    1ce2:	4657      	mov	r7, sl
-    1ce4:	464e      	mov	r6, r9
-    1ce6:	4645      	mov	r5, r8
-    1ce8:	46de      	mov	lr, fp
-    1cea:	b5e0      	push	{r5, r6, r7, lr}
-    1cec:	0247      	lsls	r7, r0, #9
-    1cee:	0046      	lsls	r6, r0, #1
-    1cf0:	4688      	mov	r8, r1
-    1cf2:	0a7f      	lsrs	r7, r7, #9
-    1cf4:	0e36      	lsrs	r6, r6, #24
-    1cf6:	0fc4      	lsrs	r4, r0, #31
-    1cf8:	2e00      	cmp	r6, #0
-    1cfa:	d047      	beq.n	1d8c <__aeabi_fmul+0xac>
-    1cfc:	2eff      	cmp	r6, #255	; 0xff
-    1cfe:	d024      	beq.n	1d4a <__aeabi_fmul+0x6a>
-    1d00:	00fb      	lsls	r3, r7, #3
-    1d02:	2780      	movs	r7, #128	; 0x80
-    1d04:	04ff      	lsls	r7, r7, #19
-    1d06:	431f      	orrs	r7, r3
-    1d08:	2300      	movs	r3, #0
-    1d0a:	4699      	mov	r9, r3
-    1d0c:	469a      	mov	sl, r3
-    1d0e:	3e7f      	subs	r6, #127	; 0x7f
-    1d10:	4643      	mov	r3, r8
-    1d12:	025d      	lsls	r5, r3, #9
-    1d14:	0058      	lsls	r0, r3, #1
-    1d16:	0fdb      	lsrs	r3, r3, #31
-    1d18:	0a6d      	lsrs	r5, r5, #9
-    1d1a:	0e00      	lsrs	r0, r0, #24
-    1d1c:	4698      	mov	r8, r3
-    1d1e:	d043      	beq.n	1da8 <__aeabi_fmul+0xc8>
-    1d20:	28ff      	cmp	r0, #255	; 0xff
-    1d22:	d03b      	beq.n	1d9c <__aeabi_fmul+0xbc>
-    1d24:	00eb      	lsls	r3, r5, #3
-    1d26:	2580      	movs	r5, #128	; 0x80
-    1d28:	2200      	movs	r2, #0
-    1d2a:	04ed      	lsls	r5, r5, #19
-    1d2c:	431d      	orrs	r5, r3
-    1d2e:	387f      	subs	r0, #127	; 0x7f
-    1d30:	1836      	adds	r6, r6, r0
-    1d32:	1c73      	adds	r3, r6, #1
-    1d34:	4641      	mov	r1, r8
-    1d36:	469b      	mov	fp, r3
-    1d38:	464b      	mov	r3, r9
-    1d3a:	4061      	eors	r1, r4
-    1d3c:	4313      	orrs	r3, r2
-    1d3e:	2b0f      	cmp	r3, #15
-    1d40:	d864      	bhi.n	1e0c <__aeabi_fmul+0x12c>
-    1d42:	4875      	ldr	r0, [pc, #468]	; (1f18 <__aeabi_fmul+0x238>)
-    1d44:	009b      	lsls	r3, r3, #2
-    1d46:	58c3      	ldr	r3, [r0, r3]
-    1d48:	469f      	mov	pc, r3
-    1d4a:	2f00      	cmp	r7, #0
-    1d4c:	d142      	bne.n	1dd4 <__aeabi_fmul+0xf4>
-    1d4e:	2308      	movs	r3, #8
-    1d50:	4699      	mov	r9, r3
-    1d52:	3b06      	subs	r3, #6
-    1d54:	26ff      	movs	r6, #255	; 0xff
-    1d56:	469a      	mov	sl, r3
-    1d58:	e7da      	b.n	1d10 <__aeabi_fmul+0x30>
-    1d5a:	4641      	mov	r1, r8
-    1d5c:	2a02      	cmp	r2, #2
-    1d5e:	d028      	beq.n	1db2 <__aeabi_fmul+0xd2>
-    1d60:	2a03      	cmp	r2, #3
-    1d62:	d100      	bne.n	1d66 <__aeabi_fmul+0x86>
-    1d64:	e0ce      	b.n	1f04 <__aeabi_fmul+0x224>
-    1d66:	2a01      	cmp	r2, #1
-    1d68:	d000      	beq.n	1d6c <__aeabi_fmul+0x8c>
-    1d6a:	e0ac      	b.n	1ec6 <__aeabi_fmul+0x1e6>
-    1d6c:	4011      	ands	r1, r2
-    1d6e:	2000      	movs	r0, #0
-    1d70:	2200      	movs	r2, #0
-    1d72:	b2cc      	uxtb	r4, r1
-    1d74:	0240      	lsls	r0, r0, #9
-    1d76:	05d2      	lsls	r2, r2, #23
-    1d78:	0a40      	lsrs	r0, r0, #9
-    1d7a:	07e4      	lsls	r4, r4, #31
-    1d7c:	4310      	orrs	r0, r2
-    1d7e:	4320      	orrs	r0, r4
-    1d80:	bc3c      	pop	{r2, r3, r4, r5}
-    1d82:	4690      	mov	r8, r2
-    1d84:	4699      	mov	r9, r3
-    1d86:	46a2      	mov	sl, r4
-    1d88:	46ab      	mov	fp, r5
-    1d8a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    1d8c:	2f00      	cmp	r7, #0
-    1d8e:	d115      	bne.n	1dbc <__aeabi_fmul+0xdc>
-    1d90:	2304      	movs	r3, #4
-    1d92:	4699      	mov	r9, r3
-    1d94:	3b03      	subs	r3, #3
-    1d96:	2600      	movs	r6, #0
-    1d98:	469a      	mov	sl, r3
-    1d9a:	e7b9      	b.n	1d10 <__aeabi_fmul+0x30>
-    1d9c:	20ff      	movs	r0, #255	; 0xff
-    1d9e:	2202      	movs	r2, #2
-    1da0:	2d00      	cmp	r5, #0
-    1da2:	d0c5      	beq.n	1d30 <__aeabi_fmul+0x50>
-    1da4:	2203      	movs	r2, #3
-    1da6:	e7c3      	b.n	1d30 <__aeabi_fmul+0x50>
-    1da8:	2d00      	cmp	r5, #0
-    1daa:	d119      	bne.n	1de0 <__aeabi_fmul+0x100>
-    1dac:	2000      	movs	r0, #0
-    1dae:	2201      	movs	r2, #1
-    1db0:	e7be      	b.n	1d30 <__aeabi_fmul+0x50>
-    1db2:	2401      	movs	r4, #1
-    1db4:	22ff      	movs	r2, #255	; 0xff
-    1db6:	400c      	ands	r4, r1
-    1db8:	2000      	movs	r0, #0
-    1dba:	e7db      	b.n	1d74 <__aeabi_fmul+0x94>
-    1dbc:	0038      	movs	r0, r7
-    1dbe:	f000 fb01 	bl	23c4 <__clzsi2>
-    1dc2:	2676      	movs	r6, #118	; 0x76
-    1dc4:	1f43      	subs	r3, r0, #5
-    1dc6:	409f      	lsls	r7, r3
-    1dc8:	2300      	movs	r3, #0
-    1dca:	4276      	negs	r6, r6
-    1dcc:	1a36      	subs	r6, r6, r0
-    1dce:	4699      	mov	r9, r3
-    1dd0:	469a      	mov	sl, r3
-    1dd2:	e79d      	b.n	1d10 <__aeabi_fmul+0x30>
-    1dd4:	230c      	movs	r3, #12
-    1dd6:	4699      	mov	r9, r3
-    1dd8:	3b09      	subs	r3, #9
-    1dda:	26ff      	movs	r6, #255	; 0xff
-    1ddc:	469a      	mov	sl, r3
-    1dde:	e797      	b.n	1d10 <__aeabi_fmul+0x30>
-    1de0:	0028      	movs	r0, r5
-    1de2:	f000 faef 	bl	23c4 <__clzsi2>
-    1de6:	1f43      	subs	r3, r0, #5
-    1de8:	409d      	lsls	r5, r3
-    1dea:	2376      	movs	r3, #118	; 0x76
-    1dec:	425b      	negs	r3, r3
-    1dee:	1a18      	subs	r0, r3, r0
-    1df0:	2200      	movs	r2, #0
-    1df2:	e79d      	b.n	1d30 <__aeabi_fmul+0x50>
-    1df4:	2080      	movs	r0, #128	; 0x80
-    1df6:	2400      	movs	r4, #0
-    1df8:	03c0      	lsls	r0, r0, #15
-    1dfa:	22ff      	movs	r2, #255	; 0xff
-    1dfc:	e7ba      	b.n	1d74 <__aeabi_fmul+0x94>
-    1dfe:	003d      	movs	r5, r7
-    1e00:	4652      	mov	r2, sl
-    1e02:	e7ab      	b.n	1d5c <__aeabi_fmul+0x7c>
-    1e04:	003d      	movs	r5, r7
-    1e06:	0021      	movs	r1, r4
-    1e08:	4652      	mov	r2, sl
-    1e0a:	e7a7      	b.n	1d5c <__aeabi_fmul+0x7c>
-    1e0c:	0c3b      	lsrs	r3, r7, #16
-    1e0e:	469c      	mov	ip, r3
-    1e10:	042a      	lsls	r2, r5, #16
-    1e12:	0c12      	lsrs	r2, r2, #16
-    1e14:	0c2b      	lsrs	r3, r5, #16
-    1e16:	0014      	movs	r4, r2
-    1e18:	4660      	mov	r0, ip
-    1e1a:	4665      	mov	r5, ip
-    1e1c:	043f      	lsls	r7, r7, #16
-    1e1e:	0c3f      	lsrs	r7, r7, #16
-    1e20:	437c      	muls	r4, r7
-    1e22:	4342      	muls	r2, r0
-    1e24:	435d      	muls	r5, r3
-    1e26:	437b      	muls	r3, r7
-    1e28:	0c27      	lsrs	r7, r4, #16
-    1e2a:	189b      	adds	r3, r3, r2
-    1e2c:	18ff      	adds	r7, r7, r3
-    1e2e:	42ba      	cmp	r2, r7
-    1e30:	d903      	bls.n	1e3a <__aeabi_fmul+0x15a>
-    1e32:	2380      	movs	r3, #128	; 0x80
-    1e34:	025b      	lsls	r3, r3, #9
-    1e36:	469c      	mov	ip, r3
-    1e38:	4465      	add	r5, ip
-    1e3a:	0424      	lsls	r4, r4, #16
-    1e3c:	043a      	lsls	r2, r7, #16
-    1e3e:	0c24      	lsrs	r4, r4, #16
-    1e40:	1912      	adds	r2, r2, r4
-    1e42:	0193      	lsls	r3, r2, #6
-    1e44:	1e5c      	subs	r4, r3, #1
-    1e46:	41a3      	sbcs	r3, r4
-    1e48:	0c3f      	lsrs	r7, r7, #16
-    1e4a:	0e92      	lsrs	r2, r2, #26
-    1e4c:	197d      	adds	r5, r7, r5
-    1e4e:	431a      	orrs	r2, r3
-    1e50:	01ad      	lsls	r5, r5, #6
-    1e52:	4315      	orrs	r5, r2
-    1e54:	012b      	lsls	r3, r5, #4
-    1e56:	d504      	bpl.n	1e62 <__aeabi_fmul+0x182>
-    1e58:	2301      	movs	r3, #1
-    1e5a:	465e      	mov	r6, fp
-    1e5c:	086a      	lsrs	r2, r5, #1
-    1e5e:	401d      	ands	r5, r3
-    1e60:	4315      	orrs	r5, r2
-    1e62:	0032      	movs	r2, r6
-    1e64:	327f      	adds	r2, #127	; 0x7f
-    1e66:	2a00      	cmp	r2, #0
-    1e68:	dd25      	ble.n	1eb6 <__aeabi_fmul+0x1d6>
-    1e6a:	076b      	lsls	r3, r5, #29
-    1e6c:	d004      	beq.n	1e78 <__aeabi_fmul+0x198>
-    1e6e:	230f      	movs	r3, #15
-    1e70:	402b      	ands	r3, r5
-    1e72:	2b04      	cmp	r3, #4
-    1e74:	d000      	beq.n	1e78 <__aeabi_fmul+0x198>
-    1e76:	3504      	adds	r5, #4
-    1e78:	012b      	lsls	r3, r5, #4
-    1e7a:	d503      	bpl.n	1e84 <__aeabi_fmul+0x1a4>
-    1e7c:	0032      	movs	r2, r6
-    1e7e:	4b27      	ldr	r3, [pc, #156]	; (1f1c <__aeabi_fmul+0x23c>)
-    1e80:	3280      	adds	r2, #128	; 0x80
-    1e82:	401d      	ands	r5, r3
-    1e84:	2afe      	cmp	r2, #254	; 0xfe
-    1e86:	dc94      	bgt.n	1db2 <__aeabi_fmul+0xd2>
-    1e88:	2401      	movs	r4, #1
-    1e8a:	01a8      	lsls	r0, r5, #6
-    1e8c:	0a40      	lsrs	r0, r0, #9
-    1e8e:	b2d2      	uxtb	r2, r2
-    1e90:	400c      	ands	r4, r1
-    1e92:	e76f      	b.n	1d74 <__aeabi_fmul+0x94>
-    1e94:	2080      	movs	r0, #128	; 0x80
-    1e96:	03c0      	lsls	r0, r0, #15
-    1e98:	4207      	tst	r7, r0
-    1e9a:	d007      	beq.n	1eac <__aeabi_fmul+0x1cc>
-    1e9c:	4205      	tst	r5, r0
-    1e9e:	d105      	bne.n	1eac <__aeabi_fmul+0x1cc>
-    1ea0:	4328      	orrs	r0, r5
-    1ea2:	0240      	lsls	r0, r0, #9
-    1ea4:	0a40      	lsrs	r0, r0, #9
-    1ea6:	4644      	mov	r4, r8
-    1ea8:	22ff      	movs	r2, #255	; 0xff
-    1eaa:	e763      	b.n	1d74 <__aeabi_fmul+0x94>
-    1eac:	4338      	orrs	r0, r7
-    1eae:	0240      	lsls	r0, r0, #9
-    1eb0:	0a40      	lsrs	r0, r0, #9
-    1eb2:	22ff      	movs	r2, #255	; 0xff
-    1eb4:	e75e      	b.n	1d74 <__aeabi_fmul+0x94>
-    1eb6:	2401      	movs	r4, #1
-    1eb8:	1aa3      	subs	r3, r4, r2
-    1eba:	2b1b      	cmp	r3, #27
-    1ebc:	dd05      	ble.n	1eca <__aeabi_fmul+0x1ea>
-    1ebe:	400c      	ands	r4, r1
-    1ec0:	2200      	movs	r2, #0
-    1ec2:	2000      	movs	r0, #0
-    1ec4:	e756      	b.n	1d74 <__aeabi_fmul+0x94>
-    1ec6:	465e      	mov	r6, fp
-    1ec8:	e7cb      	b.n	1e62 <__aeabi_fmul+0x182>
-    1eca:	002a      	movs	r2, r5
-    1ecc:	2020      	movs	r0, #32
-    1ece:	40da      	lsrs	r2, r3
-    1ed0:	1ac3      	subs	r3, r0, r3
-    1ed2:	409d      	lsls	r5, r3
-    1ed4:	002b      	movs	r3, r5
-    1ed6:	1e5d      	subs	r5, r3, #1
-    1ed8:	41ab      	sbcs	r3, r5
-    1eda:	4313      	orrs	r3, r2
-    1edc:	075a      	lsls	r2, r3, #29
-    1ede:	d004      	beq.n	1eea <__aeabi_fmul+0x20a>
-    1ee0:	220f      	movs	r2, #15
-    1ee2:	401a      	ands	r2, r3
-    1ee4:	2a04      	cmp	r2, #4
-    1ee6:	d000      	beq.n	1eea <__aeabi_fmul+0x20a>
-    1ee8:	3304      	adds	r3, #4
-    1eea:	015a      	lsls	r2, r3, #5
-    1eec:	d504      	bpl.n	1ef8 <__aeabi_fmul+0x218>
-    1eee:	2401      	movs	r4, #1
-    1ef0:	2201      	movs	r2, #1
-    1ef2:	400c      	ands	r4, r1
-    1ef4:	2000      	movs	r0, #0
-    1ef6:	e73d      	b.n	1d74 <__aeabi_fmul+0x94>
-    1ef8:	2401      	movs	r4, #1
-    1efa:	019b      	lsls	r3, r3, #6
-    1efc:	0a58      	lsrs	r0, r3, #9
-    1efe:	400c      	ands	r4, r1
-    1f00:	2200      	movs	r2, #0
-    1f02:	e737      	b.n	1d74 <__aeabi_fmul+0x94>
-    1f04:	2080      	movs	r0, #128	; 0x80
-    1f06:	2401      	movs	r4, #1
-    1f08:	03c0      	lsls	r0, r0, #15
-    1f0a:	4328      	orrs	r0, r5
-    1f0c:	0240      	lsls	r0, r0, #9
-    1f0e:	0a40      	lsrs	r0, r0, #9
-    1f10:	400c      	ands	r4, r1
-    1f12:	22ff      	movs	r2, #255	; 0xff
-    1f14:	e72e      	b.n	1d74 <__aeabi_fmul+0x94>
-    1f16:	46c0      	nop			; (mov r8, r8)
-    1f18:	000035f0 	.word	0x000035f0
-    1f1c:	f7ffffff 	.word	0xf7ffffff
-
-00001f20 <__aeabi_fsub>:
-    1f20:	b5f0      	push	{r4, r5, r6, r7, lr}
-    1f22:	464f      	mov	r7, r9
-    1f24:	46d6      	mov	lr, sl
-    1f26:	4646      	mov	r6, r8
-    1f28:	0044      	lsls	r4, r0, #1
-    1f2a:	b5c0      	push	{r6, r7, lr}
-    1f2c:	0fc2      	lsrs	r2, r0, #31
-    1f2e:	0247      	lsls	r7, r0, #9
-    1f30:	0248      	lsls	r0, r1, #9
-    1f32:	0a40      	lsrs	r0, r0, #9
-    1f34:	4684      	mov	ip, r0
-    1f36:	4666      	mov	r6, ip
-    1f38:	0a7b      	lsrs	r3, r7, #9
-    1f3a:	0048      	lsls	r0, r1, #1
-    1f3c:	0fc9      	lsrs	r1, r1, #31
-    1f3e:	469a      	mov	sl, r3
-    1f40:	0e24      	lsrs	r4, r4, #24
-    1f42:	0015      	movs	r5, r2
-    1f44:	00db      	lsls	r3, r3, #3
-    1f46:	0e00      	lsrs	r0, r0, #24
-    1f48:	4689      	mov	r9, r1
-    1f4a:	00f6      	lsls	r6, r6, #3
-    1f4c:	28ff      	cmp	r0, #255	; 0xff
-    1f4e:	d100      	bne.n	1f52 <__aeabi_fsub+0x32>
-    1f50:	e08f      	b.n	2072 <STACK_SIZE+0x72>
-    1f52:	2101      	movs	r1, #1
-    1f54:	464f      	mov	r7, r9
-    1f56:	404f      	eors	r7, r1
-    1f58:	0039      	movs	r1, r7
-    1f5a:	4291      	cmp	r1, r2
-    1f5c:	d066      	beq.n	202c <STACK_SIZE+0x2c>
-    1f5e:	1a22      	subs	r2, r4, r0
-    1f60:	2a00      	cmp	r2, #0
-    1f62:	dc00      	bgt.n	1f66 <__aeabi_fsub+0x46>
-    1f64:	e09d      	b.n	20a2 <STACK_SIZE+0xa2>
-    1f66:	2800      	cmp	r0, #0
-    1f68:	d13d      	bne.n	1fe6 <__aeabi_fsub+0xc6>
-    1f6a:	2e00      	cmp	r6, #0
-    1f6c:	d100      	bne.n	1f70 <__aeabi_fsub+0x50>
-    1f6e:	e08b      	b.n	2088 <STACK_SIZE+0x88>
-    1f70:	1e51      	subs	r1, r2, #1
-    1f72:	2900      	cmp	r1, #0
-    1f74:	d000      	beq.n	1f78 <__aeabi_fsub+0x58>
-    1f76:	e0b5      	b.n	20e4 <STACK_SIZE+0xe4>
-    1f78:	2401      	movs	r4, #1
-    1f7a:	1b9b      	subs	r3, r3, r6
-    1f7c:	015a      	lsls	r2, r3, #5
-    1f7e:	d544      	bpl.n	200a <STACK_SIZE+0xa>
-    1f80:	019b      	lsls	r3, r3, #6
-    1f82:	099f      	lsrs	r7, r3, #6
-    1f84:	0038      	movs	r0, r7
-    1f86:	f000 fa1d 	bl	23c4 <__clzsi2>
-    1f8a:	3805      	subs	r0, #5
-    1f8c:	4087      	lsls	r7, r0
-    1f8e:	4284      	cmp	r4, r0
-    1f90:	dd00      	ble.n	1f94 <__aeabi_fsub+0x74>
-    1f92:	e096      	b.n	20c2 <STACK_SIZE+0xc2>
-    1f94:	1b04      	subs	r4, r0, r4
-    1f96:	003a      	movs	r2, r7
-    1f98:	2020      	movs	r0, #32
-    1f9a:	3401      	adds	r4, #1
-    1f9c:	40e2      	lsrs	r2, r4
-    1f9e:	1b04      	subs	r4, r0, r4
-    1fa0:	40a7      	lsls	r7, r4
-    1fa2:	003b      	movs	r3, r7
-    1fa4:	1e5f      	subs	r7, r3, #1
-    1fa6:	41bb      	sbcs	r3, r7
-    1fa8:	2400      	movs	r4, #0
-    1faa:	4313      	orrs	r3, r2
-    1fac:	075a      	lsls	r2, r3, #29
-    1fae:	d004      	beq.n	1fba <__aeabi_fsub+0x9a>
-    1fb0:	220f      	movs	r2, #15
-    1fb2:	401a      	ands	r2, r3
-    1fb4:	2a04      	cmp	r2, #4
-    1fb6:	d000      	beq.n	1fba <__aeabi_fsub+0x9a>
-    1fb8:	3304      	adds	r3, #4
-    1fba:	015a      	lsls	r2, r3, #5
-    1fbc:	d527      	bpl.n	200e <STACK_SIZE+0xe>
-    1fbe:	3401      	adds	r4, #1
-    1fc0:	2cff      	cmp	r4, #255	; 0xff
-    1fc2:	d100      	bne.n	1fc6 <__aeabi_fsub+0xa6>
-    1fc4:	e079      	b.n	20ba <STACK_SIZE+0xba>
-    1fc6:	2201      	movs	r2, #1
-    1fc8:	019b      	lsls	r3, r3, #6
-    1fca:	0a5b      	lsrs	r3, r3, #9
-    1fcc:	b2e4      	uxtb	r4, r4
-    1fce:	402a      	ands	r2, r5
-    1fd0:	025b      	lsls	r3, r3, #9
-    1fd2:	05e4      	lsls	r4, r4, #23
-    1fd4:	0a58      	lsrs	r0, r3, #9
-    1fd6:	07d2      	lsls	r2, r2, #31
-    1fd8:	4320      	orrs	r0, r4
-    1fda:	4310      	orrs	r0, r2
-    1fdc:	bc1c      	pop	{r2, r3, r4}
-    1fde:	4690      	mov	r8, r2
-    1fe0:	4699      	mov	r9, r3
-    1fe2:	46a2      	mov	sl, r4
-    1fe4:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    1fe6:	2cff      	cmp	r4, #255	; 0xff
-    1fe8:	d0e0      	beq.n	1fac <__aeabi_fsub+0x8c>
-    1fea:	2180      	movs	r1, #128	; 0x80
-    1fec:	04c9      	lsls	r1, r1, #19
-    1fee:	430e      	orrs	r6, r1
-    1ff0:	2a1b      	cmp	r2, #27
-    1ff2:	dc7b      	bgt.n	20ec <STACK_SIZE+0xec>
-    1ff4:	0031      	movs	r1, r6
-    1ff6:	2020      	movs	r0, #32
-    1ff8:	40d1      	lsrs	r1, r2
-    1ffa:	1a82      	subs	r2, r0, r2
-    1ffc:	4096      	lsls	r6, r2
-    1ffe:	1e72      	subs	r2, r6, #1
-    2000:	4196      	sbcs	r6, r2
-    2002:	430e      	orrs	r6, r1
-    2004:	1b9b      	subs	r3, r3, r6
-    2006:	015a      	lsls	r2, r3, #5
-    2008:	d4ba      	bmi.n	1f80 <__aeabi_fsub+0x60>
-    200a:	075a      	lsls	r2, r3, #29
-    200c:	d1d0      	bne.n	1fb0 <__aeabi_fsub+0x90>
-    200e:	2201      	movs	r2, #1
-    2010:	08df      	lsrs	r7, r3, #3
-    2012:	402a      	ands	r2, r5
-    2014:	2cff      	cmp	r4, #255	; 0xff
-    2016:	d133      	bne.n	2080 <STACK_SIZE+0x80>
-    2018:	2f00      	cmp	r7, #0
-    201a:	d100      	bne.n	201e <STACK_SIZE+0x1e>
-    201c:	e0a8      	b.n	2170 <STACK_SIZE+0x170>
-    201e:	2380      	movs	r3, #128	; 0x80
-    2020:	03db      	lsls	r3, r3, #15
-    2022:	433b      	orrs	r3, r7
-    2024:	025b      	lsls	r3, r3, #9
-    2026:	0a5b      	lsrs	r3, r3, #9
-    2028:	24ff      	movs	r4, #255	; 0xff
-    202a:	e7d1      	b.n	1fd0 <__aeabi_fsub+0xb0>
-    202c:	1a21      	subs	r1, r4, r0
-    202e:	2900      	cmp	r1, #0
-    2030:	dd4c      	ble.n	20cc <STACK_SIZE+0xcc>
-    2032:	2800      	cmp	r0, #0
-    2034:	d02a      	beq.n	208c <STACK_SIZE+0x8c>
-    2036:	2cff      	cmp	r4, #255	; 0xff
-    2038:	d0b8      	beq.n	1fac <__aeabi_fsub+0x8c>
-    203a:	2080      	movs	r0, #128	; 0x80
-    203c:	04c0      	lsls	r0, r0, #19
-    203e:	4306      	orrs	r6, r0
-    2040:	291b      	cmp	r1, #27
-    2042:	dd00      	ble.n	2046 <STACK_SIZE+0x46>
-    2044:	e0af      	b.n	21a6 <STACK_SIZE+0x1a6>
-    2046:	0030      	movs	r0, r6
-    2048:	2720      	movs	r7, #32
-    204a:	40c8      	lsrs	r0, r1
-    204c:	1a79      	subs	r1, r7, r1
-    204e:	408e      	lsls	r6, r1
-    2050:	1e71      	subs	r1, r6, #1
-    2052:	418e      	sbcs	r6, r1
-    2054:	4306      	orrs	r6, r0
-    2056:	199b      	adds	r3, r3, r6
-    2058:	0159      	lsls	r1, r3, #5
-    205a:	d5d6      	bpl.n	200a <STACK_SIZE+0xa>
-    205c:	3401      	adds	r4, #1
-    205e:	2cff      	cmp	r4, #255	; 0xff
-    2060:	d100      	bne.n	2064 <STACK_SIZE+0x64>
-    2062:	e085      	b.n	2170 <STACK_SIZE+0x170>
-    2064:	2201      	movs	r2, #1
-    2066:	497a      	ldr	r1, [pc, #488]	; (2250 <STACK_SIZE+0x250>)
-    2068:	401a      	ands	r2, r3
-    206a:	085b      	lsrs	r3, r3, #1
-    206c:	400b      	ands	r3, r1
-    206e:	4313      	orrs	r3, r2
-    2070:	e79c      	b.n	1fac <__aeabi_fsub+0x8c>
-    2072:	2e00      	cmp	r6, #0
-    2074:	d000      	beq.n	2078 <STACK_SIZE+0x78>
-    2076:	e770      	b.n	1f5a <__aeabi_fsub+0x3a>
-    2078:	e76b      	b.n	1f52 <__aeabi_fsub+0x32>
-    207a:	1e3b      	subs	r3, r7, #0
-    207c:	d1c5      	bne.n	200a <STACK_SIZE+0xa>
-    207e:	2200      	movs	r2, #0
-    2080:	027b      	lsls	r3, r7, #9
-    2082:	0a5b      	lsrs	r3, r3, #9
-    2084:	b2e4      	uxtb	r4, r4
-    2086:	e7a3      	b.n	1fd0 <__aeabi_fsub+0xb0>
-    2088:	0014      	movs	r4, r2
-    208a:	e78f      	b.n	1fac <__aeabi_fsub+0x8c>
-    208c:	2e00      	cmp	r6, #0
-    208e:	d04d      	beq.n	212c <STACK_SIZE+0x12c>
-    2090:	1e48      	subs	r0, r1, #1
-    2092:	2800      	cmp	r0, #0
-    2094:	d157      	bne.n	2146 <STACK_SIZE+0x146>
-    2096:	199b      	adds	r3, r3, r6
-    2098:	2401      	movs	r4, #1
-    209a:	015a      	lsls	r2, r3, #5
-    209c:	d5b5      	bpl.n	200a <STACK_SIZE+0xa>
-    209e:	2402      	movs	r4, #2
-    20a0:	e7e0      	b.n	2064 <STACK_SIZE+0x64>
-    20a2:	2a00      	cmp	r2, #0
-    20a4:	d125      	bne.n	20f2 <STACK_SIZE+0xf2>
-    20a6:	1c62      	adds	r2, r4, #1
-    20a8:	b2d2      	uxtb	r2, r2
-    20aa:	2a01      	cmp	r2, #1
-    20ac:	dd72      	ble.n	2194 <STACK_SIZE+0x194>
-    20ae:	1b9f      	subs	r7, r3, r6
-    20b0:	017a      	lsls	r2, r7, #5
-    20b2:	d535      	bpl.n	2120 <STACK_SIZE+0x120>
-    20b4:	1af7      	subs	r7, r6, r3
-    20b6:	000d      	movs	r5, r1
-    20b8:	e764      	b.n	1f84 <__aeabi_fsub+0x64>
-    20ba:	2201      	movs	r2, #1
-    20bc:	2300      	movs	r3, #0
-    20be:	402a      	ands	r2, r5
-    20c0:	e786      	b.n	1fd0 <__aeabi_fsub+0xb0>
-    20c2:	003b      	movs	r3, r7
-    20c4:	4a63      	ldr	r2, [pc, #396]	; (2254 <STACK_SIZE+0x254>)
-    20c6:	1a24      	subs	r4, r4, r0
-    20c8:	4013      	ands	r3, r2
-    20ca:	e76f      	b.n	1fac <__aeabi_fsub+0x8c>
-    20cc:	2900      	cmp	r1, #0
-    20ce:	d16c      	bne.n	21aa <STACK_SIZE+0x1aa>
-    20d0:	1c61      	adds	r1, r4, #1
-    20d2:	b2c8      	uxtb	r0, r1
-    20d4:	2801      	cmp	r0, #1
-    20d6:	dd4e      	ble.n	2176 <STACK_SIZE+0x176>
-    20d8:	29ff      	cmp	r1, #255	; 0xff
-    20da:	d049      	beq.n	2170 <STACK_SIZE+0x170>
-    20dc:	199b      	adds	r3, r3, r6
-    20de:	085b      	lsrs	r3, r3, #1
-    20e0:	000c      	movs	r4, r1
-    20e2:	e763      	b.n	1fac <__aeabi_fsub+0x8c>
-    20e4:	2aff      	cmp	r2, #255	; 0xff
-    20e6:	d041      	beq.n	216c <STACK_SIZE+0x16c>
-    20e8:	000a      	movs	r2, r1
-    20ea:	e781      	b.n	1ff0 <__aeabi_fsub+0xd0>
-    20ec:	2601      	movs	r6, #1
-    20ee:	1b9b      	subs	r3, r3, r6
-    20f0:	e789      	b.n	2006 <STACK_SIZE+0x6>
-    20f2:	2c00      	cmp	r4, #0
-    20f4:	d01c      	beq.n	2130 <STACK_SIZE+0x130>
-    20f6:	28ff      	cmp	r0, #255	; 0xff
-    20f8:	d021      	beq.n	213e <STACK_SIZE+0x13e>
-    20fa:	2480      	movs	r4, #128	; 0x80
-    20fc:	04e4      	lsls	r4, r4, #19
-    20fe:	4252      	negs	r2, r2
-    2100:	4323      	orrs	r3, r4
-    2102:	2a1b      	cmp	r2, #27
-    2104:	dd00      	ble.n	2108 <STACK_SIZE+0x108>
-    2106:	e096      	b.n	2236 <STACK_SIZE+0x236>
-    2108:	001c      	movs	r4, r3
-    210a:	2520      	movs	r5, #32
-    210c:	40d4      	lsrs	r4, r2
-    210e:	1aaa      	subs	r2, r5, r2
-    2110:	4093      	lsls	r3, r2
-    2112:	1e5a      	subs	r2, r3, #1
-    2114:	4193      	sbcs	r3, r2
-    2116:	4323      	orrs	r3, r4
-    2118:	1af3      	subs	r3, r6, r3
-    211a:	0004      	movs	r4, r0
-    211c:	000d      	movs	r5, r1
-    211e:	e72d      	b.n	1f7c <__aeabi_fsub+0x5c>
-    2120:	2f00      	cmp	r7, #0
-    2122:	d000      	beq.n	2126 <STACK_SIZE+0x126>
-    2124:	e72e      	b.n	1f84 <__aeabi_fsub+0x64>
-    2126:	2200      	movs	r2, #0
-    2128:	2400      	movs	r4, #0
-    212a:	e7a9      	b.n	2080 <STACK_SIZE+0x80>
-    212c:	000c      	movs	r4, r1
-    212e:	e73d      	b.n	1fac <__aeabi_fsub+0x8c>
-    2130:	2b00      	cmp	r3, #0
-    2132:	d058      	beq.n	21e6 <STACK_SIZE+0x1e6>
-    2134:	43d2      	mvns	r2, r2
-    2136:	2a00      	cmp	r2, #0
-    2138:	d0ee      	beq.n	2118 <STACK_SIZE+0x118>
-    213a:	28ff      	cmp	r0, #255	; 0xff
-    213c:	d1e1      	bne.n	2102 <STACK_SIZE+0x102>
-    213e:	0033      	movs	r3, r6
-    2140:	24ff      	movs	r4, #255	; 0xff
-    2142:	000d      	movs	r5, r1
-    2144:	e732      	b.n	1fac <__aeabi_fsub+0x8c>
-    2146:	29ff      	cmp	r1, #255	; 0xff
-    2148:	d010      	beq.n	216c <STACK_SIZE+0x16c>
-    214a:	0001      	movs	r1, r0
-    214c:	e778      	b.n	2040 <STACK_SIZE+0x40>
-    214e:	2b00      	cmp	r3, #0
-    2150:	d06e      	beq.n	2230 <STACK_SIZE+0x230>
-    2152:	24ff      	movs	r4, #255	; 0xff
-    2154:	2e00      	cmp	r6, #0
-    2156:	d100      	bne.n	215a <STACK_SIZE+0x15a>
-    2158:	e728      	b.n	1fac <__aeabi_fsub+0x8c>
-    215a:	2280      	movs	r2, #128	; 0x80
-    215c:	4651      	mov	r1, sl
-    215e:	03d2      	lsls	r2, r2, #15
-    2160:	4211      	tst	r1, r2
-    2162:	d003      	beq.n	216c <STACK_SIZE+0x16c>
-    2164:	4661      	mov	r1, ip
-    2166:	4211      	tst	r1, r2
-    2168:	d100      	bne.n	216c <STACK_SIZE+0x16c>
-    216a:	0033      	movs	r3, r6
-    216c:	24ff      	movs	r4, #255	; 0xff
-    216e:	e71d      	b.n	1fac <__aeabi_fsub+0x8c>
-    2170:	24ff      	movs	r4, #255	; 0xff
-    2172:	2300      	movs	r3, #0
-    2174:	e72c      	b.n	1fd0 <__aeabi_fsub+0xb0>
-    2176:	2c00      	cmp	r4, #0
-    2178:	d1e9      	bne.n	214e <STACK_SIZE+0x14e>
-    217a:	2b00      	cmp	r3, #0
-    217c:	d063      	beq.n	2246 <STACK_SIZE+0x246>
-    217e:	2e00      	cmp	r6, #0
-    2180:	d100      	bne.n	2184 <STACK_SIZE+0x184>
-    2182:	e713      	b.n	1fac <__aeabi_fsub+0x8c>
-    2184:	199b      	adds	r3, r3, r6
-    2186:	015a      	lsls	r2, r3, #5
-    2188:	d400      	bmi.n	218c <STACK_SIZE+0x18c>
-    218a:	e73e      	b.n	200a <STACK_SIZE+0xa>
-    218c:	4a31      	ldr	r2, [pc, #196]	; (2254 <STACK_SIZE+0x254>)
-    218e:	000c      	movs	r4, r1
-    2190:	4013      	ands	r3, r2
-    2192:	e70b      	b.n	1fac <__aeabi_fsub+0x8c>
-    2194:	2c00      	cmp	r4, #0
-    2196:	d11e      	bne.n	21d6 <STACK_SIZE+0x1d6>
-    2198:	2b00      	cmp	r3, #0
-    219a:	d12f      	bne.n	21fc <STACK_SIZE+0x1fc>
-    219c:	2e00      	cmp	r6, #0
-    219e:	d04f      	beq.n	2240 <STACK_SIZE+0x240>
-    21a0:	0033      	movs	r3, r6
-    21a2:	000d      	movs	r5, r1
-    21a4:	e702      	b.n	1fac <__aeabi_fsub+0x8c>
-    21a6:	2601      	movs	r6, #1
-    21a8:	e755      	b.n	2056 <STACK_SIZE+0x56>
-    21aa:	2c00      	cmp	r4, #0
-    21ac:	d11f      	bne.n	21ee <STACK_SIZE+0x1ee>
-    21ae:	2b00      	cmp	r3, #0
-    21b0:	d043      	beq.n	223a <STACK_SIZE+0x23a>
-    21b2:	43c9      	mvns	r1, r1
-    21b4:	2900      	cmp	r1, #0
-    21b6:	d00b      	beq.n	21d0 <STACK_SIZE+0x1d0>
-    21b8:	28ff      	cmp	r0, #255	; 0xff
-    21ba:	d039      	beq.n	2230 <STACK_SIZE+0x230>
-    21bc:	291b      	cmp	r1, #27
-    21be:	dc44      	bgt.n	224a <STACK_SIZE+0x24a>
-    21c0:	001c      	movs	r4, r3
-    21c2:	2720      	movs	r7, #32
-    21c4:	40cc      	lsrs	r4, r1
-    21c6:	1a79      	subs	r1, r7, r1
-    21c8:	408b      	lsls	r3, r1
-    21ca:	1e59      	subs	r1, r3, #1
-    21cc:	418b      	sbcs	r3, r1
-    21ce:	4323      	orrs	r3, r4
-    21d0:	199b      	adds	r3, r3, r6
-    21d2:	0004      	movs	r4, r0
-    21d4:	e740      	b.n	2058 <STACK_SIZE+0x58>
-    21d6:	2b00      	cmp	r3, #0
-    21d8:	d11a      	bne.n	2210 <STACK_SIZE+0x210>
-    21da:	2e00      	cmp	r6, #0
-    21dc:	d124      	bne.n	2228 <STACK_SIZE+0x228>
-    21de:	2780      	movs	r7, #128	; 0x80
-    21e0:	2200      	movs	r2, #0
-    21e2:	03ff      	lsls	r7, r7, #15
-    21e4:	e71b      	b.n	201e <STACK_SIZE+0x1e>
-    21e6:	0033      	movs	r3, r6
-    21e8:	0004      	movs	r4, r0
-    21ea:	000d      	movs	r5, r1
-    21ec:	e6de      	b.n	1fac <__aeabi_fsub+0x8c>
-    21ee:	28ff      	cmp	r0, #255	; 0xff
-    21f0:	d01e      	beq.n	2230 <STACK_SIZE+0x230>
-    21f2:	2480      	movs	r4, #128	; 0x80
-    21f4:	04e4      	lsls	r4, r4, #19
-    21f6:	4249      	negs	r1, r1
-    21f8:	4323      	orrs	r3, r4
-    21fa:	e7df      	b.n	21bc <STACK_SIZE+0x1bc>
-    21fc:	2e00      	cmp	r6, #0
-    21fe:	d100      	bne.n	2202 <STACK_SIZE+0x202>
-    2200:	e6d4      	b.n	1fac <__aeabi_fsub+0x8c>
-    2202:	1b9f      	subs	r7, r3, r6
-    2204:	017a      	lsls	r2, r7, #5
-    2206:	d400      	bmi.n	220a <STACK_SIZE+0x20a>
-    2208:	e737      	b.n	207a <STACK_SIZE+0x7a>
-    220a:	1af3      	subs	r3, r6, r3
-    220c:	000d      	movs	r5, r1
-    220e:	e6cd      	b.n	1fac <__aeabi_fsub+0x8c>
-    2210:	24ff      	movs	r4, #255	; 0xff
-    2212:	2e00      	cmp	r6, #0
-    2214:	d100      	bne.n	2218 <STACK_SIZE+0x218>
-    2216:	e6c9      	b.n	1fac <__aeabi_fsub+0x8c>
-    2218:	2280      	movs	r2, #128	; 0x80
-    221a:	4650      	mov	r0, sl
-    221c:	03d2      	lsls	r2, r2, #15
-    221e:	4210      	tst	r0, r2
-    2220:	d0a4      	beq.n	216c <STACK_SIZE+0x16c>
-    2222:	4660      	mov	r0, ip
-    2224:	4210      	tst	r0, r2
-    2226:	d1a1      	bne.n	216c <STACK_SIZE+0x16c>
-    2228:	0033      	movs	r3, r6
-    222a:	000d      	movs	r5, r1
-    222c:	24ff      	movs	r4, #255	; 0xff
-    222e:	e6bd      	b.n	1fac <__aeabi_fsub+0x8c>
-    2230:	0033      	movs	r3, r6
-    2232:	24ff      	movs	r4, #255	; 0xff
-    2234:	e6ba      	b.n	1fac <__aeabi_fsub+0x8c>
-    2236:	2301      	movs	r3, #1
-    2238:	e76e      	b.n	2118 <STACK_SIZE+0x118>
-    223a:	0033      	movs	r3, r6
-    223c:	0004      	movs	r4, r0
-    223e:	e6b5      	b.n	1fac <__aeabi_fsub+0x8c>
-    2240:	2700      	movs	r7, #0
-    2242:	2200      	movs	r2, #0
-    2244:	e71c      	b.n	2080 <STACK_SIZE+0x80>
-    2246:	0033      	movs	r3, r6
-    2248:	e6b0      	b.n	1fac <__aeabi_fsub+0x8c>
-    224a:	2301      	movs	r3, #1
-    224c:	e7c0      	b.n	21d0 <STACK_SIZE+0x1d0>
-    224e:	46c0      	nop			; (mov r8, r8)
-    2250:	7dffffff 	.word	0x7dffffff
-    2254:	fbffffff 	.word	0xfbffffff
-
-00002258 <__aeabi_f2iz>:
-    2258:	0241      	lsls	r1, r0, #9
-    225a:	0043      	lsls	r3, r0, #1
-    225c:	0fc2      	lsrs	r2, r0, #31
-    225e:	0a49      	lsrs	r1, r1, #9
-    2260:	0e1b      	lsrs	r3, r3, #24
-    2262:	2000      	movs	r0, #0
-    2264:	2b7e      	cmp	r3, #126	; 0x7e
-    2266:	dd0d      	ble.n	2284 <__aeabi_f2iz+0x2c>
-    2268:	2b9d      	cmp	r3, #157	; 0x9d
-    226a:	dc0c      	bgt.n	2286 <__aeabi_f2iz+0x2e>
-    226c:	2080      	movs	r0, #128	; 0x80
-    226e:	0400      	lsls	r0, r0, #16
-    2270:	4301      	orrs	r1, r0
-    2272:	2b95      	cmp	r3, #149	; 0x95
-    2274:	dc0a      	bgt.n	228c <__aeabi_f2iz+0x34>
-    2276:	2096      	movs	r0, #150	; 0x96
-    2278:	1ac3      	subs	r3, r0, r3
-    227a:	40d9      	lsrs	r1, r3
-    227c:	4248      	negs	r0, r1
-    227e:	2a00      	cmp	r2, #0
-    2280:	d100      	bne.n	2284 <__aeabi_f2iz+0x2c>
-    2282:	0008      	movs	r0, r1
-    2284:	4770      	bx	lr
-    2286:	4b03      	ldr	r3, [pc, #12]	; (2294 <__aeabi_f2iz+0x3c>)
-    2288:	18d0      	adds	r0, r2, r3
-    228a:	e7fb      	b.n	2284 <__aeabi_f2iz+0x2c>
-    228c:	3b96      	subs	r3, #150	; 0x96
-    228e:	4099      	lsls	r1, r3
-    2290:	e7f4      	b.n	227c <__aeabi_f2iz+0x24>
-    2292:	46c0      	nop			; (mov r8, r8)
-    2294:	7fffffff 	.word	0x7fffffff
-
-00002298 <__aeabi_i2f>:
-    2298:	b570      	push	{r4, r5, r6, lr}
-    229a:	2800      	cmp	r0, #0
-    229c:	d030      	beq.n	2300 <__aeabi_i2f+0x68>
-    229e:	17c3      	asrs	r3, r0, #31
-    22a0:	18c4      	adds	r4, r0, r3
-    22a2:	405c      	eors	r4, r3
-    22a4:	0fc5      	lsrs	r5, r0, #31
-    22a6:	0020      	movs	r0, r4
-    22a8:	f000 f88c 	bl	23c4 <__clzsi2>
-    22ac:	239e      	movs	r3, #158	; 0x9e
-    22ae:	1a1b      	subs	r3, r3, r0
-    22b0:	2b96      	cmp	r3, #150	; 0x96
-    22b2:	dc0d      	bgt.n	22d0 <__aeabi_i2f+0x38>
-    22b4:	2296      	movs	r2, #150	; 0x96
-    22b6:	1ad2      	subs	r2, r2, r3
-    22b8:	4094      	lsls	r4, r2
-    22ba:	002a      	movs	r2, r5
-    22bc:	0264      	lsls	r4, r4, #9
-    22be:	0a64      	lsrs	r4, r4, #9
-    22c0:	b2db      	uxtb	r3, r3
-    22c2:	0264      	lsls	r4, r4, #9
-    22c4:	05db      	lsls	r3, r3, #23
-    22c6:	0a60      	lsrs	r0, r4, #9
-    22c8:	07d2      	lsls	r2, r2, #31
-    22ca:	4318      	orrs	r0, r3
-    22cc:	4310      	orrs	r0, r2
-    22ce:	bd70      	pop	{r4, r5, r6, pc}
-    22d0:	2b99      	cmp	r3, #153	; 0x99
-    22d2:	dc19      	bgt.n	2308 <__aeabi_i2f+0x70>
-    22d4:	2299      	movs	r2, #153	; 0x99
-    22d6:	1ad2      	subs	r2, r2, r3
-    22d8:	2a00      	cmp	r2, #0
-    22da:	dd29      	ble.n	2330 <__aeabi_i2f+0x98>
-    22dc:	4094      	lsls	r4, r2
-    22de:	0022      	movs	r2, r4
-    22e0:	4c14      	ldr	r4, [pc, #80]	; (2334 <__aeabi_i2f+0x9c>)
-    22e2:	4014      	ands	r4, r2
-    22e4:	0751      	lsls	r1, r2, #29
-    22e6:	d004      	beq.n	22f2 <__aeabi_i2f+0x5a>
-    22e8:	210f      	movs	r1, #15
-    22ea:	400a      	ands	r2, r1
-    22ec:	2a04      	cmp	r2, #4
-    22ee:	d000      	beq.n	22f2 <__aeabi_i2f+0x5a>
-    22f0:	3404      	adds	r4, #4
-    22f2:	0162      	lsls	r2, r4, #5
-    22f4:	d413      	bmi.n	231e <__aeabi_i2f+0x86>
-    22f6:	01a4      	lsls	r4, r4, #6
-    22f8:	0a64      	lsrs	r4, r4, #9
-    22fa:	b2db      	uxtb	r3, r3
-    22fc:	002a      	movs	r2, r5
-    22fe:	e7e0      	b.n	22c2 <__aeabi_i2f+0x2a>
-    2300:	2200      	movs	r2, #0
-    2302:	2300      	movs	r3, #0
-    2304:	2400      	movs	r4, #0
-    2306:	e7dc      	b.n	22c2 <__aeabi_i2f+0x2a>
-    2308:	2205      	movs	r2, #5
-    230a:	0021      	movs	r1, r4
-    230c:	1a12      	subs	r2, r2, r0
-    230e:	40d1      	lsrs	r1, r2
-    2310:	22b9      	movs	r2, #185	; 0xb9
-    2312:	1ad2      	subs	r2, r2, r3
-    2314:	4094      	lsls	r4, r2
-    2316:	1e62      	subs	r2, r4, #1
-    2318:	4194      	sbcs	r4, r2
-    231a:	430c      	orrs	r4, r1
-    231c:	e7da      	b.n	22d4 <__aeabi_i2f+0x3c>
-    231e:	4b05      	ldr	r3, [pc, #20]	; (2334 <__aeabi_i2f+0x9c>)
-    2320:	002a      	movs	r2, r5
-    2322:	401c      	ands	r4, r3
-    2324:	239f      	movs	r3, #159	; 0x9f
-    2326:	01a4      	lsls	r4, r4, #6
-    2328:	1a1b      	subs	r3, r3, r0
-    232a:	0a64      	lsrs	r4, r4, #9
-    232c:	b2db      	uxtb	r3, r3
-    232e:	e7c8      	b.n	22c2 <__aeabi_i2f+0x2a>
-    2330:	0022      	movs	r2, r4
-    2332:	e7d5      	b.n	22e0 <__aeabi_i2f+0x48>
-    2334:	fbffffff 	.word	0xfbffffff
-
-00002338 <__aeabi_ui2f>:
-    2338:	b510      	push	{r4, lr}
-    233a:	1e04      	subs	r4, r0, #0
-    233c:	d027      	beq.n	238e <__aeabi_ui2f+0x56>
-    233e:	f000 f841 	bl	23c4 <__clzsi2>
-    2342:	239e      	movs	r3, #158	; 0x9e
-    2344:	1a1b      	subs	r3, r3, r0
-    2346:	2b96      	cmp	r3, #150	; 0x96
-    2348:	dc0a      	bgt.n	2360 <__aeabi_ui2f+0x28>
-    234a:	2296      	movs	r2, #150	; 0x96
-    234c:	1ad2      	subs	r2, r2, r3
-    234e:	4094      	lsls	r4, r2
-    2350:	0264      	lsls	r4, r4, #9
-    2352:	0a64      	lsrs	r4, r4, #9
-    2354:	b2db      	uxtb	r3, r3
-    2356:	0264      	lsls	r4, r4, #9
-    2358:	05db      	lsls	r3, r3, #23
-    235a:	0a60      	lsrs	r0, r4, #9
-    235c:	4318      	orrs	r0, r3
-    235e:	bd10      	pop	{r4, pc}
-    2360:	2b99      	cmp	r3, #153	; 0x99
-    2362:	dc17      	bgt.n	2394 <__aeabi_ui2f+0x5c>
-    2364:	2299      	movs	r2, #153	; 0x99
-    2366:	1ad2      	subs	r2, r2, r3
-    2368:	2a00      	cmp	r2, #0
-    236a:	dd27      	ble.n	23bc <__aeabi_ui2f+0x84>
-    236c:	4094      	lsls	r4, r2
-    236e:	0022      	movs	r2, r4
-    2370:	4c13      	ldr	r4, [pc, #76]	; (23c0 <__aeabi_ui2f+0x88>)
-    2372:	4014      	ands	r4, r2
-    2374:	0751      	lsls	r1, r2, #29
-    2376:	d004      	beq.n	2382 <__aeabi_ui2f+0x4a>
-    2378:	210f      	movs	r1, #15
-    237a:	400a      	ands	r2, r1
-    237c:	2a04      	cmp	r2, #4
-    237e:	d000      	beq.n	2382 <__aeabi_ui2f+0x4a>
-    2380:	3404      	adds	r4, #4
-    2382:	0162      	lsls	r2, r4, #5
-    2384:	d412      	bmi.n	23ac <__aeabi_ui2f+0x74>
-    2386:	01a4      	lsls	r4, r4, #6
-    2388:	0a64      	lsrs	r4, r4, #9
-    238a:	b2db      	uxtb	r3, r3
-    238c:	e7e3      	b.n	2356 <__aeabi_ui2f+0x1e>
-    238e:	2300      	movs	r3, #0
-    2390:	2400      	movs	r4, #0
-    2392:	e7e0      	b.n	2356 <__aeabi_ui2f+0x1e>
-    2394:	22b9      	movs	r2, #185	; 0xb9
-    2396:	0021      	movs	r1, r4
-    2398:	1ad2      	subs	r2, r2, r3
-    239a:	4091      	lsls	r1, r2
-    239c:	000a      	movs	r2, r1
-    239e:	1e51      	subs	r1, r2, #1
-    23a0:	418a      	sbcs	r2, r1
-    23a2:	2105      	movs	r1, #5
-    23a4:	1a09      	subs	r1, r1, r0
-    23a6:	40cc      	lsrs	r4, r1
-    23a8:	4314      	orrs	r4, r2
-    23aa:	e7db      	b.n	2364 <__aeabi_ui2f+0x2c>
-    23ac:	4b04      	ldr	r3, [pc, #16]	; (23c0 <__aeabi_ui2f+0x88>)
-    23ae:	401c      	ands	r4, r3
-    23b0:	239f      	movs	r3, #159	; 0x9f
-    23b2:	01a4      	lsls	r4, r4, #6
-    23b4:	1a1b      	subs	r3, r3, r0
-    23b6:	0a64      	lsrs	r4, r4, #9
-    23b8:	b2db      	uxtb	r3, r3
-    23ba:	e7cc      	b.n	2356 <__aeabi_ui2f+0x1e>
-    23bc:	0022      	movs	r2, r4
-    23be:	e7d7      	b.n	2370 <__aeabi_ui2f+0x38>
-    23c0:	fbffffff 	.word	0xfbffffff
-
-000023c4 <__clzsi2>:
-    23c4:	211c      	movs	r1, #28
-    23c6:	2301      	movs	r3, #1
-    23c8:	041b      	lsls	r3, r3, #16
-    23ca:	4298      	cmp	r0, r3
-    23cc:	d301      	bcc.n	23d2 <__clzsi2+0xe>
-    23ce:	0c00      	lsrs	r0, r0, #16
-    23d0:	3910      	subs	r1, #16
-    23d2:	0a1b      	lsrs	r3, r3, #8
-    23d4:	4298      	cmp	r0, r3
-    23d6:	d301      	bcc.n	23dc <__clzsi2+0x18>
-    23d8:	0a00      	lsrs	r0, r0, #8
-    23da:	3908      	subs	r1, #8
-    23dc:	091b      	lsrs	r3, r3, #4
-    23de:	4298      	cmp	r0, r3
-    23e0:	d301      	bcc.n	23e6 <__clzsi2+0x22>
-    23e2:	0900      	lsrs	r0, r0, #4
-    23e4:	3904      	subs	r1, #4
-    23e6:	a202      	add	r2, pc, #8	; (adr r2, 23f0 <__clzsi2+0x2c>)
-    23e8:	5c10      	ldrb	r0, [r2, r0]
-    23ea:	1840      	adds	r0, r0, r1
-    23ec:	4770      	bx	lr
-    23ee:	46c0      	nop			; (mov r8, r8)
-    23f0:	02020304 	.word	0x02020304
-    23f4:	01010101 	.word	0x01010101
-	...
-
-00002400 <__libc_init_array>:
-    2400:	b570      	push	{r4, r5, r6, lr}
-    2402:	2600      	movs	r6, #0
-    2404:	4d0c      	ldr	r5, [pc, #48]	; (2438 <__libc_init_array+0x38>)
-    2406:	4c0d      	ldr	r4, [pc, #52]	; (243c <__libc_init_array+0x3c>)
-    2408:	1b64      	subs	r4, r4, r5
-    240a:	10a4      	asrs	r4, r4, #2
-    240c:	42a6      	cmp	r6, r4
-    240e:	d109      	bne.n	2424 <__libc_init_array+0x24>
-    2410:	2600      	movs	r6, #0
-    2412:	f001 f959 	bl	36c8 <_init>
-    2416:	4d0a      	ldr	r5, [pc, #40]	; (2440 <__libc_init_array+0x40>)
-    2418:	4c0a      	ldr	r4, [pc, #40]	; (2444 <__libc_init_array+0x44>)
-    241a:	1b64      	subs	r4, r4, r5
-    241c:	10a4      	asrs	r4, r4, #2
-    241e:	42a6      	cmp	r6, r4
-    2420:	d105      	bne.n	242e <__libc_init_array+0x2e>
-    2422:	bd70      	pop	{r4, r5, r6, pc}
-    2424:	00b3      	lsls	r3, r6, #2
-    2426:	58eb      	ldr	r3, [r5, r3]
-    2428:	4798      	blx	r3
-    242a:	3601      	adds	r6, #1
-    242c:	e7ee      	b.n	240c <__libc_init_array+0xc>
-    242e:	00b3      	lsls	r3, r6, #2
-    2430:	58eb      	ldr	r3, [r5, r3]
-    2432:	4798      	blx	r3
-    2434:	3601      	adds	r6, #1
-    2436:	e7f2      	b.n	241e <__libc_init_array+0x1e>
-    2438:	000036d4 	.word	0x000036d4
-    243c:	000036d4 	.word	0x000036d4
-    2440:	000036d4 	.word	0x000036d4
-    2444:	000036d8 	.word	0x000036d8
-
-00002448 <memcpy>:
-    2448:	2300      	movs	r3, #0
-    244a:	b510      	push	{r4, lr}
-    244c:	429a      	cmp	r2, r3
-    244e:	d100      	bne.n	2452 <memcpy+0xa>
-    2450:	bd10      	pop	{r4, pc}
-    2452:	5ccc      	ldrb	r4, [r1, r3]
-    2454:	54c4      	strb	r4, [r0, r3]
-    2456:	3301      	adds	r3, #1
-    2458:	e7f8      	b.n	244c <memcpy+0x4>
-
-0000245a <memset>:
-    245a:	0003      	movs	r3, r0
-    245c:	1882      	adds	r2, r0, r2
-    245e:	4293      	cmp	r3, r2
-    2460:	d100      	bne.n	2464 <memset+0xa>
-    2462:	4770      	bx	lr
-    2464:	7019      	strb	r1, [r3, #0]
-    2466:	3301      	adds	r3, #1
-    2468:	e7f9      	b.n	245e <memset+0x4>
-	...
-
-0000246c <iprintf>:
-    246c:	b40f      	push	{r0, r1, r2, r3}
-    246e:	4b0b      	ldr	r3, [pc, #44]	; (249c <iprintf+0x30>)
-    2470:	b513      	push	{r0, r1, r4, lr}
-    2472:	681c      	ldr	r4, [r3, #0]
-    2474:	2c00      	cmp	r4, #0
-    2476:	d005      	beq.n	2484 <iprintf+0x18>
-    2478:	69a3      	ldr	r3, [r4, #24]
-    247a:	2b00      	cmp	r3, #0
-    247c:	d102      	bne.n	2484 <iprintf+0x18>
-    247e:	0020      	movs	r0, r4
-    2480:	f000 faf2 	bl	2a68 <__sinit>
-    2484:	ab05      	add	r3, sp, #20
-    2486:	9a04      	ldr	r2, [sp, #16]
-    2488:	68a1      	ldr	r1, [r4, #8]
-    248a:	0020      	movs	r0, r4
-    248c:	9301      	str	r3, [sp, #4]
-    248e:	f000 fcc7 	bl	2e20 <_vfiprintf_r>
-    2492:	bc16      	pop	{r1, r2, r4}
-    2494:	bc08      	pop	{r3}
-    2496:	b004      	add	sp, #16
-    2498:	4718      	bx	r3
-    249a:	46c0      	nop			; (mov r8, r8)
-    249c:	20000018 	.word	0x20000018
-
-000024a0 <_puts_r>:
-    24a0:	b570      	push	{r4, r5, r6, lr}
-    24a2:	0005      	movs	r5, r0
-    24a4:	000e      	movs	r6, r1
-    24a6:	2800      	cmp	r0, #0
-    24a8:	d004      	beq.n	24b4 <_puts_r+0x14>
-    24aa:	6983      	ldr	r3, [r0, #24]
-    24ac:	2b00      	cmp	r3, #0
-    24ae:	d101      	bne.n	24b4 <_puts_r+0x14>
-    24b0:	f000 fada 	bl	2a68 <__sinit>
-    24b4:	69ab      	ldr	r3, [r5, #24]
-    24b6:	68ac      	ldr	r4, [r5, #8]
-    24b8:	2b00      	cmp	r3, #0
-    24ba:	d102      	bne.n	24c2 <_puts_r+0x22>
-    24bc:	0028      	movs	r0, r5
-    24be:	f000 fad3 	bl	2a68 <__sinit>
-    24c2:	4b24      	ldr	r3, [pc, #144]	; (2554 <_puts_r+0xb4>)
-    24c4:	429c      	cmp	r4, r3
-    24c6:	d10f      	bne.n	24e8 <_puts_r+0x48>
-    24c8:	686c      	ldr	r4, [r5, #4]
-    24ca:	89a3      	ldrh	r3, [r4, #12]
-    24cc:	071b      	lsls	r3, r3, #28
-    24ce:	d502      	bpl.n	24d6 <_puts_r+0x36>
-    24d0:	6923      	ldr	r3, [r4, #16]
-    24d2:	2b00      	cmp	r3, #0
-    24d4:	d120      	bne.n	2518 <_puts_r+0x78>
-    24d6:	0021      	movs	r1, r4
-    24d8:	0028      	movs	r0, r5
-    24da:	f000 f957 	bl	278c <__swsetup_r>
-    24de:	2800      	cmp	r0, #0
-    24e0:	d01a      	beq.n	2518 <_puts_r+0x78>
-    24e2:	2001      	movs	r0, #1
-    24e4:	4240      	negs	r0, r0
-    24e6:	bd70      	pop	{r4, r5, r6, pc}
-    24e8:	4b1b      	ldr	r3, [pc, #108]	; (2558 <_puts_r+0xb8>)
-    24ea:	429c      	cmp	r4, r3
-    24ec:	d101      	bne.n	24f2 <_puts_r+0x52>
-    24ee:	68ac      	ldr	r4, [r5, #8]
-    24f0:	e7eb      	b.n	24ca <_puts_r+0x2a>
-    24f2:	4b1a      	ldr	r3, [pc, #104]	; (255c <_puts_r+0xbc>)
-    24f4:	429c      	cmp	r4, r3
-    24f6:	d1e8      	bne.n	24ca <_puts_r+0x2a>
-    24f8:	68ec      	ldr	r4, [r5, #12]
-    24fa:	e7e6      	b.n	24ca <_puts_r+0x2a>
-    24fc:	3b01      	subs	r3, #1
-    24fe:	3601      	adds	r6, #1
-    2500:	60a3      	str	r3, [r4, #8]
-    2502:	2b00      	cmp	r3, #0
-    2504:	da04      	bge.n	2510 <_puts_r+0x70>
-    2506:	69a2      	ldr	r2, [r4, #24]
-    2508:	4293      	cmp	r3, r2
-    250a:	db16      	blt.n	253a <_puts_r+0x9a>
-    250c:	290a      	cmp	r1, #10
-    250e:	d014      	beq.n	253a <_puts_r+0x9a>
-    2510:	6823      	ldr	r3, [r4, #0]
-    2512:	1c5a      	adds	r2, r3, #1
-    2514:	6022      	str	r2, [r4, #0]
-    2516:	7019      	strb	r1, [r3, #0]
-    2518:	7831      	ldrb	r1, [r6, #0]
-    251a:	68a3      	ldr	r3, [r4, #8]
-    251c:	2900      	cmp	r1, #0
-    251e:	d1ed      	bne.n	24fc <_puts_r+0x5c>
-    2520:	3b01      	subs	r3, #1
-    2522:	60a3      	str	r3, [r4, #8]
-    2524:	2b00      	cmp	r3, #0
-    2526:	da0f      	bge.n	2548 <_puts_r+0xa8>
-    2528:	0022      	movs	r2, r4
-    252a:	310a      	adds	r1, #10
-    252c:	0028      	movs	r0, r5
-    252e:	f000 f8d7 	bl	26e0 <__swbuf_r>
-    2532:	1c43      	adds	r3, r0, #1
-    2534:	d0d5      	beq.n	24e2 <_puts_r+0x42>
-    2536:	200a      	movs	r0, #10
-    2538:	e7d5      	b.n	24e6 <_puts_r+0x46>
-    253a:	0022      	movs	r2, r4
-    253c:	0028      	movs	r0, r5
-    253e:	f000 f8cf 	bl	26e0 <__swbuf_r>
-    2542:	1c43      	adds	r3, r0, #1
-    2544:	d1e8      	bne.n	2518 <_puts_r+0x78>
-    2546:	e7cc      	b.n	24e2 <_puts_r+0x42>
-    2548:	200a      	movs	r0, #10
-    254a:	6823      	ldr	r3, [r4, #0]
-    254c:	1c5a      	adds	r2, r3, #1
-    254e:	6022      	str	r2, [r4, #0]
-    2550:	7018      	strb	r0, [r3, #0]
-    2552:	e7c8      	b.n	24e6 <_puts_r+0x46>
-    2554:	00003654 	.word	0x00003654
-    2558:	00003674 	.word	0x00003674
-    255c:	00003634 	.word	0x00003634
-
-00002560 <puts>:
-    2560:	b510      	push	{r4, lr}
-    2562:	4b03      	ldr	r3, [pc, #12]	; (2570 <puts+0x10>)
-    2564:	0001      	movs	r1, r0
-    2566:	6818      	ldr	r0, [r3, #0]
-    2568:	f7ff ff9a 	bl	24a0 <_puts_r>
-    256c:	bd10      	pop	{r4, pc}
-    256e:	46c0      	nop			; (mov r8, r8)
-    2570:	20000018 	.word	0x20000018
-
-00002574 <setbuf>:
-    2574:	424a      	negs	r2, r1
-    2576:	414a      	adcs	r2, r1
-    2578:	2380      	movs	r3, #128	; 0x80
-    257a:	b510      	push	{r4, lr}
-    257c:	0052      	lsls	r2, r2, #1
-    257e:	00db      	lsls	r3, r3, #3
-    2580:	f000 f802 	bl	2588 <setvbuf>
-    2584:	bd10      	pop	{r4, pc}
-	...
-
-00002588 <setvbuf>:
-    2588:	b5f0      	push	{r4, r5, r6, r7, lr}
-    258a:	001d      	movs	r5, r3
-    258c:	4b4f      	ldr	r3, [pc, #316]	; (26cc <setvbuf+0x144>)
-    258e:	b085      	sub	sp, #20
-    2590:	681e      	ldr	r6, [r3, #0]
-    2592:	0004      	movs	r4, r0
-    2594:	000f      	movs	r7, r1
-    2596:	9200      	str	r2, [sp, #0]
-    2598:	2e00      	cmp	r6, #0
-    259a:	d005      	beq.n	25a8 <setvbuf+0x20>
-    259c:	69b3      	ldr	r3, [r6, #24]
-    259e:	2b00      	cmp	r3, #0
-    25a0:	d102      	bne.n	25a8 <setvbuf+0x20>
-    25a2:	0030      	movs	r0, r6
-    25a4:	f000 fa60 	bl	2a68 <__sinit>
-    25a8:	4b49      	ldr	r3, [pc, #292]	; (26d0 <setvbuf+0x148>)
-    25aa:	429c      	cmp	r4, r3
-    25ac:	d150      	bne.n	2650 <setvbuf+0xc8>
-    25ae:	6874      	ldr	r4, [r6, #4]
-    25b0:	9b00      	ldr	r3, [sp, #0]
-    25b2:	2b02      	cmp	r3, #2
-    25b4:	d005      	beq.n	25c2 <setvbuf+0x3a>
-    25b6:	2b01      	cmp	r3, #1
-    25b8:	d900      	bls.n	25bc <setvbuf+0x34>
-    25ba:	e084      	b.n	26c6 <setvbuf+0x13e>
-    25bc:	2d00      	cmp	r5, #0
-    25be:	da00      	bge.n	25c2 <setvbuf+0x3a>
-    25c0:	e081      	b.n	26c6 <setvbuf+0x13e>
-    25c2:	0021      	movs	r1, r4
-    25c4:	0030      	movs	r0, r6
-    25c6:	f000 f9e1 	bl	298c <_fflush_r>
-    25ca:	6b61      	ldr	r1, [r4, #52]	; 0x34
-    25cc:	2900      	cmp	r1, #0
-    25ce:	d008      	beq.n	25e2 <setvbuf+0x5a>
-    25d0:	0023      	movs	r3, r4
-    25d2:	3344      	adds	r3, #68	; 0x44
-    25d4:	4299      	cmp	r1, r3
-    25d6:	d002      	beq.n	25de <setvbuf+0x56>
-    25d8:	0030      	movs	r0, r6
-    25da:	f000 fb51 	bl	2c80 <_free_r>
-    25de:	2300      	movs	r3, #0
-    25e0:	6363      	str	r3, [r4, #52]	; 0x34
-    25e2:	2300      	movs	r3, #0
-    25e4:	61a3      	str	r3, [r4, #24]
-    25e6:	6063      	str	r3, [r4, #4]
-    25e8:	89a3      	ldrh	r3, [r4, #12]
-    25ea:	061b      	lsls	r3, r3, #24
-    25ec:	d503      	bpl.n	25f6 <setvbuf+0x6e>
-    25ee:	6921      	ldr	r1, [r4, #16]
-    25f0:	0030      	movs	r0, r6
-    25f2:	f000 fb45 	bl	2c80 <_free_r>
-    25f6:	89a3      	ldrh	r3, [r4, #12]
-    25f8:	4a36      	ldr	r2, [pc, #216]	; (26d4 <setvbuf+0x14c>)
-    25fa:	4013      	ands	r3, r2
-    25fc:	81a3      	strh	r3, [r4, #12]
-    25fe:	9b00      	ldr	r3, [sp, #0]
-    2600:	2b02      	cmp	r3, #2
-    2602:	d05a      	beq.n	26ba <setvbuf+0x132>
-    2604:	ab03      	add	r3, sp, #12
-    2606:	aa02      	add	r2, sp, #8
-    2608:	0021      	movs	r1, r4
-    260a:	0030      	movs	r0, r6
-    260c:	f000 fac2 	bl	2b94 <__swhatbuf_r>
-    2610:	89a3      	ldrh	r3, [r4, #12]
-    2612:	4318      	orrs	r0, r3
-    2614:	81a0      	strh	r0, [r4, #12]
-    2616:	2d00      	cmp	r5, #0
-    2618:	d124      	bne.n	2664 <setvbuf+0xdc>
-    261a:	9d02      	ldr	r5, [sp, #8]
-    261c:	0028      	movs	r0, r5
-    261e:	f000 fb25 	bl	2c6c <malloc>
-    2622:	9501      	str	r5, [sp, #4]
-    2624:	1e07      	subs	r7, r0, #0
-    2626:	d142      	bne.n	26ae <setvbuf+0x126>
-    2628:	9b02      	ldr	r3, [sp, #8]
-    262a:	9301      	str	r3, [sp, #4]
-    262c:	42ab      	cmp	r3, r5
-    262e:	d139      	bne.n	26a4 <setvbuf+0x11c>
-    2630:	2001      	movs	r0, #1
-    2632:	4240      	negs	r0, r0
-    2634:	2302      	movs	r3, #2
-    2636:	89a2      	ldrh	r2, [r4, #12]
-    2638:	4313      	orrs	r3, r2
-    263a:	81a3      	strh	r3, [r4, #12]
-    263c:	2300      	movs	r3, #0
-    263e:	60a3      	str	r3, [r4, #8]
-    2640:	0023      	movs	r3, r4
-    2642:	3347      	adds	r3, #71	; 0x47
-    2644:	6023      	str	r3, [r4, #0]
-    2646:	6123      	str	r3, [r4, #16]
-    2648:	2301      	movs	r3, #1
-    264a:	6163      	str	r3, [r4, #20]
-    264c:	b005      	add	sp, #20
-    264e:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    2650:	4b21      	ldr	r3, [pc, #132]	; (26d8 <setvbuf+0x150>)
-    2652:	429c      	cmp	r4, r3
-    2654:	d101      	bne.n	265a <setvbuf+0xd2>
-    2656:	68b4      	ldr	r4, [r6, #8]
-    2658:	e7aa      	b.n	25b0 <setvbuf+0x28>
-    265a:	4b20      	ldr	r3, [pc, #128]	; (26dc <setvbuf+0x154>)
-    265c:	429c      	cmp	r4, r3
-    265e:	d1a7      	bne.n	25b0 <setvbuf+0x28>
-    2660:	68f4      	ldr	r4, [r6, #12]
-    2662:	e7a5      	b.n	25b0 <setvbuf+0x28>
-    2664:	2f00      	cmp	r7, #0
-    2666:	d0d9      	beq.n	261c <setvbuf+0x94>
-    2668:	69b3      	ldr	r3, [r6, #24]
-    266a:	2b00      	cmp	r3, #0
-    266c:	d102      	bne.n	2674 <setvbuf+0xec>
-    266e:	0030      	movs	r0, r6
-    2670:	f000 f9fa 	bl	2a68 <__sinit>
-    2674:	9b00      	ldr	r3, [sp, #0]
-    2676:	2b01      	cmp	r3, #1
-    2678:	d103      	bne.n	2682 <setvbuf+0xfa>
-    267a:	89a3      	ldrh	r3, [r4, #12]
-    267c:	9a00      	ldr	r2, [sp, #0]
-    267e:	431a      	orrs	r2, r3
-    2680:	81a2      	strh	r2, [r4, #12]
-    2682:	2008      	movs	r0, #8
-    2684:	89a3      	ldrh	r3, [r4, #12]
-    2686:	6027      	str	r7, [r4, #0]
-    2688:	6127      	str	r7, [r4, #16]
-    268a:	6165      	str	r5, [r4, #20]
-    268c:	4018      	ands	r0, r3
-    268e:	d018      	beq.n	26c2 <setvbuf+0x13a>
-    2690:	2001      	movs	r0, #1
-    2692:	4018      	ands	r0, r3
-    2694:	2300      	movs	r3, #0
-    2696:	4298      	cmp	r0, r3
-    2698:	d011      	beq.n	26be <setvbuf+0x136>
-    269a:	426d      	negs	r5, r5
-    269c:	60a3      	str	r3, [r4, #8]
-    269e:	61a5      	str	r5, [r4, #24]
-    26a0:	0018      	movs	r0, r3
-    26a2:	e7d3      	b.n	264c <setvbuf+0xc4>
-    26a4:	9801      	ldr	r0, [sp, #4]
-    26a6:	f000 fae1 	bl	2c6c <malloc>
-    26aa:	1e07      	subs	r7, r0, #0
-    26ac:	d0c0      	beq.n	2630 <setvbuf+0xa8>
-    26ae:	2380      	movs	r3, #128	; 0x80
-    26b0:	89a2      	ldrh	r2, [r4, #12]
-    26b2:	9d01      	ldr	r5, [sp, #4]
-    26b4:	4313      	orrs	r3, r2
-    26b6:	81a3      	strh	r3, [r4, #12]
-    26b8:	e7d6      	b.n	2668 <setvbuf+0xe0>
-    26ba:	2000      	movs	r0, #0
-    26bc:	e7ba      	b.n	2634 <setvbuf+0xac>
-    26be:	60a5      	str	r5, [r4, #8]
-    26c0:	e7c4      	b.n	264c <setvbuf+0xc4>
-    26c2:	60a0      	str	r0, [r4, #8]
-    26c4:	e7c2      	b.n	264c <setvbuf+0xc4>
-    26c6:	2001      	movs	r0, #1
-    26c8:	4240      	negs	r0, r0
-    26ca:	e7bf      	b.n	264c <setvbuf+0xc4>
-    26cc:	20000018 	.word	0x20000018
-    26d0:	00003654 	.word	0x00003654
-    26d4:	fffff35c 	.word	0xfffff35c
-    26d8:	00003674 	.word	0x00003674
-    26dc:	00003634 	.word	0x00003634
-
-000026e0 <__swbuf_r>:
-    26e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    26e2:	0005      	movs	r5, r0
-    26e4:	000e      	movs	r6, r1
-    26e6:	0014      	movs	r4, r2
-    26e8:	2800      	cmp	r0, #0
-    26ea:	d004      	beq.n	26f6 <__swbuf_r+0x16>
-    26ec:	6983      	ldr	r3, [r0, #24]
-    26ee:	2b00      	cmp	r3, #0
-    26f0:	d101      	bne.n	26f6 <__swbuf_r+0x16>
-    26f2:	f000 f9b9 	bl	2a68 <__sinit>
-    26f6:	4b22      	ldr	r3, [pc, #136]	; (2780 <__swbuf_r+0xa0>)
-    26f8:	429c      	cmp	r4, r3
-    26fa:	d12d      	bne.n	2758 <__swbuf_r+0x78>
-    26fc:	686c      	ldr	r4, [r5, #4]
-    26fe:	69a3      	ldr	r3, [r4, #24]
-    2700:	60a3      	str	r3, [r4, #8]
-    2702:	89a3      	ldrh	r3, [r4, #12]
-    2704:	071b      	lsls	r3, r3, #28
-    2706:	d531      	bpl.n	276c <__swbuf_r+0x8c>
-    2708:	6923      	ldr	r3, [r4, #16]
-    270a:	2b00      	cmp	r3, #0
-    270c:	d02e      	beq.n	276c <__swbuf_r+0x8c>
-    270e:	6823      	ldr	r3, [r4, #0]
-    2710:	6922      	ldr	r2, [r4, #16]
-    2712:	b2f7      	uxtb	r7, r6
-    2714:	1a98      	subs	r0, r3, r2
-    2716:	6963      	ldr	r3, [r4, #20]
-    2718:	b2f6      	uxtb	r6, r6
-    271a:	4298      	cmp	r0, r3
-    271c:	db05      	blt.n	272a <__swbuf_r+0x4a>
-    271e:	0021      	movs	r1, r4
-    2720:	0028      	movs	r0, r5
-    2722:	f000 f933 	bl	298c <_fflush_r>
-    2726:	2800      	cmp	r0, #0
-    2728:	d126      	bne.n	2778 <__swbuf_r+0x98>
-    272a:	68a3      	ldr	r3, [r4, #8]
-    272c:	3001      	adds	r0, #1
-    272e:	3b01      	subs	r3, #1
-    2730:	60a3      	str	r3, [r4, #8]
-    2732:	6823      	ldr	r3, [r4, #0]
-    2734:	1c5a      	adds	r2, r3, #1
-    2736:	6022      	str	r2, [r4, #0]
-    2738:	701f      	strb	r7, [r3, #0]
-    273a:	6963      	ldr	r3, [r4, #20]
-    273c:	4298      	cmp	r0, r3
-    273e:	d004      	beq.n	274a <__swbuf_r+0x6a>
-    2740:	89a3      	ldrh	r3, [r4, #12]
-    2742:	07db      	lsls	r3, r3, #31
-    2744:	d51a      	bpl.n	277c <__swbuf_r+0x9c>
-    2746:	2e0a      	cmp	r6, #10
-    2748:	d118      	bne.n	277c <__swbuf_r+0x9c>
-    274a:	0021      	movs	r1, r4
-    274c:	0028      	movs	r0, r5
-    274e:	f000 f91d 	bl	298c <_fflush_r>
-    2752:	2800      	cmp	r0, #0
-    2754:	d012      	beq.n	277c <__swbuf_r+0x9c>
-    2756:	e00f      	b.n	2778 <__swbuf_r+0x98>
-    2758:	4b0a      	ldr	r3, [pc, #40]	; (2784 <__swbuf_r+0xa4>)
-    275a:	429c      	cmp	r4, r3
-    275c:	d101      	bne.n	2762 <__swbuf_r+0x82>
-    275e:	68ac      	ldr	r4, [r5, #8]
-    2760:	e7cd      	b.n	26fe <__swbuf_r+0x1e>
-    2762:	4b09      	ldr	r3, [pc, #36]	; (2788 <__swbuf_r+0xa8>)
-    2764:	429c      	cmp	r4, r3
-    2766:	d1ca      	bne.n	26fe <__swbuf_r+0x1e>
-    2768:	68ec      	ldr	r4, [r5, #12]
-    276a:	e7c8      	b.n	26fe <__swbuf_r+0x1e>
-    276c:	0021      	movs	r1, r4
-    276e:	0028      	movs	r0, r5
-    2770:	f000 f80c 	bl	278c <__swsetup_r>
-    2774:	2800      	cmp	r0, #0
-    2776:	d0ca      	beq.n	270e <__swbuf_r+0x2e>
-    2778:	2601      	movs	r6, #1
-    277a:	4276      	negs	r6, r6
-    277c:	0030      	movs	r0, r6
-    277e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    2780:	00003654 	.word	0x00003654
-    2784:	00003674 	.word	0x00003674
-    2788:	00003634 	.word	0x00003634
-
-0000278c <__swsetup_r>:
-    278c:	4b36      	ldr	r3, [pc, #216]	; (2868 <__swsetup_r+0xdc>)
-    278e:	b570      	push	{r4, r5, r6, lr}
-    2790:	681d      	ldr	r5, [r3, #0]
-    2792:	0006      	movs	r6, r0
-    2794:	000c      	movs	r4, r1
-    2796:	2d00      	cmp	r5, #0
-    2798:	d005      	beq.n	27a6 <__swsetup_r+0x1a>
-    279a:	69ab      	ldr	r3, [r5, #24]
-    279c:	2b00      	cmp	r3, #0
-    279e:	d102      	bne.n	27a6 <__swsetup_r+0x1a>
-    27a0:	0028      	movs	r0, r5
-    27a2:	f000 f961 	bl	2a68 <__sinit>
-    27a6:	4b31      	ldr	r3, [pc, #196]	; (286c <__swsetup_r+0xe0>)
-    27a8:	429c      	cmp	r4, r3
-    27aa:	d10f      	bne.n	27cc <__swsetup_r+0x40>
-    27ac:	686c      	ldr	r4, [r5, #4]
-    27ae:	230c      	movs	r3, #12
-    27b0:	5ee2      	ldrsh	r2, [r4, r3]
-    27b2:	b293      	uxth	r3, r2
-    27b4:	0719      	lsls	r1, r3, #28
-    27b6:	d42d      	bmi.n	2814 <__swsetup_r+0x88>
-    27b8:	06d9      	lsls	r1, r3, #27
-    27ba:	d411      	bmi.n	27e0 <__swsetup_r+0x54>
-    27bc:	2309      	movs	r3, #9
-    27be:	2001      	movs	r0, #1
-    27c0:	6033      	str	r3, [r6, #0]
-    27c2:	3337      	adds	r3, #55	; 0x37
-    27c4:	4313      	orrs	r3, r2
-    27c6:	81a3      	strh	r3, [r4, #12]
-    27c8:	4240      	negs	r0, r0
-    27ca:	bd70      	pop	{r4, r5, r6, pc}
-    27cc:	4b28      	ldr	r3, [pc, #160]	; (2870 <__swsetup_r+0xe4>)
-    27ce:	429c      	cmp	r4, r3
-    27d0:	d101      	bne.n	27d6 <__swsetup_r+0x4a>
-    27d2:	68ac      	ldr	r4, [r5, #8]
-    27d4:	e7eb      	b.n	27ae <__swsetup_r+0x22>
-    27d6:	4b27      	ldr	r3, [pc, #156]	; (2874 <__swsetup_r+0xe8>)
-    27d8:	429c      	cmp	r4, r3
-    27da:	d1e8      	bne.n	27ae <__swsetup_r+0x22>
-    27dc:	68ec      	ldr	r4, [r5, #12]
-    27de:	e7e6      	b.n	27ae <__swsetup_r+0x22>
-    27e0:	075b      	lsls	r3, r3, #29
-    27e2:	d513      	bpl.n	280c <__swsetup_r+0x80>
-    27e4:	6b61      	ldr	r1, [r4, #52]	; 0x34
-    27e6:	2900      	cmp	r1, #0
-    27e8:	d008      	beq.n	27fc <__swsetup_r+0x70>
-    27ea:	0023      	movs	r3, r4
-    27ec:	3344      	adds	r3, #68	; 0x44
-    27ee:	4299      	cmp	r1, r3
-    27f0:	d002      	beq.n	27f8 <__swsetup_r+0x6c>
-    27f2:	0030      	movs	r0, r6
-    27f4:	f000 fa44 	bl	2c80 <_free_r>
-    27f8:	2300      	movs	r3, #0
-    27fa:	6363      	str	r3, [r4, #52]	; 0x34
-    27fc:	2224      	movs	r2, #36	; 0x24
-    27fe:	89a3      	ldrh	r3, [r4, #12]
-    2800:	4393      	bics	r3, r2
-    2802:	81a3      	strh	r3, [r4, #12]
-    2804:	2300      	movs	r3, #0
-    2806:	6063      	str	r3, [r4, #4]
-    2808:	6923      	ldr	r3, [r4, #16]
-    280a:	6023      	str	r3, [r4, #0]
-    280c:	2308      	movs	r3, #8
-    280e:	89a2      	ldrh	r2, [r4, #12]
-    2810:	4313      	orrs	r3, r2
-    2812:	81a3      	strh	r3, [r4, #12]
-    2814:	6923      	ldr	r3, [r4, #16]
-    2816:	2b00      	cmp	r3, #0
-    2818:	d10b      	bne.n	2832 <__swsetup_r+0xa6>
-    281a:	21a0      	movs	r1, #160	; 0xa0
-    281c:	2280      	movs	r2, #128	; 0x80
-    281e:	89a3      	ldrh	r3, [r4, #12]
-    2820:	0089      	lsls	r1, r1, #2
-    2822:	0092      	lsls	r2, r2, #2
-    2824:	400b      	ands	r3, r1
-    2826:	4293      	cmp	r3, r2
-    2828:	d003      	beq.n	2832 <__swsetup_r+0xa6>
-    282a:	0021      	movs	r1, r4
-    282c:	0030      	movs	r0, r6
-    282e:	f000 f9d9 	bl	2be4 <__smakebuf_r>
-    2832:	2301      	movs	r3, #1
-    2834:	89a2      	ldrh	r2, [r4, #12]
-    2836:	4013      	ands	r3, r2
-    2838:	d011      	beq.n	285e <__swsetup_r+0xd2>
-    283a:	2300      	movs	r3, #0
-    283c:	60a3      	str	r3, [r4, #8]
-    283e:	6963      	ldr	r3, [r4, #20]
-    2840:	425b      	negs	r3, r3
-    2842:	61a3      	str	r3, [r4, #24]
-    2844:	2000      	movs	r0, #0
-    2846:	6923      	ldr	r3, [r4, #16]
-    2848:	4283      	cmp	r3, r0
-    284a:	d1be      	bne.n	27ca <__swsetup_r+0x3e>
-    284c:	230c      	movs	r3, #12
-    284e:	5ee2      	ldrsh	r2, [r4, r3]
-    2850:	0613      	lsls	r3, r2, #24
-    2852:	d5ba      	bpl.n	27ca <__swsetup_r+0x3e>
-    2854:	2340      	movs	r3, #64	; 0x40
-    2856:	4313      	orrs	r3, r2
-    2858:	81a3      	strh	r3, [r4, #12]
-    285a:	3801      	subs	r0, #1
-    285c:	e7b5      	b.n	27ca <__swsetup_r+0x3e>
-    285e:	0792      	lsls	r2, r2, #30
-    2860:	d400      	bmi.n	2864 <__swsetup_r+0xd8>
-    2862:	6963      	ldr	r3, [r4, #20]
-    2864:	60a3      	str	r3, [r4, #8]
-    2866:	e7ed      	b.n	2844 <__swsetup_r+0xb8>
-    2868:	20000018 	.word	0x20000018
-    286c:	00003654 	.word	0x00003654
-    2870:	00003674 	.word	0x00003674
-    2874:	00003634 	.word	0x00003634
-
-00002878 <__sflush_r>:
-    2878:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    287a:	898a      	ldrh	r2, [r1, #12]
-    287c:	0005      	movs	r5, r0
-    287e:	000c      	movs	r4, r1
-    2880:	0713      	lsls	r3, r2, #28
-    2882:	d460      	bmi.n	2946 <__sflush_r+0xce>
-    2884:	684b      	ldr	r3, [r1, #4]
-    2886:	2b00      	cmp	r3, #0
-    2888:	dc04      	bgt.n	2894 <__sflush_r+0x1c>
-    288a:	6c0b      	ldr	r3, [r1, #64]	; 0x40
-    288c:	2b00      	cmp	r3, #0
-    288e:	dc01      	bgt.n	2894 <__sflush_r+0x1c>
-    2890:	2000      	movs	r0, #0
-    2892:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    2894:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
-    2896:	2f00      	cmp	r7, #0
-    2898:	d0fa      	beq.n	2890 <__sflush_r+0x18>
-    289a:	2300      	movs	r3, #0
-    289c:	682e      	ldr	r6, [r5, #0]
-    289e:	602b      	str	r3, [r5, #0]
-    28a0:	2380      	movs	r3, #128	; 0x80
-    28a2:	015b      	lsls	r3, r3, #5
-    28a4:	401a      	ands	r2, r3
-    28a6:	d034      	beq.n	2912 <__sflush_r+0x9a>
-    28a8:	6d60      	ldr	r0, [r4, #84]	; 0x54
-    28aa:	89a3      	ldrh	r3, [r4, #12]
-    28ac:	075b      	lsls	r3, r3, #29
-    28ae:	d506      	bpl.n	28be <__sflush_r+0x46>
-    28b0:	6863      	ldr	r3, [r4, #4]
-    28b2:	1ac0      	subs	r0, r0, r3
-    28b4:	6b63      	ldr	r3, [r4, #52]	; 0x34
-    28b6:	2b00      	cmp	r3, #0
-    28b8:	d001      	beq.n	28be <__sflush_r+0x46>
-    28ba:	6c23      	ldr	r3, [r4, #64]	; 0x40
-    28bc:	1ac0      	subs	r0, r0, r3
-    28be:	0002      	movs	r2, r0
-    28c0:	6a21      	ldr	r1, [r4, #32]
-    28c2:	2300      	movs	r3, #0
-    28c4:	0028      	movs	r0, r5
-    28c6:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
-    28c8:	47b8      	blx	r7
-    28ca:	89a1      	ldrh	r1, [r4, #12]
-    28cc:	1c43      	adds	r3, r0, #1
-    28ce:	d106      	bne.n	28de <__sflush_r+0x66>
-    28d0:	682b      	ldr	r3, [r5, #0]
-    28d2:	2b1d      	cmp	r3, #29
-    28d4:	d831      	bhi.n	293a <__sflush_r+0xc2>
-    28d6:	4a2c      	ldr	r2, [pc, #176]	; (2988 <__sflush_r+0x110>)
-    28d8:	40da      	lsrs	r2, r3
-    28da:	07d3      	lsls	r3, r2, #31
-    28dc:	d52d      	bpl.n	293a <__sflush_r+0xc2>
-    28de:	2300      	movs	r3, #0
-    28e0:	6063      	str	r3, [r4, #4]
-    28e2:	6923      	ldr	r3, [r4, #16]
-    28e4:	6023      	str	r3, [r4, #0]
-    28e6:	04cb      	lsls	r3, r1, #19
-    28e8:	d505      	bpl.n	28f6 <__sflush_r+0x7e>
-    28ea:	1c43      	adds	r3, r0, #1
-    28ec:	d102      	bne.n	28f4 <__sflush_r+0x7c>
-    28ee:	682b      	ldr	r3, [r5, #0]
-    28f0:	2b00      	cmp	r3, #0
-    28f2:	d100      	bne.n	28f6 <__sflush_r+0x7e>
-    28f4:	6560      	str	r0, [r4, #84]	; 0x54
-    28f6:	6b61      	ldr	r1, [r4, #52]	; 0x34
-    28f8:	602e      	str	r6, [r5, #0]
-    28fa:	2900      	cmp	r1, #0
-    28fc:	d0c8      	beq.n	2890 <__sflush_r+0x18>
-    28fe:	0023      	movs	r3, r4
-    2900:	3344      	adds	r3, #68	; 0x44
-    2902:	4299      	cmp	r1, r3
-    2904:	d002      	beq.n	290c <__sflush_r+0x94>
-    2906:	0028      	movs	r0, r5
-    2908:	f000 f9ba 	bl	2c80 <_free_r>
-    290c:	2000      	movs	r0, #0
-    290e:	6360      	str	r0, [r4, #52]	; 0x34
-    2910:	e7bf      	b.n	2892 <__sflush_r+0x1a>
-    2912:	2301      	movs	r3, #1
-    2914:	6a21      	ldr	r1, [r4, #32]
-    2916:	0028      	movs	r0, r5
-    2918:	47b8      	blx	r7
-    291a:	1c43      	adds	r3, r0, #1
-    291c:	d1c5      	bne.n	28aa <__sflush_r+0x32>
-    291e:	682b      	ldr	r3, [r5, #0]
-    2920:	2b00      	cmp	r3, #0
-    2922:	d0c2      	beq.n	28aa <__sflush_r+0x32>
-    2924:	2b1d      	cmp	r3, #29
-    2926:	d001      	beq.n	292c <__sflush_r+0xb4>
-    2928:	2b16      	cmp	r3, #22
-    292a:	d101      	bne.n	2930 <__sflush_r+0xb8>
-    292c:	602e      	str	r6, [r5, #0]
-    292e:	e7af      	b.n	2890 <__sflush_r+0x18>
-    2930:	2340      	movs	r3, #64	; 0x40
-    2932:	89a2      	ldrh	r2, [r4, #12]
-    2934:	4313      	orrs	r3, r2
-    2936:	81a3      	strh	r3, [r4, #12]
-    2938:	e7ab      	b.n	2892 <__sflush_r+0x1a>
-    293a:	2340      	movs	r3, #64	; 0x40
-    293c:	430b      	orrs	r3, r1
-    293e:	2001      	movs	r0, #1
-    2940:	81a3      	strh	r3, [r4, #12]
-    2942:	4240      	negs	r0, r0
-    2944:	e7a5      	b.n	2892 <__sflush_r+0x1a>
-    2946:	690f      	ldr	r7, [r1, #16]
-    2948:	2f00      	cmp	r7, #0
-    294a:	d0a1      	beq.n	2890 <__sflush_r+0x18>
-    294c:	680b      	ldr	r3, [r1, #0]
-    294e:	600f      	str	r7, [r1, #0]
-    2950:	1bdb      	subs	r3, r3, r7
-    2952:	9301      	str	r3, [sp, #4]
-    2954:	2300      	movs	r3, #0
-    2956:	0792      	lsls	r2, r2, #30
-    2958:	d100      	bne.n	295c <__sflush_r+0xe4>
-    295a:	694b      	ldr	r3, [r1, #20]
-    295c:	60a3      	str	r3, [r4, #8]
-    295e:	9b01      	ldr	r3, [sp, #4]
-    2960:	2b00      	cmp	r3, #0
-    2962:	dc00      	bgt.n	2966 <__sflush_r+0xee>
-    2964:	e794      	b.n	2890 <__sflush_r+0x18>
-    2966:	9b01      	ldr	r3, [sp, #4]
-    2968:	003a      	movs	r2, r7
-    296a:	6a21      	ldr	r1, [r4, #32]
-    296c:	0028      	movs	r0, r5
-    296e:	6aa6      	ldr	r6, [r4, #40]	; 0x28
-    2970:	47b0      	blx	r6
-    2972:	2800      	cmp	r0, #0
-    2974:	dc03      	bgt.n	297e <__sflush_r+0x106>
-    2976:	2340      	movs	r3, #64	; 0x40
-    2978:	89a2      	ldrh	r2, [r4, #12]
-    297a:	4313      	orrs	r3, r2
-    297c:	e7df      	b.n	293e <__sflush_r+0xc6>
-    297e:	9b01      	ldr	r3, [sp, #4]
-    2980:	183f      	adds	r7, r7, r0
-    2982:	1a1b      	subs	r3, r3, r0
-    2984:	9301      	str	r3, [sp, #4]
-    2986:	e7ea      	b.n	295e <__sflush_r+0xe6>
-    2988:	20400001 	.word	0x20400001
-
-0000298c <_fflush_r>:
-    298c:	690b      	ldr	r3, [r1, #16]
-    298e:	b570      	push	{r4, r5, r6, lr}
-    2990:	0005      	movs	r5, r0
-    2992:	000c      	movs	r4, r1
-    2994:	2b00      	cmp	r3, #0
-    2996:	d101      	bne.n	299c <_fflush_r+0x10>
-    2998:	2000      	movs	r0, #0
-    299a:	bd70      	pop	{r4, r5, r6, pc}
-    299c:	2800      	cmp	r0, #0
-    299e:	d004      	beq.n	29aa <_fflush_r+0x1e>
-    29a0:	6983      	ldr	r3, [r0, #24]
-    29a2:	2b00      	cmp	r3, #0
-    29a4:	d101      	bne.n	29aa <_fflush_r+0x1e>
-    29a6:	f000 f85f 	bl	2a68 <__sinit>
-    29aa:	4b0b      	ldr	r3, [pc, #44]	; (29d8 <_fflush_r+0x4c>)
-    29ac:	429c      	cmp	r4, r3
-    29ae:	d109      	bne.n	29c4 <_fflush_r+0x38>
-    29b0:	686c      	ldr	r4, [r5, #4]
-    29b2:	220c      	movs	r2, #12
-    29b4:	5ea3      	ldrsh	r3, [r4, r2]
-    29b6:	2b00      	cmp	r3, #0
-    29b8:	d0ee      	beq.n	2998 <_fflush_r+0xc>
-    29ba:	0021      	movs	r1, r4
-    29bc:	0028      	movs	r0, r5
-    29be:	f7ff ff5b 	bl	2878 <__sflush_r>
-    29c2:	e7ea      	b.n	299a <_fflush_r+0xe>
-    29c4:	4b05      	ldr	r3, [pc, #20]	; (29dc <_fflush_r+0x50>)
-    29c6:	429c      	cmp	r4, r3
-    29c8:	d101      	bne.n	29ce <_fflush_r+0x42>
-    29ca:	68ac      	ldr	r4, [r5, #8]
-    29cc:	e7f1      	b.n	29b2 <_fflush_r+0x26>
-    29ce:	4b04      	ldr	r3, [pc, #16]	; (29e0 <_fflush_r+0x54>)
-    29d0:	429c      	cmp	r4, r3
-    29d2:	d1ee      	bne.n	29b2 <_fflush_r+0x26>
-    29d4:	68ec      	ldr	r4, [r5, #12]
-    29d6:	e7ec      	b.n	29b2 <_fflush_r+0x26>
-    29d8:	00003654 	.word	0x00003654
-    29dc:	00003674 	.word	0x00003674
-    29e0:	00003634 	.word	0x00003634
-
-000029e4 <_cleanup_r>:
-    29e4:	b510      	push	{r4, lr}
-    29e6:	4902      	ldr	r1, [pc, #8]	; (29f0 <_cleanup_r+0xc>)
-    29e8:	f000 f8b2 	bl	2b50 <_fwalk_reent>
-    29ec:	bd10      	pop	{r4, pc}
-    29ee:	46c0      	nop			; (mov r8, r8)
-    29f0:	0000298d 	.word	0x0000298d
-
-000029f4 <std.isra.0>:
-    29f4:	2300      	movs	r3, #0
-    29f6:	b510      	push	{r4, lr}
-    29f8:	0004      	movs	r4, r0
-    29fa:	6003      	str	r3, [r0, #0]
-    29fc:	6043      	str	r3, [r0, #4]
-    29fe:	6083      	str	r3, [r0, #8]
-    2a00:	8181      	strh	r1, [r0, #12]
-    2a02:	6643      	str	r3, [r0, #100]	; 0x64
-    2a04:	81c2      	strh	r2, [r0, #14]
-    2a06:	6103      	str	r3, [r0, #16]
-    2a08:	6143      	str	r3, [r0, #20]
-    2a0a:	6183      	str	r3, [r0, #24]
-    2a0c:	0019      	movs	r1, r3
-    2a0e:	2208      	movs	r2, #8
-    2a10:	305c      	adds	r0, #92	; 0x5c
-    2a12:	f7ff fd22 	bl	245a <memset>
-    2a16:	4b05      	ldr	r3, [pc, #20]	; (2a2c <std.isra.0+0x38>)
-    2a18:	6224      	str	r4, [r4, #32]
-    2a1a:	6263      	str	r3, [r4, #36]	; 0x24
-    2a1c:	4b04      	ldr	r3, [pc, #16]	; (2a30 <std.isra.0+0x3c>)
-    2a1e:	62a3      	str	r3, [r4, #40]	; 0x28
-    2a20:	4b04      	ldr	r3, [pc, #16]	; (2a34 <std.isra.0+0x40>)
-    2a22:	62e3      	str	r3, [r4, #44]	; 0x2c
-    2a24:	4b04      	ldr	r3, [pc, #16]	; (2a38 <std.isra.0+0x44>)
-    2a26:	6323      	str	r3, [r4, #48]	; 0x30
-    2a28:	bd10      	pop	{r4, pc}
-    2a2a:	46c0      	nop			; (mov r8, r8)
-    2a2c:	0000338d 	.word	0x0000338d
-    2a30:	000033b5 	.word	0x000033b5
-    2a34:	000033ed 	.word	0x000033ed
-    2a38:	00003419 	.word	0x00003419
-
-00002a3c <__sfmoreglue>:
-    2a3c:	b570      	push	{r4, r5, r6, lr}
-    2a3e:	2568      	movs	r5, #104	; 0x68
-    2a40:	1e4a      	subs	r2, r1, #1
-    2a42:	4355      	muls	r5, r2
-    2a44:	000e      	movs	r6, r1
-    2a46:	0029      	movs	r1, r5
-    2a48:	3174      	adds	r1, #116	; 0x74
-    2a4a:	f000 f963 	bl	2d14 <_malloc_r>
-    2a4e:	1e04      	subs	r4, r0, #0
-    2a50:	d008      	beq.n	2a64 <__sfmoreglue+0x28>
-    2a52:	2100      	movs	r1, #0
-    2a54:	002a      	movs	r2, r5
-    2a56:	6001      	str	r1, [r0, #0]
-    2a58:	6046      	str	r6, [r0, #4]
-    2a5a:	300c      	adds	r0, #12
-    2a5c:	60a0      	str	r0, [r4, #8]
-    2a5e:	3268      	adds	r2, #104	; 0x68
-    2a60:	f7ff fcfb 	bl	245a <memset>
-    2a64:	0020      	movs	r0, r4
-    2a66:	bd70      	pop	{r4, r5, r6, pc}
-
-00002a68 <__sinit>:
-    2a68:	6983      	ldr	r3, [r0, #24]
-    2a6a:	b513      	push	{r0, r1, r4, lr}
-    2a6c:	0004      	movs	r4, r0
-    2a6e:	2b00      	cmp	r3, #0
-    2a70:	d128      	bne.n	2ac4 <__sinit+0x5c>
-    2a72:	6483      	str	r3, [r0, #72]	; 0x48
-    2a74:	64c3      	str	r3, [r0, #76]	; 0x4c
-    2a76:	6503      	str	r3, [r0, #80]	; 0x50
-    2a78:	4b13      	ldr	r3, [pc, #76]	; (2ac8 <__sinit+0x60>)
-    2a7a:	4a14      	ldr	r2, [pc, #80]	; (2acc <__sinit+0x64>)
-    2a7c:	681b      	ldr	r3, [r3, #0]
-    2a7e:	6282      	str	r2, [r0, #40]	; 0x28
-    2a80:	9301      	str	r3, [sp, #4]
-    2a82:	4298      	cmp	r0, r3
-    2a84:	d101      	bne.n	2a8a <__sinit+0x22>
-    2a86:	2301      	movs	r3, #1
-    2a88:	6183      	str	r3, [r0, #24]
-    2a8a:	0020      	movs	r0, r4
-    2a8c:	f000 f820 	bl	2ad0 <__sfp>
-    2a90:	6060      	str	r0, [r4, #4]
-    2a92:	0020      	movs	r0, r4
-    2a94:	f000 f81c 	bl	2ad0 <__sfp>
-    2a98:	60a0      	str	r0, [r4, #8]
-    2a9a:	0020      	movs	r0, r4
-    2a9c:	f000 f818 	bl	2ad0 <__sfp>
-    2aa0:	2200      	movs	r2, #0
-    2aa2:	60e0      	str	r0, [r4, #12]
-    2aa4:	2104      	movs	r1, #4
-    2aa6:	6860      	ldr	r0, [r4, #4]
-    2aa8:	f7ff ffa4 	bl	29f4 <std.isra.0>
-    2aac:	2201      	movs	r2, #1
-    2aae:	2109      	movs	r1, #9
-    2ab0:	68a0      	ldr	r0, [r4, #8]
-    2ab2:	f7ff ff9f 	bl	29f4 <std.isra.0>
-    2ab6:	2202      	movs	r2, #2
-    2ab8:	2112      	movs	r1, #18
-    2aba:	68e0      	ldr	r0, [r4, #12]
-    2abc:	f7ff ff9a 	bl	29f4 <std.isra.0>
-    2ac0:	2301      	movs	r3, #1
-    2ac2:	61a3      	str	r3, [r4, #24]
-    2ac4:	bd13      	pop	{r0, r1, r4, pc}
-    2ac6:	46c0      	nop			; (mov r8, r8)
-    2ac8:	00003630 	.word	0x00003630
-    2acc:	000029e5 	.word	0x000029e5
-
-00002ad0 <__sfp>:
-    2ad0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    2ad2:	4b1e      	ldr	r3, [pc, #120]	; (2b4c <__sfp+0x7c>)
-    2ad4:	0007      	movs	r7, r0
-    2ad6:	681e      	ldr	r6, [r3, #0]
-    2ad8:	69b3      	ldr	r3, [r6, #24]
-    2ada:	2b00      	cmp	r3, #0
-    2adc:	d102      	bne.n	2ae4 <__sfp+0x14>
-    2ade:	0030      	movs	r0, r6
-    2ae0:	f7ff ffc2 	bl	2a68 <__sinit>
-    2ae4:	3648      	adds	r6, #72	; 0x48
-    2ae6:	68b4      	ldr	r4, [r6, #8]
-    2ae8:	6873      	ldr	r3, [r6, #4]
-    2aea:	3b01      	subs	r3, #1
-    2aec:	d504      	bpl.n	2af8 <__sfp+0x28>
-    2aee:	6833      	ldr	r3, [r6, #0]
-    2af0:	2b00      	cmp	r3, #0
-    2af2:	d007      	beq.n	2b04 <__sfp+0x34>
-    2af4:	6836      	ldr	r6, [r6, #0]
-    2af6:	e7f6      	b.n	2ae6 <__sfp+0x16>
-    2af8:	220c      	movs	r2, #12
-    2afa:	5ea5      	ldrsh	r5, [r4, r2]
-    2afc:	2d00      	cmp	r5, #0
-    2afe:	d00d      	beq.n	2b1c <__sfp+0x4c>
-    2b00:	3468      	adds	r4, #104	; 0x68
-    2b02:	e7f2      	b.n	2aea <__sfp+0x1a>
-    2b04:	2104      	movs	r1, #4
-    2b06:	0038      	movs	r0, r7
-    2b08:	f7ff ff98 	bl	2a3c <__sfmoreglue>
-    2b0c:	6030      	str	r0, [r6, #0]
-    2b0e:	2800      	cmp	r0, #0
-    2b10:	d1f0      	bne.n	2af4 <__sfp+0x24>
-    2b12:	230c      	movs	r3, #12
-    2b14:	0004      	movs	r4, r0
-    2b16:	603b      	str	r3, [r7, #0]
-    2b18:	0020      	movs	r0, r4
-    2b1a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    2b1c:	2301      	movs	r3, #1
-    2b1e:	0020      	movs	r0, r4
-    2b20:	425b      	negs	r3, r3
-    2b22:	81e3      	strh	r3, [r4, #14]
-    2b24:	3302      	adds	r3, #2
-    2b26:	81a3      	strh	r3, [r4, #12]
-    2b28:	6665      	str	r5, [r4, #100]	; 0x64
-    2b2a:	6025      	str	r5, [r4, #0]
-    2b2c:	60a5      	str	r5, [r4, #8]
-    2b2e:	6065      	str	r5, [r4, #4]
-    2b30:	6125      	str	r5, [r4, #16]
-    2b32:	6165      	str	r5, [r4, #20]
-    2b34:	61a5      	str	r5, [r4, #24]
-    2b36:	2208      	movs	r2, #8
-    2b38:	0029      	movs	r1, r5
-    2b3a:	305c      	adds	r0, #92	; 0x5c
-    2b3c:	f7ff fc8d 	bl	245a <memset>
-    2b40:	6365      	str	r5, [r4, #52]	; 0x34
-    2b42:	63a5      	str	r5, [r4, #56]	; 0x38
-    2b44:	64a5      	str	r5, [r4, #72]	; 0x48
-    2b46:	64e5      	str	r5, [r4, #76]	; 0x4c
-    2b48:	e7e6      	b.n	2b18 <__sfp+0x48>
-    2b4a:	46c0      	nop			; (mov r8, r8)
-    2b4c:	00003630 	.word	0x00003630
-
-00002b50 <_fwalk_reent>:
-    2b50:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    2b52:	0004      	movs	r4, r0
-    2b54:	0007      	movs	r7, r0
-    2b56:	2600      	movs	r6, #0
-    2b58:	9101      	str	r1, [sp, #4]
-    2b5a:	3448      	adds	r4, #72	; 0x48
-    2b5c:	2c00      	cmp	r4, #0
-    2b5e:	d101      	bne.n	2b64 <_fwalk_reent+0x14>
-    2b60:	0030      	movs	r0, r6
-    2b62:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    2b64:	6863      	ldr	r3, [r4, #4]
-    2b66:	68a5      	ldr	r5, [r4, #8]
-    2b68:	9300      	str	r3, [sp, #0]
-    2b6a:	9b00      	ldr	r3, [sp, #0]
-    2b6c:	3b01      	subs	r3, #1
-    2b6e:	9300      	str	r3, [sp, #0]
-    2b70:	d501      	bpl.n	2b76 <_fwalk_reent+0x26>
-    2b72:	6824      	ldr	r4, [r4, #0]
-    2b74:	e7f2      	b.n	2b5c <_fwalk_reent+0xc>
-    2b76:	89ab      	ldrh	r3, [r5, #12]
-    2b78:	2b01      	cmp	r3, #1
-    2b7a:	d908      	bls.n	2b8e <_fwalk_reent+0x3e>
-    2b7c:	220e      	movs	r2, #14
-    2b7e:	5eab      	ldrsh	r3, [r5, r2]
-    2b80:	3301      	adds	r3, #1
-    2b82:	d004      	beq.n	2b8e <_fwalk_reent+0x3e>
-    2b84:	0029      	movs	r1, r5
-    2b86:	0038      	movs	r0, r7
-    2b88:	9b01      	ldr	r3, [sp, #4]
-    2b8a:	4798      	blx	r3
-    2b8c:	4306      	orrs	r6, r0
-    2b8e:	3568      	adds	r5, #104	; 0x68
-    2b90:	e7eb      	b.n	2b6a <_fwalk_reent+0x1a>
-	...
-
-00002b94 <__swhatbuf_r>:
-    2b94:	b570      	push	{r4, r5, r6, lr}
-    2b96:	000e      	movs	r6, r1
-    2b98:	001d      	movs	r5, r3
-    2b9a:	230e      	movs	r3, #14
-    2b9c:	5ec9      	ldrsh	r1, [r1, r3]
-    2b9e:	b090      	sub	sp, #64	; 0x40
-    2ba0:	0014      	movs	r4, r2
-    2ba2:	2900      	cmp	r1, #0
-    2ba4:	da07      	bge.n	2bb6 <__swhatbuf_r+0x22>
-    2ba6:	2300      	movs	r3, #0
-    2ba8:	602b      	str	r3, [r5, #0]
-    2baa:	89b3      	ldrh	r3, [r6, #12]
-    2bac:	061b      	lsls	r3, r3, #24
-    2bae:	d411      	bmi.n	2bd4 <__swhatbuf_r+0x40>
-    2bb0:	2380      	movs	r3, #128	; 0x80
-    2bb2:	00db      	lsls	r3, r3, #3
-    2bb4:	e00f      	b.n	2bd6 <__swhatbuf_r+0x42>
-    2bb6:	aa01      	add	r2, sp, #4
-    2bb8:	f000 fc5a 	bl	3470 <_fstat_r>
-    2bbc:	2800      	cmp	r0, #0
-    2bbe:	dbf2      	blt.n	2ba6 <__swhatbuf_r+0x12>
-    2bc0:	22f0      	movs	r2, #240	; 0xf0
-    2bc2:	9b02      	ldr	r3, [sp, #8]
-    2bc4:	0212      	lsls	r2, r2, #8
-    2bc6:	4013      	ands	r3, r2
-    2bc8:	4a05      	ldr	r2, [pc, #20]	; (2be0 <__swhatbuf_r+0x4c>)
-    2bca:	189b      	adds	r3, r3, r2
-    2bcc:	425a      	negs	r2, r3
-    2bce:	4153      	adcs	r3, r2
-    2bd0:	602b      	str	r3, [r5, #0]
-    2bd2:	e7ed      	b.n	2bb0 <__swhatbuf_r+0x1c>
-    2bd4:	2340      	movs	r3, #64	; 0x40
-    2bd6:	2000      	movs	r0, #0
-    2bd8:	6023      	str	r3, [r4, #0]
-    2bda:	b010      	add	sp, #64	; 0x40
-    2bdc:	bd70      	pop	{r4, r5, r6, pc}
-    2bde:	46c0      	nop			; (mov r8, r8)
-    2be0:	ffffe000 	.word	0xffffe000
-
-00002be4 <__smakebuf_r>:
-    2be4:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    2be6:	2602      	movs	r6, #2
-    2be8:	898b      	ldrh	r3, [r1, #12]
-    2bea:	0005      	movs	r5, r0
-    2bec:	000c      	movs	r4, r1
-    2bee:	4233      	tst	r3, r6
-    2bf0:	d006      	beq.n	2c00 <__smakebuf_r+0x1c>
-    2bf2:	0023      	movs	r3, r4
-    2bf4:	3347      	adds	r3, #71	; 0x47
-    2bf6:	6023      	str	r3, [r4, #0]
-    2bf8:	6123      	str	r3, [r4, #16]
-    2bfa:	2301      	movs	r3, #1
-    2bfc:	6163      	str	r3, [r4, #20]
-    2bfe:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
-    2c00:	ab01      	add	r3, sp, #4
-    2c02:	466a      	mov	r2, sp
-    2c04:	f7ff ffc6 	bl	2b94 <__swhatbuf_r>
-    2c08:	9900      	ldr	r1, [sp, #0]
-    2c0a:	0007      	movs	r7, r0
-    2c0c:	0028      	movs	r0, r5
-    2c0e:	f000 f881 	bl	2d14 <_malloc_r>
-    2c12:	2800      	cmp	r0, #0
-    2c14:	d108      	bne.n	2c28 <__smakebuf_r+0x44>
-    2c16:	220c      	movs	r2, #12
-    2c18:	5ea3      	ldrsh	r3, [r4, r2]
-    2c1a:	059a      	lsls	r2, r3, #22
-    2c1c:	d4ef      	bmi.n	2bfe <__smakebuf_r+0x1a>
-    2c1e:	2203      	movs	r2, #3
-    2c20:	4393      	bics	r3, r2
-    2c22:	431e      	orrs	r6, r3
-    2c24:	81a6      	strh	r6, [r4, #12]
-    2c26:	e7e4      	b.n	2bf2 <__smakebuf_r+0xe>
-    2c28:	4b0f      	ldr	r3, [pc, #60]	; (2c68 <__smakebuf_r+0x84>)
-    2c2a:	62ab      	str	r3, [r5, #40]	; 0x28
-    2c2c:	2380      	movs	r3, #128	; 0x80
-    2c2e:	89a2      	ldrh	r2, [r4, #12]
-    2c30:	6020      	str	r0, [r4, #0]
-    2c32:	4313      	orrs	r3, r2
-    2c34:	81a3      	strh	r3, [r4, #12]
-    2c36:	9b00      	ldr	r3, [sp, #0]
-    2c38:	6120      	str	r0, [r4, #16]
-    2c3a:	6163      	str	r3, [r4, #20]
-    2c3c:	9b01      	ldr	r3, [sp, #4]
-    2c3e:	2b00      	cmp	r3, #0
-    2c40:	d00d      	beq.n	2c5e <__smakebuf_r+0x7a>
-    2c42:	230e      	movs	r3, #14
-    2c44:	5ee1      	ldrsh	r1, [r4, r3]
-    2c46:	0028      	movs	r0, r5
-    2c48:	f000 fc24 	bl	3494 <_isatty_r>
-    2c4c:	2800      	cmp	r0, #0
-    2c4e:	d006      	beq.n	2c5e <__smakebuf_r+0x7a>
-    2c50:	2203      	movs	r2, #3
-    2c52:	89a3      	ldrh	r3, [r4, #12]
-    2c54:	4393      	bics	r3, r2
-    2c56:	001a      	movs	r2, r3
-    2c58:	2301      	movs	r3, #1
-    2c5a:	4313      	orrs	r3, r2
-    2c5c:	81a3      	strh	r3, [r4, #12]
-    2c5e:	89a0      	ldrh	r0, [r4, #12]
-    2c60:	4338      	orrs	r0, r7
-    2c62:	81a0      	strh	r0, [r4, #12]
-    2c64:	e7cb      	b.n	2bfe <__smakebuf_r+0x1a>
-    2c66:	46c0      	nop			; (mov r8, r8)
-    2c68:	000029e5 	.word	0x000029e5
-
-00002c6c <malloc>:
-    2c6c:	b510      	push	{r4, lr}
-    2c6e:	4b03      	ldr	r3, [pc, #12]	; (2c7c <malloc+0x10>)
-    2c70:	0001      	movs	r1, r0
-    2c72:	6818      	ldr	r0, [r3, #0]
-    2c74:	f000 f84e 	bl	2d14 <_malloc_r>
-    2c78:	bd10      	pop	{r4, pc}
-    2c7a:	46c0      	nop			; (mov r8, r8)
-    2c7c:	20000018 	.word	0x20000018
-
-00002c80 <_free_r>:
-    2c80:	b570      	push	{r4, r5, r6, lr}
-    2c82:	0005      	movs	r5, r0
-    2c84:	2900      	cmp	r1, #0
-    2c86:	d010      	beq.n	2caa <_free_r+0x2a>
-    2c88:	1f0c      	subs	r4, r1, #4
-    2c8a:	6823      	ldr	r3, [r4, #0]
-    2c8c:	2b00      	cmp	r3, #0
-    2c8e:	da00      	bge.n	2c92 <_free_r+0x12>
-    2c90:	18e4      	adds	r4, r4, r3
-    2c92:	0028      	movs	r0, r5
-    2c94:	f000 fc2f 	bl	34f6 <__malloc_lock>
-    2c98:	4a1d      	ldr	r2, [pc, #116]	; (2d10 <_free_r+0x90>)
-    2c9a:	6813      	ldr	r3, [r2, #0]
-    2c9c:	2b00      	cmp	r3, #0
-    2c9e:	d105      	bne.n	2cac <_free_r+0x2c>
-    2ca0:	6063      	str	r3, [r4, #4]
-    2ca2:	6014      	str	r4, [r2, #0]
-    2ca4:	0028      	movs	r0, r5
-    2ca6:	f000 fc27 	bl	34f8 <__malloc_unlock>
-    2caa:	bd70      	pop	{r4, r5, r6, pc}
-    2cac:	42a3      	cmp	r3, r4
-    2cae:	d909      	bls.n	2cc4 <_free_r+0x44>
-    2cb0:	6821      	ldr	r1, [r4, #0]
-    2cb2:	1860      	adds	r0, r4, r1
-    2cb4:	4283      	cmp	r3, r0
-    2cb6:	d1f3      	bne.n	2ca0 <_free_r+0x20>
-    2cb8:	6818      	ldr	r0, [r3, #0]
-    2cba:	685b      	ldr	r3, [r3, #4]
-    2cbc:	1841      	adds	r1, r0, r1
-    2cbe:	6021      	str	r1, [r4, #0]
-    2cc0:	e7ee      	b.n	2ca0 <_free_r+0x20>
-    2cc2:	0013      	movs	r3, r2
-    2cc4:	685a      	ldr	r2, [r3, #4]
-    2cc6:	2a00      	cmp	r2, #0
-    2cc8:	d001      	beq.n	2cce <_free_r+0x4e>
-    2cca:	42a2      	cmp	r2, r4
-    2ccc:	d9f9      	bls.n	2cc2 <_free_r+0x42>
-    2cce:	6819      	ldr	r1, [r3, #0]
-    2cd0:	1858      	adds	r0, r3, r1
-    2cd2:	42a0      	cmp	r0, r4
-    2cd4:	d10b      	bne.n	2cee <_free_r+0x6e>
-    2cd6:	6820      	ldr	r0, [r4, #0]
-    2cd8:	1809      	adds	r1, r1, r0
-    2cda:	1858      	adds	r0, r3, r1
-    2cdc:	6019      	str	r1, [r3, #0]
-    2cde:	4282      	cmp	r2, r0
-    2ce0:	d1e0      	bne.n	2ca4 <_free_r+0x24>
-    2ce2:	6810      	ldr	r0, [r2, #0]
-    2ce4:	6852      	ldr	r2, [r2, #4]
-    2ce6:	1841      	adds	r1, r0, r1
-    2ce8:	6019      	str	r1, [r3, #0]
-    2cea:	605a      	str	r2, [r3, #4]
-    2cec:	e7da      	b.n	2ca4 <_free_r+0x24>
-    2cee:	42a0      	cmp	r0, r4
-    2cf0:	d902      	bls.n	2cf8 <_free_r+0x78>
-    2cf2:	230c      	movs	r3, #12
-    2cf4:	602b      	str	r3, [r5, #0]
-    2cf6:	e7d5      	b.n	2ca4 <_free_r+0x24>
-    2cf8:	6821      	ldr	r1, [r4, #0]
-    2cfa:	1860      	adds	r0, r4, r1
-    2cfc:	4282      	cmp	r2, r0
-    2cfe:	d103      	bne.n	2d08 <_free_r+0x88>
-    2d00:	6810      	ldr	r0, [r2, #0]
-    2d02:	6852      	ldr	r2, [r2, #4]
-    2d04:	1841      	adds	r1, r0, r1
-    2d06:	6021      	str	r1, [r4, #0]
-    2d08:	6062      	str	r2, [r4, #4]
-    2d0a:	605c      	str	r4, [r3, #4]
-    2d0c:	e7ca      	b.n	2ca4 <_free_r+0x24>
-    2d0e:	46c0      	nop			; (mov r8, r8)
-    2d10:	200001cc 	.word	0x200001cc
-
-00002d14 <_malloc_r>:
-    2d14:	2303      	movs	r3, #3
-    2d16:	b570      	push	{r4, r5, r6, lr}
-    2d18:	1ccd      	adds	r5, r1, #3
-    2d1a:	439d      	bics	r5, r3
-    2d1c:	3508      	adds	r5, #8
-    2d1e:	0006      	movs	r6, r0
-    2d20:	2d0c      	cmp	r5, #12
-    2d22:	d21e      	bcs.n	2d62 <_malloc_r+0x4e>
-    2d24:	250c      	movs	r5, #12
-    2d26:	42a9      	cmp	r1, r5
-    2d28:	d81d      	bhi.n	2d66 <_malloc_r+0x52>
-    2d2a:	0030      	movs	r0, r6
-    2d2c:	f000 fbe3 	bl	34f6 <__malloc_lock>
-    2d30:	4a25      	ldr	r2, [pc, #148]	; (2dc8 <_malloc_r+0xb4>)
-    2d32:	6814      	ldr	r4, [r2, #0]
-    2d34:	0021      	movs	r1, r4
-    2d36:	2900      	cmp	r1, #0
-    2d38:	d119      	bne.n	2d6e <_malloc_r+0x5a>
-    2d3a:	4c24      	ldr	r4, [pc, #144]	; (2dcc <_malloc_r+0xb8>)
-    2d3c:	6823      	ldr	r3, [r4, #0]
-    2d3e:	2b00      	cmp	r3, #0
-    2d40:	d103      	bne.n	2d4a <_malloc_r+0x36>
-    2d42:	0030      	movs	r0, r6
-    2d44:	f000 fb10 	bl	3368 <_sbrk_r>
-    2d48:	6020      	str	r0, [r4, #0]
-    2d4a:	0029      	movs	r1, r5
-    2d4c:	0030      	movs	r0, r6
-    2d4e:	f000 fb0b 	bl	3368 <_sbrk_r>
-    2d52:	1c43      	adds	r3, r0, #1
-    2d54:	d12c      	bne.n	2db0 <_malloc_r+0x9c>
-    2d56:	230c      	movs	r3, #12
-    2d58:	0030      	movs	r0, r6
-    2d5a:	6033      	str	r3, [r6, #0]
-    2d5c:	f000 fbcc 	bl	34f8 <__malloc_unlock>
-    2d60:	e003      	b.n	2d6a <_malloc_r+0x56>
-    2d62:	2d00      	cmp	r5, #0
-    2d64:	dadf      	bge.n	2d26 <_malloc_r+0x12>
-    2d66:	230c      	movs	r3, #12
-    2d68:	6033      	str	r3, [r6, #0]
-    2d6a:	2000      	movs	r0, #0
-    2d6c:	bd70      	pop	{r4, r5, r6, pc}
-    2d6e:	680b      	ldr	r3, [r1, #0]
-    2d70:	1b5b      	subs	r3, r3, r5
-    2d72:	d41a      	bmi.n	2daa <_malloc_r+0x96>
-    2d74:	2b0b      	cmp	r3, #11
-    2d76:	d903      	bls.n	2d80 <_malloc_r+0x6c>
-    2d78:	600b      	str	r3, [r1, #0]
-    2d7a:	18cc      	adds	r4, r1, r3
-    2d7c:	6025      	str	r5, [r4, #0]
-    2d7e:	e003      	b.n	2d88 <_malloc_r+0x74>
-    2d80:	428c      	cmp	r4, r1
-    2d82:	d10e      	bne.n	2da2 <_malloc_r+0x8e>
-    2d84:	6863      	ldr	r3, [r4, #4]
-    2d86:	6013      	str	r3, [r2, #0]
-    2d88:	0030      	movs	r0, r6
-    2d8a:	f000 fbb5 	bl	34f8 <__malloc_unlock>
-    2d8e:	0020      	movs	r0, r4
-    2d90:	2207      	movs	r2, #7
-    2d92:	300b      	adds	r0, #11
-    2d94:	1d23      	adds	r3, r4, #4
-    2d96:	4390      	bics	r0, r2
-    2d98:	1ac3      	subs	r3, r0, r3
-    2d9a:	d0e7      	beq.n	2d6c <_malloc_r+0x58>
-    2d9c:	425a      	negs	r2, r3
-    2d9e:	50e2      	str	r2, [r4, r3]
-    2da0:	e7e4      	b.n	2d6c <_malloc_r+0x58>
-    2da2:	684b      	ldr	r3, [r1, #4]
-    2da4:	6063      	str	r3, [r4, #4]
-    2da6:	000c      	movs	r4, r1
-    2da8:	e7ee      	b.n	2d88 <_malloc_r+0x74>
-    2daa:	000c      	movs	r4, r1
-    2dac:	6849      	ldr	r1, [r1, #4]
-    2dae:	e7c2      	b.n	2d36 <_malloc_r+0x22>
-    2db0:	2303      	movs	r3, #3
-    2db2:	1cc4      	adds	r4, r0, #3
-    2db4:	439c      	bics	r4, r3
-    2db6:	42a0      	cmp	r0, r4
-    2db8:	d0e0      	beq.n	2d7c <_malloc_r+0x68>
-    2dba:	1a21      	subs	r1, r4, r0
-    2dbc:	0030      	movs	r0, r6
-    2dbe:	f000 fad3 	bl	3368 <_sbrk_r>
-    2dc2:	1c43      	adds	r3, r0, #1
-    2dc4:	d1da      	bne.n	2d7c <_malloc_r+0x68>
-    2dc6:	e7c6      	b.n	2d56 <_malloc_r+0x42>
-    2dc8:	200001cc 	.word	0x200001cc
-    2dcc:	200001d0 	.word	0x200001d0
-
-00002dd0 <__sfputc_r>:
-    2dd0:	6893      	ldr	r3, [r2, #8]
-    2dd2:	b510      	push	{r4, lr}
-    2dd4:	3b01      	subs	r3, #1
-    2dd6:	6093      	str	r3, [r2, #8]
-    2dd8:	2b00      	cmp	r3, #0
-    2dda:	da05      	bge.n	2de8 <__sfputc_r+0x18>
-    2ddc:	6994      	ldr	r4, [r2, #24]
-    2dde:	42a3      	cmp	r3, r4
-    2de0:	db08      	blt.n	2df4 <__sfputc_r+0x24>
-    2de2:	b2cb      	uxtb	r3, r1
-    2de4:	2b0a      	cmp	r3, #10
-    2de6:	d005      	beq.n	2df4 <__sfputc_r+0x24>
-    2de8:	6813      	ldr	r3, [r2, #0]
-    2dea:	1c58      	adds	r0, r3, #1
-    2dec:	6010      	str	r0, [r2, #0]
-    2dee:	7019      	strb	r1, [r3, #0]
-    2df0:	b2c8      	uxtb	r0, r1
-    2df2:	bd10      	pop	{r4, pc}
-    2df4:	f7ff fc74 	bl	26e0 <__swbuf_r>
-    2df8:	e7fb      	b.n	2df2 <__sfputc_r+0x22>
-
-00002dfa <__sfputs_r>:
-    2dfa:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    2dfc:	0006      	movs	r6, r0
-    2dfe:	000f      	movs	r7, r1
-    2e00:	0014      	movs	r4, r2
-    2e02:	18d5      	adds	r5, r2, r3
-    2e04:	42ac      	cmp	r4, r5
-    2e06:	d101      	bne.n	2e0c <__sfputs_r+0x12>
-    2e08:	2000      	movs	r0, #0
-    2e0a:	e007      	b.n	2e1c <__sfputs_r+0x22>
-    2e0c:	7821      	ldrb	r1, [r4, #0]
-    2e0e:	003a      	movs	r2, r7
-    2e10:	0030      	movs	r0, r6
-    2e12:	f7ff ffdd 	bl	2dd0 <__sfputc_r>
-    2e16:	3401      	adds	r4, #1
-    2e18:	1c43      	adds	r3, r0, #1
-    2e1a:	d1f3      	bne.n	2e04 <__sfputs_r+0xa>
-    2e1c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-	...
-
-00002e20 <_vfiprintf_r>:
-    2e20:	b5f0      	push	{r4, r5, r6, r7, lr}
-    2e22:	b09f      	sub	sp, #124	; 0x7c
-    2e24:	0006      	movs	r6, r0
-    2e26:	000f      	movs	r7, r1
-    2e28:	0014      	movs	r4, r2
-    2e2a:	9305      	str	r3, [sp, #20]
-    2e2c:	2800      	cmp	r0, #0
-    2e2e:	d004      	beq.n	2e3a <_vfiprintf_r+0x1a>
-    2e30:	6983      	ldr	r3, [r0, #24]
-    2e32:	2b00      	cmp	r3, #0
-    2e34:	d101      	bne.n	2e3a <_vfiprintf_r+0x1a>
-    2e36:	f7ff fe17 	bl	2a68 <__sinit>
-    2e3a:	4b7f      	ldr	r3, [pc, #508]	; (3038 <_vfiprintf_r+0x218>)
-    2e3c:	429f      	cmp	r7, r3
-    2e3e:	d15c      	bne.n	2efa <_vfiprintf_r+0xda>
-    2e40:	6877      	ldr	r7, [r6, #4]
-    2e42:	89bb      	ldrh	r3, [r7, #12]
-    2e44:	071b      	lsls	r3, r3, #28
-    2e46:	d562      	bpl.n	2f0e <_vfiprintf_r+0xee>
-    2e48:	693b      	ldr	r3, [r7, #16]
-    2e4a:	2b00      	cmp	r3, #0
-    2e4c:	d05f      	beq.n	2f0e <_vfiprintf_r+0xee>
-    2e4e:	2300      	movs	r3, #0
-    2e50:	ad06      	add	r5, sp, #24
-    2e52:	616b      	str	r3, [r5, #20]
-    2e54:	3320      	adds	r3, #32
-    2e56:	766b      	strb	r3, [r5, #25]
-    2e58:	3310      	adds	r3, #16
-    2e5a:	76ab      	strb	r3, [r5, #26]
-    2e5c:	9402      	str	r4, [sp, #8]
-    2e5e:	9c02      	ldr	r4, [sp, #8]
-    2e60:	7823      	ldrb	r3, [r4, #0]
-    2e62:	2b00      	cmp	r3, #0
-    2e64:	d15d      	bne.n	2f22 <_vfiprintf_r+0x102>
-    2e66:	9b02      	ldr	r3, [sp, #8]
-    2e68:	1ae3      	subs	r3, r4, r3
-    2e6a:	9304      	str	r3, [sp, #16]
-    2e6c:	d00d      	beq.n	2e8a <_vfiprintf_r+0x6a>
-    2e6e:	9b04      	ldr	r3, [sp, #16]
-    2e70:	9a02      	ldr	r2, [sp, #8]
-    2e72:	0039      	movs	r1, r7
-    2e74:	0030      	movs	r0, r6
-    2e76:	f7ff ffc0 	bl	2dfa <__sfputs_r>
-    2e7a:	1c43      	adds	r3, r0, #1
-    2e7c:	d100      	bne.n	2e80 <_vfiprintf_r+0x60>
-    2e7e:	e0cc      	b.n	301a <_vfiprintf_r+0x1fa>
-    2e80:	696a      	ldr	r2, [r5, #20]
-    2e82:	9b04      	ldr	r3, [sp, #16]
-    2e84:	4694      	mov	ip, r2
-    2e86:	4463      	add	r3, ip
-    2e88:	616b      	str	r3, [r5, #20]
-    2e8a:	7823      	ldrb	r3, [r4, #0]
-    2e8c:	2b00      	cmp	r3, #0
-    2e8e:	d100      	bne.n	2e92 <_vfiprintf_r+0x72>
-    2e90:	e0c3      	b.n	301a <_vfiprintf_r+0x1fa>
-    2e92:	2201      	movs	r2, #1
-    2e94:	2300      	movs	r3, #0
-    2e96:	4252      	negs	r2, r2
-    2e98:	606a      	str	r2, [r5, #4]
-    2e9a:	a902      	add	r1, sp, #8
-    2e9c:	3254      	adds	r2, #84	; 0x54
-    2e9e:	1852      	adds	r2, r2, r1
-    2ea0:	3401      	adds	r4, #1
-    2ea2:	602b      	str	r3, [r5, #0]
-    2ea4:	60eb      	str	r3, [r5, #12]
-    2ea6:	60ab      	str	r3, [r5, #8]
-    2ea8:	7013      	strb	r3, [r2, #0]
-    2eaa:	65ab      	str	r3, [r5, #88]	; 0x58
-    2eac:	7821      	ldrb	r1, [r4, #0]
-    2eae:	2205      	movs	r2, #5
-    2eb0:	4862      	ldr	r0, [pc, #392]	; (303c <_vfiprintf_r+0x21c>)
-    2eb2:	f000 fb15 	bl	34e0 <memchr>
-    2eb6:	1c63      	adds	r3, r4, #1
-    2eb8:	469c      	mov	ip, r3
-    2eba:	2800      	cmp	r0, #0
-    2ebc:	d135      	bne.n	2f2a <_vfiprintf_r+0x10a>
-    2ebe:	6829      	ldr	r1, [r5, #0]
-    2ec0:	06cb      	lsls	r3, r1, #27
-    2ec2:	d504      	bpl.n	2ece <_vfiprintf_r+0xae>
-    2ec4:	2353      	movs	r3, #83	; 0x53
-    2ec6:	aa02      	add	r2, sp, #8
-    2ec8:	3020      	adds	r0, #32
-    2eca:	189b      	adds	r3, r3, r2
-    2ecc:	7018      	strb	r0, [r3, #0]
-    2ece:	070b      	lsls	r3, r1, #28
-    2ed0:	d504      	bpl.n	2edc <_vfiprintf_r+0xbc>
-    2ed2:	2353      	movs	r3, #83	; 0x53
-    2ed4:	202b      	movs	r0, #43	; 0x2b
-    2ed6:	aa02      	add	r2, sp, #8
-    2ed8:	189b      	adds	r3, r3, r2
-    2eda:	7018      	strb	r0, [r3, #0]
-    2edc:	7823      	ldrb	r3, [r4, #0]
-    2ede:	2b2a      	cmp	r3, #42	; 0x2a
-    2ee0:	d02c      	beq.n	2f3c <_vfiprintf_r+0x11c>
-    2ee2:	2000      	movs	r0, #0
-    2ee4:	210a      	movs	r1, #10
-    2ee6:	9b09      	ldr	r3, [sp, #36]	; 0x24
-    2ee8:	7822      	ldrb	r2, [r4, #0]
-    2eea:	3a30      	subs	r2, #48	; 0x30
-    2eec:	2a09      	cmp	r2, #9
-    2eee:	d800      	bhi.n	2ef2 <_vfiprintf_r+0xd2>
-    2ef0:	e06b      	b.n	2fca <_vfiprintf_r+0x1aa>
-    2ef2:	2800      	cmp	r0, #0
-    2ef4:	d02a      	beq.n	2f4c <_vfiprintf_r+0x12c>
-    2ef6:	9309      	str	r3, [sp, #36]	; 0x24
-    2ef8:	e028      	b.n	2f4c <_vfiprintf_r+0x12c>
-    2efa:	4b51      	ldr	r3, [pc, #324]	; (3040 <_vfiprintf_r+0x220>)
-    2efc:	429f      	cmp	r7, r3
-    2efe:	d101      	bne.n	2f04 <_vfiprintf_r+0xe4>
-    2f00:	68b7      	ldr	r7, [r6, #8]
-    2f02:	e79e      	b.n	2e42 <_vfiprintf_r+0x22>
-    2f04:	4b4f      	ldr	r3, [pc, #316]	; (3044 <_vfiprintf_r+0x224>)
-    2f06:	429f      	cmp	r7, r3
-    2f08:	d19b      	bne.n	2e42 <_vfiprintf_r+0x22>
-    2f0a:	68f7      	ldr	r7, [r6, #12]
-    2f0c:	e799      	b.n	2e42 <_vfiprintf_r+0x22>
-    2f0e:	0039      	movs	r1, r7
-    2f10:	0030      	movs	r0, r6
-    2f12:	f7ff fc3b 	bl	278c <__swsetup_r>
-    2f16:	2800      	cmp	r0, #0
-    2f18:	d099      	beq.n	2e4e <_vfiprintf_r+0x2e>
-    2f1a:	2001      	movs	r0, #1
-    2f1c:	4240      	negs	r0, r0
-    2f1e:	b01f      	add	sp, #124	; 0x7c
-    2f20:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    2f22:	2b25      	cmp	r3, #37	; 0x25
-    2f24:	d09f      	beq.n	2e66 <_vfiprintf_r+0x46>
-    2f26:	3401      	adds	r4, #1
-    2f28:	e79a      	b.n	2e60 <_vfiprintf_r+0x40>
-    2f2a:	4b44      	ldr	r3, [pc, #272]	; (303c <_vfiprintf_r+0x21c>)
-    2f2c:	6829      	ldr	r1, [r5, #0]
-    2f2e:	1ac0      	subs	r0, r0, r3
-    2f30:	2301      	movs	r3, #1
-    2f32:	4083      	lsls	r3, r0
-    2f34:	430b      	orrs	r3, r1
-    2f36:	602b      	str	r3, [r5, #0]
-    2f38:	4664      	mov	r4, ip
-    2f3a:	e7b7      	b.n	2eac <_vfiprintf_r+0x8c>
-    2f3c:	9b05      	ldr	r3, [sp, #20]
-    2f3e:	1d18      	adds	r0, r3, #4
-    2f40:	681b      	ldr	r3, [r3, #0]
-    2f42:	9005      	str	r0, [sp, #20]
-    2f44:	2b00      	cmp	r3, #0
-    2f46:	db3a      	blt.n	2fbe <_vfiprintf_r+0x19e>
-    2f48:	9309      	str	r3, [sp, #36]	; 0x24
-    2f4a:	4664      	mov	r4, ip
-    2f4c:	7823      	ldrb	r3, [r4, #0]
-    2f4e:	2b2e      	cmp	r3, #46	; 0x2e
-    2f50:	d10b      	bne.n	2f6a <_vfiprintf_r+0x14a>
-    2f52:	7863      	ldrb	r3, [r4, #1]
-    2f54:	1c62      	adds	r2, r4, #1
-    2f56:	2b2a      	cmp	r3, #42	; 0x2a
-    2f58:	d13f      	bne.n	2fda <_vfiprintf_r+0x1ba>
-    2f5a:	9b05      	ldr	r3, [sp, #20]
-    2f5c:	3402      	adds	r4, #2
-    2f5e:	1d1a      	adds	r2, r3, #4
-    2f60:	681b      	ldr	r3, [r3, #0]
-    2f62:	9205      	str	r2, [sp, #20]
-    2f64:	2b00      	cmp	r3, #0
-    2f66:	db35      	blt.n	2fd4 <_vfiprintf_r+0x1b4>
-    2f68:	9307      	str	r3, [sp, #28]
-    2f6a:	7821      	ldrb	r1, [r4, #0]
-    2f6c:	2203      	movs	r2, #3
-    2f6e:	4836      	ldr	r0, [pc, #216]	; (3048 <_vfiprintf_r+0x228>)
-    2f70:	f000 fab6 	bl	34e0 <memchr>
-    2f74:	2800      	cmp	r0, #0
-    2f76:	d007      	beq.n	2f88 <_vfiprintf_r+0x168>
-    2f78:	4b33      	ldr	r3, [pc, #204]	; (3048 <_vfiprintf_r+0x228>)
-    2f7a:	682a      	ldr	r2, [r5, #0]
-    2f7c:	1ac0      	subs	r0, r0, r3
-    2f7e:	2340      	movs	r3, #64	; 0x40
-    2f80:	4083      	lsls	r3, r0
-    2f82:	4313      	orrs	r3, r2
-    2f84:	602b      	str	r3, [r5, #0]
-    2f86:	3401      	adds	r4, #1
-    2f88:	7821      	ldrb	r1, [r4, #0]
-    2f8a:	1c63      	adds	r3, r4, #1
-    2f8c:	2206      	movs	r2, #6
-    2f8e:	482f      	ldr	r0, [pc, #188]	; (304c <_vfiprintf_r+0x22c>)
-    2f90:	9302      	str	r3, [sp, #8]
-    2f92:	7629      	strb	r1, [r5, #24]
-    2f94:	f000 faa4 	bl	34e0 <memchr>
-    2f98:	2800      	cmp	r0, #0
-    2f9a:	d044      	beq.n	3026 <_vfiprintf_r+0x206>
-    2f9c:	4b2c      	ldr	r3, [pc, #176]	; (3050 <_vfiprintf_r+0x230>)
-    2f9e:	2b00      	cmp	r3, #0
-    2fa0:	d12f      	bne.n	3002 <_vfiprintf_r+0x1e2>
-    2fa2:	6829      	ldr	r1, [r5, #0]
-    2fa4:	9b05      	ldr	r3, [sp, #20]
-    2fa6:	2207      	movs	r2, #7
-    2fa8:	05c9      	lsls	r1, r1, #23
-    2faa:	d528      	bpl.n	2ffe <_vfiprintf_r+0x1de>
-    2fac:	189b      	adds	r3, r3, r2
-    2fae:	4393      	bics	r3, r2
-    2fb0:	3308      	adds	r3, #8
-    2fb2:	9305      	str	r3, [sp, #20]
-    2fb4:	696b      	ldr	r3, [r5, #20]
-    2fb6:	9a03      	ldr	r2, [sp, #12]
-    2fb8:	189b      	adds	r3, r3, r2
-    2fba:	616b      	str	r3, [r5, #20]
-    2fbc:	e74f      	b.n	2e5e <_vfiprintf_r+0x3e>
-    2fbe:	425b      	negs	r3, r3
-    2fc0:	60eb      	str	r3, [r5, #12]
-    2fc2:	2302      	movs	r3, #2
-    2fc4:	430b      	orrs	r3, r1
-    2fc6:	602b      	str	r3, [r5, #0]
-    2fc8:	e7bf      	b.n	2f4a <_vfiprintf_r+0x12a>
-    2fca:	434b      	muls	r3, r1
-    2fcc:	3401      	adds	r4, #1
-    2fce:	189b      	adds	r3, r3, r2
-    2fd0:	2001      	movs	r0, #1
-    2fd2:	e789      	b.n	2ee8 <_vfiprintf_r+0xc8>
-    2fd4:	2301      	movs	r3, #1
-    2fd6:	425b      	negs	r3, r3
-    2fd8:	e7c6      	b.n	2f68 <_vfiprintf_r+0x148>
-    2fda:	2300      	movs	r3, #0
-    2fdc:	0014      	movs	r4, r2
-    2fde:	200a      	movs	r0, #10
-    2fe0:	001a      	movs	r2, r3
-    2fe2:	606b      	str	r3, [r5, #4]
-    2fe4:	7821      	ldrb	r1, [r4, #0]
-    2fe6:	3930      	subs	r1, #48	; 0x30
-    2fe8:	2909      	cmp	r1, #9
-    2fea:	d903      	bls.n	2ff4 <_vfiprintf_r+0x1d4>
-    2fec:	2b00      	cmp	r3, #0
-    2fee:	d0bc      	beq.n	2f6a <_vfiprintf_r+0x14a>
-    2ff0:	9207      	str	r2, [sp, #28]
-    2ff2:	e7ba      	b.n	2f6a <_vfiprintf_r+0x14a>
-    2ff4:	4342      	muls	r2, r0
-    2ff6:	3401      	adds	r4, #1
-    2ff8:	1852      	adds	r2, r2, r1
-    2ffa:	2301      	movs	r3, #1
-    2ffc:	e7f2      	b.n	2fe4 <_vfiprintf_r+0x1c4>
-    2ffe:	3307      	adds	r3, #7
-    3000:	e7d5      	b.n	2fae <_vfiprintf_r+0x18e>
-    3002:	ab05      	add	r3, sp, #20
-    3004:	9300      	str	r3, [sp, #0]
-    3006:	003a      	movs	r2, r7
-    3008:	4b12      	ldr	r3, [pc, #72]	; (3054 <_vfiprintf_r+0x234>)
-    300a:	0029      	movs	r1, r5
-    300c:	0030      	movs	r0, r6
-    300e:	e000      	b.n	3012 <_vfiprintf_r+0x1f2>
-    3010:	bf00      	nop
-    3012:	9003      	str	r0, [sp, #12]
-    3014:	9b03      	ldr	r3, [sp, #12]
-    3016:	3301      	adds	r3, #1
-    3018:	d1cc      	bne.n	2fb4 <_vfiprintf_r+0x194>
-    301a:	89bb      	ldrh	r3, [r7, #12]
-    301c:	065b      	lsls	r3, r3, #25
-    301e:	d500      	bpl.n	3022 <_vfiprintf_r+0x202>
-    3020:	e77b      	b.n	2f1a <_vfiprintf_r+0xfa>
-    3022:	980b      	ldr	r0, [sp, #44]	; 0x2c
-    3024:	e77b      	b.n	2f1e <_vfiprintf_r+0xfe>
-    3026:	ab05      	add	r3, sp, #20
-    3028:	9300      	str	r3, [sp, #0]
-    302a:	003a      	movs	r2, r7
-    302c:	4b09      	ldr	r3, [pc, #36]	; (3054 <_vfiprintf_r+0x234>)
-    302e:	0029      	movs	r1, r5
-    3030:	0030      	movs	r0, r6
-    3032:	f000 f87f 	bl	3134 <_printf_i>
-    3036:	e7ec      	b.n	3012 <_vfiprintf_r+0x1f2>
-    3038:	00003654 	.word	0x00003654
-    303c:	00003694 	.word	0x00003694
-    3040:	00003674 	.word	0x00003674
-    3044:	00003634 	.word	0x00003634
-    3048:	0000369a 	.word	0x0000369a
-    304c:	0000369e 	.word	0x0000369e
-    3050:	00000000 	.word	0x00000000
-    3054:	00002dfb 	.word	0x00002dfb
-
-00003058 <_printf_common>:
-    3058:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
-    305a:	0015      	movs	r5, r2
-    305c:	9301      	str	r3, [sp, #4]
-    305e:	688a      	ldr	r2, [r1, #8]
-    3060:	690b      	ldr	r3, [r1, #16]
-    3062:	9000      	str	r0, [sp, #0]
-    3064:	000c      	movs	r4, r1
-    3066:	4293      	cmp	r3, r2
-    3068:	da00      	bge.n	306c <_printf_common+0x14>
-    306a:	0013      	movs	r3, r2
-    306c:	0022      	movs	r2, r4
-    306e:	602b      	str	r3, [r5, #0]
-    3070:	3243      	adds	r2, #67	; 0x43
-    3072:	7812      	ldrb	r2, [r2, #0]
-    3074:	2a00      	cmp	r2, #0
-    3076:	d001      	beq.n	307c <_printf_common+0x24>
-    3078:	3301      	adds	r3, #1
-    307a:	602b      	str	r3, [r5, #0]
-    307c:	6823      	ldr	r3, [r4, #0]
-    307e:	069b      	lsls	r3, r3, #26
-    3080:	d502      	bpl.n	3088 <_printf_common+0x30>
-    3082:	682b      	ldr	r3, [r5, #0]
-    3084:	3302      	adds	r3, #2
-    3086:	602b      	str	r3, [r5, #0]
-    3088:	2706      	movs	r7, #6
-    308a:	6823      	ldr	r3, [r4, #0]
-    308c:	401f      	ands	r7, r3
-    308e:	d027      	beq.n	30e0 <_printf_common+0x88>
-    3090:	0023      	movs	r3, r4
-    3092:	3343      	adds	r3, #67	; 0x43
-    3094:	781b      	ldrb	r3, [r3, #0]
-    3096:	1e5a      	subs	r2, r3, #1
-    3098:	4193      	sbcs	r3, r2
-    309a:	6822      	ldr	r2, [r4, #0]
-    309c:	0692      	lsls	r2, r2, #26
-    309e:	d430      	bmi.n	3102 <_printf_common+0xaa>
-    30a0:	0022      	movs	r2, r4
-    30a2:	9901      	ldr	r1, [sp, #4]
-    30a4:	3243      	adds	r2, #67	; 0x43
-    30a6:	9800      	ldr	r0, [sp, #0]
-    30a8:	9e08      	ldr	r6, [sp, #32]
-    30aa:	47b0      	blx	r6
-    30ac:	1c43      	adds	r3, r0, #1
-    30ae:	d025      	beq.n	30fc <_printf_common+0xa4>
-    30b0:	2306      	movs	r3, #6
-    30b2:	6820      	ldr	r0, [r4, #0]
-    30b4:	682a      	ldr	r2, [r5, #0]
-    30b6:	68e1      	ldr	r1, [r4, #12]
-    30b8:	4003      	ands	r3, r0
-    30ba:	2500      	movs	r5, #0
-    30bc:	2b04      	cmp	r3, #4
-    30be:	d103      	bne.n	30c8 <_printf_common+0x70>
-    30c0:	1a8d      	subs	r5, r1, r2
-    30c2:	43eb      	mvns	r3, r5
-    30c4:	17db      	asrs	r3, r3, #31
-    30c6:	401d      	ands	r5, r3
-    30c8:	68a3      	ldr	r3, [r4, #8]
-    30ca:	6922      	ldr	r2, [r4, #16]
-    30cc:	4293      	cmp	r3, r2
-    30ce:	dd01      	ble.n	30d4 <_printf_common+0x7c>
-    30d0:	1a9b      	subs	r3, r3, r2
-    30d2:	18ed      	adds	r5, r5, r3
-    30d4:	2700      	movs	r7, #0
-    30d6:	42bd      	cmp	r5, r7
-    30d8:	d120      	bne.n	311c <_printf_common+0xc4>
-    30da:	2000      	movs	r0, #0
-    30dc:	e010      	b.n	3100 <_printf_common+0xa8>
-    30de:	3701      	adds	r7, #1
-    30e0:	68e3      	ldr	r3, [r4, #12]
-    30e2:	682a      	ldr	r2, [r5, #0]
-    30e4:	1a9b      	subs	r3, r3, r2
-    30e6:	429f      	cmp	r7, r3
-    30e8:	dad2      	bge.n	3090 <_printf_common+0x38>
-    30ea:	0022      	movs	r2, r4
-    30ec:	2301      	movs	r3, #1
-    30ee:	3219      	adds	r2, #25
-    30f0:	9901      	ldr	r1, [sp, #4]
-    30f2:	9800      	ldr	r0, [sp, #0]
-    30f4:	9e08      	ldr	r6, [sp, #32]
-    30f6:	47b0      	blx	r6
-    30f8:	1c43      	adds	r3, r0, #1
-    30fa:	d1f0      	bne.n	30de <_printf_common+0x86>
-    30fc:	2001      	movs	r0, #1
-    30fe:	4240      	negs	r0, r0
-    3100:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
-    3102:	2030      	movs	r0, #48	; 0x30
-    3104:	18e1      	adds	r1, r4, r3
-    3106:	3143      	adds	r1, #67	; 0x43
-    3108:	7008      	strb	r0, [r1, #0]
-    310a:	0021      	movs	r1, r4
-    310c:	1c5a      	adds	r2, r3, #1
-    310e:	3145      	adds	r1, #69	; 0x45
-    3110:	7809      	ldrb	r1, [r1, #0]
-    3112:	18a2      	adds	r2, r4, r2
-    3114:	3243      	adds	r2, #67	; 0x43
-    3116:	3302      	adds	r3, #2
-    3118:	7011      	strb	r1, [r2, #0]
-    311a:	e7c1      	b.n	30a0 <_printf_common+0x48>
-    311c:	0022      	movs	r2, r4
-    311e:	2301      	movs	r3, #1
-    3120:	321a      	adds	r2, #26
-    3122:	9901      	ldr	r1, [sp, #4]
-    3124:	9800      	ldr	r0, [sp, #0]
-    3126:	9e08      	ldr	r6, [sp, #32]
-    3128:	47b0      	blx	r6
-    312a:	1c43      	adds	r3, r0, #1
-    312c:	d0e6      	beq.n	30fc <_printf_common+0xa4>
-    312e:	3701      	adds	r7, #1
-    3130:	e7d1      	b.n	30d6 <_printf_common+0x7e>
-	...
-
-00003134 <_printf_i>:
-    3134:	b5f0      	push	{r4, r5, r6, r7, lr}
-    3136:	b08b      	sub	sp, #44	; 0x2c
-    3138:	9206      	str	r2, [sp, #24]
-    313a:	000a      	movs	r2, r1
-    313c:	3243      	adds	r2, #67	; 0x43
-    313e:	9307      	str	r3, [sp, #28]
-    3140:	9005      	str	r0, [sp, #20]
-    3142:	9204      	str	r2, [sp, #16]
-    3144:	7e0a      	ldrb	r2, [r1, #24]
-    3146:	000c      	movs	r4, r1
-    3148:	9b10      	ldr	r3, [sp, #64]	; 0x40
-    314a:	2a6e      	cmp	r2, #110	; 0x6e
-    314c:	d100      	bne.n	3150 <_printf_i+0x1c>
-    314e:	e08f      	b.n	3270 <_printf_i+0x13c>
-    3150:	d817      	bhi.n	3182 <_printf_i+0x4e>
-    3152:	2a63      	cmp	r2, #99	; 0x63
-    3154:	d02c      	beq.n	31b0 <_printf_i+0x7c>
-    3156:	d808      	bhi.n	316a <_printf_i+0x36>
-    3158:	2a00      	cmp	r2, #0
-    315a:	d100      	bne.n	315e <_printf_i+0x2a>
-    315c:	e099      	b.n	3292 <_printf_i+0x15e>
-    315e:	2a58      	cmp	r2, #88	; 0x58
-    3160:	d054      	beq.n	320c <_printf_i+0xd8>
-    3162:	0026      	movs	r6, r4
-    3164:	3642      	adds	r6, #66	; 0x42
-    3166:	7032      	strb	r2, [r6, #0]
-    3168:	e029      	b.n	31be <_printf_i+0x8a>
-    316a:	2a64      	cmp	r2, #100	; 0x64
-    316c:	d001      	beq.n	3172 <_printf_i+0x3e>
-    316e:	2a69      	cmp	r2, #105	; 0x69
-    3170:	d1f7      	bne.n	3162 <_printf_i+0x2e>
-    3172:	6821      	ldr	r1, [r4, #0]
-    3174:	681a      	ldr	r2, [r3, #0]
-    3176:	0608      	lsls	r0, r1, #24
-    3178:	d523      	bpl.n	31c2 <_printf_i+0x8e>
-    317a:	1d11      	adds	r1, r2, #4
-    317c:	6019      	str	r1, [r3, #0]
-    317e:	6815      	ldr	r5, [r2, #0]
-    3180:	e025      	b.n	31ce <_printf_i+0x9a>
-    3182:	2a73      	cmp	r2, #115	; 0x73
-    3184:	d100      	bne.n	3188 <_printf_i+0x54>
-    3186:	e088      	b.n	329a <_printf_i+0x166>
-    3188:	d808      	bhi.n	319c <_printf_i+0x68>
-    318a:	2a6f      	cmp	r2, #111	; 0x6f
-    318c:	d029      	beq.n	31e2 <_printf_i+0xae>
-    318e:	2a70      	cmp	r2, #112	; 0x70
-    3190:	d1e7      	bne.n	3162 <_printf_i+0x2e>
-    3192:	2220      	movs	r2, #32
-    3194:	6809      	ldr	r1, [r1, #0]
-    3196:	430a      	orrs	r2, r1
-    3198:	6022      	str	r2, [r4, #0]
-    319a:	e003      	b.n	31a4 <_printf_i+0x70>
-    319c:	2a75      	cmp	r2, #117	; 0x75
-    319e:	d020      	beq.n	31e2 <_printf_i+0xae>
-    31a0:	2a78      	cmp	r2, #120	; 0x78
-    31a2:	d1de      	bne.n	3162 <_printf_i+0x2e>
-    31a4:	0022      	movs	r2, r4
-    31a6:	2178      	movs	r1, #120	; 0x78
-    31a8:	3245      	adds	r2, #69	; 0x45
-    31aa:	7011      	strb	r1, [r2, #0]
-    31ac:	4a6c      	ldr	r2, [pc, #432]	; (3360 <_printf_i+0x22c>)
-    31ae:	e030      	b.n	3212 <_printf_i+0xde>
-    31b0:	000e      	movs	r6, r1
-    31b2:	681a      	ldr	r2, [r3, #0]
-    31b4:	3642      	adds	r6, #66	; 0x42
-    31b6:	1d11      	adds	r1, r2, #4
-    31b8:	6019      	str	r1, [r3, #0]
-    31ba:	6813      	ldr	r3, [r2, #0]
-    31bc:	7033      	strb	r3, [r6, #0]
-    31be:	2301      	movs	r3, #1
-    31c0:	e079      	b.n	32b6 <_printf_i+0x182>
-    31c2:	0649      	lsls	r1, r1, #25
-    31c4:	d5d9      	bpl.n	317a <_printf_i+0x46>
-    31c6:	1d11      	adds	r1, r2, #4
-    31c8:	6019      	str	r1, [r3, #0]
-    31ca:	2300      	movs	r3, #0
-    31cc:	5ed5      	ldrsh	r5, [r2, r3]
-    31ce:	2d00      	cmp	r5, #0
-    31d0:	da03      	bge.n	31da <_printf_i+0xa6>
-    31d2:	232d      	movs	r3, #45	; 0x2d
-    31d4:	9a04      	ldr	r2, [sp, #16]
-    31d6:	426d      	negs	r5, r5
-    31d8:	7013      	strb	r3, [r2, #0]
-    31da:	4b62      	ldr	r3, [pc, #392]	; (3364 <_printf_i+0x230>)
-    31dc:	270a      	movs	r7, #10
-    31de:	9303      	str	r3, [sp, #12]
-    31e0:	e02f      	b.n	3242 <_printf_i+0x10e>
-    31e2:	6820      	ldr	r0, [r4, #0]
-    31e4:	6819      	ldr	r1, [r3, #0]
-    31e6:	0605      	lsls	r5, r0, #24
-    31e8:	d503      	bpl.n	31f2 <_printf_i+0xbe>
-    31ea:	1d08      	adds	r0, r1, #4
-    31ec:	6018      	str	r0, [r3, #0]
-    31ee:	680d      	ldr	r5, [r1, #0]
-    31f0:	e005      	b.n	31fe <_printf_i+0xca>
-    31f2:	0640      	lsls	r0, r0, #25
-    31f4:	d5f9      	bpl.n	31ea <_printf_i+0xb6>
-    31f6:	680d      	ldr	r5, [r1, #0]
-    31f8:	1d08      	adds	r0, r1, #4
-    31fa:	6018      	str	r0, [r3, #0]
-    31fc:	b2ad      	uxth	r5, r5
-    31fe:	4b59      	ldr	r3, [pc, #356]	; (3364 <_printf_i+0x230>)
-    3200:	2708      	movs	r7, #8
-    3202:	9303      	str	r3, [sp, #12]
-    3204:	2a6f      	cmp	r2, #111	; 0x6f
-    3206:	d018      	beq.n	323a <_printf_i+0x106>
-    3208:	270a      	movs	r7, #10
-    320a:	e016      	b.n	323a <_printf_i+0x106>
-    320c:	3145      	adds	r1, #69	; 0x45
-    320e:	700a      	strb	r2, [r1, #0]
-    3210:	4a54      	ldr	r2, [pc, #336]	; (3364 <_printf_i+0x230>)
-    3212:	9203      	str	r2, [sp, #12]
-    3214:	681a      	ldr	r2, [r3, #0]
-    3216:	6821      	ldr	r1, [r4, #0]
-    3218:	1d10      	adds	r0, r2, #4
-    321a:	6018      	str	r0, [r3, #0]
-    321c:	6815      	ldr	r5, [r2, #0]
-    321e:	0608      	lsls	r0, r1, #24
-    3220:	d522      	bpl.n	3268 <_printf_i+0x134>
-    3222:	07cb      	lsls	r3, r1, #31
-    3224:	d502      	bpl.n	322c <_printf_i+0xf8>
-    3226:	2320      	movs	r3, #32
-    3228:	4319      	orrs	r1, r3
-    322a:	6021      	str	r1, [r4, #0]
-    322c:	2710      	movs	r7, #16
-    322e:	2d00      	cmp	r5, #0
-    3230:	d103      	bne.n	323a <_printf_i+0x106>
-    3232:	2320      	movs	r3, #32
-    3234:	6822      	ldr	r2, [r4, #0]
-    3236:	439a      	bics	r2, r3
-    3238:	6022      	str	r2, [r4, #0]
-    323a:	0023      	movs	r3, r4
-    323c:	2200      	movs	r2, #0
-    323e:	3343      	adds	r3, #67	; 0x43
-    3240:	701a      	strb	r2, [r3, #0]
-    3242:	6863      	ldr	r3, [r4, #4]
-    3244:	60a3      	str	r3, [r4, #8]
-    3246:	2b00      	cmp	r3, #0
-    3248:	db5c      	blt.n	3304 <_printf_i+0x1d0>
-    324a:	2204      	movs	r2, #4
-    324c:	6821      	ldr	r1, [r4, #0]
-    324e:	4391      	bics	r1, r2
-    3250:	6021      	str	r1, [r4, #0]
-    3252:	2d00      	cmp	r5, #0
-    3254:	d158      	bne.n	3308 <_printf_i+0x1d4>
-    3256:	9e04      	ldr	r6, [sp, #16]
-    3258:	2b00      	cmp	r3, #0
-    325a:	d064      	beq.n	3326 <_printf_i+0x1f2>
-    325c:	0026      	movs	r6, r4
-    325e:	9b03      	ldr	r3, [sp, #12]
-    3260:	3642      	adds	r6, #66	; 0x42
-    3262:	781b      	ldrb	r3, [r3, #0]
-    3264:	7033      	strb	r3, [r6, #0]
-    3266:	e05e      	b.n	3326 <_printf_i+0x1f2>
-    3268:	0648      	lsls	r0, r1, #25
-    326a:	d5da      	bpl.n	3222 <_printf_i+0xee>
-    326c:	b2ad      	uxth	r5, r5
-    326e:	e7d8      	b.n	3222 <_printf_i+0xee>
-    3270:	6809      	ldr	r1, [r1, #0]
-    3272:	681a      	ldr	r2, [r3, #0]
-    3274:	0608      	lsls	r0, r1, #24
-    3276:	d505      	bpl.n	3284 <_printf_i+0x150>
-    3278:	1d11      	adds	r1, r2, #4
-    327a:	6019      	str	r1, [r3, #0]
-    327c:	6813      	ldr	r3, [r2, #0]
-    327e:	6962      	ldr	r2, [r4, #20]
-    3280:	601a      	str	r2, [r3, #0]
-    3282:	e006      	b.n	3292 <_printf_i+0x15e>
-    3284:	0649      	lsls	r1, r1, #25
-    3286:	d5f7      	bpl.n	3278 <_printf_i+0x144>
-    3288:	1d11      	adds	r1, r2, #4
-    328a:	6019      	str	r1, [r3, #0]
-    328c:	6813      	ldr	r3, [r2, #0]
-    328e:	8aa2      	ldrh	r2, [r4, #20]
-    3290:	801a      	strh	r2, [r3, #0]
-    3292:	2300      	movs	r3, #0
-    3294:	9e04      	ldr	r6, [sp, #16]
-    3296:	6123      	str	r3, [r4, #16]
-    3298:	e054      	b.n	3344 <_printf_i+0x210>
-    329a:	681a      	ldr	r2, [r3, #0]
-    329c:	1d11      	adds	r1, r2, #4
-    329e:	6019      	str	r1, [r3, #0]
-    32a0:	6816      	ldr	r6, [r2, #0]
-    32a2:	2100      	movs	r1, #0
-    32a4:	6862      	ldr	r2, [r4, #4]
-    32a6:	0030      	movs	r0, r6
-    32a8:	f000 f91a 	bl	34e0 <memchr>
-    32ac:	2800      	cmp	r0, #0
-    32ae:	d001      	beq.n	32b4 <_printf_i+0x180>
-    32b0:	1b80      	subs	r0, r0, r6
-    32b2:	6060      	str	r0, [r4, #4]
-    32b4:	6863      	ldr	r3, [r4, #4]
-    32b6:	6123      	str	r3, [r4, #16]
-    32b8:	2300      	movs	r3, #0
-    32ba:	9a04      	ldr	r2, [sp, #16]
-    32bc:	7013      	strb	r3, [r2, #0]
-    32be:	e041      	b.n	3344 <_printf_i+0x210>
-    32c0:	6923      	ldr	r3, [r4, #16]
-    32c2:	0032      	movs	r2, r6
-    32c4:	9906      	ldr	r1, [sp, #24]
-    32c6:	9805      	ldr	r0, [sp, #20]
-    32c8:	9d07      	ldr	r5, [sp, #28]
-    32ca:	47a8      	blx	r5
-    32cc:	1c43      	adds	r3, r0, #1
-    32ce:	d043      	beq.n	3358 <_printf_i+0x224>
-    32d0:	6823      	ldr	r3, [r4, #0]
-    32d2:	2500      	movs	r5, #0
-    32d4:	079b      	lsls	r3, r3, #30
-    32d6:	d40f      	bmi.n	32f8 <_printf_i+0x1c4>
-    32d8:	9b09      	ldr	r3, [sp, #36]	; 0x24
-    32da:	68e0      	ldr	r0, [r4, #12]
-    32dc:	4298      	cmp	r0, r3
-    32de:	da3d      	bge.n	335c <_printf_i+0x228>
-    32e0:	0018      	movs	r0, r3
-    32e2:	e03b      	b.n	335c <_printf_i+0x228>
-    32e4:	0022      	movs	r2, r4
-    32e6:	2301      	movs	r3, #1
-    32e8:	3219      	adds	r2, #25
-    32ea:	9906      	ldr	r1, [sp, #24]
-    32ec:	9805      	ldr	r0, [sp, #20]
-    32ee:	9e07      	ldr	r6, [sp, #28]
-    32f0:	47b0      	blx	r6
-    32f2:	1c43      	adds	r3, r0, #1
-    32f4:	d030      	beq.n	3358 <_printf_i+0x224>
-    32f6:	3501      	adds	r5, #1
-    32f8:	68e3      	ldr	r3, [r4, #12]
-    32fa:	9a09      	ldr	r2, [sp, #36]	; 0x24
-    32fc:	1a9b      	subs	r3, r3, r2
-    32fe:	429d      	cmp	r5, r3
-    3300:	dbf0      	blt.n	32e4 <_printf_i+0x1b0>
-    3302:	e7e9      	b.n	32d8 <_printf_i+0x1a4>
-    3304:	2d00      	cmp	r5, #0
-    3306:	d0a9      	beq.n	325c <_printf_i+0x128>
-    3308:	9e04      	ldr	r6, [sp, #16]
-    330a:	0028      	movs	r0, r5
-    330c:	0039      	movs	r1, r7
-    330e:	f7fe fcab 	bl	1c68 <__aeabi_uidivmod>
-    3312:	9b03      	ldr	r3, [sp, #12]
-    3314:	3e01      	subs	r6, #1
-    3316:	5c5b      	ldrb	r3, [r3, r1]
-    3318:	0028      	movs	r0, r5
-    331a:	7033      	strb	r3, [r6, #0]
-    331c:	0039      	movs	r1, r7
-    331e:	f7fe fc1d 	bl	1b5c <__udivsi3>
-    3322:	1e05      	subs	r5, r0, #0
-    3324:	d1f1      	bne.n	330a <_printf_i+0x1d6>
-    3326:	2f08      	cmp	r7, #8
-    3328:	d109      	bne.n	333e <_printf_i+0x20a>
-    332a:	6823      	ldr	r3, [r4, #0]
-    332c:	07db      	lsls	r3, r3, #31
-    332e:	d506      	bpl.n	333e <_printf_i+0x20a>
-    3330:	6863      	ldr	r3, [r4, #4]
-    3332:	6922      	ldr	r2, [r4, #16]
-    3334:	4293      	cmp	r3, r2
-    3336:	dc02      	bgt.n	333e <_printf_i+0x20a>
-    3338:	2330      	movs	r3, #48	; 0x30
-    333a:	3e01      	subs	r6, #1
-    333c:	7033      	strb	r3, [r6, #0]
-    333e:	9b04      	ldr	r3, [sp, #16]
-    3340:	1b9b      	subs	r3, r3, r6
-    3342:	6123      	str	r3, [r4, #16]
-    3344:	9b07      	ldr	r3, [sp, #28]
-    3346:	aa09      	add	r2, sp, #36	; 0x24
-    3348:	9300      	str	r3, [sp, #0]
-    334a:	0021      	movs	r1, r4
-    334c:	9b06      	ldr	r3, [sp, #24]
-    334e:	9805      	ldr	r0, [sp, #20]
-    3350:	f7ff fe82 	bl	3058 <_printf_common>
-    3354:	1c43      	adds	r3, r0, #1
-    3356:	d1b3      	bne.n	32c0 <_printf_i+0x18c>
-    3358:	2001      	movs	r0, #1
-    335a:	4240      	negs	r0, r0
-    335c:	b00b      	add	sp, #44	; 0x2c
-    335e:	bdf0      	pop	{r4, r5, r6, r7, pc}
-    3360:	000036b6 	.word	0x000036b6
-    3364:	000036a5 	.word	0x000036a5
-
-00003368 <_sbrk_r>:
-    3368:	2300      	movs	r3, #0
-    336a:	b570      	push	{r4, r5, r6, lr}
-    336c:	4c06      	ldr	r4, [pc, #24]	; (3388 <_sbrk_r+0x20>)
-    336e:	0005      	movs	r5, r0
-    3370:	0008      	movs	r0, r1
-    3372:	6023      	str	r3, [r4, #0]
-    3374:	f7fe fb62 	bl	1a3c <_sbrk>
-    3378:	1c43      	adds	r3, r0, #1
-    337a:	d103      	bne.n	3384 <_sbrk_r+0x1c>
-    337c:	6823      	ldr	r3, [r4, #0]
-    337e:	2b00      	cmp	r3, #0
-    3380:	d000      	beq.n	3384 <_sbrk_r+0x1c>
-    3382:	602b      	str	r3, [r5, #0]
-    3384:	bd70      	pop	{r4, r5, r6, pc}
-    3386:	46c0      	nop			; (mov r8, r8)
-    3388:	2000029c 	.word	0x2000029c
-
-0000338c <__sread>:
-    338c:	b570      	push	{r4, r5, r6, lr}
-    338e:	000c      	movs	r4, r1
-    3390:	250e      	movs	r5, #14
-    3392:	5f49      	ldrsh	r1, [r1, r5]
-    3394:	f000 f8b2 	bl	34fc <_read_r>
-    3398:	2800      	cmp	r0, #0
-    339a:	db03      	blt.n	33a4 <__sread+0x18>
-    339c:	6d63      	ldr	r3, [r4, #84]	; 0x54
-    339e:	181b      	adds	r3, r3, r0
-    33a0:	6563      	str	r3, [r4, #84]	; 0x54
-    33a2:	bd70      	pop	{r4, r5, r6, pc}
-    33a4:	89a3      	ldrh	r3, [r4, #12]
-    33a6:	4a02      	ldr	r2, [pc, #8]	; (33b0 <__sread+0x24>)
-    33a8:	4013      	ands	r3, r2
-    33aa:	81a3      	strh	r3, [r4, #12]
-    33ac:	e7f9      	b.n	33a2 <__sread+0x16>
-    33ae:	46c0      	nop			; (mov r8, r8)
-    33b0:	ffffefff 	.word	0xffffefff
-
-000033b4 <__swrite>:
-    33b4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    33b6:	001f      	movs	r7, r3
-    33b8:	898b      	ldrh	r3, [r1, #12]
-    33ba:	0005      	movs	r5, r0
-    33bc:	000c      	movs	r4, r1
-    33be:	0016      	movs	r6, r2
-    33c0:	05db      	lsls	r3, r3, #23
-    33c2:	d505      	bpl.n	33d0 <__swrite+0x1c>
-    33c4:	230e      	movs	r3, #14
-    33c6:	5ec9      	ldrsh	r1, [r1, r3]
-    33c8:	2200      	movs	r2, #0
-    33ca:	2302      	movs	r3, #2
-    33cc:	f000 f874 	bl	34b8 <_lseek_r>
-    33d0:	89a3      	ldrh	r3, [r4, #12]
-    33d2:	4a05      	ldr	r2, [pc, #20]	; (33e8 <__swrite+0x34>)
-    33d4:	0028      	movs	r0, r5
-    33d6:	4013      	ands	r3, r2
-    33d8:	81a3      	strh	r3, [r4, #12]
-    33da:	0032      	movs	r2, r6
-    33dc:	230e      	movs	r3, #14
-    33de:	5ee1      	ldrsh	r1, [r4, r3]
-    33e0:	003b      	movs	r3, r7
-    33e2:	f000 f81f 	bl	3424 <_write_r>
-    33e6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
-    33e8:	ffffefff 	.word	0xffffefff
-
-000033ec <__sseek>:
-    33ec:	b570      	push	{r4, r5, r6, lr}
-    33ee:	000c      	movs	r4, r1
-    33f0:	250e      	movs	r5, #14
-    33f2:	5f49      	ldrsh	r1, [r1, r5]
-    33f4:	f000 f860 	bl	34b8 <_lseek_r>
-    33f8:	89a3      	ldrh	r3, [r4, #12]
-    33fa:	1c42      	adds	r2, r0, #1
-    33fc:	d103      	bne.n	3406 <__sseek+0x1a>
-    33fe:	4a05      	ldr	r2, [pc, #20]	; (3414 <__sseek+0x28>)
-    3400:	4013      	ands	r3, r2
-    3402:	81a3      	strh	r3, [r4, #12]
-    3404:	bd70      	pop	{r4, r5, r6, pc}
-    3406:	2280      	movs	r2, #128	; 0x80
-    3408:	0152      	lsls	r2, r2, #5
-    340a:	4313      	orrs	r3, r2
-    340c:	81a3      	strh	r3, [r4, #12]
-    340e:	6560      	str	r0, [r4, #84]	; 0x54
-    3410:	e7f8      	b.n	3404 <__sseek+0x18>
-    3412:	46c0      	nop			; (mov r8, r8)
-    3414:	ffffefff 	.word	0xffffefff
-
-00003418 <__sclose>:
-    3418:	b510      	push	{r4, lr}
-    341a:	230e      	movs	r3, #14
-    341c:	5ec9      	ldrsh	r1, [r1, r3]
-    341e:	f000 f815 	bl	344c <_close_r>
-    3422:	bd10      	pop	{r4, pc}
-
-00003424 <_write_r>:
-    3424:	b570      	push	{r4, r5, r6, lr}
-    3426:	0005      	movs	r5, r0
-    3428:	0008      	movs	r0, r1
-    342a:	0011      	movs	r1, r2
-    342c:	2200      	movs	r2, #0
-    342e:	4c06      	ldr	r4, [pc, #24]	; (3448 <_write_r+0x24>)
-    3430:	6022      	str	r2, [r4, #0]
-    3432:	001a      	movs	r2, r3
-    3434:	f7fd fb56 	bl	ae4 <_write>
-    3438:	1c43      	adds	r3, r0, #1
-    343a:	d103      	bne.n	3444 <_write_r+0x20>
-    343c:	6823      	ldr	r3, [r4, #0]
-    343e:	2b00      	cmp	r3, #0
-    3440:	d000      	beq.n	3444 <_write_r+0x20>
-    3442:	602b      	str	r3, [r5, #0]
-    3444:	bd70      	pop	{r4, r5, r6, pc}
-    3446:	46c0      	nop			; (mov r8, r8)
-    3448:	2000029c 	.word	0x2000029c
-
-0000344c <_close_r>:
-    344c:	2300      	movs	r3, #0
-    344e:	b570      	push	{r4, r5, r6, lr}
-    3450:	4c06      	ldr	r4, [pc, #24]	; (346c <_close_r+0x20>)
-    3452:	0005      	movs	r5, r0
-    3454:	0008      	movs	r0, r1
-    3456:	6023      	str	r3, [r4, #0]
-    3458:	f7fe fb00 	bl	1a5c <_close>
-    345c:	1c43      	adds	r3, r0, #1
-    345e:	d103      	bne.n	3468 <_close_r+0x1c>
-    3460:	6823      	ldr	r3, [r4, #0]
-    3462:	2b00      	cmp	r3, #0
-    3464:	d000      	beq.n	3468 <_close_r+0x1c>
-    3466:	602b      	str	r3, [r5, #0]
-    3468:	bd70      	pop	{r4, r5, r6, pc}
-    346a:	46c0      	nop			; (mov r8, r8)
-    346c:	2000029c 	.word	0x2000029c
-
-00003470 <_fstat_r>:
-    3470:	2300      	movs	r3, #0
-    3472:	b570      	push	{r4, r5, r6, lr}
-    3474:	4c06      	ldr	r4, [pc, #24]	; (3490 <_fstat_r+0x20>)
-    3476:	0005      	movs	r5, r0
-    3478:	0008      	movs	r0, r1
-    347a:	0011      	movs	r1, r2
-    347c:	6023      	str	r3, [r4, #0]
-    347e:	f7fe faf0 	bl	1a62 <_fstat>
-    3482:	1c43      	adds	r3, r0, #1
-    3484:	d103      	bne.n	348e <_fstat_r+0x1e>
-    3486:	6823      	ldr	r3, [r4, #0]
-    3488:	2b00      	cmp	r3, #0
-    348a:	d000      	beq.n	348e <_fstat_r+0x1e>
-    348c:	602b      	str	r3, [r5, #0]
-    348e:	bd70      	pop	{r4, r5, r6, pc}
-    3490:	2000029c 	.word	0x2000029c
-
-00003494 <_isatty_r>:
-    3494:	2300      	movs	r3, #0
-    3496:	b570      	push	{r4, r5, r6, lr}
-    3498:	4c06      	ldr	r4, [pc, #24]	; (34b4 <_isatty_r+0x20>)
-    349a:	0005      	movs	r5, r0
-    349c:	0008      	movs	r0, r1
-    349e:	6023      	str	r3, [r4, #0]
-    34a0:	f7fe fae4 	bl	1a6c <_isatty>
-    34a4:	1c43      	adds	r3, r0, #1
-    34a6:	d103      	bne.n	34b0 <_isatty_r+0x1c>
-    34a8:	6823      	ldr	r3, [r4, #0]
-    34aa:	2b00      	cmp	r3, #0
-    34ac:	d000      	beq.n	34b0 <_isatty_r+0x1c>
-    34ae:	602b      	str	r3, [r5, #0]
-    34b0:	bd70      	pop	{r4, r5, r6, pc}
-    34b2:	46c0      	nop			; (mov r8, r8)
-    34b4:	2000029c 	.word	0x2000029c
-
-000034b8 <_lseek_r>:
-    34b8:	b570      	push	{r4, r5, r6, lr}
-    34ba:	0005      	movs	r5, r0
-    34bc:	0008      	movs	r0, r1
-    34be:	0011      	movs	r1, r2
-    34c0:	2200      	movs	r2, #0
-    34c2:	4c06      	ldr	r4, [pc, #24]	; (34dc <_lseek_r+0x24>)
-    34c4:	6022      	str	r2, [r4, #0]
-    34c6:	001a      	movs	r2, r3
-    34c8:	f7fe fad2 	bl	1a70 <_lseek>
-    34cc:	1c43      	adds	r3, r0, #1
-    34ce:	d103      	bne.n	34d8 <_lseek_r+0x20>
-    34d0:	6823      	ldr	r3, [r4, #0]
-    34d2:	2b00      	cmp	r3, #0
-    34d4:	d000      	beq.n	34d8 <_lseek_r+0x20>
-    34d6:	602b      	str	r3, [r5, #0]
-    34d8:	bd70      	pop	{r4, r5, r6, pc}
-    34da:	46c0      	nop			; (mov r8, r8)
-    34dc:	2000029c 	.word	0x2000029c
-
-000034e0 <memchr>:
-    34e0:	b2c9      	uxtb	r1, r1
-    34e2:	1882      	adds	r2, r0, r2
-    34e4:	4290      	cmp	r0, r2
-    34e6:	d101      	bne.n	34ec <memchr+0xc>
-    34e8:	2000      	movs	r0, #0
-    34ea:	4770      	bx	lr
-    34ec:	7803      	ldrb	r3, [r0, #0]
-    34ee:	428b      	cmp	r3, r1
-    34f0:	d0fb      	beq.n	34ea <memchr+0xa>
-    34f2:	3001      	adds	r0, #1
-    34f4:	e7f6      	b.n	34e4 <memchr+0x4>
-
-000034f6 <__malloc_lock>:
-    34f6:	4770      	bx	lr
-
-000034f8 <__malloc_unlock>:
-    34f8:	4770      	bx	lr
-	...
-
-000034fc <_read_r>:
-    34fc:	b570      	push	{r4, r5, r6, lr}
-    34fe:	0005      	movs	r5, r0
-    3500:	0008      	movs	r0, r1
-    3502:	0011      	movs	r1, r2
-    3504:	2200      	movs	r2, #0
-    3506:	4c06      	ldr	r4, [pc, #24]	; (3520 <_read_r+0x24>)
-    3508:	6022      	str	r2, [r4, #0]
-    350a:	001a      	movs	r2, r3
-    350c:	f7fd face 	bl	aac <_read>
-    3510:	1c43      	adds	r3, r0, #1
-    3512:	d103      	bne.n	351c <_read_r+0x20>
-    3514:	6823      	ldr	r3, [r4, #0]
-    3516:	2b00      	cmp	r3, #0
-    3518:	d000      	beq.n	351c <_read_r+0x20>
-    351a:	602b      	str	r3, [r5, #0]
-    351c:	bd70      	pop	{r4, r5, r6, pc}
-    351e:	46c0      	nop			; (mov r8, r8)
-    3520:	2000029c 	.word	0x2000029c
-    3524:	00000002 	.word	0x00000002
-    3528:	00000003 	.word	0x00000003
-    352c:	00000028 	.word	0x00000028
-    3530:	00000029 	.word	0x00000029
-    3534:	00000004 	.word	0x00000004
-    3538:	00000005 	.word	0x00000005
-    353c:	00000006 	.word	0x00000006
-    3540:	00000007 	.word	0x00000007
-    3544:	00000020 	.word	0x00000020
-    3548:	00000021 	.word	0x00000021
-    354c:	00000022 	.word	0x00000022
-    3550:	00000023 	.word	0x00000023
-    3554:	00000024 	.word	0x00000024
-    3558:	00000025 	.word	0x00000025
-    355c:	00000026 	.word	0x00000026
-    3560:	00000027 	.word	0x00000027
-    3564:	00000008 	.word	0x00000008
-    3568:	00000009 	.word	0x00000009
-    356c:	0000000a 	.word	0x0000000a
-    3570:	0000000b 	.word	0x0000000b
-    3574:	42000800 	.word	0x42000800
-    3578:	42000c00 	.word	0x42000c00
-    357c:	42001000 	.word	0x42001000
-    3580:	42001400 	.word	0x42001400
-    3584:	42001800 	.word	0x42001800
-    3588:	42001c00 	.word	0x42001c00
-    358c:	325b6325 	.word	0x325b6325
-    3590:	6325004a 	.word	0x6325004a
-    3594:	2000755b 	.word	0x2000755b
-    3598:	5b1b2d2d 	.word	0x5b1b2d2d
-    359c:	313b3133 	.word	0x313b3133
-    35a0:	6550206d 	.word	0x6550206d
-    35a4:	6975676e 	.word	0x6975676e
-    35a8:	1b73276e 	.word	0x1b73276e
-    35ac:	3b3b305b 	.word	0x3b3b305b
-    35b0:	206d3034 	.word	0x206d3034
-    35b4:	444d4153 	.word	0x444d4153
-    35b8:	41203132 	.word	0x41203132
-    35bc:	44204344 	.word	0x44204344
-    35c0:	206f6d65 	.word	0x206f6d65
-    35c4:	6e697375 	.word	0x6e697375
-    35c8:	4d442067 	.word	0x4d442067
-    35cc:	2d2d2041 	.word	0x2d2d2041
-    35d0:	56000d20 	.word	0x56000d20
-    35d4:	61746c6f 	.word	0x61746c6f
-    35d8:	203a6567 	.word	0x203a6567
-    35dc:	252e6425 	.word	0x252e6425
-    35e0:	00643330 	.word	0x00643330
-    35e4:	325b6325 	.word	0x325b6325
-    35e8:	6325004b 	.word	0x6325004b
-    35ec:	0042315b 	.word	0x0042315b
-    35f0:	00001e0c 	.word	0x00001e0c
-    35f4:	00001d5c 	.word	0x00001d5c
-    35f8:	00001d5c 	.word	0x00001d5c
-    35fc:	00001d5a 	.word	0x00001d5a
-    3600:	00001dfe 	.word	0x00001dfe
-    3604:	00001dfe 	.word	0x00001dfe
-    3608:	00001df4 	.word	0x00001df4
-    360c:	00001d5a 	.word	0x00001d5a
-    3610:	00001dfe 	.word	0x00001dfe
-    3614:	00001df4 	.word	0x00001df4
-    3618:	00001dfe 	.word	0x00001dfe
-    361c:	00001d5a 	.word	0x00001d5a
-    3620:	00001e04 	.word	0x00001e04
-    3624:	00001e04 	.word	0x00001e04
-    3628:	00001e04 	.word	0x00001e04
-    362c:	00001e94 	.word	0x00001e94
-
-00003630 <_global_impure_ptr>:
-    3630:	2000001c                                ... 
-
-00003634 <__sf_fake_stderr>:
-	...
-
-00003654 <__sf_fake_stdin>:
-	...
-
-00003674 <__sf_fake_stdout>:
-	...
-    3694:	2b302d23 6c680020 6665004c 47464567     #-0+ .hlL.efgEFG
-    36a4:	32313000 36353433 41393837 45444342     .0123456789ABCDE
-    36b4:	31300046 35343332 39383736 64636261     F.0123456789abcd
-    36c4:	00006665                                ef..
-
-000036c8 <_init>:
-    36c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    36ca:	46c0      	nop			; (mov r8, r8)
-    36cc:	bcf8      	pop	{r3, r4, r5, r6, r7}
-    36ce:	bc08      	pop	{r3}
-    36d0:	469e      	mov	lr, r3
-    36d2:	4770      	bx	lr
-
-000036d4 <__init_array_start>:
-    36d4:	000000dd 	.word	0x000000dd
-
-000036d8 <_fini>:
-    36d8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
-    36da:	46c0      	nop			; (mov r8, r8)
-    36dc:	bcf8      	pop	{r3, r4, r5, r6, r7}
-    36de:	bc08      	pop	{r3}
-    36e0:	469e      	mov	lr, r3
-    36e2:	4770      	bx	lr
-
-000036e4 <__fini_array_start>:
-    36e4:	000000b5 	.word	0x000000b5
+
+D21_ADC_with_DMA.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00005b54  00000000  00000000  00010000  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .relocate     0000007c  20000000  00005b54  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          00000220  20000080  00005be0  00020080  2**4
+                  ALLOC
+  3 .stack        00002000  200002a0  00005e00  00020080  2**0
+                  ALLOC
+  4 .ARM.attributes 00000028  00000000  00000000  0002007c  2**0
+                  CONTENTS, READONLY
+  5 .comment      00000059  00000000  00000000  000200a4  2**0
+                  CONTENTS, READONLY
+  6 .debug_frame  00000ce4  00000000  00000000  00020100  2**2
+                  CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <exception_table>:
+       0:	a0 22 00 20 81 19 00 00 7d 19 00 00 7d 19 00 00     .". ....}...}...
+	...
+      2c:	7d 19 00 00 00 00 00 00 00 00 00 00 7d 19 00 00     }...........}...
+      3c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
+      4c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 79 04 00 00     }...}...}...y...
+      5c:	7d 19 00 00 7d 19 00 00 ad 12 00 00 bd 12 00 00     }...}...........
+      6c:	cd 12 00 00 dd 12 00 00 ed 12 00 00 fd 12 00 00     ................
+      7c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
+      8c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
+      9c:	7d 19 00 00 7d 19 00 00 7d 19 00 00 7d 19 00 00     }...}...}...}...
+      ac:	7d 19 00 00 00 00 00 00                             }.......
+
+000000b4 <__do_global_dtors_aux>:
+      b4:	b510      	push	{r4, lr}
+      b6:	4c06      	ldr	r4, [pc, #24]	; (d0 <__do_global_dtors_aux+0x1c>)
+      b8:	7823      	ldrb	r3, [r4, #0]
+      ba:	2b00      	cmp	r3, #0
+      bc:	d107      	bne.n	ce <__do_global_dtors_aux+0x1a>
+      be:	4b05      	ldr	r3, [pc, #20]	; (d4 <__do_global_dtors_aux+0x20>)
+      c0:	2b00      	cmp	r3, #0
+      c2:	d002      	beq.n	ca <__do_global_dtors_aux+0x16>
+      c4:	4804      	ldr	r0, [pc, #16]	; (d8 <__do_global_dtors_aux+0x24>)
+      c6:	e000      	b.n	ca <__do_global_dtors_aux+0x16>
+      c8:	bf00      	nop
+      ca:	2301      	movs	r3, #1
+      cc:	7023      	strb	r3, [r4, #0]
+      ce:	bd10      	pop	{r4, pc}
+      d0:	20000080 	.word	0x20000080
+      d4:	00000000 	.word	0x00000000
+      d8:	00005b54 	.word	0x00005b54
+
+000000dc <frame_dummy>:
+      dc:	4b08      	ldr	r3, [pc, #32]	; (100 <frame_dummy+0x24>)
+      de:	b510      	push	{r4, lr}
+      e0:	2b00      	cmp	r3, #0
+      e2:	d003      	beq.n	ec <frame_dummy+0x10>
+      e4:	4907      	ldr	r1, [pc, #28]	; (104 <frame_dummy+0x28>)
+      e6:	4808      	ldr	r0, [pc, #32]	; (108 <frame_dummy+0x2c>)
+      e8:	e000      	b.n	ec <frame_dummy+0x10>
+      ea:	bf00      	nop
+      ec:	4807      	ldr	r0, [pc, #28]	; (10c <frame_dummy+0x30>)
+      ee:	6803      	ldr	r3, [r0, #0]
+      f0:	2b00      	cmp	r3, #0
+      f2:	d100      	bne.n	f6 <frame_dummy+0x1a>
+      f4:	bd10      	pop	{r4, pc}
+      f6:	4b06      	ldr	r3, [pc, #24]	; (110 <frame_dummy+0x34>)
+      f8:	2b00      	cmp	r3, #0
+      fa:	d0fb      	beq.n	f4 <frame_dummy+0x18>
+      fc:	4798      	blx	r3
+      fe:	e7f9      	b.n	f4 <frame_dummy+0x18>
+     100:	00000000 	.word	0x00000000
+     104:	20000084 	.word	0x20000084
+     108:	00005b54 	.word	0x00005b54
+     10c:	00005b54 	.word	0x00005b54
+     110:	00000000 	.word	0x00000000
+
+00000114 <_adc_configure_ain_pin>:
+     114:	b530      	push	{r4, r5, lr}
+     116:	b097      	sub	sp, #92	; 0x5c
+     118:	ad02      	add	r5, sp, #8
+     11a:	0004      	movs	r4, r0
+     11c:	2250      	movs	r2, #80	; 0x50
+     11e:	490a      	ldr	r1, [pc, #40]	; (148 <_adc_configure_ain_pin+0x34>)
+     120:	0028      	movs	r0, r5
+     122:	4b0a      	ldr	r3, [pc, #40]	; (14c <_adc_configure_ain_pin+0x38>)
+     124:	4798      	blx	r3
+     126:	2c13      	cmp	r4, #19
+     128:	d80b      	bhi.n	142 <_adc_configure_ain_pin+0x2e>
+     12a:	2300      	movs	r3, #0
+     12c:	00a4      	lsls	r4, r4, #2
+     12e:	a901      	add	r1, sp, #4
+     130:	5960      	ldr	r0, [r4, r5]
+     132:	704b      	strb	r3, [r1, #1]
+     134:	70cb      	strb	r3, [r1, #3]
+     136:	708b      	strb	r3, [r1, #2]
+     138:	3301      	adds	r3, #1
+     13a:	700b      	strb	r3, [r1, #0]
+     13c:	b2c0      	uxtb	r0, r0
+     13e:	4b04      	ldr	r3, [pc, #16]	; (150 <_adc_configure_ain_pin+0x3c>)
+     140:	4798      	blx	r3
+     142:	b017      	add	sp, #92	; 0x5c
+     144:	bd30      	pop	{r4, r5, pc}
+     146:	46c0      	nop			; (mov r8, r8)
+     148:	000058f0 	.word	0x000058f0
+     14c:	00004815 	.word	0x00004815
+     150:	00001921 	.word	0x00001921
+
+00000154 <adc_get_config_defaults>:
+     154:	22c0      	movs	r2, #192	; 0xc0
+     156:	0152      	lsls	r2, r2, #5
+     158:	81c2      	strh	r2, [r0, #14]
+     15a:	0002      	movs	r2, r0
+     15c:	2300      	movs	r3, #0
+     15e:	322a      	adds	r2, #42	; 0x2a
+     160:	7003      	strb	r3, [r0, #0]
+     162:	7043      	strb	r3, [r0, #1]
+     164:	8043      	strh	r3, [r0, #2]
+     166:	7103      	strb	r3, [r0, #4]
+     168:	7603      	strb	r3, [r0, #24]
+     16a:	6203      	str	r3, [r0, #32]
+     16c:	61c3      	str	r3, [r0, #28]
+     16e:	6083      	str	r3, [r0, #8]
+     170:	7303      	strb	r3, [r0, #12]
+     172:	7403      	strb	r3, [r0, #16]
+     174:	7443      	strb	r3, [r0, #17]
+     176:	7483      	strb	r3, [r0, #18]
+     178:	74c3      	strb	r3, [r0, #19]
+     17a:	7503      	strb	r3, [r0, #20]
+     17c:	7013      	strb	r3, [r2, #0]
+     17e:	1d42      	adds	r2, r0, #5
+     180:	7543      	strb	r3, [r0, #21]
+     182:	7583      	strb	r3, [r0, #22]
+     184:	77d3      	strb	r3, [r2, #31]
+     186:	84c3      	strh	r3, [r0, #38]	; 0x26
+     188:	8503      	strh	r3, [r0, #40]	; 0x28
+     18a:	75c3      	strb	r3, [r0, #23]
+     18c:	3226      	adds	r2, #38	; 0x26
+     18e:	302c      	adds	r0, #44	; 0x2c
+     190:	7013      	strb	r3, [r2, #0]
+     192:	7003      	strb	r3, [r0, #0]
+     194:	4770      	bx	lr
+	...
+
+00000198 <adc_init>:
+     198:	2380      	movs	r3, #128	; 0x80
+     19a:	b5f0      	push	{r4, r5, r6, r7, lr}
+     19c:	0014      	movs	r4, r2
+     19e:	4aac      	ldr	r2, [pc, #688]	; (450 <adc_init+0x2b8>)
+     1a0:	6001      	str	r1, [r0, #0]
+     1a2:	0007      	movs	r7, r0
+     1a4:	6a10      	ldr	r0, [r2, #32]
+     1a6:	025b      	lsls	r3, r3, #9
+     1a8:	4303      	orrs	r3, r0
+     1aa:	6213      	str	r3, [r2, #32]
+     1ac:	780b      	ldrb	r3, [r1, #0]
+     1ae:	b087      	sub	sp, #28
+     1b0:	2005      	movs	r0, #5
+     1b2:	07db      	lsls	r3, r3, #31
+     1b4:	d500      	bpl.n	1b8 <adc_init+0x20>
+     1b6:	e0e7      	b.n	388 <adc_init+0x1f0>
+     1b8:	780b      	ldrb	r3, [r1, #0]
+     1ba:	3017      	adds	r0, #23
+     1bc:	079b      	lsls	r3, r3, #30
+     1be:	d500      	bpl.n	1c2 <adc_init+0x2a>
+     1c0:	e0e2      	b.n	388 <adc_init+0x1f0>
+     1c2:	7863      	ldrb	r3, [r4, #1]
+     1c4:	713b      	strb	r3, [r7, #4]
+     1c6:	2b00      	cmp	r3, #0
+     1c8:	d104      	bne.n	1d4 <adc_init+0x3c>
+     1ca:	4aa2      	ldr	r2, [pc, #648]	; (454 <adc_init+0x2bc>)
+     1cc:	3304      	adds	r3, #4
+     1ce:	6c11      	ldr	r1, [r2, #64]	; 0x40
+     1d0:	430b      	orrs	r3, r1
+     1d2:	6413      	str	r3, [r2, #64]	; 0x40
+     1d4:	7823      	ldrb	r3, [r4, #0]
+     1d6:	a905      	add	r1, sp, #20
+     1d8:	700b      	strb	r3, [r1, #0]
+     1da:	201e      	movs	r0, #30
+     1dc:	4b9e      	ldr	r3, [pc, #632]	; (458 <adc_init+0x2c0>)
+     1de:	683d      	ldr	r5, [r7, #0]
+     1e0:	4798      	blx	r3
+     1e2:	4b9e      	ldr	r3, [pc, #632]	; (45c <adc_init+0x2c4>)
+     1e4:	201e      	movs	r0, #30
+     1e6:	4798      	blx	r3
+     1e8:	0023      	movs	r3, r4
+     1ea:	332c      	adds	r3, #44	; 0x2c
+     1ec:	9302      	str	r3, [sp, #8]
+     1ee:	781b      	ldrb	r3, [r3, #0]
+     1f0:	7b22      	ldrb	r2, [r4, #12]
+     1f2:	9201      	str	r2, [sp, #4]
+     1f4:	2b00      	cmp	r3, #0
+     1f6:	d033      	beq.n	260 <adc_init+0xc8>
+     1f8:	0022      	movs	r2, r4
+     1fa:	322b      	adds	r2, #43	; 0x2b
+     1fc:	7816      	ldrb	r6, [r2, #0]
+     1fe:	9a01      	ldr	r2, [sp, #4]
+     200:	1996      	adds	r6, r2, r6
+     202:	b2f6      	uxtb	r6, r6
+     204:	199b      	adds	r3, r3, r6
+     206:	b2db      	uxtb	r3, r3
+     208:	9303      	str	r3, [sp, #12]
+     20a:	9b01      	ldr	r3, [sp, #4]
+     20c:	1af0      	subs	r0, r6, r3
+     20e:	9b03      	ldr	r3, [sp, #12]
+     210:	b2c0      	uxtb	r0, r0
+     212:	42b3      	cmp	r3, r6
+     214:	d81b      	bhi.n	24e <adc_init+0xb6>
+     216:	89e0      	ldrh	r0, [r4, #14]
+     218:	4b91      	ldr	r3, [pc, #580]	; (460 <adc_init+0x2c8>)
+     21a:	4798      	blx	r3
+     21c:	7d63      	ldrb	r3, [r4, #21]
+     21e:	009b      	lsls	r3, r3, #2
+     220:	b2db      	uxtb	r3, r3
+     222:	702b      	strb	r3, [r5, #0]
+     224:	7da3      	ldrb	r3, [r4, #22]
+     226:	7862      	ldrb	r2, [r4, #1]
+     228:	01db      	lsls	r3, r3, #7
+     22a:	4313      	orrs	r3, r2
+     22c:	b2db      	uxtb	r3, r3
+     22e:	706b      	strb	r3, [r5, #1]
+     230:	7923      	ldrb	r3, [r4, #4]
+     232:	2b30      	cmp	r3, #48	; 0x30
+     234:	d100      	bne.n	238 <adc_init+0xa0>
+     236:	e0b4      	b.n	3a2 <adc_init+0x20a>
+     238:	d818      	bhi.n	26c <adc_init+0xd4>
+     23a:	2b10      	cmp	r3, #16
+     23c:	d100      	bne.n	240 <adc_init+0xa8>
+     23e:	e0ad      	b.n	39c <adc_init+0x204>
+     240:	2b20      	cmp	r3, #32
+     242:	d100      	bne.n	246 <adc_init+0xae>
+     244:	e0ad      	b.n	3a2 <adc_init+0x20a>
+     246:	2b00      	cmp	r3, #0
+     248:	d11a      	bne.n	280 <adc_init+0xe8>
+     24a:	001a      	movs	r2, r3
+     24c:	e0a7      	b.n	39e <adc_init+0x206>
+     24e:	230f      	movs	r3, #15
+     250:	4018      	ands	r0, r3
+     252:	7b23      	ldrb	r3, [r4, #12]
+     254:	3601      	adds	r6, #1
+     256:	18c0      	adds	r0, r0, r3
+     258:	4b81      	ldr	r3, [pc, #516]	; (460 <adc_init+0x2c8>)
+     25a:	4798      	blx	r3
+     25c:	b2f6      	uxtb	r6, r6
+     25e:	e7d4      	b.n	20a <adc_init+0x72>
+     260:	9801      	ldr	r0, [sp, #4]
+     262:	4e7f      	ldr	r6, [pc, #508]	; (460 <adc_init+0x2c8>)
+     264:	47b0      	blx	r6
+     266:	89e0      	ldrh	r0, [r4, #14]
+     268:	47b0      	blx	r6
+     26a:	e7d7      	b.n	21c <adc_init+0x84>
+     26c:	2b32      	cmp	r3, #50	; 0x32
+     26e:	d009      	beq.n	284 <adc_init+0xec>
+     270:	d200      	bcs.n	274 <adc_init+0xdc>
+     272:	e098      	b.n	3a6 <adc_init+0x20e>
+     274:	2b33      	cmp	r3, #51	; 0x33
+     276:	d100      	bne.n	27a <adc_init+0xe2>
+     278:	e08c      	b.n	394 <adc_init+0x1fc>
+     27a:	2b34      	cmp	r3, #52	; 0x34
+     27c:	d100      	bne.n	280 <adc_init+0xe8>
+     27e:	e085      	b.n	38c <adc_init+0x1f4>
+     280:	2017      	movs	r0, #23
+     282:	e081      	b.n	388 <adc_init+0x1f0>
+     284:	2204      	movs	r2, #4
+     286:	2310      	movs	r3, #16
+     288:	2102      	movs	r1, #2
+     28a:	2070      	movs	r0, #112	; 0x70
+     28c:	0109      	lsls	r1, r1, #4
+     28e:	4001      	ands	r1, r0
+     290:	430a      	orrs	r2, r1
+     292:	70aa      	strb	r2, [r5, #2]
+     294:	7de2      	ldrb	r2, [r4, #23]
+     296:	2a3f      	cmp	r2, #63	; 0x3f
+     298:	d8f2      	bhi.n	280 <adc_init+0xe8>
+     29a:	70ea      	strb	r2, [r5, #3]
+     29c:	6839      	ldr	r1, [r7, #0]
+     29e:	7e4a      	ldrb	r2, [r1, #25]
+     2a0:	b252      	sxtb	r2, r2
+     2a2:	2a00      	cmp	r2, #0
+     2a4:	dbfb      	blt.n	29e <adc_init+0x106>
+     2a6:	8861      	ldrh	r1, [r4, #2]
+     2a8:	7ce2      	ldrb	r2, [r4, #19]
+     2aa:	430a      	orrs	r2, r1
+     2ac:	1d61      	adds	r1, r4, #5
+     2ae:	7fc8      	ldrb	r0, [r1, #31]
+     2b0:	00c0      	lsls	r0, r0, #3
+     2b2:	4302      	orrs	r2, r0
+     2b4:	7d20      	ldrb	r0, [r4, #20]
+     2b6:	0080      	lsls	r0, r0, #2
+     2b8:	4302      	orrs	r2, r0
+     2ba:	7ca0      	ldrb	r0, [r4, #18]
+     2bc:	0040      	lsls	r0, r0, #1
+     2be:	4302      	orrs	r2, r0
+     2c0:	431a      	orrs	r2, r3
+     2c2:	80aa      	strh	r2, [r5, #4]
+     2c4:	7e22      	ldrb	r2, [r4, #24]
+     2c6:	4694      	mov	ip, r2
+     2c8:	2a00      	cmp	r2, #0
+     2ca:	d007      	beq.n	2dc <adc_init+0x144>
+     2cc:	2b10      	cmp	r3, #16
+     2ce:	d100      	bne.n	2d2 <adc_init+0x13a>
+     2d0:	e0af      	b.n	432 <adc_init+0x29a>
+     2d2:	d900      	bls.n	2d6 <adc_init+0x13e>
+     2d4:	e069      	b.n	3aa <adc_init+0x212>
+     2d6:	2b00      	cmp	r3, #0
+     2d8:	d100      	bne.n	2dc <adc_init+0x144>
+     2da:	e09b      	b.n	414 <adc_init+0x27c>
+     2dc:	6838      	ldr	r0, [r7, #0]
+     2de:	7e43      	ldrb	r3, [r0, #25]
+     2e0:	b25b      	sxtb	r3, r3
+     2e2:	2b00      	cmp	r3, #0
+     2e4:	dbfb      	blt.n	2de <adc_init+0x146>
+     2e6:	4663      	mov	r3, ip
+     2e8:	722b      	strb	r3, [r5, #8]
+     2ea:	683a      	ldr	r2, [r7, #0]
+     2ec:	7e53      	ldrb	r3, [r2, #25]
+     2ee:	b25b      	sxtb	r3, r3
+     2f0:	2b00      	cmp	r3, #0
+     2f2:	dbfb      	blt.n	2ec <adc_init+0x154>
+     2f4:	8ba3      	ldrh	r3, [r4, #28]
+     2f6:	83ab      	strh	r3, [r5, #28]
+     2f8:	683a      	ldr	r2, [r7, #0]
+     2fa:	7e53      	ldrb	r3, [r2, #25]
+     2fc:	b25b      	sxtb	r3, r3
+     2fe:	2b00      	cmp	r3, #0
+     300:	dbfb      	blt.n	2fa <adc_init+0x162>
+     302:	8c23      	ldrh	r3, [r4, #32]
+     304:	842b      	strh	r3, [r5, #32]
+     306:	9b02      	ldr	r3, [sp, #8]
+     308:	781a      	ldrb	r2, [r3, #0]
+     30a:	2a00      	cmp	r2, #0
+     30c:	d003      	beq.n	316 <adc_init+0x17e>
+     30e:	3a01      	subs	r2, #1
+     310:	b2d2      	uxtb	r2, r2
+     312:	2a0f      	cmp	r2, #15
+     314:	d8b4      	bhi.n	280 <adc_init+0xe8>
+     316:	0023      	movs	r3, r4
+     318:	332b      	adds	r3, #43	; 0x2b
+     31a:	7818      	ldrb	r0, [r3, #0]
+     31c:	280f      	cmp	r0, #15
+     31e:	d8af      	bhi.n	280 <adc_init+0xe8>
+     320:	683e      	ldr	r6, [r7, #0]
+     322:	7e73      	ldrb	r3, [r6, #25]
+     324:	b25b      	sxtb	r3, r3
+     326:	2b00      	cmp	r3, #0
+     328:	dbfb      	blt.n	322 <adc_init+0x18a>
+     32a:	7b26      	ldrb	r6, [r4, #12]
+     32c:	89e3      	ldrh	r3, [r4, #14]
+     32e:	0500      	lsls	r0, r0, #20
+     330:	4333      	orrs	r3, r6
+     332:	68a6      	ldr	r6, [r4, #8]
+     334:	0412      	lsls	r2, r2, #16
+     336:	4333      	orrs	r3, r6
+     338:	4303      	orrs	r3, r0
+     33a:	4313      	orrs	r3, r2
+     33c:	612b      	str	r3, [r5, #16]
+     33e:	0023      	movs	r3, r4
+     340:	332a      	adds	r3, #42	; 0x2a
+     342:	781b      	ldrb	r3, [r3, #0]
+     344:	752b      	strb	r3, [r5, #20]
+     346:	230f      	movs	r3, #15
+     348:	75ab      	strb	r3, [r5, #22]
+     34a:	7fcb      	ldrb	r3, [r1, #31]
+     34c:	2b00      	cmp	r3, #0
+     34e:	d00c      	beq.n	36a <adc_init+0x1d2>
+     350:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
+     352:	4944      	ldr	r1, [pc, #272]	; (464 <adc_init+0x2cc>)
+     354:	428b      	cmp	r3, r1
+     356:	d893      	bhi.n	280 <adc_init+0xe8>
+     358:	84ab      	strh	r3, [r5, #36]	; 0x24
+     35a:	2380      	movs	r3, #128	; 0x80
+     35c:	8d22      	ldrh	r2, [r4, #40]	; 0x28
+     35e:	011b      	lsls	r3, r3, #4
+     360:	18d3      	adds	r3, r2, r3
+     362:	b29b      	uxth	r3, r3
+     364:	428b      	cmp	r3, r1
+     366:	d88b      	bhi.n	280 <adc_init+0xe8>
+     368:	84ea      	strh	r2, [r5, #38]	; 0x26
+     36a:	22e0      	movs	r2, #224	; 0xe0
+     36c:	4b3e      	ldr	r3, [pc, #248]	; (468 <adc_init+0x2d0>)
+     36e:	2000      	movs	r0, #0
+     370:	6819      	ldr	r1, [r3, #0]
+     372:	00d2      	lsls	r2, r2, #3
+     374:	014b      	lsls	r3, r1, #5
+     376:	0019      	movs	r1, r3
+     378:	401a      	ands	r2, r3
+     37a:	4b3c      	ldr	r3, [pc, #240]	; (46c <adc_init+0x2d4>)
+     37c:	681b      	ldr	r3, [r3, #0]
+     37e:	0edb      	lsrs	r3, r3, #27
+     380:	430b      	orrs	r3, r1
+     382:	b2db      	uxtb	r3, r3
+     384:	4313      	orrs	r3, r2
+     386:	852b      	strh	r3, [r5, #40]	; 0x28
+     388:	b007      	add	sp, #28
+     38a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     38c:	7c61      	ldrb	r1, [r4, #17]
+     38e:	7c22      	ldrb	r2, [r4, #16]
+     390:	2310      	movs	r3, #16
+     392:	e77a      	b.n	28a <adc_init+0xf2>
+     394:	2206      	movs	r2, #6
+     396:	2310      	movs	r3, #16
+     398:	2101      	movs	r1, #1
+     39a:	e776      	b.n	28a <adc_init+0xf2>
+     39c:	2208      	movs	r2, #8
+     39e:	2100      	movs	r1, #0
+     3a0:	e773      	b.n	28a <adc_init+0xf2>
+     3a2:	2200      	movs	r2, #0
+     3a4:	e7fb      	b.n	39e <adc_init+0x206>
+     3a6:	2202      	movs	r2, #2
+     3a8:	e7f5      	b.n	396 <adc_init+0x1fe>
+     3aa:	2b20      	cmp	r3, #32
+     3ac:	d018      	beq.n	3e0 <adc_init+0x248>
+     3ae:	2b30      	cmp	r3, #48	; 0x30
+     3b0:	d000      	beq.n	3b4 <adc_init+0x21c>
+     3b2:	e793      	b.n	2dc <adc_init+0x144>
+     3b4:	7ce3      	ldrb	r3, [r4, #19]
+     3b6:	69e0      	ldr	r0, [r4, #28]
+     3b8:	2b00      	cmp	r3, #0
+     3ba:	d009      	beq.n	3d0 <adc_init+0x238>
+     3bc:	0003      	movs	r3, r0
+     3be:	3380      	adds	r3, #128	; 0x80
+     3c0:	2bff      	cmp	r3, #255	; 0xff
+     3c2:	d900      	bls.n	3c6 <adc_init+0x22e>
+     3c4:	e75c      	b.n	280 <adc_init+0xe8>
+     3c6:	6a23      	ldr	r3, [r4, #32]
+     3c8:	3380      	adds	r3, #128	; 0x80
+     3ca:	2bff      	cmp	r3, #255	; 0xff
+     3cc:	d900      	bls.n	3d0 <adc_init+0x238>
+     3ce:	e757      	b.n	280 <adc_init+0xe8>
+     3d0:	28ff      	cmp	r0, #255	; 0xff
+     3d2:	dd00      	ble.n	3d6 <adc_init+0x23e>
+     3d4:	e754      	b.n	280 <adc_init+0xe8>
+     3d6:	6a23      	ldr	r3, [r4, #32]
+     3d8:	2bff      	cmp	r3, #255	; 0xff
+     3da:	dd00      	ble.n	3de <adc_init+0x246>
+     3dc:	e750      	b.n	280 <adc_init+0xe8>
+     3de:	e77d      	b.n	2dc <adc_init+0x144>
+     3e0:	7ce0      	ldrb	r0, [r4, #19]
+     3e2:	69e6      	ldr	r6, [r4, #28]
+     3e4:	4b22      	ldr	r3, [pc, #136]	; (470 <adc_init+0x2d8>)
+     3e6:	2800      	cmp	r0, #0
+     3e8:	d00c      	beq.n	404 <adc_init+0x26c>
+     3ea:	2080      	movs	r0, #128	; 0x80
+     3ec:	0080      	lsls	r0, r0, #2
+     3ee:	1830      	adds	r0, r6, r0
+     3f0:	4298      	cmp	r0, r3
+     3f2:	d900      	bls.n	3f6 <adc_init+0x25e>
+     3f4:	e744      	b.n	280 <adc_init+0xe8>
+     3f6:	2280      	movs	r2, #128	; 0x80
+     3f8:	6a20      	ldr	r0, [r4, #32]
+     3fa:	0092      	lsls	r2, r2, #2
+     3fc:	1810      	adds	r0, r2, r0
+     3fe:	4298      	cmp	r0, r3
+     400:	d900      	bls.n	404 <adc_init+0x26c>
+     402:	e73d      	b.n	280 <adc_init+0xe8>
+     404:	429e      	cmp	r6, r3
+     406:	dd00      	ble.n	40a <adc_init+0x272>
+     408:	e73a      	b.n	280 <adc_init+0xe8>
+     40a:	6a22      	ldr	r2, [r4, #32]
+     40c:	429a      	cmp	r2, r3
+     40e:	dd00      	ble.n	412 <adc_init+0x27a>
+     410:	e736      	b.n	280 <adc_init+0xe8>
+     412:	e763      	b.n	2dc <adc_init+0x144>
+     414:	7ce0      	ldrb	r0, [r4, #19]
+     416:	69e6      	ldr	r6, [r4, #28]
+     418:	4b12      	ldr	r3, [pc, #72]	; (464 <adc_init+0x2cc>)
+     41a:	2800      	cmp	r0, #0
+     41c:	d0f2      	beq.n	404 <adc_init+0x26c>
+     41e:	2280      	movs	r2, #128	; 0x80
+     420:	0112      	lsls	r2, r2, #4
+     422:	18b0      	adds	r0, r6, r2
+     424:	4298      	cmp	r0, r3
+     426:	d900      	bls.n	42a <adc_init+0x292>
+     428:	e72a      	b.n	280 <adc_init+0xe8>
+     42a:	2080      	movs	r0, #128	; 0x80
+     42c:	6a22      	ldr	r2, [r4, #32]
+     42e:	0100      	lsls	r0, r0, #4
+     430:	e7e4      	b.n	3fc <adc_init+0x264>
+     432:	7ce0      	ldrb	r0, [r4, #19]
+     434:	69e6      	ldr	r6, [r4, #28]
+     436:	4b0f      	ldr	r3, [pc, #60]	; (474 <adc_init+0x2dc>)
+     438:	2800      	cmp	r0, #0
+     43a:	d0e3      	beq.n	404 <adc_init+0x26c>
+     43c:	2280      	movs	r2, #128	; 0x80
+     43e:	0212      	lsls	r2, r2, #8
+     440:	18b0      	adds	r0, r6, r2
+     442:	4298      	cmp	r0, r3
+     444:	d900      	bls.n	448 <adc_init+0x2b0>
+     446:	e71b      	b.n	280 <adc_init+0xe8>
+     448:	2080      	movs	r0, #128	; 0x80
+     44a:	6a22      	ldr	r2, [r4, #32]
+     44c:	0200      	lsls	r0, r0, #8
+     44e:	e7d5      	b.n	3fc <adc_init+0x264>
+     450:	40000400 	.word	0x40000400
+     454:	40000800 	.word	0x40000800
+     458:	0000184d 	.word	0x0000184d
+     45c:	000017c5 	.word	0x000017c5
+     460:	00000115 	.word	0x00000115
+     464:	00000fff 	.word	0x00000fff
+     468:	00806024 	.word	0x00806024
+     46c:	00806020 	.word	0x00806020
+     470:	000003ff 	.word	0x000003ff
+     474:	0000ffff 	.word	0x0000ffff
+
+00000478 <DMAC_Handler>:
+     478:	b570      	push	{r4, r5, r6, lr}
+     47a:	4b20      	ldr	r3, [pc, #128]	; (4fc <DMAC_Handler+0x84>)
+     47c:	4798      	blx	r3
+     47e:	220f      	movs	r2, #15
+     480:	4b1f      	ldr	r3, [pc, #124]	; (500 <DMAC_Handler+0x88>)
+     482:	4920      	ldr	r1, [pc, #128]	; (504 <DMAC_Handler+0x8c>)
+     484:	8c1b      	ldrh	r3, [r3, #32]
+     486:	4c20      	ldr	r4, [pc, #128]	; (508 <DMAC_Handler+0x90>)
+     488:	4013      	ands	r3, r2
+     48a:	009b      	lsls	r3, r3, #2
+     48c:	5858      	ldr	r0, [r3, r1]
+     48e:	4d1f      	ldr	r5, [pc, #124]	; (50c <DMAC_Handler+0x94>)
+     490:	7803      	ldrb	r3, [r0, #0]
+     492:	4013      	ands	r3, r2
+     494:	4a1e      	ldr	r2, [pc, #120]	; (510 <DMAC_Handler+0x98>)
+     496:	7013      	strb	r3, [r2, #0]
+     498:	7801      	ldrb	r1, [r0, #0]
+     49a:	4a1e      	ldr	r2, [pc, #120]	; (514 <DMAC_Handler+0x9c>)
+     49c:	0109      	lsls	r1, r1, #4
+     49e:	1864      	adds	r4, r4, r1
+     4a0:	1869      	adds	r1, r5, r1
+     4a2:	7813      	ldrb	r3, [r2, #0]
+     4a4:	8864      	ldrh	r4, [r4, #2]
+     4a6:	8849      	ldrh	r1, [r1, #2]
+     4a8:	b2db      	uxtb	r3, r3
+     4aa:	1a61      	subs	r1, r4, r1
+     4ac:	6141      	str	r1, [r0, #20]
+     4ae:	001c      	movs	r4, r3
+     4b0:	2101      	movs	r1, #1
+     4b2:	400c      	ands	r4, r1
+     4b4:	d00c      	beq.n	4d0 <DMAC_Handler+0x58>
+     4b6:	2310      	movs	r3, #16
+     4b8:	7011      	strb	r1, [r2, #0]
+     4ba:	7443      	strb	r3, [r0, #17]
+     4bc:	7c03      	ldrb	r3, [r0, #16]
+     4be:	420b      	tst	r3, r1
+     4c0:	d003      	beq.n	4ca <DMAC_Handler+0x52>
+     4c2:	6843      	ldr	r3, [r0, #4]
+     4c4:	2b00      	cmp	r3, #0
+     4c6:	d000      	beq.n	4ca <DMAC_Handler+0x52>
+     4c8:	4798      	blx	r3
+     4ca:	4b13      	ldr	r3, [pc, #76]	; (518 <DMAC_Handler+0xa0>)
+     4cc:	4798      	blx	r3
+     4ce:	bd70      	pop	{r4, r5, r6, pc}
+     4d0:	2102      	movs	r1, #2
+     4d2:	420b      	tst	r3, r1
+     4d4:	d006      	beq.n	4e4 <DMAC_Handler+0x6c>
+     4d6:	7011      	strb	r1, [r2, #0]
+     4d8:	7c03      	ldrb	r3, [r0, #16]
+     4da:	7444      	strb	r4, [r0, #17]
+     4dc:	420b      	tst	r3, r1
+     4de:	d0f4      	beq.n	4ca <DMAC_Handler+0x52>
+     4e0:	6883      	ldr	r3, [r0, #8]
+     4e2:	e7ef      	b.n	4c4 <DMAC_Handler+0x4c>
+     4e4:	2104      	movs	r1, #4
+     4e6:	420b      	tst	r3, r1
+     4e8:	d0ef      	beq.n	4ca <DMAC_Handler+0x52>
+     4ea:	2306      	movs	r3, #6
+     4ec:	7011      	strb	r1, [r2, #0]
+     4ee:	7443      	strb	r3, [r0, #17]
+     4f0:	7c03      	ldrb	r3, [r0, #16]
+     4f2:	420b      	tst	r3, r1
+     4f4:	d0e9      	beq.n	4ca <DMAC_Handler+0x52>
+     4f6:	68c3      	ldr	r3, [r0, #12]
+     4f8:	e7e4      	b.n	4c4 <DMAC_Handler+0x4c>
+     4fa:	46c0      	nop			; (mov r8, r8)
+     4fc:	00001379 	.word	0x00001379
+     500:	41004800 	.word	0x41004800
+     504:	2000009c 	.word	0x2000009c
+     508:	200001e0 	.word	0x200001e0
+     50c:	200000b0 	.word	0x200000b0
+     510:	4100483f 	.word	0x4100483f
+     514:	4100484e 	.word	0x4100484e
+     518:	000013ad 	.word	0x000013ad
+
+0000051c <dma_get_config_defaults>:
+     51c:	2300      	movs	r3, #0
+     51e:	2203      	movs	r2, #3
+     520:	7003      	strb	r3, [r0, #0]
+     522:	7043      	strb	r3, [r0, #1]
+     524:	7082      	strb	r2, [r0, #2]
+     526:	70c3      	strb	r3, [r0, #3]
+     528:	7103      	strb	r3, [r0, #4]
+     52a:	4770      	bx	lr
+
+0000052c <dma_allocate>:
+     52c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+     52e:	4b3f      	ldr	r3, [pc, #252]	; (62c <dma_allocate+0x100>)
+     530:	0005      	movs	r5, r0
+     532:	000e      	movs	r6, r1
+     534:	4798      	blx	r3
+     536:	4f3e      	ldr	r7, [pc, #248]	; (630 <dma_allocate+0x104>)
+     538:	783b      	ldrb	r3, [r7, #0]
+     53a:	2b00      	cmp	r3, #0
+     53c:	d116      	bne.n	56c <dma_allocate+0x40>
+     53e:	2220      	movs	r2, #32
+     540:	4b3c      	ldr	r3, [pc, #240]	; (634 <dma_allocate+0x108>)
+     542:	6959      	ldr	r1, [r3, #20]
+     544:	430a      	orrs	r2, r1
+     546:	615a      	str	r2, [r3, #20]
+     548:	2210      	movs	r2, #16
+     54a:	69d9      	ldr	r1, [r3, #28]
+     54c:	430a      	orrs	r2, r1
+     54e:	2102      	movs	r1, #2
+     550:	61da      	str	r2, [r3, #28]
+     552:	4b39      	ldr	r3, [pc, #228]	; (638 <dma_allocate+0x10c>)
+     554:	881a      	ldrh	r2, [r3, #0]
+     556:	438a      	bics	r2, r1
+     558:	801a      	strh	r2, [r3, #0]
+     55a:	2201      	movs	r2, #1
+     55c:	4937      	ldr	r1, [pc, #220]	; (63c <dma_allocate+0x110>)
+     55e:	801a      	strh	r2, [r3, #0]
+     560:	6359      	str	r1, [r3, #52]	; 0x34
+     562:	4937      	ldr	r1, [pc, #220]	; (640 <dma_allocate+0x114>)
+     564:	6399      	str	r1, [r3, #56]	; 0x38
+     566:	4937      	ldr	r1, [pc, #220]	; (644 <dma_allocate+0x118>)
+     568:	8019      	strh	r1, [r3, #0]
+     56a:	703a      	strb	r2, [r7, #0]
+     56c:	4b2f      	ldr	r3, [pc, #188]	; (62c <dma_allocate+0x100>)
+     56e:	4798      	blx	r3
+     570:	2400      	movs	r4, #0
+     572:	2301      	movs	r3, #1
+     574:	687a      	ldr	r2, [r7, #4]
+     576:	421a      	tst	r2, r3
+     578:	d14c      	bne.n	614 <dma_allocate+0xe8>
+     57a:	40a3      	lsls	r3, r4
+     57c:	687a      	ldr	r2, [r7, #4]
+     57e:	4313      	orrs	r3, r2
+     580:	607b      	str	r3, [r7, #4]
+     582:	7a3b      	ldrb	r3, [r7, #8]
+     584:	3b01      	subs	r3, #1
+     586:	723b      	strb	r3, [r7, #8]
+     588:	2701      	movs	r7, #1
+     58a:	4b2f      	ldr	r3, [pc, #188]	; (648 <dma_allocate+0x11c>)
+     58c:	4798      	blx	r3
+     58e:	2f00      	cmp	r7, #0
+     590:	d047      	beq.n	622 <dma_allocate+0xf6>
+     592:	4b2e      	ldr	r3, [pc, #184]	; (64c <dma_allocate+0x120>)
+     594:	2102      	movs	r1, #2
+     596:	702c      	strb	r4, [r5, #0]
+     598:	701c      	strb	r4, [r3, #0]
+     59a:	2401      	movs	r4, #1
+     59c:	4b2c      	ldr	r3, [pc, #176]	; (650 <dma_allocate+0x124>)
+     59e:	4f26      	ldr	r7, [pc, #152]	; (638 <dma_allocate+0x10c>)
+     5a0:	781a      	ldrb	r2, [r3, #0]
+     5a2:	438a      	bics	r2, r1
+     5a4:	701a      	strb	r2, [r3, #0]
+     5a6:	701c      	strb	r4, [r3, #0]
+     5a8:	4b20      	ldr	r3, [pc, #128]	; (62c <dma_allocate+0x100>)
+     5aa:	4798      	blx	r3
+     5ac:	220f      	movs	r2, #15
+     5ae:	782b      	ldrb	r3, [r5, #0]
+     5b0:	21fc      	movs	r1, #252	; 0xfc
+     5b2:	4013      	ands	r3, r2
+     5b4:	4a25      	ldr	r2, [pc, #148]	; (64c <dma_allocate+0x120>)
+     5b6:	0189      	lsls	r1, r1, #6
+     5b8:	7013      	strb	r3, [r2, #0]
+     5ba:	782a      	ldrb	r2, [r5, #0]
+     5bc:	693b      	ldr	r3, [r7, #16]
+     5be:	4094      	lsls	r4, r2
+     5c0:	2260      	movs	r2, #96	; 0x60
+     5c2:	43a3      	bics	r3, r4
+     5c4:	613b      	str	r3, [r7, #16]
+     5c6:	7833      	ldrb	r3, [r6, #0]
+     5c8:	015b      	lsls	r3, r3, #5
+     5ca:	4013      	ands	r3, r2
+     5cc:	7872      	ldrb	r2, [r6, #1]
+     5ce:	0212      	lsls	r2, r2, #8
+     5d0:	400a      	ands	r2, r1
+     5d2:	21c0      	movs	r1, #192	; 0xc0
+     5d4:	4313      	orrs	r3, r2
+     5d6:	78b2      	ldrb	r2, [r6, #2]
+     5d8:	0409      	lsls	r1, r1, #16
+     5da:	0592      	lsls	r2, r2, #22
+     5dc:	400a      	ands	r2, r1
+     5de:	4313      	orrs	r3, r2
+     5e0:	78f2      	ldrb	r2, [r6, #3]
+     5e2:	2a00      	cmp	r2, #0
+     5e4:	d004      	beq.n	5f0 <dma_allocate+0xc4>
+     5e6:	2107      	movs	r1, #7
+     5e8:	400a      	ands	r2, r1
+     5ea:	3101      	adds	r1, #1
+     5ec:	430a      	orrs	r2, r1
+     5ee:	4313      	orrs	r3, r2
+     5f0:	7932      	ldrb	r2, [r6, #4]
+     5f2:	2a00      	cmp	r2, #0
+     5f4:	d001      	beq.n	5fa <dma_allocate+0xce>
+     5f6:	2210      	movs	r2, #16
+     5f8:	4313      	orrs	r3, r2
+     5fa:	2400      	movs	r4, #0
+     5fc:	647b      	str	r3, [r7, #68]	; 0x44
+     5fe:	4b12      	ldr	r3, [pc, #72]	; (648 <dma_allocate+0x11c>)
+     600:	4798      	blx	r3
+     602:	782b      	ldrb	r3, [r5, #0]
+     604:	4a13      	ldr	r2, [pc, #76]	; (654 <dma_allocate+0x128>)
+     606:	009b      	lsls	r3, r3, #2
+     608:	509d      	str	r5, [r3, r2]
+     60a:	61ac      	str	r4, [r5, #24]
+     60c:	4b0e      	ldr	r3, [pc, #56]	; (648 <dma_allocate+0x11c>)
+     60e:	4798      	blx	r3
+     610:	0020      	movs	r0, r4
+     612:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+     614:	3401      	adds	r4, #1
+     616:	b2e4      	uxtb	r4, r4
+     618:	0852      	lsrs	r2, r2, #1
+     61a:	2c05      	cmp	r4, #5
+     61c:	d1ab      	bne.n	576 <dma_allocate+0x4a>
+     61e:	2700      	movs	r7, #0
+     620:	e7b3      	b.n	58a <dma_allocate+0x5e>
+     622:	4b09      	ldr	r3, [pc, #36]	; (648 <dma_allocate+0x11c>)
+     624:	4798      	blx	r3
+     626:	2014      	movs	r0, #20
+     628:	e7f3      	b.n	612 <dma_allocate+0xe6>
+     62a:	46c0      	nop			; (mov r8, r8)
+     62c:	00001379 	.word	0x00001379
+     630:	20000000 	.word	0x20000000
+     634:	40000400 	.word	0x40000400
+     638:	41004800 	.word	0x41004800
+     63c:	200001e0 	.word	0x200001e0
+     640:	200000b0 	.word	0x200000b0
+     644:	00000f02 	.word	0x00000f02
+     648:	000013ad 	.word	0x000013ad
+     64c:	4100483f 	.word	0x4100483f
+     650:	41004840 	.word	0x41004840
+     654:	2000009c 	.word	0x2000009c
+
+00000658 <dma_start_transfer_job>:
+     658:	b570      	push	{r4, r5, r6, lr}
+     65a:	0005      	movs	r5, r0
+     65c:	4b18      	ldr	r3, [pc, #96]	; (6c0 <dma_start_transfer_job+0x68>)
+     65e:	4798      	blx	r3
+     660:	7c6c      	ldrb	r4, [r5, #17]
+     662:	4e18      	ldr	r6, [pc, #96]	; (6c4 <dma_start_transfer_job+0x6c>)
+     664:	b2e4      	uxtb	r4, r4
+     666:	2c05      	cmp	r4, #5
+     668:	d102      	bne.n	670 <dma_start_transfer_job+0x18>
+     66a:	47b0      	blx	r6
+     66c:	0020      	movs	r0, r4
+     66e:	bd70      	pop	{r4, r5, r6, pc}
+     670:	69ab      	ldr	r3, [r5, #24]
+     672:	885b      	ldrh	r3, [r3, #2]
+     674:	2b00      	cmp	r3, #0
+     676:	d102      	bne.n	67e <dma_start_transfer_job+0x26>
+     678:	47b0      	blx	r6
+     67a:	2017      	movs	r0, #23
+     67c:	e7f7      	b.n	66e <dma_start_transfer_job+0x16>
+     67e:	2240      	movs	r2, #64	; 0x40
+     680:	4b11      	ldr	r3, [pc, #68]	; (6c8 <dma_start_transfer_job+0x70>)
+     682:	601a      	str	r2, [r3, #0]
+     684:	782b      	ldrb	r3, [r5, #0]
+     686:	3a31      	subs	r2, #49	; 0x31
+     688:	4013      	ands	r3, r2
+     68a:	4a10      	ldr	r2, [pc, #64]	; (6cc <dma_start_transfer_job+0x74>)
+     68c:	7013      	strb	r3, [r2, #0]
+     68e:	782b      	ldrb	r3, [r5, #0]
+     690:	4a0f      	ldr	r2, [pc, #60]	; (6d0 <dma_start_transfer_job+0x78>)
+     692:	5cd3      	ldrb	r3, [r2, r3]
+     694:	2207      	movs	r2, #7
+     696:	4013      	ands	r3, r2
+     698:	4a0e      	ldr	r2, [pc, #56]	; (6d4 <dma_start_transfer_job+0x7c>)
+     69a:	7013      	strb	r3, [r2, #0]
+     69c:	2305      	movs	r3, #5
+     69e:	7828      	ldrb	r0, [r5, #0]
+     6a0:	746b      	strb	r3, [r5, #17]
+     6a2:	4b0d      	ldr	r3, [pc, #52]	; (6d8 <dma_start_transfer_job+0x80>)
+     6a4:	0100      	lsls	r0, r0, #4
+     6a6:	18c0      	adds	r0, r0, r3
+     6a8:	69a9      	ldr	r1, [r5, #24]
+     6aa:	2210      	movs	r2, #16
+     6ac:	4b0b      	ldr	r3, [pc, #44]	; (6dc <dma_start_transfer_job+0x84>)
+     6ae:	4798      	blx	r3
+     6b0:	2302      	movs	r3, #2
+     6b2:	4a0b      	ldr	r2, [pc, #44]	; (6e0 <dma_start_transfer_job+0x88>)
+     6b4:	7811      	ldrb	r1, [r2, #0]
+     6b6:	430b      	orrs	r3, r1
+     6b8:	7013      	strb	r3, [r2, #0]
+     6ba:	47b0      	blx	r6
+     6bc:	2000      	movs	r0, #0
+     6be:	e7d6      	b.n	66e <dma_start_transfer_job+0x16>
+     6c0:	00001379 	.word	0x00001379
+     6c4:	000013ad 	.word	0x000013ad
+     6c8:	e000e100 	.word	0xe000e100
+     6cc:	4100483f 	.word	0x4100483f
+     6d0:	20000100 	.word	0x20000100
+     6d4:	4100484d 	.word	0x4100484d
+     6d8:	200001e0 	.word	0x200001e0
+     6dc:	00004815 	.word	0x00004815
+     6e0:	41004840 	.word	0x41004840
+
+000006e4 <dma_descriptor_create>:
+     6e4:	b570      	push	{r4, r5, r6, lr}
+     6e6:	2401      	movs	r4, #1
+     6e8:	2603      	movs	r6, #3
+     6ea:	8803      	ldrh	r3, [r0, #0]
+     6ec:	780a      	ldrb	r2, [r1, #0]
+     6ee:	43a3      	bics	r3, r4
+     6f0:	4022      	ands	r2, r4
+     6f2:	4313      	orrs	r3, r2
+     6f4:	8003      	strh	r3, [r0, #0]
+     6f6:	784a      	ldrb	r2, [r1, #1]
+     6f8:	2506      	movs	r5, #6
+     6fa:	4032      	ands	r2, r6
+     6fc:	40a2      	lsls	r2, r4
+     6fe:	8803      	ldrh	r3, [r0, #0]
+     700:	43ab      	bics	r3, r5
+     702:	4313      	orrs	r3, r2
+     704:	8003      	strh	r3, [r0, #0]
+     706:	788b      	ldrb	r3, [r1, #2]
+     708:	2218      	movs	r2, #24
+     70a:	4033      	ands	r3, r6
+     70c:	40b3      	lsls	r3, r6
+     70e:	8805      	ldrh	r5, [r0, #0]
+     710:	4395      	bics	r5, r2
+     712:	431d      	orrs	r5, r3
+     714:	8005      	strh	r5, [r0, #0]
+     716:	78ca      	ldrb	r2, [r1, #3]
+     718:	8803      	ldrh	r3, [r0, #0]
+     71a:	4d18      	ldr	r5, [pc, #96]	; (77c <dma_descriptor_create+0x98>)
+     71c:	4032      	ands	r2, r6
+     71e:	0212      	lsls	r2, r2, #8
+     720:	402b      	ands	r3, r5
+     722:	4313      	orrs	r3, r2
+     724:	8003      	strh	r3, [r0, #0]
+     726:	790a      	ldrb	r2, [r1, #4]
+     728:	8803      	ldrh	r3, [r0, #0]
+     72a:	4d15      	ldr	r5, [pc, #84]	; (780 <dma_descriptor_create+0x9c>)
+     72c:	4022      	ands	r2, r4
+     72e:	0292      	lsls	r2, r2, #10
+     730:	402b      	ands	r3, r5
+     732:	4313      	orrs	r3, r2
+     734:	8003      	strh	r3, [r0, #0]
+     736:	794a      	ldrb	r2, [r1, #5]
+     738:	8803      	ldrh	r3, [r0, #0]
+     73a:	4d12      	ldr	r5, [pc, #72]	; (784 <dma_descriptor_create+0xa0>)
+     73c:	4022      	ands	r2, r4
+     73e:	402b      	ands	r3, r5
+     740:	02d2      	lsls	r2, r2, #11
+     742:	4313      	orrs	r3, r2
+     744:	8003      	strh	r3, [r0, #0]
+     746:	798a      	ldrb	r2, [r1, #6]
+     748:	8803      	ldrh	r3, [r0, #0]
+     74a:	4022      	ands	r2, r4
+     74c:	4c0e      	ldr	r4, [pc, #56]	; (788 <dma_descriptor_create+0xa4>)
+     74e:	0312      	lsls	r2, r2, #12
+     750:	4023      	ands	r3, r4
+     752:	4313      	orrs	r3, r2
+     754:	8003      	strh	r3, [r0, #0]
+     756:	2307      	movs	r3, #7
+     758:	79ca      	ldrb	r2, [r1, #7]
+     75a:	401a      	ands	r2, r3
+     75c:	8803      	ldrh	r3, [r0, #0]
+     75e:	0352      	lsls	r2, r2, #13
+     760:	04db      	lsls	r3, r3, #19
+     762:	0cdb      	lsrs	r3, r3, #19
+     764:	4313      	orrs	r3, r2
+     766:	8003      	strh	r3, [r0, #0]
+     768:	890b      	ldrh	r3, [r1, #8]
+     76a:	8043      	strh	r3, [r0, #2]
+     76c:	68cb      	ldr	r3, [r1, #12]
+     76e:	6043      	str	r3, [r0, #4]
+     770:	690b      	ldr	r3, [r1, #16]
+     772:	6083      	str	r3, [r0, #8]
+     774:	694b      	ldr	r3, [r1, #20]
+     776:	60c3      	str	r3, [r0, #12]
+     778:	bd70      	pop	{r4, r5, r6, pc}
+     77a:	46c0      	nop			; (mov r8, r8)
+     77c:	fffffcff 	.word	0xfffffcff
+     780:	fffffbff 	.word	0xfffffbff
+     784:	fffff7ff 	.word	0xfffff7ff
+     788:	ffffefff 	.word	0xffffefff
+
+0000078c <dma_add_descriptor>:
+     78c:	0002      	movs	r2, r0
+     78e:	7c43      	ldrb	r3, [r0, #17]
+     790:	2005      	movs	r0, #5
+     792:	4283      	cmp	r3, r0
+     794:	d004      	beq.n	7a0 <dma_add_descriptor+0x14>
+     796:	6993      	ldr	r3, [r2, #24]
+     798:	2b00      	cmp	r3, #0
+     79a:	d103      	bne.n	7a4 <dma_add_descriptor+0x18>
+     79c:	0018      	movs	r0, r3
+     79e:	6191      	str	r1, [r2, #24]
+     7a0:	4770      	bx	lr
+     7a2:	68db      	ldr	r3, [r3, #12]
+     7a4:	68d8      	ldr	r0, [r3, #12]
+     7a6:	2800      	cmp	r0, #0
+     7a8:	d1fb      	bne.n	7a2 <dma_add_descriptor+0x16>
+     7aa:	60d9      	str	r1, [r3, #12]
+     7ac:	e7f8      	b.n	7a0 <dma_add_descriptor+0x14>
+	...
+
+000007b0 <long_division>:
+     7b0:	b5f0      	push	{r4, r5, r6, r7, lr}
+     7b2:	2400      	movs	r4, #0
+     7b4:	b089      	sub	sp, #36	; 0x24
+     7b6:	9200      	str	r2, [sp, #0]
+     7b8:	9301      	str	r3, [sp, #4]
+     7ba:	233f      	movs	r3, #63	; 0x3f
+     7bc:	2600      	movs	r6, #0
+     7be:	2700      	movs	r7, #0
+     7c0:	0025      	movs	r5, r4
+     7c2:	9006      	str	r0, [sp, #24]
+     7c4:	9107      	str	r1, [sp, #28]
+     7c6:	9303      	str	r3, [sp, #12]
+     7c8:	9a03      	ldr	r2, [sp, #12]
+     7ca:	4b13      	ldr	r3, [pc, #76]	; (818 <long_division+0x68>)
+     7cc:	2001      	movs	r0, #1
+     7ce:	2100      	movs	r1, #0
+     7d0:	4798      	blx	r3
+     7d2:	19b6      	adds	r6, r6, r6
+     7d4:	417f      	adcs	r7, r7
+     7d6:	9b06      	ldr	r3, [sp, #24]
+     7d8:	9a07      	ldr	r2, [sp, #28]
+     7da:	4003      	ands	r3, r0
+     7dc:	400a      	ands	r2, r1
+     7de:	9604      	str	r6, [sp, #16]
+     7e0:	9705      	str	r7, [sp, #20]
+     7e2:	4313      	orrs	r3, r2
+     7e4:	d003      	beq.n	7ee <long_division+0x3e>
+     7e6:	2301      	movs	r3, #1
+     7e8:	4333      	orrs	r3, r6
+     7ea:	001e      	movs	r6, r3
+     7ec:	9f05      	ldr	r7, [sp, #20]
+     7ee:	9b01      	ldr	r3, [sp, #4]
+     7f0:	42bb      	cmp	r3, r7
+     7f2:	d809      	bhi.n	808 <long_division+0x58>
+     7f4:	d102      	bne.n	7fc <long_division+0x4c>
+     7f6:	9b00      	ldr	r3, [sp, #0]
+     7f8:	42b3      	cmp	r3, r6
+     7fa:	d805      	bhi.n	808 <long_division+0x58>
+     7fc:	9a00      	ldr	r2, [sp, #0]
+     7fe:	9b01      	ldr	r3, [sp, #4]
+     800:	1ab6      	subs	r6, r6, r2
+     802:	419f      	sbcs	r7, r3
+     804:	4304      	orrs	r4, r0
+     806:	430d      	orrs	r5, r1
+     808:	9b03      	ldr	r3, [sp, #12]
+     80a:	1e5a      	subs	r2, r3, #1
+     80c:	9203      	str	r2, [sp, #12]
+     80e:	d2db      	bcs.n	7c8 <long_division+0x18>
+     810:	0020      	movs	r0, r4
+     812:	0029      	movs	r1, r5
+     814:	b009      	add	sp, #36	; 0x24
+     816:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     818:	00002275 	.word	0x00002275
+
+0000081c <_sercom_get_sync_baud_val>:
+     81c:	b510      	push	{r4, lr}
+     81e:	0849      	lsrs	r1, r1, #1
+     820:	0004      	movs	r4, r0
+     822:	2300      	movs	r3, #0
+     824:	2040      	movs	r0, #64	; 0x40
+     826:	42a1      	cmp	r1, r4
+     828:	d201      	bcs.n	82e <_sercom_get_sync_baud_val+0x12>
+     82a:	bd10      	pop	{r4, pc}
+     82c:	0003      	movs	r3, r0
+     82e:	1c58      	adds	r0, r3, #1
+     830:	1b09      	subs	r1, r1, r4
+     832:	b280      	uxth	r0, r0
+     834:	428c      	cmp	r4, r1
+     836:	d9f9      	bls.n	82c <_sercom_get_sync_baud_val+0x10>
+     838:	2040      	movs	r0, #64	; 0x40
+     83a:	2bff      	cmp	r3, #255	; 0xff
+     83c:	d8f5      	bhi.n	82a <_sercom_get_sync_baud_val+0xe>
+     83e:	8013      	strh	r3, [r2, #0]
+     840:	2000      	movs	r0, #0
+     842:	e7f2      	b.n	82a <_sercom_get_sync_baud_val+0xe>
+
+00000844 <_sercom_get_async_baud_val>:
+     844:	b5f0      	push	{r4, r5, r6, r7, lr}
+     846:	b085      	sub	sp, #20
+     848:	001e      	movs	r6, r3
+     84a:	ab0a      	add	r3, sp, #40	; 0x28
+     84c:	000d      	movs	r5, r1
+     84e:	7819      	ldrb	r1, [r3, #0]
+     850:	0003      	movs	r3, r0
+     852:	434b      	muls	r3, r1
+     854:	9203      	str	r2, [sp, #12]
+     856:	2740      	movs	r7, #64	; 0x40
+     858:	42ab      	cmp	r3, r5
+     85a:	d817      	bhi.n	88c <_sercom_get_async_baud_val+0x48>
+     85c:	2e00      	cmp	r6, #0
+     85e:	d118      	bne.n	892 <_sercom_get_async_baud_val+0x4e>
+     860:	0002      	movs	r2, r0
+     862:	0033      	movs	r3, r6
+     864:	0008      	movs	r0, r1
+     866:	4c1b      	ldr	r4, [pc, #108]	; (8d4 <_sercom_get_async_baud_val+0x90>)
+     868:	0031      	movs	r1, r6
+     86a:	47a0      	blx	r4
+     86c:	002a      	movs	r2, r5
+     86e:	0001      	movs	r1, r0
+     870:	0033      	movs	r3, r6
+     872:	4c19      	ldr	r4, [pc, #100]	; (8d8 <_sercom_get_async_baud_val+0x94>)
+     874:	0030      	movs	r0, r6
+     876:	47a0      	blx	r4
+     878:	2200      	movs	r2, #0
+     87a:	2301      	movs	r3, #1
+     87c:	1a12      	subs	r2, r2, r0
+     87e:	418b      	sbcs	r3, r1
+     880:	0c14      	lsrs	r4, r2, #16
+     882:	0418      	lsls	r0, r3, #16
+     884:	4304      	orrs	r4, r0
+     886:	2700      	movs	r7, #0
+     888:	9b03      	ldr	r3, [sp, #12]
+     88a:	801c      	strh	r4, [r3, #0]
+     88c:	0038      	movs	r0, r7
+     88e:	b005      	add	sp, #20
+     890:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     892:	2400      	movs	r4, #0
+     894:	2e01      	cmp	r6, #1
+     896:	d1f6      	bne.n	886 <_sercom_get_async_baud_val+0x42>
+     898:	000a      	movs	r2, r1
+     89a:	0023      	movs	r3, r4
+     89c:	0021      	movs	r1, r4
+     89e:	4e0d      	ldr	r6, [pc, #52]	; (8d4 <_sercom_get_async_baud_val+0x90>)
+     8a0:	47b0      	blx	r6
+     8a2:	9000      	str	r0, [sp, #0]
+     8a4:	9101      	str	r1, [sp, #4]
+     8a6:	000b      	movs	r3, r1
+     8a8:	0002      	movs	r2, r0
+     8aa:	0021      	movs	r1, r4
+     8ac:	0028      	movs	r0, r5
+     8ae:	4c0a      	ldr	r4, [pc, #40]	; (8d8 <_sercom_get_async_baud_val+0x94>)
+     8b0:	47a0      	blx	r4
+     8b2:	2380      	movs	r3, #128	; 0x80
+     8b4:	0006      	movs	r6, r0
+     8b6:	019b      	lsls	r3, r3, #6
+     8b8:	4298      	cmp	r0, r3
+     8ba:	d8e7      	bhi.n	88c <_sercom_get_async_baud_val+0x48>
+     8bc:	9a00      	ldr	r2, [sp, #0]
+     8be:	9b01      	ldr	r3, [sp, #4]
+     8c0:	0f69      	lsrs	r1, r5, #29
+     8c2:	00e8      	lsls	r0, r5, #3
+     8c4:	47a0      	blx	r4
+     8c6:	00f4      	lsls	r4, r6, #3
+     8c8:	1b04      	subs	r4, r0, r4
+     8ca:	b2e4      	uxtb	r4, r4
+     8cc:	0364      	lsls	r4, r4, #13
+     8ce:	4334      	orrs	r4, r6
+     8d0:	e7d9      	b.n	886 <_sercom_get_async_baud_val+0x42>
+     8d2:	46c0      	nop			; (mov r8, r8)
+     8d4:	00002309 	.word	0x00002309
+     8d8:	000007b1 	.word	0x000007b1
+
+000008dc <sercom_set_gclk_generator>:
+     8dc:	b537      	push	{r0, r1, r2, r4, r5, lr}
+     8de:	4c0d      	ldr	r4, [pc, #52]	; (914 <sercom_set_gclk_generator+0x38>)
+     8e0:	0005      	movs	r5, r0
+     8e2:	7823      	ldrb	r3, [r4, #0]
+     8e4:	2b00      	cmp	r3, #0
+     8e6:	d001      	beq.n	8ec <sercom_set_gclk_generator+0x10>
+     8e8:	2900      	cmp	r1, #0
+     8ea:	d00c      	beq.n	906 <sercom_set_gclk_generator+0x2a>
+     8ec:	a901      	add	r1, sp, #4
+     8ee:	2013      	movs	r0, #19
+     8f0:	4b09      	ldr	r3, [pc, #36]	; (918 <sercom_set_gclk_generator+0x3c>)
+     8f2:	700d      	strb	r5, [r1, #0]
+     8f4:	4798      	blx	r3
+     8f6:	2013      	movs	r0, #19
+     8f8:	4b08      	ldr	r3, [pc, #32]	; (91c <sercom_set_gclk_generator+0x40>)
+     8fa:	4798      	blx	r3
+     8fc:	2301      	movs	r3, #1
+     8fe:	2000      	movs	r0, #0
+     900:	7065      	strb	r5, [r4, #1]
+     902:	7023      	strb	r3, [r4, #0]
+     904:	bd3e      	pop	{r1, r2, r3, r4, r5, pc}
+     906:	7863      	ldrb	r3, [r4, #1]
+     908:	0008      	movs	r0, r1
+     90a:	42ab      	cmp	r3, r5
+     90c:	d0fa      	beq.n	904 <sercom_set_gclk_generator+0x28>
+     90e:	201d      	movs	r0, #29
+     910:	e7f8      	b.n	904 <sercom_set_gclk_generator+0x28>
+     912:	46c0      	nop			; (mov r8, r8)
+     914:	20000105 	.word	0x20000105
+     918:	0000184d 	.word	0x0000184d
+     91c:	000017c5 	.word	0x000017c5
+
+00000920 <_sercom_get_default_pad>:
+     920:	4a39      	ldr	r2, [pc, #228]	; (a08 <_sercom_get_default_pad+0xe8>)
+     922:	0003      	movs	r3, r0
+     924:	b500      	push	{lr}
+     926:	0008      	movs	r0, r1
+     928:	4293      	cmp	r3, r2
+     92a:	d033      	beq.n	994 <_sercom_get_default_pad+0x74>
+     92c:	d807      	bhi.n	93e <_sercom_get_default_pad+0x1e>
+     92e:	4a37      	ldr	r2, [pc, #220]	; (a0c <_sercom_get_default_pad+0xec>)
+     930:	4293      	cmp	r3, r2
+     932:	d014      	beq.n	95e <_sercom_get_default_pad+0x3e>
+     934:	4a36      	ldr	r2, [pc, #216]	; (a10 <_sercom_get_default_pad+0xf0>)
+     936:	4293      	cmp	r3, r2
+     938:	d01f      	beq.n	97a <_sercom_get_default_pad+0x5a>
+     93a:	2300      	movs	r3, #0
+     93c:	e017      	b.n	96e <_sercom_get_default_pad+0x4e>
+     93e:	4a35      	ldr	r2, [pc, #212]	; (a14 <_sercom_get_default_pad+0xf4>)
+     940:	4293      	cmp	r3, r2
+     942:	d03a      	beq.n	9ba <_sercom_get_default_pad+0x9a>
+     944:	4a34      	ldr	r2, [pc, #208]	; (a18 <_sercom_get_default_pad+0xf8>)
+     946:	4293      	cmp	r3, r2
+     948:	d044      	beq.n	9d4 <_sercom_get_default_pad+0xb4>
+     94a:	4a34      	ldr	r2, [pc, #208]	; (a1c <_sercom_get_default_pad+0xfc>)
+     94c:	4293      	cmp	r3, r2
+     94e:	d1f4      	bne.n	93a <_sercom_get_default_pad+0x1a>
+     950:	2300      	movs	r3, #0
+     952:	2903      	cmp	r1, #3
+     954:	d80b      	bhi.n	96e <_sercom_get_default_pad+0x4e>
+     956:	f001 fbf7 	bl	2148 <__gnu_thumb1_case_uqi>
+     95a:	2a50      	.short	0x2a50
+     95c:	2e2c      	.short	0x2e2c
+     95e:	2300      	movs	r3, #0
+     960:	2903      	cmp	r1, #3
+     962:	d804      	bhi.n	96e <_sercom_get_default_pad+0x4e>
+     964:	f001 fbf0 	bl	2148 <__gnu_thumb1_case_uqi>
+     968:	07050243 	.word	0x07050243
+     96c:	4b2c      	ldr	r3, [pc, #176]	; (a20 <_sercom_get_default_pad+0x100>)
+     96e:	0018      	movs	r0, r3
+     970:	bd00      	pop	{pc}
+     972:	4b2c      	ldr	r3, [pc, #176]	; (a24 <_sercom_get_default_pad+0x104>)
+     974:	e7fb      	b.n	96e <_sercom_get_default_pad+0x4e>
+     976:	4b2c      	ldr	r3, [pc, #176]	; (a28 <_sercom_get_default_pad+0x108>)
+     978:	e7f9      	b.n	96e <_sercom_get_default_pad+0x4e>
+     97a:	2300      	movs	r3, #0
+     97c:	2903      	cmp	r1, #3
+     97e:	d8f6      	bhi.n	96e <_sercom_get_default_pad+0x4e>
+     980:	f001 fbe2 	bl	2148 <__gnu_thumb1_case_uqi>
+     984:	06040237 	.word	0x06040237
+     988:	4b28      	ldr	r3, [pc, #160]	; (a2c <_sercom_get_default_pad+0x10c>)
+     98a:	e7f0      	b.n	96e <_sercom_get_default_pad+0x4e>
+     98c:	4b28      	ldr	r3, [pc, #160]	; (a30 <_sercom_get_default_pad+0x110>)
+     98e:	e7ee      	b.n	96e <_sercom_get_default_pad+0x4e>
+     990:	4b28      	ldr	r3, [pc, #160]	; (a34 <_sercom_get_default_pad+0x114>)
+     992:	e7ec      	b.n	96e <_sercom_get_default_pad+0x4e>
+     994:	2300      	movs	r3, #0
+     996:	2903      	cmp	r1, #3
+     998:	d8e9      	bhi.n	96e <_sercom_get_default_pad+0x4e>
+     99a:	f001 fbd5 	bl	2148 <__gnu_thumb1_case_uqi>
+     99e:	022c      	.short	0x022c
+     9a0:	0604      	.short	0x0604
+     9a2:	4b25      	ldr	r3, [pc, #148]	; (a38 <_sercom_get_default_pad+0x118>)
+     9a4:	e7e3      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9a6:	4b25      	ldr	r3, [pc, #148]	; (a3c <_sercom_get_default_pad+0x11c>)
+     9a8:	e7e1      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9aa:	4b25      	ldr	r3, [pc, #148]	; (a40 <_sercom_get_default_pad+0x120>)
+     9ac:	e7df      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9ae:	4b25      	ldr	r3, [pc, #148]	; (a44 <_sercom_get_default_pad+0x124>)
+     9b0:	e7dd      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9b2:	4b25      	ldr	r3, [pc, #148]	; (a48 <_sercom_get_default_pad+0x128>)
+     9b4:	e7db      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9b6:	4b25      	ldr	r3, [pc, #148]	; (a4c <_sercom_get_default_pad+0x12c>)
+     9b8:	e7d9      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9ba:	2300      	movs	r3, #0
+     9bc:	2903      	cmp	r1, #3
+     9be:	d8d6      	bhi.n	96e <_sercom_get_default_pad+0x4e>
+     9c0:	f001 fbc2 	bl	2148 <__gnu_thumb1_case_uqi>
+     9c4:	0604021d 	.word	0x0604021d
+     9c8:	4b21      	ldr	r3, [pc, #132]	; (a50 <_sercom_get_default_pad+0x130>)
+     9ca:	e7d0      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9cc:	4b21      	ldr	r3, [pc, #132]	; (a54 <_sercom_get_default_pad+0x134>)
+     9ce:	e7ce      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9d0:	4b21      	ldr	r3, [pc, #132]	; (a58 <_sercom_get_default_pad+0x138>)
+     9d2:	e7cc      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9d4:	2300      	movs	r3, #0
+     9d6:	2903      	cmp	r1, #3
+     9d8:	d8c9      	bhi.n	96e <_sercom_get_default_pad+0x4e>
+     9da:	f001 fbb5 	bl	2148 <__gnu_thumb1_case_uqi>
+     9de:	0212      	.short	0x0212
+     9e0:	0604      	.short	0x0604
+     9e2:	4b1e      	ldr	r3, [pc, #120]	; (a5c <_sercom_get_default_pad+0x13c>)
+     9e4:	e7c3      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9e6:	4b1e      	ldr	r3, [pc, #120]	; (a60 <_sercom_get_default_pad+0x140>)
+     9e8:	e7c1      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9ea:	4b1e      	ldr	r3, [pc, #120]	; (a64 <_sercom_get_default_pad+0x144>)
+     9ec:	e7bf      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9ee:	4b1e      	ldr	r3, [pc, #120]	; (a68 <_sercom_get_default_pad+0x148>)
+     9f0:	e7bd      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9f2:	2303      	movs	r3, #3
+     9f4:	e7bb      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9f6:	4b1d      	ldr	r3, [pc, #116]	; (a6c <_sercom_get_default_pad+0x14c>)
+     9f8:	e7b9      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9fa:	4b1d      	ldr	r3, [pc, #116]	; (a70 <_sercom_get_default_pad+0x150>)
+     9fc:	e7b7      	b.n	96e <_sercom_get_default_pad+0x4e>
+     9fe:	4b1d      	ldr	r3, [pc, #116]	; (a74 <_sercom_get_default_pad+0x154>)
+     a00:	e7b5      	b.n	96e <_sercom_get_default_pad+0x4e>
+     a02:	4b1d      	ldr	r3, [pc, #116]	; (a78 <_sercom_get_default_pad+0x158>)
+     a04:	e7b3      	b.n	96e <_sercom_get_default_pad+0x4e>
+     a06:	46c0      	nop			; (mov r8, r8)
+     a08:	42001000 	.word	0x42001000
+     a0c:	42000800 	.word	0x42000800
+     a10:	42000c00 	.word	0x42000c00
+     a14:	42001800 	.word	0x42001800
+     a18:	42001c00 	.word	0x42001c00
+     a1c:	42001400 	.word	0x42001400
+     a20:	00050003 	.word	0x00050003
+     a24:	00060003 	.word	0x00060003
+     a28:	00070003 	.word	0x00070003
+     a2c:	00010003 	.word	0x00010003
+     a30:	001e0003 	.word	0x001e0003
+     a34:	001f0003 	.word	0x001f0003
+     a38:	00090003 	.word	0x00090003
+     a3c:	000a0003 	.word	0x000a0003
+     a40:	000b0003 	.word	0x000b0003
+     a44:	00110003 	.word	0x00110003
+     a48:	00120003 	.word	0x00120003
+     a4c:	00130003 	.word	0x00130003
+     a50:	000d0003 	.word	0x000d0003
+     a54:	000e0003 	.word	0x000e0003
+     a58:	000f0003 	.word	0x000f0003
+     a5c:	00170003 	.word	0x00170003
+     a60:	00180003 	.word	0x00180003
+     a64:	00190003 	.word	0x00190003
+     a68:	00040003 	.word	0x00040003
+     a6c:	00080003 	.word	0x00080003
+     a70:	00100003 	.word	0x00100003
+     a74:	000c0003 	.word	0x000c0003
+     a78:	00160003 	.word	0x00160003
+
+00000a7c <_sercom_get_sercom_inst_index>:
+     a7c:	b570      	push	{r4, r5, r6, lr}
+     a7e:	b086      	sub	sp, #24
+     a80:	4669      	mov	r1, sp
+     a82:	4b09      	ldr	r3, [pc, #36]	; (aa8 <_sercom_get_sercom_inst_index+0x2c>)
+     a84:	466a      	mov	r2, sp
+     a86:	cb70      	ldmia	r3!, {r4, r5, r6}
+     a88:	c170      	stmia	r1!, {r4, r5, r6}
+     a8a:	cb70      	ldmia	r3!, {r4, r5, r6}
+     a8c:	c170      	stmia	r1!, {r4, r5, r6}
+     a8e:	2300      	movs	r3, #0
+     a90:	0099      	lsls	r1, r3, #2
+     a92:	5851      	ldr	r1, [r2, r1]
+     a94:	4281      	cmp	r1, r0
+     a96:	d102      	bne.n	a9e <_sercom_get_sercom_inst_index+0x22>
+     a98:	b2d8      	uxtb	r0, r3
+     a9a:	b006      	add	sp, #24
+     a9c:	bd70      	pop	{r4, r5, r6, pc}
+     a9e:	3301      	adds	r3, #1
+     aa0:	2b06      	cmp	r3, #6
+     aa2:	d1f5      	bne.n	a90 <_sercom_get_sercom_inst_index+0x14>
+     aa4:	2000      	movs	r0, #0
+     aa6:	e7f8      	b.n	a9a <_sercom_get_sercom_inst_index+0x1e>
+     aa8:	00005940 	.word	0x00005940
+
+00000aac <_read>:
+     aac:	b570      	push	{r4, r5, r6, lr}
+     aae:	000e      	movs	r6, r1
+     ab0:	0014      	movs	r4, r2
+     ab2:	0015      	movs	r5, r2
+     ab4:	2800      	cmp	r0, #0
+     ab6:	d008      	beq.n	aca <_read+0x1e>
+     ab8:	2001      	movs	r0, #1
+     aba:	4240      	negs	r0, r0
+     abc:	e00c      	b.n	ad8 <_read+0x2c>
+     abe:	4b07      	ldr	r3, [pc, #28]	; (adc <_read+0x30>)
+     ac0:	3d01      	subs	r5, #1
+     ac2:	6818      	ldr	r0, [r3, #0]
+     ac4:	4b06      	ldr	r3, [pc, #24]	; (ae0 <_read+0x34>)
+     ac6:	681b      	ldr	r3, [r3, #0]
+     ac8:	4798      	blx	r3
+     aca:	1b61      	subs	r1, r4, r5
+     acc:	1871      	adds	r1, r6, r1
+     ace:	2d00      	cmp	r5, #0
+     ad0:	dcf5      	bgt.n	abe <_read+0x12>
+     ad2:	43e0      	mvns	r0, r4
+     ad4:	17c0      	asrs	r0, r0, #31
+     ad6:	4020      	ands	r0, r4
+     ad8:	bd70      	pop	{r4, r5, r6, pc}
+     ada:	46c0      	nop			; (mov r8, r8)
+     adc:	20000238 	.word	0x20000238
+     ae0:	20000230 	.word	0x20000230
+
+00000ae4 <_write>:
+     ae4:	3801      	subs	r0, #1
+     ae6:	b570      	push	{r4, r5, r6, lr}
+     ae8:	000e      	movs	r6, r1
+     aea:	2802      	cmp	r0, #2
+     aec:	d80d      	bhi.n	b0a <_write+0x26>
+     aee:	000c      	movs	r4, r1
+     af0:	188d      	adds	r5, r1, r2
+     af2:	1ba0      	subs	r0, r4, r6
+     af4:	42ac      	cmp	r4, r5
+     af6:	d00a      	beq.n	b0e <_write+0x2a>
+     af8:	4b05      	ldr	r3, [pc, #20]	; (b10 <_write+0x2c>)
+     afa:	7821      	ldrb	r1, [r4, #0]
+     afc:	6818      	ldr	r0, [r3, #0]
+     afe:	4b05      	ldr	r3, [pc, #20]	; (b14 <_write+0x30>)
+     b00:	3401      	adds	r4, #1
+     b02:	681b      	ldr	r3, [r3, #0]
+     b04:	4798      	blx	r3
+     b06:	2800      	cmp	r0, #0
+     b08:	daf3      	bge.n	af2 <_write+0xe>
+     b0a:	2001      	movs	r0, #1
+     b0c:	4240      	negs	r0, r0
+     b0e:	bd70      	pop	{r4, r5, r6, pc}
+     b10:	20000238 	.word	0x20000238
+     b14:	20000234 	.word	0x20000234
+
+00000b18 <padc_init>:
+     b18:	b570      	push	{r4, r5, r6, lr}
+     b1a:	b094      	sub	sp, #80	; 0x50
+     b1c:	ac08      	add	r4, sp, #32
+     b1e:	0020      	movs	r0, r4
+     b20:	4b28      	ldr	r3, [pc, #160]	; (bc4 <padc_init+0xac>)
+     b22:	4798      	blx	r3
+     b24:	2104      	movs	r1, #4
+     b26:	2280      	movs	r2, #128	; 0x80
+     b28:	7321      	strb	r1, [r4, #12]
+     b2a:	21c0      	movs	r1, #192	; 0xc0
+     b2c:	2300      	movs	r3, #0
+     b2e:	4d26      	ldr	r5, [pc, #152]	; (bc8 <padc_init+0xb0>)
+     b30:	0052      	lsls	r2, r2, #1
+     b32:	8062      	strh	r2, [r4, #2]
+     b34:	0149      	lsls	r1, r1, #5
+     b36:	3aff      	subs	r2, #255	; 0xff
+     b38:	60a3      	str	r3, [r4, #8]
+     b3a:	7123      	strb	r3, [r4, #4]
+     b3c:	7062      	strb	r2, [r4, #1]
+     b3e:	81e1      	strh	r1, [r4, #14]
+     b40:	7522      	strb	r2, [r4, #20]
+     b42:	74a3      	strb	r3, [r4, #18]
+     b44:	0022      	movs	r2, r4
+     b46:	4b21      	ldr	r3, [pc, #132]	; (bcc <padc_init+0xb4>)
+     b48:	4921      	ldr	r1, [pc, #132]	; (bd0 <padc_init+0xb8>)
+     b4a:	0028      	movs	r0, r5
+     b4c:	4798      	blx	r3
+     b4e:	682b      	ldr	r3, [r5, #0]
+     b50:	7e5a      	ldrb	r2, [r3, #25]
+     b52:	b252      	sxtb	r2, r2
+     b54:	2a00      	cmp	r2, #0
+     b56:	dbfb      	blt.n	b50 <padc_init+0x38>
+     b58:	220f      	movs	r2, #15
+     b5a:	759a      	strb	r2, [r3, #22]
+     b5c:	761a      	strb	r2, [r3, #24]
+     b5e:	7819      	ldrb	r1, [r3, #0]
+     b60:	3a0d      	subs	r2, #13
+     b62:	430a      	orrs	r2, r1
+     b64:	701a      	strb	r2, [r3, #0]
+     b66:	682a      	ldr	r2, [r5, #0]
+     b68:	7e53      	ldrb	r3, [r2, #25]
+     b6a:	b25b      	sxtb	r3, r3
+     b6c:	2b00      	cmp	r3, #0
+     b6e:	dbfb      	blt.n	b68 <padc_init+0x50>
+     b70:	4668      	mov	r0, sp
+     b72:	4b18      	ldr	r3, [pc, #96]	; (bd4 <padc_init+0xbc>)
+     b74:	4798      	blx	r3
+     b76:	466a      	mov	r2, sp
+     b78:	2327      	movs	r3, #39	; 0x27
+     b7a:	2400      	movs	r4, #0
+     b7c:	4e16      	ldr	r6, [pc, #88]	; (bd8 <padc_init+0xc0>)
+     b7e:	4669      	mov	r1, sp
+     b80:	7053      	strb	r3, [r2, #1]
+     b82:	0030      	movs	r0, r6
+     b84:	4b15      	ldr	r3, [pc, #84]	; (bdc <padc_init+0xc4>)
+     b86:	7094      	strb	r4, [r2, #2]
+     b88:	4798      	blx	r3
+     b8a:	2301      	movs	r3, #1
+     b8c:	a902      	add	r1, sp, #8
+     b8e:	700b      	strb	r3, [r1, #0]
+     b90:	714b      	strb	r3, [r1, #5]
+     b92:	70cb      	strb	r3, [r1, #3]
+     b94:	330f      	adds	r3, #15
+     b96:	810b      	strh	r3, [r1, #8]
+     b98:	682b      	ldr	r3, [r5, #0]
+     b9a:	704c      	strb	r4, [r1, #1]
+     b9c:	331a      	adds	r3, #26
+     b9e:	60cb      	str	r3, [r1, #12]
+     ba0:	4b0f      	ldr	r3, [pc, #60]	; (be0 <padc_init+0xc8>)
+     ba2:	708c      	strb	r4, [r1, #2]
+     ba4:	718c      	strb	r4, [r1, #6]
+     ba6:	71cc      	strb	r4, [r1, #7]
+     ba8:	710c      	strb	r4, [r1, #4]
+     baa:	4c0e      	ldr	r4, [pc, #56]	; (be4 <padc_init+0xcc>)
+     bac:	3320      	adds	r3, #32
+     bae:	610b      	str	r3, [r1, #16]
+     bb0:	0020      	movs	r0, r4
+     bb2:	4b0d      	ldr	r3, [pc, #52]	; (be8 <padc_init+0xd0>)
+     bb4:	614c      	str	r4, [r1, #20]
+     bb6:	4798      	blx	r3
+     bb8:	0021      	movs	r1, r4
+     bba:	0030      	movs	r0, r6
+     bbc:	4b0b      	ldr	r3, [pc, #44]	; (bec <padc_init+0xd4>)
+     bbe:	4798      	blx	r3
+     bc0:	b014      	add	sp, #80	; 0x50
+     bc2:	bd70      	pop	{r4, r5, r6, pc}
+     bc4:	00000155 	.word	0x00000155
+     bc8:	20000108 	.word	0x20000108
+     bcc:	00000199 	.word	0x00000199
+     bd0:	42004000 	.word	0x42004000
+     bd4:	0000051d 	.word	0x0000051d
+     bd8:	20000110 	.word	0x20000110
+     bdc:	0000052d 	.word	0x0000052d
+     be0:	2000012c 	.word	0x2000012c
+     be4:	20000240 	.word	0x20000240
+     be8:	000006e5 	.word	0x000006e5
+     bec:	0000078d 	.word	0x0000078d
+
+00000bf0 <padc_start>:
+     bf0:	b510      	push	{r4, lr}
+     bf2:	4b09      	ldr	r3, [pc, #36]	; (c18 <padc_start+0x28>)
+     bf4:	681b      	ldr	r3, [r3, #0]
+     bf6:	7e5a      	ldrb	r2, [r3, #25]
+     bf8:	b252      	sxtb	r2, r2
+     bfa:	2a00      	cmp	r2, #0
+     bfc:	dbfb      	blt.n	bf6 <padc_start+0x6>
+     bfe:	2202      	movs	r2, #2
+     c00:	7b19      	ldrb	r1, [r3, #12]
+     c02:	430a      	orrs	r2, r1
+     c04:	731a      	strb	r2, [r3, #12]
+     c06:	7e5a      	ldrb	r2, [r3, #25]
+     c08:	b252      	sxtb	r2, r2
+     c0a:	2a00      	cmp	r2, #0
+     c0c:	dbfb      	blt.n	c06 <padc_start+0x16>
+     c0e:	4803      	ldr	r0, [pc, #12]	; (c1c <padc_start+0x2c>)
+     c10:	4b03      	ldr	r3, [pc, #12]	; (c20 <padc_start+0x30>)
+     c12:	4798      	blx	r3
+     c14:	bd10      	pop	{r4, pc}
+     c16:	46c0      	nop			; (mov r8, r8)
+     c18:	20000108 	.word	0x20000108
+     c1c:	20000110 	.word	0x20000110
+     c20:	00000659 	.word	0x00000659
+
+00000c24 <padc_get_raw>:
+     c24:	2300      	movs	r3, #0
+     c26:	0018      	movs	r0, r3
+     c28:	4904      	ldr	r1, [pc, #16]	; (c3c <padc_get_raw+0x18>)
+     c2a:	5a5a      	ldrh	r2, [r3, r1]
+     c2c:	3302      	adds	r3, #2
+     c2e:	1880      	adds	r0, r0, r2
+     c30:	2b20      	cmp	r3, #32
+     c32:	d1fa      	bne.n	c2a <padc_get_raw+0x6>
+     c34:	0900      	lsrs	r0, r0, #4
+     c36:	b280      	uxth	r0, r0
+     c38:	4770      	bx	lr
+     c3a:	46c0      	nop			; (mov r8, r8)
+     c3c:	2000012c 	.word	0x2000012c
+
+00000c40 <padc_get_voltage>:
+     c40:	b510      	push	{r4, lr}
+     c42:	4b04      	ldr	r3, [pc, #16]	; (c54 <padc_get_voltage+0x14>)
+     c44:	4798      	blx	r3
+     c46:	4b04      	ldr	r3, [pc, #16]	; (c58 <padc_get_voltage+0x18>)
+     c48:	4798      	blx	r3
+     c4a:	4904      	ldr	r1, [pc, #16]	; (c5c <padc_get_voltage+0x1c>)
+     c4c:	4b04      	ldr	r3, [pc, #16]	; (c60 <padc_get_voltage+0x20>)
+     c4e:	4798      	blx	r3
+     c50:	bd10      	pop	{r4, pc}
+     c52:	46c0      	nop			; (mov r8, r8)
+     c54:	00000c25 	.word	0x00000c25
+     c58:	000029f1 	.word	0x000029f1
+     c5c:	3a0cf909 	.word	0x3a0cf909
+     c60:	00002399 	.word	0x00002399
+
+00000c64 <usart_serial_getchar>:
+     c64:	b573      	push	{r0, r1, r4, r5, r6, lr}
+     c66:	466b      	mov	r3, sp
+     c68:	1d9c      	adds	r4, r3, #6
+     c6a:	2300      	movs	r3, #0
+     c6c:	0006      	movs	r6, r0
+     c6e:	000d      	movs	r5, r1
+     c70:	8023      	strh	r3, [r4, #0]
+     c72:	0021      	movs	r1, r4
+     c74:	0030      	movs	r0, r6
+     c76:	4b03      	ldr	r3, [pc, #12]	; (c84 <usart_serial_getchar+0x20>)
+     c78:	4798      	blx	r3
+     c7a:	2800      	cmp	r0, #0
+     c7c:	d1f9      	bne.n	c72 <usart_serial_getchar+0xe>
+     c7e:	8823      	ldrh	r3, [r4, #0]
+     c80:	702b      	strb	r3, [r5, #0]
+     c82:	bd73      	pop	{r0, r1, r4, r5, r6, pc}
+     c84:	00001073 	.word	0x00001073
+
+00000c88 <usart_serial_putchar>:
+     c88:	b570      	push	{r4, r5, r6, lr}
+     c8a:	0004      	movs	r4, r0
+     c8c:	000d      	movs	r5, r1
+     c8e:	b2a9      	uxth	r1, r5
+     c90:	0020      	movs	r0, r4
+     c92:	4b02      	ldr	r3, [pc, #8]	; (c9c <usart_serial_putchar+0x14>)
+     c94:	4798      	blx	r3
+     c96:	2800      	cmp	r0, #0
+     c98:	d1f9      	bne.n	c8e <usart_serial_putchar+0x6>
+     c9a:	bd70      	pop	{r4, r5, r6, pc}
+     c9c:	00001051 	.word	0x00001051
+
+00000ca0 <pusart_init>:
+     ca0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+     ca2:	2380      	movs	r3, #128	; 0x80
+     ca4:	4a2d      	ldr	r2, [pc, #180]	; (d5c <pusart_init+0xbc>)
+     ca6:	05db      	lsls	r3, r3, #23
+     ca8:	6013      	str	r3, [r2, #0]
+     caa:	23ff      	movs	r3, #255	; 0xff
+     cac:	2501      	movs	r5, #1
+     cae:	2400      	movs	r4, #0
+     cb0:	8113      	strh	r3, [r2, #8]
+     cb2:	1d53      	adds	r3, r2, #5
+     cb4:	77dd      	strb	r5, [r3, #31]
+     cb6:	1d93      	adds	r3, r2, #6
+     cb8:	77dd      	strb	r5, [r3, #31]
+     cba:	1dd3      	adds	r3, r2, #7
+     cbc:	77dc      	strb	r4, [r3, #31]
+     cbe:	0013      	movs	r3, r2
+     cc0:	3308      	adds	r3, #8
+     cc2:	77dc      	strb	r4, [r3, #31]
+     cc4:	0013      	movs	r3, r2
+     cc6:	332c      	adds	r3, #44	; 0x2c
+     cc8:	701c      	strb	r4, [r3, #0]
+     cca:	0013      	movs	r3, r2
+     ccc:	332d      	adds	r3, #45	; 0x2d
+     cce:	701c      	strb	r4, [r3, #0]
+     cd0:	2313      	movs	r3, #19
+     cd2:	7693      	strb	r3, [r2, #26]
+     cd4:	4b22      	ldr	r3, [pc, #136]	; (d60 <pusart_init+0xc0>)
+     cd6:	4e23      	ldr	r6, [pc, #140]	; (d64 <pusart_init+0xc4>)
+     cd8:	6313      	str	r3, [r2, #48]	; 0x30
+     cda:	4b23      	ldr	r3, [pc, #140]	; (d68 <pusart_init+0xc8>)
+     cdc:	6054      	str	r4, [r2, #4]
+     cde:	6353      	str	r3, [r2, #52]	; 0x34
+     ce0:	2301      	movs	r3, #1
+     ce2:	425b      	negs	r3, r3
+     ce4:	6393      	str	r3, [r2, #56]	; 0x38
+     ce6:	63d3      	str	r3, [r2, #60]	; 0x3c
+     ce8:	2380      	movs	r3, #128	; 0x80
+     cea:	035b      	lsls	r3, r3, #13
+     cec:	60d3      	str	r3, [r2, #12]
+     cee:	23e1      	movs	r3, #225	; 0xe1
+     cf0:	025b      	lsls	r3, r3, #9
+     cf2:	6213      	str	r3, [r2, #32]
+     cf4:	4b1d      	ldr	r3, [pc, #116]	; (d6c <pusart_init+0xcc>)
+     cf6:	7294      	strb	r4, [r2, #10]
+     cf8:	72d4      	strb	r4, [r2, #11]
+     cfa:	6294      	str	r4, [r2, #40]	; 0x28
+     cfc:	6154      	str	r4, [r2, #20]
+     cfe:	8214      	strh	r4, [r2, #16]
+     d00:	76d4      	strb	r4, [r2, #27]
+     d02:	7614      	strb	r4, [r2, #24]
+     d04:	7714      	strb	r4, [r2, #28]
+     d06:	7654      	strb	r4, [r2, #25]
+     d08:	7754      	strb	r4, [r2, #29]
+     d0a:	4919      	ldr	r1, [pc, #100]	; (d70 <pusart_init+0xd0>)
+     d0c:	601e      	str	r6, [r3, #0]
+     d0e:	4b19      	ldr	r3, [pc, #100]	; (d74 <pusart_init+0xd4>)
+     d10:	0030      	movs	r0, r6
+     d12:	6019      	str	r1, [r3, #0]
+     d14:	4918      	ldr	r1, [pc, #96]	; (d78 <pusart_init+0xd8>)
+     d16:	4b19      	ldr	r3, [pc, #100]	; (d7c <pusart_init+0xdc>)
+     d18:	6019      	str	r1, [r3, #0]
+     d1a:	4919      	ldr	r1, [pc, #100]	; (d80 <pusart_init+0xe0>)
+     d1c:	4b19      	ldr	r3, [pc, #100]	; (d84 <pusart_init+0xe4>)
+     d1e:	4798      	blx	r3
+     d20:	4f19      	ldr	r7, [pc, #100]	; (d88 <pusart_init+0xe8>)
+     d22:	0021      	movs	r1, r4
+     d24:	683b      	ldr	r3, [r7, #0]
+     d26:	6898      	ldr	r0, [r3, #8]
+     d28:	4b18      	ldr	r3, [pc, #96]	; (d8c <pusart_init+0xec>)
+     d2a:	4798      	blx	r3
+     d2c:	683b      	ldr	r3, [r7, #0]
+     d2e:	0021      	movs	r1, r4
+     d30:	6858      	ldr	r0, [r3, #4]
+     d32:	4b16      	ldr	r3, [pc, #88]	; (d8c <pusart_init+0xec>)
+     d34:	4798      	blx	r3
+     d36:	6834      	ldr	r4, [r6, #0]
+     d38:	4b15      	ldr	r3, [pc, #84]	; (d90 <pusart_init+0xf0>)
+     d3a:	0020      	movs	r0, r4
+     d3c:	4798      	blx	r3
+     d3e:	231f      	movs	r3, #31
+     d40:	4018      	ands	r0, r3
+     d42:	4085      	lsls	r5, r0
+     d44:	4b13      	ldr	r3, [pc, #76]	; (d94 <pusart_init+0xf4>)
+     d46:	601d      	str	r5, [r3, #0]
+     d48:	6832      	ldr	r2, [r6, #0]
+     d4a:	69d3      	ldr	r3, [r2, #28]
+     d4c:	2b00      	cmp	r3, #0
+     d4e:	d1fc      	bne.n	d4a <pusart_init+0xaa>
+     d50:	6822      	ldr	r2, [r4, #0]
+     d52:	3302      	adds	r3, #2
+     d54:	4313      	orrs	r3, r2
+     d56:	6023      	str	r3, [r4, #0]
+     d58:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+     d5a:	46c0      	nop			; (mov r8, r8)
+     d5c:	2000014c 	.word	0x2000014c
+     d60:	00160002 	.word	0x00160002
+     d64:	20000250 	.word	0x20000250
+     d68:	00170002 	.word	0x00170002
+     d6c:	20000238 	.word	0x20000238
+     d70:	00000c89 	.word	0x00000c89
+     d74:	20000234 	.word	0x20000234
+     d78:	00000c65 	.word	0x00000c65
+     d7c:	20000230 	.word	0x20000230
+     d80:	42001400 	.word	0x42001400
+     d84:	00000d99 	.word	0x00000d99
+     d88:	20000018 	.word	0x20000018
+     d8c:	00004941 	.word	0x00004941
+     d90:	00001281 	.word	0x00001281
+     d94:	e000e100 	.word	0xe000e100
+
+00000d98 <usart_init>:
+     d98:	b5f0      	push	{r4, r5, r6, r7, lr}
+     d9a:	0007      	movs	r7, r0
+     d9c:	b093      	sub	sp, #76	; 0x4c
+     d9e:	4b9e      	ldr	r3, [pc, #632]	; (1018 <usart_init+0x280>)
+     da0:	6039      	str	r1, [r7, #0]
+     da2:	0008      	movs	r0, r1
+     da4:	0014      	movs	r4, r2
+     da6:	9104      	str	r1, [sp, #16]
+     da8:	4798      	blx	r3
+     daa:	2201      	movs	r2, #1
+     dac:	9b04      	ldr	r3, [sp, #16]
+     dae:	0006      	movs	r6, r0
+     db0:	681b      	ldr	r3, [r3, #0]
+     db2:	2005      	movs	r0, #5
+     db4:	4213      	tst	r3, r2
+     db6:	d000      	beq.n	dba <usart_init+0x22>
+     db8:	e10a      	b.n	fd0 <usart_init+0x238>
+     dba:	9b04      	ldr	r3, [sp, #16]
+     dbc:	3017      	adds	r0, #23
+     dbe:	681d      	ldr	r5, [r3, #0]
+     dc0:	2302      	movs	r3, #2
+     dc2:	401d      	ands	r5, r3
+     dc4:	d000      	beq.n	dc8 <usart_init+0x30>
+     dc6:	e103      	b.n	fd0 <usart_init+0x238>
+     dc8:	18f3      	adds	r3, r6, r3
+     dca:	381b      	subs	r0, #27
+     dcc:	4098      	lsls	r0, r3
+     dce:	0003      	movs	r3, r0
+     dd0:	4a92      	ldr	r2, [pc, #584]	; (101c <usart_init+0x284>)
+     dd2:	3614      	adds	r6, #20
+     dd4:	6a11      	ldr	r1, [r2, #32]
+     dd6:	b2f6      	uxtb	r6, r6
+     dd8:	430b      	orrs	r3, r1
+     dda:	6213      	str	r3, [r2, #32]
+     ddc:	0023      	movs	r3, r4
+     dde:	332d      	adds	r3, #45	; 0x2d
+     de0:	9302      	str	r3, [sp, #8]
+     de2:	781b      	ldrb	r3, [r3, #0]
+     de4:	a90c      	add	r1, sp, #48	; 0x30
+     de6:	700b      	strb	r3, [r1, #0]
+     de8:	0030      	movs	r0, r6
+     dea:	4b8d      	ldr	r3, [pc, #564]	; (1020 <usart_init+0x288>)
+     dec:	4798      	blx	r3
+     dee:	0030      	movs	r0, r6
+     df0:	4b8c      	ldr	r3, [pc, #560]	; (1024 <usart_init+0x28c>)
+     df2:	4798      	blx	r3
+     df4:	9b02      	ldr	r3, [sp, #8]
+     df6:	0029      	movs	r1, r5
+     df8:	7818      	ldrb	r0, [r3, #0]
+     dfa:	4b8b      	ldr	r3, [pc, #556]	; (1028 <usart_init+0x290>)
+     dfc:	4798      	blx	r3
+     dfe:	7ae3      	ldrb	r3, [r4, #11]
+     e00:	2608      	movs	r6, #8
+     e02:	717b      	strb	r3, [r7, #5]
+     e04:	1d63      	adds	r3, r4, #5
+     e06:	7fdb      	ldrb	r3, [r3, #31]
+     e08:	71bb      	strb	r3, [r7, #6]
+     e0a:	1da3      	adds	r3, r4, #6
+     e0c:	7fdb      	ldrb	r3, [r3, #31]
+     e0e:	71fb      	strb	r3, [r7, #7]
+     e10:	7ee3      	ldrb	r3, [r4, #27]
+     e12:	723b      	strb	r3, [r7, #8]
+     e14:	7f23      	ldrb	r3, [r4, #28]
+     e16:	727b      	strb	r3, [r7, #9]
+     e18:	683b      	ldr	r3, [r7, #0]
+     e1a:	9303      	str	r3, [sp, #12]
+     e1c:	0018      	movs	r0, r3
+     e1e:	4b7e      	ldr	r3, [pc, #504]	; (1018 <usart_init+0x280>)
+     e20:	4798      	blx	r3
+     e22:	ab0e      	add	r3, sp, #56	; 0x38
+     e24:	801d      	strh	r5, [r3, #0]
+     e26:	8a23      	ldrh	r3, [r4, #16]
+     e28:	3014      	adds	r0, #20
+     e2a:	9302      	str	r3, [sp, #8]
+     e2c:	2380      	movs	r3, #128	; 0x80
+     e2e:	9a02      	ldr	r2, [sp, #8]
+     e30:	01db      	lsls	r3, r3, #7
+     e32:	429a      	cmp	r2, r3
+     e34:	d014      	beq.n	e60 <usart_init+0xc8>
+     e36:	d808      	bhi.n	e4a <usart_init+0xb2>
+     e38:	2380      	movs	r3, #128	; 0x80
+     e3a:	2610      	movs	r6, #16
+     e3c:	019b      	lsls	r3, r3, #6
+     e3e:	429a      	cmp	r2, r3
+     e40:	d100      	bne.n	e44 <usart_init+0xac>
+     e42:	e0c8      	b.n	fd6 <usart_init+0x23e>
+     e44:	2610      	movs	r6, #16
+     e46:	2500      	movs	r5, #0
+     e48:	e00a      	b.n	e60 <usart_init+0xc8>
+     e4a:	23c0      	movs	r3, #192	; 0xc0
+     e4c:	9a02      	ldr	r2, [sp, #8]
+     e4e:	01db      	lsls	r3, r3, #7
+     e50:	429a      	cmp	r2, r3
+     e52:	d100      	bne.n	e56 <usart_init+0xbe>
+     e54:	e0be      	b.n	fd4 <usart_init+0x23c>
+     e56:	2380      	movs	r3, #128	; 0x80
+     e58:	2603      	movs	r6, #3
+     e5a:	021b      	lsls	r3, r3, #8
+     e5c:	429a      	cmp	r2, r3
+     e5e:	d1f1      	bne.n	e44 <usart_init+0xac>
+     e60:	6823      	ldr	r3, [r4, #0]
+     e62:	9306      	str	r3, [sp, #24]
+     e64:	68e3      	ldr	r3, [r4, #12]
+     e66:	9307      	str	r3, [sp, #28]
+     e68:	6963      	ldr	r3, [r4, #20]
+     e6a:	9308      	str	r3, [sp, #32]
+     e6c:	7e23      	ldrb	r3, [r4, #24]
+     e6e:	9309      	str	r3, [sp, #36]	; 0x24
+     e70:	1de3      	adds	r3, r4, #7
+     e72:	7fdb      	ldrb	r3, [r3, #31]
+     e74:	930a      	str	r3, [sp, #40]	; 0x28
+     e76:	6863      	ldr	r3, [r4, #4]
+     e78:	9305      	str	r3, [sp, #20]
+     e7a:	0023      	movs	r3, r4
+     e7c:	9a05      	ldr	r2, [sp, #20]
+     e7e:	3308      	adds	r3, #8
+     e80:	2a00      	cmp	r2, #0
+     e82:	d100      	bne.n	e86 <usart_init+0xee>
+     e84:	e0a9      	b.n	fda <usart_init+0x242>
+     e86:	2280      	movs	r2, #128	; 0x80
+     e88:	9905      	ldr	r1, [sp, #20]
+     e8a:	0552      	lsls	r2, r2, #21
+     e8c:	4291      	cmp	r1, r2
+     e8e:	d10e      	bne.n	eae <usart_init+0x116>
+     e90:	7fdb      	ldrb	r3, [r3, #31]
+     e92:	2b00      	cmp	r3, #0
+     e94:	d10b      	bne.n	eae <usart_init+0x116>
+     e96:	4b65      	ldr	r3, [pc, #404]	; (102c <usart_init+0x294>)
+     e98:	b2c0      	uxtb	r0, r0
+     e9a:	6a25      	ldr	r5, [r4, #32]
+     e9c:	4798      	blx	r3
+     e9e:	aa0e      	add	r2, sp, #56	; 0x38
+     ea0:	0001      	movs	r1, r0
+     ea2:	4b63      	ldr	r3, [pc, #396]	; (1030 <usart_init+0x298>)
+     ea4:	0028      	movs	r0, r5
+     ea6:	4798      	blx	r3
+     ea8:	2800      	cmp	r0, #0
+     eaa:	d000      	beq.n	eae <usart_init+0x116>
+     eac:	e090      	b.n	fd0 <usart_init+0x238>
+     eae:	7e63      	ldrb	r3, [r4, #25]
+     eb0:	2b00      	cmp	r3, #0
+     eb2:	d002      	beq.n	eba <usart_init+0x122>
+     eb4:	7ea3      	ldrb	r3, [r4, #26]
+     eb6:	9a03      	ldr	r2, [sp, #12]
+     eb8:	7393      	strb	r3, [r2, #14]
+     eba:	ae0e      	add	r6, sp, #56	; 0x38
+     ebc:	8833      	ldrh	r3, [r6, #0]
+     ebe:	9a03      	ldr	r2, [sp, #12]
+     ec0:	8193      	strh	r3, [r2, #12]
+     ec2:	9a07      	ldr	r2, [sp, #28]
+     ec4:	9b06      	ldr	r3, [sp, #24]
+     ec6:	4313      	orrs	r3, r2
+     ec8:	9a08      	ldr	r2, [sp, #32]
+     eca:	4313      	orrs	r3, r2
+     ecc:	9a05      	ldr	r2, [sp, #20]
+     ece:	4313      	orrs	r3, r2
+     ed0:	9a02      	ldr	r2, [sp, #8]
+     ed2:	4313      	orrs	r3, r2
+     ed4:	9a09      	ldr	r2, [sp, #36]	; 0x24
+     ed6:	0212      	lsls	r2, r2, #8
+     ed8:	4313      	orrs	r3, r2
+     eda:	9a0a      	ldr	r2, [sp, #40]	; 0x28
+     edc:	0752      	lsls	r2, r2, #29
+     ede:	4313      	orrs	r3, r2
+     ee0:	0022      	movs	r2, r4
+     ee2:	3208      	adds	r2, #8
+     ee4:	7fd2      	ldrb	r2, [r2, #31]
+     ee6:	2a00      	cmp	r2, #0
+     ee8:	d101      	bne.n	eee <usart_init+0x156>
+     eea:	3204      	adds	r2, #4
+     eec:	4313      	orrs	r3, r2
+     eee:	7e62      	ldrb	r2, [r4, #25]
+     ef0:	7f21      	ldrb	r1, [r4, #28]
+     ef2:	0292      	lsls	r2, r2, #10
+     ef4:	0249      	lsls	r1, r1, #9
+     ef6:	430a      	orrs	r2, r1
+     ef8:	7f61      	ldrb	r1, [r4, #29]
+     efa:	7ae0      	ldrb	r0, [r4, #11]
+     efc:	0209      	lsls	r1, r1, #8
+     efe:	430a      	orrs	r2, r1
+     f00:	1d61      	adds	r1, r4, #5
+     f02:	7fc9      	ldrb	r1, [r1, #31]
+     f04:	0449      	lsls	r1, r1, #17
+     f06:	430a      	orrs	r2, r1
+     f08:	1da1      	adds	r1, r4, #6
+     f0a:	7fc9      	ldrb	r1, [r1, #31]
+     f0c:	0409      	lsls	r1, r1, #16
+     f0e:	430a      	orrs	r2, r1
+     f10:	7aa1      	ldrb	r1, [r4, #10]
+     f12:	4301      	orrs	r1, r0
+     f14:	430a      	orrs	r2, r1
+     f16:	8921      	ldrh	r1, [r4, #8]
+     f18:	29ff      	cmp	r1, #255	; 0xff
+     f1a:	d100      	bne.n	f1e <usart_init+0x186>
+     f1c:	e073      	b.n	1006 <usart_init+0x26e>
+     f1e:	2080      	movs	r0, #128	; 0x80
+     f20:	0440      	lsls	r0, r0, #17
+     f22:	4303      	orrs	r3, r0
+     f24:	430a      	orrs	r2, r1
+     f26:	0021      	movs	r1, r4
+     f28:	312c      	adds	r1, #44	; 0x2c
+     f2a:	7809      	ldrb	r1, [r1, #0]
+     f2c:	2900      	cmp	r1, #0
+     f2e:	d103      	bne.n	f38 <usart_init+0x1a0>
+     f30:	4940      	ldr	r1, [pc, #256]	; (1034 <usart_init+0x29c>)
+     f32:	7889      	ldrb	r1, [r1, #2]
+     f34:	0789      	lsls	r1, r1, #30
+     f36:	d501      	bpl.n	f3c <usart_init+0x1a4>
+     f38:	2180      	movs	r1, #128	; 0x80
+     f3a:	430b      	orrs	r3, r1
+     f3c:	6838      	ldr	r0, [r7, #0]
+     f3e:	69c1      	ldr	r1, [r0, #28]
+     f40:	2900      	cmp	r1, #0
+     f42:	d1fc      	bne.n	f3e <usart_init+0x1a6>
+     f44:	9903      	ldr	r1, [sp, #12]
+     f46:	604a      	str	r2, [r1, #4]
+     f48:	6839      	ldr	r1, [r7, #0]
+     f4a:	69ca      	ldr	r2, [r1, #28]
+     f4c:	2a00      	cmp	r2, #0
+     f4e:	d1fc      	bne.n	f4a <usart_init+0x1b2>
+     f50:	9903      	ldr	r1, [sp, #12]
+     f52:	ad0d      	add	r5, sp, #52	; 0x34
+     f54:	600b      	str	r3, [r1, #0]
+     f56:	2380      	movs	r3, #128	; 0x80
+     f58:	702b      	strb	r3, [r5, #0]
+     f5a:	6b23      	ldr	r3, [r4, #48]	; 0x30
+     f5c:	706a      	strb	r2, [r5, #1]
+     f5e:	930e      	str	r3, [sp, #56]	; 0x38
+     f60:	6b63      	ldr	r3, [r4, #52]	; 0x34
+     f62:	70ea      	strb	r2, [r5, #3]
+     f64:	6073      	str	r3, [r6, #4]
+     f66:	6ba3      	ldr	r3, [r4, #56]	; 0x38
+     f68:	70aa      	strb	r2, [r5, #2]
+     f6a:	60b3      	str	r3, [r6, #8]
+     f6c:	6be3      	ldr	r3, [r4, #60]	; 0x3c
+     f6e:	0014      	movs	r4, r2
+     f70:	60f3      	str	r3, [r6, #12]
+     f72:	00a3      	lsls	r3, r4, #2
+     f74:	58f0      	ldr	r0, [r6, r3]
+     f76:	b2e1      	uxtb	r1, r4
+     f78:	2800      	cmp	r0, #0
+     f7a:	d102      	bne.n	f82 <usart_init+0x1ea>
+     f7c:	9804      	ldr	r0, [sp, #16]
+     f7e:	4b2e      	ldr	r3, [pc, #184]	; (1038 <usart_init+0x2a0>)
+     f80:	4798      	blx	r3
+     f82:	1c43      	adds	r3, r0, #1
+     f84:	d005      	beq.n	f92 <usart_init+0x1fa>
+     f86:	7028      	strb	r0, [r5, #0]
+     f88:	0c00      	lsrs	r0, r0, #16
+     f8a:	b2c0      	uxtb	r0, r0
+     f8c:	0029      	movs	r1, r5
+     f8e:	4b2b      	ldr	r3, [pc, #172]	; (103c <usart_init+0x2a4>)
+     f90:	4798      	blx	r3
+     f92:	3401      	adds	r4, #1
+     f94:	2c04      	cmp	r4, #4
+     f96:	d1ec      	bne.n	f72 <usart_init+0x1da>
+     f98:	003b      	movs	r3, r7
+     f9a:	2400      	movs	r4, #0
+     f9c:	3330      	adds	r3, #48	; 0x30
+     f9e:	85fc      	strh	r4, [r7, #46]	; 0x2e
+     fa0:	60fc      	str	r4, [r7, #12]
+     fa2:	613c      	str	r4, [r7, #16]
+     fa4:	617c      	str	r4, [r7, #20]
+     fa6:	61bc      	str	r4, [r7, #24]
+     fa8:	61fc      	str	r4, [r7, #28]
+     faa:	623c      	str	r4, [r7, #32]
+     fac:	62bc      	str	r4, [r7, #40]	; 0x28
+     fae:	627c      	str	r4, [r7, #36]	; 0x24
+     fb0:	85bc      	strh	r4, [r7, #44]	; 0x2c
+     fb2:	709c      	strb	r4, [r3, #2]
+     fb4:	701c      	strb	r4, [r3, #0]
+     fb6:	705c      	strb	r4, [r3, #1]
+     fb8:	70dc      	strb	r4, [r3, #3]
+     fba:	6838      	ldr	r0, [r7, #0]
+     fbc:	4b16      	ldr	r3, [pc, #88]	; (1018 <usart_init+0x280>)
+     fbe:	4798      	blx	r3
+     fc0:	0005      	movs	r5, r0
+     fc2:	4b1f      	ldr	r3, [pc, #124]	; (1040 <usart_init+0x2a8>)
+     fc4:	491f      	ldr	r1, [pc, #124]	; (1044 <usart_init+0x2ac>)
+     fc6:	4798      	blx	r3
+     fc8:	0020      	movs	r0, r4
+     fca:	4b1f      	ldr	r3, [pc, #124]	; (1048 <usart_init+0x2b0>)
+     fcc:	00ad      	lsls	r5, r5, #2
+     fce:	50ef      	str	r7, [r5, r3]
+     fd0:	b013      	add	sp, #76	; 0x4c
+     fd2:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     fd4:	2608      	movs	r6, #8
+     fd6:	2501      	movs	r5, #1
+     fd8:	e742      	b.n	e60 <usart_init+0xc8>
+     fda:	7fdb      	ldrb	r3, [r3, #31]
+     fdc:	2b00      	cmp	r3, #0
+     fde:	d007      	beq.n	ff0 <usart_init+0x258>
+     fe0:	002b      	movs	r3, r5
+     fe2:	9600      	str	r6, [sp, #0]
+     fe4:	6aa1      	ldr	r1, [r4, #40]	; 0x28
+     fe6:	6a20      	ldr	r0, [r4, #32]
+     fe8:	aa0e      	add	r2, sp, #56	; 0x38
+     fea:	4d18      	ldr	r5, [pc, #96]	; (104c <usart_init+0x2b4>)
+     fec:	47a8      	blx	r5
+     fee:	e75b      	b.n	ea8 <usart_init+0x110>
+     ff0:	6a23      	ldr	r3, [r4, #32]
+     ff2:	b2c0      	uxtb	r0, r0
+     ff4:	930b      	str	r3, [sp, #44]	; 0x2c
+     ff6:	4b0d      	ldr	r3, [pc, #52]	; (102c <usart_init+0x294>)
+     ff8:	4798      	blx	r3
+     ffa:	9600      	str	r6, [sp, #0]
+     ffc:	0001      	movs	r1, r0
+     ffe:	002b      	movs	r3, r5
+    1000:	aa0e      	add	r2, sp, #56	; 0x38
+    1002:	980b      	ldr	r0, [sp, #44]	; 0x2c
+    1004:	e7f1      	b.n	fea <usart_init+0x252>
+    1006:	7ee1      	ldrb	r1, [r4, #27]
+    1008:	2900      	cmp	r1, #0
+    100a:	d100      	bne.n	100e <usart_init+0x276>
+    100c:	e78b      	b.n	f26 <usart_init+0x18e>
+    100e:	2180      	movs	r1, #128	; 0x80
+    1010:	04c9      	lsls	r1, r1, #19
+    1012:	430b      	orrs	r3, r1
+    1014:	e787      	b.n	f26 <usart_init+0x18e>
+    1016:	46c0      	nop			; (mov r8, r8)
+    1018:	00000a7d 	.word	0x00000a7d
+    101c:	40000400 	.word	0x40000400
+    1020:	0000184d 	.word	0x0000184d
+    1024:	000017c5 	.word	0x000017c5
+    1028:	000008dd 	.word	0x000008dd
+    102c:	00001869 	.word	0x00001869
+    1030:	0000081d 	.word	0x0000081d
+    1034:	41002000 	.word	0x41002000
+    1038:	00000921 	.word	0x00000921
+    103c:	00001921 	.word	0x00001921
+    1040:	00001249 	.word	0x00001249
+    1044:	000010dd 	.word	0x000010dd
+    1048:	20000284 	.word	0x20000284
+    104c:	00000845 	.word	0x00000845
+
+00001050 <usart_write_wait>:
+    1050:	79c2      	ldrb	r2, [r0, #7]
+    1052:	231c      	movs	r3, #28
+    1054:	2a00      	cmp	r2, #0
+    1056:	d00a      	beq.n	106e <usart_write_wait+0x1e>
+    1058:	8dc2      	ldrh	r2, [r0, #46]	; 0x2e
+    105a:	3b17      	subs	r3, #23
+    105c:	2a00      	cmp	r2, #0
+    105e:	d106      	bne.n	106e <usart_write_wait+0x1e>
+    1060:	6803      	ldr	r3, [r0, #0]
+    1062:	3202      	adds	r2, #2
+    1064:	8519      	strh	r1, [r3, #40]	; 0x28
+    1066:	7e19      	ldrb	r1, [r3, #24]
+    1068:	4211      	tst	r1, r2
+    106a:	d0fc      	beq.n	1066 <usart_write_wait+0x16>
+    106c:	2300      	movs	r3, #0
+    106e:	0018      	movs	r0, r3
+    1070:	4770      	bx	lr
+
+00001072 <usart_read_wait>:
+    1072:	b510      	push	{r4, lr}
+    1074:	7982      	ldrb	r2, [r0, #6]
+    1076:	231c      	movs	r3, #28
+    1078:	2a00      	cmp	r2, #0
+    107a:	d011      	beq.n	10a0 <usart_read_wait+0x2e>
+    107c:	8d82      	ldrh	r2, [r0, #44]	; 0x2c
+    107e:	3b17      	subs	r3, #23
+    1080:	2a00      	cmp	r2, #0
+    1082:	d10d      	bne.n	10a0 <usart_read_wait+0x2e>
+    1084:	6802      	ldr	r2, [r0, #0]
+    1086:	2004      	movs	r0, #4
+    1088:	7e14      	ldrb	r4, [r2, #24]
+    108a:	4204      	tst	r4, r0
+    108c:	d008      	beq.n	10a0 <usart_read_wait+0x2e>
+    108e:	8b53      	ldrh	r3, [r2, #26]
+    1090:	b2db      	uxtb	r3, r3
+    1092:	069c      	lsls	r4, r3, #26
+    1094:	d01d      	beq.n	10d2 <usart_read_wait+0x60>
+    1096:	2402      	movs	r4, #2
+    1098:	4223      	tst	r3, r4
+    109a:	d003      	beq.n	10a4 <usart_read_wait+0x32>
+    109c:	231a      	movs	r3, #26
+    109e:	8354      	strh	r4, [r2, #26]
+    10a0:	0018      	movs	r0, r3
+    10a2:	bd10      	pop	{r4, pc}
+    10a4:	4203      	tst	r3, r0
+    10a6:	d002      	beq.n	10ae <usart_read_wait+0x3c>
+    10a8:	8350      	strh	r0, [r2, #26]
+    10aa:	231e      	movs	r3, #30
+    10ac:	e7f8      	b.n	10a0 <usart_read_wait+0x2e>
+    10ae:	2001      	movs	r0, #1
+    10b0:	4203      	tst	r3, r0
+    10b2:	d002      	beq.n	10ba <usart_read_wait+0x48>
+    10b4:	8350      	strh	r0, [r2, #26]
+    10b6:	2313      	movs	r3, #19
+    10b8:	e7f2      	b.n	10a0 <usart_read_wait+0x2e>
+    10ba:	2010      	movs	r0, #16
+    10bc:	4203      	tst	r3, r0
+    10be:	d002      	beq.n	10c6 <usart_read_wait+0x54>
+    10c0:	8350      	strh	r0, [r2, #26]
+    10c2:	2342      	movs	r3, #66	; 0x42
+    10c4:	e7ec      	b.n	10a0 <usart_read_wait+0x2e>
+    10c6:	2020      	movs	r0, #32
+    10c8:	4203      	tst	r3, r0
+    10ca:	d002      	beq.n	10d2 <usart_read_wait+0x60>
+    10cc:	8350      	strh	r0, [r2, #26]
+    10ce:	2341      	movs	r3, #65	; 0x41
+    10d0:	e7e6      	b.n	10a0 <usart_read_wait+0x2e>
+    10d2:	8d13      	ldrh	r3, [r2, #40]	; 0x28
+    10d4:	800b      	strh	r3, [r1, #0]
+    10d6:	2300      	movs	r3, #0
+    10d8:	e7e2      	b.n	10a0 <usart_read_wait+0x2e>
+	...
+
+000010dc <_usart_interrupt_handler>:
+    10dc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    10de:	4b58      	ldr	r3, [pc, #352]	; (1240 <_usart_interrupt_handler+0x164>)
+    10e0:	0080      	lsls	r0, r0, #2
+    10e2:	58c4      	ldr	r4, [r0, r3]
+    10e4:	6825      	ldr	r5, [r4, #0]
+    10e6:	69eb      	ldr	r3, [r5, #28]
+    10e8:	2b00      	cmp	r3, #0
+    10ea:	d1fc      	bne.n	10e6 <_usart_interrupt_handler+0xa>
+    10ec:	7e2b      	ldrb	r3, [r5, #24]
+    10ee:	7daf      	ldrb	r7, [r5, #22]
+    10f0:	401f      	ands	r7, r3
+    10f2:	0023      	movs	r3, r4
+    10f4:	3330      	adds	r3, #48	; 0x30
+    10f6:	781a      	ldrb	r2, [r3, #0]
+    10f8:	785e      	ldrb	r6, [r3, #1]
+    10fa:	2301      	movs	r3, #1
+    10fc:	4016      	ands	r6, r2
+    10fe:	421f      	tst	r7, r3
+    1100:	d019      	beq.n	1136 <_usart_interrupt_handler+0x5a>
+    1102:	8de2      	ldrh	r2, [r4, #46]	; 0x2e
+    1104:	2a00      	cmp	r2, #0
+    1106:	d100      	bne.n	110a <_usart_interrupt_handler+0x2e>
+    1108:	e072      	b.n	11f0 <_usart_interrupt_handler+0x114>
+    110a:	6aa2      	ldr	r2, [r4, #40]	; 0x28
+    110c:	1c51      	adds	r1, r2, #1
+    110e:	7813      	ldrb	r3, [r2, #0]
+    1110:	62a1      	str	r1, [r4, #40]	; 0x28
+    1112:	7961      	ldrb	r1, [r4, #5]
+    1114:	b2db      	uxtb	r3, r3
+    1116:	2901      	cmp	r1, #1
+    1118:	d064      	beq.n	11e4 <_usart_interrupt_handler+0x108>
+    111a:	b29b      	uxth	r3, r3
+    111c:	05db      	lsls	r3, r3, #23
+    111e:	0ddb      	lsrs	r3, r3, #23
+    1120:	852b      	strh	r3, [r5, #40]	; 0x28
+    1122:	8de3      	ldrh	r3, [r4, #46]	; 0x2e
+    1124:	3b01      	subs	r3, #1
+    1126:	b29b      	uxth	r3, r3
+    1128:	85e3      	strh	r3, [r4, #46]	; 0x2e
+    112a:	2b00      	cmp	r3, #0
+    112c:	d103      	bne.n	1136 <_usart_interrupt_handler+0x5a>
+    112e:	3301      	adds	r3, #1
+    1130:	752b      	strb	r3, [r5, #20]
+    1132:	3301      	adds	r3, #1
+    1134:	75ab      	strb	r3, [r5, #22]
+    1136:	2302      	movs	r3, #2
+    1138:	421f      	tst	r7, r3
+    113a:	d009      	beq.n	1150 <_usart_interrupt_handler+0x74>
+    113c:	752b      	strb	r3, [r5, #20]
+    113e:	0023      	movs	r3, r4
+    1140:	2200      	movs	r2, #0
+    1142:	3333      	adds	r3, #51	; 0x33
+    1144:	701a      	strb	r2, [r3, #0]
+    1146:	07f3      	lsls	r3, r6, #31
+    1148:	d502      	bpl.n	1150 <_usart_interrupt_handler+0x74>
+    114a:	0020      	movs	r0, r4
+    114c:	68e3      	ldr	r3, [r4, #12]
+    114e:	4798      	blx	r3
+    1150:	2304      	movs	r3, #4
+    1152:	421f      	tst	r7, r3
+    1154:	d027      	beq.n	11a6 <_usart_interrupt_handler+0xca>
+    1156:	8da2      	ldrh	r2, [r4, #44]	; 0x2c
+    1158:	2a00      	cmp	r2, #0
+    115a:	d100      	bne.n	115e <_usart_interrupt_handler+0x82>
+    115c:	e06d      	b.n	123a <_usart_interrupt_handler+0x15e>
+    115e:	8b6b      	ldrh	r3, [r5, #26]
+    1160:	b2db      	uxtb	r3, r3
+    1162:	071a      	lsls	r2, r3, #28
+    1164:	d446      	bmi.n	11f4 <_usart_interrupt_handler+0x118>
+    1166:	223f      	movs	r2, #63	; 0x3f
+    1168:	4013      	ands	r3, r2
+    116a:	d045      	beq.n	11f8 <_usart_interrupt_handler+0x11c>
+    116c:	2202      	movs	r2, #2
+    116e:	211a      	movs	r1, #26
+    1170:	4213      	tst	r3, r2
+    1172:	d10f      	bne.n	1194 <_usart_interrupt_handler+0xb8>
+    1174:	2204      	movs	r2, #4
+    1176:	211e      	movs	r1, #30
+    1178:	4213      	tst	r3, r2
+    117a:	d10b      	bne.n	1194 <_usart_interrupt_handler+0xb8>
+    117c:	2201      	movs	r2, #1
+    117e:	2113      	movs	r1, #19
+    1180:	4213      	tst	r3, r2
+    1182:	d107      	bne.n	1194 <_usart_interrupt_handler+0xb8>
+    1184:	2210      	movs	r2, #16
+    1186:	2142      	movs	r1, #66	; 0x42
+    1188:	4213      	tst	r3, r2
+    118a:	d103      	bne.n	1194 <_usart_interrupt_handler+0xb8>
+    118c:	2220      	movs	r2, #32
+    118e:	4213      	tst	r3, r2
+    1190:	d004      	beq.n	119c <_usart_interrupt_handler+0xc0>
+    1192:	2141      	movs	r1, #65	; 0x41
+    1194:	0023      	movs	r3, r4
+    1196:	3332      	adds	r3, #50	; 0x32
+    1198:	7019      	strb	r1, [r3, #0]
+    119a:	836a      	strh	r2, [r5, #26]
+    119c:	0773      	lsls	r3, r6, #29
+    119e:	d502      	bpl.n	11a6 <_usart_interrupt_handler+0xca>
+    11a0:	0020      	movs	r0, r4
+    11a2:	6963      	ldr	r3, [r4, #20]
+    11a4:	4798      	blx	r3
+    11a6:	2310      	movs	r3, #16
+    11a8:	421f      	tst	r7, r3
+    11aa:	d006      	beq.n	11ba <_usart_interrupt_handler+0xde>
+    11ac:	752b      	strb	r3, [r5, #20]
+    11ae:	762b      	strb	r3, [r5, #24]
+    11b0:	421e      	tst	r6, r3
+    11b2:	d002      	beq.n	11ba <_usart_interrupt_handler+0xde>
+    11b4:	0020      	movs	r0, r4
+    11b6:	69e3      	ldr	r3, [r4, #28]
+    11b8:	4798      	blx	r3
+    11ba:	2320      	movs	r3, #32
+    11bc:	421f      	tst	r7, r3
+    11be:	d006      	beq.n	11ce <_usart_interrupt_handler+0xf2>
+    11c0:	752b      	strb	r3, [r5, #20]
+    11c2:	762b      	strb	r3, [r5, #24]
+    11c4:	0733      	lsls	r3, r6, #28
+    11c6:	d502      	bpl.n	11ce <_usart_interrupt_handler+0xf2>
+    11c8:	0020      	movs	r0, r4
+    11ca:	69a3      	ldr	r3, [r4, #24]
+    11cc:	4798      	blx	r3
+    11ce:	2308      	movs	r3, #8
+    11d0:	421f      	tst	r7, r3
+    11d2:	d006      	beq.n	11e2 <_usart_interrupt_handler+0x106>
+    11d4:	752b      	strb	r3, [r5, #20]
+    11d6:	762b      	strb	r3, [r5, #24]
+    11d8:	06b3      	lsls	r3, r6, #26
+    11da:	d502      	bpl.n	11e2 <_usart_interrupt_handler+0x106>
+    11dc:	6a23      	ldr	r3, [r4, #32]
+    11de:	0020      	movs	r0, r4
+    11e0:	4798      	blx	r3
+    11e2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    11e4:	7851      	ldrb	r1, [r2, #1]
+    11e6:	3202      	adds	r2, #2
+    11e8:	0209      	lsls	r1, r1, #8
+    11ea:	430b      	orrs	r3, r1
+    11ec:	62a2      	str	r2, [r4, #40]	; 0x28
+    11ee:	e795      	b.n	111c <_usart_interrupt_handler+0x40>
+    11f0:	752b      	strb	r3, [r5, #20]
+    11f2:	e7a0      	b.n	1136 <_usart_interrupt_handler+0x5a>
+    11f4:	2237      	movs	r2, #55	; 0x37
+    11f6:	e7b7      	b.n	1168 <_usart_interrupt_handler+0x8c>
+    11f8:	8d2b      	ldrh	r3, [r5, #40]	; 0x28
+    11fa:	6a61      	ldr	r1, [r4, #36]	; 0x24
+    11fc:	05db      	lsls	r3, r3, #23
+    11fe:	0ddb      	lsrs	r3, r3, #23
+    1200:	b2da      	uxtb	r2, r3
+    1202:	700a      	strb	r2, [r1, #0]
+    1204:	6a62      	ldr	r2, [r4, #36]	; 0x24
+    1206:	1c51      	adds	r1, r2, #1
+    1208:	6261      	str	r1, [r4, #36]	; 0x24
+    120a:	7961      	ldrb	r1, [r4, #5]
+    120c:	2901      	cmp	r1, #1
+    120e:	d104      	bne.n	121a <_usart_interrupt_handler+0x13e>
+    1210:	0a1b      	lsrs	r3, r3, #8
+    1212:	7053      	strb	r3, [r2, #1]
+    1214:	6a63      	ldr	r3, [r4, #36]	; 0x24
+    1216:	3301      	adds	r3, #1
+    1218:	6263      	str	r3, [r4, #36]	; 0x24
+    121a:	8da3      	ldrh	r3, [r4, #44]	; 0x2c
+    121c:	3b01      	subs	r3, #1
+    121e:	b29b      	uxth	r3, r3
+    1220:	85a3      	strh	r3, [r4, #44]	; 0x2c
+    1222:	2b00      	cmp	r3, #0
+    1224:	d1bf      	bne.n	11a6 <_usart_interrupt_handler+0xca>
+    1226:	2204      	movs	r2, #4
+    1228:	752a      	strb	r2, [r5, #20]
+    122a:	0022      	movs	r2, r4
+    122c:	3232      	adds	r2, #50	; 0x32
+    122e:	7013      	strb	r3, [r2, #0]
+    1230:	07b3      	lsls	r3, r6, #30
+    1232:	d5b8      	bpl.n	11a6 <_usart_interrupt_handler+0xca>
+    1234:	0020      	movs	r0, r4
+    1236:	6923      	ldr	r3, [r4, #16]
+    1238:	e7b4      	b.n	11a4 <_usart_interrupt_handler+0xc8>
+    123a:	752b      	strb	r3, [r5, #20]
+    123c:	e7b3      	b.n	11a6 <_usart_interrupt_handler+0xca>
+    123e:	46c0      	nop			; (mov r8, r8)
+    1240:	20000284 	.word	0x20000284
+
+00001244 <_sercom_default_handler>:
+    1244:	4770      	bx	lr
+	...
+
+00001248 <_sercom_set_handler>:
+    1248:	b5f0      	push	{r4, r5, r6, r7, lr}
+    124a:	4c09      	ldr	r4, [pc, #36]	; (1270 <_sercom_set_handler+0x28>)
+    124c:	4a09      	ldr	r2, [pc, #36]	; (1274 <_sercom_set_handler+0x2c>)
+    124e:	7823      	ldrb	r3, [r4, #0]
+    1250:	2b00      	cmp	r3, #0
+    1252:	d109      	bne.n	1268 <_sercom_set_handler+0x20>
+    1254:	001e      	movs	r6, r3
+    1256:	4f08      	ldr	r7, [pc, #32]	; (1278 <_sercom_set_handler+0x30>)
+    1258:	4d08      	ldr	r5, [pc, #32]	; (127c <_sercom_set_handler+0x34>)
+    125a:	50d7      	str	r7, [r2, r3]
+    125c:	50ee      	str	r6, [r5, r3]
+    125e:	3304      	adds	r3, #4
+    1260:	2b18      	cmp	r3, #24
+    1262:	d1fa      	bne.n	125a <_sercom_set_handler+0x12>
+    1264:	3b17      	subs	r3, #23
+    1266:	7023      	strb	r3, [r4, #0]
+    1268:	0080      	lsls	r0, r0, #2
+    126a:	5011      	str	r1, [r2, r0]
+    126c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    126e:	46c0      	nop			; (mov r8, r8)
+    1270:	2000018c 	.word	0x2000018c
+    1274:	20000190 	.word	0x20000190
+    1278:	00001245 	.word	0x00001245
+    127c:	20000284 	.word	0x20000284
+
+00001280 <_sercom_get_interrupt_vector>:
+    1280:	b507      	push	{r0, r1, r2, lr}
+    1282:	2309      	movs	r3, #9
+    1284:	466a      	mov	r2, sp
+    1286:	7013      	strb	r3, [r2, #0]
+    1288:	3301      	adds	r3, #1
+    128a:	7053      	strb	r3, [r2, #1]
+    128c:	3301      	adds	r3, #1
+    128e:	7093      	strb	r3, [r2, #2]
+    1290:	3301      	adds	r3, #1
+    1292:	70d3      	strb	r3, [r2, #3]
+    1294:	3301      	adds	r3, #1
+    1296:	7113      	strb	r3, [r2, #4]
+    1298:	3301      	adds	r3, #1
+    129a:	7153      	strb	r3, [r2, #5]
+    129c:	4b02      	ldr	r3, [pc, #8]	; (12a8 <_sercom_get_interrupt_vector+0x28>)
+    129e:	4798      	blx	r3
+    12a0:	466b      	mov	r3, sp
+    12a2:	5618      	ldrsb	r0, [r3, r0]
+    12a4:	bd0e      	pop	{r1, r2, r3, pc}
+    12a6:	46c0      	nop			; (mov r8, r8)
+    12a8:	00000a7d 	.word	0x00000a7d
+
+000012ac <SERCOM0_Handler>:
+    12ac:	b510      	push	{r4, lr}
+    12ae:	4b02      	ldr	r3, [pc, #8]	; (12b8 <SERCOM0_Handler+0xc>)
+    12b0:	2000      	movs	r0, #0
+    12b2:	681b      	ldr	r3, [r3, #0]
+    12b4:	4798      	blx	r3
+    12b6:	bd10      	pop	{r4, pc}
+    12b8:	20000190 	.word	0x20000190
+
+000012bc <SERCOM1_Handler>:
+    12bc:	b510      	push	{r4, lr}
+    12be:	4b02      	ldr	r3, [pc, #8]	; (12c8 <SERCOM1_Handler+0xc>)
+    12c0:	2001      	movs	r0, #1
+    12c2:	685b      	ldr	r3, [r3, #4]
+    12c4:	4798      	blx	r3
+    12c6:	bd10      	pop	{r4, pc}
+    12c8:	20000190 	.word	0x20000190
+
+000012cc <SERCOM2_Handler>:
+    12cc:	b510      	push	{r4, lr}
+    12ce:	4b02      	ldr	r3, [pc, #8]	; (12d8 <SERCOM2_Handler+0xc>)
+    12d0:	2002      	movs	r0, #2
+    12d2:	689b      	ldr	r3, [r3, #8]
+    12d4:	4798      	blx	r3
+    12d6:	bd10      	pop	{r4, pc}
+    12d8:	20000190 	.word	0x20000190
+
+000012dc <SERCOM3_Handler>:
+    12dc:	b510      	push	{r4, lr}
+    12de:	4b02      	ldr	r3, [pc, #8]	; (12e8 <SERCOM3_Handler+0xc>)
+    12e0:	2003      	movs	r0, #3
+    12e2:	68db      	ldr	r3, [r3, #12]
+    12e4:	4798      	blx	r3
+    12e6:	bd10      	pop	{r4, pc}
+    12e8:	20000190 	.word	0x20000190
+
+000012ec <SERCOM4_Handler>:
+    12ec:	b510      	push	{r4, lr}
+    12ee:	4b02      	ldr	r3, [pc, #8]	; (12f8 <SERCOM4_Handler+0xc>)
+    12f0:	2004      	movs	r0, #4
+    12f2:	691b      	ldr	r3, [r3, #16]
+    12f4:	4798      	blx	r3
+    12f6:	bd10      	pop	{r4, pc}
+    12f8:	20000190 	.word	0x20000190
+
+000012fc <SERCOM5_Handler>:
+    12fc:	b510      	push	{r4, lr}
+    12fe:	4b02      	ldr	r3, [pc, #8]	; (1308 <SERCOM5_Handler+0xc>)
+    1300:	2005      	movs	r0, #5
+    1302:	695b      	ldr	r3, [r3, #20]
+    1304:	4798      	blx	r3
+    1306:	bd10      	pop	{r4, pc}
+    1308:	20000190 	.word	0x20000190
+
+0000130c <delay_init>:
+    130c:	b570      	push	{r4, r5, r6, lr}
+    130e:	4b09      	ldr	r3, [pc, #36]	; (1334 <delay_init+0x28>)
+    1310:	2000      	movs	r0, #0
+    1312:	4798      	blx	r3
+    1314:	21fa      	movs	r1, #250	; 0xfa
+    1316:	4c08      	ldr	r4, [pc, #32]	; (1338 <delay_init+0x2c>)
+    1318:	0089      	lsls	r1, r1, #2
+    131a:	0005      	movs	r5, r0
+    131c:	47a0      	blx	r4
+    131e:	4b07      	ldr	r3, [pc, #28]	; (133c <delay_init+0x30>)
+    1320:	4907      	ldr	r1, [pc, #28]	; (1340 <delay_init+0x34>)
+    1322:	6018      	str	r0, [r3, #0]
+    1324:	0028      	movs	r0, r5
+    1326:	47a0      	blx	r4
+    1328:	2205      	movs	r2, #5
+    132a:	4b06      	ldr	r3, [pc, #24]	; (1344 <delay_init+0x38>)
+    132c:	6018      	str	r0, [r3, #0]
+    132e:	4b06      	ldr	r3, [pc, #24]	; (1348 <delay_init+0x3c>)
+    1330:	601a      	str	r2, [r3, #0]
+    1332:	bd70      	pop	{r4, r5, r6, pc}
+    1334:	0000173d 	.word	0x0000173d
+    1338:	0000215d 	.word	0x0000215d
+    133c:	2000000c 	.word	0x2000000c
+    1340:	000f4240 	.word	0x000f4240
+    1344:	20000010 	.word	0x20000010
+    1348:	e000e010 	.word	0xe000e010
+
+0000134c <delay_cycles_ms>:
+    134c:	b530      	push	{r4, r5, lr}
+    134e:	2480      	movs	r4, #128	; 0x80
+    1350:	2100      	movs	r1, #0
+    1352:	4b07      	ldr	r3, [pc, #28]	; (1370 <delay_cycles_ms+0x24>)
+    1354:	0264      	lsls	r4, r4, #9
+    1356:	681a      	ldr	r2, [r3, #0]
+    1358:	4b06      	ldr	r3, [pc, #24]	; (1374 <delay_cycles_ms+0x28>)
+    135a:	3801      	subs	r0, #1
+    135c:	d200      	bcs.n	1360 <delay_cycles_ms+0x14>
+    135e:	bd30      	pop	{r4, r5, pc}
+    1360:	2a00      	cmp	r2, #0
+    1362:	d0fa      	beq.n	135a <delay_cycles_ms+0xe>
+    1364:	605a      	str	r2, [r3, #4]
+    1366:	6099      	str	r1, [r3, #8]
+    1368:	681d      	ldr	r5, [r3, #0]
+    136a:	4225      	tst	r5, r4
+    136c:	d0fc      	beq.n	1368 <delay_cycles_ms+0x1c>
+    136e:	e7f4      	b.n	135a <delay_cycles_ms+0xe>
+    1370:	2000000c 	.word	0x2000000c
+    1374:	e000e010 	.word	0xe000e010
+
+00001378 <cpu_irq_enter_critical>:
+    1378:	4b09      	ldr	r3, [pc, #36]	; (13a0 <cpu_irq_enter_critical+0x28>)
+    137a:	6819      	ldr	r1, [r3, #0]
+    137c:	2900      	cmp	r1, #0
+    137e:	d10b      	bne.n	1398 <cpu_irq_enter_critical+0x20>
+    1380:	f3ef 8010 	mrs	r0, PRIMASK
+    1384:	4a07      	ldr	r2, [pc, #28]	; (13a4 <cpu_irq_enter_critical+0x2c>)
+    1386:	2800      	cmp	r0, #0
+    1388:	d105      	bne.n	1396 <cpu_irq_enter_critical+0x1e>
+    138a:	b672      	cpsid	i
+    138c:	f3bf 8f5f 	dmb	sy
+    1390:	4905      	ldr	r1, [pc, #20]	; (13a8 <cpu_irq_enter_critical+0x30>)
+    1392:	7008      	strb	r0, [r1, #0]
+    1394:	2101      	movs	r1, #1
+    1396:	7011      	strb	r1, [r2, #0]
+    1398:	681a      	ldr	r2, [r3, #0]
+    139a:	3201      	adds	r2, #1
+    139c:	601a      	str	r2, [r3, #0]
+    139e:	4770      	bx	lr
+    13a0:	200001a8 	.word	0x200001a8
+    13a4:	200001ac 	.word	0x200001ac
+    13a8:	20000014 	.word	0x20000014
+
+000013ac <cpu_irq_leave_critical>:
+    13ac:	4b08      	ldr	r3, [pc, #32]	; (13d0 <cpu_irq_leave_critical+0x24>)
+    13ae:	681a      	ldr	r2, [r3, #0]
+    13b0:	3a01      	subs	r2, #1
+    13b2:	601a      	str	r2, [r3, #0]
+    13b4:	681b      	ldr	r3, [r3, #0]
+    13b6:	2b00      	cmp	r3, #0
+    13b8:	d109      	bne.n	13ce <cpu_irq_leave_critical+0x22>
+    13ba:	4b06      	ldr	r3, [pc, #24]	; (13d4 <cpu_irq_leave_critical+0x28>)
+    13bc:	781b      	ldrb	r3, [r3, #0]
+    13be:	2b00      	cmp	r3, #0
+    13c0:	d005      	beq.n	13ce <cpu_irq_leave_critical+0x22>
+    13c2:	2201      	movs	r2, #1
+    13c4:	4b04      	ldr	r3, [pc, #16]	; (13d8 <cpu_irq_leave_critical+0x2c>)
+    13c6:	701a      	strb	r2, [r3, #0]
+    13c8:	f3bf 8f5f 	dmb	sy
+    13cc:	b662      	cpsie	i
+    13ce:	4770      	bx	lr
+    13d0:	200001a8 	.word	0x200001a8
+    13d4:	200001ac 	.word	0x200001ac
+    13d8:	20000014 	.word	0x20000014
+
+000013dc <system_board_init>:
+    13dc:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    13de:	2501      	movs	r5, #1
+    13e0:	2700      	movs	r7, #0
+    13e2:	ac01      	add	r4, sp, #4
+    13e4:	4e08      	ldr	r6, [pc, #32]	; (1408 <system_board_init+0x2c>)
+    13e6:	0021      	movs	r1, r4
+    13e8:	203e      	movs	r0, #62	; 0x3e
+    13ea:	7065      	strb	r5, [r4, #1]
+    13ec:	70a7      	strb	r7, [r4, #2]
+    13ee:	7025      	strb	r5, [r4, #0]
+    13f0:	47b0      	blx	r6
+    13f2:	2280      	movs	r2, #128	; 0x80
+    13f4:	4b05      	ldr	r3, [pc, #20]	; (140c <system_board_init+0x30>)
+    13f6:	05d2      	lsls	r2, r2, #23
+    13f8:	601a      	str	r2, [r3, #0]
+    13fa:	0021      	movs	r1, r4
+    13fc:	200f      	movs	r0, #15
+    13fe:	7027      	strb	r7, [r4, #0]
+    1400:	7065      	strb	r5, [r4, #1]
+    1402:	47b0      	blx	r6
+    1404:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
+    1406:	46c0      	nop			; (mov r8, r8)
+    1408:	00001411 	.word	0x00001411
+    140c:	41004498 	.word	0x41004498
+
+00001410 <port_pin_set_config>:
+    1410:	b507      	push	{r0, r1, r2, lr}
+    1412:	2280      	movs	r2, #128	; 0x80
+    1414:	ab01      	add	r3, sp, #4
+    1416:	701a      	strb	r2, [r3, #0]
+    1418:	780a      	ldrb	r2, [r1, #0]
+    141a:	705a      	strb	r2, [r3, #1]
+    141c:	784a      	ldrb	r2, [r1, #1]
+    141e:	709a      	strb	r2, [r3, #2]
+    1420:	788a      	ldrb	r2, [r1, #2]
+    1422:	0019      	movs	r1, r3
+    1424:	70da      	strb	r2, [r3, #3]
+    1426:	4b01      	ldr	r3, [pc, #4]	; (142c <port_pin_set_config+0x1c>)
+    1428:	4798      	blx	r3
+    142a:	bd07      	pop	{r0, r1, r2, pc}
+    142c:	00001921 	.word	0x00001921
+
+00001430 <_system_dfll_wait_for_sync>:
+    1430:	2310      	movs	r3, #16
+    1432:	4902      	ldr	r1, [pc, #8]	; (143c <_system_dfll_wait_for_sync+0xc>)
+    1434:	68ca      	ldr	r2, [r1, #12]
+    1436:	421a      	tst	r2, r3
+    1438:	d0fc      	beq.n	1434 <_system_dfll_wait_for_sync+0x4>
+    143a:	4770      	bx	lr
+    143c:	40000800 	.word	0x40000800
+
+00001440 <system_clock_source_get_hz>:
+    1440:	b570      	push	{r4, r5, r6, lr}
+    1442:	2808      	cmp	r0, #8
+    1444:	d806      	bhi.n	1454 <system_clock_source_get_hz+0x14>
+    1446:	f000 fe7f 	bl	2148 <__gnu_thumb1_case_uqi>
+    144a:	0508      	.short	0x0508
+    144c:	12303005 	.word	0x12303005
+    1450:	150b      	.short	0x150b
+    1452:	28          	.byte	0x28
+    1453:	00          	.byte	0x00
+    1454:	2400      	movs	r4, #0
+    1456:	0020      	movs	r0, r4
+    1458:	bd70      	pop	{r4, r5, r6, pc}
+    145a:	4b16      	ldr	r3, [pc, #88]	; (14b4 <system_clock_source_get_hz+0x74>)
+    145c:	691c      	ldr	r4, [r3, #16]
+    145e:	e7fa      	b.n	1456 <system_clock_source_get_hz+0x16>
+    1460:	4b15      	ldr	r3, [pc, #84]	; (14b8 <system_clock_source_get_hz+0x78>)
+    1462:	4c16      	ldr	r4, [pc, #88]	; (14bc <system_clock_source_get_hz+0x7c>)
+    1464:	6a1b      	ldr	r3, [r3, #32]
+    1466:	059b      	lsls	r3, r3, #22
+    1468:	0f9b      	lsrs	r3, r3, #30
+    146a:	40dc      	lsrs	r4, r3
+    146c:	e7f3      	b.n	1456 <system_clock_source_get_hz+0x16>
+    146e:	4b11      	ldr	r3, [pc, #68]	; (14b4 <system_clock_source_get_hz+0x74>)
+    1470:	695c      	ldr	r4, [r3, #20]
+    1472:	e7f0      	b.n	1456 <system_clock_source_get_hz+0x16>
+    1474:	4d0f      	ldr	r5, [pc, #60]	; (14b4 <system_clock_source_get_hz+0x74>)
+    1476:	2400      	movs	r4, #0
+    1478:	682b      	ldr	r3, [r5, #0]
+    147a:	079b      	lsls	r3, r3, #30
+    147c:	d5eb      	bpl.n	1456 <system_clock_source_get_hz+0x16>
+    147e:	4b10      	ldr	r3, [pc, #64]	; (14c0 <system_clock_source_get_hz+0x80>)
+    1480:	4798      	blx	r3
+    1482:	2224      	movs	r2, #36	; 0x24
+    1484:	682b      	ldr	r3, [r5, #0]
+    1486:	4013      	ands	r3, r2
+    1488:	2b04      	cmp	r3, #4
+    148a:	d111      	bne.n	14b0 <system_clock_source_get_hz+0x70>
+    148c:	0020      	movs	r0, r4
+    148e:	4b0d      	ldr	r3, [pc, #52]	; (14c4 <system_clock_source_get_hz+0x84>)
+    1490:	4798      	blx	r3
+    1492:	68ac      	ldr	r4, [r5, #8]
+    1494:	b2a4      	uxth	r4, r4
+    1496:	4344      	muls	r4, r0
+    1498:	e7dd      	b.n	1456 <system_clock_source_get_hz+0x16>
+    149a:	4b0b      	ldr	r3, [pc, #44]	; (14c8 <system_clock_source_get_hz+0x88>)
+    149c:	2400      	movs	r4, #0
+    149e:	781b      	ldrb	r3, [r3, #0]
+    14a0:	075b      	lsls	r3, r3, #29
+    14a2:	d5d8      	bpl.n	1456 <system_clock_source_get_hz+0x16>
+    14a4:	4b03      	ldr	r3, [pc, #12]	; (14b4 <system_clock_source_get_hz+0x74>)
+    14a6:	68dc      	ldr	r4, [r3, #12]
+    14a8:	e7d5      	b.n	1456 <system_clock_source_get_hz+0x16>
+    14aa:	2480      	movs	r4, #128	; 0x80
+    14ac:	0224      	lsls	r4, r4, #8
+    14ae:	e7d2      	b.n	1456 <system_clock_source_get_hz+0x16>
+    14b0:	4c06      	ldr	r4, [pc, #24]	; (14cc <system_clock_source_get_hz+0x8c>)
+    14b2:	e7d0      	b.n	1456 <system_clock_source_get_hz+0x16>
+    14b4:	200001b0 	.word	0x200001b0
+    14b8:	40000800 	.word	0x40000800
+    14bc:	007a1200 	.word	0x007a1200
+    14c0:	00001431 	.word	0x00001431
+    14c4:	00001869 	.word	0x00001869
+    14c8:	40000850 	.word	0x40000850
+    14cc:	02dc6c00 	.word	0x02dc6c00
+
+000014d0 <system_clock_source_osc8m_set_config>:
+    14d0:	b570      	push	{r4, r5, r6, lr}
+    14d2:	7884      	ldrb	r4, [r0, #2]
+    14d4:	7802      	ldrb	r2, [r0, #0]
+    14d6:	7845      	ldrb	r5, [r0, #1]
+    14d8:	2001      	movs	r0, #1
+    14da:	2640      	movs	r6, #64	; 0x40
+    14dc:	4005      	ands	r5, r0
+    14de:	4020      	ands	r0, r4
+    14e0:	2480      	movs	r4, #128	; 0x80
+    14e2:	4908      	ldr	r1, [pc, #32]	; (1504 <system_clock_source_osc8m_set_config+0x34>)
+    14e4:	01ad      	lsls	r5, r5, #6
+    14e6:	6a0b      	ldr	r3, [r1, #32]
+    14e8:	01c0      	lsls	r0, r0, #7
+    14ea:	43b3      	bics	r3, r6
+    14ec:	432b      	orrs	r3, r5
+    14ee:	43a3      	bics	r3, r4
+    14f0:	4303      	orrs	r3, r0
+    14f2:	2003      	movs	r0, #3
+    14f4:	4002      	ands	r2, r0
+    14f6:	4804      	ldr	r0, [pc, #16]	; (1508 <system_clock_source_osc8m_set_config+0x38>)
+    14f8:	0212      	lsls	r2, r2, #8
+    14fa:	4003      	ands	r3, r0
+    14fc:	4313      	orrs	r3, r2
+    14fe:	620b      	str	r3, [r1, #32]
+    1500:	bd70      	pop	{r4, r5, r6, pc}
+    1502:	46c0      	nop			; (mov r8, r8)
+    1504:	40000800 	.word	0x40000800
+    1508:	fffffcff 	.word	0xfffffcff
+
+0000150c <system_clock_source_enable>:
+    150c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    150e:	2808      	cmp	r0, #8
+    1510:	d806      	bhi.n	1520 <system_clock_source_enable+0x14>
+    1512:	f000 fe19 	bl	2148 <__gnu_thumb1_case_uqi>
+    1516:	0514      	.short	0x0514
+    1518:	1a0e0c05 	.word	0x1a0e0c05
+    151c:	2007      	.short	0x2007
+    151e:	34          	.byte	0x34
+    151f:	00          	.byte	0x00
+    1520:	2017      	movs	r0, #23
+    1522:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    1524:	2302      	movs	r3, #2
+    1526:	4a19      	ldr	r2, [pc, #100]	; (158c <system_clock_source_enable+0x80>)
+    1528:	6a11      	ldr	r1, [r2, #32]
+    152a:	430b      	orrs	r3, r1
+    152c:	6213      	str	r3, [r2, #32]
+    152e:	2000      	movs	r0, #0
+    1530:	e7f7      	b.n	1522 <system_clock_source_enable+0x16>
+    1532:	2302      	movs	r3, #2
+    1534:	4a15      	ldr	r2, [pc, #84]	; (158c <system_clock_source_enable+0x80>)
+    1536:	6991      	ldr	r1, [r2, #24]
+    1538:	430b      	orrs	r3, r1
+    153a:	6193      	str	r3, [r2, #24]
+    153c:	e7f7      	b.n	152e <system_clock_source_enable+0x22>
+    153e:	2302      	movs	r3, #2
+    1540:	4a12      	ldr	r2, [pc, #72]	; (158c <system_clock_source_enable+0x80>)
+    1542:	8a11      	ldrh	r1, [r2, #16]
+    1544:	430b      	orrs	r3, r1
+    1546:	8213      	strh	r3, [r2, #16]
+    1548:	e7f1      	b.n	152e <system_clock_source_enable+0x22>
+    154a:	2302      	movs	r3, #2
+    154c:	4a0f      	ldr	r2, [pc, #60]	; (158c <system_clock_source_enable+0x80>)
+    154e:	8a91      	ldrh	r1, [r2, #20]
+    1550:	430b      	orrs	r3, r1
+    1552:	8293      	strh	r3, [r2, #20]
+    1554:	e7eb      	b.n	152e <system_clock_source_enable+0x22>
+    1556:	2202      	movs	r2, #2
+    1558:	2400      	movs	r4, #0
+    155a:	4e0d      	ldr	r6, [pc, #52]	; (1590 <system_clock_source_enable+0x84>)
+    155c:	4d0b      	ldr	r5, [pc, #44]	; (158c <system_clock_source_enable+0x80>)
+    155e:	6833      	ldr	r3, [r6, #0]
+    1560:	4f0c      	ldr	r7, [pc, #48]	; (1594 <system_clock_source_enable+0x88>)
+    1562:	4313      	orrs	r3, r2
+    1564:	6033      	str	r3, [r6, #0]
+    1566:	84aa      	strh	r2, [r5, #36]	; 0x24
+    1568:	47b8      	blx	r7
+    156a:	68b3      	ldr	r3, [r6, #8]
+    156c:	62eb      	str	r3, [r5, #44]	; 0x2c
+    156e:	6873      	ldr	r3, [r6, #4]
+    1570:	62ab      	str	r3, [r5, #40]	; 0x28
+    1572:	84ac      	strh	r4, [r5, #36]	; 0x24
+    1574:	47b8      	blx	r7
+    1576:	6833      	ldr	r3, [r6, #0]
+    1578:	b29b      	uxth	r3, r3
+    157a:	84ab      	strh	r3, [r5, #36]	; 0x24
+    157c:	e7d7      	b.n	152e <system_clock_source_enable+0x22>
+    157e:	2302      	movs	r3, #2
+    1580:	4a05      	ldr	r2, [pc, #20]	; (1598 <system_clock_source_enable+0x8c>)
+    1582:	7811      	ldrb	r1, [r2, #0]
+    1584:	430b      	orrs	r3, r1
+    1586:	7013      	strb	r3, [r2, #0]
+    1588:	e7d1      	b.n	152e <system_clock_source_enable+0x22>
+    158a:	46c0      	nop			; (mov r8, r8)
+    158c:	40000800 	.word	0x40000800
+    1590:	200001b0 	.word	0x200001b0
+    1594:	00001431 	.word	0x00001431
+    1598:	40000844 	.word	0x40000844
+
+0000159c <system_clock_init>:
+    159c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
+    159e:	22c2      	movs	r2, #194	; 0xc2
+    15a0:	211e      	movs	r1, #30
+    15a2:	4b19      	ldr	r3, [pc, #100]	; (1608 <system_clock_init+0x6c>)
+    15a4:	00d2      	lsls	r2, r2, #3
+    15a6:	609a      	str	r2, [r3, #8]
+    15a8:	4a18      	ldr	r2, [pc, #96]	; (160c <system_clock_init+0x70>)
+    15aa:	2400      	movs	r4, #0
+    15ac:	6853      	ldr	r3, [r2, #4]
+    15ae:	ad01      	add	r5, sp, #4
+    15b0:	438b      	bics	r3, r1
+    15b2:	6053      	str	r3, [r2, #4]
+    15b4:	2301      	movs	r3, #1
+    15b6:	702b      	strb	r3, [r5, #0]
+    15b8:	b2e0      	uxtb	r0, r4
+    15ba:	0029      	movs	r1, r5
+    15bc:	4b14      	ldr	r3, [pc, #80]	; (1610 <system_clock_init+0x74>)
+    15be:	3401      	adds	r4, #1
+    15c0:	4798      	blx	r3
+    15c2:	2c25      	cmp	r4, #37	; 0x25
+    15c4:	d1f8      	bne.n	15b8 <system_clock_init+0x1c>
+    15c6:	2400      	movs	r4, #0
+    15c8:	466b      	mov	r3, sp
+    15ca:	2601      	movs	r6, #1
+    15cc:	705c      	strb	r4, [r3, #1]
+    15ce:	709e      	strb	r6, [r3, #2]
+    15d0:	701c      	strb	r4, [r3, #0]
+    15d2:	4668      	mov	r0, sp
+    15d4:	4b0f      	ldr	r3, [pc, #60]	; (1614 <system_clock_init+0x78>)
+    15d6:	4798      	blx	r3
+    15d8:	4b0f      	ldr	r3, [pc, #60]	; (1618 <system_clock_init+0x7c>)
+    15da:	2006      	movs	r0, #6
+    15dc:	4798      	blx	r3
+    15de:	4b0f      	ldr	r3, [pc, #60]	; (161c <system_clock_init+0x80>)
+    15e0:	4798      	blx	r3
+    15e2:	4b0f      	ldr	r3, [pc, #60]	; (1620 <system_clock_init+0x84>)
+    15e4:	0029      	movs	r1, r5
+    15e6:	721c      	strb	r4, [r3, #8]
+    15e8:	725c      	strb	r4, [r3, #9]
+    15ea:	729c      	strb	r4, [r3, #10]
+    15ec:	72dc      	strb	r4, [r3, #11]
+    15ee:	2306      	movs	r3, #6
+    15f0:	0020      	movs	r0, r4
+    15f2:	702b      	strb	r3, [r5, #0]
+    15f4:	4b0b      	ldr	r3, [pc, #44]	; (1624 <system_clock_init+0x88>)
+    15f6:	606e      	str	r6, [r5, #4]
+    15f8:	706c      	strb	r4, [r5, #1]
+    15fa:	722c      	strb	r4, [r5, #8]
+    15fc:	726c      	strb	r4, [r5, #9]
+    15fe:	4798      	blx	r3
+    1600:	0020      	movs	r0, r4
+    1602:	4b09      	ldr	r3, [pc, #36]	; (1628 <system_clock_init+0x8c>)
+    1604:	4798      	blx	r3
+    1606:	bd7f      	pop	{r0, r1, r2, r3, r4, r5, r6, pc}
+    1608:	40000800 	.word	0x40000800
+    160c:	41004000 	.word	0x41004000
+    1610:	0000184d 	.word	0x0000184d
+    1614:	000014d1 	.word	0x000014d1
+    1618:	0000150d 	.word	0x0000150d
+    161c:	00001639 	.word	0x00001639
+    1620:	40000400 	.word	0x40000400
+    1624:	00001659 	.word	0x00001659
+    1628:	000016fd 	.word	0x000016fd
+
+0000162c <system_gclk_is_syncing>:
+    162c:	4b01      	ldr	r3, [pc, #4]	; (1634 <system_gclk_is_syncing+0x8>)
+    162e:	7858      	ldrb	r0, [r3, #1]
+    1630:	09c0      	lsrs	r0, r0, #7
+    1632:	4770      	bx	lr
+    1634:	40000c00 	.word	0x40000c00
+
+00001638 <system_gclk_init>:
+    1638:	2308      	movs	r3, #8
+    163a:	4a05      	ldr	r2, [pc, #20]	; (1650 <system_gclk_init+0x18>)
+    163c:	6991      	ldr	r1, [r2, #24]
+    163e:	430b      	orrs	r3, r1
+    1640:	6193      	str	r3, [r2, #24]
+    1642:	2301      	movs	r3, #1
+    1644:	4a03      	ldr	r2, [pc, #12]	; (1654 <system_gclk_init+0x1c>)
+    1646:	7013      	strb	r3, [r2, #0]
+    1648:	7811      	ldrb	r1, [r2, #0]
+    164a:	4219      	tst	r1, r3
+    164c:	d1fc      	bne.n	1648 <system_gclk_init+0x10>
+    164e:	4770      	bx	lr
+    1650:	40000400 	.word	0x40000400
+    1654:	40000c00 	.word	0x40000c00
+
+00001658 <system_gclk_gen_set_config>:
+    1658:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    165a:	780c      	ldrb	r4, [r1, #0]
+    165c:	784b      	ldrb	r3, [r1, #1]
+    165e:	0224      	lsls	r4, r4, #8
+    1660:	0006      	movs	r6, r0
+    1662:	0005      	movs	r5, r0
+    1664:	4304      	orrs	r4, r0
+    1666:	2b00      	cmp	r3, #0
+    1668:	d002      	beq.n	1670 <system_gclk_gen_set_config+0x18>
+    166a:	2380      	movs	r3, #128	; 0x80
+    166c:	02db      	lsls	r3, r3, #11
+    166e:	431c      	orrs	r4, r3
+    1670:	7a4b      	ldrb	r3, [r1, #9]
+    1672:	2b00      	cmp	r3, #0
+    1674:	d002      	beq.n	167c <system_gclk_gen_set_config+0x24>
+    1676:	2380      	movs	r3, #128	; 0x80
+    1678:	031b      	lsls	r3, r3, #12
+    167a:	431c      	orrs	r4, r3
+    167c:	684b      	ldr	r3, [r1, #4]
+    167e:	2b01      	cmp	r3, #1
+    1680:	d912      	bls.n	16a8 <system_gclk_gen_set_config+0x50>
+    1682:	1e5d      	subs	r5, r3, #1
+    1684:	401d      	ands	r5, r3
+    1686:	2202      	movs	r2, #2
+    1688:	2d00      	cmp	r5, #0
+    168a:	d006      	beq.n	169a <system_gclk_gen_set_config+0x42>
+    168c:	021d      	lsls	r5, r3, #8
+    168e:	2380      	movs	r3, #128	; 0x80
+    1690:	4335      	orrs	r5, r6
+    1692:	029b      	lsls	r3, r3, #10
+    1694:	e007      	b.n	16a6 <system_gclk_gen_set_config+0x4e>
+    1696:	3501      	adds	r5, #1
+    1698:	0052      	lsls	r2, r2, #1
+    169a:	429a      	cmp	r2, r3
+    169c:	d3fb      	bcc.n	1696 <system_gclk_gen_set_config+0x3e>
+    169e:	2380      	movs	r3, #128	; 0x80
+    16a0:	022d      	lsls	r5, r5, #8
+    16a2:	4335      	orrs	r5, r6
+    16a4:	035b      	lsls	r3, r3, #13
+    16a6:	431c      	orrs	r4, r3
+    16a8:	7a0b      	ldrb	r3, [r1, #8]
+    16aa:	2b00      	cmp	r3, #0
+    16ac:	d002      	beq.n	16b4 <system_gclk_gen_set_config+0x5c>
+    16ae:	2380      	movs	r3, #128	; 0x80
+    16b0:	039b      	lsls	r3, r3, #14
+    16b2:	431c      	orrs	r4, r3
+    16b4:	4f0c      	ldr	r7, [pc, #48]	; (16e8 <system_gclk_gen_set_config+0x90>)
+    16b6:	47b8      	blx	r7
+    16b8:	2800      	cmp	r0, #0
+    16ba:	d1fb      	bne.n	16b4 <system_gclk_gen_set_config+0x5c>
+    16bc:	4b0b      	ldr	r3, [pc, #44]	; (16ec <system_gclk_gen_set_config+0x94>)
+    16be:	4798      	blx	r3
+    16c0:	4b0b      	ldr	r3, [pc, #44]	; (16f0 <system_gclk_gen_set_config+0x98>)
+    16c2:	701e      	strb	r6, [r3, #0]
+    16c4:	47b8      	blx	r7
+    16c6:	2800      	cmp	r0, #0
+    16c8:	d1fc      	bne.n	16c4 <system_gclk_gen_set_config+0x6c>
+    16ca:	4b0a      	ldr	r3, [pc, #40]	; (16f4 <system_gclk_gen_set_config+0x9c>)
+    16cc:	609d      	str	r5, [r3, #8]
+    16ce:	001d      	movs	r5, r3
+    16d0:	47b8      	blx	r7
+    16d2:	2800      	cmp	r0, #0
+    16d4:	d1fc      	bne.n	16d0 <system_gclk_gen_set_config+0x78>
+    16d6:	2280      	movs	r2, #128	; 0x80
+    16d8:	686b      	ldr	r3, [r5, #4]
+    16da:	0252      	lsls	r2, r2, #9
+    16dc:	4013      	ands	r3, r2
+    16de:	431c      	orrs	r4, r3
+    16e0:	606c      	str	r4, [r5, #4]
+    16e2:	4b05      	ldr	r3, [pc, #20]	; (16f8 <system_gclk_gen_set_config+0xa0>)
+    16e4:	4798      	blx	r3
+    16e6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    16e8:	0000162d 	.word	0x0000162d
+    16ec:	00001379 	.word	0x00001379
+    16f0:	40000c08 	.word	0x40000c08
+    16f4:	40000c00 	.word	0x40000c00
+    16f8:	000013ad 	.word	0x000013ad
+
+000016fc <system_gclk_gen_enable>:
+    16fc:	b570      	push	{r4, r5, r6, lr}
+    16fe:	0005      	movs	r5, r0
+    1700:	4c09      	ldr	r4, [pc, #36]	; (1728 <system_gclk_gen_enable+0x2c>)
+    1702:	47a0      	blx	r4
+    1704:	2800      	cmp	r0, #0
+    1706:	d1fb      	bne.n	1700 <system_gclk_gen_enable+0x4>
+    1708:	4b08      	ldr	r3, [pc, #32]	; (172c <system_gclk_gen_enable+0x30>)
+    170a:	4798      	blx	r3
+    170c:	4b08      	ldr	r3, [pc, #32]	; (1730 <system_gclk_gen_enable+0x34>)
+    170e:	701d      	strb	r5, [r3, #0]
+    1710:	47a0      	blx	r4
+    1712:	2800      	cmp	r0, #0
+    1714:	d1fc      	bne.n	1710 <system_gclk_gen_enable+0x14>
+    1716:	2380      	movs	r3, #128	; 0x80
+    1718:	4a06      	ldr	r2, [pc, #24]	; (1734 <system_gclk_gen_enable+0x38>)
+    171a:	025b      	lsls	r3, r3, #9
+    171c:	6851      	ldr	r1, [r2, #4]
+    171e:	430b      	orrs	r3, r1
+    1720:	6053      	str	r3, [r2, #4]
+    1722:	4b05      	ldr	r3, [pc, #20]	; (1738 <system_gclk_gen_enable+0x3c>)
+    1724:	4798      	blx	r3
+    1726:	bd70      	pop	{r4, r5, r6, pc}
+    1728:	0000162d 	.word	0x0000162d
+    172c:	00001379 	.word	0x00001379
+    1730:	40000c04 	.word	0x40000c04
+    1734:	40000c00 	.word	0x40000c00
+    1738:	000013ad 	.word	0x000013ad
+
+0000173c <system_gclk_gen_get_hz>:
+    173c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    173e:	0007      	movs	r7, r0
+    1740:	4e18      	ldr	r6, [pc, #96]	; (17a4 <system_gclk_gen_get_hz+0x68>)
+    1742:	47b0      	blx	r6
+    1744:	2800      	cmp	r0, #0
+    1746:	d1fb      	bne.n	1740 <system_gclk_gen_get_hz+0x4>
+    1748:	4b17      	ldr	r3, [pc, #92]	; (17a8 <system_gclk_gen_get_hz+0x6c>)
+    174a:	4798      	blx	r3
+    174c:	4b17      	ldr	r3, [pc, #92]	; (17ac <system_gclk_gen_get_hz+0x70>)
+    174e:	701f      	strb	r7, [r3, #0]
+    1750:	9301      	str	r3, [sp, #4]
+    1752:	47b0      	blx	r6
+    1754:	2800      	cmp	r0, #0
+    1756:	d1fc      	bne.n	1752 <system_gclk_gen_get_hz+0x16>
+    1758:	4d15      	ldr	r5, [pc, #84]	; (17b0 <system_gclk_gen_get_hz+0x74>)
+    175a:	4b16      	ldr	r3, [pc, #88]	; (17b4 <system_gclk_gen_get_hz+0x78>)
+    175c:	6868      	ldr	r0, [r5, #4]
+    175e:	04c0      	lsls	r0, r0, #19
+    1760:	0ec0      	lsrs	r0, r0, #27
+    1762:	4798      	blx	r3
+    1764:	0004      	movs	r4, r0
+    1766:	9b01      	ldr	r3, [sp, #4]
+    1768:	701f      	strb	r7, [r3, #0]
+    176a:	686b      	ldr	r3, [r5, #4]
+    176c:	02db      	lsls	r3, r3, #11
+    176e:	0fdb      	lsrs	r3, r3, #31
+    1770:	9301      	str	r3, [sp, #4]
+    1772:	4b11      	ldr	r3, [pc, #68]	; (17b8 <system_gclk_gen_get_hz+0x7c>)
+    1774:	701f      	strb	r7, [r3, #0]
+    1776:	47b0      	blx	r6
+    1778:	2800      	cmp	r0, #0
+    177a:	d1fc      	bne.n	1776 <system_gclk_gen_get_hz+0x3a>
+    177c:	68ad      	ldr	r5, [r5, #8]
+    177e:	4b0f      	ldr	r3, [pc, #60]	; (17bc <system_gclk_gen_get_hz+0x80>)
+    1780:	4798      	blx	r3
+    1782:	9b01      	ldr	r3, [sp, #4]
+    1784:	022d      	lsls	r5, r5, #8
+    1786:	0c2d      	lsrs	r5, r5, #16
+    1788:	2b00      	cmp	r3, #0
+    178a:	d108      	bne.n	179e <system_gclk_gen_get_hz+0x62>
+    178c:	2d01      	cmp	r5, #1
+    178e:	d904      	bls.n	179a <system_gclk_gen_get_hz+0x5e>
+    1790:	0020      	movs	r0, r4
+    1792:	0029      	movs	r1, r5
+    1794:	4b0a      	ldr	r3, [pc, #40]	; (17c0 <system_gclk_gen_get_hz+0x84>)
+    1796:	4798      	blx	r3
+    1798:	0004      	movs	r4, r0
+    179a:	0020      	movs	r0, r4
+    179c:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    179e:	3501      	adds	r5, #1
+    17a0:	40ec      	lsrs	r4, r5
+    17a2:	e7fa      	b.n	179a <system_gclk_gen_get_hz+0x5e>
+    17a4:	0000162d 	.word	0x0000162d
+    17a8:	00001379 	.word	0x00001379
+    17ac:	40000c04 	.word	0x40000c04
+    17b0:	40000c00 	.word	0x40000c00
+    17b4:	00001441 	.word	0x00001441
+    17b8:	40000c08 	.word	0x40000c08
+    17bc:	000013ad 	.word	0x000013ad
+    17c0:	0000215d 	.word	0x0000215d
+
+000017c4 <system_gclk_chan_enable>:
+    17c4:	b510      	push	{r4, lr}
+    17c6:	0004      	movs	r4, r0
+    17c8:	4b06      	ldr	r3, [pc, #24]	; (17e4 <system_gclk_chan_enable+0x20>)
+    17ca:	4798      	blx	r3
+    17cc:	4b06      	ldr	r3, [pc, #24]	; (17e8 <system_gclk_chan_enable+0x24>)
+    17ce:	4a07      	ldr	r2, [pc, #28]	; (17ec <system_gclk_chan_enable+0x28>)
+    17d0:	701c      	strb	r4, [r3, #0]
+    17d2:	2380      	movs	r3, #128	; 0x80
+    17d4:	8851      	ldrh	r1, [r2, #2]
+    17d6:	01db      	lsls	r3, r3, #7
+    17d8:	430b      	orrs	r3, r1
+    17da:	8053      	strh	r3, [r2, #2]
+    17dc:	4b04      	ldr	r3, [pc, #16]	; (17f0 <system_gclk_chan_enable+0x2c>)
+    17de:	4798      	blx	r3
+    17e0:	bd10      	pop	{r4, pc}
+    17e2:	46c0      	nop			; (mov r8, r8)
+    17e4:	00001379 	.word	0x00001379
+    17e8:	40000c02 	.word	0x40000c02
+    17ec:	40000c00 	.word	0x40000c00
+    17f0:	000013ad 	.word	0x000013ad
+
+000017f4 <system_gclk_chan_disable>:
+    17f4:	b510      	push	{r4, lr}
+    17f6:	0004      	movs	r4, r0
+    17f8:	4b0e      	ldr	r3, [pc, #56]	; (1834 <system_gclk_chan_disable+0x40>)
+    17fa:	4798      	blx	r3
+    17fc:	4b0e      	ldr	r3, [pc, #56]	; (1838 <system_gclk_chan_disable+0x44>)
+    17fe:	4a0f      	ldr	r2, [pc, #60]	; (183c <system_gclk_chan_disable+0x48>)
+    1800:	701c      	strb	r4, [r3, #0]
+    1802:	4b0f      	ldr	r3, [pc, #60]	; (1840 <system_gclk_chan_disable+0x4c>)
+    1804:	4c0f      	ldr	r4, [pc, #60]	; (1844 <system_gclk_chan_disable+0x50>)
+    1806:	8858      	ldrh	r0, [r3, #2]
+    1808:	8859      	ldrh	r1, [r3, #2]
+    180a:	0500      	lsls	r0, r0, #20
+    180c:	4011      	ands	r1, r2
+    180e:	8059      	strh	r1, [r3, #2]
+    1810:	8859      	ldrh	r1, [r3, #2]
+    1812:	0f00      	lsrs	r0, r0, #28
+    1814:	4021      	ands	r1, r4
+    1816:	8059      	strh	r1, [r3, #2]
+    1818:	0011      	movs	r1, r2
+    181a:	2280      	movs	r2, #128	; 0x80
+    181c:	01d2      	lsls	r2, r2, #7
+    181e:	885c      	ldrh	r4, [r3, #2]
+    1820:	4214      	tst	r4, r2
+    1822:	d1fc      	bne.n	181e <system_gclk_chan_disable+0x2a>
+    1824:	885a      	ldrh	r2, [r3, #2]
+    1826:	0200      	lsls	r0, r0, #8
+    1828:	400a      	ands	r2, r1
+    182a:	4302      	orrs	r2, r0
+    182c:	805a      	strh	r2, [r3, #2]
+    182e:	4b06      	ldr	r3, [pc, #24]	; (1848 <system_gclk_chan_disable+0x54>)
+    1830:	4798      	blx	r3
+    1832:	bd10      	pop	{r4, pc}
+    1834:	00001379 	.word	0x00001379
+    1838:	40000c02 	.word	0x40000c02
+    183c:	fffff0ff 	.word	0xfffff0ff
+    1840:	40000c00 	.word	0x40000c00
+    1844:	ffffbfff 	.word	0xffffbfff
+    1848:	000013ad 	.word	0x000013ad
+
+0000184c <system_gclk_chan_set_config>:
+    184c:	b510      	push	{r4, lr}
+    184e:	780c      	ldrb	r4, [r1, #0]
+    1850:	4b03      	ldr	r3, [pc, #12]	; (1860 <system_gclk_chan_set_config+0x14>)
+    1852:	0224      	lsls	r4, r4, #8
+    1854:	4304      	orrs	r4, r0
+    1856:	4798      	blx	r3
+    1858:	4b02      	ldr	r3, [pc, #8]	; (1864 <system_gclk_chan_set_config+0x18>)
+    185a:	b2a4      	uxth	r4, r4
+    185c:	805c      	strh	r4, [r3, #2]
+    185e:	bd10      	pop	{r4, pc}
+    1860:	000017f5 	.word	0x000017f5
+    1864:	40000c00 	.word	0x40000c00
+
+00001868 <system_gclk_chan_get_hz>:
+    1868:	b510      	push	{r4, lr}
+    186a:	0004      	movs	r4, r0
+    186c:	4b06      	ldr	r3, [pc, #24]	; (1888 <system_gclk_chan_get_hz+0x20>)
+    186e:	4798      	blx	r3
+    1870:	4b06      	ldr	r3, [pc, #24]	; (188c <system_gclk_chan_get_hz+0x24>)
+    1872:	701c      	strb	r4, [r3, #0]
+    1874:	4b06      	ldr	r3, [pc, #24]	; (1890 <system_gclk_chan_get_hz+0x28>)
+    1876:	885c      	ldrh	r4, [r3, #2]
+    1878:	4b06      	ldr	r3, [pc, #24]	; (1894 <system_gclk_chan_get_hz+0x2c>)
+    187a:	0524      	lsls	r4, r4, #20
+    187c:	0f24      	lsrs	r4, r4, #28
+    187e:	4798      	blx	r3
+    1880:	0020      	movs	r0, r4
+    1882:	4b05      	ldr	r3, [pc, #20]	; (1898 <system_gclk_chan_get_hz+0x30>)
+    1884:	4798      	blx	r3
+    1886:	bd10      	pop	{r4, pc}
+    1888:	00001379 	.word	0x00001379
+    188c:	40000c02 	.word	0x40000c02
+    1890:	40000c00 	.word	0x40000c00
+    1894:	000013ad 	.word	0x000013ad
+    1898:	0000173d 	.word	0x0000173d
+
+0000189c <_system_pinmux_config>:
+    189c:	78d3      	ldrb	r3, [r2, #3]
+    189e:	b530      	push	{r4, r5, lr}
+    18a0:	2b00      	cmp	r3, #0
+    18a2:	d135      	bne.n	1910 <_system_pinmux_config+0x74>
+    18a4:	7814      	ldrb	r4, [r2, #0]
+    18a6:	2c80      	cmp	r4, #128	; 0x80
+    18a8:	d003      	beq.n	18b2 <_system_pinmux_config+0x16>
+    18aa:	2380      	movs	r3, #128	; 0x80
+    18ac:	0624      	lsls	r4, r4, #24
+    18ae:	025b      	lsls	r3, r3, #9
+    18b0:	4323      	orrs	r3, r4
+    18b2:	2502      	movs	r5, #2
+    18b4:	7854      	ldrb	r4, [r2, #1]
+    18b6:	43ac      	bics	r4, r5
+    18b8:	d106      	bne.n	18c8 <_system_pinmux_config+0x2c>
+    18ba:	7894      	ldrb	r4, [r2, #2]
+    18bc:	2c00      	cmp	r4, #0
+    18be:	d124      	bne.n	190a <_system_pinmux_config+0x6e>
+    18c0:	2480      	movs	r4, #128	; 0x80
+    18c2:	02a4      	lsls	r4, r4, #10
+    18c4:	4323      	orrs	r3, r4
+    18c6:	6041      	str	r1, [r0, #4]
+    18c8:	7854      	ldrb	r4, [r2, #1]
+    18ca:	3c01      	subs	r4, #1
+    18cc:	2c01      	cmp	r4, #1
+    18ce:	d801      	bhi.n	18d4 <_system_pinmux_config+0x38>
+    18d0:	4c12      	ldr	r4, [pc, #72]	; (191c <_system_pinmux_config+0x80>)
+    18d2:	4023      	ands	r3, r4
+    18d4:	24a0      	movs	r4, #160	; 0xa0
+    18d6:	b28d      	uxth	r5, r1
+    18d8:	05e4      	lsls	r4, r4, #23
+    18da:	432c      	orrs	r4, r5
+    18dc:	431c      	orrs	r4, r3
+    18de:	6284      	str	r4, [r0, #40]	; 0x28
+    18e0:	24d0      	movs	r4, #208	; 0xd0
+    18e2:	0c0d      	lsrs	r5, r1, #16
+    18e4:	0624      	lsls	r4, r4, #24
+    18e6:	432c      	orrs	r4, r5
+    18e8:	431c      	orrs	r4, r3
+    18ea:	6284      	str	r4, [r0, #40]	; 0x28
+    18ec:	78d4      	ldrb	r4, [r2, #3]
+    18ee:	2c00      	cmp	r4, #0
+    18f0:	d10a      	bne.n	1908 <_system_pinmux_config+0x6c>
+    18f2:	035b      	lsls	r3, r3, #13
+    18f4:	d503      	bpl.n	18fe <_system_pinmux_config+0x62>
+    18f6:	7893      	ldrb	r3, [r2, #2]
+    18f8:	2b01      	cmp	r3, #1
+    18fa:	d10c      	bne.n	1916 <_system_pinmux_config+0x7a>
+    18fc:	6181      	str	r1, [r0, #24]
+    18fe:	7853      	ldrb	r3, [r2, #1]
+    1900:	3b01      	subs	r3, #1
+    1902:	2b01      	cmp	r3, #1
+    1904:	d800      	bhi.n	1908 <_system_pinmux_config+0x6c>
+    1906:	6081      	str	r1, [r0, #8]
+    1908:	bd30      	pop	{r4, r5, pc}
+    190a:	24c0      	movs	r4, #192	; 0xc0
+    190c:	02e4      	lsls	r4, r4, #11
+    190e:	e7d9      	b.n	18c4 <_system_pinmux_config+0x28>
+    1910:	6041      	str	r1, [r0, #4]
+    1912:	2300      	movs	r3, #0
+    1914:	e7de      	b.n	18d4 <_system_pinmux_config+0x38>
+    1916:	6141      	str	r1, [r0, #20]
+    1918:	e7f1      	b.n	18fe <_system_pinmux_config+0x62>
+    191a:	46c0      	nop			; (mov r8, r8)
+    191c:	fffbffff 	.word	0xfffbffff
+
+00001920 <system_pinmux_pin_set_config>:
+    1920:	b510      	push	{r4, lr}
+    1922:	0003      	movs	r3, r0
+    1924:	000a      	movs	r2, r1
+    1926:	0944      	lsrs	r4, r0, #5
+    1928:	09c1      	lsrs	r1, r0, #7
+    192a:	2000      	movs	r0, #0
+    192c:	4281      	cmp	r1, r0
+    192e:	d102      	bne.n	1936 <system_pinmux_pin_set_config+0x16>
+    1930:	4904      	ldr	r1, [pc, #16]	; (1944 <system_pinmux_pin_set_config+0x24>)
+    1932:	01e0      	lsls	r0, r4, #7
+    1934:	1840      	adds	r0, r0, r1
+    1936:	211f      	movs	r1, #31
+    1938:	400b      	ands	r3, r1
+    193a:	391e      	subs	r1, #30
+    193c:	4099      	lsls	r1, r3
+    193e:	4b02      	ldr	r3, [pc, #8]	; (1948 <system_pinmux_pin_set_config+0x28>)
+    1940:	4798      	blx	r3
+    1942:	bd10      	pop	{r4, pc}
+    1944:	41004400 	.word	0x41004400
+    1948:	0000189d 	.word	0x0000189d
+
+0000194c <_system_dummy_init>:
+    194c:	4770      	bx	lr
+	...
+
+00001950 <system_init>:
+    1950:	b510      	push	{r4, lr}
+    1952:	4b05      	ldr	r3, [pc, #20]	; (1968 <system_init+0x18>)
+    1954:	4798      	blx	r3
+    1956:	4b05      	ldr	r3, [pc, #20]	; (196c <system_init+0x1c>)
+    1958:	4798      	blx	r3
+    195a:	4b05      	ldr	r3, [pc, #20]	; (1970 <system_init+0x20>)
+    195c:	4798      	blx	r3
+    195e:	4b05      	ldr	r3, [pc, #20]	; (1974 <system_init+0x24>)
+    1960:	4798      	blx	r3
+    1962:	4b05      	ldr	r3, [pc, #20]	; (1978 <system_init+0x28>)
+    1964:	4798      	blx	r3
+    1966:	bd10      	pop	{r4, pc}
+    1968:	0000159d 	.word	0x0000159d
+    196c:	000013dd 	.word	0x000013dd
+    1970:	0000194d 	.word	0x0000194d
+    1974:	0000194d 	.word	0x0000194d
+    1978:	0000194d 	.word	0x0000194d
+
+0000197c <Dummy_Handler>:
+    197c:	e7fe      	b.n	197c <Dummy_Handler>
+	...
+
+00001980 <Reset_Handler>:
+    1980:	4821      	ldr	r0, [pc, #132]	; (1a08 <Reset_Handler+0x88>)
+    1982:	4922      	ldr	r1, [pc, #136]	; (1a0c <Reset_Handler+0x8c>)
+    1984:	b570      	push	{r4, r5, r6, lr}
+    1986:	4288      	cmp	r0, r1
+    1988:	d004      	beq.n	1994 <Reset_Handler+0x14>
+    198a:	2300      	movs	r3, #0
+    198c:	4c20      	ldr	r4, [pc, #128]	; (1a10 <Reset_Handler+0x90>)
+    198e:	18ca      	adds	r2, r1, r3
+    1990:	42a2      	cmp	r2, r4
+    1992:	d332      	bcc.n	19fa <Reset_Handler+0x7a>
+    1994:	2100      	movs	r1, #0
+    1996:	4b1f      	ldr	r3, [pc, #124]	; (1a14 <Reset_Handler+0x94>)
+    1998:	4a1f      	ldr	r2, [pc, #124]	; (1a18 <Reset_Handler+0x98>)
+    199a:	4293      	cmp	r3, r2
+    199c:	d331      	bcc.n	1a02 <Reset_Handler+0x82>
+    199e:	21ff      	movs	r1, #255	; 0xff
+    19a0:	4b1e      	ldr	r3, [pc, #120]	; (1a1c <Reset_Handler+0x9c>)
+    19a2:	4a1f      	ldr	r2, [pc, #124]	; (1a20 <Reset_Handler+0xa0>)
+    19a4:	438b      	bics	r3, r1
+    19a6:	6093      	str	r3, [r2, #8]
+    19a8:	2202      	movs	r2, #2
+    19aa:	250c      	movs	r5, #12
+    19ac:	2408      	movs	r4, #8
+    19ae:	2630      	movs	r6, #48	; 0x30
+    19b0:	4b1c      	ldr	r3, [pc, #112]	; (1a24 <Reset_Handler+0xa4>)
+    19b2:	481d      	ldr	r0, [pc, #116]	; (1a28 <Reset_Handler+0xa8>)
+    19b4:	625a      	str	r2, [r3, #36]	; 0x24
+    19b6:	78c3      	ldrb	r3, [r0, #3]
+    19b8:	39fc      	subs	r1, #252	; 0xfc
+    19ba:	438b      	bics	r3, r1
+    19bc:	4313      	orrs	r3, r2
+    19be:	70c3      	strb	r3, [r0, #3]
+    19c0:	78c3      	ldrb	r3, [r0, #3]
+    19c2:	43ab      	bics	r3, r5
+    19c4:	4323      	orrs	r3, r4
+    19c6:	70c3      	strb	r3, [r0, #3]
+    19c8:	4b18      	ldr	r3, [pc, #96]	; (1a2c <Reset_Handler+0xac>)
+    19ca:	7b98      	ldrb	r0, [r3, #14]
+    19cc:	43b0      	bics	r0, r6
+    19ce:	0006      	movs	r6, r0
+    19d0:	2020      	movs	r0, #32
+    19d2:	4330      	orrs	r0, r6
+    19d4:	7398      	strb	r0, [r3, #14]
+    19d6:	7b98      	ldrb	r0, [r3, #14]
+    19d8:	43a8      	bics	r0, r5
+    19da:	4304      	orrs	r4, r0
+    19dc:	739c      	strb	r4, [r3, #14]
+    19de:	7b98      	ldrb	r0, [r3, #14]
+    19e0:	4388      	bics	r0, r1
+    19e2:	4302      	orrs	r2, r0
+    19e4:	739a      	strb	r2, [r3, #14]
+    19e6:	2380      	movs	r3, #128	; 0x80
+    19e8:	4a11      	ldr	r2, [pc, #68]	; (1a30 <Reset_Handler+0xb0>)
+    19ea:	6851      	ldr	r1, [r2, #4]
+    19ec:	430b      	orrs	r3, r1
+    19ee:	6053      	str	r3, [r2, #4]
+    19f0:	4b10      	ldr	r3, [pc, #64]	; (1a34 <Reset_Handler+0xb4>)
+    19f2:	4798      	blx	r3
+    19f4:	4b10      	ldr	r3, [pc, #64]	; (1a38 <Reset_Handler+0xb8>)
+    19f6:	4798      	blx	r3
+    19f8:	e7fe      	b.n	19f8 <Reset_Handler+0x78>
+    19fa:	58c5      	ldr	r5, [r0, r3]
+    19fc:	3304      	adds	r3, #4
+    19fe:	6015      	str	r5, [r2, #0]
+    1a00:	e7c5      	b.n	198e <Reset_Handler+0xe>
+    1a02:	c302      	stmia	r3!, {r1}
+    1a04:	e7c9      	b.n	199a <Reset_Handler+0x1a>
+    1a06:	46c0      	nop			; (mov r8, r8)
+    1a08:	00005b54 	.word	0x00005b54
+    1a0c:	20000000 	.word	0x20000000
+    1a10:	2000007c 	.word	0x2000007c
+    1a14:	20000080 	.word	0x20000080
+    1a18:	200002a0 	.word	0x200002a0
+    1a1c:	00000000 	.word	0x00000000
+    1a20:	e000ed00 	.word	0xe000ed00
+    1a24:	410070fc 	.word	0x410070fc
+    1a28:	41005000 	.word	0x41005000
+    1a2c:	41004800 	.word	0x41004800
+    1a30:	41004000 	.word	0x41004000
+    1a34:	000047cd 	.word	0x000047cd
+    1a38:	00001a75 	.word	0x00001a75
+
+00001a3c <_sbrk>:
+    1a3c:	4b05      	ldr	r3, [pc, #20]	; (1a54 <_sbrk+0x18>)
+    1a3e:	0002      	movs	r2, r0
+    1a40:	6819      	ldr	r1, [r3, #0]
+    1a42:	2900      	cmp	r1, #0
+    1a44:	d101      	bne.n	1a4a <_sbrk+0xe>
+    1a46:	4904      	ldr	r1, [pc, #16]	; (1a58 <_sbrk+0x1c>)
+    1a48:	6019      	str	r1, [r3, #0]
+    1a4a:	6818      	ldr	r0, [r3, #0]
+    1a4c:	1882      	adds	r2, r0, r2
+    1a4e:	601a      	str	r2, [r3, #0]
+    1a50:	4770      	bx	lr
+    1a52:	46c0      	nop			; (mov r8, r8)
+    1a54:	200001c8 	.word	0x200001c8
+    1a58:	200022a0 	.word	0x200022a0
+
+00001a5c <_close>:
+    1a5c:	2001      	movs	r0, #1
+    1a5e:	4240      	negs	r0, r0
+    1a60:	4770      	bx	lr
+
+00001a62 <_fstat>:
+    1a62:	2380      	movs	r3, #128	; 0x80
+    1a64:	019b      	lsls	r3, r3, #6
+    1a66:	2000      	movs	r0, #0
+    1a68:	604b      	str	r3, [r1, #4]
+    1a6a:	4770      	bx	lr
+
+00001a6c <_isatty>:
+    1a6c:	2001      	movs	r0, #1
+    1a6e:	4770      	bx	lr
+
+00001a70 <_lseek>:
+    1a70:	2000      	movs	r0, #0
+    1a72:	4770      	bx	lr
+
+00001a74 <main>:
+    1a74:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    1a76:	4b41      	ldr	r3, [pc, #260]	; (1b7c <main+0x108>)
+    1a78:	4798      	blx	r3
+    1a7a:	4b41      	ldr	r3, [pc, #260]	; (1b80 <main+0x10c>)
+    1a7c:	4798      	blx	r3
+    1a7e:	2201      	movs	r2, #1
+    1a80:	4b40      	ldr	r3, [pc, #256]	; (1b84 <main+0x110>)
+    1a82:	701a      	strb	r2, [r3, #0]
+    1a84:	f3bf 8f5f 	dmb	sy
+    1a88:	b662      	cpsie	i
+    1a8a:	4b3f      	ldr	r3, [pc, #252]	; (1b88 <main+0x114>)
+    1a8c:	4798      	blx	r3
+    1a8e:	4b3f      	ldr	r3, [pc, #252]	; (1b8c <main+0x118>)
+    1a90:	4798      	blx	r3
+    1a92:	4b3f      	ldr	r3, [pc, #252]	; (1b90 <main+0x11c>)
+    1a94:	4798      	blx	r3
+    1a96:	211b      	movs	r1, #27
+    1a98:	4c3e      	ldr	r4, [pc, #248]	; (1b94 <main+0x120>)
+    1a9a:	483f      	ldr	r0, [pc, #252]	; (1b98 <main+0x124>)
+    1a9c:	47a0      	blx	r4
+    1a9e:	211b      	movs	r1, #27
+    1aa0:	483e      	ldr	r0, [pc, #248]	; (1b9c <main+0x128>)
+    1aa2:	47a0      	blx	r4
+    1aa4:	483e      	ldr	r0, [pc, #248]	; (1ba0 <main+0x12c>)
+    1aa6:	4b3f      	ldr	r3, [pc, #252]	; (1ba4 <main+0x130>)
+    1aa8:	4798      	blx	r3
+    1aaa:	4b3f      	ldr	r3, [pc, #252]	; (1ba8 <main+0x134>)
+    1aac:	4798      	blx	r3
+    1aae:	4b3f      	ldr	r3, [pc, #252]	; (1bac <main+0x138>)
+    1ab0:	493f      	ldr	r1, [pc, #252]	; (1bb0 <main+0x13c>)
+    1ab2:	1c06      	adds	r6, r0, #0
+    1ab4:	4798      	blx	r3
+    1ab6:	4f3f      	ldr	r7, [pc, #252]	; (1bb4 <main+0x140>)
+    1ab8:	47b8      	blx	r7
+    1aba:	9000      	str	r0, [sp, #0]
+    1abc:	9101      	str	r1, [sp, #4]
+    1abe:	1c30      	adds	r0, r6, #0
+    1ac0:	47b8      	blx	r7
+    1ac2:	4c3d      	ldr	r4, [pc, #244]	; (1bb8 <main+0x144>)
+    1ac4:	0002      	movs	r2, r0
+    1ac6:	000b      	movs	r3, r1
+    1ac8:	483c      	ldr	r0, [pc, #240]	; (1bbc <main+0x148>)
+    1aca:	493d      	ldr	r1, [pc, #244]	; (1bc0 <main+0x14c>)
+    1acc:	47a0      	blx	r4
+    1ace:	4c3d      	ldr	r4, [pc, #244]	; (1bc4 <main+0x150>)
+    1ad0:	0002      	movs	r2, r0
+    1ad2:	000b      	movs	r3, r1
+    1ad4:	9800      	ldr	r0, [sp, #0]
+    1ad6:	9901      	ldr	r1, [sp, #4]
+    1ad8:	47a0      	blx	r4
+    1ada:	4b3b      	ldr	r3, [pc, #236]	; (1bc8 <main+0x154>)
+    1adc:	4798      	blx	r3
+    1ade:	4b3b      	ldr	r3, [pc, #236]	; (1bcc <main+0x158>)
+    1ae0:	4798      	blx	r3
+    1ae2:	4c3b      	ldr	r4, [pc, #236]	; (1bd0 <main+0x15c>)
+    1ae4:	4a3b      	ldr	r2, [pc, #236]	; (1bd4 <main+0x160>)
+    1ae6:	4b3c      	ldr	r3, [pc, #240]	; (1bd8 <main+0x164>)
+    1ae8:	47a0      	blx	r4
+    1aea:	4b3c      	ldr	r3, [pc, #240]	; (1bdc <main+0x168>)
+    1aec:	4798      	blx	r3
+    1aee:	4a3c      	ldr	r2, [pc, #240]	; (1be0 <main+0x16c>)
+    1af0:	4b3c      	ldr	r3, [pc, #240]	; (1be4 <main+0x170>)
+    1af2:	47a0      	blx	r4
+    1af4:	4c3c      	ldr	r4, [pc, #240]	; (1be8 <main+0x174>)
+    1af6:	4a3d      	ldr	r2, [pc, #244]	; (1bec <main+0x178>)
+    1af8:	4b3d      	ldr	r3, [pc, #244]	; (1bf0 <main+0x17c>)
+    1afa:	47a0      	blx	r4
+    1afc:	4c31      	ldr	r4, [pc, #196]	; (1bc4 <main+0x150>)
+    1afe:	0002      	movs	r2, r0
+    1b00:	000b      	movs	r3, r1
+    1b02:	2000      	movs	r0, #0
+    1b04:	493b      	ldr	r1, [pc, #236]	; (1bf4 <main+0x180>)
+    1b06:	47a0      	blx	r4
+    1b08:	4c3b      	ldr	r4, [pc, #236]	; (1bf8 <main+0x184>)
+    1b0a:	47a0      	blx	r4
+    1b0c:	47b8      	blx	r7
+    1b0e:	4a2b      	ldr	r2, [pc, #172]	; (1bbc <main+0x148>)
+    1b10:	4b3a      	ldr	r3, [pc, #232]	; (1bfc <main+0x188>)
+    1b12:	4d29      	ldr	r5, [pc, #164]	; (1bb8 <main+0x144>)
+    1b14:	47a8      	blx	r5
+    1b16:	47a0      	blx	r4
+    1b18:	4d39      	ldr	r5, [pc, #228]	; (1c00 <main+0x18c>)
+    1b1a:	1c07      	adds	r7, r0, #0
+    1b1c:	1c30      	adds	r0, r6, #0
+    1b1e:	47a8      	blx	r5
+    1b20:	4b38      	ldr	r3, [pc, #224]	; (1c04 <main+0x190>)
+    1b22:	0004      	movs	r4, r0
+    1b24:	4798      	blx	r3
+    1b26:	4b38      	ldr	r3, [pc, #224]	; (1c08 <main+0x194>)
+    1b28:	1c01      	adds	r1, r0, #0
+    1b2a:	1c30      	adds	r0, r6, #0
+    1b2c:	4798      	blx	r3
+    1b2e:	4b1f      	ldr	r3, [pc, #124]	; (1bac <main+0x138>)
+    1b30:	4936      	ldr	r1, [pc, #216]	; (1c0c <main+0x198>)
+    1b32:	4798      	blx	r3
+    1b34:	47a8      	blx	r5
+    1b36:	0021      	movs	r1, r4
+    1b38:	0002      	movs	r2, r0
+    1b3a:	4c16      	ldr	r4, [pc, #88]	; (1b94 <main+0x120>)
+    1b3c:	4834      	ldr	r0, [pc, #208]	; (1c10 <main+0x19c>)
+    1b3e:	47a0      	blx	r4
+    1b40:	1c38      	adds	r0, r7, #0
+    1b42:	47a8      	blx	r5
+    1b44:	4b2f      	ldr	r3, [pc, #188]	; (1c04 <main+0x190>)
+    1b46:	0006      	movs	r6, r0
+    1b48:	4798      	blx	r3
+    1b4a:	4b2f      	ldr	r3, [pc, #188]	; (1c08 <main+0x194>)
+    1b4c:	1c01      	adds	r1, r0, #0
+    1b4e:	1c38      	adds	r0, r7, #0
+    1b50:	4798      	blx	r3
+    1b52:	47a8      	blx	r5
+    1b54:	22fa      	movs	r2, #250	; 0xfa
+    1b56:	0092      	lsls	r2, r2, #2
+    1b58:	4342      	muls	r2, r0
+    1b5a:	0031      	movs	r1, r6
+    1b5c:	482d      	ldr	r0, [pc, #180]	; (1c14 <main+0x1a0>)
+    1b5e:	47a0      	blx	r4
+    1b60:	20fa      	movs	r0, #250	; 0xfa
+    1b62:	4b2d      	ldr	r3, [pc, #180]	; (1c18 <main+0x1a4>)
+    1b64:	0040      	lsls	r0, r0, #1
+    1b66:	4798      	blx	r3
+    1b68:	211b      	movs	r1, #27
+    1b6a:	482c      	ldr	r0, [pc, #176]	; (1c1c <main+0x1a8>)
+    1b6c:	47a0      	blx	r4
+    1b6e:	211b      	movs	r1, #27
+    1b70:	480a      	ldr	r0, [pc, #40]	; (1b9c <main+0x128>)
+    1b72:	47a0      	blx	r4
+    1b74:	211b      	movs	r1, #27
+    1b76:	482a      	ldr	r0, [pc, #168]	; (1c20 <main+0x1ac>)
+    1b78:	47a0      	blx	r4
+    1b7a:	e796      	b.n	1aaa <main+0x36>
+    1b7c:	00001951 	.word	0x00001951
+    1b80:	0000130d 	.word	0x0000130d
+    1b84:	20000014 	.word	0x20000014
+    1b88:	00000ca1 	.word	0x00000ca1
+    1b8c:	00000b19 	.word	0x00000b19
+    1b90:	00000bf1 	.word	0x00000bf1
+    1b94:	00004839 	.word	0x00004839
+    1b98:	00005958 	.word	0x00005958
+    1b9c:	0000595e 	.word	0x0000595e
+    1ba0:	00005963 	.word	0x00005963
+    1ba4:	0000492d 	.word	0x0000492d
+    1ba8:	00000c41 	.word	0x00000c41
+    1bac:	00002399 	.word	0x00002399
+    1bb0:	461c4000 	.word	0x461c4000
+    1bb4:	000045cd 	.word	0x000045cd
+    1bb8:	00003e05 	.word	0x00003e05
+    1bbc:	66666666 	.word	0x66666666
+    1bc0:	400a6666 	.word	0x400a6666
+    1bc4:	0000309d 	.word	0x0000309d
+    1bc8:	0000235d 	.word	0x0000235d
+    1bcc:	0000455d 	.word	0x0000455d
+    1bd0:	00003905 	.word	0x00003905
+    1bd4:	eb1c432d 	.word	0xeb1c432d
+    1bd8:	3f1a36e2 	.word	0x3f1a36e2
+    1bdc:	00001c25 	.word	0x00001c25
+    1be0:	61261cd8 	.word	0x61261cd8
+    1be4:	3f31329f 	.word	0x3f31329f
+    1be8:	00002a7d 	.word	0x00002a7d
+    1bec:	a0f7e55d 	.word	0xa0f7e55d
+    1bf0:	3f6b79e1 	.word	0x3f6b79e1
+    1bf4:	3ff00000 	.word	0x3ff00000
+    1bf8:	00004671 	.word	0x00004671
+    1bfc:	40711266 	.word	0x40711266
+    1c00:	00002911 	.word	0x00002911
+    1c04:	00002951 	.word	0x00002951
+    1c08:	000025d9 	.word	0x000025d9
+    1c0c:	447a0000 	.word	0x447a0000
+    1c10:	0000599f 	.word	0x0000599f
+    1c14:	000059b1 	.word	0x000059b1
+    1c18:	0000134d 	.word	0x0000134d
+    1c1c:	000059c6 	.word	0x000059c6
+    1c20:	000059cc 	.word	0x000059cc
+
+00001c24 <log>:
+    1c24:	b5f0      	push	{r4, r5, r6, r7, lr}
+    1c26:	46c6      	mov	lr, r8
+    1c28:	b500      	push	{lr}
+    1c2a:	b08c      	sub	sp, #48	; 0x30
+    1c2c:	0004      	movs	r4, r0
+    1c2e:	000d      	movs	r5, r1
+    1c30:	f000 f880 	bl	1d34 <__ieee754_log>
+    1c34:	4b3a      	ldr	r3, [pc, #232]	; (1d20 <log+0xfc>)
+    1c36:	0006      	movs	r6, r0
+    1c38:	781b      	ldrb	r3, [r3, #0]
+    1c3a:	000f      	movs	r7, r1
+    1c3c:	b25b      	sxtb	r3, r3
+    1c3e:	4698      	mov	r8, r3
+    1c40:	3301      	adds	r3, #1
+    1c42:	d00f      	beq.n	1c64 <log+0x40>
+    1c44:	0022      	movs	r2, r4
+    1c46:	002b      	movs	r3, r5
+    1c48:	0020      	movs	r0, r4
+    1c4a:	0029      	movs	r1, r5
+    1c4c:	f002 fbf0 	bl	4430 <__aeabi_dcmpun>
+    1c50:	2800      	cmp	r0, #0
+    1c52:	d107      	bne.n	1c64 <log+0x40>
+    1c54:	2200      	movs	r2, #0
+    1c56:	2300      	movs	r3, #0
+    1c58:	0020      	movs	r0, r4
+    1c5a:	0029      	movs	r1, r5
+    1c5c:	f000 fb40 	bl	22e0 <__aeabi_dcmpgt>
+    1c60:	2800      	cmp	r0, #0
+    1c62:	d005      	beq.n	1c70 <log+0x4c>
+    1c64:	0030      	movs	r0, r6
+    1c66:	0039      	movs	r1, r7
+    1c68:	b00c      	add	sp, #48	; 0x30
+    1c6a:	bc04      	pop	{r2}
+    1c6c:	4690      	mov	r8, r2
+    1c6e:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    1c70:	4b2c      	ldr	r3, [pc, #176]	; (1d24 <log+0x100>)
+    1c72:	900a      	str	r0, [sp, #40]	; 0x28
+    1c74:	9303      	str	r3, [sp, #12]
+    1c76:	4643      	mov	r3, r8
+    1c78:	9404      	str	r4, [sp, #16]
+    1c7a:	9505      	str	r5, [sp, #20]
+    1c7c:	9406      	str	r4, [sp, #24]
+    1c7e:	9507      	str	r5, [sp, #28]
+    1c80:	2b00      	cmp	r3, #0
+    1c82:	d11a      	bne.n	1cba <log+0x96>
+    1c84:	22e0      	movs	r2, #224	; 0xe0
+    1c86:	4b28      	ldr	r3, [pc, #160]	; (1d28 <log+0x104>)
+    1c88:	0612      	lsls	r2, r2, #24
+    1c8a:	9208      	str	r2, [sp, #32]
+    1c8c:	9309      	str	r3, [sp, #36]	; 0x24
+    1c8e:	0020      	movs	r0, r4
+    1c90:	2200      	movs	r2, #0
+    1c92:	2300      	movs	r3, #0
+    1c94:	0029      	movs	r1, r5
+    1c96:	f000 fb09 	bl	22ac <__aeabi_dcmpeq>
+    1c9a:	2800      	cmp	r0, #0
+    1c9c:	d038      	beq.n	1d10 <log+0xec>
+    1c9e:	2302      	movs	r3, #2
+    1ca0:	9302      	str	r3, [sp, #8]
+    1ca2:	a802      	add	r0, sp, #8
+    1ca4:	f000 fa48 	bl	2138 <matherr>
+    1ca8:	2800      	cmp	r0, #0
+    1caa:	d017      	beq.n	1cdc <log+0xb8>
+    1cac:	9b0a      	ldr	r3, [sp, #40]	; 0x28
+    1cae:	9301      	str	r3, [sp, #4]
+    1cb0:	2b00      	cmp	r3, #0
+    1cb2:	d118      	bne.n	1ce6 <log+0xc2>
+    1cb4:	9e08      	ldr	r6, [sp, #32]
+    1cb6:	9f09      	ldr	r7, [sp, #36]	; 0x24
+    1cb8:	e7d4      	b.n	1c64 <log+0x40>
+    1cba:	2200      	movs	r2, #0
+    1cbc:	4b1b      	ldr	r3, [pc, #108]	; (1d2c <log+0x108>)
+    1cbe:	0020      	movs	r0, r4
+    1cc0:	9208      	str	r2, [sp, #32]
+    1cc2:	9309      	str	r3, [sp, #36]	; 0x24
+    1cc4:	0029      	movs	r1, r5
+    1cc6:	2200      	movs	r2, #0
+    1cc8:	2300      	movs	r3, #0
+    1cca:	f000 faef 	bl	22ac <__aeabi_dcmpeq>
+    1cce:	2800      	cmp	r0, #0
+    1cd0:	d00f      	beq.n	1cf2 <log+0xce>
+    1cd2:	2302      	movs	r3, #2
+    1cd4:	9302      	str	r3, [sp, #8]
+    1cd6:	4643      	mov	r3, r8
+    1cd8:	2b02      	cmp	r3, #2
+    1cda:	d1e2      	bne.n	1ca2 <log+0x7e>
+    1cdc:	f002 fd70 	bl	47c0 <__errno>
+    1ce0:	2322      	movs	r3, #34	; 0x22
+    1ce2:	6003      	str	r3, [r0, #0]
+    1ce4:	e7e2      	b.n	1cac <log+0x88>
+    1ce6:	f002 fd6b 	bl	47c0 <__errno>
+    1cea:	9b0a      	ldr	r3, [sp, #40]	; 0x28
+    1cec:	9301      	str	r3, [sp, #4]
+    1cee:	6003      	str	r3, [r0, #0]
+    1cf0:	e7e0      	b.n	1cb4 <log+0x90>
+    1cf2:	2301      	movs	r3, #1
+    1cf4:	9302      	str	r3, [sp, #8]
+    1cf6:	4643      	mov	r3, r8
+    1cf8:	2b02      	cmp	r3, #2
+    1cfa:	d10b      	bne.n	1d14 <log+0xf0>
+    1cfc:	f002 fd60 	bl	47c0 <__errno>
+    1d00:	2321      	movs	r3, #33	; 0x21
+    1d02:	6003      	str	r3, [r0, #0]
+    1d04:	480a      	ldr	r0, [pc, #40]	; (1d30 <log+0x10c>)
+    1d06:	f000 fa19 	bl	213c <nan>
+    1d0a:	9008      	str	r0, [sp, #32]
+    1d0c:	9109      	str	r1, [sp, #36]	; 0x24
+    1d0e:	e7cd      	b.n	1cac <log+0x88>
+    1d10:	2301      	movs	r3, #1
+    1d12:	9302      	str	r3, [sp, #8]
+    1d14:	a802      	add	r0, sp, #8
+    1d16:	f000 fa0f 	bl	2138 <matherr>
+    1d1a:	2800      	cmp	r0, #0
+    1d1c:	d1f2      	bne.n	1d04 <log+0xe0>
+    1d1e:	e7ed      	b.n	1cfc <log+0xd8>
+    1d20:	20000015 	.word	0x20000015
+    1d24:	000059d4 	.word	0x000059d4
+    1d28:	c7efffff 	.word	0xc7efffff
+    1d2c:	fff00000 	.word	0xfff00000
+    1d30:	000059d8 	.word	0x000059d8
+
+00001d34 <__ieee754_log>:
+    1d34:	b5f0      	push	{r4, r5, r6, r7, lr}
+    1d36:	46d6      	mov	lr, sl
+    1d38:	464f      	mov	r7, r9
+    1d3a:	4646      	mov	r6, r8
+    1d3c:	b5c0      	push	{r6, r7, lr}
+    1d3e:	4ada      	ldr	r2, [pc, #872]	; (20a8 <STACK_SIZE+0xa8>)
+    1d40:	b088      	sub	sp, #32
+    1d42:	000b      	movs	r3, r1
+    1d44:	4291      	cmp	r1, r2
+    1d46:	dc55      	bgt.n	1df4 <__ieee754_log+0xc0>
+    1d48:	004a      	lsls	r2, r1, #1
+    1d4a:	0852      	lsrs	r2, r2, #1
+    1d4c:	4302      	orrs	r2, r0
+    1d4e:	d100      	bne.n	1d52 <__ieee754_log+0x1e>
+    1d50:	e0ef      	b.n	1f32 <__ieee754_log+0x1fe>
+    1d52:	2900      	cmp	r1, #0
+    1d54:	da00      	bge.n	1d58 <__ieee754_log+0x24>
+    1d56:	e179      	b.n	204c <STACK_SIZE+0x4c>
+    1d58:	4bd4      	ldr	r3, [pc, #848]	; (20ac <STACK_SIZE+0xac>)
+    1d5a:	2200      	movs	r2, #0
+    1d5c:	f001 fdd2 	bl	3904 <__aeabi_dmul>
+    1d60:	2536      	movs	r5, #54	; 0x36
+    1d62:	4cd3      	ldr	r4, [pc, #844]	; (20b0 <STACK_SIZE+0xb0>)
+    1d64:	000b      	movs	r3, r1
+    1d66:	426d      	negs	r5, r5
+    1d68:	42a3      	cmp	r3, r4
+    1d6a:	dc47      	bgt.n	1dfc <__ieee754_log+0xc8>
+    1d6c:	151a      	asrs	r2, r3, #20
+    1d6e:	4cd1      	ldr	r4, [pc, #836]	; (20b4 <STACK_SIZE+0xb4>)
+    1d70:	031b      	lsls	r3, r3, #12
+    1d72:	0b1b      	lsrs	r3, r3, #12
+    1d74:	4698      	mov	r8, r3
+    1d76:	46a4      	mov	ip, r4
+    1d78:	2480      	movs	r4, #128	; 0x80
+    1d7a:	4bcf      	ldr	r3, [pc, #828]	; (20b8 <STACK_SIZE+0xb8>)
+    1d7c:	0364      	lsls	r4, r4, #13
+    1d7e:	4443      	add	r3, r8
+    1d80:	4023      	ands	r3, r4
+    1d82:	4cce      	ldr	r4, [pc, #824]	; (20bc <STACK_SIZE+0xbc>)
+    1d84:	4462      	add	r2, ip
+    1d86:	1952      	adds	r2, r2, r5
+    1d88:	405c      	eors	r4, r3
+    1d8a:	4645      	mov	r5, r8
+    1d8c:	151b      	asrs	r3, r3, #20
+    1d8e:	4699      	mov	r9, r3
+    1d90:	4325      	orrs	r5, r4
+    1d92:	4bca      	ldr	r3, [pc, #808]	; (20bc <STACK_SIZE+0xbc>)
+    1d94:	0029      	movs	r1, r5
+    1d96:	4491      	add	r9, r2
+    1d98:	2200      	movs	r2, #0
+    1d9a:	f002 f833 	bl	3e04 <__aeabi_dsub>
+    1d9e:	4643      	mov	r3, r8
+    1da0:	3302      	adds	r3, #2
+    1da2:	031b      	lsls	r3, r3, #12
+    1da4:	0006      	movs	r6, r0
+    1da6:	000f      	movs	r7, r1
+    1da8:	0b1b      	lsrs	r3, r3, #12
+    1daa:	2200      	movs	r2, #0
+    1dac:	2b02      	cmp	r3, #2
+    1dae:	dc2f      	bgt.n	1e10 <__ieee754_log+0xdc>
+    1db0:	2300      	movs	r3, #0
+    1db2:	f000 fa7b 	bl	22ac <__aeabi_dcmpeq>
+    1db6:	2800      	cmp	r0, #0
+    1db8:	d100      	bne.n	1dbc <__ieee754_log+0x88>
+    1dba:	e0c1      	b.n	1f40 <__ieee754_log+0x20c>
+    1dbc:	464b      	mov	r3, r9
+    1dbe:	2b00      	cmp	r3, #0
+    1dc0:	d100      	bne.n	1dc4 <__ieee754_log+0x90>
+    1dc2:	e14c      	b.n	205e <STACK_SIZE+0x5e>
+    1dc4:	4648      	mov	r0, r9
+    1dc6:	f002 fb87 	bl	44d8 <__aeabi_i2d>
+    1dca:	4abd      	ldr	r2, [pc, #756]	; (20c0 <STACK_SIZE+0xc0>)
+    1dcc:	4bbd      	ldr	r3, [pc, #756]	; (20c4 <STACK_SIZE+0xc4>)
+    1dce:	0004      	movs	r4, r0
+    1dd0:	000d      	movs	r5, r1
+    1dd2:	f001 fd97 	bl	3904 <__aeabi_dmul>
+    1dd6:	4abc      	ldr	r2, [pc, #752]	; (20c8 <STACK_SIZE+0xc8>)
+    1dd8:	0006      	movs	r6, r0
+    1dda:	000f      	movs	r7, r1
+    1ddc:	4bbb      	ldr	r3, [pc, #748]	; (20cc <STACK_SIZE+0xcc>)
+    1dde:	0020      	movs	r0, r4
+    1de0:	0029      	movs	r1, r5
+    1de2:	f001 fd8f 	bl	3904 <__aeabi_dmul>
+    1de6:	0002      	movs	r2, r0
+    1de8:	000b      	movs	r3, r1
+    1dea:	0030      	movs	r0, r6
+    1dec:	0039      	movs	r1, r7
+    1dee:	f000 fe45 	bl	2a7c <__aeabi_dadd>
+    1df2:	e007      	b.n	1e04 <__ieee754_log+0xd0>
+    1df4:	4cae      	ldr	r4, [pc, #696]	; (20b0 <STACK_SIZE+0xb0>)
+    1df6:	2500      	movs	r5, #0
+    1df8:	42a3      	cmp	r3, r4
+    1dfa:	ddb7      	ble.n	1d6c <__ieee754_log+0x38>
+    1dfc:	0002      	movs	r2, r0
+    1dfe:	000b      	movs	r3, r1
+    1e00:	f000 fe3c 	bl	2a7c <__aeabi_dadd>
+    1e04:	b008      	add	sp, #32
+    1e06:	bc1c      	pop	{r2, r3, r4}
+    1e08:	4690      	mov	r8, r2
+    1e0a:	4699      	mov	r9, r3
+    1e0c:	46a2      	mov	sl, r4
+    1e0e:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    1e10:	2380      	movs	r3, #128	; 0x80
+    1e12:	05db      	lsls	r3, r3, #23
+    1e14:	f000 fe32 	bl	2a7c <__aeabi_dadd>
+    1e18:	0002      	movs	r2, r0
+    1e1a:	000b      	movs	r3, r1
+    1e1c:	0030      	movs	r0, r6
+    1e1e:	0039      	movs	r1, r7
+    1e20:	f001 f93c 	bl	309c <__aeabi_ddiv>
+    1e24:	0004      	movs	r4, r0
+    1e26:	4648      	mov	r0, r9
+    1e28:	000d      	movs	r5, r1
+    1e2a:	f002 fb55 	bl	44d8 <__aeabi_i2d>
+    1e2e:	0022      	movs	r2, r4
+    1e30:	9002      	str	r0, [sp, #8]
+    1e32:	9103      	str	r1, [sp, #12]
+    1e34:	002b      	movs	r3, r5
+    1e36:	0020      	movs	r0, r4
+    1e38:	0029      	movs	r1, r5
+    1e3a:	9404      	str	r4, [sp, #16]
+    1e3c:	9505      	str	r5, [sp, #20]
+    1e3e:	f001 fd61 	bl	3904 <__aeabi_dmul>
+    1e42:	0004      	movs	r4, r0
+    1e44:	000d      	movs	r5, r1
+    1e46:	4ba2      	ldr	r3, [pc, #648]	; (20d0 <STACK_SIZE+0xd0>)
+    1e48:	0002      	movs	r2, r0
+    1e4a:	4443      	add	r3, r8
+    1e4c:	469a      	mov	sl, r3
+    1e4e:	000b      	movs	r3, r1
+    1e50:	9400      	str	r4, [sp, #0]
+    1e52:	9501      	str	r5, [sp, #4]
+    1e54:	f001 fd56 	bl	3904 <__aeabi_dmul>
+    1e58:	0004      	movs	r4, r0
+    1e5a:	000d      	movs	r5, r1
+    1e5c:	4a9d      	ldr	r2, [pc, #628]	; (20d4 <STACK_SIZE+0xd4>)
+    1e5e:	4b9e      	ldr	r3, [pc, #632]	; (20d8 <STACK_SIZE+0xd8>)
+    1e60:	f001 fd50 	bl	3904 <__aeabi_dmul>
+    1e64:	4a9d      	ldr	r2, [pc, #628]	; (20dc <STACK_SIZE+0xdc>)
+    1e66:	4b9e      	ldr	r3, [pc, #632]	; (20e0 <STACK_SIZE+0xe0>)
+    1e68:	f000 fe08 	bl	2a7c <__aeabi_dadd>
+    1e6c:	0022      	movs	r2, r4
+    1e6e:	002b      	movs	r3, r5
+    1e70:	f001 fd48 	bl	3904 <__aeabi_dmul>
+    1e74:	4a9b      	ldr	r2, [pc, #620]	; (20e4 <STACK_SIZE+0xe4>)
+    1e76:	4b9c      	ldr	r3, [pc, #624]	; (20e8 <STACK_SIZE+0xe8>)
+    1e78:	f000 fe00 	bl	2a7c <__aeabi_dadd>
+    1e7c:	0022      	movs	r2, r4
+    1e7e:	002b      	movs	r3, r5
+    1e80:	f001 fd40 	bl	3904 <__aeabi_dmul>
+    1e84:	4a99      	ldr	r2, [pc, #612]	; (20ec <STACK_SIZE+0xec>)
+    1e86:	4b9a      	ldr	r3, [pc, #616]	; (20f0 <STACK_SIZE+0xf0>)
+    1e88:	f000 fdf8 	bl	2a7c <__aeabi_dadd>
+    1e8c:	9a00      	ldr	r2, [sp, #0]
+    1e8e:	9b01      	ldr	r3, [sp, #4]
+    1e90:	f001 fd38 	bl	3904 <__aeabi_dmul>
+    1e94:	4a97      	ldr	r2, [pc, #604]	; (20f4 <STACK_SIZE+0xf4>)
+    1e96:	9000      	str	r0, [sp, #0]
+    1e98:	9101      	str	r1, [sp, #4]
+    1e9a:	4b97      	ldr	r3, [pc, #604]	; (20f8 <STACK_SIZE+0xf8>)
+    1e9c:	0020      	movs	r0, r4
+    1e9e:	0029      	movs	r1, r5
+    1ea0:	f001 fd30 	bl	3904 <__aeabi_dmul>
+    1ea4:	4a95      	ldr	r2, [pc, #596]	; (20fc <STACK_SIZE+0xfc>)
+    1ea6:	4b96      	ldr	r3, [pc, #600]	; (2100 <STACK_SIZE+0x100>)
+    1ea8:	f000 fde8 	bl	2a7c <__aeabi_dadd>
+    1eac:	0022      	movs	r2, r4
+    1eae:	002b      	movs	r3, r5
+    1eb0:	f001 fd28 	bl	3904 <__aeabi_dmul>
+    1eb4:	4a93      	ldr	r2, [pc, #588]	; (2104 <STACK_SIZE+0x104>)
+    1eb6:	4b94      	ldr	r3, [pc, #592]	; (2108 <STACK_SIZE+0x108>)
+    1eb8:	f000 fde0 	bl	2a7c <__aeabi_dadd>
+    1ebc:	0022      	movs	r2, r4
+    1ebe:	002b      	movs	r3, r5
+    1ec0:	f001 fd20 	bl	3904 <__aeabi_dmul>
+    1ec4:	000b      	movs	r3, r1
+    1ec6:	0002      	movs	r2, r0
+    1ec8:	9800      	ldr	r0, [sp, #0]
+    1eca:	9901      	ldr	r1, [sp, #4]
+    1ecc:	f000 fdd6 	bl	2a7c <__aeabi_dadd>
+    1ed0:	000d      	movs	r5, r1
+    1ed2:	4641      	mov	r1, r8
+    1ed4:	4b8d      	ldr	r3, [pc, #564]	; (210c <STACK_SIZE+0x10c>)
+    1ed6:	0004      	movs	r4, r0
+    1ed8:	1a5b      	subs	r3, r3, r1
+    1eda:	4651      	mov	r1, sl
+    1edc:	430b      	orrs	r3, r1
+    1ede:	2b00      	cmp	r3, #0
+    1ee0:	dd54      	ble.n	1f8c <__ieee754_log+0x258>
+    1ee2:	2200      	movs	r2, #0
+    1ee4:	4b8a      	ldr	r3, [pc, #552]	; (2110 <STACK_SIZE+0x110>)
+    1ee6:	0030      	movs	r0, r6
+    1ee8:	0039      	movs	r1, r7
+    1eea:	f001 fd0b 	bl	3904 <__aeabi_dmul>
+    1eee:	0032      	movs	r2, r6
+    1ef0:	003b      	movs	r3, r7
+    1ef2:	f001 fd07 	bl	3904 <__aeabi_dmul>
+    1ef6:	464b      	mov	r3, r9
+    1ef8:	000a      	movs	r2, r1
+    1efa:	0001      	movs	r1, r0
+    1efc:	9100      	str	r1, [sp, #0]
+    1efe:	9201      	str	r2, [sp, #4]
+    1f00:	2b00      	cmp	r3, #0
+    1f02:	d172      	bne.n	1fea <__ieee754_log+0x2b6>
+    1f04:	0013      	movs	r3, r2
+    1f06:	0029      	movs	r1, r5
+    1f08:	0002      	movs	r2, r0
+    1f0a:	0020      	movs	r0, r4
+    1f0c:	f000 fdb6 	bl	2a7c <__aeabi_dadd>
+    1f10:	9a04      	ldr	r2, [sp, #16]
+    1f12:	9b05      	ldr	r3, [sp, #20]
+    1f14:	f001 fcf6 	bl	3904 <__aeabi_dmul>
+    1f18:	0002      	movs	r2, r0
+    1f1a:	000b      	movs	r3, r1
+    1f1c:	9800      	ldr	r0, [sp, #0]
+    1f1e:	9901      	ldr	r1, [sp, #4]
+    1f20:	f001 ff70 	bl	3e04 <__aeabi_dsub>
+    1f24:	0002      	movs	r2, r0
+    1f26:	000b      	movs	r3, r1
+    1f28:	0030      	movs	r0, r6
+    1f2a:	0039      	movs	r1, r7
+    1f2c:	f001 ff6a 	bl	3e04 <__aeabi_dsub>
+    1f30:	e768      	b.n	1e04 <__ieee754_log+0xd0>
+    1f32:	2200      	movs	r2, #0
+    1f34:	2300      	movs	r3, #0
+    1f36:	2000      	movs	r0, #0
+    1f38:	4976      	ldr	r1, [pc, #472]	; (2114 <STACK_SIZE+0x114>)
+    1f3a:	f001 f8af 	bl	309c <__aeabi_ddiv>
+    1f3e:	e761      	b.n	1e04 <__ieee754_log+0xd0>
+    1f40:	4a75      	ldr	r2, [pc, #468]	; (2118 <STACK_SIZE+0x118>)
+    1f42:	4b76      	ldr	r3, [pc, #472]	; (211c <STACK_SIZE+0x11c>)
+    1f44:	0030      	movs	r0, r6
+    1f46:	0039      	movs	r1, r7
+    1f48:	f001 fcdc 	bl	3904 <__aeabi_dmul>
+    1f4c:	0002      	movs	r2, r0
+    1f4e:	000b      	movs	r3, r1
+    1f50:	2000      	movs	r0, #0
+    1f52:	496f      	ldr	r1, [pc, #444]	; (2110 <STACK_SIZE+0x110>)
+    1f54:	f001 ff56 	bl	3e04 <__aeabi_dsub>
+    1f58:	0032      	movs	r2, r6
+    1f5a:	0004      	movs	r4, r0
+    1f5c:	000d      	movs	r5, r1
+    1f5e:	003b      	movs	r3, r7
+    1f60:	0030      	movs	r0, r6
+    1f62:	0039      	movs	r1, r7
+    1f64:	f001 fcce 	bl	3904 <__aeabi_dmul>
+    1f68:	000b      	movs	r3, r1
+    1f6a:	0002      	movs	r2, r0
+    1f6c:	0029      	movs	r1, r5
+    1f6e:	0020      	movs	r0, r4
+    1f70:	f001 fcc8 	bl	3904 <__aeabi_dmul>
+    1f74:	464b      	mov	r3, r9
+    1f76:	0004      	movs	r4, r0
+    1f78:	000d      	movs	r5, r1
+    1f7a:	2b00      	cmp	r3, #0
+    1f7c:	d172      	bne.n	2064 <STACK_SIZE+0x64>
+    1f7e:	0002      	movs	r2, r0
+    1f80:	000b      	movs	r3, r1
+    1f82:	0030      	movs	r0, r6
+    1f84:	0039      	movs	r1, r7
+    1f86:	f001 ff3d 	bl	3e04 <__aeabi_dsub>
+    1f8a:	e73b      	b.n	1e04 <__ieee754_log+0xd0>
+    1f8c:	464b      	mov	r3, r9
+    1f8e:	2b00      	cmp	r3, #0
+    1f90:	d100      	bne.n	1f94 <__ieee754_log+0x260>
+    1f92:	e0c5      	b.n	2120 <STACK_SIZE+0x120>
+    1f94:	9802      	ldr	r0, [sp, #8]
+    1f96:	9903      	ldr	r1, [sp, #12]
+    1f98:	4a49      	ldr	r2, [pc, #292]	; (20c0 <STACK_SIZE+0xc0>)
+    1f9a:	4b4a      	ldr	r3, [pc, #296]	; (20c4 <STACK_SIZE+0xc4>)
+    1f9c:	f001 fcb2 	bl	3904 <__aeabi_dmul>
+    1fa0:	0022      	movs	r2, r4
+    1fa2:	9000      	str	r0, [sp, #0]
+    1fa4:	9101      	str	r1, [sp, #4]
+    1fa6:	002b      	movs	r3, r5
+    1fa8:	0030      	movs	r0, r6
+    1faa:	0039      	movs	r1, r7
+    1fac:	f001 ff2a 	bl	3e04 <__aeabi_dsub>
+    1fb0:	9a04      	ldr	r2, [sp, #16]
+    1fb2:	9b05      	ldr	r3, [sp, #20]
+    1fb4:	f001 fca6 	bl	3904 <__aeabi_dmul>
+    1fb8:	4a43      	ldr	r2, [pc, #268]	; (20c8 <STACK_SIZE+0xc8>)
+    1fba:	0004      	movs	r4, r0
+    1fbc:	000d      	movs	r5, r1
+    1fbe:	9802      	ldr	r0, [sp, #8]
+    1fc0:	9903      	ldr	r1, [sp, #12]
+    1fc2:	4b42      	ldr	r3, [pc, #264]	; (20cc <STACK_SIZE+0xcc>)
+    1fc4:	f001 fc9e 	bl	3904 <__aeabi_dmul>
+    1fc8:	0002      	movs	r2, r0
+    1fca:	000b      	movs	r3, r1
+    1fcc:	0020      	movs	r0, r4
+    1fce:	0029      	movs	r1, r5
+    1fd0:	f001 ff18 	bl	3e04 <__aeabi_dsub>
+    1fd4:	0032      	movs	r2, r6
+    1fd6:	003b      	movs	r3, r7
+    1fd8:	f001 ff14 	bl	3e04 <__aeabi_dsub>
+    1fdc:	0002      	movs	r2, r0
+    1fde:	000b      	movs	r3, r1
+    1fe0:	9800      	ldr	r0, [sp, #0]
+    1fe2:	9901      	ldr	r1, [sp, #4]
+    1fe4:	f001 ff0e 	bl	3e04 <__aeabi_dsub>
+    1fe8:	e70c      	b.n	1e04 <__ieee754_log+0xd0>
+    1fea:	4a35      	ldr	r2, [pc, #212]	; (20c0 <STACK_SIZE+0xc0>)
+    1fec:	4b35      	ldr	r3, [pc, #212]	; (20c4 <STACK_SIZE+0xc4>)
+    1fee:	9802      	ldr	r0, [sp, #8]
+    1ff0:	9903      	ldr	r1, [sp, #12]
+    1ff2:	f001 fc87 	bl	3904 <__aeabi_dmul>
+    1ff6:	9a00      	ldr	r2, [sp, #0]
+    1ff8:	9b01      	ldr	r3, [sp, #4]
+    1ffa:	9006      	str	r0, [sp, #24]
+    1ffc:	9107      	str	r1, [sp, #28]
+    1ffe:	0020      	movs	r0, r4
+    2000:	0029      	movs	r1, r5
+    2002:	f000 fd3b 	bl	2a7c <__aeabi_dadd>
+    2006:	9a04      	ldr	r2, [sp, #16]
+    2008:	9b05      	ldr	r3, [sp, #20]
+    200a:	f001 fc7b 	bl	3904 <__aeabi_dmul>
+    200e:	4a2e      	ldr	r2, [pc, #184]	; (20c8 <STACK_SIZE+0xc8>)
+    2010:	0004      	movs	r4, r0
+    2012:	000d      	movs	r5, r1
+    2014:	9802      	ldr	r0, [sp, #8]
+    2016:	9903      	ldr	r1, [sp, #12]
+    2018:	4b2c      	ldr	r3, [pc, #176]	; (20cc <STACK_SIZE+0xcc>)
+    201a:	f001 fc73 	bl	3904 <__aeabi_dmul>
+    201e:	0002      	movs	r2, r0
+    2020:	000b      	movs	r3, r1
+    2022:	0020      	movs	r0, r4
+    2024:	0029      	movs	r1, r5
+    2026:	f000 fd29 	bl	2a7c <__aeabi_dadd>
+    202a:	0002      	movs	r2, r0
+    202c:	000b      	movs	r3, r1
+    202e:	9800      	ldr	r0, [sp, #0]
+    2030:	9901      	ldr	r1, [sp, #4]
+    2032:	f001 fee7 	bl	3e04 <__aeabi_dsub>
+    2036:	0032      	movs	r2, r6
+    2038:	003b      	movs	r3, r7
+    203a:	f001 fee3 	bl	3e04 <__aeabi_dsub>
+    203e:	0002      	movs	r2, r0
+    2040:	000b      	movs	r3, r1
+    2042:	9806      	ldr	r0, [sp, #24]
+    2044:	9907      	ldr	r1, [sp, #28]
+    2046:	f001 fedd 	bl	3e04 <__aeabi_dsub>
+    204a:	e6db      	b.n	1e04 <__ieee754_log+0xd0>
+    204c:	0002      	movs	r2, r0
+    204e:	000b      	movs	r3, r1
+    2050:	f001 fed8 	bl	3e04 <__aeabi_dsub>
+    2054:	2200      	movs	r2, #0
+    2056:	2300      	movs	r3, #0
+    2058:	f001 f820 	bl	309c <__aeabi_ddiv>
+    205c:	e6d2      	b.n	1e04 <__ieee754_log+0xd0>
+    205e:	2000      	movs	r0, #0
+    2060:	2100      	movs	r1, #0
+    2062:	e6cf      	b.n	1e04 <__ieee754_log+0xd0>
+    2064:	4648      	mov	r0, r9
+    2066:	f002 fa37 	bl	44d8 <__aeabi_i2d>
+    206a:	4a15      	ldr	r2, [pc, #84]	; (20c0 <STACK_SIZE+0xc0>)
+    206c:	4b15      	ldr	r3, [pc, #84]	; (20c4 <STACK_SIZE+0xc4>)
+    206e:	9000      	str	r0, [sp, #0]
+    2070:	9101      	str	r1, [sp, #4]
+    2072:	f001 fc47 	bl	3904 <__aeabi_dmul>
+    2076:	4a14      	ldr	r2, [pc, #80]	; (20c8 <STACK_SIZE+0xc8>)
+    2078:	9002      	str	r0, [sp, #8]
+    207a:	9103      	str	r1, [sp, #12]
+    207c:	9800      	ldr	r0, [sp, #0]
+    207e:	9901      	ldr	r1, [sp, #4]
+    2080:	4b12      	ldr	r3, [pc, #72]	; (20cc <STACK_SIZE+0xcc>)
+    2082:	f001 fc3f 	bl	3904 <__aeabi_dmul>
+    2086:	0002      	movs	r2, r0
+    2088:	000b      	movs	r3, r1
+    208a:	0020      	movs	r0, r4
+    208c:	0029      	movs	r1, r5
+    208e:	f001 feb9 	bl	3e04 <__aeabi_dsub>
+    2092:	0032      	movs	r2, r6
+    2094:	003b      	movs	r3, r7
+    2096:	f001 feb5 	bl	3e04 <__aeabi_dsub>
+    209a:	0002      	movs	r2, r0
+    209c:	000b      	movs	r3, r1
+    209e:	9802      	ldr	r0, [sp, #8]
+    20a0:	9903      	ldr	r1, [sp, #12]
+    20a2:	f001 feaf 	bl	3e04 <__aeabi_dsub>
+    20a6:	e6ad      	b.n	1e04 <__ieee754_log+0xd0>
+    20a8:	000fffff 	.word	0x000fffff
+    20ac:	43500000 	.word	0x43500000
+    20b0:	7fefffff 	.word	0x7fefffff
+    20b4:	fffffc01 	.word	0xfffffc01
+    20b8:	00095f64 	.word	0x00095f64
+    20bc:	3ff00000 	.word	0x3ff00000
+    20c0:	fee00000 	.word	0xfee00000
+    20c4:	3fe62e42 	.word	0x3fe62e42
+    20c8:	35793c76 	.word	0x35793c76
+    20cc:	3dea39ef 	.word	0x3dea39ef
+    20d0:	fff9eb86 	.word	0xfff9eb86
+    20d4:	df3e5244 	.word	0xdf3e5244
+    20d8:	3fc2f112 	.word	0x3fc2f112
+    20dc:	96cb03de 	.word	0x96cb03de
+    20e0:	3fc74664 	.word	0x3fc74664
+    20e4:	94229359 	.word	0x94229359
+    20e8:	3fd24924 	.word	0x3fd24924
+    20ec:	55555593 	.word	0x55555593
+    20f0:	3fe55555 	.word	0x3fe55555
+    20f4:	d078c69f 	.word	0xd078c69f
+    20f8:	3fc39a09 	.word	0x3fc39a09
+    20fc:	1d8e78af 	.word	0x1d8e78af
+    2100:	3fcc71c5 	.word	0x3fcc71c5
+    2104:	9997fa04 	.word	0x9997fa04
+    2108:	3fd99999 	.word	0x3fd99999
+    210c:	0006b851 	.word	0x0006b851
+    2110:	3fe00000 	.word	0x3fe00000
+    2114:	c3500000 	.word	0xc3500000
+    2118:	55555555 	.word	0x55555555
+    211c:	3fd55555 	.word	0x3fd55555
+    2120:	0022      	movs	r2, r4
+    2122:	002b      	movs	r3, r5
+    2124:	0030      	movs	r0, r6
+    2126:	0039      	movs	r1, r7
+    2128:	f001 fe6c 	bl	3e04 <__aeabi_dsub>
+    212c:	9a04      	ldr	r2, [sp, #16]
+    212e:	9b05      	ldr	r3, [sp, #20]
+    2130:	f001 fbe8 	bl	3904 <__aeabi_dmul>
+    2134:	e6f6      	b.n	1f24 <__ieee754_log+0x1f0>
+    2136:	46c0      	nop			; (mov r8, r8)
+
+00002138 <matherr>:
+    2138:	2000      	movs	r0, #0
+    213a:	4770      	bx	lr
+
+0000213c <nan>:
+    213c:	2000      	movs	r0, #0
+    213e:	4901      	ldr	r1, [pc, #4]	; (2144 <nan+0x8>)
+    2140:	4770      	bx	lr
+    2142:	46c0      	nop			; (mov r8, r8)
+    2144:	7ff80000 	.word	0x7ff80000
+
+00002148 <__gnu_thumb1_case_uqi>:
+    2148:	b402      	push	{r1}
+    214a:	4671      	mov	r1, lr
+    214c:	0849      	lsrs	r1, r1, #1
+    214e:	0049      	lsls	r1, r1, #1
+    2150:	5c09      	ldrb	r1, [r1, r0]
+    2152:	0049      	lsls	r1, r1, #1
+    2154:	448e      	add	lr, r1
+    2156:	bc02      	pop	{r1}
+    2158:	4770      	bx	lr
+    215a:	46c0      	nop			; (mov r8, r8)
+
+0000215c <__udivsi3>:
+    215c:	2200      	movs	r2, #0
+    215e:	0843      	lsrs	r3, r0, #1
+    2160:	428b      	cmp	r3, r1
+    2162:	d374      	bcc.n	224e <__udivsi3+0xf2>
+    2164:	0903      	lsrs	r3, r0, #4
+    2166:	428b      	cmp	r3, r1
+    2168:	d35f      	bcc.n	222a <__udivsi3+0xce>
+    216a:	0a03      	lsrs	r3, r0, #8
+    216c:	428b      	cmp	r3, r1
+    216e:	d344      	bcc.n	21fa <__udivsi3+0x9e>
+    2170:	0b03      	lsrs	r3, r0, #12
+    2172:	428b      	cmp	r3, r1
+    2174:	d328      	bcc.n	21c8 <__udivsi3+0x6c>
+    2176:	0c03      	lsrs	r3, r0, #16
+    2178:	428b      	cmp	r3, r1
+    217a:	d30d      	bcc.n	2198 <__udivsi3+0x3c>
+    217c:	22ff      	movs	r2, #255	; 0xff
+    217e:	0209      	lsls	r1, r1, #8
+    2180:	ba12      	rev	r2, r2
+    2182:	0c03      	lsrs	r3, r0, #16
+    2184:	428b      	cmp	r3, r1
+    2186:	d302      	bcc.n	218e <__udivsi3+0x32>
+    2188:	1212      	asrs	r2, r2, #8
+    218a:	0209      	lsls	r1, r1, #8
+    218c:	d065      	beq.n	225a <__udivsi3+0xfe>
+    218e:	0b03      	lsrs	r3, r0, #12
+    2190:	428b      	cmp	r3, r1
+    2192:	d319      	bcc.n	21c8 <__udivsi3+0x6c>
+    2194:	e000      	b.n	2198 <__udivsi3+0x3c>
+    2196:	0a09      	lsrs	r1, r1, #8
+    2198:	0bc3      	lsrs	r3, r0, #15
+    219a:	428b      	cmp	r3, r1
+    219c:	d301      	bcc.n	21a2 <__udivsi3+0x46>
+    219e:	03cb      	lsls	r3, r1, #15
+    21a0:	1ac0      	subs	r0, r0, r3
+    21a2:	4152      	adcs	r2, r2
+    21a4:	0b83      	lsrs	r3, r0, #14
+    21a6:	428b      	cmp	r3, r1
+    21a8:	d301      	bcc.n	21ae <__udivsi3+0x52>
+    21aa:	038b      	lsls	r3, r1, #14
+    21ac:	1ac0      	subs	r0, r0, r3
+    21ae:	4152      	adcs	r2, r2
+    21b0:	0b43      	lsrs	r3, r0, #13
+    21b2:	428b      	cmp	r3, r1
+    21b4:	d301      	bcc.n	21ba <__udivsi3+0x5e>
+    21b6:	034b      	lsls	r3, r1, #13
+    21b8:	1ac0      	subs	r0, r0, r3
+    21ba:	4152      	adcs	r2, r2
+    21bc:	0b03      	lsrs	r3, r0, #12
+    21be:	428b      	cmp	r3, r1
+    21c0:	d301      	bcc.n	21c6 <__udivsi3+0x6a>
+    21c2:	030b      	lsls	r3, r1, #12
+    21c4:	1ac0      	subs	r0, r0, r3
+    21c6:	4152      	adcs	r2, r2
+    21c8:	0ac3      	lsrs	r3, r0, #11
+    21ca:	428b      	cmp	r3, r1
+    21cc:	d301      	bcc.n	21d2 <__udivsi3+0x76>
+    21ce:	02cb      	lsls	r3, r1, #11
+    21d0:	1ac0      	subs	r0, r0, r3
+    21d2:	4152      	adcs	r2, r2
+    21d4:	0a83      	lsrs	r3, r0, #10
+    21d6:	428b      	cmp	r3, r1
+    21d8:	d301      	bcc.n	21de <__udivsi3+0x82>
+    21da:	028b      	lsls	r3, r1, #10
+    21dc:	1ac0      	subs	r0, r0, r3
+    21de:	4152      	adcs	r2, r2
+    21e0:	0a43      	lsrs	r3, r0, #9
+    21e2:	428b      	cmp	r3, r1
+    21e4:	d301      	bcc.n	21ea <__udivsi3+0x8e>
+    21e6:	024b      	lsls	r3, r1, #9
+    21e8:	1ac0      	subs	r0, r0, r3
+    21ea:	4152      	adcs	r2, r2
+    21ec:	0a03      	lsrs	r3, r0, #8
+    21ee:	428b      	cmp	r3, r1
+    21f0:	d301      	bcc.n	21f6 <__udivsi3+0x9a>
+    21f2:	020b      	lsls	r3, r1, #8
+    21f4:	1ac0      	subs	r0, r0, r3
+    21f6:	4152      	adcs	r2, r2
+    21f8:	d2cd      	bcs.n	2196 <__udivsi3+0x3a>
+    21fa:	09c3      	lsrs	r3, r0, #7
+    21fc:	428b      	cmp	r3, r1
+    21fe:	d301      	bcc.n	2204 <__udivsi3+0xa8>
+    2200:	01cb      	lsls	r3, r1, #7
+    2202:	1ac0      	subs	r0, r0, r3
+    2204:	4152      	adcs	r2, r2
+    2206:	0983      	lsrs	r3, r0, #6
+    2208:	428b      	cmp	r3, r1
+    220a:	d301      	bcc.n	2210 <__udivsi3+0xb4>
+    220c:	018b      	lsls	r3, r1, #6
+    220e:	1ac0      	subs	r0, r0, r3
+    2210:	4152      	adcs	r2, r2
+    2212:	0943      	lsrs	r3, r0, #5
+    2214:	428b      	cmp	r3, r1
+    2216:	d301      	bcc.n	221c <__udivsi3+0xc0>
+    2218:	014b      	lsls	r3, r1, #5
+    221a:	1ac0      	subs	r0, r0, r3
+    221c:	4152      	adcs	r2, r2
+    221e:	0903      	lsrs	r3, r0, #4
+    2220:	428b      	cmp	r3, r1
+    2222:	d301      	bcc.n	2228 <__udivsi3+0xcc>
+    2224:	010b      	lsls	r3, r1, #4
+    2226:	1ac0      	subs	r0, r0, r3
+    2228:	4152      	adcs	r2, r2
+    222a:	08c3      	lsrs	r3, r0, #3
+    222c:	428b      	cmp	r3, r1
+    222e:	d301      	bcc.n	2234 <__udivsi3+0xd8>
+    2230:	00cb      	lsls	r3, r1, #3
+    2232:	1ac0      	subs	r0, r0, r3
+    2234:	4152      	adcs	r2, r2
+    2236:	0883      	lsrs	r3, r0, #2
+    2238:	428b      	cmp	r3, r1
+    223a:	d301      	bcc.n	2240 <__udivsi3+0xe4>
+    223c:	008b      	lsls	r3, r1, #2
+    223e:	1ac0      	subs	r0, r0, r3
+    2240:	4152      	adcs	r2, r2
+    2242:	0843      	lsrs	r3, r0, #1
+    2244:	428b      	cmp	r3, r1
+    2246:	d301      	bcc.n	224c <__udivsi3+0xf0>
+    2248:	004b      	lsls	r3, r1, #1
+    224a:	1ac0      	subs	r0, r0, r3
+    224c:	4152      	adcs	r2, r2
+    224e:	1a41      	subs	r1, r0, r1
+    2250:	d200      	bcs.n	2254 <__udivsi3+0xf8>
+    2252:	4601      	mov	r1, r0
+    2254:	4152      	adcs	r2, r2
+    2256:	4610      	mov	r0, r2
+    2258:	4770      	bx	lr
+    225a:	e7ff      	b.n	225c <__udivsi3+0x100>
+    225c:	b501      	push	{r0, lr}
+    225e:	2000      	movs	r0, #0
+    2260:	f000 f806 	bl	2270 <__aeabi_idiv0>
+    2264:	bd02      	pop	{r1, pc}
+    2266:	46c0      	nop			; (mov r8, r8)
+
+00002268 <__aeabi_uidivmod>:
+    2268:	2900      	cmp	r1, #0
+    226a:	d0f7      	beq.n	225c <__udivsi3+0x100>
+    226c:	e776      	b.n	215c <__udivsi3>
+    226e:	4770      	bx	lr
+
+00002270 <__aeabi_idiv0>:
+    2270:	4770      	bx	lr
+    2272:	46c0      	nop			; (mov r8, r8)
+
+00002274 <__aeabi_llsl>:
+    2274:	4091      	lsls	r1, r2
+    2276:	1c03      	adds	r3, r0, #0
+    2278:	4090      	lsls	r0, r2
+    227a:	469c      	mov	ip, r3
+    227c:	3a20      	subs	r2, #32
+    227e:	4093      	lsls	r3, r2
+    2280:	4319      	orrs	r1, r3
+    2282:	4252      	negs	r2, r2
+    2284:	4663      	mov	r3, ip
+    2286:	40d3      	lsrs	r3, r2
+    2288:	4319      	orrs	r1, r3
+    228a:	4770      	bx	lr
+
+0000228c <__aeabi_cdrcmple>:
+    228c:	4684      	mov	ip, r0
+    228e:	1c10      	adds	r0, r2, #0
+    2290:	4662      	mov	r2, ip
+    2292:	468c      	mov	ip, r1
+    2294:	1c19      	adds	r1, r3, #0
+    2296:	4663      	mov	r3, ip
+    2298:	e000      	b.n	229c <__aeabi_cdcmpeq>
+    229a:	46c0      	nop			; (mov r8, r8)
+
+0000229c <__aeabi_cdcmpeq>:
+    229c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
+    229e:	f001 facf 	bl	3840 <__ledf2>
+    22a2:	2800      	cmp	r0, #0
+    22a4:	d401      	bmi.n	22aa <__aeabi_cdcmpeq+0xe>
+    22a6:	2100      	movs	r1, #0
+    22a8:	42c8      	cmn	r0, r1
+    22aa:	bd1f      	pop	{r0, r1, r2, r3, r4, pc}
+
+000022ac <__aeabi_dcmpeq>:
+    22ac:	b510      	push	{r4, lr}
+    22ae:	f001 fa29 	bl	3704 <__eqdf2>
+    22b2:	4240      	negs	r0, r0
+    22b4:	3001      	adds	r0, #1
+    22b6:	bd10      	pop	{r4, pc}
+
+000022b8 <__aeabi_dcmplt>:
+    22b8:	b510      	push	{r4, lr}
+    22ba:	f001 fac1 	bl	3840 <__ledf2>
+    22be:	2800      	cmp	r0, #0
+    22c0:	db01      	blt.n	22c6 <__aeabi_dcmplt+0xe>
+    22c2:	2000      	movs	r0, #0
+    22c4:	bd10      	pop	{r4, pc}
+    22c6:	2001      	movs	r0, #1
+    22c8:	bd10      	pop	{r4, pc}
+    22ca:	46c0      	nop			; (mov r8, r8)
+
+000022cc <__aeabi_dcmple>:
+    22cc:	b510      	push	{r4, lr}
+    22ce:	f001 fab7 	bl	3840 <__ledf2>
+    22d2:	2800      	cmp	r0, #0
+    22d4:	dd01      	ble.n	22da <__aeabi_dcmple+0xe>
+    22d6:	2000      	movs	r0, #0
+    22d8:	bd10      	pop	{r4, pc}
+    22da:	2001      	movs	r0, #1
+    22dc:	bd10      	pop	{r4, pc}
+    22de:	46c0      	nop			; (mov r8, r8)
+
+000022e0 <__aeabi_dcmpgt>:
+    22e0:	b510      	push	{r4, lr}
+    22e2:	f001 fa49 	bl	3778 <__gedf2>
+    22e6:	2800      	cmp	r0, #0
+    22e8:	dc01      	bgt.n	22ee <__aeabi_dcmpgt+0xe>
+    22ea:	2000      	movs	r0, #0
+    22ec:	bd10      	pop	{r4, pc}
+    22ee:	2001      	movs	r0, #1
+    22f0:	bd10      	pop	{r4, pc}
+    22f2:	46c0      	nop			; (mov r8, r8)
+
+000022f4 <__aeabi_dcmpge>:
+    22f4:	b510      	push	{r4, lr}
+    22f6:	f001 fa3f 	bl	3778 <__gedf2>
+    22fa:	2800      	cmp	r0, #0
+    22fc:	da01      	bge.n	2302 <__aeabi_dcmpge+0xe>
+    22fe:	2000      	movs	r0, #0
+    2300:	bd10      	pop	{r4, pc}
+    2302:	2001      	movs	r0, #1
+    2304:	bd10      	pop	{r4, pc}
+    2306:	46c0      	nop			; (mov r8, r8)
+
+00002308 <__aeabi_lmul>:
+    2308:	b5f0      	push	{r4, r5, r6, r7, lr}
+    230a:	46ce      	mov	lr, r9
+    230c:	4647      	mov	r7, r8
+    230e:	0415      	lsls	r5, r2, #16
+    2310:	0c2d      	lsrs	r5, r5, #16
+    2312:	002e      	movs	r6, r5
+    2314:	b580      	push	{r7, lr}
+    2316:	0407      	lsls	r7, r0, #16
+    2318:	0c14      	lsrs	r4, r2, #16
+    231a:	0c3f      	lsrs	r7, r7, #16
+    231c:	4699      	mov	r9, r3
+    231e:	0c03      	lsrs	r3, r0, #16
+    2320:	437e      	muls	r6, r7
+    2322:	435d      	muls	r5, r3
+    2324:	4367      	muls	r7, r4
+    2326:	4363      	muls	r3, r4
+    2328:	197f      	adds	r7, r7, r5
+    232a:	0c34      	lsrs	r4, r6, #16
+    232c:	19e4      	adds	r4, r4, r7
+    232e:	469c      	mov	ip, r3
+    2330:	42a5      	cmp	r5, r4
+    2332:	d903      	bls.n	233c <__aeabi_lmul+0x34>
+    2334:	2380      	movs	r3, #128	; 0x80
+    2336:	025b      	lsls	r3, r3, #9
+    2338:	4698      	mov	r8, r3
+    233a:	44c4      	add	ip, r8
+    233c:	464b      	mov	r3, r9
+    233e:	4351      	muls	r1, r2
+    2340:	4343      	muls	r3, r0
+    2342:	0436      	lsls	r6, r6, #16
+    2344:	0c36      	lsrs	r6, r6, #16
+    2346:	0c25      	lsrs	r5, r4, #16
+    2348:	0424      	lsls	r4, r4, #16
+    234a:	4465      	add	r5, ip
+    234c:	19a4      	adds	r4, r4, r6
+    234e:	1859      	adds	r1, r3, r1
+    2350:	1949      	adds	r1, r1, r5
+    2352:	0020      	movs	r0, r4
+    2354:	bc0c      	pop	{r2, r3}
+    2356:	4690      	mov	r8, r2
+    2358:	4699      	mov	r9, r3
+    235a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+
+0000235c <__aeabi_d2uiz>:
+    235c:	b570      	push	{r4, r5, r6, lr}
+    235e:	2200      	movs	r2, #0
+    2360:	4b0c      	ldr	r3, [pc, #48]	; (2394 <__aeabi_d2uiz+0x38>)
+    2362:	0004      	movs	r4, r0
+    2364:	000d      	movs	r5, r1
+    2366:	f7ff ffc5 	bl	22f4 <__aeabi_dcmpge>
+    236a:	2800      	cmp	r0, #0
+    236c:	d104      	bne.n	2378 <__aeabi_d2uiz+0x1c>
+    236e:	0020      	movs	r0, r4
+    2370:	0029      	movs	r1, r5
+    2372:	f002 f87d 	bl	4470 <__aeabi_d2iz>
+    2376:	bd70      	pop	{r4, r5, r6, pc}
+    2378:	4b06      	ldr	r3, [pc, #24]	; (2394 <__aeabi_d2uiz+0x38>)
+    237a:	2200      	movs	r2, #0
+    237c:	0020      	movs	r0, r4
+    237e:	0029      	movs	r1, r5
+    2380:	f001 fd40 	bl	3e04 <__aeabi_dsub>
+    2384:	f002 f874 	bl	4470 <__aeabi_d2iz>
+    2388:	2380      	movs	r3, #128	; 0x80
+    238a:	061b      	lsls	r3, r3, #24
+    238c:	469c      	mov	ip, r3
+    238e:	4460      	add	r0, ip
+    2390:	e7f1      	b.n	2376 <__aeabi_d2uiz+0x1a>
+    2392:	46c0      	nop			; (mov r8, r8)
+    2394:	41e00000 	.word	0x41e00000
+
+00002398 <__aeabi_fmul>:
+    2398:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    239a:	4657      	mov	r7, sl
+    239c:	464e      	mov	r6, r9
+    239e:	4645      	mov	r5, r8
+    23a0:	46de      	mov	lr, fp
+    23a2:	b5e0      	push	{r5, r6, r7, lr}
+    23a4:	0247      	lsls	r7, r0, #9
+    23a6:	0046      	lsls	r6, r0, #1
+    23a8:	4688      	mov	r8, r1
+    23aa:	0a7f      	lsrs	r7, r7, #9
+    23ac:	0e36      	lsrs	r6, r6, #24
+    23ae:	0fc4      	lsrs	r4, r0, #31
+    23b0:	2e00      	cmp	r6, #0
+    23b2:	d047      	beq.n	2444 <__aeabi_fmul+0xac>
+    23b4:	2eff      	cmp	r6, #255	; 0xff
+    23b6:	d024      	beq.n	2402 <__aeabi_fmul+0x6a>
+    23b8:	00fb      	lsls	r3, r7, #3
+    23ba:	2780      	movs	r7, #128	; 0x80
+    23bc:	04ff      	lsls	r7, r7, #19
+    23be:	431f      	orrs	r7, r3
+    23c0:	2300      	movs	r3, #0
+    23c2:	4699      	mov	r9, r3
+    23c4:	469a      	mov	sl, r3
+    23c6:	3e7f      	subs	r6, #127	; 0x7f
+    23c8:	4643      	mov	r3, r8
+    23ca:	025d      	lsls	r5, r3, #9
+    23cc:	0058      	lsls	r0, r3, #1
+    23ce:	0fdb      	lsrs	r3, r3, #31
+    23d0:	0a6d      	lsrs	r5, r5, #9
+    23d2:	0e00      	lsrs	r0, r0, #24
+    23d4:	4698      	mov	r8, r3
+    23d6:	d043      	beq.n	2460 <__aeabi_fmul+0xc8>
+    23d8:	28ff      	cmp	r0, #255	; 0xff
+    23da:	d03b      	beq.n	2454 <__aeabi_fmul+0xbc>
+    23dc:	00eb      	lsls	r3, r5, #3
+    23de:	2580      	movs	r5, #128	; 0x80
+    23e0:	2200      	movs	r2, #0
+    23e2:	04ed      	lsls	r5, r5, #19
+    23e4:	431d      	orrs	r5, r3
+    23e6:	387f      	subs	r0, #127	; 0x7f
+    23e8:	1836      	adds	r6, r6, r0
+    23ea:	1c73      	adds	r3, r6, #1
+    23ec:	4641      	mov	r1, r8
+    23ee:	469b      	mov	fp, r3
+    23f0:	464b      	mov	r3, r9
+    23f2:	4061      	eors	r1, r4
+    23f4:	4313      	orrs	r3, r2
+    23f6:	2b0f      	cmp	r3, #15
+    23f8:	d864      	bhi.n	24c4 <__aeabi_fmul+0x12c>
+    23fa:	4875      	ldr	r0, [pc, #468]	; (25d0 <__aeabi_fmul+0x238>)
+    23fc:	009b      	lsls	r3, r3, #2
+    23fe:	58c3      	ldr	r3, [r0, r3]
+    2400:	469f      	mov	pc, r3
+    2402:	2f00      	cmp	r7, #0
+    2404:	d142      	bne.n	248c <__aeabi_fmul+0xf4>
+    2406:	2308      	movs	r3, #8
+    2408:	4699      	mov	r9, r3
+    240a:	3b06      	subs	r3, #6
+    240c:	26ff      	movs	r6, #255	; 0xff
+    240e:	469a      	mov	sl, r3
+    2410:	e7da      	b.n	23c8 <__aeabi_fmul+0x30>
+    2412:	4641      	mov	r1, r8
+    2414:	2a02      	cmp	r2, #2
+    2416:	d028      	beq.n	246a <__aeabi_fmul+0xd2>
+    2418:	2a03      	cmp	r2, #3
+    241a:	d100      	bne.n	241e <__aeabi_fmul+0x86>
+    241c:	e0ce      	b.n	25bc <__aeabi_fmul+0x224>
+    241e:	2a01      	cmp	r2, #1
+    2420:	d000      	beq.n	2424 <__aeabi_fmul+0x8c>
+    2422:	e0ac      	b.n	257e <__aeabi_fmul+0x1e6>
+    2424:	4011      	ands	r1, r2
+    2426:	2000      	movs	r0, #0
+    2428:	2200      	movs	r2, #0
+    242a:	b2cc      	uxtb	r4, r1
+    242c:	0240      	lsls	r0, r0, #9
+    242e:	05d2      	lsls	r2, r2, #23
+    2430:	0a40      	lsrs	r0, r0, #9
+    2432:	07e4      	lsls	r4, r4, #31
+    2434:	4310      	orrs	r0, r2
+    2436:	4320      	orrs	r0, r4
+    2438:	bc3c      	pop	{r2, r3, r4, r5}
+    243a:	4690      	mov	r8, r2
+    243c:	4699      	mov	r9, r3
+    243e:	46a2      	mov	sl, r4
+    2440:	46ab      	mov	fp, r5
+    2442:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    2444:	2f00      	cmp	r7, #0
+    2446:	d115      	bne.n	2474 <__aeabi_fmul+0xdc>
+    2448:	2304      	movs	r3, #4
+    244a:	4699      	mov	r9, r3
+    244c:	3b03      	subs	r3, #3
+    244e:	2600      	movs	r6, #0
+    2450:	469a      	mov	sl, r3
+    2452:	e7b9      	b.n	23c8 <__aeabi_fmul+0x30>
+    2454:	20ff      	movs	r0, #255	; 0xff
+    2456:	2202      	movs	r2, #2
+    2458:	2d00      	cmp	r5, #0
+    245a:	d0c5      	beq.n	23e8 <__aeabi_fmul+0x50>
+    245c:	2203      	movs	r2, #3
+    245e:	e7c3      	b.n	23e8 <__aeabi_fmul+0x50>
+    2460:	2d00      	cmp	r5, #0
+    2462:	d119      	bne.n	2498 <__aeabi_fmul+0x100>
+    2464:	2000      	movs	r0, #0
+    2466:	2201      	movs	r2, #1
+    2468:	e7be      	b.n	23e8 <__aeabi_fmul+0x50>
+    246a:	2401      	movs	r4, #1
+    246c:	22ff      	movs	r2, #255	; 0xff
+    246e:	400c      	ands	r4, r1
+    2470:	2000      	movs	r0, #0
+    2472:	e7db      	b.n	242c <__aeabi_fmul+0x94>
+    2474:	0038      	movs	r0, r7
+    2476:	f002 f985 	bl	4784 <__clzsi2>
+    247a:	2676      	movs	r6, #118	; 0x76
+    247c:	1f43      	subs	r3, r0, #5
+    247e:	409f      	lsls	r7, r3
+    2480:	2300      	movs	r3, #0
+    2482:	4276      	negs	r6, r6
+    2484:	1a36      	subs	r6, r6, r0
+    2486:	4699      	mov	r9, r3
+    2488:	469a      	mov	sl, r3
+    248a:	e79d      	b.n	23c8 <__aeabi_fmul+0x30>
+    248c:	230c      	movs	r3, #12
+    248e:	4699      	mov	r9, r3
+    2490:	3b09      	subs	r3, #9
+    2492:	26ff      	movs	r6, #255	; 0xff
+    2494:	469a      	mov	sl, r3
+    2496:	e797      	b.n	23c8 <__aeabi_fmul+0x30>
+    2498:	0028      	movs	r0, r5
+    249a:	f002 f973 	bl	4784 <__clzsi2>
+    249e:	1f43      	subs	r3, r0, #5
+    24a0:	409d      	lsls	r5, r3
+    24a2:	2376      	movs	r3, #118	; 0x76
+    24a4:	425b      	negs	r3, r3
+    24a6:	1a18      	subs	r0, r3, r0
+    24a8:	2200      	movs	r2, #0
+    24aa:	e79d      	b.n	23e8 <__aeabi_fmul+0x50>
+    24ac:	2080      	movs	r0, #128	; 0x80
+    24ae:	2400      	movs	r4, #0
+    24b0:	03c0      	lsls	r0, r0, #15
+    24b2:	22ff      	movs	r2, #255	; 0xff
+    24b4:	e7ba      	b.n	242c <__aeabi_fmul+0x94>
+    24b6:	003d      	movs	r5, r7
+    24b8:	4652      	mov	r2, sl
+    24ba:	e7ab      	b.n	2414 <__aeabi_fmul+0x7c>
+    24bc:	003d      	movs	r5, r7
+    24be:	0021      	movs	r1, r4
+    24c0:	4652      	mov	r2, sl
+    24c2:	e7a7      	b.n	2414 <__aeabi_fmul+0x7c>
+    24c4:	0c3b      	lsrs	r3, r7, #16
+    24c6:	469c      	mov	ip, r3
+    24c8:	042a      	lsls	r2, r5, #16
+    24ca:	0c12      	lsrs	r2, r2, #16
+    24cc:	0c2b      	lsrs	r3, r5, #16
+    24ce:	0014      	movs	r4, r2
+    24d0:	4660      	mov	r0, ip
+    24d2:	4665      	mov	r5, ip
+    24d4:	043f      	lsls	r7, r7, #16
+    24d6:	0c3f      	lsrs	r7, r7, #16
+    24d8:	437c      	muls	r4, r7
+    24da:	4342      	muls	r2, r0
+    24dc:	435d      	muls	r5, r3
+    24de:	437b      	muls	r3, r7
+    24e0:	0c27      	lsrs	r7, r4, #16
+    24e2:	189b      	adds	r3, r3, r2
+    24e4:	18ff      	adds	r7, r7, r3
+    24e6:	42ba      	cmp	r2, r7
+    24e8:	d903      	bls.n	24f2 <__aeabi_fmul+0x15a>
+    24ea:	2380      	movs	r3, #128	; 0x80
+    24ec:	025b      	lsls	r3, r3, #9
+    24ee:	469c      	mov	ip, r3
+    24f0:	4465      	add	r5, ip
+    24f2:	0424      	lsls	r4, r4, #16
+    24f4:	043a      	lsls	r2, r7, #16
+    24f6:	0c24      	lsrs	r4, r4, #16
+    24f8:	1912      	adds	r2, r2, r4
+    24fa:	0193      	lsls	r3, r2, #6
+    24fc:	1e5c      	subs	r4, r3, #1
+    24fe:	41a3      	sbcs	r3, r4
+    2500:	0c3f      	lsrs	r7, r7, #16
+    2502:	0e92      	lsrs	r2, r2, #26
+    2504:	197d      	adds	r5, r7, r5
+    2506:	431a      	orrs	r2, r3
+    2508:	01ad      	lsls	r5, r5, #6
+    250a:	4315      	orrs	r5, r2
+    250c:	012b      	lsls	r3, r5, #4
+    250e:	d504      	bpl.n	251a <__aeabi_fmul+0x182>
+    2510:	2301      	movs	r3, #1
+    2512:	465e      	mov	r6, fp
+    2514:	086a      	lsrs	r2, r5, #1
+    2516:	401d      	ands	r5, r3
+    2518:	4315      	orrs	r5, r2
+    251a:	0032      	movs	r2, r6
+    251c:	327f      	adds	r2, #127	; 0x7f
+    251e:	2a00      	cmp	r2, #0
+    2520:	dd25      	ble.n	256e <__aeabi_fmul+0x1d6>
+    2522:	076b      	lsls	r3, r5, #29
+    2524:	d004      	beq.n	2530 <__aeabi_fmul+0x198>
+    2526:	230f      	movs	r3, #15
+    2528:	402b      	ands	r3, r5
+    252a:	2b04      	cmp	r3, #4
+    252c:	d000      	beq.n	2530 <__aeabi_fmul+0x198>
+    252e:	3504      	adds	r5, #4
+    2530:	012b      	lsls	r3, r5, #4
+    2532:	d503      	bpl.n	253c <__aeabi_fmul+0x1a4>
+    2534:	0032      	movs	r2, r6
+    2536:	4b27      	ldr	r3, [pc, #156]	; (25d4 <__aeabi_fmul+0x23c>)
+    2538:	3280      	adds	r2, #128	; 0x80
+    253a:	401d      	ands	r5, r3
+    253c:	2afe      	cmp	r2, #254	; 0xfe
+    253e:	dc94      	bgt.n	246a <__aeabi_fmul+0xd2>
+    2540:	2401      	movs	r4, #1
+    2542:	01a8      	lsls	r0, r5, #6
+    2544:	0a40      	lsrs	r0, r0, #9
+    2546:	b2d2      	uxtb	r2, r2
+    2548:	400c      	ands	r4, r1
+    254a:	e76f      	b.n	242c <__aeabi_fmul+0x94>
+    254c:	2080      	movs	r0, #128	; 0x80
+    254e:	03c0      	lsls	r0, r0, #15
+    2550:	4207      	tst	r7, r0
+    2552:	d007      	beq.n	2564 <__aeabi_fmul+0x1cc>
+    2554:	4205      	tst	r5, r0
+    2556:	d105      	bne.n	2564 <__aeabi_fmul+0x1cc>
+    2558:	4328      	orrs	r0, r5
+    255a:	0240      	lsls	r0, r0, #9
+    255c:	0a40      	lsrs	r0, r0, #9
+    255e:	4644      	mov	r4, r8
+    2560:	22ff      	movs	r2, #255	; 0xff
+    2562:	e763      	b.n	242c <__aeabi_fmul+0x94>
+    2564:	4338      	orrs	r0, r7
+    2566:	0240      	lsls	r0, r0, #9
+    2568:	0a40      	lsrs	r0, r0, #9
+    256a:	22ff      	movs	r2, #255	; 0xff
+    256c:	e75e      	b.n	242c <__aeabi_fmul+0x94>
+    256e:	2401      	movs	r4, #1
+    2570:	1aa3      	subs	r3, r4, r2
+    2572:	2b1b      	cmp	r3, #27
+    2574:	dd05      	ble.n	2582 <__aeabi_fmul+0x1ea>
+    2576:	400c      	ands	r4, r1
+    2578:	2200      	movs	r2, #0
+    257a:	2000      	movs	r0, #0
+    257c:	e756      	b.n	242c <__aeabi_fmul+0x94>
+    257e:	465e      	mov	r6, fp
+    2580:	e7cb      	b.n	251a <__aeabi_fmul+0x182>
+    2582:	002a      	movs	r2, r5
+    2584:	2020      	movs	r0, #32
+    2586:	40da      	lsrs	r2, r3
+    2588:	1ac3      	subs	r3, r0, r3
+    258a:	409d      	lsls	r5, r3
+    258c:	002b      	movs	r3, r5
+    258e:	1e5d      	subs	r5, r3, #1
+    2590:	41ab      	sbcs	r3, r5
+    2592:	4313      	orrs	r3, r2
+    2594:	075a      	lsls	r2, r3, #29
+    2596:	d004      	beq.n	25a2 <__aeabi_fmul+0x20a>
+    2598:	220f      	movs	r2, #15
+    259a:	401a      	ands	r2, r3
+    259c:	2a04      	cmp	r2, #4
+    259e:	d000      	beq.n	25a2 <__aeabi_fmul+0x20a>
+    25a0:	3304      	adds	r3, #4
+    25a2:	015a      	lsls	r2, r3, #5
+    25a4:	d504      	bpl.n	25b0 <__aeabi_fmul+0x218>
+    25a6:	2401      	movs	r4, #1
+    25a8:	2201      	movs	r2, #1
+    25aa:	400c      	ands	r4, r1
+    25ac:	2000      	movs	r0, #0
+    25ae:	e73d      	b.n	242c <__aeabi_fmul+0x94>
+    25b0:	2401      	movs	r4, #1
+    25b2:	019b      	lsls	r3, r3, #6
+    25b4:	0a58      	lsrs	r0, r3, #9
+    25b6:	400c      	ands	r4, r1
+    25b8:	2200      	movs	r2, #0
+    25ba:	e737      	b.n	242c <__aeabi_fmul+0x94>
+    25bc:	2080      	movs	r0, #128	; 0x80
+    25be:	2401      	movs	r4, #1
+    25c0:	03c0      	lsls	r0, r0, #15
+    25c2:	4328      	orrs	r0, r5
+    25c4:	0240      	lsls	r0, r0, #9
+    25c6:	0a40      	lsrs	r0, r0, #9
+    25c8:	400c      	ands	r4, r1
+    25ca:	22ff      	movs	r2, #255	; 0xff
+    25cc:	e72e      	b.n	242c <__aeabi_fmul+0x94>
+    25ce:	46c0      	nop			; (mov r8, r8)
+    25d0:	000059dc 	.word	0x000059dc
+    25d4:	f7ffffff 	.word	0xf7ffffff
+
+000025d8 <__aeabi_fsub>:
+    25d8:	b5f0      	push	{r4, r5, r6, r7, lr}
+    25da:	464f      	mov	r7, r9
+    25dc:	46d6      	mov	lr, sl
+    25de:	4646      	mov	r6, r8
+    25e0:	0044      	lsls	r4, r0, #1
+    25e2:	b5c0      	push	{r6, r7, lr}
+    25e4:	0fc2      	lsrs	r2, r0, #31
+    25e6:	0247      	lsls	r7, r0, #9
+    25e8:	0248      	lsls	r0, r1, #9
+    25ea:	0a40      	lsrs	r0, r0, #9
+    25ec:	4684      	mov	ip, r0
+    25ee:	4666      	mov	r6, ip
+    25f0:	0a7b      	lsrs	r3, r7, #9
+    25f2:	0048      	lsls	r0, r1, #1
+    25f4:	0fc9      	lsrs	r1, r1, #31
+    25f6:	469a      	mov	sl, r3
+    25f8:	0e24      	lsrs	r4, r4, #24
+    25fa:	0015      	movs	r5, r2
+    25fc:	00db      	lsls	r3, r3, #3
+    25fe:	0e00      	lsrs	r0, r0, #24
+    2600:	4689      	mov	r9, r1
+    2602:	00f6      	lsls	r6, r6, #3
+    2604:	28ff      	cmp	r0, #255	; 0xff
+    2606:	d100      	bne.n	260a <__aeabi_fsub+0x32>
+    2608:	e08f      	b.n	272a <__aeabi_fsub+0x152>
+    260a:	2101      	movs	r1, #1
+    260c:	464f      	mov	r7, r9
+    260e:	404f      	eors	r7, r1
+    2610:	0039      	movs	r1, r7
+    2612:	4291      	cmp	r1, r2
+    2614:	d066      	beq.n	26e4 <__aeabi_fsub+0x10c>
+    2616:	1a22      	subs	r2, r4, r0
+    2618:	2a00      	cmp	r2, #0
+    261a:	dc00      	bgt.n	261e <__aeabi_fsub+0x46>
+    261c:	e09d      	b.n	275a <__aeabi_fsub+0x182>
+    261e:	2800      	cmp	r0, #0
+    2620:	d13d      	bne.n	269e <__aeabi_fsub+0xc6>
+    2622:	2e00      	cmp	r6, #0
+    2624:	d100      	bne.n	2628 <__aeabi_fsub+0x50>
+    2626:	e08b      	b.n	2740 <__aeabi_fsub+0x168>
+    2628:	1e51      	subs	r1, r2, #1
+    262a:	2900      	cmp	r1, #0
+    262c:	d000      	beq.n	2630 <__aeabi_fsub+0x58>
+    262e:	e0b5      	b.n	279c <__aeabi_fsub+0x1c4>
+    2630:	2401      	movs	r4, #1
+    2632:	1b9b      	subs	r3, r3, r6
+    2634:	015a      	lsls	r2, r3, #5
+    2636:	d544      	bpl.n	26c2 <__aeabi_fsub+0xea>
+    2638:	019b      	lsls	r3, r3, #6
+    263a:	099f      	lsrs	r7, r3, #6
+    263c:	0038      	movs	r0, r7
+    263e:	f002 f8a1 	bl	4784 <__clzsi2>
+    2642:	3805      	subs	r0, #5
+    2644:	4087      	lsls	r7, r0
+    2646:	4284      	cmp	r4, r0
+    2648:	dd00      	ble.n	264c <__aeabi_fsub+0x74>
+    264a:	e096      	b.n	277a <__aeabi_fsub+0x1a2>
+    264c:	1b04      	subs	r4, r0, r4
+    264e:	003a      	movs	r2, r7
+    2650:	2020      	movs	r0, #32
+    2652:	3401      	adds	r4, #1
+    2654:	40e2      	lsrs	r2, r4
+    2656:	1b04      	subs	r4, r0, r4
+    2658:	40a7      	lsls	r7, r4
+    265a:	003b      	movs	r3, r7
+    265c:	1e5f      	subs	r7, r3, #1
+    265e:	41bb      	sbcs	r3, r7
+    2660:	2400      	movs	r4, #0
+    2662:	4313      	orrs	r3, r2
+    2664:	075a      	lsls	r2, r3, #29
+    2666:	d004      	beq.n	2672 <__aeabi_fsub+0x9a>
+    2668:	220f      	movs	r2, #15
+    266a:	401a      	ands	r2, r3
+    266c:	2a04      	cmp	r2, #4
+    266e:	d000      	beq.n	2672 <__aeabi_fsub+0x9a>
+    2670:	3304      	adds	r3, #4
+    2672:	015a      	lsls	r2, r3, #5
+    2674:	d527      	bpl.n	26c6 <__aeabi_fsub+0xee>
+    2676:	3401      	adds	r4, #1
+    2678:	2cff      	cmp	r4, #255	; 0xff
+    267a:	d100      	bne.n	267e <__aeabi_fsub+0xa6>
+    267c:	e079      	b.n	2772 <__aeabi_fsub+0x19a>
+    267e:	2201      	movs	r2, #1
+    2680:	019b      	lsls	r3, r3, #6
+    2682:	0a5b      	lsrs	r3, r3, #9
+    2684:	b2e4      	uxtb	r4, r4
+    2686:	402a      	ands	r2, r5
+    2688:	025b      	lsls	r3, r3, #9
+    268a:	05e4      	lsls	r4, r4, #23
+    268c:	0a58      	lsrs	r0, r3, #9
+    268e:	07d2      	lsls	r2, r2, #31
+    2690:	4320      	orrs	r0, r4
+    2692:	4310      	orrs	r0, r2
+    2694:	bc1c      	pop	{r2, r3, r4}
+    2696:	4690      	mov	r8, r2
+    2698:	4699      	mov	r9, r3
+    269a:	46a2      	mov	sl, r4
+    269c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    269e:	2cff      	cmp	r4, #255	; 0xff
+    26a0:	d0e0      	beq.n	2664 <__aeabi_fsub+0x8c>
+    26a2:	2180      	movs	r1, #128	; 0x80
+    26a4:	04c9      	lsls	r1, r1, #19
+    26a6:	430e      	orrs	r6, r1
+    26a8:	2a1b      	cmp	r2, #27
+    26aa:	dc7b      	bgt.n	27a4 <__aeabi_fsub+0x1cc>
+    26ac:	0031      	movs	r1, r6
+    26ae:	2020      	movs	r0, #32
+    26b0:	40d1      	lsrs	r1, r2
+    26b2:	1a82      	subs	r2, r0, r2
+    26b4:	4096      	lsls	r6, r2
+    26b6:	1e72      	subs	r2, r6, #1
+    26b8:	4196      	sbcs	r6, r2
+    26ba:	430e      	orrs	r6, r1
+    26bc:	1b9b      	subs	r3, r3, r6
+    26be:	015a      	lsls	r2, r3, #5
+    26c0:	d4ba      	bmi.n	2638 <__aeabi_fsub+0x60>
+    26c2:	075a      	lsls	r2, r3, #29
+    26c4:	d1d0      	bne.n	2668 <__aeabi_fsub+0x90>
+    26c6:	2201      	movs	r2, #1
+    26c8:	08df      	lsrs	r7, r3, #3
+    26ca:	402a      	ands	r2, r5
+    26cc:	2cff      	cmp	r4, #255	; 0xff
+    26ce:	d133      	bne.n	2738 <__aeabi_fsub+0x160>
+    26d0:	2f00      	cmp	r7, #0
+    26d2:	d100      	bne.n	26d6 <__aeabi_fsub+0xfe>
+    26d4:	e0a8      	b.n	2828 <__aeabi_fsub+0x250>
+    26d6:	2380      	movs	r3, #128	; 0x80
+    26d8:	03db      	lsls	r3, r3, #15
+    26da:	433b      	orrs	r3, r7
+    26dc:	025b      	lsls	r3, r3, #9
+    26de:	0a5b      	lsrs	r3, r3, #9
+    26e0:	24ff      	movs	r4, #255	; 0xff
+    26e2:	e7d1      	b.n	2688 <__aeabi_fsub+0xb0>
+    26e4:	1a21      	subs	r1, r4, r0
+    26e6:	2900      	cmp	r1, #0
+    26e8:	dd4c      	ble.n	2784 <__aeabi_fsub+0x1ac>
+    26ea:	2800      	cmp	r0, #0
+    26ec:	d02a      	beq.n	2744 <__aeabi_fsub+0x16c>
+    26ee:	2cff      	cmp	r4, #255	; 0xff
+    26f0:	d0b8      	beq.n	2664 <__aeabi_fsub+0x8c>
+    26f2:	2080      	movs	r0, #128	; 0x80
+    26f4:	04c0      	lsls	r0, r0, #19
+    26f6:	4306      	orrs	r6, r0
+    26f8:	291b      	cmp	r1, #27
+    26fa:	dd00      	ble.n	26fe <__aeabi_fsub+0x126>
+    26fc:	e0af      	b.n	285e <__aeabi_fsub+0x286>
+    26fe:	0030      	movs	r0, r6
+    2700:	2720      	movs	r7, #32
+    2702:	40c8      	lsrs	r0, r1
+    2704:	1a79      	subs	r1, r7, r1
+    2706:	408e      	lsls	r6, r1
+    2708:	1e71      	subs	r1, r6, #1
+    270a:	418e      	sbcs	r6, r1
+    270c:	4306      	orrs	r6, r0
+    270e:	199b      	adds	r3, r3, r6
+    2710:	0159      	lsls	r1, r3, #5
+    2712:	d5d6      	bpl.n	26c2 <__aeabi_fsub+0xea>
+    2714:	3401      	adds	r4, #1
+    2716:	2cff      	cmp	r4, #255	; 0xff
+    2718:	d100      	bne.n	271c <__aeabi_fsub+0x144>
+    271a:	e085      	b.n	2828 <__aeabi_fsub+0x250>
+    271c:	2201      	movs	r2, #1
+    271e:	497a      	ldr	r1, [pc, #488]	; (2908 <__aeabi_fsub+0x330>)
+    2720:	401a      	ands	r2, r3
+    2722:	085b      	lsrs	r3, r3, #1
+    2724:	400b      	ands	r3, r1
+    2726:	4313      	orrs	r3, r2
+    2728:	e79c      	b.n	2664 <__aeabi_fsub+0x8c>
+    272a:	2e00      	cmp	r6, #0
+    272c:	d000      	beq.n	2730 <__aeabi_fsub+0x158>
+    272e:	e770      	b.n	2612 <__aeabi_fsub+0x3a>
+    2730:	e76b      	b.n	260a <__aeabi_fsub+0x32>
+    2732:	1e3b      	subs	r3, r7, #0
+    2734:	d1c5      	bne.n	26c2 <__aeabi_fsub+0xea>
+    2736:	2200      	movs	r2, #0
+    2738:	027b      	lsls	r3, r7, #9
+    273a:	0a5b      	lsrs	r3, r3, #9
+    273c:	b2e4      	uxtb	r4, r4
+    273e:	e7a3      	b.n	2688 <__aeabi_fsub+0xb0>
+    2740:	0014      	movs	r4, r2
+    2742:	e78f      	b.n	2664 <__aeabi_fsub+0x8c>
+    2744:	2e00      	cmp	r6, #0
+    2746:	d04d      	beq.n	27e4 <__aeabi_fsub+0x20c>
+    2748:	1e48      	subs	r0, r1, #1
+    274a:	2800      	cmp	r0, #0
+    274c:	d157      	bne.n	27fe <__aeabi_fsub+0x226>
+    274e:	199b      	adds	r3, r3, r6
+    2750:	2401      	movs	r4, #1
+    2752:	015a      	lsls	r2, r3, #5
+    2754:	d5b5      	bpl.n	26c2 <__aeabi_fsub+0xea>
+    2756:	2402      	movs	r4, #2
+    2758:	e7e0      	b.n	271c <__aeabi_fsub+0x144>
+    275a:	2a00      	cmp	r2, #0
+    275c:	d125      	bne.n	27aa <__aeabi_fsub+0x1d2>
+    275e:	1c62      	adds	r2, r4, #1
+    2760:	b2d2      	uxtb	r2, r2
+    2762:	2a01      	cmp	r2, #1
+    2764:	dd72      	ble.n	284c <__aeabi_fsub+0x274>
+    2766:	1b9f      	subs	r7, r3, r6
+    2768:	017a      	lsls	r2, r7, #5
+    276a:	d535      	bpl.n	27d8 <__aeabi_fsub+0x200>
+    276c:	1af7      	subs	r7, r6, r3
+    276e:	000d      	movs	r5, r1
+    2770:	e764      	b.n	263c <__aeabi_fsub+0x64>
+    2772:	2201      	movs	r2, #1
+    2774:	2300      	movs	r3, #0
+    2776:	402a      	ands	r2, r5
+    2778:	e786      	b.n	2688 <__aeabi_fsub+0xb0>
+    277a:	003b      	movs	r3, r7
+    277c:	4a63      	ldr	r2, [pc, #396]	; (290c <__aeabi_fsub+0x334>)
+    277e:	1a24      	subs	r4, r4, r0
+    2780:	4013      	ands	r3, r2
+    2782:	e76f      	b.n	2664 <__aeabi_fsub+0x8c>
+    2784:	2900      	cmp	r1, #0
+    2786:	d16c      	bne.n	2862 <__aeabi_fsub+0x28a>
+    2788:	1c61      	adds	r1, r4, #1
+    278a:	b2c8      	uxtb	r0, r1
+    278c:	2801      	cmp	r0, #1
+    278e:	dd4e      	ble.n	282e <__aeabi_fsub+0x256>
+    2790:	29ff      	cmp	r1, #255	; 0xff
+    2792:	d049      	beq.n	2828 <__aeabi_fsub+0x250>
+    2794:	199b      	adds	r3, r3, r6
+    2796:	085b      	lsrs	r3, r3, #1
+    2798:	000c      	movs	r4, r1
+    279a:	e763      	b.n	2664 <__aeabi_fsub+0x8c>
+    279c:	2aff      	cmp	r2, #255	; 0xff
+    279e:	d041      	beq.n	2824 <__aeabi_fsub+0x24c>
+    27a0:	000a      	movs	r2, r1
+    27a2:	e781      	b.n	26a8 <__aeabi_fsub+0xd0>
+    27a4:	2601      	movs	r6, #1
+    27a6:	1b9b      	subs	r3, r3, r6
+    27a8:	e789      	b.n	26be <__aeabi_fsub+0xe6>
+    27aa:	2c00      	cmp	r4, #0
+    27ac:	d01c      	beq.n	27e8 <__aeabi_fsub+0x210>
+    27ae:	28ff      	cmp	r0, #255	; 0xff
+    27b0:	d021      	beq.n	27f6 <__aeabi_fsub+0x21e>
+    27b2:	2480      	movs	r4, #128	; 0x80
+    27b4:	04e4      	lsls	r4, r4, #19
+    27b6:	4252      	negs	r2, r2
+    27b8:	4323      	orrs	r3, r4
+    27ba:	2a1b      	cmp	r2, #27
+    27bc:	dd00      	ble.n	27c0 <__aeabi_fsub+0x1e8>
+    27be:	e096      	b.n	28ee <__aeabi_fsub+0x316>
+    27c0:	001c      	movs	r4, r3
+    27c2:	2520      	movs	r5, #32
+    27c4:	40d4      	lsrs	r4, r2
+    27c6:	1aaa      	subs	r2, r5, r2
+    27c8:	4093      	lsls	r3, r2
+    27ca:	1e5a      	subs	r2, r3, #1
+    27cc:	4193      	sbcs	r3, r2
+    27ce:	4323      	orrs	r3, r4
+    27d0:	1af3      	subs	r3, r6, r3
+    27d2:	0004      	movs	r4, r0
+    27d4:	000d      	movs	r5, r1
+    27d6:	e72d      	b.n	2634 <__aeabi_fsub+0x5c>
+    27d8:	2f00      	cmp	r7, #0
+    27da:	d000      	beq.n	27de <__aeabi_fsub+0x206>
+    27dc:	e72e      	b.n	263c <__aeabi_fsub+0x64>
+    27de:	2200      	movs	r2, #0
+    27e0:	2400      	movs	r4, #0
+    27e2:	e7a9      	b.n	2738 <__aeabi_fsub+0x160>
+    27e4:	000c      	movs	r4, r1
+    27e6:	e73d      	b.n	2664 <__aeabi_fsub+0x8c>
+    27e8:	2b00      	cmp	r3, #0
+    27ea:	d058      	beq.n	289e <__aeabi_fsub+0x2c6>
+    27ec:	43d2      	mvns	r2, r2
+    27ee:	2a00      	cmp	r2, #0
+    27f0:	d0ee      	beq.n	27d0 <__aeabi_fsub+0x1f8>
+    27f2:	28ff      	cmp	r0, #255	; 0xff
+    27f4:	d1e1      	bne.n	27ba <__aeabi_fsub+0x1e2>
+    27f6:	0033      	movs	r3, r6
+    27f8:	24ff      	movs	r4, #255	; 0xff
+    27fa:	000d      	movs	r5, r1
+    27fc:	e732      	b.n	2664 <__aeabi_fsub+0x8c>
+    27fe:	29ff      	cmp	r1, #255	; 0xff
+    2800:	d010      	beq.n	2824 <__aeabi_fsub+0x24c>
+    2802:	0001      	movs	r1, r0
+    2804:	e778      	b.n	26f8 <__aeabi_fsub+0x120>
+    2806:	2b00      	cmp	r3, #0
+    2808:	d06e      	beq.n	28e8 <__aeabi_fsub+0x310>
+    280a:	24ff      	movs	r4, #255	; 0xff
+    280c:	2e00      	cmp	r6, #0
+    280e:	d100      	bne.n	2812 <__aeabi_fsub+0x23a>
+    2810:	e728      	b.n	2664 <__aeabi_fsub+0x8c>
+    2812:	2280      	movs	r2, #128	; 0x80
+    2814:	4651      	mov	r1, sl
+    2816:	03d2      	lsls	r2, r2, #15
+    2818:	4211      	tst	r1, r2
+    281a:	d003      	beq.n	2824 <__aeabi_fsub+0x24c>
+    281c:	4661      	mov	r1, ip
+    281e:	4211      	tst	r1, r2
+    2820:	d100      	bne.n	2824 <__aeabi_fsub+0x24c>
+    2822:	0033      	movs	r3, r6
+    2824:	24ff      	movs	r4, #255	; 0xff
+    2826:	e71d      	b.n	2664 <__aeabi_fsub+0x8c>
+    2828:	24ff      	movs	r4, #255	; 0xff
+    282a:	2300      	movs	r3, #0
+    282c:	e72c      	b.n	2688 <__aeabi_fsub+0xb0>
+    282e:	2c00      	cmp	r4, #0
+    2830:	d1e9      	bne.n	2806 <__aeabi_fsub+0x22e>
+    2832:	2b00      	cmp	r3, #0
+    2834:	d063      	beq.n	28fe <__aeabi_fsub+0x326>
+    2836:	2e00      	cmp	r6, #0
+    2838:	d100      	bne.n	283c <__aeabi_fsub+0x264>
+    283a:	e713      	b.n	2664 <__aeabi_fsub+0x8c>
+    283c:	199b      	adds	r3, r3, r6
+    283e:	015a      	lsls	r2, r3, #5
+    2840:	d400      	bmi.n	2844 <__aeabi_fsub+0x26c>
+    2842:	e73e      	b.n	26c2 <__aeabi_fsub+0xea>
+    2844:	4a31      	ldr	r2, [pc, #196]	; (290c <__aeabi_fsub+0x334>)
+    2846:	000c      	movs	r4, r1
+    2848:	4013      	ands	r3, r2
+    284a:	e70b      	b.n	2664 <__aeabi_fsub+0x8c>
+    284c:	2c00      	cmp	r4, #0
+    284e:	d11e      	bne.n	288e <__aeabi_fsub+0x2b6>
+    2850:	2b00      	cmp	r3, #0
+    2852:	d12f      	bne.n	28b4 <__aeabi_fsub+0x2dc>
+    2854:	2e00      	cmp	r6, #0
+    2856:	d04f      	beq.n	28f8 <__aeabi_fsub+0x320>
+    2858:	0033      	movs	r3, r6
+    285a:	000d      	movs	r5, r1
+    285c:	e702      	b.n	2664 <__aeabi_fsub+0x8c>
+    285e:	2601      	movs	r6, #1
+    2860:	e755      	b.n	270e <__aeabi_fsub+0x136>
+    2862:	2c00      	cmp	r4, #0
+    2864:	d11f      	bne.n	28a6 <__aeabi_fsub+0x2ce>
+    2866:	2b00      	cmp	r3, #0
+    2868:	d043      	beq.n	28f2 <__aeabi_fsub+0x31a>
+    286a:	43c9      	mvns	r1, r1
+    286c:	2900      	cmp	r1, #0
+    286e:	d00b      	beq.n	2888 <__aeabi_fsub+0x2b0>
+    2870:	28ff      	cmp	r0, #255	; 0xff
+    2872:	d039      	beq.n	28e8 <__aeabi_fsub+0x310>
+    2874:	291b      	cmp	r1, #27
+    2876:	dc44      	bgt.n	2902 <__aeabi_fsub+0x32a>
+    2878:	001c      	movs	r4, r3
+    287a:	2720      	movs	r7, #32
+    287c:	40cc      	lsrs	r4, r1
+    287e:	1a79      	subs	r1, r7, r1
+    2880:	408b      	lsls	r3, r1
+    2882:	1e59      	subs	r1, r3, #1
+    2884:	418b      	sbcs	r3, r1
+    2886:	4323      	orrs	r3, r4
+    2888:	199b      	adds	r3, r3, r6
+    288a:	0004      	movs	r4, r0
+    288c:	e740      	b.n	2710 <__aeabi_fsub+0x138>
+    288e:	2b00      	cmp	r3, #0
+    2890:	d11a      	bne.n	28c8 <__aeabi_fsub+0x2f0>
+    2892:	2e00      	cmp	r6, #0
+    2894:	d124      	bne.n	28e0 <__aeabi_fsub+0x308>
+    2896:	2780      	movs	r7, #128	; 0x80
+    2898:	2200      	movs	r2, #0
+    289a:	03ff      	lsls	r7, r7, #15
+    289c:	e71b      	b.n	26d6 <__aeabi_fsub+0xfe>
+    289e:	0033      	movs	r3, r6
+    28a0:	0004      	movs	r4, r0
+    28a2:	000d      	movs	r5, r1
+    28a4:	e6de      	b.n	2664 <__aeabi_fsub+0x8c>
+    28a6:	28ff      	cmp	r0, #255	; 0xff
+    28a8:	d01e      	beq.n	28e8 <__aeabi_fsub+0x310>
+    28aa:	2480      	movs	r4, #128	; 0x80
+    28ac:	04e4      	lsls	r4, r4, #19
+    28ae:	4249      	negs	r1, r1
+    28b0:	4323      	orrs	r3, r4
+    28b2:	e7df      	b.n	2874 <__aeabi_fsub+0x29c>
+    28b4:	2e00      	cmp	r6, #0
+    28b6:	d100      	bne.n	28ba <__aeabi_fsub+0x2e2>
+    28b8:	e6d4      	b.n	2664 <__aeabi_fsub+0x8c>
+    28ba:	1b9f      	subs	r7, r3, r6
+    28bc:	017a      	lsls	r2, r7, #5
+    28be:	d400      	bmi.n	28c2 <__aeabi_fsub+0x2ea>
+    28c0:	e737      	b.n	2732 <__aeabi_fsub+0x15a>
+    28c2:	1af3      	subs	r3, r6, r3
+    28c4:	000d      	movs	r5, r1
+    28c6:	e6cd      	b.n	2664 <__aeabi_fsub+0x8c>
+    28c8:	24ff      	movs	r4, #255	; 0xff
+    28ca:	2e00      	cmp	r6, #0
+    28cc:	d100      	bne.n	28d0 <__aeabi_fsub+0x2f8>
+    28ce:	e6c9      	b.n	2664 <__aeabi_fsub+0x8c>
+    28d0:	2280      	movs	r2, #128	; 0x80
+    28d2:	4650      	mov	r0, sl
+    28d4:	03d2      	lsls	r2, r2, #15
+    28d6:	4210      	tst	r0, r2
+    28d8:	d0a4      	beq.n	2824 <__aeabi_fsub+0x24c>
+    28da:	4660      	mov	r0, ip
+    28dc:	4210      	tst	r0, r2
+    28de:	d1a1      	bne.n	2824 <__aeabi_fsub+0x24c>
+    28e0:	0033      	movs	r3, r6
+    28e2:	000d      	movs	r5, r1
+    28e4:	24ff      	movs	r4, #255	; 0xff
+    28e6:	e6bd      	b.n	2664 <__aeabi_fsub+0x8c>
+    28e8:	0033      	movs	r3, r6
+    28ea:	24ff      	movs	r4, #255	; 0xff
+    28ec:	e6ba      	b.n	2664 <__aeabi_fsub+0x8c>
+    28ee:	2301      	movs	r3, #1
+    28f0:	e76e      	b.n	27d0 <__aeabi_fsub+0x1f8>
+    28f2:	0033      	movs	r3, r6
+    28f4:	0004      	movs	r4, r0
+    28f6:	e6b5      	b.n	2664 <__aeabi_fsub+0x8c>
+    28f8:	2700      	movs	r7, #0
+    28fa:	2200      	movs	r2, #0
+    28fc:	e71c      	b.n	2738 <__aeabi_fsub+0x160>
+    28fe:	0033      	movs	r3, r6
+    2900:	e6b0      	b.n	2664 <__aeabi_fsub+0x8c>
+    2902:	2301      	movs	r3, #1
+    2904:	e7c0      	b.n	2888 <__aeabi_fsub+0x2b0>
+    2906:	46c0      	nop			; (mov r8, r8)
+    2908:	7dffffff 	.word	0x7dffffff
+    290c:	fbffffff 	.word	0xfbffffff
+
+00002910 <__aeabi_f2iz>:
+    2910:	0241      	lsls	r1, r0, #9
+    2912:	0043      	lsls	r3, r0, #1
+    2914:	0fc2      	lsrs	r2, r0, #31
+    2916:	0a49      	lsrs	r1, r1, #9
+    2918:	0e1b      	lsrs	r3, r3, #24
+    291a:	2000      	movs	r0, #0
+    291c:	2b7e      	cmp	r3, #126	; 0x7e
+    291e:	dd0d      	ble.n	293c <__aeabi_f2iz+0x2c>
+    2920:	2b9d      	cmp	r3, #157	; 0x9d
+    2922:	dc0c      	bgt.n	293e <__aeabi_f2iz+0x2e>
+    2924:	2080      	movs	r0, #128	; 0x80
+    2926:	0400      	lsls	r0, r0, #16
+    2928:	4301      	orrs	r1, r0
+    292a:	2b95      	cmp	r3, #149	; 0x95
+    292c:	dc0a      	bgt.n	2944 <__aeabi_f2iz+0x34>
+    292e:	2096      	movs	r0, #150	; 0x96
+    2930:	1ac3      	subs	r3, r0, r3
+    2932:	40d9      	lsrs	r1, r3
+    2934:	4248      	negs	r0, r1
+    2936:	2a00      	cmp	r2, #0
+    2938:	d100      	bne.n	293c <__aeabi_f2iz+0x2c>
+    293a:	0008      	movs	r0, r1
+    293c:	4770      	bx	lr
+    293e:	4b03      	ldr	r3, [pc, #12]	; (294c <__aeabi_f2iz+0x3c>)
+    2940:	18d0      	adds	r0, r2, r3
+    2942:	e7fb      	b.n	293c <__aeabi_f2iz+0x2c>
+    2944:	3b96      	subs	r3, #150	; 0x96
+    2946:	4099      	lsls	r1, r3
+    2948:	e7f4      	b.n	2934 <__aeabi_f2iz+0x24>
+    294a:	46c0      	nop			; (mov r8, r8)
+    294c:	7fffffff 	.word	0x7fffffff
+
+00002950 <__aeabi_i2f>:
+    2950:	b570      	push	{r4, r5, r6, lr}
+    2952:	2800      	cmp	r0, #0
+    2954:	d030      	beq.n	29b8 <__aeabi_i2f+0x68>
+    2956:	17c3      	asrs	r3, r0, #31
+    2958:	18c4      	adds	r4, r0, r3
+    295a:	405c      	eors	r4, r3
+    295c:	0fc5      	lsrs	r5, r0, #31
+    295e:	0020      	movs	r0, r4
+    2960:	f001 ff10 	bl	4784 <__clzsi2>
+    2964:	239e      	movs	r3, #158	; 0x9e
+    2966:	1a1b      	subs	r3, r3, r0
+    2968:	2b96      	cmp	r3, #150	; 0x96
+    296a:	dc0d      	bgt.n	2988 <__aeabi_i2f+0x38>
+    296c:	2296      	movs	r2, #150	; 0x96
+    296e:	1ad2      	subs	r2, r2, r3
+    2970:	4094      	lsls	r4, r2
+    2972:	002a      	movs	r2, r5
+    2974:	0264      	lsls	r4, r4, #9
+    2976:	0a64      	lsrs	r4, r4, #9
+    2978:	b2db      	uxtb	r3, r3
+    297a:	0264      	lsls	r4, r4, #9
+    297c:	05db      	lsls	r3, r3, #23
+    297e:	0a60      	lsrs	r0, r4, #9
+    2980:	07d2      	lsls	r2, r2, #31
+    2982:	4318      	orrs	r0, r3
+    2984:	4310      	orrs	r0, r2
+    2986:	bd70      	pop	{r4, r5, r6, pc}
+    2988:	2b99      	cmp	r3, #153	; 0x99
+    298a:	dc19      	bgt.n	29c0 <__aeabi_i2f+0x70>
+    298c:	2299      	movs	r2, #153	; 0x99
+    298e:	1ad2      	subs	r2, r2, r3
+    2990:	2a00      	cmp	r2, #0
+    2992:	dd29      	ble.n	29e8 <__aeabi_i2f+0x98>
+    2994:	4094      	lsls	r4, r2
+    2996:	0022      	movs	r2, r4
+    2998:	4c14      	ldr	r4, [pc, #80]	; (29ec <__aeabi_i2f+0x9c>)
+    299a:	4014      	ands	r4, r2
+    299c:	0751      	lsls	r1, r2, #29
+    299e:	d004      	beq.n	29aa <__aeabi_i2f+0x5a>
+    29a0:	210f      	movs	r1, #15
+    29a2:	400a      	ands	r2, r1
+    29a4:	2a04      	cmp	r2, #4
+    29a6:	d000      	beq.n	29aa <__aeabi_i2f+0x5a>
+    29a8:	3404      	adds	r4, #4
+    29aa:	0162      	lsls	r2, r4, #5
+    29ac:	d413      	bmi.n	29d6 <__aeabi_i2f+0x86>
+    29ae:	01a4      	lsls	r4, r4, #6
+    29b0:	0a64      	lsrs	r4, r4, #9
+    29b2:	b2db      	uxtb	r3, r3
+    29b4:	002a      	movs	r2, r5
+    29b6:	e7e0      	b.n	297a <__aeabi_i2f+0x2a>
+    29b8:	2200      	movs	r2, #0
+    29ba:	2300      	movs	r3, #0
+    29bc:	2400      	movs	r4, #0
+    29be:	e7dc      	b.n	297a <__aeabi_i2f+0x2a>
+    29c0:	2205      	movs	r2, #5
+    29c2:	0021      	movs	r1, r4
+    29c4:	1a12      	subs	r2, r2, r0
+    29c6:	40d1      	lsrs	r1, r2
+    29c8:	22b9      	movs	r2, #185	; 0xb9
+    29ca:	1ad2      	subs	r2, r2, r3
+    29cc:	4094      	lsls	r4, r2
+    29ce:	1e62      	subs	r2, r4, #1
+    29d0:	4194      	sbcs	r4, r2
+    29d2:	430c      	orrs	r4, r1
+    29d4:	e7da      	b.n	298c <__aeabi_i2f+0x3c>
+    29d6:	4b05      	ldr	r3, [pc, #20]	; (29ec <__aeabi_i2f+0x9c>)
+    29d8:	002a      	movs	r2, r5
+    29da:	401c      	ands	r4, r3
+    29dc:	239f      	movs	r3, #159	; 0x9f
+    29de:	01a4      	lsls	r4, r4, #6
+    29e0:	1a1b      	subs	r3, r3, r0
+    29e2:	0a64      	lsrs	r4, r4, #9
+    29e4:	b2db      	uxtb	r3, r3
+    29e6:	e7c8      	b.n	297a <__aeabi_i2f+0x2a>
+    29e8:	0022      	movs	r2, r4
+    29ea:	e7d5      	b.n	2998 <__aeabi_i2f+0x48>
+    29ec:	fbffffff 	.word	0xfbffffff
+
+000029f0 <__aeabi_ui2f>:
+    29f0:	b510      	push	{r4, lr}
+    29f2:	1e04      	subs	r4, r0, #0
+    29f4:	d027      	beq.n	2a46 <__aeabi_ui2f+0x56>
+    29f6:	f001 fec5 	bl	4784 <__clzsi2>
+    29fa:	239e      	movs	r3, #158	; 0x9e
+    29fc:	1a1b      	subs	r3, r3, r0
+    29fe:	2b96      	cmp	r3, #150	; 0x96
+    2a00:	dc0a      	bgt.n	2a18 <__aeabi_ui2f+0x28>
+    2a02:	2296      	movs	r2, #150	; 0x96
+    2a04:	1ad2      	subs	r2, r2, r3
+    2a06:	4094      	lsls	r4, r2
+    2a08:	0264      	lsls	r4, r4, #9
+    2a0a:	0a64      	lsrs	r4, r4, #9
+    2a0c:	b2db      	uxtb	r3, r3
+    2a0e:	0264      	lsls	r4, r4, #9
+    2a10:	05db      	lsls	r3, r3, #23
+    2a12:	0a60      	lsrs	r0, r4, #9
+    2a14:	4318      	orrs	r0, r3
+    2a16:	bd10      	pop	{r4, pc}
+    2a18:	2b99      	cmp	r3, #153	; 0x99
+    2a1a:	dc17      	bgt.n	2a4c <__aeabi_ui2f+0x5c>
+    2a1c:	2299      	movs	r2, #153	; 0x99
+    2a1e:	1ad2      	subs	r2, r2, r3
+    2a20:	2a00      	cmp	r2, #0
+    2a22:	dd27      	ble.n	2a74 <__aeabi_ui2f+0x84>
+    2a24:	4094      	lsls	r4, r2
+    2a26:	0022      	movs	r2, r4
+    2a28:	4c13      	ldr	r4, [pc, #76]	; (2a78 <__aeabi_ui2f+0x88>)
+    2a2a:	4014      	ands	r4, r2
+    2a2c:	0751      	lsls	r1, r2, #29
+    2a2e:	d004      	beq.n	2a3a <__aeabi_ui2f+0x4a>
+    2a30:	210f      	movs	r1, #15
+    2a32:	400a      	ands	r2, r1
+    2a34:	2a04      	cmp	r2, #4
+    2a36:	d000      	beq.n	2a3a <__aeabi_ui2f+0x4a>
+    2a38:	3404      	adds	r4, #4
+    2a3a:	0162      	lsls	r2, r4, #5
+    2a3c:	d412      	bmi.n	2a64 <__aeabi_ui2f+0x74>
+    2a3e:	01a4      	lsls	r4, r4, #6
+    2a40:	0a64      	lsrs	r4, r4, #9
+    2a42:	b2db      	uxtb	r3, r3
+    2a44:	e7e3      	b.n	2a0e <__aeabi_ui2f+0x1e>
+    2a46:	2300      	movs	r3, #0
+    2a48:	2400      	movs	r4, #0
+    2a4a:	e7e0      	b.n	2a0e <__aeabi_ui2f+0x1e>
+    2a4c:	22b9      	movs	r2, #185	; 0xb9
+    2a4e:	0021      	movs	r1, r4
+    2a50:	1ad2      	subs	r2, r2, r3
+    2a52:	4091      	lsls	r1, r2
+    2a54:	000a      	movs	r2, r1
+    2a56:	1e51      	subs	r1, r2, #1
+    2a58:	418a      	sbcs	r2, r1
+    2a5a:	2105      	movs	r1, #5
+    2a5c:	1a09      	subs	r1, r1, r0
+    2a5e:	40cc      	lsrs	r4, r1
+    2a60:	4314      	orrs	r4, r2
+    2a62:	e7db      	b.n	2a1c <__aeabi_ui2f+0x2c>
+    2a64:	4b04      	ldr	r3, [pc, #16]	; (2a78 <__aeabi_ui2f+0x88>)
+    2a66:	401c      	ands	r4, r3
+    2a68:	239f      	movs	r3, #159	; 0x9f
+    2a6a:	01a4      	lsls	r4, r4, #6
+    2a6c:	1a1b      	subs	r3, r3, r0
+    2a6e:	0a64      	lsrs	r4, r4, #9
+    2a70:	b2db      	uxtb	r3, r3
+    2a72:	e7cc      	b.n	2a0e <__aeabi_ui2f+0x1e>
+    2a74:	0022      	movs	r2, r4
+    2a76:	e7d7      	b.n	2a28 <__aeabi_ui2f+0x38>
+    2a78:	fbffffff 	.word	0xfbffffff
+
+00002a7c <__aeabi_dadd>:
+    2a7c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    2a7e:	4645      	mov	r5, r8
+    2a80:	46de      	mov	lr, fp
+    2a82:	4657      	mov	r7, sl
+    2a84:	464e      	mov	r6, r9
+    2a86:	030c      	lsls	r4, r1, #12
+    2a88:	b5e0      	push	{r5, r6, r7, lr}
+    2a8a:	004e      	lsls	r6, r1, #1
+    2a8c:	0fc9      	lsrs	r1, r1, #31
+    2a8e:	4688      	mov	r8, r1
+    2a90:	000d      	movs	r5, r1
+    2a92:	0a61      	lsrs	r1, r4, #9
+    2a94:	0f44      	lsrs	r4, r0, #29
+    2a96:	430c      	orrs	r4, r1
+    2a98:	00c7      	lsls	r7, r0, #3
+    2a9a:	0319      	lsls	r1, r3, #12
+    2a9c:	0058      	lsls	r0, r3, #1
+    2a9e:	0fdb      	lsrs	r3, r3, #31
+    2aa0:	469b      	mov	fp, r3
+    2aa2:	0a4b      	lsrs	r3, r1, #9
+    2aa4:	0f51      	lsrs	r1, r2, #29
+    2aa6:	430b      	orrs	r3, r1
+    2aa8:	0d76      	lsrs	r6, r6, #21
+    2aaa:	0d40      	lsrs	r0, r0, #21
+    2aac:	0019      	movs	r1, r3
+    2aae:	00d2      	lsls	r2, r2, #3
+    2ab0:	45d8      	cmp	r8, fp
+    2ab2:	d100      	bne.n	2ab6 <__aeabi_dadd+0x3a>
+    2ab4:	e0ae      	b.n	2c14 <__aeabi_dadd+0x198>
+    2ab6:	1a35      	subs	r5, r6, r0
+    2ab8:	2d00      	cmp	r5, #0
+    2aba:	dc00      	bgt.n	2abe <__aeabi_dadd+0x42>
+    2abc:	e0f6      	b.n	2cac <__aeabi_dadd+0x230>
+    2abe:	2800      	cmp	r0, #0
+    2ac0:	d10f      	bne.n	2ae2 <__aeabi_dadd+0x66>
+    2ac2:	4313      	orrs	r3, r2
+    2ac4:	d100      	bne.n	2ac8 <__aeabi_dadd+0x4c>
+    2ac6:	e0db      	b.n	2c80 <__aeabi_dadd+0x204>
+    2ac8:	1e6b      	subs	r3, r5, #1
+    2aca:	2b00      	cmp	r3, #0
+    2acc:	d000      	beq.n	2ad0 <__aeabi_dadd+0x54>
+    2ace:	e137      	b.n	2d40 <__aeabi_dadd+0x2c4>
+    2ad0:	1aba      	subs	r2, r7, r2
+    2ad2:	4297      	cmp	r7, r2
+    2ad4:	41bf      	sbcs	r7, r7
+    2ad6:	1a64      	subs	r4, r4, r1
+    2ad8:	427f      	negs	r7, r7
+    2ada:	1be4      	subs	r4, r4, r7
+    2adc:	2601      	movs	r6, #1
+    2ade:	0017      	movs	r7, r2
+    2ae0:	e024      	b.n	2b2c <__aeabi_dadd+0xb0>
+    2ae2:	4bc6      	ldr	r3, [pc, #792]	; (2dfc <__aeabi_dadd+0x380>)
+    2ae4:	429e      	cmp	r6, r3
+    2ae6:	d04d      	beq.n	2b84 <__aeabi_dadd+0x108>
+    2ae8:	2380      	movs	r3, #128	; 0x80
+    2aea:	041b      	lsls	r3, r3, #16
+    2aec:	4319      	orrs	r1, r3
+    2aee:	2d38      	cmp	r5, #56	; 0x38
+    2af0:	dd00      	ble.n	2af4 <__aeabi_dadd+0x78>
+    2af2:	e107      	b.n	2d04 <__aeabi_dadd+0x288>
+    2af4:	2d1f      	cmp	r5, #31
+    2af6:	dd00      	ble.n	2afa <__aeabi_dadd+0x7e>
+    2af8:	e138      	b.n	2d6c <__aeabi_dadd+0x2f0>
+    2afa:	2020      	movs	r0, #32
+    2afc:	1b43      	subs	r3, r0, r5
+    2afe:	469a      	mov	sl, r3
+    2b00:	000b      	movs	r3, r1
+    2b02:	4650      	mov	r0, sl
+    2b04:	4083      	lsls	r3, r0
+    2b06:	4699      	mov	r9, r3
+    2b08:	0013      	movs	r3, r2
+    2b0a:	4648      	mov	r0, r9
+    2b0c:	40eb      	lsrs	r3, r5
+    2b0e:	4318      	orrs	r0, r3
+    2b10:	0003      	movs	r3, r0
+    2b12:	4650      	mov	r0, sl
+    2b14:	4082      	lsls	r2, r0
+    2b16:	1e50      	subs	r0, r2, #1
+    2b18:	4182      	sbcs	r2, r0
+    2b1a:	40e9      	lsrs	r1, r5
+    2b1c:	431a      	orrs	r2, r3
+    2b1e:	1aba      	subs	r2, r7, r2
+    2b20:	1a61      	subs	r1, r4, r1
+    2b22:	4297      	cmp	r7, r2
+    2b24:	41a4      	sbcs	r4, r4
+    2b26:	0017      	movs	r7, r2
+    2b28:	4264      	negs	r4, r4
+    2b2a:	1b0c      	subs	r4, r1, r4
+    2b2c:	0223      	lsls	r3, r4, #8
+    2b2e:	d562      	bpl.n	2bf6 <__aeabi_dadd+0x17a>
+    2b30:	0264      	lsls	r4, r4, #9
+    2b32:	0a65      	lsrs	r5, r4, #9
+    2b34:	2d00      	cmp	r5, #0
+    2b36:	d100      	bne.n	2b3a <__aeabi_dadd+0xbe>
+    2b38:	e0df      	b.n	2cfa <__aeabi_dadd+0x27e>
+    2b3a:	0028      	movs	r0, r5
+    2b3c:	f001 fe22 	bl	4784 <__clzsi2>
+    2b40:	0003      	movs	r3, r0
+    2b42:	3b08      	subs	r3, #8
+    2b44:	2b1f      	cmp	r3, #31
+    2b46:	dd00      	ble.n	2b4a <__aeabi_dadd+0xce>
+    2b48:	e0d2      	b.n	2cf0 <__aeabi_dadd+0x274>
+    2b4a:	2220      	movs	r2, #32
+    2b4c:	003c      	movs	r4, r7
+    2b4e:	1ad2      	subs	r2, r2, r3
+    2b50:	409d      	lsls	r5, r3
+    2b52:	40d4      	lsrs	r4, r2
+    2b54:	409f      	lsls	r7, r3
+    2b56:	4325      	orrs	r5, r4
+    2b58:	429e      	cmp	r6, r3
+    2b5a:	dd00      	ble.n	2b5e <__aeabi_dadd+0xe2>
+    2b5c:	e0c4      	b.n	2ce8 <__aeabi_dadd+0x26c>
+    2b5e:	1b9e      	subs	r6, r3, r6
+    2b60:	1c73      	adds	r3, r6, #1
+    2b62:	2b1f      	cmp	r3, #31
+    2b64:	dd00      	ble.n	2b68 <__aeabi_dadd+0xec>
+    2b66:	e0f1      	b.n	2d4c <__aeabi_dadd+0x2d0>
+    2b68:	2220      	movs	r2, #32
+    2b6a:	0038      	movs	r0, r7
+    2b6c:	0029      	movs	r1, r5
+    2b6e:	1ad2      	subs	r2, r2, r3
+    2b70:	40d8      	lsrs	r0, r3
+    2b72:	4091      	lsls	r1, r2
+    2b74:	4097      	lsls	r7, r2
+    2b76:	002c      	movs	r4, r5
+    2b78:	4301      	orrs	r1, r0
+    2b7a:	1e78      	subs	r0, r7, #1
+    2b7c:	4187      	sbcs	r7, r0
+    2b7e:	40dc      	lsrs	r4, r3
+    2b80:	2600      	movs	r6, #0
+    2b82:	430f      	orrs	r7, r1
+    2b84:	077b      	lsls	r3, r7, #29
+    2b86:	d009      	beq.n	2b9c <__aeabi_dadd+0x120>
+    2b88:	230f      	movs	r3, #15
+    2b8a:	403b      	ands	r3, r7
+    2b8c:	2b04      	cmp	r3, #4
+    2b8e:	d005      	beq.n	2b9c <__aeabi_dadd+0x120>
+    2b90:	1d3b      	adds	r3, r7, #4
+    2b92:	42bb      	cmp	r3, r7
+    2b94:	41bf      	sbcs	r7, r7
+    2b96:	427f      	negs	r7, r7
+    2b98:	19e4      	adds	r4, r4, r7
+    2b9a:	001f      	movs	r7, r3
+    2b9c:	0223      	lsls	r3, r4, #8
+    2b9e:	d52c      	bpl.n	2bfa <__aeabi_dadd+0x17e>
+    2ba0:	4b96      	ldr	r3, [pc, #600]	; (2dfc <__aeabi_dadd+0x380>)
+    2ba2:	3601      	adds	r6, #1
+    2ba4:	429e      	cmp	r6, r3
+    2ba6:	d100      	bne.n	2baa <__aeabi_dadd+0x12e>
+    2ba8:	e09a      	b.n	2ce0 <__aeabi_dadd+0x264>
+    2baa:	4645      	mov	r5, r8
+    2bac:	4b94      	ldr	r3, [pc, #592]	; (2e00 <__aeabi_dadd+0x384>)
+    2bae:	08ff      	lsrs	r7, r7, #3
+    2bb0:	401c      	ands	r4, r3
+    2bb2:	0760      	lsls	r0, r4, #29
+    2bb4:	0576      	lsls	r6, r6, #21
+    2bb6:	0264      	lsls	r4, r4, #9
+    2bb8:	4307      	orrs	r7, r0
+    2bba:	0b24      	lsrs	r4, r4, #12
+    2bbc:	0d76      	lsrs	r6, r6, #21
+    2bbe:	2100      	movs	r1, #0
+    2bc0:	0324      	lsls	r4, r4, #12
+    2bc2:	0b23      	lsrs	r3, r4, #12
+    2bc4:	0d0c      	lsrs	r4, r1, #20
+    2bc6:	4a8f      	ldr	r2, [pc, #572]	; (2e04 <__aeabi_dadd+0x388>)
+    2bc8:	0524      	lsls	r4, r4, #20
+    2bca:	431c      	orrs	r4, r3
+    2bcc:	4014      	ands	r4, r2
+    2bce:	0533      	lsls	r3, r6, #20
+    2bd0:	4323      	orrs	r3, r4
+    2bd2:	005b      	lsls	r3, r3, #1
+    2bd4:	07ed      	lsls	r5, r5, #31
+    2bd6:	085b      	lsrs	r3, r3, #1
+    2bd8:	432b      	orrs	r3, r5
+    2bda:	0038      	movs	r0, r7
+    2bdc:	0019      	movs	r1, r3
+    2bde:	bc3c      	pop	{r2, r3, r4, r5}
+    2be0:	4690      	mov	r8, r2
+    2be2:	4699      	mov	r9, r3
+    2be4:	46a2      	mov	sl, r4
+    2be6:	46ab      	mov	fp, r5
+    2be8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    2bea:	4664      	mov	r4, ip
+    2bec:	4304      	orrs	r4, r0
+    2bee:	d100      	bne.n	2bf2 <__aeabi_dadd+0x176>
+    2bf0:	e211      	b.n	3016 <__aeabi_dadd+0x59a>
+    2bf2:	0004      	movs	r4, r0
+    2bf4:	4667      	mov	r7, ip
+    2bf6:	077b      	lsls	r3, r7, #29
+    2bf8:	d1c6      	bne.n	2b88 <__aeabi_dadd+0x10c>
+    2bfa:	4645      	mov	r5, r8
+    2bfc:	0760      	lsls	r0, r4, #29
+    2bfe:	08ff      	lsrs	r7, r7, #3
+    2c00:	4307      	orrs	r7, r0
+    2c02:	08e4      	lsrs	r4, r4, #3
+    2c04:	4b7d      	ldr	r3, [pc, #500]	; (2dfc <__aeabi_dadd+0x380>)
+    2c06:	429e      	cmp	r6, r3
+    2c08:	d030      	beq.n	2c6c <__aeabi_dadd+0x1f0>
+    2c0a:	0324      	lsls	r4, r4, #12
+    2c0c:	0576      	lsls	r6, r6, #21
+    2c0e:	0b24      	lsrs	r4, r4, #12
+    2c10:	0d76      	lsrs	r6, r6, #21
+    2c12:	e7d4      	b.n	2bbe <__aeabi_dadd+0x142>
+    2c14:	1a33      	subs	r3, r6, r0
+    2c16:	469a      	mov	sl, r3
+    2c18:	2b00      	cmp	r3, #0
+    2c1a:	dd78      	ble.n	2d0e <__aeabi_dadd+0x292>
+    2c1c:	2800      	cmp	r0, #0
+    2c1e:	d031      	beq.n	2c84 <__aeabi_dadd+0x208>
+    2c20:	4876      	ldr	r0, [pc, #472]	; (2dfc <__aeabi_dadd+0x380>)
+    2c22:	4286      	cmp	r6, r0
+    2c24:	d0ae      	beq.n	2b84 <__aeabi_dadd+0x108>
+    2c26:	2080      	movs	r0, #128	; 0x80
+    2c28:	0400      	lsls	r0, r0, #16
+    2c2a:	4301      	orrs	r1, r0
+    2c2c:	4653      	mov	r3, sl
+    2c2e:	2b38      	cmp	r3, #56	; 0x38
+    2c30:	dc00      	bgt.n	2c34 <__aeabi_dadd+0x1b8>
+    2c32:	e0e9      	b.n	2e08 <__aeabi_dadd+0x38c>
+    2c34:	430a      	orrs	r2, r1
+    2c36:	1e51      	subs	r1, r2, #1
+    2c38:	418a      	sbcs	r2, r1
+    2c3a:	2100      	movs	r1, #0
+    2c3c:	19d2      	adds	r2, r2, r7
+    2c3e:	42ba      	cmp	r2, r7
+    2c40:	41bf      	sbcs	r7, r7
+    2c42:	1909      	adds	r1, r1, r4
+    2c44:	427c      	negs	r4, r7
+    2c46:	0017      	movs	r7, r2
+    2c48:	190c      	adds	r4, r1, r4
+    2c4a:	0223      	lsls	r3, r4, #8
+    2c4c:	d5d3      	bpl.n	2bf6 <__aeabi_dadd+0x17a>
+    2c4e:	4b6b      	ldr	r3, [pc, #428]	; (2dfc <__aeabi_dadd+0x380>)
+    2c50:	3601      	adds	r6, #1
+    2c52:	429e      	cmp	r6, r3
+    2c54:	d100      	bne.n	2c58 <__aeabi_dadd+0x1dc>
+    2c56:	e13a      	b.n	2ece <__aeabi_dadd+0x452>
+    2c58:	2001      	movs	r0, #1
+    2c5a:	4b69      	ldr	r3, [pc, #420]	; (2e00 <__aeabi_dadd+0x384>)
+    2c5c:	401c      	ands	r4, r3
+    2c5e:	087b      	lsrs	r3, r7, #1
+    2c60:	4007      	ands	r7, r0
+    2c62:	431f      	orrs	r7, r3
+    2c64:	07e0      	lsls	r0, r4, #31
+    2c66:	4307      	orrs	r7, r0
+    2c68:	0864      	lsrs	r4, r4, #1
+    2c6a:	e78b      	b.n	2b84 <__aeabi_dadd+0x108>
+    2c6c:	0023      	movs	r3, r4
+    2c6e:	433b      	orrs	r3, r7
+    2c70:	d100      	bne.n	2c74 <__aeabi_dadd+0x1f8>
+    2c72:	e1cb      	b.n	300c <__aeabi_dadd+0x590>
+    2c74:	2280      	movs	r2, #128	; 0x80
+    2c76:	0312      	lsls	r2, r2, #12
+    2c78:	4314      	orrs	r4, r2
+    2c7a:	0324      	lsls	r4, r4, #12
+    2c7c:	0b24      	lsrs	r4, r4, #12
+    2c7e:	e79e      	b.n	2bbe <__aeabi_dadd+0x142>
+    2c80:	002e      	movs	r6, r5
+    2c82:	e77f      	b.n	2b84 <__aeabi_dadd+0x108>
+    2c84:	0008      	movs	r0, r1
+    2c86:	4310      	orrs	r0, r2
+    2c88:	d100      	bne.n	2c8c <__aeabi_dadd+0x210>
+    2c8a:	e0b4      	b.n	2df6 <__aeabi_dadd+0x37a>
+    2c8c:	1e58      	subs	r0, r3, #1
+    2c8e:	2800      	cmp	r0, #0
+    2c90:	d000      	beq.n	2c94 <__aeabi_dadd+0x218>
+    2c92:	e0de      	b.n	2e52 <__aeabi_dadd+0x3d6>
+    2c94:	18ba      	adds	r2, r7, r2
+    2c96:	42ba      	cmp	r2, r7
+    2c98:	419b      	sbcs	r3, r3
+    2c9a:	1864      	adds	r4, r4, r1
+    2c9c:	425b      	negs	r3, r3
+    2c9e:	18e4      	adds	r4, r4, r3
+    2ca0:	0017      	movs	r7, r2
+    2ca2:	2601      	movs	r6, #1
+    2ca4:	0223      	lsls	r3, r4, #8
+    2ca6:	d5a6      	bpl.n	2bf6 <__aeabi_dadd+0x17a>
+    2ca8:	2602      	movs	r6, #2
+    2caa:	e7d5      	b.n	2c58 <__aeabi_dadd+0x1dc>
+    2cac:	2d00      	cmp	r5, #0
+    2cae:	d16e      	bne.n	2d8e <__aeabi_dadd+0x312>
+    2cb0:	1c70      	adds	r0, r6, #1
+    2cb2:	0540      	lsls	r0, r0, #21
+    2cb4:	0d40      	lsrs	r0, r0, #21
+    2cb6:	2801      	cmp	r0, #1
+    2cb8:	dc00      	bgt.n	2cbc <__aeabi_dadd+0x240>
+    2cba:	e0f9      	b.n	2eb0 <__aeabi_dadd+0x434>
+    2cbc:	1ab8      	subs	r0, r7, r2
+    2cbe:	4684      	mov	ip, r0
+    2cc0:	4287      	cmp	r7, r0
+    2cc2:	4180      	sbcs	r0, r0
+    2cc4:	1ae5      	subs	r5, r4, r3
+    2cc6:	4240      	negs	r0, r0
+    2cc8:	1a2d      	subs	r5, r5, r0
+    2cca:	0228      	lsls	r0, r5, #8
+    2ccc:	d400      	bmi.n	2cd0 <__aeabi_dadd+0x254>
+    2cce:	e089      	b.n	2de4 <__aeabi_dadd+0x368>
+    2cd0:	1bd7      	subs	r7, r2, r7
+    2cd2:	42ba      	cmp	r2, r7
+    2cd4:	4192      	sbcs	r2, r2
+    2cd6:	1b1c      	subs	r4, r3, r4
+    2cd8:	4252      	negs	r2, r2
+    2cda:	1aa5      	subs	r5, r4, r2
+    2cdc:	46d8      	mov	r8, fp
+    2cde:	e729      	b.n	2b34 <__aeabi_dadd+0xb8>
+    2ce0:	4645      	mov	r5, r8
+    2ce2:	2400      	movs	r4, #0
+    2ce4:	2700      	movs	r7, #0
+    2ce6:	e76a      	b.n	2bbe <__aeabi_dadd+0x142>
+    2ce8:	4c45      	ldr	r4, [pc, #276]	; (2e00 <__aeabi_dadd+0x384>)
+    2cea:	1af6      	subs	r6, r6, r3
+    2cec:	402c      	ands	r4, r5
+    2cee:	e749      	b.n	2b84 <__aeabi_dadd+0x108>
+    2cf0:	003d      	movs	r5, r7
+    2cf2:	3828      	subs	r0, #40	; 0x28
+    2cf4:	4085      	lsls	r5, r0
+    2cf6:	2700      	movs	r7, #0
+    2cf8:	e72e      	b.n	2b58 <__aeabi_dadd+0xdc>
+    2cfa:	0038      	movs	r0, r7
+    2cfc:	f001 fd42 	bl	4784 <__clzsi2>
+    2d00:	3020      	adds	r0, #32
+    2d02:	e71d      	b.n	2b40 <__aeabi_dadd+0xc4>
+    2d04:	430a      	orrs	r2, r1
+    2d06:	1e51      	subs	r1, r2, #1
+    2d08:	418a      	sbcs	r2, r1
+    2d0a:	2100      	movs	r1, #0
+    2d0c:	e707      	b.n	2b1e <__aeabi_dadd+0xa2>
+    2d0e:	2b00      	cmp	r3, #0
+    2d10:	d000      	beq.n	2d14 <__aeabi_dadd+0x298>
+    2d12:	e0f3      	b.n	2efc <__aeabi_dadd+0x480>
+    2d14:	1c70      	adds	r0, r6, #1
+    2d16:	0543      	lsls	r3, r0, #21
+    2d18:	0d5b      	lsrs	r3, r3, #21
+    2d1a:	2b01      	cmp	r3, #1
+    2d1c:	dc00      	bgt.n	2d20 <__aeabi_dadd+0x2a4>
+    2d1e:	e0ad      	b.n	2e7c <__aeabi_dadd+0x400>
+    2d20:	4b36      	ldr	r3, [pc, #216]	; (2dfc <__aeabi_dadd+0x380>)
+    2d22:	4298      	cmp	r0, r3
+    2d24:	d100      	bne.n	2d28 <__aeabi_dadd+0x2ac>
+    2d26:	e0d1      	b.n	2ecc <__aeabi_dadd+0x450>
+    2d28:	18ba      	adds	r2, r7, r2
+    2d2a:	42ba      	cmp	r2, r7
+    2d2c:	41bf      	sbcs	r7, r7
+    2d2e:	1864      	adds	r4, r4, r1
+    2d30:	427f      	negs	r7, r7
+    2d32:	19e4      	adds	r4, r4, r7
+    2d34:	07e7      	lsls	r7, r4, #31
+    2d36:	0852      	lsrs	r2, r2, #1
+    2d38:	4317      	orrs	r7, r2
+    2d3a:	0864      	lsrs	r4, r4, #1
+    2d3c:	0006      	movs	r6, r0
+    2d3e:	e721      	b.n	2b84 <__aeabi_dadd+0x108>
+    2d40:	482e      	ldr	r0, [pc, #184]	; (2dfc <__aeabi_dadd+0x380>)
+    2d42:	4285      	cmp	r5, r0
+    2d44:	d100      	bne.n	2d48 <__aeabi_dadd+0x2cc>
+    2d46:	e093      	b.n	2e70 <__aeabi_dadd+0x3f4>
+    2d48:	001d      	movs	r5, r3
+    2d4a:	e6d0      	b.n	2aee <__aeabi_dadd+0x72>
+    2d4c:	0029      	movs	r1, r5
+    2d4e:	3e1f      	subs	r6, #31
+    2d50:	40f1      	lsrs	r1, r6
+    2d52:	2b20      	cmp	r3, #32
+    2d54:	d100      	bne.n	2d58 <__aeabi_dadd+0x2dc>
+    2d56:	e08d      	b.n	2e74 <__aeabi_dadd+0x3f8>
+    2d58:	2240      	movs	r2, #64	; 0x40
+    2d5a:	1ad3      	subs	r3, r2, r3
+    2d5c:	409d      	lsls	r5, r3
+    2d5e:	432f      	orrs	r7, r5
+    2d60:	1e7d      	subs	r5, r7, #1
+    2d62:	41af      	sbcs	r7, r5
+    2d64:	2400      	movs	r4, #0
+    2d66:	430f      	orrs	r7, r1
+    2d68:	2600      	movs	r6, #0
+    2d6a:	e744      	b.n	2bf6 <__aeabi_dadd+0x17a>
+    2d6c:	002b      	movs	r3, r5
+    2d6e:	0008      	movs	r0, r1
+    2d70:	3b20      	subs	r3, #32
+    2d72:	40d8      	lsrs	r0, r3
+    2d74:	0003      	movs	r3, r0
+    2d76:	2d20      	cmp	r5, #32
+    2d78:	d100      	bne.n	2d7c <__aeabi_dadd+0x300>
+    2d7a:	e07d      	b.n	2e78 <__aeabi_dadd+0x3fc>
+    2d7c:	2040      	movs	r0, #64	; 0x40
+    2d7e:	1b45      	subs	r5, r0, r5
+    2d80:	40a9      	lsls	r1, r5
+    2d82:	430a      	orrs	r2, r1
+    2d84:	1e51      	subs	r1, r2, #1
+    2d86:	418a      	sbcs	r2, r1
+    2d88:	2100      	movs	r1, #0
+    2d8a:	431a      	orrs	r2, r3
+    2d8c:	e6c7      	b.n	2b1e <__aeabi_dadd+0xa2>
+    2d8e:	2e00      	cmp	r6, #0
+    2d90:	d050      	beq.n	2e34 <__aeabi_dadd+0x3b8>
+    2d92:	4e1a      	ldr	r6, [pc, #104]	; (2dfc <__aeabi_dadd+0x380>)
+    2d94:	42b0      	cmp	r0, r6
+    2d96:	d057      	beq.n	2e48 <__aeabi_dadd+0x3cc>
+    2d98:	2680      	movs	r6, #128	; 0x80
+    2d9a:	426b      	negs	r3, r5
+    2d9c:	4699      	mov	r9, r3
+    2d9e:	0436      	lsls	r6, r6, #16
+    2da0:	4334      	orrs	r4, r6
+    2da2:	464b      	mov	r3, r9
+    2da4:	2b38      	cmp	r3, #56	; 0x38
+    2da6:	dd00      	ble.n	2daa <__aeabi_dadd+0x32e>
+    2da8:	e0d6      	b.n	2f58 <__aeabi_dadd+0x4dc>
+    2daa:	2b1f      	cmp	r3, #31
+    2dac:	dd00      	ble.n	2db0 <__aeabi_dadd+0x334>
+    2dae:	e135      	b.n	301c <__aeabi_dadd+0x5a0>
+    2db0:	2620      	movs	r6, #32
+    2db2:	1af5      	subs	r5, r6, r3
+    2db4:	0026      	movs	r6, r4
+    2db6:	40ae      	lsls	r6, r5
+    2db8:	46b2      	mov	sl, r6
+    2dba:	003e      	movs	r6, r7
+    2dbc:	40de      	lsrs	r6, r3
+    2dbe:	46ac      	mov	ip, r5
+    2dc0:	0035      	movs	r5, r6
+    2dc2:	4656      	mov	r6, sl
+    2dc4:	432e      	orrs	r6, r5
+    2dc6:	4665      	mov	r5, ip
+    2dc8:	40af      	lsls	r7, r5
+    2dca:	1e7d      	subs	r5, r7, #1
+    2dcc:	41af      	sbcs	r7, r5
+    2dce:	40dc      	lsrs	r4, r3
+    2dd0:	4337      	orrs	r7, r6
+    2dd2:	1bd7      	subs	r7, r2, r7
+    2dd4:	42ba      	cmp	r2, r7
+    2dd6:	4192      	sbcs	r2, r2
+    2dd8:	1b0c      	subs	r4, r1, r4
+    2dda:	4252      	negs	r2, r2
+    2ddc:	1aa4      	subs	r4, r4, r2
+    2dde:	0006      	movs	r6, r0
+    2de0:	46d8      	mov	r8, fp
+    2de2:	e6a3      	b.n	2b2c <__aeabi_dadd+0xb0>
+    2de4:	4664      	mov	r4, ip
+    2de6:	4667      	mov	r7, ip
+    2de8:	432c      	orrs	r4, r5
+    2dea:	d000      	beq.n	2dee <__aeabi_dadd+0x372>
+    2dec:	e6a2      	b.n	2b34 <__aeabi_dadd+0xb8>
+    2dee:	2500      	movs	r5, #0
+    2df0:	2600      	movs	r6, #0
+    2df2:	2700      	movs	r7, #0
+    2df4:	e706      	b.n	2c04 <__aeabi_dadd+0x188>
+    2df6:	001e      	movs	r6, r3
+    2df8:	e6c4      	b.n	2b84 <__aeabi_dadd+0x108>
+    2dfa:	46c0      	nop			; (mov r8, r8)
+    2dfc:	000007ff 	.word	0x000007ff
+    2e00:	ff7fffff 	.word	0xff7fffff
+    2e04:	800fffff 	.word	0x800fffff
+    2e08:	2b1f      	cmp	r3, #31
+    2e0a:	dc63      	bgt.n	2ed4 <__aeabi_dadd+0x458>
+    2e0c:	2020      	movs	r0, #32
+    2e0e:	1ac3      	subs	r3, r0, r3
+    2e10:	0008      	movs	r0, r1
+    2e12:	4098      	lsls	r0, r3
+    2e14:	469c      	mov	ip, r3
+    2e16:	4683      	mov	fp, r0
+    2e18:	4653      	mov	r3, sl
+    2e1a:	0010      	movs	r0, r2
+    2e1c:	40d8      	lsrs	r0, r3
+    2e1e:	0003      	movs	r3, r0
+    2e20:	4658      	mov	r0, fp
+    2e22:	4318      	orrs	r0, r3
+    2e24:	4663      	mov	r3, ip
+    2e26:	409a      	lsls	r2, r3
+    2e28:	1e53      	subs	r3, r2, #1
+    2e2a:	419a      	sbcs	r2, r3
+    2e2c:	4653      	mov	r3, sl
+    2e2e:	4302      	orrs	r2, r0
+    2e30:	40d9      	lsrs	r1, r3
+    2e32:	e703      	b.n	2c3c <__aeabi_dadd+0x1c0>
+    2e34:	0026      	movs	r6, r4
+    2e36:	433e      	orrs	r6, r7
+    2e38:	d006      	beq.n	2e48 <__aeabi_dadd+0x3cc>
+    2e3a:	43eb      	mvns	r3, r5
+    2e3c:	4699      	mov	r9, r3
+    2e3e:	2b00      	cmp	r3, #0
+    2e40:	d0c7      	beq.n	2dd2 <__aeabi_dadd+0x356>
+    2e42:	4e94      	ldr	r6, [pc, #592]	; (3094 <__aeabi_dadd+0x618>)
+    2e44:	42b0      	cmp	r0, r6
+    2e46:	d1ac      	bne.n	2da2 <__aeabi_dadd+0x326>
+    2e48:	000c      	movs	r4, r1
+    2e4a:	0017      	movs	r7, r2
+    2e4c:	0006      	movs	r6, r0
+    2e4e:	46d8      	mov	r8, fp
+    2e50:	e698      	b.n	2b84 <__aeabi_dadd+0x108>
+    2e52:	4b90      	ldr	r3, [pc, #576]	; (3094 <__aeabi_dadd+0x618>)
+    2e54:	459a      	cmp	sl, r3
+    2e56:	d00b      	beq.n	2e70 <__aeabi_dadd+0x3f4>
+    2e58:	4682      	mov	sl, r0
+    2e5a:	e6e7      	b.n	2c2c <__aeabi_dadd+0x1b0>
+    2e5c:	2800      	cmp	r0, #0
+    2e5e:	d000      	beq.n	2e62 <__aeabi_dadd+0x3e6>
+    2e60:	e09e      	b.n	2fa0 <__aeabi_dadd+0x524>
+    2e62:	0018      	movs	r0, r3
+    2e64:	4310      	orrs	r0, r2
+    2e66:	d100      	bne.n	2e6a <__aeabi_dadd+0x3ee>
+    2e68:	e0e9      	b.n	303e <__aeabi_dadd+0x5c2>
+    2e6a:	001c      	movs	r4, r3
+    2e6c:	0017      	movs	r7, r2
+    2e6e:	46d8      	mov	r8, fp
+    2e70:	4e88      	ldr	r6, [pc, #544]	; (3094 <__aeabi_dadd+0x618>)
+    2e72:	e687      	b.n	2b84 <__aeabi_dadd+0x108>
+    2e74:	2500      	movs	r5, #0
+    2e76:	e772      	b.n	2d5e <__aeabi_dadd+0x2e2>
+    2e78:	2100      	movs	r1, #0
+    2e7a:	e782      	b.n	2d82 <__aeabi_dadd+0x306>
+    2e7c:	0023      	movs	r3, r4
+    2e7e:	433b      	orrs	r3, r7
+    2e80:	2e00      	cmp	r6, #0
+    2e82:	d000      	beq.n	2e86 <__aeabi_dadd+0x40a>
+    2e84:	e0ab      	b.n	2fde <__aeabi_dadd+0x562>
+    2e86:	2b00      	cmp	r3, #0
+    2e88:	d100      	bne.n	2e8c <__aeabi_dadd+0x410>
+    2e8a:	e0e7      	b.n	305c <__aeabi_dadd+0x5e0>
+    2e8c:	000b      	movs	r3, r1
+    2e8e:	4313      	orrs	r3, r2
+    2e90:	d100      	bne.n	2e94 <__aeabi_dadd+0x418>
+    2e92:	e677      	b.n	2b84 <__aeabi_dadd+0x108>
+    2e94:	18ba      	adds	r2, r7, r2
+    2e96:	42ba      	cmp	r2, r7
+    2e98:	41bf      	sbcs	r7, r7
+    2e9a:	1864      	adds	r4, r4, r1
+    2e9c:	427f      	negs	r7, r7
+    2e9e:	19e4      	adds	r4, r4, r7
+    2ea0:	0223      	lsls	r3, r4, #8
+    2ea2:	d400      	bmi.n	2ea6 <__aeabi_dadd+0x42a>
+    2ea4:	e0f2      	b.n	308c <__aeabi_dadd+0x610>
+    2ea6:	4b7c      	ldr	r3, [pc, #496]	; (3098 <__aeabi_dadd+0x61c>)
+    2ea8:	0017      	movs	r7, r2
+    2eaa:	401c      	ands	r4, r3
+    2eac:	0006      	movs	r6, r0
+    2eae:	e669      	b.n	2b84 <__aeabi_dadd+0x108>
+    2eb0:	0020      	movs	r0, r4
+    2eb2:	4338      	orrs	r0, r7
+    2eb4:	2e00      	cmp	r6, #0
+    2eb6:	d1d1      	bne.n	2e5c <__aeabi_dadd+0x3e0>
+    2eb8:	2800      	cmp	r0, #0
+    2eba:	d15b      	bne.n	2f74 <__aeabi_dadd+0x4f8>
+    2ebc:	001c      	movs	r4, r3
+    2ebe:	4314      	orrs	r4, r2
+    2ec0:	d100      	bne.n	2ec4 <__aeabi_dadd+0x448>
+    2ec2:	e0a8      	b.n	3016 <__aeabi_dadd+0x59a>
+    2ec4:	001c      	movs	r4, r3
+    2ec6:	0017      	movs	r7, r2
+    2ec8:	46d8      	mov	r8, fp
+    2eca:	e65b      	b.n	2b84 <__aeabi_dadd+0x108>
+    2ecc:	0006      	movs	r6, r0
+    2ece:	2400      	movs	r4, #0
+    2ed0:	2700      	movs	r7, #0
+    2ed2:	e697      	b.n	2c04 <__aeabi_dadd+0x188>
+    2ed4:	4650      	mov	r0, sl
+    2ed6:	000b      	movs	r3, r1
+    2ed8:	3820      	subs	r0, #32
+    2eda:	40c3      	lsrs	r3, r0
+    2edc:	4699      	mov	r9, r3
+    2ede:	4653      	mov	r3, sl
+    2ee0:	2b20      	cmp	r3, #32
+    2ee2:	d100      	bne.n	2ee6 <__aeabi_dadd+0x46a>
+    2ee4:	e095      	b.n	3012 <__aeabi_dadd+0x596>
+    2ee6:	2340      	movs	r3, #64	; 0x40
+    2ee8:	4650      	mov	r0, sl
+    2eea:	1a1b      	subs	r3, r3, r0
+    2eec:	4099      	lsls	r1, r3
+    2eee:	430a      	orrs	r2, r1
+    2ef0:	1e51      	subs	r1, r2, #1
+    2ef2:	418a      	sbcs	r2, r1
+    2ef4:	464b      	mov	r3, r9
+    2ef6:	2100      	movs	r1, #0
+    2ef8:	431a      	orrs	r2, r3
+    2efa:	e69f      	b.n	2c3c <__aeabi_dadd+0x1c0>
+    2efc:	2e00      	cmp	r6, #0
+    2efe:	d130      	bne.n	2f62 <__aeabi_dadd+0x4e6>
+    2f00:	0026      	movs	r6, r4
+    2f02:	433e      	orrs	r6, r7
+    2f04:	d067      	beq.n	2fd6 <__aeabi_dadd+0x55a>
+    2f06:	43db      	mvns	r3, r3
+    2f08:	469a      	mov	sl, r3
+    2f0a:	2b00      	cmp	r3, #0
+    2f0c:	d01c      	beq.n	2f48 <__aeabi_dadd+0x4cc>
+    2f0e:	4e61      	ldr	r6, [pc, #388]	; (3094 <__aeabi_dadd+0x618>)
+    2f10:	42b0      	cmp	r0, r6
+    2f12:	d060      	beq.n	2fd6 <__aeabi_dadd+0x55a>
+    2f14:	4653      	mov	r3, sl
+    2f16:	2b38      	cmp	r3, #56	; 0x38
+    2f18:	dd00      	ble.n	2f1c <__aeabi_dadd+0x4a0>
+    2f1a:	e096      	b.n	304a <__aeabi_dadd+0x5ce>
+    2f1c:	2b1f      	cmp	r3, #31
+    2f1e:	dd00      	ble.n	2f22 <__aeabi_dadd+0x4a6>
+    2f20:	e09f      	b.n	3062 <__aeabi_dadd+0x5e6>
+    2f22:	2620      	movs	r6, #32
+    2f24:	1af3      	subs	r3, r6, r3
+    2f26:	0026      	movs	r6, r4
+    2f28:	409e      	lsls	r6, r3
+    2f2a:	469c      	mov	ip, r3
+    2f2c:	46b3      	mov	fp, r6
+    2f2e:	4653      	mov	r3, sl
+    2f30:	003e      	movs	r6, r7
+    2f32:	40de      	lsrs	r6, r3
+    2f34:	0033      	movs	r3, r6
+    2f36:	465e      	mov	r6, fp
+    2f38:	431e      	orrs	r6, r3
+    2f3a:	4663      	mov	r3, ip
+    2f3c:	409f      	lsls	r7, r3
+    2f3e:	1e7b      	subs	r3, r7, #1
+    2f40:	419f      	sbcs	r7, r3
+    2f42:	4653      	mov	r3, sl
+    2f44:	40dc      	lsrs	r4, r3
+    2f46:	4337      	orrs	r7, r6
+    2f48:	18bf      	adds	r7, r7, r2
+    2f4a:	4297      	cmp	r7, r2
+    2f4c:	4192      	sbcs	r2, r2
+    2f4e:	1864      	adds	r4, r4, r1
+    2f50:	4252      	negs	r2, r2
+    2f52:	18a4      	adds	r4, r4, r2
+    2f54:	0006      	movs	r6, r0
+    2f56:	e678      	b.n	2c4a <__aeabi_dadd+0x1ce>
+    2f58:	4327      	orrs	r7, r4
+    2f5a:	1e7c      	subs	r4, r7, #1
+    2f5c:	41a7      	sbcs	r7, r4
+    2f5e:	2400      	movs	r4, #0
+    2f60:	e737      	b.n	2dd2 <__aeabi_dadd+0x356>
+    2f62:	4e4c      	ldr	r6, [pc, #304]	; (3094 <__aeabi_dadd+0x618>)
+    2f64:	42b0      	cmp	r0, r6
+    2f66:	d036      	beq.n	2fd6 <__aeabi_dadd+0x55a>
+    2f68:	2680      	movs	r6, #128	; 0x80
+    2f6a:	425b      	negs	r3, r3
+    2f6c:	0436      	lsls	r6, r6, #16
+    2f6e:	469a      	mov	sl, r3
+    2f70:	4334      	orrs	r4, r6
+    2f72:	e7cf      	b.n	2f14 <__aeabi_dadd+0x498>
+    2f74:	0018      	movs	r0, r3
+    2f76:	4310      	orrs	r0, r2
+    2f78:	d100      	bne.n	2f7c <__aeabi_dadd+0x500>
+    2f7a:	e603      	b.n	2b84 <__aeabi_dadd+0x108>
+    2f7c:	1ab8      	subs	r0, r7, r2
+    2f7e:	4684      	mov	ip, r0
+    2f80:	4567      	cmp	r7, ip
+    2f82:	41ad      	sbcs	r5, r5
+    2f84:	1ae0      	subs	r0, r4, r3
+    2f86:	426d      	negs	r5, r5
+    2f88:	1b40      	subs	r0, r0, r5
+    2f8a:	0205      	lsls	r5, r0, #8
+    2f8c:	d400      	bmi.n	2f90 <__aeabi_dadd+0x514>
+    2f8e:	e62c      	b.n	2bea <__aeabi_dadd+0x16e>
+    2f90:	1bd7      	subs	r7, r2, r7
+    2f92:	42ba      	cmp	r2, r7
+    2f94:	4192      	sbcs	r2, r2
+    2f96:	1b1c      	subs	r4, r3, r4
+    2f98:	4252      	negs	r2, r2
+    2f9a:	1aa4      	subs	r4, r4, r2
+    2f9c:	46d8      	mov	r8, fp
+    2f9e:	e5f1      	b.n	2b84 <__aeabi_dadd+0x108>
+    2fa0:	0018      	movs	r0, r3
+    2fa2:	4310      	orrs	r0, r2
+    2fa4:	d100      	bne.n	2fa8 <__aeabi_dadd+0x52c>
+    2fa6:	e763      	b.n	2e70 <__aeabi_dadd+0x3f4>
+    2fa8:	08f8      	lsrs	r0, r7, #3
+    2faa:	0767      	lsls	r7, r4, #29
+    2fac:	4307      	orrs	r7, r0
+    2fae:	2080      	movs	r0, #128	; 0x80
+    2fb0:	08e4      	lsrs	r4, r4, #3
+    2fb2:	0300      	lsls	r0, r0, #12
+    2fb4:	4204      	tst	r4, r0
+    2fb6:	d008      	beq.n	2fca <__aeabi_dadd+0x54e>
+    2fb8:	08dd      	lsrs	r5, r3, #3
+    2fba:	4205      	tst	r5, r0
+    2fbc:	d105      	bne.n	2fca <__aeabi_dadd+0x54e>
+    2fbe:	08d2      	lsrs	r2, r2, #3
+    2fc0:	0759      	lsls	r1, r3, #29
+    2fc2:	4311      	orrs	r1, r2
+    2fc4:	000f      	movs	r7, r1
+    2fc6:	002c      	movs	r4, r5
+    2fc8:	46d8      	mov	r8, fp
+    2fca:	0f7b      	lsrs	r3, r7, #29
+    2fcc:	00e4      	lsls	r4, r4, #3
+    2fce:	431c      	orrs	r4, r3
+    2fd0:	00ff      	lsls	r7, r7, #3
+    2fd2:	4e30      	ldr	r6, [pc, #192]	; (3094 <__aeabi_dadd+0x618>)
+    2fd4:	e5d6      	b.n	2b84 <__aeabi_dadd+0x108>
+    2fd6:	000c      	movs	r4, r1
+    2fd8:	0017      	movs	r7, r2
+    2fda:	0006      	movs	r6, r0
+    2fdc:	e5d2      	b.n	2b84 <__aeabi_dadd+0x108>
+    2fde:	2b00      	cmp	r3, #0
+    2fe0:	d038      	beq.n	3054 <__aeabi_dadd+0x5d8>
+    2fe2:	000b      	movs	r3, r1
+    2fe4:	4313      	orrs	r3, r2
+    2fe6:	d100      	bne.n	2fea <__aeabi_dadd+0x56e>
+    2fe8:	e742      	b.n	2e70 <__aeabi_dadd+0x3f4>
+    2fea:	08f8      	lsrs	r0, r7, #3
+    2fec:	0767      	lsls	r7, r4, #29
+    2fee:	4307      	orrs	r7, r0
+    2ff0:	2080      	movs	r0, #128	; 0x80
+    2ff2:	08e4      	lsrs	r4, r4, #3
+    2ff4:	0300      	lsls	r0, r0, #12
+    2ff6:	4204      	tst	r4, r0
+    2ff8:	d0e7      	beq.n	2fca <__aeabi_dadd+0x54e>
+    2ffa:	08cb      	lsrs	r3, r1, #3
+    2ffc:	4203      	tst	r3, r0
+    2ffe:	d1e4      	bne.n	2fca <__aeabi_dadd+0x54e>
+    3000:	08d2      	lsrs	r2, r2, #3
+    3002:	0749      	lsls	r1, r1, #29
+    3004:	4311      	orrs	r1, r2
+    3006:	000f      	movs	r7, r1
+    3008:	001c      	movs	r4, r3
+    300a:	e7de      	b.n	2fca <__aeabi_dadd+0x54e>
+    300c:	2700      	movs	r7, #0
+    300e:	2400      	movs	r4, #0
+    3010:	e5d5      	b.n	2bbe <__aeabi_dadd+0x142>
+    3012:	2100      	movs	r1, #0
+    3014:	e76b      	b.n	2eee <__aeabi_dadd+0x472>
+    3016:	2500      	movs	r5, #0
+    3018:	2700      	movs	r7, #0
+    301a:	e5f3      	b.n	2c04 <__aeabi_dadd+0x188>
+    301c:	464e      	mov	r6, r9
+    301e:	0025      	movs	r5, r4
+    3020:	3e20      	subs	r6, #32
+    3022:	40f5      	lsrs	r5, r6
+    3024:	464b      	mov	r3, r9
+    3026:	002e      	movs	r6, r5
+    3028:	2b20      	cmp	r3, #32
+    302a:	d02d      	beq.n	3088 <__aeabi_dadd+0x60c>
+    302c:	2540      	movs	r5, #64	; 0x40
+    302e:	1aed      	subs	r5, r5, r3
+    3030:	40ac      	lsls	r4, r5
+    3032:	4327      	orrs	r7, r4
+    3034:	1e7c      	subs	r4, r7, #1
+    3036:	41a7      	sbcs	r7, r4
+    3038:	2400      	movs	r4, #0
+    303a:	4337      	orrs	r7, r6
+    303c:	e6c9      	b.n	2dd2 <__aeabi_dadd+0x356>
+    303e:	2480      	movs	r4, #128	; 0x80
+    3040:	2500      	movs	r5, #0
+    3042:	0324      	lsls	r4, r4, #12
+    3044:	4e13      	ldr	r6, [pc, #76]	; (3094 <__aeabi_dadd+0x618>)
+    3046:	2700      	movs	r7, #0
+    3048:	e5dc      	b.n	2c04 <__aeabi_dadd+0x188>
+    304a:	4327      	orrs	r7, r4
+    304c:	1e7c      	subs	r4, r7, #1
+    304e:	41a7      	sbcs	r7, r4
+    3050:	2400      	movs	r4, #0
+    3052:	e779      	b.n	2f48 <__aeabi_dadd+0x4cc>
+    3054:	000c      	movs	r4, r1
+    3056:	0017      	movs	r7, r2
+    3058:	4e0e      	ldr	r6, [pc, #56]	; (3094 <__aeabi_dadd+0x618>)
+    305a:	e593      	b.n	2b84 <__aeabi_dadd+0x108>
+    305c:	000c      	movs	r4, r1
+    305e:	0017      	movs	r7, r2
+    3060:	e590      	b.n	2b84 <__aeabi_dadd+0x108>
+    3062:	4656      	mov	r6, sl
+    3064:	0023      	movs	r3, r4
+    3066:	3e20      	subs	r6, #32
+    3068:	40f3      	lsrs	r3, r6
+    306a:	4699      	mov	r9, r3
+    306c:	4653      	mov	r3, sl
+    306e:	2b20      	cmp	r3, #32
+    3070:	d00e      	beq.n	3090 <__aeabi_dadd+0x614>
+    3072:	2340      	movs	r3, #64	; 0x40
+    3074:	4656      	mov	r6, sl
+    3076:	1b9b      	subs	r3, r3, r6
+    3078:	409c      	lsls	r4, r3
+    307a:	4327      	orrs	r7, r4
+    307c:	1e7c      	subs	r4, r7, #1
+    307e:	41a7      	sbcs	r7, r4
+    3080:	464b      	mov	r3, r9
+    3082:	2400      	movs	r4, #0
+    3084:	431f      	orrs	r7, r3
+    3086:	e75f      	b.n	2f48 <__aeabi_dadd+0x4cc>
+    3088:	2400      	movs	r4, #0
+    308a:	e7d2      	b.n	3032 <__aeabi_dadd+0x5b6>
+    308c:	0017      	movs	r7, r2
+    308e:	e5b2      	b.n	2bf6 <__aeabi_dadd+0x17a>
+    3090:	2400      	movs	r4, #0
+    3092:	e7f2      	b.n	307a <__aeabi_dadd+0x5fe>
+    3094:	000007ff 	.word	0x000007ff
+    3098:	ff7fffff 	.word	0xff7fffff
+
+0000309c <__aeabi_ddiv>:
+    309c:	b5f0      	push	{r4, r5, r6, r7, lr}
+    309e:	4657      	mov	r7, sl
+    30a0:	4645      	mov	r5, r8
+    30a2:	46de      	mov	lr, fp
+    30a4:	464e      	mov	r6, r9
+    30a6:	b5e0      	push	{r5, r6, r7, lr}
+    30a8:	004c      	lsls	r4, r1, #1
+    30aa:	030e      	lsls	r6, r1, #12
+    30ac:	b087      	sub	sp, #28
+    30ae:	4683      	mov	fp, r0
+    30b0:	4692      	mov	sl, r2
+    30b2:	001d      	movs	r5, r3
+    30b4:	4680      	mov	r8, r0
+    30b6:	0b36      	lsrs	r6, r6, #12
+    30b8:	0d64      	lsrs	r4, r4, #21
+    30ba:	0fcf      	lsrs	r7, r1, #31
+    30bc:	2c00      	cmp	r4, #0
+    30be:	d04f      	beq.n	3160 <__aeabi_ddiv+0xc4>
+    30c0:	4b6f      	ldr	r3, [pc, #444]	; (3280 <__aeabi_ddiv+0x1e4>)
+    30c2:	429c      	cmp	r4, r3
+    30c4:	d035      	beq.n	3132 <__aeabi_ddiv+0x96>
+    30c6:	2380      	movs	r3, #128	; 0x80
+    30c8:	0f42      	lsrs	r2, r0, #29
+    30ca:	041b      	lsls	r3, r3, #16
+    30cc:	00f6      	lsls	r6, r6, #3
+    30ce:	4313      	orrs	r3, r2
+    30d0:	4333      	orrs	r3, r6
+    30d2:	4699      	mov	r9, r3
+    30d4:	00c3      	lsls	r3, r0, #3
+    30d6:	4698      	mov	r8, r3
+    30d8:	4b6a      	ldr	r3, [pc, #424]	; (3284 <__aeabi_ddiv+0x1e8>)
+    30da:	2600      	movs	r6, #0
+    30dc:	469c      	mov	ip, r3
+    30de:	2300      	movs	r3, #0
+    30e0:	4464      	add	r4, ip
+    30e2:	9303      	str	r3, [sp, #12]
+    30e4:	032b      	lsls	r3, r5, #12
+    30e6:	0b1b      	lsrs	r3, r3, #12
+    30e8:	469b      	mov	fp, r3
+    30ea:	006b      	lsls	r3, r5, #1
+    30ec:	0fed      	lsrs	r5, r5, #31
+    30ee:	4650      	mov	r0, sl
+    30f0:	0d5b      	lsrs	r3, r3, #21
+    30f2:	9501      	str	r5, [sp, #4]
+    30f4:	d05e      	beq.n	31b4 <__aeabi_ddiv+0x118>
+    30f6:	4a62      	ldr	r2, [pc, #392]	; (3280 <__aeabi_ddiv+0x1e4>)
+    30f8:	4293      	cmp	r3, r2
+    30fa:	d053      	beq.n	31a4 <__aeabi_ddiv+0x108>
+    30fc:	465a      	mov	r2, fp
+    30fe:	00d1      	lsls	r1, r2, #3
+    3100:	2280      	movs	r2, #128	; 0x80
+    3102:	0f40      	lsrs	r0, r0, #29
+    3104:	0412      	lsls	r2, r2, #16
+    3106:	4302      	orrs	r2, r0
+    3108:	430a      	orrs	r2, r1
+    310a:	4693      	mov	fp, r2
+    310c:	4652      	mov	r2, sl
+    310e:	00d1      	lsls	r1, r2, #3
+    3110:	4a5c      	ldr	r2, [pc, #368]	; (3284 <__aeabi_ddiv+0x1e8>)
+    3112:	4694      	mov	ip, r2
+    3114:	2200      	movs	r2, #0
+    3116:	4463      	add	r3, ip
+    3118:	0038      	movs	r0, r7
+    311a:	4068      	eors	r0, r5
+    311c:	4684      	mov	ip, r0
+    311e:	9002      	str	r0, [sp, #8]
+    3120:	1ae4      	subs	r4, r4, r3
+    3122:	4316      	orrs	r6, r2
+    3124:	2e0f      	cmp	r6, #15
+    3126:	d900      	bls.n	312a <__aeabi_ddiv+0x8e>
+    3128:	e0b4      	b.n	3294 <__aeabi_ddiv+0x1f8>
+    312a:	4b57      	ldr	r3, [pc, #348]	; (3288 <__aeabi_ddiv+0x1ec>)
+    312c:	00b6      	lsls	r6, r6, #2
+    312e:	599b      	ldr	r3, [r3, r6]
+    3130:	469f      	mov	pc, r3
+    3132:	0003      	movs	r3, r0
+    3134:	4333      	orrs	r3, r6
+    3136:	4699      	mov	r9, r3
+    3138:	d16c      	bne.n	3214 <__aeabi_ddiv+0x178>
+    313a:	2300      	movs	r3, #0
+    313c:	4698      	mov	r8, r3
+    313e:	3302      	adds	r3, #2
+    3140:	2608      	movs	r6, #8
+    3142:	9303      	str	r3, [sp, #12]
+    3144:	e7ce      	b.n	30e4 <__aeabi_ddiv+0x48>
+    3146:	46cb      	mov	fp, r9
+    3148:	4641      	mov	r1, r8
+    314a:	9a03      	ldr	r2, [sp, #12]
+    314c:	9701      	str	r7, [sp, #4]
+    314e:	2a02      	cmp	r2, #2
+    3150:	d165      	bne.n	321e <__aeabi_ddiv+0x182>
+    3152:	9b01      	ldr	r3, [sp, #4]
+    3154:	4c4a      	ldr	r4, [pc, #296]	; (3280 <__aeabi_ddiv+0x1e4>)
+    3156:	469c      	mov	ip, r3
+    3158:	2300      	movs	r3, #0
+    315a:	2200      	movs	r2, #0
+    315c:	4698      	mov	r8, r3
+    315e:	e06b      	b.n	3238 <__aeabi_ddiv+0x19c>
+    3160:	0003      	movs	r3, r0
+    3162:	4333      	orrs	r3, r6
+    3164:	4699      	mov	r9, r3
+    3166:	d04e      	beq.n	3206 <__aeabi_ddiv+0x16a>
+    3168:	2e00      	cmp	r6, #0
+    316a:	d100      	bne.n	316e <__aeabi_ddiv+0xd2>
+    316c:	e1bc      	b.n	34e8 <__aeabi_ddiv+0x44c>
+    316e:	0030      	movs	r0, r6
+    3170:	f001 fb08 	bl	4784 <__clzsi2>
+    3174:	0003      	movs	r3, r0
+    3176:	3b0b      	subs	r3, #11
+    3178:	2b1c      	cmp	r3, #28
+    317a:	dd00      	ble.n	317e <__aeabi_ddiv+0xe2>
+    317c:	e1ac      	b.n	34d8 <__aeabi_ddiv+0x43c>
+    317e:	221d      	movs	r2, #29
+    3180:	1ad3      	subs	r3, r2, r3
+    3182:	465a      	mov	r2, fp
+    3184:	0001      	movs	r1, r0
+    3186:	40da      	lsrs	r2, r3
+    3188:	3908      	subs	r1, #8
+    318a:	408e      	lsls	r6, r1
+    318c:	0013      	movs	r3, r2
+    318e:	4333      	orrs	r3, r6
+    3190:	4699      	mov	r9, r3
+    3192:	465b      	mov	r3, fp
+    3194:	408b      	lsls	r3, r1
+    3196:	4698      	mov	r8, r3
+    3198:	2300      	movs	r3, #0
+    319a:	4c3c      	ldr	r4, [pc, #240]	; (328c <__aeabi_ddiv+0x1f0>)
+    319c:	2600      	movs	r6, #0
+    319e:	1a24      	subs	r4, r4, r0
+    31a0:	9303      	str	r3, [sp, #12]
+    31a2:	e79f      	b.n	30e4 <__aeabi_ddiv+0x48>
+    31a4:	4651      	mov	r1, sl
+    31a6:	465a      	mov	r2, fp
+    31a8:	4311      	orrs	r1, r2
+    31aa:	d129      	bne.n	3200 <__aeabi_ddiv+0x164>
+    31ac:	2200      	movs	r2, #0
+    31ae:	4693      	mov	fp, r2
+    31b0:	3202      	adds	r2, #2
+    31b2:	e7b1      	b.n	3118 <__aeabi_ddiv+0x7c>
+    31b4:	4659      	mov	r1, fp
+    31b6:	4301      	orrs	r1, r0
+    31b8:	d01e      	beq.n	31f8 <__aeabi_ddiv+0x15c>
+    31ba:	465b      	mov	r3, fp
+    31bc:	2b00      	cmp	r3, #0
+    31be:	d100      	bne.n	31c2 <__aeabi_ddiv+0x126>
+    31c0:	e19e      	b.n	3500 <__aeabi_ddiv+0x464>
+    31c2:	4658      	mov	r0, fp
+    31c4:	f001 fade 	bl	4784 <__clzsi2>
+    31c8:	0003      	movs	r3, r0
+    31ca:	3b0b      	subs	r3, #11
+    31cc:	2b1c      	cmp	r3, #28
+    31ce:	dd00      	ble.n	31d2 <__aeabi_ddiv+0x136>
+    31d0:	e18f      	b.n	34f2 <__aeabi_ddiv+0x456>
+    31d2:	0002      	movs	r2, r0
+    31d4:	4659      	mov	r1, fp
+    31d6:	3a08      	subs	r2, #8
+    31d8:	4091      	lsls	r1, r2
+    31da:	468b      	mov	fp, r1
+    31dc:	211d      	movs	r1, #29
+    31de:	1acb      	subs	r3, r1, r3
+    31e0:	4651      	mov	r1, sl
+    31e2:	40d9      	lsrs	r1, r3
+    31e4:	000b      	movs	r3, r1
+    31e6:	4659      	mov	r1, fp
+    31e8:	430b      	orrs	r3, r1
+    31ea:	4651      	mov	r1, sl
+    31ec:	469b      	mov	fp, r3
+    31ee:	4091      	lsls	r1, r2
+    31f0:	4b26      	ldr	r3, [pc, #152]	; (328c <__aeabi_ddiv+0x1f0>)
+    31f2:	2200      	movs	r2, #0
+    31f4:	1a1b      	subs	r3, r3, r0
+    31f6:	e78f      	b.n	3118 <__aeabi_ddiv+0x7c>
+    31f8:	2300      	movs	r3, #0
+    31fa:	2201      	movs	r2, #1
+    31fc:	469b      	mov	fp, r3
+    31fe:	e78b      	b.n	3118 <__aeabi_ddiv+0x7c>
+    3200:	4651      	mov	r1, sl
+    3202:	2203      	movs	r2, #3
+    3204:	e788      	b.n	3118 <__aeabi_ddiv+0x7c>
+    3206:	2300      	movs	r3, #0
+    3208:	4698      	mov	r8, r3
+    320a:	3301      	adds	r3, #1
+    320c:	2604      	movs	r6, #4
+    320e:	2400      	movs	r4, #0
+    3210:	9303      	str	r3, [sp, #12]
+    3212:	e767      	b.n	30e4 <__aeabi_ddiv+0x48>
+    3214:	2303      	movs	r3, #3
+    3216:	46b1      	mov	r9, r6
+    3218:	9303      	str	r3, [sp, #12]
+    321a:	260c      	movs	r6, #12
+    321c:	e762      	b.n	30e4 <__aeabi_ddiv+0x48>
+    321e:	2a03      	cmp	r2, #3
+    3220:	d100      	bne.n	3224 <__aeabi_ddiv+0x188>
+    3222:	e25c      	b.n	36de <__aeabi_ddiv+0x642>
+    3224:	9b01      	ldr	r3, [sp, #4]
+    3226:	2a01      	cmp	r2, #1
+    3228:	d000      	beq.n	322c <__aeabi_ddiv+0x190>
+    322a:	e1e4      	b.n	35f6 <__aeabi_ddiv+0x55a>
+    322c:	4013      	ands	r3, r2
+    322e:	469c      	mov	ip, r3
+    3230:	2300      	movs	r3, #0
+    3232:	2400      	movs	r4, #0
+    3234:	2200      	movs	r2, #0
+    3236:	4698      	mov	r8, r3
+    3238:	2100      	movs	r1, #0
+    323a:	0312      	lsls	r2, r2, #12
+    323c:	0b13      	lsrs	r3, r2, #12
+    323e:	0d0a      	lsrs	r2, r1, #20
+    3240:	0512      	lsls	r2, r2, #20
+    3242:	431a      	orrs	r2, r3
+    3244:	0523      	lsls	r3, r4, #20
+    3246:	4c12      	ldr	r4, [pc, #72]	; (3290 <__aeabi_ddiv+0x1f4>)
+    3248:	4640      	mov	r0, r8
+    324a:	4022      	ands	r2, r4
+    324c:	4313      	orrs	r3, r2
+    324e:	4662      	mov	r2, ip
+    3250:	005b      	lsls	r3, r3, #1
+    3252:	07d2      	lsls	r2, r2, #31
+    3254:	085b      	lsrs	r3, r3, #1
+    3256:	4313      	orrs	r3, r2
+    3258:	0019      	movs	r1, r3
+    325a:	b007      	add	sp, #28
+    325c:	bc3c      	pop	{r2, r3, r4, r5}
+    325e:	4690      	mov	r8, r2
+    3260:	4699      	mov	r9, r3
+    3262:	46a2      	mov	sl, r4
+    3264:	46ab      	mov	fp, r5
+    3266:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    3268:	2300      	movs	r3, #0
+    326a:	2280      	movs	r2, #128	; 0x80
+    326c:	469c      	mov	ip, r3
+    326e:	0312      	lsls	r2, r2, #12
+    3270:	4698      	mov	r8, r3
+    3272:	4c03      	ldr	r4, [pc, #12]	; (3280 <__aeabi_ddiv+0x1e4>)
+    3274:	e7e0      	b.n	3238 <__aeabi_ddiv+0x19c>
+    3276:	2300      	movs	r3, #0
+    3278:	4c01      	ldr	r4, [pc, #4]	; (3280 <__aeabi_ddiv+0x1e4>)
+    327a:	2200      	movs	r2, #0
+    327c:	4698      	mov	r8, r3
+    327e:	e7db      	b.n	3238 <__aeabi_ddiv+0x19c>
+    3280:	000007ff 	.word	0x000007ff
+    3284:	fffffc01 	.word	0xfffffc01
+    3288:	00005a1c 	.word	0x00005a1c
+    328c:	fffffc0d 	.word	0xfffffc0d
+    3290:	800fffff 	.word	0x800fffff
+    3294:	45d9      	cmp	r9, fp
+    3296:	d900      	bls.n	329a <__aeabi_ddiv+0x1fe>
+    3298:	e139      	b.n	350e <__aeabi_ddiv+0x472>
+    329a:	d100      	bne.n	329e <__aeabi_ddiv+0x202>
+    329c:	e134      	b.n	3508 <__aeabi_ddiv+0x46c>
+    329e:	2300      	movs	r3, #0
+    32a0:	4646      	mov	r6, r8
+    32a2:	464d      	mov	r5, r9
+    32a4:	469a      	mov	sl, r3
+    32a6:	3c01      	subs	r4, #1
+    32a8:	465b      	mov	r3, fp
+    32aa:	0e0a      	lsrs	r2, r1, #24
+    32ac:	021b      	lsls	r3, r3, #8
+    32ae:	431a      	orrs	r2, r3
+    32b0:	020b      	lsls	r3, r1, #8
+    32b2:	0c17      	lsrs	r7, r2, #16
+    32b4:	9303      	str	r3, [sp, #12]
+    32b6:	0413      	lsls	r3, r2, #16
+    32b8:	0c1b      	lsrs	r3, r3, #16
+    32ba:	0039      	movs	r1, r7
+    32bc:	0028      	movs	r0, r5
+    32be:	4690      	mov	r8, r2
+    32c0:	9301      	str	r3, [sp, #4]
+    32c2:	f7fe ff4b 	bl	215c <__udivsi3>
+    32c6:	0002      	movs	r2, r0
+    32c8:	9b01      	ldr	r3, [sp, #4]
+    32ca:	4683      	mov	fp, r0
+    32cc:	435a      	muls	r2, r3
+    32ce:	0028      	movs	r0, r5
+    32d0:	0039      	movs	r1, r7
+    32d2:	4691      	mov	r9, r2
+    32d4:	f7fe ffc8 	bl	2268 <__aeabi_uidivmod>
+    32d8:	0c35      	lsrs	r5, r6, #16
+    32da:	0409      	lsls	r1, r1, #16
+    32dc:	430d      	orrs	r5, r1
+    32de:	45a9      	cmp	r9, r5
+    32e0:	d90d      	bls.n	32fe <__aeabi_ddiv+0x262>
+    32e2:	465b      	mov	r3, fp
+    32e4:	4445      	add	r5, r8
+    32e6:	3b01      	subs	r3, #1
+    32e8:	45a8      	cmp	r8, r5
+    32ea:	d900      	bls.n	32ee <__aeabi_ddiv+0x252>
+    32ec:	e13a      	b.n	3564 <__aeabi_ddiv+0x4c8>
+    32ee:	45a9      	cmp	r9, r5
+    32f0:	d800      	bhi.n	32f4 <__aeabi_ddiv+0x258>
+    32f2:	e137      	b.n	3564 <__aeabi_ddiv+0x4c8>
+    32f4:	2302      	movs	r3, #2
+    32f6:	425b      	negs	r3, r3
+    32f8:	469c      	mov	ip, r3
+    32fa:	4445      	add	r5, r8
+    32fc:	44e3      	add	fp, ip
+    32fe:	464b      	mov	r3, r9
+    3300:	1aeb      	subs	r3, r5, r3
+    3302:	0039      	movs	r1, r7
+    3304:	0018      	movs	r0, r3
+    3306:	9304      	str	r3, [sp, #16]
+    3308:	f7fe ff28 	bl	215c <__udivsi3>
+    330c:	9b01      	ldr	r3, [sp, #4]
+    330e:	0005      	movs	r5, r0
+    3310:	4343      	muls	r3, r0
+    3312:	0039      	movs	r1, r7
+    3314:	9804      	ldr	r0, [sp, #16]
+    3316:	4699      	mov	r9, r3
+    3318:	f7fe ffa6 	bl	2268 <__aeabi_uidivmod>
+    331c:	0433      	lsls	r3, r6, #16
+    331e:	0409      	lsls	r1, r1, #16
+    3320:	0c1b      	lsrs	r3, r3, #16
+    3322:	430b      	orrs	r3, r1
+    3324:	4599      	cmp	r9, r3
+    3326:	d909      	bls.n	333c <__aeabi_ddiv+0x2a0>
+    3328:	4443      	add	r3, r8
+    332a:	1e6a      	subs	r2, r5, #1
+    332c:	4598      	cmp	r8, r3
+    332e:	d900      	bls.n	3332 <__aeabi_ddiv+0x296>
+    3330:	e11a      	b.n	3568 <__aeabi_ddiv+0x4cc>
+    3332:	4599      	cmp	r9, r3
+    3334:	d800      	bhi.n	3338 <__aeabi_ddiv+0x29c>
+    3336:	e117      	b.n	3568 <__aeabi_ddiv+0x4cc>
+    3338:	3d02      	subs	r5, #2
+    333a:	4443      	add	r3, r8
+    333c:	464a      	mov	r2, r9
+    333e:	1a9b      	subs	r3, r3, r2
+    3340:	465a      	mov	r2, fp
+    3342:	0412      	lsls	r2, r2, #16
+    3344:	432a      	orrs	r2, r5
+    3346:	9903      	ldr	r1, [sp, #12]
+    3348:	4693      	mov	fp, r2
+    334a:	0c10      	lsrs	r0, r2, #16
+    334c:	0c0a      	lsrs	r2, r1, #16
+    334e:	4691      	mov	r9, r2
+    3350:	0409      	lsls	r1, r1, #16
+    3352:	465a      	mov	r2, fp
+    3354:	0c09      	lsrs	r1, r1, #16
+    3356:	464e      	mov	r6, r9
+    3358:	000d      	movs	r5, r1
+    335a:	0412      	lsls	r2, r2, #16
+    335c:	0c12      	lsrs	r2, r2, #16
+    335e:	4345      	muls	r5, r0
+    3360:	9105      	str	r1, [sp, #20]
+    3362:	4351      	muls	r1, r2
+    3364:	4372      	muls	r2, r6
+    3366:	4370      	muls	r0, r6
+    3368:	1952      	adds	r2, r2, r5
+    336a:	0c0e      	lsrs	r6, r1, #16
+    336c:	18b2      	adds	r2, r6, r2
+    336e:	4295      	cmp	r5, r2
+    3370:	d903      	bls.n	337a <__aeabi_ddiv+0x2de>
+    3372:	2580      	movs	r5, #128	; 0x80
+    3374:	026d      	lsls	r5, r5, #9
+    3376:	46ac      	mov	ip, r5
+    3378:	4460      	add	r0, ip
+    337a:	0c15      	lsrs	r5, r2, #16
+    337c:	0409      	lsls	r1, r1, #16
+    337e:	0412      	lsls	r2, r2, #16
+    3380:	0c09      	lsrs	r1, r1, #16
+    3382:	1828      	adds	r0, r5, r0
+    3384:	1852      	adds	r2, r2, r1
+    3386:	4283      	cmp	r3, r0
+    3388:	d200      	bcs.n	338c <__aeabi_ddiv+0x2f0>
+    338a:	e0ce      	b.n	352a <__aeabi_ddiv+0x48e>
+    338c:	d100      	bne.n	3390 <__aeabi_ddiv+0x2f4>
+    338e:	e0c8      	b.n	3522 <__aeabi_ddiv+0x486>
+    3390:	1a1d      	subs	r5, r3, r0
+    3392:	4653      	mov	r3, sl
+    3394:	1a9e      	subs	r6, r3, r2
+    3396:	45b2      	cmp	sl, r6
+    3398:	4192      	sbcs	r2, r2
+    339a:	4252      	negs	r2, r2
+    339c:	1aab      	subs	r3, r5, r2
+    339e:	469a      	mov	sl, r3
+    33a0:	4598      	cmp	r8, r3
+    33a2:	d100      	bne.n	33a6 <__aeabi_ddiv+0x30a>
+    33a4:	e117      	b.n	35d6 <__aeabi_ddiv+0x53a>
+    33a6:	0039      	movs	r1, r7
+    33a8:	0018      	movs	r0, r3
+    33aa:	f7fe fed7 	bl	215c <__udivsi3>
+    33ae:	9b01      	ldr	r3, [sp, #4]
+    33b0:	0005      	movs	r5, r0
+    33b2:	4343      	muls	r3, r0
+    33b4:	0039      	movs	r1, r7
+    33b6:	4650      	mov	r0, sl
+    33b8:	9304      	str	r3, [sp, #16]
+    33ba:	f7fe ff55 	bl	2268 <__aeabi_uidivmod>
+    33be:	9804      	ldr	r0, [sp, #16]
+    33c0:	040b      	lsls	r3, r1, #16
+    33c2:	0c31      	lsrs	r1, r6, #16
+    33c4:	4319      	orrs	r1, r3
+    33c6:	4288      	cmp	r0, r1
+    33c8:	d909      	bls.n	33de <__aeabi_ddiv+0x342>
+    33ca:	4441      	add	r1, r8
+    33cc:	1e6b      	subs	r3, r5, #1
+    33ce:	4588      	cmp	r8, r1
+    33d0:	d900      	bls.n	33d4 <__aeabi_ddiv+0x338>
+    33d2:	e107      	b.n	35e4 <__aeabi_ddiv+0x548>
+    33d4:	4288      	cmp	r0, r1
+    33d6:	d800      	bhi.n	33da <__aeabi_ddiv+0x33e>
+    33d8:	e104      	b.n	35e4 <__aeabi_ddiv+0x548>
+    33da:	3d02      	subs	r5, #2
+    33dc:	4441      	add	r1, r8
+    33de:	9b04      	ldr	r3, [sp, #16]
+    33e0:	1acb      	subs	r3, r1, r3
+    33e2:	0018      	movs	r0, r3
+    33e4:	0039      	movs	r1, r7
+    33e6:	9304      	str	r3, [sp, #16]
+    33e8:	f7fe feb8 	bl	215c <__udivsi3>
+    33ec:	9b01      	ldr	r3, [sp, #4]
+    33ee:	4682      	mov	sl, r0
+    33f0:	4343      	muls	r3, r0
+    33f2:	0039      	movs	r1, r7
+    33f4:	9804      	ldr	r0, [sp, #16]
+    33f6:	9301      	str	r3, [sp, #4]
+    33f8:	f7fe ff36 	bl	2268 <__aeabi_uidivmod>
+    33fc:	9801      	ldr	r0, [sp, #4]
+    33fe:	040b      	lsls	r3, r1, #16
+    3400:	0431      	lsls	r1, r6, #16
+    3402:	0c09      	lsrs	r1, r1, #16
+    3404:	4319      	orrs	r1, r3
+    3406:	4288      	cmp	r0, r1
+    3408:	d90d      	bls.n	3426 <__aeabi_ddiv+0x38a>
+    340a:	4653      	mov	r3, sl
+    340c:	4441      	add	r1, r8
+    340e:	3b01      	subs	r3, #1
+    3410:	4588      	cmp	r8, r1
+    3412:	d900      	bls.n	3416 <__aeabi_ddiv+0x37a>
+    3414:	e0e8      	b.n	35e8 <__aeabi_ddiv+0x54c>
+    3416:	4288      	cmp	r0, r1
+    3418:	d800      	bhi.n	341c <__aeabi_ddiv+0x380>
+    341a:	e0e5      	b.n	35e8 <__aeabi_ddiv+0x54c>
+    341c:	2302      	movs	r3, #2
+    341e:	425b      	negs	r3, r3
+    3420:	469c      	mov	ip, r3
+    3422:	4441      	add	r1, r8
+    3424:	44e2      	add	sl, ip
+    3426:	9b01      	ldr	r3, [sp, #4]
+    3428:	042d      	lsls	r5, r5, #16
+    342a:	1ace      	subs	r6, r1, r3
+    342c:	4651      	mov	r1, sl
+    342e:	4329      	orrs	r1, r5
+    3430:	9d05      	ldr	r5, [sp, #20]
+    3432:	464f      	mov	r7, r9
+    3434:	002a      	movs	r2, r5
+    3436:	040b      	lsls	r3, r1, #16
+    3438:	0c08      	lsrs	r0, r1, #16
+    343a:	0c1b      	lsrs	r3, r3, #16
+    343c:	435a      	muls	r2, r3
+    343e:	4345      	muls	r5, r0
+    3440:	437b      	muls	r3, r7
+    3442:	4378      	muls	r0, r7
+    3444:	195b      	adds	r3, r3, r5
+    3446:	0c17      	lsrs	r7, r2, #16
+    3448:	18fb      	adds	r3, r7, r3
+    344a:	429d      	cmp	r5, r3
+    344c:	d903      	bls.n	3456 <__aeabi_ddiv+0x3ba>
+    344e:	2580      	movs	r5, #128	; 0x80
+    3450:	026d      	lsls	r5, r5, #9
+    3452:	46ac      	mov	ip, r5
+    3454:	4460      	add	r0, ip
+    3456:	0c1d      	lsrs	r5, r3, #16
+    3458:	0412      	lsls	r2, r2, #16
+    345a:	041b      	lsls	r3, r3, #16
+    345c:	0c12      	lsrs	r2, r2, #16
+    345e:	1828      	adds	r0, r5, r0
+    3460:	189b      	adds	r3, r3, r2
+    3462:	4286      	cmp	r6, r0
+    3464:	d200      	bcs.n	3468 <__aeabi_ddiv+0x3cc>
+    3466:	e093      	b.n	3590 <__aeabi_ddiv+0x4f4>
+    3468:	d100      	bne.n	346c <__aeabi_ddiv+0x3d0>
+    346a:	e08e      	b.n	358a <__aeabi_ddiv+0x4ee>
+    346c:	2301      	movs	r3, #1
+    346e:	4319      	orrs	r1, r3
+    3470:	4ba0      	ldr	r3, [pc, #640]	; (36f4 <__aeabi_ddiv+0x658>)
+    3472:	18e3      	adds	r3, r4, r3
+    3474:	2b00      	cmp	r3, #0
+    3476:	dc00      	bgt.n	347a <__aeabi_ddiv+0x3de>
+    3478:	e099      	b.n	35ae <__aeabi_ddiv+0x512>
+    347a:	074a      	lsls	r2, r1, #29
+    347c:	d000      	beq.n	3480 <__aeabi_ddiv+0x3e4>
+    347e:	e09e      	b.n	35be <__aeabi_ddiv+0x522>
+    3480:	465a      	mov	r2, fp
+    3482:	01d2      	lsls	r2, r2, #7
+    3484:	d506      	bpl.n	3494 <__aeabi_ddiv+0x3f8>
+    3486:	465a      	mov	r2, fp
+    3488:	4b9b      	ldr	r3, [pc, #620]	; (36f8 <__aeabi_ddiv+0x65c>)
+    348a:	401a      	ands	r2, r3
+    348c:	2380      	movs	r3, #128	; 0x80
+    348e:	4693      	mov	fp, r2
+    3490:	00db      	lsls	r3, r3, #3
+    3492:	18e3      	adds	r3, r4, r3
+    3494:	4a99      	ldr	r2, [pc, #612]	; (36fc <__aeabi_ddiv+0x660>)
+    3496:	4293      	cmp	r3, r2
+    3498:	dd68      	ble.n	356c <__aeabi_ddiv+0x4d0>
+    349a:	2301      	movs	r3, #1
+    349c:	9a02      	ldr	r2, [sp, #8]
+    349e:	4c98      	ldr	r4, [pc, #608]	; (3700 <__aeabi_ddiv+0x664>)
+    34a0:	401a      	ands	r2, r3
+    34a2:	2300      	movs	r3, #0
+    34a4:	4694      	mov	ip, r2
+    34a6:	4698      	mov	r8, r3
+    34a8:	2200      	movs	r2, #0
+    34aa:	e6c5      	b.n	3238 <__aeabi_ddiv+0x19c>
+    34ac:	2280      	movs	r2, #128	; 0x80
+    34ae:	464b      	mov	r3, r9
+    34b0:	0312      	lsls	r2, r2, #12
+    34b2:	4213      	tst	r3, r2
+    34b4:	d00a      	beq.n	34cc <__aeabi_ddiv+0x430>
+    34b6:	465b      	mov	r3, fp
+    34b8:	4213      	tst	r3, r2
+    34ba:	d106      	bne.n	34ca <__aeabi_ddiv+0x42e>
+    34bc:	431a      	orrs	r2, r3
+    34be:	0312      	lsls	r2, r2, #12
+    34c0:	0b12      	lsrs	r2, r2, #12
+    34c2:	46ac      	mov	ip, r5
+    34c4:	4688      	mov	r8, r1
+    34c6:	4c8e      	ldr	r4, [pc, #568]	; (3700 <__aeabi_ddiv+0x664>)
+    34c8:	e6b6      	b.n	3238 <__aeabi_ddiv+0x19c>
+    34ca:	464b      	mov	r3, r9
+    34cc:	431a      	orrs	r2, r3
+    34ce:	0312      	lsls	r2, r2, #12
+    34d0:	0b12      	lsrs	r2, r2, #12
+    34d2:	46bc      	mov	ip, r7
+    34d4:	4c8a      	ldr	r4, [pc, #552]	; (3700 <__aeabi_ddiv+0x664>)
+    34d6:	e6af      	b.n	3238 <__aeabi_ddiv+0x19c>
+    34d8:	0003      	movs	r3, r0
+    34da:	465a      	mov	r2, fp
+    34dc:	3b28      	subs	r3, #40	; 0x28
+    34de:	409a      	lsls	r2, r3
+    34e0:	2300      	movs	r3, #0
+    34e2:	4691      	mov	r9, r2
+    34e4:	4698      	mov	r8, r3
+    34e6:	e657      	b.n	3198 <__aeabi_ddiv+0xfc>
+    34e8:	4658      	mov	r0, fp
+    34ea:	f001 f94b 	bl	4784 <__clzsi2>
+    34ee:	3020      	adds	r0, #32
+    34f0:	e640      	b.n	3174 <__aeabi_ddiv+0xd8>
+    34f2:	0003      	movs	r3, r0
+    34f4:	4652      	mov	r2, sl
+    34f6:	3b28      	subs	r3, #40	; 0x28
+    34f8:	409a      	lsls	r2, r3
+    34fa:	2100      	movs	r1, #0
+    34fc:	4693      	mov	fp, r2
+    34fe:	e677      	b.n	31f0 <__aeabi_ddiv+0x154>
+    3500:	f001 f940 	bl	4784 <__clzsi2>
+    3504:	3020      	adds	r0, #32
+    3506:	e65f      	b.n	31c8 <__aeabi_ddiv+0x12c>
+    3508:	4588      	cmp	r8, r1
+    350a:	d200      	bcs.n	350e <__aeabi_ddiv+0x472>
+    350c:	e6c7      	b.n	329e <__aeabi_ddiv+0x202>
+    350e:	464b      	mov	r3, r9
+    3510:	07de      	lsls	r6, r3, #31
+    3512:	085d      	lsrs	r5, r3, #1
+    3514:	4643      	mov	r3, r8
+    3516:	085b      	lsrs	r3, r3, #1
+    3518:	431e      	orrs	r6, r3
+    351a:	4643      	mov	r3, r8
+    351c:	07db      	lsls	r3, r3, #31
+    351e:	469a      	mov	sl, r3
+    3520:	e6c2      	b.n	32a8 <__aeabi_ddiv+0x20c>
+    3522:	2500      	movs	r5, #0
+    3524:	4592      	cmp	sl, r2
+    3526:	d300      	bcc.n	352a <__aeabi_ddiv+0x48e>
+    3528:	e733      	b.n	3392 <__aeabi_ddiv+0x2f6>
+    352a:	9e03      	ldr	r6, [sp, #12]
+    352c:	4659      	mov	r1, fp
+    352e:	46b4      	mov	ip, r6
+    3530:	44e2      	add	sl, ip
+    3532:	45b2      	cmp	sl, r6
+    3534:	41ad      	sbcs	r5, r5
+    3536:	426d      	negs	r5, r5
+    3538:	4445      	add	r5, r8
+    353a:	18eb      	adds	r3, r5, r3
+    353c:	3901      	subs	r1, #1
+    353e:	4598      	cmp	r8, r3
+    3540:	d207      	bcs.n	3552 <__aeabi_ddiv+0x4b6>
+    3542:	4298      	cmp	r0, r3
+    3544:	d900      	bls.n	3548 <__aeabi_ddiv+0x4ac>
+    3546:	e07f      	b.n	3648 <__aeabi_ddiv+0x5ac>
+    3548:	d100      	bne.n	354c <__aeabi_ddiv+0x4b0>
+    354a:	e0bc      	b.n	36c6 <__aeabi_ddiv+0x62a>
+    354c:	1a1d      	subs	r5, r3, r0
+    354e:	468b      	mov	fp, r1
+    3550:	e71f      	b.n	3392 <__aeabi_ddiv+0x2f6>
+    3552:	4598      	cmp	r8, r3
+    3554:	d1fa      	bne.n	354c <__aeabi_ddiv+0x4b0>
+    3556:	9d03      	ldr	r5, [sp, #12]
+    3558:	4555      	cmp	r5, sl
+    355a:	d9f2      	bls.n	3542 <__aeabi_ddiv+0x4a6>
+    355c:	4643      	mov	r3, r8
+    355e:	468b      	mov	fp, r1
+    3560:	1a1d      	subs	r5, r3, r0
+    3562:	e716      	b.n	3392 <__aeabi_ddiv+0x2f6>
+    3564:	469b      	mov	fp, r3
+    3566:	e6ca      	b.n	32fe <__aeabi_ddiv+0x262>
+    3568:	0015      	movs	r5, r2
+    356a:	e6e7      	b.n	333c <__aeabi_ddiv+0x2a0>
+    356c:	465a      	mov	r2, fp
+    356e:	08c9      	lsrs	r1, r1, #3
+    3570:	0752      	lsls	r2, r2, #29
+    3572:	430a      	orrs	r2, r1
+    3574:	055b      	lsls	r3, r3, #21
+    3576:	4690      	mov	r8, r2
+    3578:	0d5c      	lsrs	r4, r3, #21
+    357a:	465a      	mov	r2, fp
+    357c:	2301      	movs	r3, #1
+    357e:	9902      	ldr	r1, [sp, #8]
+    3580:	0252      	lsls	r2, r2, #9
+    3582:	4019      	ands	r1, r3
+    3584:	0b12      	lsrs	r2, r2, #12
+    3586:	468c      	mov	ip, r1
+    3588:	e656      	b.n	3238 <__aeabi_ddiv+0x19c>
+    358a:	2b00      	cmp	r3, #0
+    358c:	d100      	bne.n	3590 <__aeabi_ddiv+0x4f4>
+    358e:	e76f      	b.n	3470 <__aeabi_ddiv+0x3d4>
+    3590:	4446      	add	r6, r8
+    3592:	1e4a      	subs	r2, r1, #1
+    3594:	45b0      	cmp	r8, r6
+    3596:	d929      	bls.n	35ec <__aeabi_ddiv+0x550>
+    3598:	0011      	movs	r1, r2
+    359a:	4286      	cmp	r6, r0
+    359c:	d000      	beq.n	35a0 <__aeabi_ddiv+0x504>
+    359e:	e765      	b.n	346c <__aeabi_ddiv+0x3d0>
+    35a0:	9a03      	ldr	r2, [sp, #12]
+    35a2:	4293      	cmp	r3, r2
+    35a4:	d000      	beq.n	35a8 <__aeabi_ddiv+0x50c>
+    35a6:	e761      	b.n	346c <__aeabi_ddiv+0x3d0>
+    35a8:	e762      	b.n	3470 <__aeabi_ddiv+0x3d4>
+    35aa:	2101      	movs	r1, #1
+    35ac:	4249      	negs	r1, r1
+    35ae:	2001      	movs	r0, #1
+    35b0:	1ac2      	subs	r2, r0, r3
+    35b2:	2a38      	cmp	r2, #56	; 0x38
+    35b4:	dd21      	ble.n	35fa <__aeabi_ddiv+0x55e>
+    35b6:	9b02      	ldr	r3, [sp, #8]
+    35b8:	4003      	ands	r3, r0
+    35ba:	469c      	mov	ip, r3
+    35bc:	e638      	b.n	3230 <__aeabi_ddiv+0x194>
+    35be:	220f      	movs	r2, #15
+    35c0:	400a      	ands	r2, r1
+    35c2:	2a04      	cmp	r2, #4
+    35c4:	d100      	bne.n	35c8 <__aeabi_ddiv+0x52c>
+    35c6:	e75b      	b.n	3480 <__aeabi_ddiv+0x3e4>
+    35c8:	000a      	movs	r2, r1
+    35ca:	1d11      	adds	r1, r2, #4
+    35cc:	4291      	cmp	r1, r2
+    35ce:	4192      	sbcs	r2, r2
+    35d0:	4252      	negs	r2, r2
+    35d2:	4493      	add	fp, r2
+    35d4:	e754      	b.n	3480 <__aeabi_ddiv+0x3e4>
+    35d6:	4b47      	ldr	r3, [pc, #284]	; (36f4 <__aeabi_ddiv+0x658>)
+    35d8:	18e3      	adds	r3, r4, r3
+    35da:	2b00      	cmp	r3, #0
+    35dc:	dde5      	ble.n	35aa <__aeabi_ddiv+0x50e>
+    35de:	2201      	movs	r2, #1
+    35e0:	4252      	negs	r2, r2
+    35e2:	e7f2      	b.n	35ca <__aeabi_ddiv+0x52e>
+    35e4:	001d      	movs	r5, r3
+    35e6:	e6fa      	b.n	33de <__aeabi_ddiv+0x342>
+    35e8:	469a      	mov	sl, r3
+    35ea:	e71c      	b.n	3426 <__aeabi_ddiv+0x38a>
+    35ec:	42b0      	cmp	r0, r6
+    35ee:	d839      	bhi.n	3664 <__aeabi_ddiv+0x5c8>
+    35f0:	d06e      	beq.n	36d0 <__aeabi_ddiv+0x634>
+    35f2:	0011      	movs	r1, r2
+    35f4:	e73a      	b.n	346c <__aeabi_ddiv+0x3d0>
+    35f6:	9302      	str	r3, [sp, #8]
+    35f8:	e73a      	b.n	3470 <__aeabi_ddiv+0x3d4>
+    35fa:	2a1f      	cmp	r2, #31
+    35fc:	dc3c      	bgt.n	3678 <__aeabi_ddiv+0x5dc>
+    35fe:	2320      	movs	r3, #32
+    3600:	1a9b      	subs	r3, r3, r2
+    3602:	000c      	movs	r4, r1
+    3604:	4658      	mov	r0, fp
+    3606:	4099      	lsls	r1, r3
+    3608:	4098      	lsls	r0, r3
+    360a:	1e4b      	subs	r3, r1, #1
+    360c:	4199      	sbcs	r1, r3
+    360e:	465b      	mov	r3, fp
+    3610:	40d4      	lsrs	r4, r2
+    3612:	40d3      	lsrs	r3, r2
+    3614:	4320      	orrs	r0, r4
+    3616:	4308      	orrs	r0, r1
+    3618:	001a      	movs	r2, r3
+    361a:	0743      	lsls	r3, r0, #29
+    361c:	d009      	beq.n	3632 <__aeabi_ddiv+0x596>
+    361e:	230f      	movs	r3, #15
+    3620:	4003      	ands	r3, r0
+    3622:	2b04      	cmp	r3, #4
+    3624:	d005      	beq.n	3632 <__aeabi_ddiv+0x596>
+    3626:	0001      	movs	r1, r0
+    3628:	1d08      	adds	r0, r1, #4
+    362a:	4288      	cmp	r0, r1
+    362c:	419b      	sbcs	r3, r3
+    362e:	425b      	negs	r3, r3
+    3630:	18d2      	adds	r2, r2, r3
+    3632:	0213      	lsls	r3, r2, #8
+    3634:	d53a      	bpl.n	36ac <__aeabi_ddiv+0x610>
+    3636:	2301      	movs	r3, #1
+    3638:	9a02      	ldr	r2, [sp, #8]
+    363a:	2401      	movs	r4, #1
+    363c:	401a      	ands	r2, r3
+    363e:	2300      	movs	r3, #0
+    3640:	4694      	mov	ip, r2
+    3642:	4698      	mov	r8, r3
+    3644:	2200      	movs	r2, #0
+    3646:	e5f7      	b.n	3238 <__aeabi_ddiv+0x19c>
+    3648:	2102      	movs	r1, #2
+    364a:	4249      	negs	r1, r1
+    364c:	468c      	mov	ip, r1
+    364e:	9d03      	ldr	r5, [sp, #12]
+    3650:	44e3      	add	fp, ip
+    3652:	46ac      	mov	ip, r5
+    3654:	44e2      	add	sl, ip
+    3656:	45aa      	cmp	sl, r5
+    3658:	41ad      	sbcs	r5, r5
+    365a:	426d      	negs	r5, r5
+    365c:	4445      	add	r5, r8
+    365e:	18ed      	adds	r5, r5, r3
+    3660:	1a2d      	subs	r5, r5, r0
+    3662:	e696      	b.n	3392 <__aeabi_ddiv+0x2f6>
+    3664:	1e8a      	subs	r2, r1, #2
+    3666:	9903      	ldr	r1, [sp, #12]
+    3668:	004d      	lsls	r5, r1, #1
+    366a:	428d      	cmp	r5, r1
+    366c:	4189      	sbcs	r1, r1
+    366e:	4249      	negs	r1, r1
+    3670:	4441      	add	r1, r8
+    3672:	1876      	adds	r6, r6, r1
+    3674:	9503      	str	r5, [sp, #12]
+    3676:	e78f      	b.n	3598 <__aeabi_ddiv+0x4fc>
+    3678:	201f      	movs	r0, #31
+    367a:	4240      	negs	r0, r0
+    367c:	1ac3      	subs	r3, r0, r3
+    367e:	4658      	mov	r0, fp
+    3680:	40d8      	lsrs	r0, r3
+    3682:	0003      	movs	r3, r0
+    3684:	2a20      	cmp	r2, #32
+    3686:	d028      	beq.n	36da <__aeabi_ddiv+0x63e>
+    3688:	2040      	movs	r0, #64	; 0x40
+    368a:	465d      	mov	r5, fp
+    368c:	1a82      	subs	r2, r0, r2
+    368e:	4095      	lsls	r5, r2
+    3690:	4329      	orrs	r1, r5
+    3692:	1e4a      	subs	r2, r1, #1
+    3694:	4191      	sbcs	r1, r2
+    3696:	4319      	orrs	r1, r3
+    3698:	2307      	movs	r3, #7
+    369a:	2200      	movs	r2, #0
+    369c:	400b      	ands	r3, r1
+    369e:	d009      	beq.n	36b4 <__aeabi_ddiv+0x618>
+    36a0:	230f      	movs	r3, #15
+    36a2:	2200      	movs	r2, #0
+    36a4:	400b      	ands	r3, r1
+    36a6:	0008      	movs	r0, r1
+    36a8:	2b04      	cmp	r3, #4
+    36aa:	d1bd      	bne.n	3628 <__aeabi_ddiv+0x58c>
+    36ac:	0001      	movs	r1, r0
+    36ae:	0753      	lsls	r3, r2, #29
+    36b0:	0252      	lsls	r2, r2, #9
+    36b2:	0b12      	lsrs	r2, r2, #12
+    36b4:	08c9      	lsrs	r1, r1, #3
+    36b6:	4319      	orrs	r1, r3
+    36b8:	2301      	movs	r3, #1
+    36ba:	4688      	mov	r8, r1
+    36bc:	9902      	ldr	r1, [sp, #8]
+    36be:	2400      	movs	r4, #0
+    36c0:	4019      	ands	r1, r3
+    36c2:	468c      	mov	ip, r1
+    36c4:	e5b8      	b.n	3238 <__aeabi_ddiv+0x19c>
+    36c6:	4552      	cmp	r2, sl
+    36c8:	d8be      	bhi.n	3648 <__aeabi_ddiv+0x5ac>
+    36ca:	468b      	mov	fp, r1
+    36cc:	2500      	movs	r5, #0
+    36ce:	e660      	b.n	3392 <__aeabi_ddiv+0x2f6>
+    36d0:	9d03      	ldr	r5, [sp, #12]
+    36d2:	429d      	cmp	r5, r3
+    36d4:	d3c6      	bcc.n	3664 <__aeabi_ddiv+0x5c8>
+    36d6:	0011      	movs	r1, r2
+    36d8:	e762      	b.n	35a0 <__aeabi_ddiv+0x504>
+    36da:	2500      	movs	r5, #0
+    36dc:	e7d8      	b.n	3690 <__aeabi_ddiv+0x5f4>
+    36de:	2280      	movs	r2, #128	; 0x80
+    36e0:	465b      	mov	r3, fp
+    36e2:	0312      	lsls	r2, r2, #12
+    36e4:	431a      	orrs	r2, r3
+    36e6:	9b01      	ldr	r3, [sp, #4]
+    36e8:	0312      	lsls	r2, r2, #12
+    36ea:	0b12      	lsrs	r2, r2, #12
+    36ec:	469c      	mov	ip, r3
+    36ee:	4688      	mov	r8, r1
+    36f0:	4c03      	ldr	r4, [pc, #12]	; (3700 <__aeabi_ddiv+0x664>)
+    36f2:	e5a1      	b.n	3238 <__aeabi_ddiv+0x19c>
+    36f4:	000003ff 	.word	0x000003ff
+    36f8:	feffffff 	.word	0xfeffffff
+    36fc:	000007fe 	.word	0x000007fe
+    3700:	000007ff 	.word	0x000007ff
+
+00003704 <__eqdf2>:
+    3704:	b5f0      	push	{r4, r5, r6, r7, lr}
+    3706:	464f      	mov	r7, r9
+    3708:	4646      	mov	r6, r8
+    370a:	46d6      	mov	lr, sl
+    370c:	005c      	lsls	r4, r3, #1
+    370e:	b5c0      	push	{r6, r7, lr}
+    3710:	031f      	lsls	r7, r3, #12
+    3712:	0fdb      	lsrs	r3, r3, #31
+    3714:	469a      	mov	sl, r3
+    3716:	4b17      	ldr	r3, [pc, #92]	; (3774 <__eqdf2+0x70>)
+    3718:	030e      	lsls	r6, r1, #12
+    371a:	004d      	lsls	r5, r1, #1
+    371c:	4684      	mov	ip, r0
+    371e:	4680      	mov	r8, r0
+    3720:	0b36      	lsrs	r6, r6, #12
+    3722:	0d6d      	lsrs	r5, r5, #21
+    3724:	0fc9      	lsrs	r1, r1, #31
+    3726:	4691      	mov	r9, r2
+    3728:	0b3f      	lsrs	r7, r7, #12
+    372a:	0d64      	lsrs	r4, r4, #21
+    372c:	2001      	movs	r0, #1
+    372e:	429d      	cmp	r5, r3
+    3730:	d008      	beq.n	3744 <__eqdf2+0x40>
+    3732:	429c      	cmp	r4, r3
+    3734:	d001      	beq.n	373a <__eqdf2+0x36>
+    3736:	42a5      	cmp	r5, r4
+    3738:	d00b      	beq.n	3752 <__eqdf2+0x4e>
+    373a:	bc1c      	pop	{r2, r3, r4}
+    373c:	4690      	mov	r8, r2
+    373e:	4699      	mov	r9, r3
+    3740:	46a2      	mov	sl, r4
+    3742:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    3744:	4663      	mov	r3, ip
+    3746:	4333      	orrs	r3, r6
+    3748:	d1f7      	bne.n	373a <__eqdf2+0x36>
+    374a:	42ac      	cmp	r4, r5
+    374c:	d1f5      	bne.n	373a <__eqdf2+0x36>
+    374e:	433a      	orrs	r2, r7
+    3750:	d1f3      	bne.n	373a <__eqdf2+0x36>
+    3752:	2001      	movs	r0, #1
+    3754:	42be      	cmp	r6, r7
+    3756:	d1f0      	bne.n	373a <__eqdf2+0x36>
+    3758:	45c8      	cmp	r8, r9
+    375a:	d1ee      	bne.n	373a <__eqdf2+0x36>
+    375c:	4551      	cmp	r1, sl
+    375e:	d007      	beq.n	3770 <__eqdf2+0x6c>
+    3760:	2d00      	cmp	r5, #0
+    3762:	d1ea      	bne.n	373a <__eqdf2+0x36>
+    3764:	4663      	mov	r3, ip
+    3766:	431e      	orrs	r6, r3
+    3768:	0030      	movs	r0, r6
+    376a:	1e46      	subs	r6, r0, #1
+    376c:	41b0      	sbcs	r0, r6
+    376e:	e7e4      	b.n	373a <__eqdf2+0x36>
+    3770:	2000      	movs	r0, #0
+    3772:	e7e2      	b.n	373a <__eqdf2+0x36>
+    3774:	000007ff 	.word	0x000007ff
+
+00003778 <__gedf2>:
+    3778:	b5f0      	push	{r4, r5, r6, r7, lr}
+    377a:	4645      	mov	r5, r8
+    377c:	46de      	mov	lr, fp
+    377e:	4657      	mov	r7, sl
+    3780:	464e      	mov	r6, r9
+    3782:	b5e0      	push	{r5, r6, r7, lr}
+    3784:	031f      	lsls	r7, r3, #12
+    3786:	0b3d      	lsrs	r5, r7, #12
+    3788:	4f2c      	ldr	r7, [pc, #176]	; (383c <__gedf2+0xc4>)
+    378a:	030e      	lsls	r6, r1, #12
+    378c:	004c      	lsls	r4, r1, #1
+    378e:	46ab      	mov	fp, r5
+    3790:	005d      	lsls	r5, r3, #1
+    3792:	4684      	mov	ip, r0
+    3794:	0b36      	lsrs	r6, r6, #12
+    3796:	0d64      	lsrs	r4, r4, #21
+    3798:	0fc9      	lsrs	r1, r1, #31
+    379a:	4690      	mov	r8, r2
+    379c:	0d6d      	lsrs	r5, r5, #21
+    379e:	0fdb      	lsrs	r3, r3, #31
+    37a0:	42bc      	cmp	r4, r7
+    37a2:	d02a      	beq.n	37fa <__gedf2+0x82>
+    37a4:	4f25      	ldr	r7, [pc, #148]	; (383c <__gedf2+0xc4>)
+    37a6:	42bd      	cmp	r5, r7
+    37a8:	d02d      	beq.n	3806 <__gedf2+0x8e>
+    37aa:	2c00      	cmp	r4, #0
+    37ac:	d10f      	bne.n	37ce <__gedf2+0x56>
+    37ae:	4330      	orrs	r0, r6
+    37b0:	0007      	movs	r7, r0
+    37b2:	4681      	mov	r9, r0
+    37b4:	4278      	negs	r0, r7
+    37b6:	4178      	adcs	r0, r7
+    37b8:	b2c0      	uxtb	r0, r0
+    37ba:	2d00      	cmp	r5, #0
+    37bc:	d117      	bne.n	37ee <__gedf2+0x76>
+    37be:	465f      	mov	r7, fp
+    37c0:	433a      	orrs	r2, r7
+    37c2:	d114      	bne.n	37ee <__gedf2+0x76>
+    37c4:	464b      	mov	r3, r9
+    37c6:	2000      	movs	r0, #0
+    37c8:	2b00      	cmp	r3, #0
+    37ca:	d00a      	beq.n	37e2 <__gedf2+0x6a>
+    37cc:	e006      	b.n	37dc <__gedf2+0x64>
+    37ce:	2d00      	cmp	r5, #0
+    37d0:	d102      	bne.n	37d8 <__gedf2+0x60>
+    37d2:	4658      	mov	r0, fp
+    37d4:	4302      	orrs	r2, r0
+    37d6:	d001      	beq.n	37dc <__gedf2+0x64>
+    37d8:	4299      	cmp	r1, r3
+    37da:	d018      	beq.n	380e <__gedf2+0x96>
+    37dc:	4248      	negs	r0, r1
+    37de:	2101      	movs	r1, #1
+    37e0:	4308      	orrs	r0, r1
+    37e2:	bc3c      	pop	{r2, r3, r4, r5}
+    37e4:	4690      	mov	r8, r2
+    37e6:	4699      	mov	r9, r3
+    37e8:	46a2      	mov	sl, r4
+    37ea:	46ab      	mov	fp, r5
+    37ec:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    37ee:	2800      	cmp	r0, #0
+    37f0:	d0f2      	beq.n	37d8 <__gedf2+0x60>
+    37f2:	2001      	movs	r0, #1
+    37f4:	3b01      	subs	r3, #1
+    37f6:	4318      	orrs	r0, r3
+    37f8:	e7f3      	b.n	37e2 <__gedf2+0x6a>
+    37fa:	0037      	movs	r7, r6
+    37fc:	4307      	orrs	r7, r0
+    37fe:	d0d1      	beq.n	37a4 <__gedf2+0x2c>
+    3800:	2002      	movs	r0, #2
+    3802:	4240      	negs	r0, r0
+    3804:	e7ed      	b.n	37e2 <__gedf2+0x6a>
+    3806:	465f      	mov	r7, fp
+    3808:	4317      	orrs	r7, r2
+    380a:	d0ce      	beq.n	37aa <__gedf2+0x32>
+    380c:	e7f8      	b.n	3800 <__gedf2+0x88>
+    380e:	42ac      	cmp	r4, r5
+    3810:	dce4      	bgt.n	37dc <__gedf2+0x64>
+    3812:	da03      	bge.n	381c <__gedf2+0xa4>
+    3814:	1e48      	subs	r0, r1, #1
+    3816:	2101      	movs	r1, #1
+    3818:	4308      	orrs	r0, r1
+    381a:	e7e2      	b.n	37e2 <__gedf2+0x6a>
+    381c:	455e      	cmp	r6, fp
+    381e:	d8dd      	bhi.n	37dc <__gedf2+0x64>
+    3820:	d006      	beq.n	3830 <__gedf2+0xb8>
+    3822:	2000      	movs	r0, #0
+    3824:	455e      	cmp	r6, fp
+    3826:	d2dc      	bcs.n	37e2 <__gedf2+0x6a>
+    3828:	2301      	movs	r3, #1
+    382a:	1e48      	subs	r0, r1, #1
+    382c:	4318      	orrs	r0, r3
+    382e:	e7d8      	b.n	37e2 <__gedf2+0x6a>
+    3830:	45c4      	cmp	ip, r8
+    3832:	d8d3      	bhi.n	37dc <__gedf2+0x64>
+    3834:	2000      	movs	r0, #0
+    3836:	45c4      	cmp	ip, r8
+    3838:	d3f6      	bcc.n	3828 <__gedf2+0xb0>
+    383a:	e7d2      	b.n	37e2 <__gedf2+0x6a>
+    383c:	000007ff 	.word	0x000007ff
+
+00003840 <__ledf2>:
+    3840:	b5f0      	push	{r4, r5, r6, r7, lr}
+    3842:	464e      	mov	r6, r9
+    3844:	4645      	mov	r5, r8
+    3846:	46de      	mov	lr, fp
+    3848:	4657      	mov	r7, sl
+    384a:	005c      	lsls	r4, r3, #1
+    384c:	b5e0      	push	{r5, r6, r7, lr}
+    384e:	031f      	lsls	r7, r3, #12
+    3850:	0fdb      	lsrs	r3, r3, #31
+    3852:	4699      	mov	r9, r3
+    3854:	4b2a      	ldr	r3, [pc, #168]	; (3900 <__ledf2+0xc0>)
+    3856:	030e      	lsls	r6, r1, #12
+    3858:	004d      	lsls	r5, r1, #1
+    385a:	0fc9      	lsrs	r1, r1, #31
+    385c:	4684      	mov	ip, r0
+    385e:	0b36      	lsrs	r6, r6, #12
+    3860:	0d6d      	lsrs	r5, r5, #21
+    3862:	468b      	mov	fp, r1
+    3864:	4690      	mov	r8, r2
+    3866:	0b3f      	lsrs	r7, r7, #12
+    3868:	0d64      	lsrs	r4, r4, #21
+    386a:	429d      	cmp	r5, r3
+    386c:	d020      	beq.n	38b0 <__ledf2+0x70>
+    386e:	4b24      	ldr	r3, [pc, #144]	; (3900 <__ledf2+0xc0>)
+    3870:	429c      	cmp	r4, r3
+    3872:	d022      	beq.n	38ba <__ledf2+0x7a>
+    3874:	2d00      	cmp	r5, #0
+    3876:	d112      	bne.n	389e <__ledf2+0x5e>
+    3878:	4330      	orrs	r0, r6
+    387a:	4243      	negs	r3, r0
+    387c:	4143      	adcs	r3, r0
+    387e:	b2db      	uxtb	r3, r3
+    3880:	2c00      	cmp	r4, #0
+    3882:	d01f      	beq.n	38c4 <__ledf2+0x84>
+    3884:	2b00      	cmp	r3, #0
+    3886:	d00c      	beq.n	38a2 <__ledf2+0x62>
+    3888:	464b      	mov	r3, r9
+    388a:	2001      	movs	r0, #1
+    388c:	3b01      	subs	r3, #1
+    388e:	4303      	orrs	r3, r0
+    3890:	0018      	movs	r0, r3
+    3892:	bc3c      	pop	{r2, r3, r4, r5}
+    3894:	4690      	mov	r8, r2
+    3896:	4699      	mov	r9, r3
+    3898:	46a2      	mov	sl, r4
+    389a:	46ab      	mov	fp, r5
+    389c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    389e:	2c00      	cmp	r4, #0
+    38a0:	d016      	beq.n	38d0 <__ledf2+0x90>
+    38a2:	45cb      	cmp	fp, r9
+    38a4:	d017      	beq.n	38d6 <__ledf2+0x96>
+    38a6:	465b      	mov	r3, fp
+    38a8:	4259      	negs	r1, r3
+    38aa:	2301      	movs	r3, #1
+    38ac:	430b      	orrs	r3, r1
+    38ae:	e7ef      	b.n	3890 <__ledf2+0x50>
+    38b0:	0031      	movs	r1, r6
+    38b2:	2302      	movs	r3, #2
+    38b4:	4301      	orrs	r1, r0
+    38b6:	d1eb      	bne.n	3890 <__ledf2+0x50>
+    38b8:	e7d9      	b.n	386e <__ledf2+0x2e>
+    38ba:	0039      	movs	r1, r7
+    38bc:	2302      	movs	r3, #2
+    38be:	4311      	orrs	r1, r2
+    38c0:	d1e6      	bne.n	3890 <__ledf2+0x50>
+    38c2:	e7d7      	b.n	3874 <__ledf2+0x34>
+    38c4:	433a      	orrs	r2, r7
+    38c6:	d1dd      	bne.n	3884 <__ledf2+0x44>
+    38c8:	2300      	movs	r3, #0
+    38ca:	2800      	cmp	r0, #0
+    38cc:	d0e0      	beq.n	3890 <__ledf2+0x50>
+    38ce:	e7ea      	b.n	38a6 <__ledf2+0x66>
+    38d0:	433a      	orrs	r2, r7
+    38d2:	d1e6      	bne.n	38a2 <__ledf2+0x62>
+    38d4:	e7e7      	b.n	38a6 <__ledf2+0x66>
+    38d6:	42a5      	cmp	r5, r4
+    38d8:	dce5      	bgt.n	38a6 <__ledf2+0x66>
+    38da:	db05      	blt.n	38e8 <__ledf2+0xa8>
+    38dc:	42be      	cmp	r6, r7
+    38de:	d8e2      	bhi.n	38a6 <__ledf2+0x66>
+    38e0:	d007      	beq.n	38f2 <__ledf2+0xb2>
+    38e2:	2300      	movs	r3, #0
+    38e4:	42be      	cmp	r6, r7
+    38e6:	d2d3      	bcs.n	3890 <__ledf2+0x50>
+    38e8:	4659      	mov	r1, fp
+    38ea:	2301      	movs	r3, #1
+    38ec:	3901      	subs	r1, #1
+    38ee:	430b      	orrs	r3, r1
+    38f0:	e7ce      	b.n	3890 <__ledf2+0x50>
+    38f2:	45c4      	cmp	ip, r8
+    38f4:	d8d7      	bhi.n	38a6 <__ledf2+0x66>
+    38f6:	2300      	movs	r3, #0
+    38f8:	45c4      	cmp	ip, r8
+    38fa:	d3f5      	bcc.n	38e8 <__ledf2+0xa8>
+    38fc:	e7c8      	b.n	3890 <__ledf2+0x50>
+    38fe:	46c0      	nop			; (mov r8, r8)
+    3900:	000007ff 	.word	0x000007ff
+
+00003904 <__aeabi_dmul>:
+    3904:	b5f0      	push	{r4, r5, r6, r7, lr}
+    3906:	4657      	mov	r7, sl
+    3908:	4645      	mov	r5, r8
+    390a:	46de      	mov	lr, fp
+    390c:	464e      	mov	r6, r9
+    390e:	b5e0      	push	{r5, r6, r7, lr}
+    3910:	030c      	lsls	r4, r1, #12
+    3912:	4698      	mov	r8, r3
+    3914:	004e      	lsls	r6, r1, #1
+    3916:	0b23      	lsrs	r3, r4, #12
+    3918:	b087      	sub	sp, #28
+    391a:	0007      	movs	r7, r0
+    391c:	4692      	mov	sl, r2
+    391e:	469b      	mov	fp, r3
+    3920:	0d76      	lsrs	r6, r6, #21
+    3922:	0fcd      	lsrs	r5, r1, #31
+    3924:	2e00      	cmp	r6, #0
+    3926:	d06b      	beq.n	3a00 <__aeabi_dmul+0xfc>
+    3928:	4b6d      	ldr	r3, [pc, #436]	; (3ae0 <__aeabi_dmul+0x1dc>)
+    392a:	429e      	cmp	r6, r3
+    392c:	d035      	beq.n	399a <__aeabi_dmul+0x96>
+    392e:	2480      	movs	r4, #128	; 0x80
+    3930:	465b      	mov	r3, fp
+    3932:	0f42      	lsrs	r2, r0, #29
+    3934:	0424      	lsls	r4, r4, #16
+    3936:	00db      	lsls	r3, r3, #3
+    3938:	4314      	orrs	r4, r2
+    393a:	431c      	orrs	r4, r3
+    393c:	00c3      	lsls	r3, r0, #3
+    393e:	4699      	mov	r9, r3
+    3940:	4b68      	ldr	r3, [pc, #416]	; (3ae4 <__aeabi_dmul+0x1e0>)
+    3942:	46a3      	mov	fp, r4
+    3944:	469c      	mov	ip, r3
+    3946:	2300      	movs	r3, #0
+    3948:	2700      	movs	r7, #0
+    394a:	4466      	add	r6, ip
+    394c:	9302      	str	r3, [sp, #8]
+    394e:	4643      	mov	r3, r8
+    3950:	031c      	lsls	r4, r3, #12
+    3952:	005a      	lsls	r2, r3, #1
+    3954:	0fdb      	lsrs	r3, r3, #31
+    3956:	4650      	mov	r0, sl
+    3958:	0b24      	lsrs	r4, r4, #12
+    395a:	0d52      	lsrs	r2, r2, #21
+    395c:	4698      	mov	r8, r3
+    395e:	d100      	bne.n	3962 <__aeabi_dmul+0x5e>
+    3960:	e076      	b.n	3a50 <__aeabi_dmul+0x14c>
+    3962:	4b5f      	ldr	r3, [pc, #380]	; (3ae0 <__aeabi_dmul+0x1dc>)
+    3964:	429a      	cmp	r2, r3
+    3966:	d06d      	beq.n	3a44 <__aeabi_dmul+0x140>
+    3968:	2380      	movs	r3, #128	; 0x80
+    396a:	0f41      	lsrs	r1, r0, #29
+    396c:	041b      	lsls	r3, r3, #16
+    396e:	430b      	orrs	r3, r1
+    3970:	495c      	ldr	r1, [pc, #368]	; (3ae4 <__aeabi_dmul+0x1e0>)
+    3972:	00e4      	lsls	r4, r4, #3
+    3974:	468c      	mov	ip, r1
+    3976:	431c      	orrs	r4, r3
+    3978:	00c3      	lsls	r3, r0, #3
+    397a:	2000      	movs	r0, #0
+    397c:	4462      	add	r2, ip
+    397e:	4641      	mov	r1, r8
+    3980:	18b6      	adds	r6, r6, r2
+    3982:	4069      	eors	r1, r5
+    3984:	1c72      	adds	r2, r6, #1
+    3986:	9101      	str	r1, [sp, #4]
+    3988:	4694      	mov	ip, r2
+    398a:	4307      	orrs	r7, r0
+    398c:	2f0f      	cmp	r7, #15
+    398e:	d900      	bls.n	3992 <__aeabi_dmul+0x8e>
+    3990:	e0b0      	b.n	3af4 <__aeabi_dmul+0x1f0>
+    3992:	4a55      	ldr	r2, [pc, #340]	; (3ae8 <__aeabi_dmul+0x1e4>)
+    3994:	00bf      	lsls	r7, r7, #2
+    3996:	59d2      	ldr	r2, [r2, r7]
+    3998:	4697      	mov	pc, r2
+    399a:	465b      	mov	r3, fp
+    399c:	4303      	orrs	r3, r0
+    399e:	4699      	mov	r9, r3
+    39a0:	d000      	beq.n	39a4 <__aeabi_dmul+0xa0>
+    39a2:	e087      	b.n	3ab4 <__aeabi_dmul+0x1b0>
+    39a4:	2300      	movs	r3, #0
+    39a6:	469b      	mov	fp, r3
+    39a8:	3302      	adds	r3, #2
+    39aa:	2708      	movs	r7, #8
+    39ac:	9302      	str	r3, [sp, #8]
+    39ae:	e7ce      	b.n	394e <__aeabi_dmul+0x4a>
+    39b0:	4642      	mov	r2, r8
+    39b2:	9201      	str	r2, [sp, #4]
+    39b4:	2802      	cmp	r0, #2
+    39b6:	d067      	beq.n	3a88 <__aeabi_dmul+0x184>
+    39b8:	2803      	cmp	r0, #3
+    39ba:	d100      	bne.n	39be <__aeabi_dmul+0xba>
+    39bc:	e20e      	b.n	3ddc <__aeabi_dmul+0x4d8>
+    39be:	2801      	cmp	r0, #1
+    39c0:	d000      	beq.n	39c4 <__aeabi_dmul+0xc0>
+    39c2:	e162      	b.n	3c8a <__aeabi_dmul+0x386>
+    39c4:	2300      	movs	r3, #0
+    39c6:	2400      	movs	r4, #0
+    39c8:	2200      	movs	r2, #0
+    39ca:	4699      	mov	r9, r3
+    39cc:	9901      	ldr	r1, [sp, #4]
+    39ce:	4001      	ands	r1, r0
+    39d0:	b2cd      	uxtb	r5, r1
+    39d2:	2100      	movs	r1, #0
+    39d4:	0312      	lsls	r2, r2, #12
+    39d6:	0d0b      	lsrs	r3, r1, #20
+    39d8:	0b12      	lsrs	r2, r2, #12
+    39da:	051b      	lsls	r3, r3, #20
+    39dc:	4313      	orrs	r3, r2
+    39de:	4a43      	ldr	r2, [pc, #268]	; (3aec <__aeabi_dmul+0x1e8>)
+    39e0:	0524      	lsls	r4, r4, #20
+    39e2:	4013      	ands	r3, r2
+    39e4:	431c      	orrs	r4, r3
+    39e6:	0064      	lsls	r4, r4, #1
+    39e8:	07ed      	lsls	r5, r5, #31
+    39ea:	0864      	lsrs	r4, r4, #1
+    39ec:	432c      	orrs	r4, r5
+    39ee:	4648      	mov	r0, r9
+    39f0:	0021      	movs	r1, r4
+    39f2:	b007      	add	sp, #28
+    39f4:	bc3c      	pop	{r2, r3, r4, r5}
+    39f6:	4690      	mov	r8, r2
+    39f8:	4699      	mov	r9, r3
+    39fa:	46a2      	mov	sl, r4
+    39fc:	46ab      	mov	fp, r5
+    39fe:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    3a00:	4303      	orrs	r3, r0
+    3a02:	4699      	mov	r9, r3
+    3a04:	d04f      	beq.n	3aa6 <__aeabi_dmul+0x1a2>
+    3a06:	465b      	mov	r3, fp
+    3a08:	2b00      	cmp	r3, #0
+    3a0a:	d100      	bne.n	3a0e <__aeabi_dmul+0x10a>
+    3a0c:	e189      	b.n	3d22 <__aeabi_dmul+0x41e>
+    3a0e:	4658      	mov	r0, fp
+    3a10:	f000 feb8 	bl	4784 <__clzsi2>
+    3a14:	0003      	movs	r3, r0
+    3a16:	3b0b      	subs	r3, #11
+    3a18:	2b1c      	cmp	r3, #28
+    3a1a:	dd00      	ble.n	3a1e <__aeabi_dmul+0x11a>
+    3a1c:	e17a      	b.n	3d14 <__aeabi_dmul+0x410>
+    3a1e:	221d      	movs	r2, #29
+    3a20:	1ad3      	subs	r3, r2, r3
+    3a22:	003a      	movs	r2, r7
+    3a24:	0001      	movs	r1, r0
+    3a26:	465c      	mov	r4, fp
+    3a28:	40da      	lsrs	r2, r3
+    3a2a:	3908      	subs	r1, #8
+    3a2c:	408c      	lsls	r4, r1
+    3a2e:	0013      	movs	r3, r2
+    3a30:	408f      	lsls	r7, r1
+    3a32:	4323      	orrs	r3, r4
+    3a34:	469b      	mov	fp, r3
+    3a36:	46b9      	mov	r9, r7
+    3a38:	2300      	movs	r3, #0
+    3a3a:	4e2d      	ldr	r6, [pc, #180]	; (3af0 <__aeabi_dmul+0x1ec>)
+    3a3c:	2700      	movs	r7, #0
+    3a3e:	1a36      	subs	r6, r6, r0
+    3a40:	9302      	str	r3, [sp, #8]
+    3a42:	e784      	b.n	394e <__aeabi_dmul+0x4a>
+    3a44:	4653      	mov	r3, sl
+    3a46:	4323      	orrs	r3, r4
+    3a48:	d12a      	bne.n	3aa0 <__aeabi_dmul+0x19c>
+    3a4a:	2400      	movs	r4, #0
+    3a4c:	2002      	movs	r0, #2
+    3a4e:	e796      	b.n	397e <__aeabi_dmul+0x7a>
+    3a50:	4653      	mov	r3, sl
+    3a52:	4323      	orrs	r3, r4
+    3a54:	d020      	beq.n	3a98 <__aeabi_dmul+0x194>
+    3a56:	2c00      	cmp	r4, #0
+    3a58:	d100      	bne.n	3a5c <__aeabi_dmul+0x158>
+    3a5a:	e157      	b.n	3d0c <__aeabi_dmul+0x408>
+    3a5c:	0020      	movs	r0, r4
+    3a5e:	f000 fe91 	bl	4784 <__clzsi2>
+    3a62:	0003      	movs	r3, r0
+    3a64:	3b0b      	subs	r3, #11
+    3a66:	2b1c      	cmp	r3, #28
+    3a68:	dd00      	ble.n	3a6c <__aeabi_dmul+0x168>
+    3a6a:	e149      	b.n	3d00 <__aeabi_dmul+0x3fc>
+    3a6c:	211d      	movs	r1, #29
+    3a6e:	1acb      	subs	r3, r1, r3
+    3a70:	4651      	mov	r1, sl
+    3a72:	0002      	movs	r2, r0
+    3a74:	40d9      	lsrs	r1, r3
+    3a76:	4653      	mov	r3, sl
+    3a78:	3a08      	subs	r2, #8
+    3a7a:	4094      	lsls	r4, r2
+    3a7c:	4093      	lsls	r3, r2
+    3a7e:	430c      	orrs	r4, r1
+    3a80:	4a1b      	ldr	r2, [pc, #108]	; (3af0 <__aeabi_dmul+0x1ec>)
+    3a82:	1a12      	subs	r2, r2, r0
+    3a84:	2000      	movs	r0, #0
+    3a86:	e77a      	b.n	397e <__aeabi_dmul+0x7a>
+    3a88:	2501      	movs	r5, #1
+    3a8a:	9b01      	ldr	r3, [sp, #4]
+    3a8c:	4c14      	ldr	r4, [pc, #80]	; (3ae0 <__aeabi_dmul+0x1dc>)
+    3a8e:	401d      	ands	r5, r3
+    3a90:	2300      	movs	r3, #0
+    3a92:	2200      	movs	r2, #0
+    3a94:	4699      	mov	r9, r3
+    3a96:	e79c      	b.n	39d2 <__aeabi_dmul+0xce>
+    3a98:	2400      	movs	r4, #0
+    3a9a:	2200      	movs	r2, #0
+    3a9c:	2001      	movs	r0, #1
+    3a9e:	e76e      	b.n	397e <__aeabi_dmul+0x7a>
+    3aa0:	4653      	mov	r3, sl
+    3aa2:	2003      	movs	r0, #3
+    3aa4:	e76b      	b.n	397e <__aeabi_dmul+0x7a>
+    3aa6:	2300      	movs	r3, #0
+    3aa8:	469b      	mov	fp, r3
+    3aaa:	3301      	adds	r3, #1
+    3aac:	2704      	movs	r7, #4
+    3aae:	2600      	movs	r6, #0
+    3ab0:	9302      	str	r3, [sp, #8]
+    3ab2:	e74c      	b.n	394e <__aeabi_dmul+0x4a>
+    3ab4:	2303      	movs	r3, #3
+    3ab6:	4681      	mov	r9, r0
+    3ab8:	270c      	movs	r7, #12
+    3aba:	9302      	str	r3, [sp, #8]
+    3abc:	e747      	b.n	394e <__aeabi_dmul+0x4a>
+    3abe:	2280      	movs	r2, #128	; 0x80
+    3ac0:	2300      	movs	r3, #0
+    3ac2:	2500      	movs	r5, #0
+    3ac4:	0312      	lsls	r2, r2, #12
+    3ac6:	4699      	mov	r9, r3
+    3ac8:	4c05      	ldr	r4, [pc, #20]	; (3ae0 <__aeabi_dmul+0x1dc>)
+    3aca:	e782      	b.n	39d2 <__aeabi_dmul+0xce>
+    3acc:	465c      	mov	r4, fp
+    3ace:	464b      	mov	r3, r9
+    3ad0:	9802      	ldr	r0, [sp, #8]
+    3ad2:	e76f      	b.n	39b4 <__aeabi_dmul+0xb0>
+    3ad4:	465c      	mov	r4, fp
+    3ad6:	464b      	mov	r3, r9
+    3ad8:	9501      	str	r5, [sp, #4]
+    3ada:	9802      	ldr	r0, [sp, #8]
+    3adc:	e76a      	b.n	39b4 <__aeabi_dmul+0xb0>
+    3ade:	46c0      	nop			; (mov r8, r8)
+    3ae0:	000007ff 	.word	0x000007ff
+    3ae4:	fffffc01 	.word	0xfffffc01
+    3ae8:	00005a5c 	.word	0x00005a5c
+    3aec:	800fffff 	.word	0x800fffff
+    3af0:	fffffc0d 	.word	0xfffffc0d
+    3af4:	464a      	mov	r2, r9
+    3af6:	4649      	mov	r1, r9
+    3af8:	0c17      	lsrs	r7, r2, #16
+    3afa:	0c1a      	lsrs	r2, r3, #16
+    3afc:	041b      	lsls	r3, r3, #16
+    3afe:	0c1b      	lsrs	r3, r3, #16
+    3b00:	0408      	lsls	r0, r1, #16
+    3b02:	0019      	movs	r1, r3
+    3b04:	0c00      	lsrs	r0, r0, #16
+    3b06:	4341      	muls	r1, r0
+    3b08:	0015      	movs	r5, r2
+    3b0a:	4688      	mov	r8, r1
+    3b0c:	0019      	movs	r1, r3
+    3b0e:	437d      	muls	r5, r7
+    3b10:	4379      	muls	r1, r7
+    3b12:	9503      	str	r5, [sp, #12]
+    3b14:	4689      	mov	r9, r1
+    3b16:	0029      	movs	r1, r5
+    3b18:	0015      	movs	r5, r2
+    3b1a:	4345      	muls	r5, r0
+    3b1c:	444d      	add	r5, r9
+    3b1e:	9502      	str	r5, [sp, #8]
+    3b20:	4645      	mov	r5, r8
+    3b22:	0c2d      	lsrs	r5, r5, #16
+    3b24:	46aa      	mov	sl, r5
+    3b26:	9d02      	ldr	r5, [sp, #8]
+    3b28:	4455      	add	r5, sl
+    3b2a:	45a9      	cmp	r9, r5
+    3b2c:	d906      	bls.n	3b3c <__aeabi_dmul+0x238>
+    3b2e:	468a      	mov	sl, r1
+    3b30:	2180      	movs	r1, #128	; 0x80
+    3b32:	0249      	lsls	r1, r1, #9
+    3b34:	4689      	mov	r9, r1
+    3b36:	44ca      	add	sl, r9
+    3b38:	4651      	mov	r1, sl
+    3b3a:	9103      	str	r1, [sp, #12]
+    3b3c:	0c29      	lsrs	r1, r5, #16
+    3b3e:	9104      	str	r1, [sp, #16]
+    3b40:	4641      	mov	r1, r8
+    3b42:	0409      	lsls	r1, r1, #16
+    3b44:	042d      	lsls	r5, r5, #16
+    3b46:	0c09      	lsrs	r1, r1, #16
+    3b48:	4688      	mov	r8, r1
+    3b4a:	0029      	movs	r1, r5
+    3b4c:	0c25      	lsrs	r5, r4, #16
+    3b4e:	0424      	lsls	r4, r4, #16
+    3b50:	4441      	add	r1, r8
+    3b52:	0c24      	lsrs	r4, r4, #16
+    3b54:	9105      	str	r1, [sp, #20]
+    3b56:	0021      	movs	r1, r4
+    3b58:	4341      	muls	r1, r0
+    3b5a:	4688      	mov	r8, r1
+    3b5c:	0021      	movs	r1, r4
+    3b5e:	4379      	muls	r1, r7
+    3b60:	468a      	mov	sl, r1
+    3b62:	4368      	muls	r0, r5
+    3b64:	4641      	mov	r1, r8
+    3b66:	4450      	add	r0, sl
+    3b68:	4681      	mov	r9, r0
+    3b6a:	0c08      	lsrs	r0, r1, #16
+    3b6c:	4448      	add	r0, r9
+    3b6e:	436f      	muls	r7, r5
+    3b70:	4582      	cmp	sl, r0
+    3b72:	d903      	bls.n	3b7c <__aeabi_dmul+0x278>
+    3b74:	2180      	movs	r1, #128	; 0x80
+    3b76:	0249      	lsls	r1, r1, #9
+    3b78:	4689      	mov	r9, r1
+    3b7a:	444f      	add	r7, r9
+    3b7c:	0c01      	lsrs	r1, r0, #16
+    3b7e:	4689      	mov	r9, r1
+    3b80:	0039      	movs	r1, r7
+    3b82:	4449      	add	r1, r9
+    3b84:	9102      	str	r1, [sp, #8]
+    3b86:	4641      	mov	r1, r8
+    3b88:	040f      	lsls	r7, r1, #16
+    3b8a:	9904      	ldr	r1, [sp, #16]
+    3b8c:	0c3f      	lsrs	r7, r7, #16
+    3b8e:	4688      	mov	r8, r1
+    3b90:	0400      	lsls	r0, r0, #16
+    3b92:	19c0      	adds	r0, r0, r7
+    3b94:	4480      	add	r8, r0
+    3b96:	4641      	mov	r1, r8
+    3b98:	9104      	str	r1, [sp, #16]
+    3b9a:	4659      	mov	r1, fp
+    3b9c:	0c0f      	lsrs	r7, r1, #16
+    3b9e:	0409      	lsls	r1, r1, #16
+    3ba0:	0c09      	lsrs	r1, r1, #16
+    3ba2:	4688      	mov	r8, r1
+    3ba4:	4359      	muls	r1, r3
+    3ba6:	468a      	mov	sl, r1
+    3ba8:	0039      	movs	r1, r7
+    3baa:	4351      	muls	r1, r2
+    3bac:	4689      	mov	r9, r1
+    3bae:	4641      	mov	r1, r8
+    3bb0:	434a      	muls	r2, r1
+    3bb2:	4651      	mov	r1, sl
+    3bb4:	0c09      	lsrs	r1, r1, #16
+    3bb6:	468b      	mov	fp, r1
+    3bb8:	437b      	muls	r3, r7
+    3bba:	18d2      	adds	r2, r2, r3
+    3bbc:	445a      	add	r2, fp
+    3bbe:	4293      	cmp	r3, r2
+    3bc0:	d903      	bls.n	3bca <__aeabi_dmul+0x2c6>
+    3bc2:	2380      	movs	r3, #128	; 0x80
+    3bc4:	025b      	lsls	r3, r3, #9
+    3bc6:	469b      	mov	fp, r3
+    3bc8:	44d9      	add	r9, fp
+    3bca:	4651      	mov	r1, sl
+    3bcc:	0409      	lsls	r1, r1, #16
+    3bce:	0c09      	lsrs	r1, r1, #16
+    3bd0:	468a      	mov	sl, r1
+    3bd2:	4641      	mov	r1, r8
+    3bd4:	4361      	muls	r1, r4
+    3bd6:	437c      	muls	r4, r7
+    3bd8:	0c13      	lsrs	r3, r2, #16
+    3bda:	0412      	lsls	r2, r2, #16
+    3bdc:	444b      	add	r3, r9
+    3bde:	4452      	add	r2, sl
+    3be0:	46a1      	mov	r9, r4
+    3be2:	468a      	mov	sl, r1
+    3be4:	003c      	movs	r4, r7
+    3be6:	4641      	mov	r1, r8
+    3be8:	436c      	muls	r4, r5
+    3bea:	434d      	muls	r5, r1
+    3bec:	4651      	mov	r1, sl
+    3bee:	444d      	add	r5, r9
+    3bf0:	0c0f      	lsrs	r7, r1, #16
+    3bf2:	197d      	adds	r5, r7, r5
+    3bf4:	45a9      	cmp	r9, r5
+    3bf6:	d903      	bls.n	3c00 <__aeabi_dmul+0x2fc>
+    3bf8:	2180      	movs	r1, #128	; 0x80
+    3bfa:	0249      	lsls	r1, r1, #9
+    3bfc:	4688      	mov	r8, r1
+    3bfe:	4444      	add	r4, r8
+    3c00:	9f04      	ldr	r7, [sp, #16]
+    3c02:	9903      	ldr	r1, [sp, #12]
+    3c04:	46b8      	mov	r8, r7
+    3c06:	4441      	add	r1, r8
+    3c08:	468b      	mov	fp, r1
+    3c0a:	4583      	cmp	fp, r0
+    3c0c:	4180      	sbcs	r0, r0
+    3c0e:	4241      	negs	r1, r0
+    3c10:	4688      	mov	r8, r1
+    3c12:	4651      	mov	r1, sl
+    3c14:	0408      	lsls	r0, r1, #16
+    3c16:	042f      	lsls	r7, r5, #16
+    3c18:	0c00      	lsrs	r0, r0, #16
+    3c1a:	183f      	adds	r7, r7, r0
+    3c1c:	4658      	mov	r0, fp
+    3c1e:	9902      	ldr	r1, [sp, #8]
+    3c20:	1810      	adds	r0, r2, r0
+    3c22:	4689      	mov	r9, r1
+    3c24:	4290      	cmp	r0, r2
+    3c26:	4192      	sbcs	r2, r2
+    3c28:	444f      	add	r7, r9
+    3c2a:	46ba      	mov	sl, r7
+    3c2c:	4252      	negs	r2, r2
+    3c2e:	4699      	mov	r9, r3
+    3c30:	4693      	mov	fp, r2
+    3c32:	44c2      	add	sl, r8
+    3c34:	44d1      	add	r9, sl
+    3c36:	44cb      	add	fp, r9
+    3c38:	428f      	cmp	r7, r1
+    3c3a:	41bf      	sbcs	r7, r7
+    3c3c:	45c2      	cmp	sl, r8
+    3c3e:	4189      	sbcs	r1, r1
+    3c40:	4599      	cmp	r9, r3
+    3c42:	419b      	sbcs	r3, r3
+    3c44:	4593      	cmp	fp, r2
+    3c46:	4192      	sbcs	r2, r2
+    3c48:	427f      	negs	r7, r7
+    3c4a:	4249      	negs	r1, r1
+    3c4c:	0c2d      	lsrs	r5, r5, #16
+    3c4e:	4252      	negs	r2, r2
+    3c50:	430f      	orrs	r7, r1
+    3c52:	425b      	negs	r3, r3
+    3c54:	4313      	orrs	r3, r2
+    3c56:	197f      	adds	r7, r7, r5
+    3c58:	18ff      	adds	r7, r7, r3
+    3c5a:	465b      	mov	r3, fp
+    3c5c:	193c      	adds	r4, r7, r4
+    3c5e:	0ddb      	lsrs	r3, r3, #23
+    3c60:	9a05      	ldr	r2, [sp, #20]
+    3c62:	0264      	lsls	r4, r4, #9
+    3c64:	431c      	orrs	r4, r3
+    3c66:	0243      	lsls	r3, r0, #9
+    3c68:	4313      	orrs	r3, r2
+    3c6a:	1e5d      	subs	r5, r3, #1
+    3c6c:	41ab      	sbcs	r3, r5
+    3c6e:	465a      	mov	r2, fp
+    3c70:	0dc0      	lsrs	r0, r0, #23
+    3c72:	4303      	orrs	r3, r0
+    3c74:	0252      	lsls	r2, r2, #9
+    3c76:	4313      	orrs	r3, r2
+    3c78:	01e2      	lsls	r2, r4, #7
+    3c7a:	d556      	bpl.n	3d2a <__aeabi_dmul+0x426>
+    3c7c:	2001      	movs	r0, #1
+    3c7e:	085a      	lsrs	r2, r3, #1
+    3c80:	4003      	ands	r3, r0
+    3c82:	4313      	orrs	r3, r2
+    3c84:	07e2      	lsls	r2, r4, #31
+    3c86:	4313      	orrs	r3, r2
+    3c88:	0864      	lsrs	r4, r4, #1
+    3c8a:	485a      	ldr	r0, [pc, #360]	; (3df4 <__aeabi_dmul+0x4f0>)
+    3c8c:	4460      	add	r0, ip
+    3c8e:	2800      	cmp	r0, #0
+    3c90:	dd4d      	ble.n	3d2e <__aeabi_dmul+0x42a>
+    3c92:	075a      	lsls	r2, r3, #29
+    3c94:	d009      	beq.n	3caa <__aeabi_dmul+0x3a6>
+    3c96:	220f      	movs	r2, #15
+    3c98:	401a      	ands	r2, r3
+    3c9a:	2a04      	cmp	r2, #4
+    3c9c:	d005      	beq.n	3caa <__aeabi_dmul+0x3a6>
+    3c9e:	1d1a      	adds	r2, r3, #4
+    3ca0:	429a      	cmp	r2, r3
+    3ca2:	419b      	sbcs	r3, r3
+    3ca4:	425b      	negs	r3, r3
+    3ca6:	18e4      	adds	r4, r4, r3
+    3ca8:	0013      	movs	r3, r2
+    3caa:	01e2      	lsls	r2, r4, #7
+    3cac:	d504      	bpl.n	3cb8 <__aeabi_dmul+0x3b4>
+    3cae:	2080      	movs	r0, #128	; 0x80
+    3cb0:	4a51      	ldr	r2, [pc, #324]	; (3df8 <__aeabi_dmul+0x4f4>)
+    3cb2:	00c0      	lsls	r0, r0, #3
+    3cb4:	4014      	ands	r4, r2
+    3cb6:	4460      	add	r0, ip
+    3cb8:	4a50      	ldr	r2, [pc, #320]	; (3dfc <__aeabi_dmul+0x4f8>)
+    3cba:	4290      	cmp	r0, r2
+    3cbc:	dd00      	ble.n	3cc0 <__aeabi_dmul+0x3bc>
+    3cbe:	e6e3      	b.n	3a88 <__aeabi_dmul+0x184>
+    3cc0:	2501      	movs	r5, #1
+    3cc2:	08db      	lsrs	r3, r3, #3
+    3cc4:	0762      	lsls	r2, r4, #29
+    3cc6:	431a      	orrs	r2, r3
+    3cc8:	0264      	lsls	r4, r4, #9
+    3cca:	9b01      	ldr	r3, [sp, #4]
+    3ccc:	4691      	mov	r9, r2
+    3cce:	0b22      	lsrs	r2, r4, #12
+    3cd0:	0544      	lsls	r4, r0, #21
+    3cd2:	0d64      	lsrs	r4, r4, #21
+    3cd4:	401d      	ands	r5, r3
+    3cd6:	e67c      	b.n	39d2 <__aeabi_dmul+0xce>
+    3cd8:	2280      	movs	r2, #128	; 0x80
+    3cda:	4659      	mov	r1, fp
+    3cdc:	0312      	lsls	r2, r2, #12
+    3cde:	4211      	tst	r1, r2
+    3ce0:	d008      	beq.n	3cf4 <__aeabi_dmul+0x3f0>
+    3ce2:	4214      	tst	r4, r2
+    3ce4:	d106      	bne.n	3cf4 <__aeabi_dmul+0x3f0>
+    3ce6:	4322      	orrs	r2, r4
+    3ce8:	0312      	lsls	r2, r2, #12
+    3cea:	0b12      	lsrs	r2, r2, #12
+    3cec:	4645      	mov	r5, r8
+    3cee:	4699      	mov	r9, r3
+    3cf0:	4c43      	ldr	r4, [pc, #268]	; (3e00 <__aeabi_dmul+0x4fc>)
+    3cf2:	e66e      	b.n	39d2 <__aeabi_dmul+0xce>
+    3cf4:	465b      	mov	r3, fp
+    3cf6:	431a      	orrs	r2, r3
+    3cf8:	0312      	lsls	r2, r2, #12
+    3cfa:	0b12      	lsrs	r2, r2, #12
+    3cfc:	4c40      	ldr	r4, [pc, #256]	; (3e00 <__aeabi_dmul+0x4fc>)
+    3cfe:	e668      	b.n	39d2 <__aeabi_dmul+0xce>
+    3d00:	0003      	movs	r3, r0
+    3d02:	4654      	mov	r4, sl
+    3d04:	3b28      	subs	r3, #40	; 0x28
+    3d06:	409c      	lsls	r4, r3
+    3d08:	2300      	movs	r3, #0
+    3d0a:	e6b9      	b.n	3a80 <__aeabi_dmul+0x17c>
+    3d0c:	f000 fd3a 	bl	4784 <__clzsi2>
+    3d10:	3020      	adds	r0, #32
+    3d12:	e6a6      	b.n	3a62 <__aeabi_dmul+0x15e>
+    3d14:	0003      	movs	r3, r0
+    3d16:	3b28      	subs	r3, #40	; 0x28
+    3d18:	409f      	lsls	r7, r3
+    3d1a:	2300      	movs	r3, #0
+    3d1c:	46bb      	mov	fp, r7
+    3d1e:	4699      	mov	r9, r3
+    3d20:	e68a      	b.n	3a38 <__aeabi_dmul+0x134>
+    3d22:	f000 fd2f 	bl	4784 <__clzsi2>
+    3d26:	3020      	adds	r0, #32
+    3d28:	e674      	b.n	3a14 <__aeabi_dmul+0x110>
+    3d2a:	46b4      	mov	ip, r6
+    3d2c:	e7ad      	b.n	3c8a <__aeabi_dmul+0x386>
+    3d2e:	2501      	movs	r5, #1
+    3d30:	1a2a      	subs	r2, r5, r0
+    3d32:	2a38      	cmp	r2, #56	; 0x38
+    3d34:	dd06      	ble.n	3d44 <__aeabi_dmul+0x440>
+    3d36:	9b01      	ldr	r3, [sp, #4]
+    3d38:	2400      	movs	r4, #0
+    3d3a:	401d      	ands	r5, r3
+    3d3c:	2300      	movs	r3, #0
+    3d3e:	2200      	movs	r2, #0
+    3d40:	4699      	mov	r9, r3
+    3d42:	e646      	b.n	39d2 <__aeabi_dmul+0xce>
+    3d44:	2a1f      	cmp	r2, #31
+    3d46:	dc21      	bgt.n	3d8c <__aeabi_dmul+0x488>
+    3d48:	2520      	movs	r5, #32
+    3d4a:	0020      	movs	r0, r4
+    3d4c:	1aad      	subs	r5, r5, r2
+    3d4e:	001e      	movs	r6, r3
+    3d50:	40ab      	lsls	r3, r5
+    3d52:	40a8      	lsls	r0, r5
+    3d54:	40d6      	lsrs	r6, r2
+    3d56:	1e5d      	subs	r5, r3, #1
+    3d58:	41ab      	sbcs	r3, r5
+    3d5a:	4330      	orrs	r0, r6
+    3d5c:	4318      	orrs	r0, r3
+    3d5e:	40d4      	lsrs	r4, r2
+    3d60:	0743      	lsls	r3, r0, #29
+    3d62:	d009      	beq.n	3d78 <__aeabi_dmul+0x474>
+    3d64:	230f      	movs	r3, #15
+    3d66:	4003      	ands	r3, r0
+    3d68:	2b04      	cmp	r3, #4
+    3d6a:	d005      	beq.n	3d78 <__aeabi_dmul+0x474>
+    3d6c:	0003      	movs	r3, r0
+    3d6e:	1d18      	adds	r0, r3, #4
+    3d70:	4298      	cmp	r0, r3
+    3d72:	419b      	sbcs	r3, r3
+    3d74:	425b      	negs	r3, r3
+    3d76:	18e4      	adds	r4, r4, r3
+    3d78:	0223      	lsls	r3, r4, #8
+    3d7a:	d521      	bpl.n	3dc0 <__aeabi_dmul+0x4bc>
+    3d7c:	2501      	movs	r5, #1
+    3d7e:	9b01      	ldr	r3, [sp, #4]
+    3d80:	2401      	movs	r4, #1
+    3d82:	401d      	ands	r5, r3
+    3d84:	2300      	movs	r3, #0
+    3d86:	2200      	movs	r2, #0
+    3d88:	4699      	mov	r9, r3
+    3d8a:	e622      	b.n	39d2 <__aeabi_dmul+0xce>
+    3d8c:	251f      	movs	r5, #31
+    3d8e:	0021      	movs	r1, r4
+    3d90:	426d      	negs	r5, r5
+    3d92:	1a28      	subs	r0, r5, r0
+    3d94:	40c1      	lsrs	r1, r0
+    3d96:	0008      	movs	r0, r1
+    3d98:	2a20      	cmp	r2, #32
+    3d9a:	d01d      	beq.n	3dd8 <__aeabi_dmul+0x4d4>
+    3d9c:	355f      	adds	r5, #95	; 0x5f
+    3d9e:	1aaa      	subs	r2, r5, r2
+    3da0:	4094      	lsls	r4, r2
+    3da2:	4323      	orrs	r3, r4
+    3da4:	1e5c      	subs	r4, r3, #1
+    3da6:	41a3      	sbcs	r3, r4
+    3da8:	2507      	movs	r5, #7
+    3daa:	4303      	orrs	r3, r0
+    3dac:	401d      	ands	r5, r3
+    3dae:	2200      	movs	r2, #0
+    3db0:	2d00      	cmp	r5, #0
+    3db2:	d009      	beq.n	3dc8 <__aeabi_dmul+0x4c4>
+    3db4:	220f      	movs	r2, #15
+    3db6:	2400      	movs	r4, #0
+    3db8:	401a      	ands	r2, r3
+    3dba:	0018      	movs	r0, r3
+    3dbc:	2a04      	cmp	r2, #4
+    3dbe:	d1d6      	bne.n	3d6e <__aeabi_dmul+0x46a>
+    3dc0:	0003      	movs	r3, r0
+    3dc2:	0765      	lsls	r5, r4, #29
+    3dc4:	0264      	lsls	r4, r4, #9
+    3dc6:	0b22      	lsrs	r2, r4, #12
+    3dc8:	08db      	lsrs	r3, r3, #3
+    3dca:	432b      	orrs	r3, r5
+    3dcc:	2501      	movs	r5, #1
+    3dce:	4699      	mov	r9, r3
+    3dd0:	9b01      	ldr	r3, [sp, #4]
+    3dd2:	2400      	movs	r4, #0
+    3dd4:	401d      	ands	r5, r3
+    3dd6:	e5fc      	b.n	39d2 <__aeabi_dmul+0xce>
+    3dd8:	2400      	movs	r4, #0
+    3dda:	e7e2      	b.n	3da2 <__aeabi_dmul+0x49e>
+    3ddc:	2280      	movs	r2, #128	; 0x80
+    3dde:	2501      	movs	r5, #1
+    3de0:	0312      	lsls	r2, r2, #12
+    3de2:	4322      	orrs	r2, r4
+    3de4:	9901      	ldr	r1, [sp, #4]
+    3de6:	0312      	lsls	r2, r2, #12
+    3de8:	0b12      	lsrs	r2, r2, #12
+    3dea:	400d      	ands	r5, r1
+    3dec:	4699      	mov	r9, r3
+    3dee:	4c04      	ldr	r4, [pc, #16]	; (3e00 <__aeabi_dmul+0x4fc>)
+    3df0:	e5ef      	b.n	39d2 <__aeabi_dmul+0xce>
+    3df2:	46c0      	nop			; (mov r8, r8)
+    3df4:	000003ff 	.word	0x000003ff
+    3df8:	feffffff 	.word	0xfeffffff
+    3dfc:	000007fe 	.word	0x000007fe
+    3e00:	000007ff 	.word	0x000007ff
+
+00003e04 <__aeabi_dsub>:
+    3e04:	b5f0      	push	{r4, r5, r6, r7, lr}
+    3e06:	4646      	mov	r6, r8
+    3e08:	46d6      	mov	lr, sl
+    3e0a:	464f      	mov	r7, r9
+    3e0c:	030c      	lsls	r4, r1, #12
+    3e0e:	b5c0      	push	{r6, r7, lr}
+    3e10:	0fcd      	lsrs	r5, r1, #31
+    3e12:	004e      	lsls	r6, r1, #1
+    3e14:	0a61      	lsrs	r1, r4, #9
+    3e16:	0f44      	lsrs	r4, r0, #29
+    3e18:	430c      	orrs	r4, r1
+    3e1a:	00c1      	lsls	r1, r0, #3
+    3e1c:	0058      	lsls	r0, r3, #1
+    3e1e:	0d40      	lsrs	r0, r0, #21
+    3e20:	4684      	mov	ip, r0
+    3e22:	468a      	mov	sl, r1
+    3e24:	000f      	movs	r7, r1
+    3e26:	0319      	lsls	r1, r3, #12
+    3e28:	0f50      	lsrs	r0, r2, #29
+    3e2a:	0a49      	lsrs	r1, r1, #9
+    3e2c:	4301      	orrs	r1, r0
+    3e2e:	48c6      	ldr	r0, [pc, #792]	; (4148 <__aeabi_dsub+0x344>)
+    3e30:	0d76      	lsrs	r6, r6, #21
+    3e32:	46a8      	mov	r8, r5
+    3e34:	0fdb      	lsrs	r3, r3, #31
+    3e36:	00d2      	lsls	r2, r2, #3
+    3e38:	4584      	cmp	ip, r0
+    3e3a:	d100      	bne.n	3e3e <__aeabi_dsub+0x3a>
+    3e3c:	e0d8      	b.n	3ff0 <__aeabi_dsub+0x1ec>
+    3e3e:	2001      	movs	r0, #1
+    3e40:	4043      	eors	r3, r0
+    3e42:	42ab      	cmp	r3, r5
+    3e44:	d100      	bne.n	3e48 <__aeabi_dsub+0x44>
+    3e46:	e0a6      	b.n	3f96 <__aeabi_dsub+0x192>
+    3e48:	4660      	mov	r0, ip
+    3e4a:	1a35      	subs	r5, r6, r0
+    3e4c:	2d00      	cmp	r5, #0
+    3e4e:	dc00      	bgt.n	3e52 <__aeabi_dsub+0x4e>
+    3e50:	e105      	b.n	405e <__aeabi_dsub+0x25a>
+    3e52:	2800      	cmp	r0, #0
+    3e54:	d110      	bne.n	3e78 <__aeabi_dsub+0x74>
+    3e56:	000b      	movs	r3, r1
+    3e58:	4313      	orrs	r3, r2
+    3e5a:	d100      	bne.n	3e5e <__aeabi_dsub+0x5a>
+    3e5c:	e0d7      	b.n	400e <__aeabi_dsub+0x20a>
+    3e5e:	1e6b      	subs	r3, r5, #1
+    3e60:	2b00      	cmp	r3, #0
+    3e62:	d000      	beq.n	3e66 <__aeabi_dsub+0x62>
+    3e64:	e14b      	b.n	40fe <__aeabi_dsub+0x2fa>
+    3e66:	4653      	mov	r3, sl
+    3e68:	1a9f      	subs	r7, r3, r2
+    3e6a:	45ba      	cmp	sl, r7
+    3e6c:	4180      	sbcs	r0, r0
+    3e6e:	1a64      	subs	r4, r4, r1
+    3e70:	4240      	negs	r0, r0
+    3e72:	1a24      	subs	r4, r4, r0
+    3e74:	2601      	movs	r6, #1
+    3e76:	e01e      	b.n	3eb6 <__aeabi_dsub+0xb2>
+    3e78:	4bb3      	ldr	r3, [pc, #716]	; (4148 <__aeabi_dsub+0x344>)
+    3e7a:	429e      	cmp	r6, r3
+    3e7c:	d048      	beq.n	3f10 <__aeabi_dsub+0x10c>
+    3e7e:	2380      	movs	r3, #128	; 0x80
+    3e80:	041b      	lsls	r3, r3, #16
+    3e82:	4319      	orrs	r1, r3
+    3e84:	2d38      	cmp	r5, #56	; 0x38
+    3e86:	dd00      	ble.n	3e8a <__aeabi_dsub+0x86>
+    3e88:	e119      	b.n	40be <__aeabi_dsub+0x2ba>
+    3e8a:	2d1f      	cmp	r5, #31
+    3e8c:	dd00      	ble.n	3e90 <__aeabi_dsub+0x8c>
+    3e8e:	e14c      	b.n	412a <__aeabi_dsub+0x326>
+    3e90:	2320      	movs	r3, #32
+    3e92:	000f      	movs	r7, r1
+    3e94:	1b5b      	subs	r3, r3, r5
+    3e96:	0010      	movs	r0, r2
+    3e98:	409a      	lsls	r2, r3
+    3e9a:	409f      	lsls	r7, r3
+    3e9c:	40e8      	lsrs	r0, r5
+    3e9e:	1e53      	subs	r3, r2, #1
+    3ea0:	419a      	sbcs	r2, r3
+    3ea2:	40e9      	lsrs	r1, r5
+    3ea4:	4307      	orrs	r7, r0
+    3ea6:	4317      	orrs	r7, r2
+    3ea8:	4653      	mov	r3, sl
+    3eaa:	1bdf      	subs	r7, r3, r7
+    3eac:	1a61      	subs	r1, r4, r1
+    3eae:	45ba      	cmp	sl, r7
+    3eb0:	41a4      	sbcs	r4, r4
+    3eb2:	4264      	negs	r4, r4
+    3eb4:	1b0c      	subs	r4, r1, r4
+    3eb6:	0223      	lsls	r3, r4, #8
+    3eb8:	d400      	bmi.n	3ebc <__aeabi_dsub+0xb8>
+    3eba:	e0c5      	b.n	4048 <__aeabi_dsub+0x244>
+    3ebc:	0264      	lsls	r4, r4, #9
+    3ebe:	0a65      	lsrs	r5, r4, #9
+    3ec0:	2d00      	cmp	r5, #0
+    3ec2:	d100      	bne.n	3ec6 <__aeabi_dsub+0xc2>
+    3ec4:	e0f6      	b.n	40b4 <__aeabi_dsub+0x2b0>
+    3ec6:	0028      	movs	r0, r5
+    3ec8:	f000 fc5c 	bl	4784 <__clzsi2>
+    3ecc:	0003      	movs	r3, r0
+    3ece:	3b08      	subs	r3, #8
+    3ed0:	2b1f      	cmp	r3, #31
+    3ed2:	dd00      	ble.n	3ed6 <__aeabi_dsub+0xd2>
+    3ed4:	e0e9      	b.n	40aa <__aeabi_dsub+0x2a6>
+    3ed6:	2220      	movs	r2, #32
+    3ed8:	003c      	movs	r4, r7
+    3eda:	1ad2      	subs	r2, r2, r3
+    3edc:	409d      	lsls	r5, r3
+    3ede:	40d4      	lsrs	r4, r2
+    3ee0:	409f      	lsls	r7, r3
+    3ee2:	4325      	orrs	r5, r4
+    3ee4:	429e      	cmp	r6, r3
+    3ee6:	dd00      	ble.n	3eea <__aeabi_dsub+0xe6>
+    3ee8:	e0db      	b.n	40a2 <__aeabi_dsub+0x29e>
+    3eea:	1b9e      	subs	r6, r3, r6
+    3eec:	1c73      	adds	r3, r6, #1
+    3eee:	2b1f      	cmp	r3, #31
+    3ef0:	dd00      	ble.n	3ef4 <__aeabi_dsub+0xf0>
+    3ef2:	e10a      	b.n	410a <__aeabi_dsub+0x306>
+    3ef4:	2220      	movs	r2, #32
+    3ef6:	0038      	movs	r0, r7
+    3ef8:	1ad2      	subs	r2, r2, r3
+    3efa:	0029      	movs	r1, r5
+    3efc:	4097      	lsls	r7, r2
+    3efe:	002c      	movs	r4, r5
+    3f00:	4091      	lsls	r1, r2
+    3f02:	40d8      	lsrs	r0, r3
+    3f04:	1e7a      	subs	r2, r7, #1
+    3f06:	4197      	sbcs	r7, r2
+    3f08:	40dc      	lsrs	r4, r3
+    3f0a:	2600      	movs	r6, #0
+    3f0c:	4301      	orrs	r1, r0
+    3f0e:	430f      	orrs	r7, r1
+    3f10:	077b      	lsls	r3, r7, #29
+    3f12:	d009      	beq.n	3f28 <__aeabi_dsub+0x124>
+    3f14:	230f      	movs	r3, #15
+    3f16:	403b      	ands	r3, r7
+    3f18:	2b04      	cmp	r3, #4
+    3f1a:	d005      	beq.n	3f28 <__aeabi_dsub+0x124>
+    3f1c:	1d3b      	adds	r3, r7, #4
+    3f1e:	42bb      	cmp	r3, r7
+    3f20:	41bf      	sbcs	r7, r7
+    3f22:	427f      	negs	r7, r7
+    3f24:	19e4      	adds	r4, r4, r7
+    3f26:	001f      	movs	r7, r3
+    3f28:	0223      	lsls	r3, r4, #8
+    3f2a:	d525      	bpl.n	3f78 <__aeabi_dsub+0x174>
+    3f2c:	4b86      	ldr	r3, [pc, #536]	; (4148 <__aeabi_dsub+0x344>)
+    3f2e:	3601      	adds	r6, #1
+    3f30:	429e      	cmp	r6, r3
+    3f32:	d100      	bne.n	3f36 <__aeabi_dsub+0x132>
+    3f34:	e0af      	b.n	4096 <__aeabi_dsub+0x292>
+    3f36:	4b85      	ldr	r3, [pc, #532]	; (414c <__aeabi_dsub+0x348>)
+    3f38:	2501      	movs	r5, #1
+    3f3a:	401c      	ands	r4, r3
+    3f3c:	4643      	mov	r3, r8
+    3f3e:	0762      	lsls	r2, r4, #29
+    3f40:	08ff      	lsrs	r7, r7, #3
+    3f42:	0264      	lsls	r4, r4, #9
+    3f44:	0576      	lsls	r6, r6, #21
+    3f46:	4317      	orrs	r7, r2
+    3f48:	0b24      	lsrs	r4, r4, #12
+    3f4a:	0d76      	lsrs	r6, r6, #21
+    3f4c:	401d      	ands	r5, r3
+    3f4e:	2100      	movs	r1, #0
+    3f50:	0324      	lsls	r4, r4, #12
+    3f52:	0b23      	lsrs	r3, r4, #12
+    3f54:	0d0c      	lsrs	r4, r1, #20
+    3f56:	4a7e      	ldr	r2, [pc, #504]	; (4150 <__aeabi_dsub+0x34c>)
+    3f58:	0524      	lsls	r4, r4, #20
+    3f5a:	431c      	orrs	r4, r3
+    3f5c:	4014      	ands	r4, r2
+    3f5e:	0533      	lsls	r3, r6, #20
+    3f60:	4323      	orrs	r3, r4
+    3f62:	005b      	lsls	r3, r3, #1
+    3f64:	07ed      	lsls	r5, r5, #31
+    3f66:	085b      	lsrs	r3, r3, #1
+    3f68:	432b      	orrs	r3, r5
+    3f6a:	0038      	movs	r0, r7
+    3f6c:	0019      	movs	r1, r3
+    3f6e:	bc1c      	pop	{r2, r3, r4}
+    3f70:	4690      	mov	r8, r2
+    3f72:	4699      	mov	r9, r3
+    3f74:	46a2      	mov	sl, r4
+    3f76:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    3f78:	2501      	movs	r5, #1
+    3f7a:	4643      	mov	r3, r8
+    3f7c:	0762      	lsls	r2, r4, #29
+    3f7e:	08ff      	lsrs	r7, r7, #3
+    3f80:	4317      	orrs	r7, r2
+    3f82:	08e4      	lsrs	r4, r4, #3
+    3f84:	401d      	ands	r5, r3
+    3f86:	4b70      	ldr	r3, [pc, #448]	; (4148 <__aeabi_dsub+0x344>)
+    3f88:	429e      	cmp	r6, r3
+    3f8a:	d036      	beq.n	3ffa <__aeabi_dsub+0x1f6>
+    3f8c:	0324      	lsls	r4, r4, #12
+    3f8e:	0576      	lsls	r6, r6, #21
+    3f90:	0b24      	lsrs	r4, r4, #12
+    3f92:	0d76      	lsrs	r6, r6, #21
+    3f94:	e7db      	b.n	3f4e <__aeabi_dsub+0x14a>
+    3f96:	4663      	mov	r3, ip
+    3f98:	1af3      	subs	r3, r6, r3
+    3f9a:	2b00      	cmp	r3, #0
+    3f9c:	dc00      	bgt.n	3fa0 <__aeabi_dsub+0x19c>
+    3f9e:	e094      	b.n	40ca <__aeabi_dsub+0x2c6>
+    3fa0:	4660      	mov	r0, ip
+    3fa2:	2800      	cmp	r0, #0
+    3fa4:	d035      	beq.n	4012 <__aeabi_dsub+0x20e>
+    3fa6:	4868      	ldr	r0, [pc, #416]	; (4148 <__aeabi_dsub+0x344>)
+    3fa8:	4286      	cmp	r6, r0
+    3faa:	d0b1      	beq.n	3f10 <__aeabi_dsub+0x10c>
+    3fac:	2780      	movs	r7, #128	; 0x80
+    3fae:	043f      	lsls	r7, r7, #16
+    3fb0:	4339      	orrs	r1, r7
+    3fb2:	2b38      	cmp	r3, #56	; 0x38
+    3fb4:	dc00      	bgt.n	3fb8 <__aeabi_dsub+0x1b4>
+    3fb6:	e0fd      	b.n	41b4 <__aeabi_dsub+0x3b0>
+    3fb8:	430a      	orrs	r2, r1
+    3fba:	0017      	movs	r7, r2
+    3fbc:	2100      	movs	r1, #0
+    3fbe:	1e7a      	subs	r2, r7, #1
+    3fc0:	4197      	sbcs	r7, r2
+    3fc2:	4457      	add	r7, sl
+    3fc4:	4557      	cmp	r7, sl
+    3fc6:	4180      	sbcs	r0, r0
+    3fc8:	1909      	adds	r1, r1, r4
+    3fca:	4244      	negs	r4, r0
+    3fcc:	190c      	adds	r4, r1, r4
+    3fce:	0223      	lsls	r3, r4, #8
+    3fd0:	d53a      	bpl.n	4048 <__aeabi_dsub+0x244>
+    3fd2:	4b5d      	ldr	r3, [pc, #372]	; (4148 <__aeabi_dsub+0x344>)
+    3fd4:	3601      	adds	r6, #1
+    3fd6:	429e      	cmp	r6, r3
+    3fd8:	d100      	bne.n	3fdc <__aeabi_dsub+0x1d8>
+    3fda:	e14b      	b.n	4274 <__aeabi_dsub+0x470>
+    3fdc:	2201      	movs	r2, #1
+    3fde:	4b5b      	ldr	r3, [pc, #364]	; (414c <__aeabi_dsub+0x348>)
+    3fe0:	401c      	ands	r4, r3
+    3fe2:	087b      	lsrs	r3, r7, #1
+    3fe4:	4017      	ands	r7, r2
+    3fe6:	431f      	orrs	r7, r3
+    3fe8:	07e2      	lsls	r2, r4, #31
+    3fea:	4317      	orrs	r7, r2
+    3fec:	0864      	lsrs	r4, r4, #1
+    3fee:	e78f      	b.n	3f10 <__aeabi_dsub+0x10c>
+    3ff0:	0008      	movs	r0, r1
+    3ff2:	4310      	orrs	r0, r2
+    3ff4:	d000      	beq.n	3ff8 <__aeabi_dsub+0x1f4>
+    3ff6:	e724      	b.n	3e42 <__aeabi_dsub+0x3e>
+    3ff8:	e721      	b.n	3e3e <__aeabi_dsub+0x3a>
+    3ffa:	0023      	movs	r3, r4
+    3ffc:	433b      	orrs	r3, r7
+    3ffe:	d100      	bne.n	4002 <__aeabi_dsub+0x1fe>
+    4000:	e1b9      	b.n	4376 <__aeabi_dsub+0x572>
+    4002:	2280      	movs	r2, #128	; 0x80
+    4004:	0312      	lsls	r2, r2, #12
+    4006:	4314      	orrs	r4, r2
+    4008:	0324      	lsls	r4, r4, #12
+    400a:	0b24      	lsrs	r4, r4, #12
+    400c:	e79f      	b.n	3f4e <__aeabi_dsub+0x14a>
+    400e:	002e      	movs	r6, r5
+    4010:	e77e      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4012:	0008      	movs	r0, r1
+    4014:	4310      	orrs	r0, r2
+    4016:	d100      	bne.n	401a <__aeabi_dsub+0x216>
+    4018:	e0ca      	b.n	41b0 <__aeabi_dsub+0x3ac>
+    401a:	1e58      	subs	r0, r3, #1
+    401c:	4684      	mov	ip, r0
+    401e:	2800      	cmp	r0, #0
+    4020:	d000      	beq.n	4024 <__aeabi_dsub+0x220>
+    4022:	e0e7      	b.n	41f4 <__aeabi_dsub+0x3f0>
+    4024:	4452      	add	r2, sl
+    4026:	4552      	cmp	r2, sl
+    4028:	4180      	sbcs	r0, r0
+    402a:	1864      	adds	r4, r4, r1
+    402c:	4240      	negs	r0, r0
+    402e:	1824      	adds	r4, r4, r0
+    4030:	0017      	movs	r7, r2
+    4032:	2601      	movs	r6, #1
+    4034:	0223      	lsls	r3, r4, #8
+    4036:	d507      	bpl.n	4048 <__aeabi_dsub+0x244>
+    4038:	2602      	movs	r6, #2
+    403a:	e7cf      	b.n	3fdc <__aeabi_dsub+0x1d8>
+    403c:	4664      	mov	r4, ip
+    403e:	432c      	orrs	r4, r5
+    4040:	d100      	bne.n	4044 <__aeabi_dsub+0x240>
+    4042:	e1b3      	b.n	43ac <__aeabi_dsub+0x5a8>
+    4044:	002c      	movs	r4, r5
+    4046:	4667      	mov	r7, ip
+    4048:	077b      	lsls	r3, r7, #29
+    404a:	d000      	beq.n	404e <__aeabi_dsub+0x24a>
+    404c:	e762      	b.n	3f14 <__aeabi_dsub+0x110>
+    404e:	0763      	lsls	r3, r4, #29
+    4050:	08ff      	lsrs	r7, r7, #3
+    4052:	431f      	orrs	r7, r3
+    4054:	2501      	movs	r5, #1
+    4056:	4643      	mov	r3, r8
+    4058:	08e4      	lsrs	r4, r4, #3
+    405a:	401d      	ands	r5, r3
+    405c:	e793      	b.n	3f86 <__aeabi_dsub+0x182>
+    405e:	2d00      	cmp	r5, #0
+    4060:	d178      	bne.n	4154 <__aeabi_dsub+0x350>
+    4062:	1c75      	adds	r5, r6, #1
+    4064:	056d      	lsls	r5, r5, #21
+    4066:	0d6d      	lsrs	r5, r5, #21
+    4068:	2d01      	cmp	r5, #1
+    406a:	dc00      	bgt.n	406e <__aeabi_dsub+0x26a>
+    406c:	e0f2      	b.n	4254 <__aeabi_dsub+0x450>
+    406e:	4650      	mov	r0, sl
+    4070:	1a80      	subs	r0, r0, r2
+    4072:	4582      	cmp	sl, r0
+    4074:	41bf      	sbcs	r7, r7
+    4076:	1a65      	subs	r5, r4, r1
+    4078:	427f      	negs	r7, r7
+    407a:	1bed      	subs	r5, r5, r7
+    407c:	4684      	mov	ip, r0
+    407e:	0228      	lsls	r0, r5, #8
+    4080:	d400      	bmi.n	4084 <__aeabi_dsub+0x280>
+    4082:	e08c      	b.n	419e <__aeabi_dsub+0x39a>
+    4084:	4650      	mov	r0, sl
+    4086:	1a17      	subs	r7, r2, r0
+    4088:	42ba      	cmp	r2, r7
+    408a:	4192      	sbcs	r2, r2
+    408c:	1b0c      	subs	r4, r1, r4
+    408e:	4255      	negs	r5, r2
+    4090:	1b65      	subs	r5, r4, r5
+    4092:	4698      	mov	r8, r3
+    4094:	e714      	b.n	3ec0 <__aeabi_dsub+0xbc>
+    4096:	2501      	movs	r5, #1
+    4098:	4643      	mov	r3, r8
+    409a:	2400      	movs	r4, #0
+    409c:	401d      	ands	r5, r3
+    409e:	2700      	movs	r7, #0
+    40a0:	e755      	b.n	3f4e <__aeabi_dsub+0x14a>
+    40a2:	4c2a      	ldr	r4, [pc, #168]	; (414c <__aeabi_dsub+0x348>)
+    40a4:	1af6      	subs	r6, r6, r3
+    40a6:	402c      	ands	r4, r5
+    40a8:	e732      	b.n	3f10 <__aeabi_dsub+0x10c>
+    40aa:	003d      	movs	r5, r7
+    40ac:	3828      	subs	r0, #40	; 0x28
+    40ae:	4085      	lsls	r5, r0
+    40b0:	2700      	movs	r7, #0
+    40b2:	e717      	b.n	3ee4 <__aeabi_dsub+0xe0>
+    40b4:	0038      	movs	r0, r7
+    40b6:	f000 fb65 	bl	4784 <__clzsi2>
+    40ba:	3020      	adds	r0, #32
+    40bc:	e706      	b.n	3ecc <__aeabi_dsub+0xc8>
+    40be:	430a      	orrs	r2, r1
+    40c0:	0017      	movs	r7, r2
+    40c2:	2100      	movs	r1, #0
+    40c4:	1e7a      	subs	r2, r7, #1
+    40c6:	4197      	sbcs	r7, r2
+    40c8:	e6ee      	b.n	3ea8 <__aeabi_dsub+0xa4>
+    40ca:	2b00      	cmp	r3, #0
+    40cc:	d000      	beq.n	40d0 <__aeabi_dsub+0x2cc>
+    40ce:	e0e5      	b.n	429c <__aeabi_dsub+0x498>
+    40d0:	1c73      	adds	r3, r6, #1
+    40d2:	469c      	mov	ip, r3
+    40d4:	055b      	lsls	r3, r3, #21
+    40d6:	0d5b      	lsrs	r3, r3, #21
+    40d8:	2b01      	cmp	r3, #1
+    40da:	dc00      	bgt.n	40de <__aeabi_dsub+0x2da>
+    40dc:	e09f      	b.n	421e <__aeabi_dsub+0x41a>
+    40de:	4b1a      	ldr	r3, [pc, #104]	; (4148 <__aeabi_dsub+0x344>)
+    40e0:	459c      	cmp	ip, r3
+    40e2:	d100      	bne.n	40e6 <__aeabi_dsub+0x2e2>
+    40e4:	e0c5      	b.n	4272 <__aeabi_dsub+0x46e>
+    40e6:	4452      	add	r2, sl
+    40e8:	4552      	cmp	r2, sl
+    40ea:	4180      	sbcs	r0, r0
+    40ec:	1864      	adds	r4, r4, r1
+    40ee:	4240      	negs	r0, r0
+    40f0:	1824      	adds	r4, r4, r0
+    40f2:	07e7      	lsls	r7, r4, #31
+    40f4:	0852      	lsrs	r2, r2, #1
+    40f6:	4317      	orrs	r7, r2
+    40f8:	0864      	lsrs	r4, r4, #1
+    40fa:	4666      	mov	r6, ip
+    40fc:	e708      	b.n	3f10 <__aeabi_dsub+0x10c>
+    40fe:	4812      	ldr	r0, [pc, #72]	; (4148 <__aeabi_dsub+0x344>)
+    4100:	4285      	cmp	r5, r0
+    4102:	d100      	bne.n	4106 <__aeabi_dsub+0x302>
+    4104:	e085      	b.n	4212 <__aeabi_dsub+0x40e>
+    4106:	001d      	movs	r5, r3
+    4108:	e6bc      	b.n	3e84 <__aeabi_dsub+0x80>
+    410a:	0029      	movs	r1, r5
+    410c:	3e1f      	subs	r6, #31
+    410e:	40f1      	lsrs	r1, r6
+    4110:	2b20      	cmp	r3, #32
+    4112:	d100      	bne.n	4116 <__aeabi_dsub+0x312>
+    4114:	e07f      	b.n	4216 <__aeabi_dsub+0x412>
+    4116:	2240      	movs	r2, #64	; 0x40
+    4118:	1ad3      	subs	r3, r2, r3
+    411a:	409d      	lsls	r5, r3
+    411c:	432f      	orrs	r7, r5
+    411e:	1e7d      	subs	r5, r7, #1
+    4120:	41af      	sbcs	r7, r5
+    4122:	2400      	movs	r4, #0
+    4124:	430f      	orrs	r7, r1
+    4126:	2600      	movs	r6, #0
+    4128:	e78e      	b.n	4048 <__aeabi_dsub+0x244>
+    412a:	002b      	movs	r3, r5
+    412c:	000f      	movs	r7, r1
+    412e:	3b20      	subs	r3, #32
+    4130:	40df      	lsrs	r7, r3
+    4132:	2d20      	cmp	r5, #32
+    4134:	d071      	beq.n	421a <__aeabi_dsub+0x416>
+    4136:	2340      	movs	r3, #64	; 0x40
+    4138:	1b5d      	subs	r5, r3, r5
+    413a:	40a9      	lsls	r1, r5
+    413c:	430a      	orrs	r2, r1
+    413e:	1e51      	subs	r1, r2, #1
+    4140:	418a      	sbcs	r2, r1
+    4142:	2100      	movs	r1, #0
+    4144:	4317      	orrs	r7, r2
+    4146:	e6af      	b.n	3ea8 <__aeabi_dsub+0xa4>
+    4148:	000007ff 	.word	0x000007ff
+    414c:	ff7fffff 	.word	0xff7fffff
+    4150:	800fffff 	.word	0x800fffff
+    4154:	2e00      	cmp	r6, #0
+    4156:	d03e      	beq.n	41d6 <__aeabi_dsub+0x3d2>
+    4158:	4eb3      	ldr	r6, [pc, #716]	; (4428 <__aeabi_dsub+0x624>)
+    415a:	45b4      	cmp	ip, r6
+    415c:	d045      	beq.n	41ea <__aeabi_dsub+0x3e6>
+    415e:	2680      	movs	r6, #128	; 0x80
+    4160:	0436      	lsls	r6, r6, #16
+    4162:	426d      	negs	r5, r5
+    4164:	4334      	orrs	r4, r6
+    4166:	2d38      	cmp	r5, #56	; 0x38
+    4168:	dd00      	ble.n	416c <__aeabi_dsub+0x368>
+    416a:	e0a8      	b.n	42be <__aeabi_dsub+0x4ba>
+    416c:	2d1f      	cmp	r5, #31
+    416e:	dd00      	ble.n	4172 <__aeabi_dsub+0x36e>
+    4170:	e11f      	b.n	43b2 <__aeabi_dsub+0x5ae>
+    4172:	2620      	movs	r6, #32
+    4174:	0027      	movs	r7, r4
+    4176:	4650      	mov	r0, sl
+    4178:	1b76      	subs	r6, r6, r5
+    417a:	40b7      	lsls	r7, r6
+    417c:	40e8      	lsrs	r0, r5
+    417e:	4307      	orrs	r7, r0
+    4180:	4650      	mov	r0, sl
+    4182:	40b0      	lsls	r0, r6
+    4184:	1e46      	subs	r6, r0, #1
+    4186:	41b0      	sbcs	r0, r6
+    4188:	40ec      	lsrs	r4, r5
+    418a:	4338      	orrs	r0, r7
+    418c:	1a17      	subs	r7, r2, r0
+    418e:	42ba      	cmp	r2, r7
+    4190:	4192      	sbcs	r2, r2
+    4192:	1b0c      	subs	r4, r1, r4
+    4194:	4252      	negs	r2, r2
+    4196:	1aa4      	subs	r4, r4, r2
+    4198:	4666      	mov	r6, ip
+    419a:	4698      	mov	r8, r3
+    419c:	e68b      	b.n	3eb6 <__aeabi_dsub+0xb2>
+    419e:	4664      	mov	r4, ip
+    41a0:	4667      	mov	r7, ip
+    41a2:	432c      	orrs	r4, r5
+    41a4:	d000      	beq.n	41a8 <__aeabi_dsub+0x3a4>
+    41a6:	e68b      	b.n	3ec0 <__aeabi_dsub+0xbc>
+    41a8:	2500      	movs	r5, #0
+    41aa:	2600      	movs	r6, #0
+    41ac:	2700      	movs	r7, #0
+    41ae:	e6ea      	b.n	3f86 <__aeabi_dsub+0x182>
+    41b0:	001e      	movs	r6, r3
+    41b2:	e6ad      	b.n	3f10 <__aeabi_dsub+0x10c>
+    41b4:	2b1f      	cmp	r3, #31
+    41b6:	dc60      	bgt.n	427a <__aeabi_dsub+0x476>
+    41b8:	2720      	movs	r7, #32
+    41ba:	1af8      	subs	r0, r7, r3
+    41bc:	000f      	movs	r7, r1
+    41be:	4684      	mov	ip, r0
+    41c0:	4087      	lsls	r7, r0
+    41c2:	0010      	movs	r0, r2
+    41c4:	40d8      	lsrs	r0, r3
+    41c6:	4307      	orrs	r7, r0
+    41c8:	4660      	mov	r0, ip
+    41ca:	4082      	lsls	r2, r0
+    41cc:	1e50      	subs	r0, r2, #1
+    41ce:	4182      	sbcs	r2, r0
+    41d0:	40d9      	lsrs	r1, r3
+    41d2:	4317      	orrs	r7, r2
+    41d4:	e6f5      	b.n	3fc2 <__aeabi_dsub+0x1be>
+    41d6:	0026      	movs	r6, r4
+    41d8:	4650      	mov	r0, sl
+    41da:	4306      	orrs	r6, r0
+    41dc:	d005      	beq.n	41ea <__aeabi_dsub+0x3e6>
+    41de:	43ed      	mvns	r5, r5
+    41e0:	2d00      	cmp	r5, #0
+    41e2:	d0d3      	beq.n	418c <__aeabi_dsub+0x388>
+    41e4:	4e90      	ldr	r6, [pc, #576]	; (4428 <__aeabi_dsub+0x624>)
+    41e6:	45b4      	cmp	ip, r6
+    41e8:	d1bd      	bne.n	4166 <__aeabi_dsub+0x362>
+    41ea:	000c      	movs	r4, r1
+    41ec:	0017      	movs	r7, r2
+    41ee:	4666      	mov	r6, ip
+    41f0:	4698      	mov	r8, r3
+    41f2:	e68d      	b.n	3f10 <__aeabi_dsub+0x10c>
+    41f4:	488c      	ldr	r0, [pc, #560]	; (4428 <__aeabi_dsub+0x624>)
+    41f6:	4283      	cmp	r3, r0
+    41f8:	d00b      	beq.n	4212 <__aeabi_dsub+0x40e>
+    41fa:	4663      	mov	r3, ip
+    41fc:	e6d9      	b.n	3fb2 <__aeabi_dsub+0x1ae>
+    41fe:	2d00      	cmp	r5, #0
+    4200:	d000      	beq.n	4204 <__aeabi_dsub+0x400>
+    4202:	e096      	b.n	4332 <__aeabi_dsub+0x52e>
+    4204:	0008      	movs	r0, r1
+    4206:	4310      	orrs	r0, r2
+    4208:	d100      	bne.n	420c <__aeabi_dsub+0x408>
+    420a:	e0e2      	b.n	43d2 <__aeabi_dsub+0x5ce>
+    420c:	000c      	movs	r4, r1
+    420e:	0017      	movs	r7, r2
+    4210:	4698      	mov	r8, r3
+    4212:	4e85      	ldr	r6, [pc, #532]	; (4428 <__aeabi_dsub+0x624>)
+    4214:	e67c      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4216:	2500      	movs	r5, #0
+    4218:	e780      	b.n	411c <__aeabi_dsub+0x318>
+    421a:	2100      	movs	r1, #0
+    421c:	e78e      	b.n	413c <__aeabi_dsub+0x338>
+    421e:	0023      	movs	r3, r4
+    4220:	4650      	mov	r0, sl
+    4222:	4303      	orrs	r3, r0
+    4224:	2e00      	cmp	r6, #0
+    4226:	d000      	beq.n	422a <__aeabi_dsub+0x426>
+    4228:	e0a8      	b.n	437c <__aeabi_dsub+0x578>
+    422a:	2b00      	cmp	r3, #0
+    422c:	d100      	bne.n	4230 <__aeabi_dsub+0x42c>
+    422e:	e0de      	b.n	43ee <__aeabi_dsub+0x5ea>
+    4230:	000b      	movs	r3, r1
+    4232:	4313      	orrs	r3, r2
+    4234:	d100      	bne.n	4238 <__aeabi_dsub+0x434>
+    4236:	e66b      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4238:	4452      	add	r2, sl
+    423a:	4552      	cmp	r2, sl
+    423c:	4180      	sbcs	r0, r0
+    423e:	1864      	adds	r4, r4, r1
+    4240:	4240      	negs	r0, r0
+    4242:	1824      	adds	r4, r4, r0
+    4244:	0017      	movs	r7, r2
+    4246:	0223      	lsls	r3, r4, #8
+    4248:	d400      	bmi.n	424c <__aeabi_dsub+0x448>
+    424a:	e6fd      	b.n	4048 <__aeabi_dsub+0x244>
+    424c:	4b77      	ldr	r3, [pc, #476]	; (442c <__aeabi_dsub+0x628>)
+    424e:	4666      	mov	r6, ip
+    4250:	401c      	ands	r4, r3
+    4252:	e65d      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4254:	0025      	movs	r5, r4
+    4256:	4650      	mov	r0, sl
+    4258:	4305      	orrs	r5, r0
+    425a:	2e00      	cmp	r6, #0
+    425c:	d1cf      	bne.n	41fe <__aeabi_dsub+0x3fa>
+    425e:	2d00      	cmp	r5, #0
+    4260:	d14f      	bne.n	4302 <__aeabi_dsub+0x4fe>
+    4262:	000c      	movs	r4, r1
+    4264:	4314      	orrs	r4, r2
+    4266:	d100      	bne.n	426a <__aeabi_dsub+0x466>
+    4268:	e0a0      	b.n	43ac <__aeabi_dsub+0x5a8>
+    426a:	000c      	movs	r4, r1
+    426c:	0017      	movs	r7, r2
+    426e:	4698      	mov	r8, r3
+    4270:	e64e      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4272:	4666      	mov	r6, ip
+    4274:	2400      	movs	r4, #0
+    4276:	2700      	movs	r7, #0
+    4278:	e685      	b.n	3f86 <__aeabi_dsub+0x182>
+    427a:	001f      	movs	r7, r3
+    427c:	0008      	movs	r0, r1
+    427e:	3f20      	subs	r7, #32
+    4280:	40f8      	lsrs	r0, r7
+    4282:	0007      	movs	r7, r0
+    4284:	2b20      	cmp	r3, #32
+    4286:	d100      	bne.n	428a <__aeabi_dsub+0x486>
+    4288:	e08e      	b.n	43a8 <__aeabi_dsub+0x5a4>
+    428a:	2040      	movs	r0, #64	; 0x40
+    428c:	1ac3      	subs	r3, r0, r3
+    428e:	4099      	lsls	r1, r3
+    4290:	430a      	orrs	r2, r1
+    4292:	1e51      	subs	r1, r2, #1
+    4294:	418a      	sbcs	r2, r1
+    4296:	2100      	movs	r1, #0
+    4298:	4317      	orrs	r7, r2
+    429a:	e692      	b.n	3fc2 <__aeabi_dsub+0x1be>
+    429c:	2e00      	cmp	r6, #0
+    429e:	d114      	bne.n	42ca <__aeabi_dsub+0x4c6>
+    42a0:	0026      	movs	r6, r4
+    42a2:	4650      	mov	r0, sl
+    42a4:	4306      	orrs	r6, r0
+    42a6:	d062      	beq.n	436e <__aeabi_dsub+0x56a>
+    42a8:	43db      	mvns	r3, r3
+    42aa:	2b00      	cmp	r3, #0
+    42ac:	d15c      	bne.n	4368 <__aeabi_dsub+0x564>
+    42ae:	1887      	adds	r7, r0, r2
+    42b0:	4297      	cmp	r7, r2
+    42b2:	4192      	sbcs	r2, r2
+    42b4:	1864      	adds	r4, r4, r1
+    42b6:	4252      	negs	r2, r2
+    42b8:	18a4      	adds	r4, r4, r2
+    42ba:	4666      	mov	r6, ip
+    42bc:	e687      	b.n	3fce <__aeabi_dsub+0x1ca>
+    42be:	4650      	mov	r0, sl
+    42c0:	4320      	orrs	r0, r4
+    42c2:	1e44      	subs	r4, r0, #1
+    42c4:	41a0      	sbcs	r0, r4
+    42c6:	2400      	movs	r4, #0
+    42c8:	e760      	b.n	418c <__aeabi_dsub+0x388>
+    42ca:	4e57      	ldr	r6, [pc, #348]	; (4428 <__aeabi_dsub+0x624>)
+    42cc:	45b4      	cmp	ip, r6
+    42ce:	d04e      	beq.n	436e <__aeabi_dsub+0x56a>
+    42d0:	2680      	movs	r6, #128	; 0x80
+    42d2:	0436      	lsls	r6, r6, #16
+    42d4:	425b      	negs	r3, r3
+    42d6:	4334      	orrs	r4, r6
+    42d8:	2b38      	cmp	r3, #56	; 0x38
+    42da:	dd00      	ble.n	42de <__aeabi_dsub+0x4da>
+    42dc:	e07f      	b.n	43de <__aeabi_dsub+0x5da>
+    42de:	2b1f      	cmp	r3, #31
+    42e0:	dd00      	ble.n	42e4 <__aeabi_dsub+0x4e0>
+    42e2:	e08b      	b.n	43fc <__aeabi_dsub+0x5f8>
+    42e4:	2620      	movs	r6, #32
+    42e6:	0027      	movs	r7, r4
+    42e8:	4650      	mov	r0, sl
+    42ea:	1af6      	subs	r6, r6, r3
+    42ec:	40b7      	lsls	r7, r6
+    42ee:	40d8      	lsrs	r0, r3
+    42f0:	4307      	orrs	r7, r0
+    42f2:	4650      	mov	r0, sl
+    42f4:	40b0      	lsls	r0, r6
+    42f6:	1e46      	subs	r6, r0, #1
+    42f8:	41b0      	sbcs	r0, r6
+    42fa:	4307      	orrs	r7, r0
+    42fc:	40dc      	lsrs	r4, r3
+    42fe:	18bf      	adds	r7, r7, r2
+    4300:	e7d6      	b.n	42b0 <__aeabi_dsub+0x4ac>
+    4302:	000d      	movs	r5, r1
+    4304:	4315      	orrs	r5, r2
+    4306:	d100      	bne.n	430a <__aeabi_dsub+0x506>
+    4308:	e602      	b.n	3f10 <__aeabi_dsub+0x10c>
+    430a:	4650      	mov	r0, sl
+    430c:	1a80      	subs	r0, r0, r2
+    430e:	4582      	cmp	sl, r0
+    4310:	41bf      	sbcs	r7, r7
+    4312:	1a65      	subs	r5, r4, r1
+    4314:	427f      	negs	r7, r7
+    4316:	1bed      	subs	r5, r5, r7
+    4318:	4684      	mov	ip, r0
+    431a:	0228      	lsls	r0, r5, #8
+    431c:	d400      	bmi.n	4320 <__aeabi_dsub+0x51c>
+    431e:	e68d      	b.n	403c <__aeabi_dsub+0x238>
+    4320:	4650      	mov	r0, sl
+    4322:	1a17      	subs	r7, r2, r0
+    4324:	42ba      	cmp	r2, r7
+    4326:	4192      	sbcs	r2, r2
+    4328:	1b0c      	subs	r4, r1, r4
+    432a:	4252      	negs	r2, r2
+    432c:	1aa4      	subs	r4, r4, r2
+    432e:	4698      	mov	r8, r3
+    4330:	e5ee      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4332:	000d      	movs	r5, r1
+    4334:	4315      	orrs	r5, r2
+    4336:	d100      	bne.n	433a <__aeabi_dsub+0x536>
+    4338:	e76b      	b.n	4212 <__aeabi_dsub+0x40e>
+    433a:	4650      	mov	r0, sl
+    433c:	0767      	lsls	r7, r4, #29
+    433e:	08c0      	lsrs	r0, r0, #3
+    4340:	4307      	orrs	r7, r0
+    4342:	2080      	movs	r0, #128	; 0x80
+    4344:	08e4      	lsrs	r4, r4, #3
+    4346:	0300      	lsls	r0, r0, #12
+    4348:	4204      	tst	r4, r0
+    434a:	d007      	beq.n	435c <__aeabi_dsub+0x558>
+    434c:	08cd      	lsrs	r5, r1, #3
+    434e:	4205      	tst	r5, r0
+    4350:	d104      	bne.n	435c <__aeabi_dsub+0x558>
+    4352:	002c      	movs	r4, r5
+    4354:	4698      	mov	r8, r3
+    4356:	08d7      	lsrs	r7, r2, #3
+    4358:	0749      	lsls	r1, r1, #29
+    435a:	430f      	orrs	r7, r1
+    435c:	0f7b      	lsrs	r3, r7, #29
+    435e:	00e4      	lsls	r4, r4, #3
+    4360:	431c      	orrs	r4, r3
+    4362:	00ff      	lsls	r7, r7, #3
+    4364:	4e30      	ldr	r6, [pc, #192]	; (4428 <__aeabi_dsub+0x624>)
+    4366:	e5d3      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4368:	4e2f      	ldr	r6, [pc, #188]	; (4428 <__aeabi_dsub+0x624>)
+    436a:	45b4      	cmp	ip, r6
+    436c:	d1b4      	bne.n	42d8 <__aeabi_dsub+0x4d4>
+    436e:	000c      	movs	r4, r1
+    4370:	0017      	movs	r7, r2
+    4372:	4666      	mov	r6, ip
+    4374:	e5cc      	b.n	3f10 <__aeabi_dsub+0x10c>
+    4376:	2700      	movs	r7, #0
+    4378:	2400      	movs	r4, #0
+    437a:	e5e8      	b.n	3f4e <__aeabi_dsub+0x14a>
+    437c:	2b00      	cmp	r3, #0
+    437e:	d039      	beq.n	43f4 <__aeabi_dsub+0x5f0>
+    4380:	000b      	movs	r3, r1
+    4382:	4313      	orrs	r3, r2
+    4384:	d100      	bne.n	4388 <__aeabi_dsub+0x584>
+    4386:	e744      	b.n	4212 <__aeabi_dsub+0x40e>
+    4388:	08c0      	lsrs	r0, r0, #3
+    438a:	0767      	lsls	r7, r4, #29
+    438c:	4307      	orrs	r7, r0
+    438e:	2080      	movs	r0, #128	; 0x80
+    4390:	08e4      	lsrs	r4, r4, #3
+    4392:	0300      	lsls	r0, r0, #12
+    4394:	4204      	tst	r4, r0
+    4396:	d0e1      	beq.n	435c <__aeabi_dsub+0x558>
+    4398:	08cb      	lsrs	r3, r1, #3
+    439a:	4203      	tst	r3, r0
+    439c:	d1de      	bne.n	435c <__aeabi_dsub+0x558>
+    439e:	08d7      	lsrs	r7, r2, #3
+    43a0:	0749      	lsls	r1, r1, #29
+    43a2:	430f      	orrs	r7, r1
+    43a4:	001c      	movs	r4, r3
+    43a6:	e7d9      	b.n	435c <__aeabi_dsub+0x558>
+    43a8:	2100      	movs	r1, #0
+    43aa:	e771      	b.n	4290 <__aeabi_dsub+0x48c>
+    43ac:	2500      	movs	r5, #0
+    43ae:	2700      	movs	r7, #0
+    43b0:	e5e9      	b.n	3f86 <__aeabi_dsub+0x182>
+    43b2:	002e      	movs	r6, r5
+    43b4:	0027      	movs	r7, r4
+    43b6:	3e20      	subs	r6, #32
+    43b8:	40f7      	lsrs	r7, r6
+    43ba:	2d20      	cmp	r5, #32
+    43bc:	d02f      	beq.n	441e <__aeabi_dsub+0x61a>
+    43be:	2640      	movs	r6, #64	; 0x40
+    43c0:	1b75      	subs	r5, r6, r5
+    43c2:	40ac      	lsls	r4, r5
+    43c4:	4650      	mov	r0, sl
+    43c6:	4320      	orrs	r0, r4
+    43c8:	1e44      	subs	r4, r0, #1
+    43ca:	41a0      	sbcs	r0, r4
+    43cc:	2400      	movs	r4, #0
+    43ce:	4338      	orrs	r0, r7
+    43d0:	e6dc      	b.n	418c <__aeabi_dsub+0x388>
+    43d2:	2480      	movs	r4, #128	; 0x80
+    43d4:	2500      	movs	r5, #0
+    43d6:	0324      	lsls	r4, r4, #12
+    43d8:	4e13      	ldr	r6, [pc, #76]	; (4428 <__aeabi_dsub+0x624>)
+    43da:	2700      	movs	r7, #0
+    43dc:	e5d3      	b.n	3f86 <__aeabi_dsub+0x182>
+    43de:	4650      	mov	r0, sl
+    43e0:	4320      	orrs	r0, r4
+    43e2:	0007      	movs	r7, r0
+    43e4:	1e78      	subs	r0, r7, #1
+    43e6:	4187      	sbcs	r7, r0
+    43e8:	2400      	movs	r4, #0
+    43ea:	18bf      	adds	r7, r7, r2
+    43ec:	e760      	b.n	42b0 <__aeabi_dsub+0x4ac>
+    43ee:	000c      	movs	r4, r1
+    43f0:	0017      	movs	r7, r2
+    43f2:	e58d      	b.n	3f10 <__aeabi_dsub+0x10c>
+    43f4:	000c      	movs	r4, r1
+    43f6:	0017      	movs	r7, r2
+    43f8:	4e0b      	ldr	r6, [pc, #44]	; (4428 <__aeabi_dsub+0x624>)
+    43fa:	e589      	b.n	3f10 <__aeabi_dsub+0x10c>
+    43fc:	001e      	movs	r6, r3
+    43fe:	0027      	movs	r7, r4
+    4400:	3e20      	subs	r6, #32
+    4402:	40f7      	lsrs	r7, r6
+    4404:	2b20      	cmp	r3, #32
+    4406:	d00c      	beq.n	4422 <__aeabi_dsub+0x61e>
+    4408:	2640      	movs	r6, #64	; 0x40
+    440a:	1af3      	subs	r3, r6, r3
+    440c:	409c      	lsls	r4, r3
+    440e:	4650      	mov	r0, sl
+    4410:	4320      	orrs	r0, r4
+    4412:	1e44      	subs	r4, r0, #1
+    4414:	41a0      	sbcs	r0, r4
+    4416:	4307      	orrs	r7, r0
+    4418:	2400      	movs	r4, #0
+    441a:	18bf      	adds	r7, r7, r2
+    441c:	e748      	b.n	42b0 <__aeabi_dsub+0x4ac>
+    441e:	2400      	movs	r4, #0
+    4420:	e7d0      	b.n	43c4 <__aeabi_dsub+0x5c0>
+    4422:	2400      	movs	r4, #0
+    4424:	e7f3      	b.n	440e <__aeabi_dsub+0x60a>
+    4426:	46c0      	nop			; (mov r8, r8)
+    4428:	000007ff 	.word	0x000007ff
+    442c:	ff7fffff 	.word	0xff7fffff
+
+00004430 <__aeabi_dcmpun>:
+    4430:	b570      	push	{r4, r5, r6, lr}
+    4432:	4e0e      	ldr	r6, [pc, #56]	; (446c <__aeabi_dcmpun+0x3c>)
+    4434:	030d      	lsls	r5, r1, #12
+    4436:	031c      	lsls	r4, r3, #12
+    4438:	0049      	lsls	r1, r1, #1
+    443a:	005b      	lsls	r3, r3, #1
+    443c:	0b2d      	lsrs	r5, r5, #12
+    443e:	0d49      	lsrs	r1, r1, #21
+    4440:	0b24      	lsrs	r4, r4, #12
+    4442:	0d5b      	lsrs	r3, r3, #21
+    4444:	42b1      	cmp	r1, r6
+    4446:	d004      	beq.n	4452 <__aeabi_dcmpun+0x22>
+    4448:	4908      	ldr	r1, [pc, #32]	; (446c <__aeabi_dcmpun+0x3c>)
+    444a:	2000      	movs	r0, #0
+    444c:	428b      	cmp	r3, r1
+    444e:	d008      	beq.n	4462 <__aeabi_dcmpun+0x32>
+    4450:	bd70      	pop	{r4, r5, r6, pc}
+    4452:	4305      	orrs	r5, r0
+    4454:	2001      	movs	r0, #1
+    4456:	2d00      	cmp	r5, #0
+    4458:	d1fa      	bne.n	4450 <__aeabi_dcmpun+0x20>
+    445a:	4904      	ldr	r1, [pc, #16]	; (446c <__aeabi_dcmpun+0x3c>)
+    445c:	2000      	movs	r0, #0
+    445e:	428b      	cmp	r3, r1
+    4460:	d1f6      	bne.n	4450 <__aeabi_dcmpun+0x20>
+    4462:	4314      	orrs	r4, r2
+    4464:	0020      	movs	r0, r4
+    4466:	1e44      	subs	r4, r0, #1
+    4468:	41a0      	sbcs	r0, r4
+    446a:	e7f1      	b.n	4450 <__aeabi_dcmpun+0x20>
+    446c:	000007ff 	.word	0x000007ff
+
+00004470 <__aeabi_d2iz>:
+    4470:	b530      	push	{r4, r5, lr}
+    4472:	4d13      	ldr	r5, [pc, #76]	; (44c0 <__aeabi_d2iz+0x50>)
+    4474:	030a      	lsls	r2, r1, #12
+    4476:	004b      	lsls	r3, r1, #1
+    4478:	0b12      	lsrs	r2, r2, #12
+    447a:	0d5b      	lsrs	r3, r3, #21
+    447c:	0fc9      	lsrs	r1, r1, #31
+    447e:	2400      	movs	r4, #0
+    4480:	42ab      	cmp	r3, r5
+    4482:	dd10      	ble.n	44a6 <__aeabi_d2iz+0x36>
+    4484:	4c0f      	ldr	r4, [pc, #60]	; (44c4 <__aeabi_d2iz+0x54>)
+    4486:	42a3      	cmp	r3, r4
+    4488:	dc0f      	bgt.n	44aa <__aeabi_d2iz+0x3a>
+    448a:	2480      	movs	r4, #128	; 0x80
+    448c:	4d0e      	ldr	r5, [pc, #56]	; (44c8 <__aeabi_d2iz+0x58>)
+    448e:	0364      	lsls	r4, r4, #13
+    4490:	4322      	orrs	r2, r4
+    4492:	1aed      	subs	r5, r5, r3
+    4494:	2d1f      	cmp	r5, #31
+    4496:	dd0b      	ble.n	44b0 <__aeabi_d2iz+0x40>
+    4498:	480c      	ldr	r0, [pc, #48]	; (44cc <__aeabi_d2iz+0x5c>)
+    449a:	1ac3      	subs	r3, r0, r3
+    449c:	40da      	lsrs	r2, r3
+    449e:	4254      	negs	r4, r2
+    44a0:	2900      	cmp	r1, #0
+    44a2:	d100      	bne.n	44a6 <__aeabi_d2iz+0x36>
+    44a4:	0014      	movs	r4, r2
+    44a6:	0020      	movs	r0, r4
+    44a8:	bd30      	pop	{r4, r5, pc}
+    44aa:	4b09      	ldr	r3, [pc, #36]	; (44d0 <__aeabi_d2iz+0x60>)
+    44ac:	18cc      	adds	r4, r1, r3
+    44ae:	e7fa      	b.n	44a6 <__aeabi_d2iz+0x36>
+    44b0:	4c08      	ldr	r4, [pc, #32]	; (44d4 <__aeabi_d2iz+0x64>)
+    44b2:	40e8      	lsrs	r0, r5
+    44b4:	46a4      	mov	ip, r4
+    44b6:	4463      	add	r3, ip
+    44b8:	409a      	lsls	r2, r3
+    44ba:	4302      	orrs	r2, r0
+    44bc:	e7ef      	b.n	449e <__aeabi_d2iz+0x2e>
+    44be:	46c0      	nop			; (mov r8, r8)
+    44c0:	000003fe 	.word	0x000003fe
+    44c4:	0000041d 	.word	0x0000041d
+    44c8:	00000433 	.word	0x00000433
+    44cc:	00000413 	.word	0x00000413
+    44d0:	7fffffff 	.word	0x7fffffff
+    44d4:	fffffbed 	.word	0xfffffbed
+
+000044d8 <__aeabi_i2d>:
+    44d8:	b570      	push	{r4, r5, r6, lr}
+    44da:	2800      	cmp	r0, #0
+    44dc:	d030      	beq.n	4540 <__aeabi_i2d+0x68>
+    44de:	17c3      	asrs	r3, r0, #31
+    44e0:	18c4      	adds	r4, r0, r3
+    44e2:	405c      	eors	r4, r3
+    44e4:	0fc5      	lsrs	r5, r0, #31
+    44e6:	0020      	movs	r0, r4
+    44e8:	f000 f94c 	bl	4784 <__clzsi2>
+    44ec:	4b17      	ldr	r3, [pc, #92]	; (454c <__aeabi_i2d+0x74>)
+    44ee:	4a18      	ldr	r2, [pc, #96]	; (4550 <__aeabi_i2d+0x78>)
+    44f0:	1a1b      	subs	r3, r3, r0
+    44f2:	1ad2      	subs	r2, r2, r3
+    44f4:	2a1f      	cmp	r2, #31
+    44f6:	dd18      	ble.n	452a <__aeabi_i2d+0x52>
+    44f8:	4a16      	ldr	r2, [pc, #88]	; (4554 <__aeabi_i2d+0x7c>)
+    44fa:	1ad2      	subs	r2, r2, r3
+    44fc:	4094      	lsls	r4, r2
+    44fe:	2200      	movs	r2, #0
+    4500:	0324      	lsls	r4, r4, #12
+    4502:	055b      	lsls	r3, r3, #21
+    4504:	0b24      	lsrs	r4, r4, #12
+    4506:	0d5b      	lsrs	r3, r3, #21
+    4508:	2100      	movs	r1, #0
+    450a:	0010      	movs	r0, r2
+    450c:	0324      	lsls	r4, r4, #12
+    450e:	0d0a      	lsrs	r2, r1, #20
+    4510:	0b24      	lsrs	r4, r4, #12
+    4512:	0512      	lsls	r2, r2, #20
+    4514:	4322      	orrs	r2, r4
+    4516:	4c10      	ldr	r4, [pc, #64]	; (4558 <__aeabi_i2d+0x80>)
+    4518:	051b      	lsls	r3, r3, #20
+    451a:	4022      	ands	r2, r4
+    451c:	4313      	orrs	r3, r2
+    451e:	005b      	lsls	r3, r3, #1
+    4520:	07ed      	lsls	r5, r5, #31
+    4522:	085b      	lsrs	r3, r3, #1
+    4524:	432b      	orrs	r3, r5
+    4526:	0019      	movs	r1, r3
+    4528:	bd70      	pop	{r4, r5, r6, pc}
+    452a:	0021      	movs	r1, r4
+    452c:	4091      	lsls	r1, r2
+    452e:	000a      	movs	r2, r1
+    4530:	210b      	movs	r1, #11
+    4532:	1a08      	subs	r0, r1, r0
+    4534:	40c4      	lsrs	r4, r0
+    4536:	055b      	lsls	r3, r3, #21
+    4538:	0324      	lsls	r4, r4, #12
+    453a:	0b24      	lsrs	r4, r4, #12
+    453c:	0d5b      	lsrs	r3, r3, #21
+    453e:	e7e3      	b.n	4508 <__aeabi_i2d+0x30>
+    4540:	2500      	movs	r5, #0
+    4542:	2300      	movs	r3, #0
+    4544:	2400      	movs	r4, #0
+    4546:	2200      	movs	r2, #0
+    4548:	e7de      	b.n	4508 <__aeabi_i2d+0x30>
+    454a:	46c0      	nop			; (mov r8, r8)
+    454c:	0000041e 	.word	0x0000041e
+    4550:	00000433 	.word	0x00000433
+    4554:	00000413 	.word	0x00000413
+    4558:	800fffff 	.word	0x800fffff
+
+0000455c <__aeabi_ui2d>:
+    455c:	b510      	push	{r4, lr}
+    455e:	1e04      	subs	r4, r0, #0
+    4560:	d028      	beq.n	45b4 <__aeabi_ui2d+0x58>
+    4562:	f000 f90f 	bl	4784 <__clzsi2>
+    4566:	4b15      	ldr	r3, [pc, #84]	; (45bc <__aeabi_ui2d+0x60>)
+    4568:	4a15      	ldr	r2, [pc, #84]	; (45c0 <__aeabi_ui2d+0x64>)
+    456a:	1a1b      	subs	r3, r3, r0
+    456c:	1ad2      	subs	r2, r2, r3
+    456e:	2a1f      	cmp	r2, #31
+    4570:	dd15      	ble.n	459e <__aeabi_ui2d+0x42>
+    4572:	4a14      	ldr	r2, [pc, #80]	; (45c4 <__aeabi_ui2d+0x68>)
+    4574:	1ad2      	subs	r2, r2, r3
+    4576:	4094      	lsls	r4, r2
+    4578:	2200      	movs	r2, #0
+    457a:	0324      	lsls	r4, r4, #12
+    457c:	055b      	lsls	r3, r3, #21
+    457e:	0b24      	lsrs	r4, r4, #12
+    4580:	0d5b      	lsrs	r3, r3, #21
+    4582:	2100      	movs	r1, #0
+    4584:	0010      	movs	r0, r2
+    4586:	0324      	lsls	r4, r4, #12
+    4588:	0d0a      	lsrs	r2, r1, #20
+    458a:	0b24      	lsrs	r4, r4, #12
+    458c:	0512      	lsls	r2, r2, #20
+    458e:	4322      	orrs	r2, r4
+    4590:	4c0d      	ldr	r4, [pc, #52]	; (45c8 <__aeabi_ui2d+0x6c>)
+    4592:	051b      	lsls	r3, r3, #20
+    4594:	4022      	ands	r2, r4
+    4596:	4313      	orrs	r3, r2
+    4598:	005b      	lsls	r3, r3, #1
+    459a:	0859      	lsrs	r1, r3, #1
+    459c:	bd10      	pop	{r4, pc}
+    459e:	0021      	movs	r1, r4
+    45a0:	4091      	lsls	r1, r2
+    45a2:	000a      	movs	r2, r1
+    45a4:	210b      	movs	r1, #11
+    45a6:	1a08      	subs	r0, r1, r0
+    45a8:	40c4      	lsrs	r4, r0
+    45aa:	055b      	lsls	r3, r3, #21
+    45ac:	0324      	lsls	r4, r4, #12
+    45ae:	0b24      	lsrs	r4, r4, #12
+    45b0:	0d5b      	lsrs	r3, r3, #21
+    45b2:	e7e6      	b.n	4582 <__aeabi_ui2d+0x26>
+    45b4:	2300      	movs	r3, #0
+    45b6:	2400      	movs	r4, #0
+    45b8:	2200      	movs	r2, #0
+    45ba:	e7e2      	b.n	4582 <__aeabi_ui2d+0x26>
+    45bc:	0000041e 	.word	0x0000041e
+    45c0:	00000433 	.word	0x00000433
+    45c4:	00000413 	.word	0x00000413
+    45c8:	800fffff 	.word	0x800fffff
+
+000045cc <__aeabi_f2d>:
+    45cc:	0041      	lsls	r1, r0, #1
+    45ce:	0e09      	lsrs	r1, r1, #24
+    45d0:	1c4b      	adds	r3, r1, #1
+    45d2:	b570      	push	{r4, r5, r6, lr}
+    45d4:	b2db      	uxtb	r3, r3
+    45d6:	0246      	lsls	r6, r0, #9
+    45d8:	0a75      	lsrs	r5, r6, #9
+    45da:	0fc4      	lsrs	r4, r0, #31
+    45dc:	2b01      	cmp	r3, #1
+    45de:	dd14      	ble.n	460a <__aeabi_f2d+0x3e>
+    45e0:	23e0      	movs	r3, #224	; 0xe0
+    45e2:	009b      	lsls	r3, r3, #2
+    45e4:	076d      	lsls	r5, r5, #29
+    45e6:	0b36      	lsrs	r6, r6, #12
+    45e8:	18cb      	adds	r3, r1, r3
+    45ea:	2100      	movs	r1, #0
+    45ec:	0d0a      	lsrs	r2, r1, #20
+    45ee:	0028      	movs	r0, r5
+    45f0:	0512      	lsls	r2, r2, #20
+    45f2:	4d1c      	ldr	r5, [pc, #112]	; (4664 <__aeabi_f2d+0x98>)
+    45f4:	4332      	orrs	r2, r6
+    45f6:	055b      	lsls	r3, r3, #21
+    45f8:	402a      	ands	r2, r5
+    45fa:	085b      	lsrs	r3, r3, #1
+    45fc:	4313      	orrs	r3, r2
+    45fe:	005b      	lsls	r3, r3, #1
+    4600:	07e4      	lsls	r4, r4, #31
+    4602:	085b      	lsrs	r3, r3, #1
+    4604:	4323      	orrs	r3, r4
+    4606:	0019      	movs	r1, r3
+    4608:	bd70      	pop	{r4, r5, r6, pc}
+    460a:	2900      	cmp	r1, #0
+    460c:	d114      	bne.n	4638 <__aeabi_f2d+0x6c>
+    460e:	2d00      	cmp	r5, #0
+    4610:	d01e      	beq.n	4650 <__aeabi_f2d+0x84>
+    4612:	0028      	movs	r0, r5
+    4614:	f000 f8b6 	bl	4784 <__clzsi2>
+    4618:	280a      	cmp	r0, #10
+    461a:	dc1c      	bgt.n	4656 <__aeabi_f2d+0x8a>
+    461c:	230b      	movs	r3, #11
+    461e:	002a      	movs	r2, r5
+    4620:	1a1b      	subs	r3, r3, r0
+    4622:	40da      	lsrs	r2, r3
+    4624:	0003      	movs	r3, r0
+    4626:	3315      	adds	r3, #21
+    4628:	409d      	lsls	r5, r3
+    462a:	4b0f      	ldr	r3, [pc, #60]	; (4668 <__aeabi_f2d+0x9c>)
+    462c:	0312      	lsls	r2, r2, #12
+    462e:	1a1b      	subs	r3, r3, r0
+    4630:	055b      	lsls	r3, r3, #21
+    4632:	0b16      	lsrs	r6, r2, #12
+    4634:	0d5b      	lsrs	r3, r3, #21
+    4636:	e7d8      	b.n	45ea <__aeabi_f2d+0x1e>
+    4638:	2d00      	cmp	r5, #0
+    463a:	d006      	beq.n	464a <__aeabi_f2d+0x7e>
+    463c:	0b32      	lsrs	r2, r6, #12
+    463e:	2680      	movs	r6, #128	; 0x80
+    4640:	0336      	lsls	r6, r6, #12
+    4642:	076d      	lsls	r5, r5, #29
+    4644:	4316      	orrs	r6, r2
+    4646:	4b09      	ldr	r3, [pc, #36]	; (466c <__aeabi_f2d+0xa0>)
+    4648:	e7cf      	b.n	45ea <__aeabi_f2d+0x1e>
+    464a:	4b08      	ldr	r3, [pc, #32]	; (466c <__aeabi_f2d+0xa0>)
+    464c:	2600      	movs	r6, #0
+    464e:	e7cc      	b.n	45ea <__aeabi_f2d+0x1e>
+    4650:	2300      	movs	r3, #0
+    4652:	2600      	movs	r6, #0
+    4654:	e7c9      	b.n	45ea <__aeabi_f2d+0x1e>
+    4656:	0003      	movs	r3, r0
+    4658:	002a      	movs	r2, r5
+    465a:	3b0b      	subs	r3, #11
+    465c:	409a      	lsls	r2, r3
+    465e:	2500      	movs	r5, #0
+    4660:	e7e3      	b.n	462a <__aeabi_f2d+0x5e>
+    4662:	46c0      	nop			; (mov r8, r8)
+    4664:	800fffff 	.word	0x800fffff
+    4668:	00000389 	.word	0x00000389
+    466c:	000007ff 	.word	0x000007ff
+
+00004670 <__aeabi_d2f>:
+    4670:	b5f0      	push	{r4, r5, r6, r7, lr}
+    4672:	004c      	lsls	r4, r1, #1
+    4674:	0d64      	lsrs	r4, r4, #21
+    4676:	030b      	lsls	r3, r1, #12
+    4678:	1c62      	adds	r2, r4, #1
+    467a:	0f45      	lsrs	r5, r0, #29
+    467c:	0a5b      	lsrs	r3, r3, #9
+    467e:	0552      	lsls	r2, r2, #21
+    4680:	432b      	orrs	r3, r5
+    4682:	0fc9      	lsrs	r1, r1, #31
+    4684:	00c5      	lsls	r5, r0, #3
+    4686:	0d52      	lsrs	r2, r2, #21
+    4688:	2a01      	cmp	r2, #1
+    468a:	dd28      	ble.n	46de <__aeabi_d2f+0x6e>
+    468c:	4a3a      	ldr	r2, [pc, #232]	; (4778 <__aeabi_d2f+0x108>)
+    468e:	18a6      	adds	r6, r4, r2
+    4690:	2efe      	cmp	r6, #254	; 0xfe
+    4692:	dc1b      	bgt.n	46cc <__aeabi_d2f+0x5c>
+    4694:	2e00      	cmp	r6, #0
+    4696:	dd3e      	ble.n	4716 <__aeabi_d2f+0xa6>
+    4698:	0180      	lsls	r0, r0, #6
+    469a:	0002      	movs	r2, r0
+    469c:	1e50      	subs	r0, r2, #1
+    469e:	4182      	sbcs	r2, r0
+    46a0:	0f6d      	lsrs	r5, r5, #29
+    46a2:	432a      	orrs	r2, r5
+    46a4:	00db      	lsls	r3, r3, #3
+    46a6:	4313      	orrs	r3, r2
+    46a8:	075a      	lsls	r2, r3, #29
+    46aa:	d004      	beq.n	46b6 <__aeabi_d2f+0x46>
+    46ac:	220f      	movs	r2, #15
+    46ae:	401a      	ands	r2, r3
+    46b0:	2a04      	cmp	r2, #4
+    46b2:	d000      	beq.n	46b6 <__aeabi_d2f+0x46>
+    46b4:	3304      	adds	r3, #4
+    46b6:	2280      	movs	r2, #128	; 0x80
+    46b8:	04d2      	lsls	r2, r2, #19
+    46ba:	401a      	ands	r2, r3
+    46bc:	d05a      	beq.n	4774 <__aeabi_d2f+0x104>
+    46be:	3601      	adds	r6, #1
+    46c0:	2eff      	cmp	r6, #255	; 0xff
+    46c2:	d003      	beq.n	46cc <__aeabi_d2f+0x5c>
+    46c4:	019b      	lsls	r3, r3, #6
+    46c6:	0a5b      	lsrs	r3, r3, #9
+    46c8:	b2f4      	uxtb	r4, r6
+    46ca:	e001      	b.n	46d0 <__aeabi_d2f+0x60>
+    46cc:	24ff      	movs	r4, #255	; 0xff
+    46ce:	2300      	movs	r3, #0
+    46d0:	0258      	lsls	r0, r3, #9
+    46d2:	05e4      	lsls	r4, r4, #23
+    46d4:	0a40      	lsrs	r0, r0, #9
+    46d6:	07c9      	lsls	r1, r1, #31
+    46d8:	4320      	orrs	r0, r4
+    46da:	4308      	orrs	r0, r1
+    46dc:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    46de:	2c00      	cmp	r4, #0
+    46e0:	d007      	beq.n	46f2 <__aeabi_d2f+0x82>
+    46e2:	431d      	orrs	r5, r3
+    46e4:	d0f2      	beq.n	46cc <__aeabi_d2f+0x5c>
+    46e6:	2080      	movs	r0, #128	; 0x80
+    46e8:	00db      	lsls	r3, r3, #3
+    46ea:	0480      	lsls	r0, r0, #18
+    46ec:	4303      	orrs	r3, r0
+    46ee:	26ff      	movs	r6, #255	; 0xff
+    46f0:	e7da      	b.n	46a8 <__aeabi_d2f+0x38>
+    46f2:	432b      	orrs	r3, r5
+    46f4:	d003      	beq.n	46fe <__aeabi_d2f+0x8e>
+    46f6:	2305      	movs	r3, #5
+    46f8:	08db      	lsrs	r3, r3, #3
+    46fa:	2cff      	cmp	r4, #255	; 0xff
+    46fc:	d003      	beq.n	4706 <__aeabi_d2f+0x96>
+    46fe:	025b      	lsls	r3, r3, #9
+    4700:	0a5b      	lsrs	r3, r3, #9
+    4702:	b2e4      	uxtb	r4, r4
+    4704:	e7e4      	b.n	46d0 <__aeabi_d2f+0x60>
+    4706:	2b00      	cmp	r3, #0
+    4708:	d032      	beq.n	4770 <__aeabi_d2f+0x100>
+    470a:	2080      	movs	r0, #128	; 0x80
+    470c:	03c0      	lsls	r0, r0, #15
+    470e:	4303      	orrs	r3, r0
+    4710:	025b      	lsls	r3, r3, #9
+    4712:	0a5b      	lsrs	r3, r3, #9
+    4714:	e7dc      	b.n	46d0 <__aeabi_d2f+0x60>
+    4716:	0032      	movs	r2, r6
+    4718:	3217      	adds	r2, #23
+    471a:	db14      	blt.n	4746 <__aeabi_d2f+0xd6>
+    471c:	2280      	movs	r2, #128	; 0x80
+    471e:	271e      	movs	r7, #30
+    4720:	0412      	lsls	r2, r2, #16
+    4722:	4313      	orrs	r3, r2
+    4724:	1bbf      	subs	r7, r7, r6
+    4726:	2f1f      	cmp	r7, #31
+    4728:	dc0f      	bgt.n	474a <__aeabi_d2f+0xda>
+    472a:	4a14      	ldr	r2, [pc, #80]	; (477c <__aeabi_d2f+0x10c>)
+    472c:	4694      	mov	ip, r2
+    472e:	4464      	add	r4, ip
+    4730:	002a      	movs	r2, r5
+    4732:	40a5      	lsls	r5, r4
+    4734:	002e      	movs	r6, r5
+    4736:	40a3      	lsls	r3, r4
+    4738:	1e75      	subs	r5, r6, #1
+    473a:	41ae      	sbcs	r6, r5
+    473c:	40fa      	lsrs	r2, r7
+    473e:	4333      	orrs	r3, r6
+    4740:	4313      	orrs	r3, r2
+    4742:	2600      	movs	r6, #0
+    4744:	e7b0      	b.n	46a8 <__aeabi_d2f+0x38>
+    4746:	2400      	movs	r4, #0
+    4748:	e7d5      	b.n	46f6 <__aeabi_d2f+0x86>
+    474a:	2202      	movs	r2, #2
+    474c:	4252      	negs	r2, r2
+    474e:	1b96      	subs	r6, r2, r6
+    4750:	001a      	movs	r2, r3
+    4752:	40f2      	lsrs	r2, r6
+    4754:	2f20      	cmp	r7, #32
+    4756:	d009      	beq.n	476c <__aeabi_d2f+0xfc>
+    4758:	4809      	ldr	r0, [pc, #36]	; (4780 <__aeabi_d2f+0x110>)
+    475a:	4684      	mov	ip, r0
+    475c:	4464      	add	r4, ip
+    475e:	40a3      	lsls	r3, r4
+    4760:	432b      	orrs	r3, r5
+    4762:	1e5d      	subs	r5, r3, #1
+    4764:	41ab      	sbcs	r3, r5
+    4766:	2600      	movs	r6, #0
+    4768:	4313      	orrs	r3, r2
+    476a:	e79d      	b.n	46a8 <__aeabi_d2f+0x38>
+    476c:	2300      	movs	r3, #0
+    476e:	e7f7      	b.n	4760 <__aeabi_d2f+0xf0>
+    4770:	2300      	movs	r3, #0
+    4772:	e7ad      	b.n	46d0 <__aeabi_d2f+0x60>
+    4774:	0034      	movs	r4, r6
+    4776:	e7bf      	b.n	46f8 <__aeabi_d2f+0x88>
+    4778:	fffffc80 	.word	0xfffffc80
+    477c:	fffffc82 	.word	0xfffffc82
+    4780:	fffffca2 	.word	0xfffffca2
+
+00004784 <__clzsi2>:
+    4784:	211c      	movs	r1, #28
+    4786:	2301      	movs	r3, #1
+    4788:	041b      	lsls	r3, r3, #16
+    478a:	4298      	cmp	r0, r3
+    478c:	d301      	bcc.n	4792 <__clzsi2+0xe>
+    478e:	0c00      	lsrs	r0, r0, #16
+    4790:	3910      	subs	r1, #16
+    4792:	0a1b      	lsrs	r3, r3, #8
+    4794:	4298      	cmp	r0, r3
+    4796:	d301      	bcc.n	479c <__clzsi2+0x18>
+    4798:	0a00      	lsrs	r0, r0, #8
+    479a:	3908      	subs	r1, #8
+    479c:	091b      	lsrs	r3, r3, #4
+    479e:	4298      	cmp	r0, r3
+    47a0:	d301      	bcc.n	47a6 <__clzsi2+0x22>
+    47a2:	0900      	lsrs	r0, r0, #4
+    47a4:	3904      	subs	r1, #4
+    47a6:	a202      	add	r2, pc, #8	; (adr r2, 47b0 <__clzsi2+0x2c>)
+    47a8:	5c10      	ldrb	r0, [r2, r0]
+    47aa:	1840      	adds	r0, r0, r1
+    47ac:	4770      	bx	lr
+    47ae:	46c0      	nop			; (mov r8, r8)
+    47b0:	02020304 	.word	0x02020304
+    47b4:	01010101 	.word	0x01010101
+	...
+
+000047c0 <__errno>:
+    47c0:	4b01      	ldr	r3, [pc, #4]	; (47c8 <__errno+0x8>)
+    47c2:	6818      	ldr	r0, [r3, #0]
+    47c4:	4770      	bx	lr
+    47c6:	46c0      	nop			; (mov r8, r8)
+    47c8:	20000018 	.word	0x20000018
+
+000047cc <__libc_init_array>:
+    47cc:	b570      	push	{r4, r5, r6, lr}
+    47ce:	2600      	movs	r6, #0
+    47d0:	4d0c      	ldr	r5, [pc, #48]	; (4804 <__libc_init_array+0x38>)
+    47d2:	4c0d      	ldr	r4, [pc, #52]	; (4808 <__libc_init_array+0x3c>)
+    47d4:	1b64      	subs	r4, r4, r5
+    47d6:	10a4      	asrs	r4, r4, #2
+    47d8:	42a6      	cmp	r6, r4
+    47da:	d109      	bne.n	47f0 <__libc_init_array+0x24>
+    47dc:	2600      	movs	r6, #0
+    47de:	f001 f9a9 	bl	5b34 <_init>
+    47e2:	4d0a      	ldr	r5, [pc, #40]	; (480c <__libc_init_array+0x40>)
+    47e4:	4c0a      	ldr	r4, [pc, #40]	; (4810 <__libc_init_array+0x44>)
+    47e6:	1b64      	subs	r4, r4, r5
+    47e8:	10a4      	asrs	r4, r4, #2
+    47ea:	42a6      	cmp	r6, r4
+    47ec:	d105      	bne.n	47fa <__libc_init_array+0x2e>
+    47ee:	bd70      	pop	{r4, r5, r6, pc}
+    47f0:	00b3      	lsls	r3, r6, #2
+    47f2:	58eb      	ldr	r3, [r5, r3]
+    47f4:	4798      	blx	r3
+    47f6:	3601      	adds	r6, #1
+    47f8:	e7ee      	b.n	47d8 <__libc_init_array+0xc>
+    47fa:	00b3      	lsls	r3, r6, #2
+    47fc:	58eb      	ldr	r3, [r5, r3]
+    47fe:	4798      	blx	r3
+    4800:	3601      	adds	r6, #1
+    4802:	e7f2      	b.n	47ea <__libc_init_array+0x1e>
+    4804:	00005b40 	.word	0x00005b40
+    4808:	00005b40 	.word	0x00005b40
+    480c:	00005b40 	.word	0x00005b40
+    4810:	00005b44 	.word	0x00005b44
+
+00004814 <memcpy>:
+    4814:	2300      	movs	r3, #0
+    4816:	b510      	push	{r4, lr}
+    4818:	429a      	cmp	r2, r3
+    481a:	d100      	bne.n	481e <memcpy+0xa>
+    481c:	bd10      	pop	{r4, pc}
+    481e:	5ccc      	ldrb	r4, [r1, r3]
+    4820:	54c4      	strb	r4, [r0, r3]
+    4822:	3301      	adds	r3, #1
+    4824:	e7f8      	b.n	4818 <memcpy+0x4>
+
+00004826 <memset>:
+    4826:	0003      	movs	r3, r0
+    4828:	1882      	adds	r2, r0, r2
+    482a:	4293      	cmp	r3, r2
+    482c:	d100      	bne.n	4830 <memset+0xa>
+    482e:	4770      	bx	lr
+    4830:	7019      	strb	r1, [r3, #0]
+    4832:	3301      	adds	r3, #1
+    4834:	e7f9      	b.n	482a <memset+0x4>
+	...
+
+00004838 <iprintf>:
+    4838:	b40f      	push	{r0, r1, r2, r3}
+    483a:	4b0b      	ldr	r3, [pc, #44]	; (4868 <iprintf+0x30>)
+    483c:	b513      	push	{r0, r1, r4, lr}
+    483e:	681c      	ldr	r4, [r3, #0]
+    4840:	2c00      	cmp	r4, #0
+    4842:	d005      	beq.n	4850 <iprintf+0x18>
+    4844:	69a3      	ldr	r3, [r4, #24]
+    4846:	2b00      	cmp	r3, #0
+    4848:	d102      	bne.n	4850 <iprintf+0x18>
+    484a:	0020      	movs	r0, r4
+    484c:	f000 faf2 	bl	4e34 <__sinit>
+    4850:	ab05      	add	r3, sp, #20
+    4852:	9a04      	ldr	r2, [sp, #16]
+    4854:	68a1      	ldr	r1, [r4, #8]
+    4856:	0020      	movs	r0, r4
+    4858:	9301      	str	r3, [sp, #4]
+    485a:	f000 fcc7 	bl	51ec <_vfiprintf_r>
+    485e:	bc16      	pop	{r1, r2, r4}
+    4860:	bc08      	pop	{r3}
+    4862:	b004      	add	sp, #16
+    4864:	4718      	bx	r3
+    4866:	46c0      	nop			; (mov r8, r8)
+    4868:	20000018 	.word	0x20000018
+
+0000486c <_puts_r>:
+    486c:	b570      	push	{r4, r5, r6, lr}
+    486e:	0005      	movs	r5, r0
+    4870:	000e      	movs	r6, r1
+    4872:	2800      	cmp	r0, #0
+    4874:	d004      	beq.n	4880 <_puts_r+0x14>
+    4876:	6983      	ldr	r3, [r0, #24]
+    4878:	2b00      	cmp	r3, #0
+    487a:	d101      	bne.n	4880 <_puts_r+0x14>
+    487c:	f000 fada 	bl	4e34 <__sinit>
+    4880:	69ab      	ldr	r3, [r5, #24]
+    4882:	68ac      	ldr	r4, [r5, #8]
+    4884:	2b00      	cmp	r3, #0
+    4886:	d102      	bne.n	488e <_puts_r+0x22>
+    4888:	0028      	movs	r0, r5
+    488a:	f000 fad3 	bl	4e34 <__sinit>
+    488e:	4b24      	ldr	r3, [pc, #144]	; (4920 <_puts_r+0xb4>)
+    4890:	429c      	cmp	r4, r3
+    4892:	d10f      	bne.n	48b4 <_puts_r+0x48>
+    4894:	686c      	ldr	r4, [r5, #4]
+    4896:	89a3      	ldrh	r3, [r4, #12]
+    4898:	071b      	lsls	r3, r3, #28
+    489a:	d502      	bpl.n	48a2 <_puts_r+0x36>
+    489c:	6923      	ldr	r3, [r4, #16]
+    489e:	2b00      	cmp	r3, #0
+    48a0:	d120      	bne.n	48e4 <_puts_r+0x78>
+    48a2:	0021      	movs	r1, r4
+    48a4:	0028      	movs	r0, r5
+    48a6:	f000 f957 	bl	4b58 <__swsetup_r>
+    48aa:	2800      	cmp	r0, #0
+    48ac:	d01a      	beq.n	48e4 <_puts_r+0x78>
+    48ae:	2001      	movs	r0, #1
+    48b0:	4240      	negs	r0, r0
+    48b2:	bd70      	pop	{r4, r5, r6, pc}
+    48b4:	4b1b      	ldr	r3, [pc, #108]	; (4924 <_puts_r+0xb8>)
+    48b6:	429c      	cmp	r4, r3
+    48b8:	d101      	bne.n	48be <_puts_r+0x52>
+    48ba:	68ac      	ldr	r4, [r5, #8]
+    48bc:	e7eb      	b.n	4896 <_puts_r+0x2a>
+    48be:	4b1a      	ldr	r3, [pc, #104]	; (4928 <_puts_r+0xbc>)
+    48c0:	429c      	cmp	r4, r3
+    48c2:	d1e8      	bne.n	4896 <_puts_r+0x2a>
+    48c4:	68ec      	ldr	r4, [r5, #12]
+    48c6:	e7e6      	b.n	4896 <_puts_r+0x2a>
+    48c8:	3b01      	subs	r3, #1
+    48ca:	3601      	adds	r6, #1
+    48cc:	60a3      	str	r3, [r4, #8]
+    48ce:	2b00      	cmp	r3, #0
+    48d0:	da04      	bge.n	48dc <_puts_r+0x70>
+    48d2:	69a2      	ldr	r2, [r4, #24]
+    48d4:	4293      	cmp	r3, r2
+    48d6:	db16      	blt.n	4906 <_puts_r+0x9a>
+    48d8:	290a      	cmp	r1, #10
+    48da:	d014      	beq.n	4906 <_puts_r+0x9a>
+    48dc:	6823      	ldr	r3, [r4, #0]
+    48de:	1c5a      	adds	r2, r3, #1
+    48e0:	6022      	str	r2, [r4, #0]
+    48e2:	7019      	strb	r1, [r3, #0]
+    48e4:	7831      	ldrb	r1, [r6, #0]
+    48e6:	68a3      	ldr	r3, [r4, #8]
+    48e8:	2900      	cmp	r1, #0
+    48ea:	d1ed      	bne.n	48c8 <_puts_r+0x5c>
+    48ec:	3b01      	subs	r3, #1
+    48ee:	60a3      	str	r3, [r4, #8]
+    48f0:	2b00      	cmp	r3, #0
+    48f2:	da0f      	bge.n	4914 <_puts_r+0xa8>
+    48f4:	0022      	movs	r2, r4
+    48f6:	310a      	adds	r1, #10
+    48f8:	0028      	movs	r0, r5
+    48fa:	f000 f8d7 	bl	4aac <__swbuf_r>
+    48fe:	1c43      	adds	r3, r0, #1
+    4900:	d0d5      	beq.n	48ae <_puts_r+0x42>
+    4902:	200a      	movs	r0, #10
+    4904:	e7d5      	b.n	48b2 <_puts_r+0x46>
+    4906:	0022      	movs	r2, r4
+    4908:	0028      	movs	r0, r5
+    490a:	f000 f8cf 	bl	4aac <__swbuf_r>
+    490e:	1c43      	adds	r3, r0, #1
+    4910:	d1e8      	bne.n	48e4 <_puts_r+0x78>
+    4912:	e7cc      	b.n	48ae <_puts_r+0x42>
+    4914:	200a      	movs	r0, #10
+    4916:	6823      	ldr	r3, [r4, #0]
+    4918:	1c5a      	adds	r2, r3, #1
+    491a:	6022      	str	r2, [r4, #0]
+    491c:	7018      	strb	r0, [r3, #0]
+    491e:	e7c8      	b.n	48b2 <_puts_r+0x46>
+    4920:	00005ac0 	.word	0x00005ac0
+    4924:	00005ae0 	.word	0x00005ae0
+    4928:	00005aa0 	.word	0x00005aa0
+
+0000492c <puts>:
+    492c:	b510      	push	{r4, lr}
+    492e:	4b03      	ldr	r3, [pc, #12]	; (493c <puts+0x10>)
+    4930:	0001      	movs	r1, r0
+    4932:	6818      	ldr	r0, [r3, #0]
+    4934:	f7ff ff9a 	bl	486c <_puts_r>
+    4938:	bd10      	pop	{r4, pc}
+    493a:	46c0      	nop			; (mov r8, r8)
+    493c:	20000018 	.word	0x20000018
+
+00004940 <setbuf>:
+    4940:	424a      	negs	r2, r1
+    4942:	414a      	adcs	r2, r1
+    4944:	2380      	movs	r3, #128	; 0x80
+    4946:	b510      	push	{r4, lr}
+    4948:	0052      	lsls	r2, r2, #1
+    494a:	00db      	lsls	r3, r3, #3
+    494c:	f000 f802 	bl	4954 <setvbuf>
+    4950:	bd10      	pop	{r4, pc}
+	...
+
+00004954 <setvbuf>:
+    4954:	b5f0      	push	{r4, r5, r6, r7, lr}
+    4956:	001d      	movs	r5, r3
+    4958:	4b4f      	ldr	r3, [pc, #316]	; (4a98 <setvbuf+0x144>)
+    495a:	b085      	sub	sp, #20
+    495c:	681e      	ldr	r6, [r3, #0]
+    495e:	0004      	movs	r4, r0
+    4960:	000f      	movs	r7, r1
+    4962:	9200      	str	r2, [sp, #0]
+    4964:	2e00      	cmp	r6, #0
+    4966:	d005      	beq.n	4974 <setvbuf+0x20>
+    4968:	69b3      	ldr	r3, [r6, #24]
+    496a:	2b00      	cmp	r3, #0
+    496c:	d102      	bne.n	4974 <setvbuf+0x20>
+    496e:	0030      	movs	r0, r6
+    4970:	f000 fa60 	bl	4e34 <__sinit>
+    4974:	4b49      	ldr	r3, [pc, #292]	; (4a9c <setvbuf+0x148>)
+    4976:	429c      	cmp	r4, r3
+    4978:	d150      	bne.n	4a1c <setvbuf+0xc8>
+    497a:	6874      	ldr	r4, [r6, #4]
+    497c:	9b00      	ldr	r3, [sp, #0]
+    497e:	2b02      	cmp	r3, #2
+    4980:	d005      	beq.n	498e <setvbuf+0x3a>
+    4982:	2b01      	cmp	r3, #1
+    4984:	d900      	bls.n	4988 <setvbuf+0x34>
+    4986:	e084      	b.n	4a92 <setvbuf+0x13e>
+    4988:	2d00      	cmp	r5, #0
+    498a:	da00      	bge.n	498e <setvbuf+0x3a>
+    498c:	e081      	b.n	4a92 <setvbuf+0x13e>
+    498e:	0021      	movs	r1, r4
+    4990:	0030      	movs	r0, r6
+    4992:	f000 f9e1 	bl	4d58 <_fflush_r>
+    4996:	6b61      	ldr	r1, [r4, #52]	; 0x34
+    4998:	2900      	cmp	r1, #0
+    499a:	d008      	beq.n	49ae <setvbuf+0x5a>
+    499c:	0023      	movs	r3, r4
+    499e:	3344      	adds	r3, #68	; 0x44
+    49a0:	4299      	cmp	r1, r3
+    49a2:	d002      	beq.n	49aa <setvbuf+0x56>
+    49a4:	0030      	movs	r0, r6
+    49a6:	f000 fb51 	bl	504c <_free_r>
+    49aa:	2300      	movs	r3, #0
+    49ac:	6363      	str	r3, [r4, #52]	; 0x34
+    49ae:	2300      	movs	r3, #0
+    49b0:	61a3      	str	r3, [r4, #24]
+    49b2:	6063      	str	r3, [r4, #4]
+    49b4:	89a3      	ldrh	r3, [r4, #12]
+    49b6:	061b      	lsls	r3, r3, #24
+    49b8:	d503      	bpl.n	49c2 <setvbuf+0x6e>
+    49ba:	6921      	ldr	r1, [r4, #16]
+    49bc:	0030      	movs	r0, r6
+    49be:	f000 fb45 	bl	504c <_free_r>
+    49c2:	89a3      	ldrh	r3, [r4, #12]
+    49c4:	4a36      	ldr	r2, [pc, #216]	; (4aa0 <setvbuf+0x14c>)
+    49c6:	4013      	ands	r3, r2
+    49c8:	81a3      	strh	r3, [r4, #12]
+    49ca:	9b00      	ldr	r3, [sp, #0]
+    49cc:	2b02      	cmp	r3, #2
+    49ce:	d05a      	beq.n	4a86 <setvbuf+0x132>
+    49d0:	ab03      	add	r3, sp, #12
+    49d2:	aa02      	add	r2, sp, #8
+    49d4:	0021      	movs	r1, r4
+    49d6:	0030      	movs	r0, r6
+    49d8:	f000 fac2 	bl	4f60 <__swhatbuf_r>
+    49dc:	89a3      	ldrh	r3, [r4, #12]
+    49de:	4318      	orrs	r0, r3
+    49e0:	81a0      	strh	r0, [r4, #12]
+    49e2:	2d00      	cmp	r5, #0
+    49e4:	d124      	bne.n	4a30 <setvbuf+0xdc>
+    49e6:	9d02      	ldr	r5, [sp, #8]
+    49e8:	0028      	movs	r0, r5
+    49ea:	f000 fb25 	bl	5038 <malloc>
+    49ee:	9501      	str	r5, [sp, #4]
+    49f0:	1e07      	subs	r7, r0, #0
+    49f2:	d142      	bne.n	4a7a <setvbuf+0x126>
+    49f4:	9b02      	ldr	r3, [sp, #8]
+    49f6:	9301      	str	r3, [sp, #4]
+    49f8:	42ab      	cmp	r3, r5
+    49fa:	d139      	bne.n	4a70 <setvbuf+0x11c>
+    49fc:	2001      	movs	r0, #1
+    49fe:	4240      	negs	r0, r0
+    4a00:	2302      	movs	r3, #2
+    4a02:	89a2      	ldrh	r2, [r4, #12]
+    4a04:	4313      	orrs	r3, r2
+    4a06:	81a3      	strh	r3, [r4, #12]
+    4a08:	2300      	movs	r3, #0
+    4a0a:	60a3      	str	r3, [r4, #8]
+    4a0c:	0023      	movs	r3, r4
+    4a0e:	3347      	adds	r3, #71	; 0x47
+    4a10:	6023      	str	r3, [r4, #0]
+    4a12:	6123      	str	r3, [r4, #16]
+    4a14:	2301      	movs	r3, #1
+    4a16:	6163      	str	r3, [r4, #20]
+    4a18:	b005      	add	sp, #20
+    4a1a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    4a1c:	4b21      	ldr	r3, [pc, #132]	; (4aa4 <setvbuf+0x150>)
+    4a1e:	429c      	cmp	r4, r3
+    4a20:	d101      	bne.n	4a26 <setvbuf+0xd2>
+    4a22:	68b4      	ldr	r4, [r6, #8]
+    4a24:	e7aa      	b.n	497c <setvbuf+0x28>
+    4a26:	4b20      	ldr	r3, [pc, #128]	; (4aa8 <setvbuf+0x154>)
+    4a28:	429c      	cmp	r4, r3
+    4a2a:	d1a7      	bne.n	497c <setvbuf+0x28>
+    4a2c:	68f4      	ldr	r4, [r6, #12]
+    4a2e:	e7a5      	b.n	497c <setvbuf+0x28>
+    4a30:	2f00      	cmp	r7, #0
+    4a32:	d0d9      	beq.n	49e8 <setvbuf+0x94>
+    4a34:	69b3      	ldr	r3, [r6, #24]
+    4a36:	2b00      	cmp	r3, #0
+    4a38:	d102      	bne.n	4a40 <setvbuf+0xec>
+    4a3a:	0030      	movs	r0, r6
+    4a3c:	f000 f9fa 	bl	4e34 <__sinit>
+    4a40:	9b00      	ldr	r3, [sp, #0]
+    4a42:	2b01      	cmp	r3, #1
+    4a44:	d103      	bne.n	4a4e <setvbuf+0xfa>
+    4a46:	89a3      	ldrh	r3, [r4, #12]
+    4a48:	9a00      	ldr	r2, [sp, #0]
+    4a4a:	431a      	orrs	r2, r3
+    4a4c:	81a2      	strh	r2, [r4, #12]
+    4a4e:	2008      	movs	r0, #8
+    4a50:	89a3      	ldrh	r3, [r4, #12]
+    4a52:	6027      	str	r7, [r4, #0]
+    4a54:	6127      	str	r7, [r4, #16]
+    4a56:	6165      	str	r5, [r4, #20]
+    4a58:	4018      	ands	r0, r3
+    4a5a:	d018      	beq.n	4a8e <setvbuf+0x13a>
+    4a5c:	2001      	movs	r0, #1
+    4a5e:	4018      	ands	r0, r3
+    4a60:	2300      	movs	r3, #0
+    4a62:	4298      	cmp	r0, r3
+    4a64:	d011      	beq.n	4a8a <setvbuf+0x136>
+    4a66:	426d      	negs	r5, r5
+    4a68:	60a3      	str	r3, [r4, #8]
+    4a6a:	61a5      	str	r5, [r4, #24]
+    4a6c:	0018      	movs	r0, r3
+    4a6e:	e7d3      	b.n	4a18 <setvbuf+0xc4>
+    4a70:	9801      	ldr	r0, [sp, #4]
+    4a72:	f000 fae1 	bl	5038 <malloc>
+    4a76:	1e07      	subs	r7, r0, #0
+    4a78:	d0c0      	beq.n	49fc <setvbuf+0xa8>
+    4a7a:	2380      	movs	r3, #128	; 0x80
+    4a7c:	89a2      	ldrh	r2, [r4, #12]
+    4a7e:	9d01      	ldr	r5, [sp, #4]
+    4a80:	4313      	orrs	r3, r2
+    4a82:	81a3      	strh	r3, [r4, #12]
+    4a84:	e7d6      	b.n	4a34 <setvbuf+0xe0>
+    4a86:	2000      	movs	r0, #0
+    4a88:	e7ba      	b.n	4a00 <setvbuf+0xac>
+    4a8a:	60a5      	str	r5, [r4, #8]
+    4a8c:	e7c4      	b.n	4a18 <setvbuf+0xc4>
+    4a8e:	60a0      	str	r0, [r4, #8]
+    4a90:	e7c2      	b.n	4a18 <setvbuf+0xc4>
+    4a92:	2001      	movs	r0, #1
+    4a94:	4240      	negs	r0, r0
+    4a96:	e7bf      	b.n	4a18 <setvbuf+0xc4>
+    4a98:	20000018 	.word	0x20000018
+    4a9c:	00005ac0 	.word	0x00005ac0
+    4aa0:	fffff35c 	.word	0xfffff35c
+    4aa4:	00005ae0 	.word	0x00005ae0
+    4aa8:	00005aa0 	.word	0x00005aa0
+
+00004aac <__swbuf_r>:
+    4aac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    4aae:	0005      	movs	r5, r0
+    4ab0:	000e      	movs	r6, r1
+    4ab2:	0014      	movs	r4, r2
+    4ab4:	2800      	cmp	r0, #0
+    4ab6:	d004      	beq.n	4ac2 <__swbuf_r+0x16>
+    4ab8:	6983      	ldr	r3, [r0, #24]
+    4aba:	2b00      	cmp	r3, #0
+    4abc:	d101      	bne.n	4ac2 <__swbuf_r+0x16>
+    4abe:	f000 f9b9 	bl	4e34 <__sinit>
+    4ac2:	4b22      	ldr	r3, [pc, #136]	; (4b4c <__swbuf_r+0xa0>)
+    4ac4:	429c      	cmp	r4, r3
+    4ac6:	d12d      	bne.n	4b24 <__swbuf_r+0x78>
+    4ac8:	686c      	ldr	r4, [r5, #4]
+    4aca:	69a3      	ldr	r3, [r4, #24]
+    4acc:	60a3      	str	r3, [r4, #8]
+    4ace:	89a3      	ldrh	r3, [r4, #12]
+    4ad0:	071b      	lsls	r3, r3, #28
+    4ad2:	d531      	bpl.n	4b38 <__swbuf_r+0x8c>
+    4ad4:	6923      	ldr	r3, [r4, #16]
+    4ad6:	2b00      	cmp	r3, #0
+    4ad8:	d02e      	beq.n	4b38 <__swbuf_r+0x8c>
+    4ada:	6823      	ldr	r3, [r4, #0]
+    4adc:	6922      	ldr	r2, [r4, #16]
+    4ade:	b2f7      	uxtb	r7, r6
+    4ae0:	1a98      	subs	r0, r3, r2
+    4ae2:	6963      	ldr	r3, [r4, #20]
+    4ae4:	b2f6      	uxtb	r6, r6
+    4ae6:	4298      	cmp	r0, r3
+    4ae8:	db05      	blt.n	4af6 <__swbuf_r+0x4a>
+    4aea:	0021      	movs	r1, r4
+    4aec:	0028      	movs	r0, r5
+    4aee:	f000 f933 	bl	4d58 <_fflush_r>
+    4af2:	2800      	cmp	r0, #0
+    4af4:	d126      	bne.n	4b44 <__swbuf_r+0x98>
+    4af6:	68a3      	ldr	r3, [r4, #8]
+    4af8:	3001      	adds	r0, #1
+    4afa:	3b01      	subs	r3, #1
+    4afc:	60a3      	str	r3, [r4, #8]
+    4afe:	6823      	ldr	r3, [r4, #0]
+    4b00:	1c5a      	adds	r2, r3, #1
+    4b02:	6022      	str	r2, [r4, #0]
+    4b04:	701f      	strb	r7, [r3, #0]
+    4b06:	6963      	ldr	r3, [r4, #20]
+    4b08:	4298      	cmp	r0, r3
+    4b0a:	d004      	beq.n	4b16 <__swbuf_r+0x6a>
+    4b0c:	89a3      	ldrh	r3, [r4, #12]
+    4b0e:	07db      	lsls	r3, r3, #31
+    4b10:	d51a      	bpl.n	4b48 <__swbuf_r+0x9c>
+    4b12:	2e0a      	cmp	r6, #10
+    4b14:	d118      	bne.n	4b48 <__swbuf_r+0x9c>
+    4b16:	0021      	movs	r1, r4
+    4b18:	0028      	movs	r0, r5
+    4b1a:	f000 f91d 	bl	4d58 <_fflush_r>
+    4b1e:	2800      	cmp	r0, #0
+    4b20:	d012      	beq.n	4b48 <__swbuf_r+0x9c>
+    4b22:	e00f      	b.n	4b44 <__swbuf_r+0x98>
+    4b24:	4b0a      	ldr	r3, [pc, #40]	; (4b50 <__swbuf_r+0xa4>)
+    4b26:	429c      	cmp	r4, r3
+    4b28:	d101      	bne.n	4b2e <__swbuf_r+0x82>
+    4b2a:	68ac      	ldr	r4, [r5, #8]
+    4b2c:	e7cd      	b.n	4aca <__swbuf_r+0x1e>
+    4b2e:	4b09      	ldr	r3, [pc, #36]	; (4b54 <__swbuf_r+0xa8>)
+    4b30:	429c      	cmp	r4, r3
+    4b32:	d1ca      	bne.n	4aca <__swbuf_r+0x1e>
+    4b34:	68ec      	ldr	r4, [r5, #12]
+    4b36:	e7c8      	b.n	4aca <__swbuf_r+0x1e>
+    4b38:	0021      	movs	r1, r4
+    4b3a:	0028      	movs	r0, r5
+    4b3c:	f000 f80c 	bl	4b58 <__swsetup_r>
+    4b40:	2800      	cmp	r0, #0
+    4b42:	d0ca      	beq.n	4ada <__swbuf_r+0x2e>
+    4b44:	2601      	movs	r6, #1
+    4b46:	4276      	negs	r6, r6
+    4b48:	0030      	movs	r0, r6
+    4b4a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    4b4c:	00005ac0 	.word	0x00005ac0
+    4b50:	00005ae0 	.word	0x00005ae0
+    4b54:	00005aa0 	.word	0x00005aa0
+
+00004b58 <__swsetup_r>:
+    4b58:	4b36      	ldr	r3, [pc, #216]	; (4c34 <__swsetup_r+0xdc>)
+    4b5a:	b570      	push	{r4, r5, r6, lr}
+    4b5c:	681d      	ldr	r5, [r3, #0]
+    4b5e:	0006      	movs	r6, r0
+    4b60:	000c      	movs	r4, r1
+    4b62:	2d00      	cmp	r5, #0
+    4b64:	d005      	beq.n	4b72 <__swsetup_r+0x1a>
+    4b66:	69ab      	ldr	r3, [r5, #24]
+    4b68:	2b00      	cmp	r3, #0
+    4b6a:	d102      	bne.n	4b72 <__swsetup_r+0x1a>
+    4b6c:	0028      	movs	r0, r5
+    4b6e:	f000 f961 	bl	4e34 <__sinit>
+    4b72:	4b31      	ldr	r3, [pc, #196]	; (4c38 <__swsetup_r+0xe0>)
+    4b74:	429c      	cmp	r4, r3
+    4b76:	d10f      	bne.n	4b98 <__swsetup_r+0x40>
+    4b78:	686c      	ldr	r4, [r5, #4]
+    4b7a:	230c      	movs	r3, #12
+    4b7c:	5ee2      	ldrsh	r2, [r4, r3]
+    4b7e:	b293      	uxth	r3, r2
+    4b80:	0719      	lsls	r1, r3, #28
+    4b82:	d42d      	bmi.n	4be0 <__swsetup_r+0x88>
+    4b84:	06d9      	lsls	r1, r3, #27
+    4b86:	d411      	bmi.n	4bac <__swsetup_r+0x54>
+    4b88:	2309      	movs	r3, #9
+    4b8a:	2001      	movs	r0, #1
+    4b8c:	6033      	str	r3, [r6, #0]
+    4b8e:	3337      	adds	r3, #55	; 0x37
+    4b90:	4313      	orrs	r3, r2
+    4b92:	81a3      	strh	r3, [r4, #12]
+    4b94:	4240      	negs	r0, r0
+    4b96:	bd70      	pop	{r4, r5, r6, pc}
+    4b98:	4b28      	ldr	r3, [pc, #160]	; (4c3c <__swsetup_r+0xe4>)
+    4b9a:	429c      	cmp	r4, r3
+    4b9c:	d101      	bne.n	4ba2 <__swsetup_r+0x4a>
+    4b9e:	68ac      	ldr	r4, [r5, #8]
+    4ba0:	e7eb      	b.n	4b7a <__swsetup_r+0x22>
+    4ba2:	4b27      	ldr	r3, [pc, #156]	; (4c40 <__swsetup_r+0xe8>)
+    4ba4:	429c      	cmp	r4, r3
+    4ba6:	d1e8      	bne.n	4b7a <__swsetup_r+0x22>
+    4ba8:	68ec      	ldr	r4, [r5, #12]
+    4baa:	e7e6      	b.n	4b7a <__swsetup_r+0x22>
+    4bac:	075b      	lsls	r3, r3, #29
+    4bae:	d513      	bpl.n	4bd8 <__swsetup_r+0x80>
+    4bb0:	6b61      	ldr	r1, [r4, #52]	; 0x34
+    4bb2:	2900      	cmp	r1, #0
+    4bb4:	d008      	beq.n	4bc8 <__swsetup_r+0x70>
+    4bb6:	0023      	movs	r3, r4
+    4bb8:	3344      	adds	r3, #68	; 0x44
+    4bba:	4299      	cmp	r1, r3
+    4bbc:	d002      	beq.n	4bc4 <__swsetup_r+0x6c>
+    4bbe:	0030      	movs	r0, r6
+    4bc0:	f000 fa44 	bl	504c <_free_r>
+    4bc4:	2300      	movs	r3, #0
+    4bc6:	6363      	str	r3, [r4, #52]	; 0x34
+    4bc8:	2224      	movs	r2, #36	; 0x24
+    4bca:	89a3      	ldrh	r3, [r4, #12]
+    4bcc:	4393      	bics	r3, r2
+    4bce:	81a3      	strh	r3, [r4, #12]
+    4bd0:	2300      	movs	r3, #0
+    4bd2:	6063      	str	r3, [r4, #4]
+    4bd4:	6923      	ldr	r3, [r4, #16]
+    4bd6:	6023      	str	r3, [r4, #0]
+    4bd8:	2308      	movs	r3, #8
+    4bda:	89a2      	ldrh	r2, [r4, #12]
+    4bdc:	4313      	orrs	r3, r2
+    4bde:	81a3      	strh	r3, [r4, #12]
+    4be0:	6923      	ldr	r3, [r4, #16]
+    4be2:	2b00      	cmp	r3, #0
+    4be4:	d10b      	bne.n	4bfe <__swsetup_r+0xa6>
+    4be6:	21a0      	movs	r1, #160	; 0xa0
+    4be8:	2280      	movs	r2, #128	; 0x80
+    4bea:	89a3      	ldrh	r3, [r4, #12]
+    4bec:	0089      	lsls	r1, r1, #2
+    4bee:	0092      	lsls	r2, r2, #2
+    4bf0:	400b      	ands	r3, r1
+    4bf2:	4293      	cmp	r3, r2
+    4bf4:	d003      	beq.n	4bfe <__swsetup_r+0xa6>
+    4bf6:	0021      	movs	r1, r4
+    4bf8:	0030      	movs	r0, r6
+    4bfa:	f000 f9d9 	bl	4fb0 <__smakebuf_r>
+    4bfe:	2301      	movs	r3, #1
+    4c00:	89a2      	ldrh	r2, [r4, #12]
+    4c02:	4013      	ands	r3, r2
+    4c04:	d011      	beq.n	4c2a <__swsetup_r+0xd2>
+    4c06:	2300      	movs	r3, #0
+    4c08:	60a3      	str	r3, [r4, #8]
+    4c0a:	6963      	ldr	r3, [r4, #20]
+    4c0c:	425b      	negs	r3, r3
+    4c0e:	61a3      	str	r3, [r4, #24]
+    4c10:	2000      	movs	r0, #0
+    4c12:	6923      	ldr	r3, [r4, #16]
+    4c14:	4283      	cmp	r3, r0
+    4c16:	d1be      	bne.n	4b96 <__swsetup_r+0x3e>
+    4c18:	230c      	movs	r3, #12
+    4c1a:	5ee2      	ldrsh	r2, [r4, r3]
+    4c1c:	0613      	lsls	r3, r2, #24
+    4c1e:	d5ba      	bpl.n	4b96 <__swsetup_r+0x3e>
+    4c20:	2340      	movs	r3, #64	; 0x40
+    4c22:	4313      	orrs	r3, r2
+    4c24:	81a3      	strh	r3, [r4, #12]
+    4c26:	3801      	subs	r0, #1
+    4c28:	e7b5      	b.n	4b96 <__swsetup_r+0x3e>
+    4c2a:	0792      	lsls	r2, r2, #30
+    4c2c:	d400      	bmi.n	4c30 <__swsetup_r+0xd8>
+    4c2e:	6963      	ldr	r3, [r4, #20]
+    4c30:	60a3      	str	r3, [r4, #8]
+    4c32:	e7ed      	b.n	4c10 <__swsetup_r+0xb8>
+    4c34:	20000018 	.word	0x20000018
+    4c38:	00005ac0 	.word	0x00005ac0
+    4c3c:	00005ae0 	.word	0x00005ae0
+    4c40:	00005aa0 	.word	0x00005aa0
+
+00004c44 <__sflush_r>:
+    4c44:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    4c46:	898a      	ldrh	r2, [r1, #12]
+    4c48:	0005      	movs	r5, r0
+    4c4a:	000c      	movs	r4, r1
+    4c4c:	0713      	lsls	r3, r2, #28
+    4c4e:	d460      	bmi.n	4d12 <__sflush_r+0xce>
+    4c50:	684b      	ldr	r3, [r1, #4]
+    4c52:	2b00      	cmp	r3, #0
+    4c54:	dc04      	bgt.n	4c60 <__sflush_r+0x1c>
+    4c56:	6c0b      	ldr	r3, [r1, #64]	; 0x40
+    4c58:	2b00      	cmp	r3, #0
+    4c5a:	dc01      	bgt.n	4c60 <__sflush_r+0x1c>
+    4c5c:	2000      	movs	r0, #0
+    4c5e:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    4c60:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
+    4c62:	2f00      	cmp	r7, #0
+    4c64:	d0fa      	beq.n	4c5c <__sflush_r+0x18>
+    4c66:	2300      	movs	r3, #0
+    4c68:	682e      	ldr	r6, [r5, #0]
+    4c6a:	602b      	str	r3, [r5, #0]
+    4c6c:	2380      	movs	r3, #128	; 0x80
+    4c6e:	015b      	lsls	r3, r3, #5
+    4c70:	401a      	ands	r2, r3
+    4c72:	d034      	beq.n	4cde <__sflush_r+0x9a>
+    4c74:	6d60      	ldr	r0, [r4, #84]	; 0x54
+    4c76:	89a3      	ldrh	r3, [r4, #12]
+    4c78:	075b      	lsls	r3, r3, #29
+    4c7a:	d506      	bpl.n	4c8a <__sflush_r+0x46>
+    4c7c:	6863      	ldr	r3, [r4, #4]
+    4c7e:	1ac0      	subs	r0, r0, r3
+    4c80:	6b63      	ldr	r3, [r4, #52]	; 0x34
+    4c82:	2b00      	cmp	r3, #0
+    4c84:	d001      	beq.n	4c8a <__sflush_r+0x46>
+    4c86:	6c23      	ldr	r3, [r4, #64]	; 0x40
+    4c88:	1ac0      	subs	r0, r0, r3
+    4c8a:	0002      	movs	r2, r0
+    4c8c:	6a21      	ldr	r1, [r4, #32]
+    4c8e:	2300      	movs	r3, #0
+    4c90:	0028      	movs	r0, r5
+    4c92:	6ae7      	ldr	r7, [r4, #44]	; 0x2c
+    4c94:	47b8      	blx	r7
+    4c96:	89a1      	ldrh	r1, [r4, #12]
+    4c98:	1c43      	adds	r3, r0, #1
+    4c9a:	d106      	bne.n	4caa <__sflush_r+0x66>
+    4c9c:	682b      	ldr	r3, [r5, #0]
+    4c9e:	2b1d      	cmp	r3, #29
+    4ca0:	d831      	bhi.n	4d06 <__sflush_r+0xc2>
+    4ca2:	4a2c      	ldr	r2, [pc, #176]	; (4d54 <__sflush_r+0x110>)
+    4ca4:	40da      	lsrs	r2, r3
+    4ca6:	07d3      	lsls	r3, r2, #31
+    4ca8:	d52d      	bpl.n	4d06 <__sflush_r+0xc2>
+    4caa:	2300      	movs	r3, #0
+    4cac:	6063      	str	r3, [r4, #4]
+    4cae:	6923      	ldr	r3, [r4, #16]
+    4cb0:	6023      	str	r3, [r4, #0]
+    4cb2:	04cb      	lsls	r3, r1, #19
+    4cb4:	d505      	bpl.n	4cc2 <__sflush_r+0x7e>
+    4cb6:	1c43      	adds	r3, r0, #1
+    4cb8:	d102      	bne.n	4cc0 <__sflush_r+0x7c>
+    4cba:	682b      	ldr	r3, [r5, #0]
+    4cbc:	2b00      	cmp	r3, #0
+    4cbe:	d100      	bne.n	4cc2 <__sflush_r+0x7e>
+    4cc0:	6560      	str	r0, [r4, #84]	; 0x54
+    4cc2:	6b61      	ldr	r1, [r4, #52]	; 0x34
+    4cc4:	602e      	str	r6, [r5, #0]
+    4cc6:	2900      	cmp	r1, #0
+    4cc8:	d0c8      	beq.n	4c5c <__sflush_r+0x18>
+    4cca:	0023      	movs	r3, r4
+    4ccc:	3344      	adds	r3, #68	; 0x44
+    4cce:	4299      	cmp	r1, r3
+    4cd0:	d002      	beq.n	4cd8 <__sflush_r+0x94>
+    4cd2:	0028      	movs	r0, r5
+    4cd4:	f000 f9ba 	bl	504c <_free_r>
+    4cd8:	2000      	movs	r0, #0
+    4cda:	6360      	str	r0, [r4, #52]	; 0x34
+    4cdc:	e7bf      	b.n	4c5e <__sflush_r+0x1a>
+    4cde:	2301      	movs	r3, #1
+    4ce0:	6a21      	ldr	r1, [r4, #32]
+    4ce2:	0028      	movs	r0, r5
+    4ce4:	47b8      	blx	r7
+    4ce6:	1c43      	adds	r3, r0, #1
+    4ce8:	d1c5      	bne.n	4c76 <__sflush_r+0x32>
+    4cea:	682b      	ldr	r3, [r5, #0]
+    4cec:	2b00      	cmp	r3, #0
+    4cee:	d0c2      	beq.n	4c76 <__sflush_r+0x32>
+    4cf0:	2b1d      	cmp	r3, #29
+    4cf2:	d001      	beq.n	4cf8 <__sflush_r+0xb4>
+    4cf4:	2b16      	cmp	r3, #22
+    4cf6:	d101      	bne.n	4cfc <__sflush_r+0xb8>
+    4cf8:	602e      	str	r6, [r5, #0]
+    4cfa:	e7af      	b.n	4c5c <__sflush_r+0x18>
+    4cfc:	2340      	movs	r3, #64	; 0x40
+    4cfe:	89a2      	ldrh	r2, [r4, #12]
+    4d00:	4313      	orrs	r3, r2
+    4d02:	81a3      	strh	r3, [r4, #12]
+    4d04:	e7ab      	b.n	4c5e <__sflush_r+0x1a>
+    4d06:	2340      	movs	r3, #64	; 0x40
+    4d08:	430b      	orrs	r3, r1
+    4d0a:	2001      	movs	r0, #1
+    4d0c:	81a3      	strh	r3, [r4, #12]
+    4d0e:	4240      	negs	r0, r0
+    4d10:	e7a5      	b.n	4c5e <__sflush_r+0x1a>
+    4d12:	690f      	ldr	r7, [r1, #16]
+    4d14:	2f00      	cmp	r7, #0
+    4d16:	d0a1      	beq.n	4c5c <__sflush_r+0x18>
+    4d18:	680b      	ldr	r3, [r1, #0]
+    4d1a:	600f      	str	r7, [r1, #0]
+    4d1c:	1bdb      	subs	r3, r3, r7
+    4d1e:	9301      	str	r3, [sp, #4]
+    4d20:	2300      	movs	r3, #0
+    4d22:	0792      	lsls	r2, r2, #30
+    4d24:	d100      	bne.n	4d28 <__sflush_r+0xe4>
+    4d26:	694b      	ldr	r3, [r1, #20]
+    4d28:	60a3      	str	r3, [r4, #8]
+    4d2a:	9b01      	ldr	r3, [sp, #4]
+    4d2c:	2b00      	cmp	r3, #0
+    4d2e:	dc00      	bgt.n	4d32 <__sflush_r+0xee>
+    4d30:	e794      	b.n	4c5c <__sflush_r+0x18>
+    4d32:	9b01      	ldr	r3, [sp, #4]
+    4d34:	003a      	movs	r2, r7
+    4d36:	6a21      	ldr	r1, [r4, #32]
+    4d38:	0028      	movs	r0, r5
+    4d3a:	6aa6      	ldr	r6, [r4, #40]	; 0x28
+    4d3c:	47b0      	blx	r6
+    4d3e:	2800      	cmp	r0, #0
+    4d40:	dc03      	bgt.n	4d4a <__sflush_r+0x106>
+    4d42:	2340      	movs	r3, #64	; 0x40
+    4d44:	89a2      	ldrh	r2, [r4, #12]
+    4d46:	4313      	orrs	r3, r2
+    4d48:	e7df      	b.n	4d0a <__sflush_r+0xc6>
+    4d4a:	9b01      	ldr	r3, [sp, #4]
+    4d4c:	183f      	adds	r7, r7, r0
+    4d4e:	1a1b      	subs	r3, r3, r0
+    4d50:	9301      	str	r3, [sp, #4]
+    4d52:	e7ea      	b.n	4d2a <__sflush_r+0xe6>
+    4d54:	20400001 	.word	0x20400001
+
+00004d58 <_fflush_r>:
+    4d58:	690b      	ldr	r3, [r1, #16]
+    4d5a:	b570      	push	{r4, r5, r6, lr}
+    4d5c:	0005      	movs	r5, r0
+    4d5e:	000c      	movs	r4, r1
+    4d60:	2b00      	cmp	r3, #0
+    4d62:	d101      	bne.n	4d68 <_fflush_r+0x10>
+    4d64:	2000      	movs	r0, #0
+    4d66:	bd70      	pop	{r4, r5, r6, pc}
+    4d68:	2800      	cmp	r0, #0
+    4d6a:	d004      	beq.n	4d76 <_fflush_r+0x1e>
+    4d6c:	6983      	ldr	r3, [r0, #24]
+    4d6e:	2b00      	cmp	r3, #0
+    4d70:	d101      	bne.n	4d76 <_fflush_r+0x1e>
+    4d72:	f000 f85f 	bl	4e34 <__sinit>
+    4d76:	4b0b      	ldr	r3, [pc, #44]	; (4da4 <_fflush_r+0x4c>)
+    4d78:	429c      	cmp	r4, r3
+    4d7a:	d109      	bne.n	4d90 <_fflush_r+0x38>
+    4d7c:	686c      	ldr	r4, [r5, #4]
+    4d7e:	220c      	movs	r2, #12
+    4d80:	5ea3      	ldrsh	r3, [r4, r2]
+    4d82:	2b00      	cmp	r3, #0
+    4d84:	d0ee      	beq.n	4d64 <_fflush_r+0xc>
+    4d86:	0021      	movs	r1, r4
+    4d88:	0028      	movs	r0, r5
+    4d8a:	f7ff ff5b 	bl	4c44 <__sflush_r>
+    4d8e:	e7ea      	b.n	4d66 <_fflush_r+0xe>
+    4d90:	4b05      	ldr	r3, [pc, #20]	; (4da8 <_fflush_r+0x50>)
+    4d92:	429c      	cmp	r4, r3
+    4d94:	d101      	bne.n	4d9a <_fflush_r+0x42>
+    4d96:	68ac      	ldr	r4, [r5, #8]
+    4d98:	e7f1      	b.n	4d7e <_fflush_r+0x26>
+    4d9a:	4b04      	ldr	r3, [pc, #16]	; (4dac <_fflush_r+0x54>)
+    4d9c:	429c      	cmp	r4, r3
+    4d9e:	d1ee      	bne.n	4d7e <_fflush_r+0x26>
+    4da0:	68ec      	ldr	r4, [r5, #12]
+    4da2:	e7ec      	b.n	4d7e <_fflush_r+0x26>
+    4da4:	00005ac0 	.word	0x00005ac0
+    4da8:	00005ae0 	.word	0x00005ae0
+    4dac:	00005aa0 	.word	0x00005aa0
+
+00004db0 <_cleanup_r>:
+    4db0:	b510      	push	{r4, lr}
+    4db2:	4902      	ldr	r1, [pc, #8]	; (4dbc <_cleanup_r+0xc>)
+    4db4:	f000 f8b2 	bl	4f1c <_fwalk_reent>
+    4db8:	bd10      	pop	{r4, pc}
+    4dba:	46c0      	nop			; (mov r8, r8)
+    4dbc:	00004d59 	.word	0x00004d59
+
+00004dc0 <std.isra.0>:
+    4dc0:	2300      	movs	r3, #0
+    4dc2:	b510      	push	{r4, lr}
+    4dc4:	0004      	movs	r4, r0
+    4dc6:	6003      	str	r3, [r0, #0]
+    4dc8:	6043      	str	r3, [r0, #4]
+    4dca:	6083      	str	r3, [r0, #8]
+    4dcc:	8181      	strh	r1, [r0, #12]
+    4dce:	6643      	str	r3, [r0, #100]	; 0x64
+    4dd0:	81c2      	strh	r2, [r0, #14]
+    4dd2:	6103      	str	r3, [r0, #16]
+    4dd4:	6143      	str	r3, [r0, #20]
+    4dd6:	6183      	str	r3, [r0, #24]
+    4dd8:	0019      	movs	r1, r3
+    4dda:	2208      	movs	r2, #8
+    4ddc:	305c      	adds	r0, #92	; 0x5c
+    4dde:	f7ff fd22 	bl	4826 <memset>
+    4de2:	4b05      	ldr	r3, [pc, #20]	; (4df8 <std.isra.0+0x38>)
+    4de4:	6224      	str	r4, [r4, #32]
+    4de6:	6263      	str	r3, [r4, #36]	; 0x24
+    4de8:	4b04      	ldr	r3, [pc, #16]	; (4dfc <std.isra.0+0x3c>)
+    4dea:	62a3      	str	r3, [r4, #40]	; 0x28
+    4dec:	4b04      	ldr	r3, [pc, #16]	; (4e00 <std.isra.0+0x40>)
+    4dee:	62e3      	str	r3, [r4, #44]	; 0x2c
+    4df0:	4b04      	ldr	r3, [pc, #16]	; (4e04 <std.isra.0+0x44>)
+    4df2:	6323      	str	r3, [r4, #48]	; 0x30
+    4df4:	bd10      	pop	{r4, pc}
+    4df6:	46c0      	nop			; (mov r8, r8)
+    4df8:	00005759 	.word	0x00005759
+    4dfc:	00005781 	.word	0x00005781
+    4e00:	000057b9 	.word	0x000057b9
+    4e04:	000057e5 	.word	0x000057e5
+
+00004e08 <__sfmoreglue>:
+    4e08:	b570      	push	{r4, r5, r6, lr}
+    4e0a:	2568      	movs	r5, #104	; 0x68
+    4e0c:	1e4a      	subs	r2, r1, #1
+    4e0e:	4355      	muls	r5, r2
+    4e10:	000e      	movs	r6, r1
+    4e12:	0029      	movs	r1, r5
+    4e14:	3174      	adds	r1, #116	; 0x74
+    4e16:	f000 f963 	bl	50e0 <_malloc_r>
+    4e1a:	1e04      	subs	r4, r0, #0
+    4e1c:	d008      	beq.n	4e30 <__sfmoreglue+0x28>
+    4e1e:	2100      	movs	r1, #0
+    4e20:	002a      	movs	r2, r5
+    4e22:	6001      	str	r1, [r0, #0]
+    4e24:	6046      	str	r6, [r0, #4]
+    4e26:	300c      	adds	r0, #12
+    4e28:	60a0      	str	r0, [r4, #8]
+    4e2a:	3268      	adds	r2, #104	; 0x68
+    4e2c:	f7ff fcfb 	bl	4826 <memset>
+    4e30:	0020      	movs	r0, r4
+    4e32:	bd70      	pop	{r4, r5, r6, pc}
+
+00004e34 <__sinit>:
+    4e34:	6983      	ldr	r3, [r0, #24]
+    4e36:	b513      	push	{r0, r1, r4, lr}
+    4e38:	0004      	movs	r4, r0
+    4e3a:	2b00      	cmp	r3, #0
+    4e3c:	d128      	bne.n	4e90 <__sinit+0x5c>
+    4e3e:	6483      	str	r3, [r0, #72]	; 0x48
+    4e40:	64c3      	str	r3, [r0, #76]	; 0x4c
+    4e42:	6503      	str	r3, [r0, #80]	; 0x50
+    4e44:	4b13      	ldr	r3, [pc, #76]	; (4e94 <__sinit+0x60>)
+    4e46:	4a14      	ldr	r2, [pc, #80]	; (4e98 <__sinit+0x64>)
+    4e48:	681b      	ldr	r3, [r3, #0]
+    4e4a:	6282      	str	r2, [r0, #40]	; 0x28
+    4e4c:	9301      	str	r3, [sp, #4]
+    4e4e:	4298      	cmp	r0, r3
+    4e50:	d101      	bne.n	4e56 <__sinit+0x22>
+    4e52:	2301      	movs	r3, #1
+    4e54:	6183      	str	r3, [r0, #24]
+    4e56:	0020      	movs	r0, r4
+    4e58:	f000 f820 	bl	4e9c <__sfp>
+    4e5c:	6060      	str	r0, [r4, #4]
+    4e5e:	0020      	movs	r0, r4
+    4e60:	f000 f81c 	bl	4e9c <__sfp>
+    4e64:	60a0      	str	r0, [r4, #8]
+    4e66:	0020      	movs	r0, r4
+    4e68:	f000 f818 	bl	4e9c <__sfp>
+    4e6c:	2200      	movs	r2, #0
+    4e6e:	60e0      	str	r0, [r4, #12]
+    4e70:	2104      	movs	r1, #4
+    4e72:	6860      	ldr	r0, [r4, #4]
+    4e74:	f7ff ffa4 	bl	4dc0 <std.isra.0>
+    4e78:	2201      	movs	r2, #1
+    4e7a:	2109      	movs	r1, #9
+    4e7c:	68a0      	ldr	r0, [r4, #8]
+    4e7e:	f7ff ff9f 	bl	4dc0 <std.isra.0>
+    4e82:	2202      	movs	r2, #2
+    4e84:	2112      	movs	r1, #18
+    4e86:	68e0      	ldr	r0, [r4, #12]
+    4e88:	f7ff ff9a 	bl	4dc0 <std.isra.0>
+    4e8c:	2301      	movs	r3, #1
+    4e8e:	61a3      	str	r3, [r4, #24]
+    4e90:	bd13      	pop	{r0, r1, r4, pc}
+    4e92:	46c0      	nop			; (mov r8, r8)
+    4e94:	00005a9c 	.word	0x00005a9c
+    4e98:	00004db1 	.word	0x00004db1
+
+00004e9c <__sfp>:
+    4e9c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    4e9e:	4b1e      	ldr	r3, [pc, #120]	; (4f18 <__sfp+0x7c>)
+    4ea0:	0007      	movs	r7, r0
+    4ea2:	681e      	ldr	r6, [r3, #0]
+    4ea4:	69b3      	ldr	r3, [r6, #24]
+    4ea6:	2b00      	cmp	r3, #0
+    4ea8:	d102      	bne.n	4eb0 <__sfp+0x14>
+    4eaa:	0030      	movs	r0, r6
+    4eac:	f7ff ffc2 	bl	4e34 <__sinit>
+    4eb0:	3648      	adds	r6, #72	; 0x48
+    4eb2:	68b4      	ldr	r4, [r6, #8]
+    4eb4:	6873      	ldr	r3, [r6, #4]
+    4eb6:	3b01      	subs	r3, #1
+    4eb8:	d504      	bpl.n	4ec4 <__sfp+0x28>
+    4eba:	6833      	ldr	r3, [r6, #0]
+    4ebc:	2b00      	cmp	r3, #0
+    4ebe:	d007      	beq.n	4ed0 <__sfp+0x34>
+    4ec0:	6836      	ldr	r6, [r6, #0]
+    4ec2:	e7f6      	b.n	4eb2 <__sfp+0x16>
+    4ec4:	220c      	movs	r2, #12
+    4ec6:	5ea5      	ldrsh	r5, [r4, r2]
+    4ec8:	2d00      	cmp	r5, #0
+    4eca:	d00d      	beq.n	4ee8 <__sfp+0x4c>
+    4ecc:	3468      	adds	r4, #104	; 0x68
+    4ece:	e7f2      	b.n	4eb6 <__sfp+0x1a>
+    4ed0:	2104      	movs	r1, #4
+    4ed2:	0038      	movs	r0, r7
+    4ed4:	f7ff ff98 	bl	4e08 <__sfmoreglue>
+    4ed8:	6030      	str	r0, [r6, #0]
+    4eda:	2800      	cmp	r0, #0
+    4edc:	d1f0      	bne.n	4ec0 <__sfp+0x24>
+    4ede:	230c      	movs	r3, #12
+    4ee0:	0004      	movs	r4, r0
+    4ee2:	603b      	str	r3, [r7, #0]
+    4ee4:	0020      	movs	r0, r4
+    4ee6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    4ee8:	2301      	movs	r3, #1
+    4eea:	0020      	movs	r0, r4
+    4eec:	425b      	negs	r3, r3
+    4eee:	81e3      	strh	r3, [r4, #14]
+    4ef0:	3302      	adds	r3, #2
+    4ef2:	81a3      	strh	r3, [r4, #12]
+    4ef4:	6665      	str	r5, [r4, #100]	; 0x64
+    4ef6:	6025      	str	r5, [r4, #0]
+    4ef8:	60a5      	str	r5, [r4, #8]
+    4efa:	6065      	str	r5, [r4, #4]
+    4efc:	6125      	str	r5, [r4, #16]
+    4efe:	6165      	str	r5, [r4, #20]
+    4f00:	61a5      	str	r5, [r4, #24]
+    4f02:	2208      	movs	r2, #8
+    4f04:	0029      	movs	r1, r5
+    4f06:	305c      	adds	r0, #92	; 0x5c
+    4f08:	f7ff fc8d 	bl	4826 <memset>
+    4f0c:	6365      	str	r5, [r4, #52]	; 0x34
+    4f0e:	63a5      	str	r5, [r4, #56]	; 0x38
+    4f10:	64a5      	str	r5, [r4, #72]	; 0x48
+    4f12:	64e5      	str	r5, [r4, #76]	; 0x4c
+    4f14:	e7e6      	b.n	4ee4 <__sfp+0x48>
+    4f16:	46c0      	nop			; (mov r8, r8)
+    4f18:	00005a9c 	.word	0x00005a9c
+
+00004f1c <_fwalk_reent>:
+    4f1c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    4f1e:	0004      	movs	r4, r0
+    4f20:	0007      	movs	r7, r0
+    4f22:	2600      	movs	r6, #0
+    4f24:	9101      	str	r1, [sp, #4]
+    4f26:	3448      	adds	r4, #72	; 0x48
+    4f28:	2c00      	cmp	r4, #0
+    4f2a:	d101      	bne.n	4f30 <_fwalk_reent+0x14>
+    4f2c:	0030      	movs	r0, r6
+    4f2e:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    4f30:	6863      	ldr	r3, [r4, #4]
+    4f32:	68a5      	ldr	r5, [r4, #8]
+    4f34:	9300      	str	r3, [sp, #0]
+    4f36:	9b00      	ldr	r3, [sp, #0]
+    4f38:	3b01      	subs	r3, #1
+    4f3a:	9300      	str	r3, [sp, #0]
+    4f3c:	d501      	bpl.n	4f42 <_fwalk_reent+0x26>
+    4f3e:	6824      	ldr	r4, [r4, #0]
+    4f40:	e7f2      	b.n	4f28 <_fwalk_reent+0xc>
+    4f42:	89ab      	ldrh	r3, [r5, #12]
+    4f44:	2b01      	cmp	r3, #1
+    4f46:	d908      	bls.n	4f5a <_fwalk_reent+0x3e>
+    4f48:	220e      	movs	r2, #14
+    4f4a:	5eab      	ldrsh	r3, [r5, r2]
+    4f4c:	3301      	adds	r3, #1
+    4f4e:	d004      	beq.n	4f5a <_fwalk_reent+0x3e>
+    4f50:	0029      	movs	r1, r5
+    4f52:	0038      	movs	r0, r7
+    4f54:	9b01      	ldr	r3, [sp, #4]
+    4f56:	4798      	blx	r3
+    4f58:	4306      	orrs	r6, r0
+    4f5a:	3568      	adds	r5, #104	; 0x68
+    4f5c:	e7eb      	b.n	4f36 <_fwalk_reent+0x1a>
+	...
+
+00004f60 <__swhatbuf_r>:
+    4f60:	b570      	push	{r4, r5, r6, lr}
+    4f62:	000e      	movs	r6, r1
+    4f64:	001d      	movs	r5, r3
+    4f66:	230e      	movs	r3, #14
+    4f68:	5ec9      	ldrsh	r1, [r1, r3]
+    4f6a:	b090      	sub	sp, #64	; 0x40
+    4f6c:	0014      	movs	r4, r2
+    4f6e:	2900      	cmp	r1, #0
+    4f70:	da07      	bge.n	4f82 <__swhatbuf_r+0x22>
+    4f72:	2300      	movs	r3, #0
+    4f74:	602b      	str	r3, [r5, #0]
+    4f76:	89b3      	ldrh	r3, [r6, #12]
+    4f78:	061b      	lsls	r3, r3, #24
+    4f7a:	d411      	bmi.n	4fa0 <__swhatbuf_r+0x40>
+    4f7c:	2380      	movs	r3, #128	; 0x80
+    4f7e:	00db      	lsls	r3, r3, #3
+    4f80:	e00f      	b.n	4fa2 <__swhatbuf_r+0x42>
+    4f82:	aa01      	add	r2, sp, #4
+    4f84:	f000 fc5a 	bl	583c <_fstat_r>
+    4f88:	2800      	cmp	r0, #0
+    4f8a:	dbf2      	blt.n	4f72 <__swhatbuf_r+0x12>
+    4f8c:	22f0      	movs	r2, #240	; 0xf0
+    4f8e:	9b02      	ldr	r3, [sp, #8]
+    4f90:	0212      	lsls	r2, r2, #8
+    4f92:	4013      	ands	r3, r2
+    4f94:	4a05      	ldr	r2, [pc, #20]	; (4fac <__swhatbuf_r+0x4c>)
+    4f96:	189b      	adds	r3, r3, r2
+    4f98:	425a      	negs	r2, r3
+    4f9a:	4153      	adcs	r3, r2
+    4f9c:	602b      	str	r3, [r5, #0]
+    4f9e:	e7ed      	b.n	4f7c <__swhatbuf_r+0x1c>
+    4fa0:	2340      	movs	r3, #64	; 0x40
+    4fa2:	2000      	movs	r0, #0
+    4fa4:	6023      	str	r3, [r4, #0]
+    4fa6:	b010      	add	sp, #64	; 0x40
+    4fa8:	bd70      	pop	{r4, r5, r6, pc}
+    4faa:	46c0      	nop			; (mov r8, r8)
+    4fac:	ffffe000 	.word	0xffffe000
+
+00004fb0 <__smakebuf_r>:
+    4fb0:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    4fb2:	2602      	movs	r6, #2
+    4fb4:	898b      	ldrh	r3, [r1, #12]
+    4fb6:	0005      	movs	r5, r0
+    4fb8:	000c      	movs	r4, r1
+    4fba:	4233      	tst	r3, r6
+    4fbc:	d006      	beq.n	4fcc <__smakebuf_r+0x1c>
+    4fbe:	0023      	movs	r3, r4
+    4fc0:	3347      	adds	r3, #71	; 0x47
+    4fc2:	6023      	str	r3, [r4, #0]
+    4fc4:	6123      	str	r3, [r4, #16]
+    4fc6:	2301      	movs	r3, #1
+    4fc8:	6163      	str	r3, [r4, #20]
+    4fca:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
+    4fcc:	ab01      	add	r3, sp, #4
+    4fce:	466a      	mov	r2, sp
+    4fd0:	f7ff ffc6 	bl	4f60 <__swhatbuf_r>
+    4fd4:	9900      	ldr	r1, [sp, #0]
+    4fd6:	0007      	movs	r7, r0
+    4fd8:	0028      	movs	r0, r5
+    4fda:	f000 f881 	bl	50e0 <_malloc_r>
+    4fde:	2800      	cmp	r0, #0
+    4fe0:	d108      	bne.n	4ff4 <__smakebuf_r+0x44>
+    4fe2:	220c      	movs	r2, #12
+    4fe4:	5ea3      	ldrsh	r3, [r4, r2]
+    4fe6:	059a      	lsls	r2, r3, #22
+    4fe8:	d4ef      	bmi.n	4fca <__smakebuf_r+0x1a>
+    4fea:	2203      	movs	r2, #3
+    4fec:	4393      	bics	r3, r2
+    4fee:	431e      	orrs	r6, r3
+    4ff0:	81a6      	strh	r6, [r4, #12]
+    4ff2:	e7e4      	b.n	4fbe <__smakebuf_r+0xe>
+    4ff4:	4b0f      	ldr	r3, [pc, #60]	; (5034 <__smakebuf_r+0x84>)
+    4ff6:	62ab      	str	r3, [r5, #40]	; 0x28
+    4ff8:	2380      	movs	r3, #128	; 0x80
+    4ffa:	89a2      	ldrh	r2, [r4, #12]
+    4ffc:	6020      	str	r0, [r4, #0]
+    4ffe:	4313      	orrs	r3, r2
+    5000:	81a3      	strh	r3, [r4, #12]
+    5002:	9b00      	ldr	r3, [sp, #0]
+    5004:	6120      	str	r0, [r4, #16]
+    5006:	6163      	str	r3, [r4, #20]
+    5008:	9b01      	ldr	r3, [sp, #4]
+    500a:	2b00      	cmp	r3, #0
+    500c:	d00d      	beq.n	502a <__smakebuf_r+0x7a>
+    500e:	230e      	movs	r3, #14
+    5010:	5ee1      	ldrsh	r1, [r4, r3]
+    5012:	0028      	movs	r0, r5
+    5014:	f000 fc24 	bl	5860 <_isatty_r>
+    5018:	2800      	cmp	r0, #0
+    501a:	d006      	beq.n	502a <__smakebuf_r+0x7a>
+    501c:	2203      	movs	r2, #3
+    501e:	89a3      	ldrh	r3, [r4, #12]
+    5020:	4393      	bics	r3, r2
+    5022:	001a      	movs	r2, r3
+    5024:	2301      	movs	r3, #1
+    5026:	4313      	orrs	r3, r2
+    5028:	81a3      	strh	r3, [r4, #12]
+    502a:	89a0      	ldrh	r0, [r4, #12]
+    502c:	4338      	orrs	r0, r7
+    502e:	81a0      	strh	r0, [r4, #12]
+    5030:	e7cb      	b.n	4fca <__smakebuf_r+0x1a>
+    5032:	46c0      	nop			; (mov r8, r8)
+    5034:	00004db1 	.word	0x00004db1
+
+00005038 <malloc>:
+    5038:	b510      	push	{r4, lr}
+    503a:	4b03      	ldr	r3, [pc, #12]	; (5048 <malloc+0x10>)
+    503c:	0001      	movs	r1, r0
+    503e:	6818      	ldr	r0, [r3, #0]
+    5040:	f000 f84e 	bl	50e0 <_malloc_r>
+    5044:	bd10      	pop	{r4, pc}
+    5046:	46c0      	nop			; (mov r8, r8)
+    5048:	20000018 	.word	0x20000018
+
+0000504c <_free_r>:
+    504c:	b570      	push	{r4, r5, r6, lr}
+    504e:	0005      	movs	r5, r0
+    5050:	2900      	cmp	r1, #0
+    5052:	d010      	beq.n	5076 <_free_r+0x2a>
+    5054:	1f0c      	subs	r4, r1, #4
+    5056:	6823      	ldr	r3, [r4, #0]
+    5058:	2b00      	cmp	r3, #0
+    505a:	da00      	bge.n	505e <_free_r+0x12>
+    505c:	18e4      	adds	r4, r4, r3
+    505e:	0028      	movs	r0, r5
+    5060:	f000 fc2f 	bl	58c2 <__malloc_lock>
+    5064:	4a1d      	ldr	r2, [pc, #116]	; (50dc <_free_r+0x90>)
+    5066:	6813      	ldr	r3, [r2, #0]
+    5068:	2b00      	cmp	r3, #0
+    506a:	d105      	bne.n	5078 <_free_r+0x2c>
+    506c:	6063      	str	r3, [r4, #4]
+    506e:	6014      	str	r4, [r2, #0]
+    5070:	0028      	movs	r0, r5
+    5072:	f000 fc27 	bl	58c4 <__malloc_unlock>
+    5076:	bd70      	pop	{r4, r5, r6, pc}
+    5078:	42a3      	cmp	r3, r4
+    507a:	d909      	bls.n	5090 <_free_r+0x44>
+    507c:	6821      	ldr	r1, [r4, #0]
+    507e:	1860      	adds	r0, r4, r1
+    5080:	4283      	cmp	r3, r0
+    5082:	d1f3      	bne.n	506c <_free_r+0x20>
+    5084:	6818      	ldr	r0, [r3, #0]
+    5086:	685b      	ldr	r3, [r3, #4]
+    5088:	1841      	adds	r1, r0, r1
+    508a:	6021      	str	r1, [r4, #0]
+    508c:	e7ee      	b.n	506c <_free_r+0x20>
+    508e:	0013      	movs	r3, r2
+    5090:	685a      	ldr	r2, [r3, #4]
+    5092:	2a00      	cmp	r2, #0
+    5094:	d001      	beq.n	509a <_free_r+0x4e>
+    5096:	42a2      	cmp	r2, r4
+    5098:	d9f9      	bls.n	508e <_free_r+0x42>
+    509a:	6819      	ldr	r1, [r3, #0]
+    509c:	1858      	adds	r0, r3, r1
+    509e:	42a0      	cmp	r0, r4
+    50a0:	d10b      	bne.n	50ba <_free_r+0x6e>
+    50a2:	6820      	ldr	r0, [r4, #0]
+    50a4:	1809      	adds	r1, r1, r0
+    50a6:	1858      	adds	r0, r3, r1
+    50a8:	6019      	str	r1, [r3, #0]
+    50aa:	4282      	cmp	r2, r0
+    50ac:	d1e0      	bne.n	5070 <_free_r+0x24>
+    50ae:	6810      	ldr	r0, [r2, #0]
+    50b0:	6852      	ldr	r2, [r2, #4]
+    50b2:	1841      	adds	r1, r0, r1
+    50b4:	6019      	str	r1, [r3, #0]
+    50b6:	605a      	str	r2, [r3, #4]
+    50b8:	e7da      	b.n	5070 <_free_r+0x24>
+    50ba:	42a0      	cmp	r0, r4
+    50bc:	d902      	bls.n	50c4 <_free_r+0x78>
+    50be:	230c      	movs	r3, #12
+    50c0:	602b      	str	r3, [r5, #0]
+    50c2:	e7d5      	b.n	5070 <_free_r+0x24>
+    50c4:	6821      	ldr	r1, [r4, #0]
+    50c6:	1860      	adds	r0, r4, r1
+    50c8:	4282      	cmp	r2, r0
+    50ca:	d103      	bne.n	50d4 <_free_r+0x88>
+    50cc:	6810      	ldr	r0, [r2, #0]
+    50ce:	6852      	ldr	r2, [r2, #4]
+    50d0:	1841      	adds	r1, r0, r1
+    50d2:	6021      	str	r1, [r4, #0]
+    50d4:	6062      	str	r2, [r4, #4]
+    50d6:	605c      	str	r4, [r3, #4]
+    50d8:	e7ca      	b.n	5070 <_free_r+0x24>
+    50da:	46c0      	nop			; (mov r8, r8)
+    50dc:	200001cc 	.word	0x200001cc
+
+000050e0 <_malloc_r>:
+    50e0:	2303      	movs	r3, #3
+    50e2:	b570      	push	{r4, r5, r6, lr}
+    50e4:	1ccd      	adds	r5, r1, #3
+    50e6:	439d      	bics	r5, r3
+    50e8:	3508      	adds	r5, #8
+    50ea:	0006      	movs	r6, r0
+    50ec:	2d0c      	cmp	r5, #12
+    50ee:	d21e      	bcs.n	512e <_malloc_r+0x4e>
+    50f0:	250c      	movs	r5, #12
+    50f2:	42a9      	cmp	r1, r5
+    50f4:	d81d      	bhi.n	5132 <_malloc_r+0x52>
+    50f6:	0030      	movs	r0, r6
+    50f8:	f000 fbe3 	bl	58c2 <__malloc_lock>
+    50fc:	4a25      	ldr	r2, [pc, #148]	; (5194 <_malloc_r+0xb4>)
+    50fe:	6814      	ldr	r4, [r2, #0]
+    5100:	0021      	movs	r1, r4
+    5102:	2900      	cmp	r1, #0
+    5104:	d119      	bne.n	513a <_malloc_r+0x5a>
+    5106:	4c24      	ldr	r4, [pc, #144]	; (5198 <_malloc_r+0xb8>)
+    5108:	6823      	ldr	r3, [r4, #0]
+    510a:	2b00      	cmp	r3, #0
+    510c:	d103      	bne.n	5116 <_malloc_r+0x36>
+    510e:	0030      	movs	r0, r6
+    5110:	f000 fb10 	bl	5734 <_sbrk_r>
+    5114:	6020      	str	r0, [r4, #0]
+    5116:	0029      	movs	r1, r5
+    5118:	0030      	movs	r0, r6
+    511a:	f000 fb0b 	bl	5734 <_sbrk_r>
+    511e:	1c43      	adds	r3, r0, #1
+    5120:	d12c      	bne.n	517c <_malloc_r+0x9c>
+    5122:	230c      	movs	r3, #12
+    5124:	0030      	movs	r0, r6
+    5126:	6033      	str	r3, [r6, #0]
+    5128:	f000 fbcc 	bl	58c4 <__malloc_unlock>
+    512c:	e003      	b.n	5136 <_malloc_r+0x56>
+    512e:	2d00      	cmp	r5, #0
+    5130:	dadf      	bge.n	50f2 <_malloc_r+0x12>
+    5132:	230c      	movs	r3, #12
+    5134:	6033      	str	r3, [r6, #0]
+    5136:	2000      	movs	r0, #0
+    5138:	bd70      	pop	{r4, r5, r6, pc}
+    513a:	680b      	ldr	r3, [r1, #0]
+    513c:	1b5b      	subs	r3, r3, r5
+    513e:	d41a      	bmi.n	5176 <_malloc_r+0x96>
+    5140:	2b0b      	cmp	r3, #11
+    5142:	d903      	bls.n	514c <_malloc_r+0x6c>
+    5144:	600b      	str	r3, [r1, #0]
+    5146:	18cc      	adds	r4, r1, r3
+    5148:	6025      	str	r5, [r4, #0]
+    514a:	e003      	b.n	5154 <_malloc_r+0x74>
+    514c:	428c      	cmp	r4, r1
+    514e:	d10e      	bne.n	516e <_malloc_r+0x8e>
+    5150:	6863      	ldr	r3, [r4, #4]
+    5152:	6013      	str	r3, [r2, #0]
+    5154:	0030      	movs	r0, r6
+    5156:	f000 fbb5 	bl	58c4 <__malloc_unlock>
+    515a:	0020      	movs	r0, r4
+    515c:	2207      	movs	r2, #7
+    515e:	300b      	adds	r0, #11
+    5160:	1d23      	adds	r3, r4, #4
+    5162:	4390      	bics	r0, r2
+    5164:	1ac3      	subs	r3, r0, r3
+    5166:	d0e7      	beq.n	5138 <_malloc_r+0x58>
+    5168:	425a      	negs	r2, r3
+    516a:	50e2      	str	r2, [r4, r3]
+    516c:	e7e4      	b.n	5138 <_malloc_r+0x58>
+    516e:	684b      	ldr	r3, [r1, #4]
+    5170:	6063      	str	r3, [r4, #4]
+    5172:	000c      	movs	r4, r1
+    5174:	e7ee      	b.n	5154 <_malloc_r+0x74>
+    5176:	000c      	movs	r4, r1
+    5178:	6849      	ldr	r1, [r1, #4]
+    517a:	e7c2      	b.n	5102 <_malloc_r+0x22>
+    517c:	2303      	movs	r3, #3
+    517e:	1cc4      	adds	r4, r0, #3
+    5180:	439c      	bics	r4, r3
+    5182:	42a0      	cmp	r0, r4
+    5184:	d0e0      	beq.n	5148 <_malloc_r+0x68>
+    5186:	1a21      	subs	r1, r4, r0
+    5188:	0030      	movs	r0, r6
+    518a:	f000 fad3 	bl	5734 <_sbrk_r>
+    518e:	1c43      	adds	r3, r0, #1
+    5190:	d1da      	bne.n	5148 <_malloc_r+0x68>
+    5192:	e7c6      	b.n	5122 <_malloc_r+0x42>
+    5194:	200001cc 	.word	0x200001cc
+    5198:	200001d0 	.word	0x200001d0
+
+0000519c <__sfputc_r>:
+    519c:	6893      	ldr	r3, [r2, #8]
+    519e:	b510      	push	{r4, lr}
+    51a0:	3b01      	subs	r3, #1
+    51a2:	6093      	str	r3, [r2, #8]
+    51a4:	2b00      	cmp	r3, #0
+    51a6:	da05      	bge.n	51b4 <__sfputc_r+0x18>
+    51a8:	6994      	ldr	r4, [r2, #24]
+    51aa:	42a3      	cmp	r3, r4
+    51ac:	db08      	blt.n	51c0 <__sfputc_r+0x24>
+    51ae:	b2cb      	uxtb	r3, r1
+    51b0:	2b0a      	cmp	r3, #10
+    51b2:	d005      	beq.n	51c0 <__sfputc_r+0x24>
+    51b4:	6813      	ldr	r3, [r2, #0]
+    51b6:	1c58      	adds	r0, r3, #1
+    51b8:	6010      	str	r0, [r2, #0]
+    51ba:	7019      	strb	r1, [r3, #0]
+    51bc:	b2c8      	uxtb	r0, r1
+    51be:	bd10      	pop	{r4, pc}
+    51c0:	f7ff fc74 	bl	4aac <__swbuf_r>
+    51c4:	e7fb      	b.n	51be <__sfputc_r+0x22>
+
+000051c6 <__sfputs_r>:
+    51c6:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    51c8:	0006      	movs	r6, r0
+    51ca:	000f      	movs	r7, r1
+    51cc:	0014      	movs	r4, r2
+    51ce:	18d5      	adds	r5, r2, r3
+    51d0:	42ac      	cmp	r4, r5
+    51d2:	d101      	bne.n	51d8 <__sfputs_r+0x12>
+    51d4:	2000      	movs	r0, #0
+    51d6:	e007      	b.n	51e8 <__sfputs_r+0x22>
+    51d8:	7821      	ldrb	r1, [r4, #0]
+    51da:	003a      	movs	r2, r7
+    51dc:	0030      	movs	r0, r6
+    51de:	f7ff ffdd 	bl	519c <__sfputc_r>
+    51e2:	3401      	adds	r4, #1
+    51e4:	1c43      	adds	r3, r0, #1
+    51e6:	d1f3      	bne.n	51d0 <__sfputs_r+0xa>
+    51e8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+	...
+
+000051ec <_vfiprintf_r>:
+    51ec:	b5f0      	push	{r4, r5, r6, r7, lr}
+    51ee:	b09f      	sub	sp, #124	; 0x7c
+    51f0:	0006      	movs	r6, r0
+    51f2:	000f      	movs	r7, r1
+    51f4:	0014      	movs	r4, r2
+    51f6:	9305      	str	r3, [sp, #20]
+    51f8:	2800      	cmp	r0, #0
+    51fa:	d004      	beq.n	5206 <_vfiprintf_r+0x1a>
+    51fc:	6983      	ldr	r3, [r0, #24]
+    51fe:	2b00      	cmp	r3, #0
+    5200:	d101      	bne.n	5206 <_vfiprintf_r+0x1a>
+    5202:	f7ff fe17 	bl	4e34 <__sinit>
+    5206:	4b7f      	ldr	r3, [pc, #508]	; (5404 <_vfiprintf_r+0x218>)
+    5208:	429f      	cmp	r7, r3
+    520a:	d15c      	bne.n	52c6 <_vfiprintf_r+0xda>
+    520c:	6877      	ldr	r7, [r6, #4]
+    520e:	89bb      	ldrh	r3, [r7, #12]
+    5210:	071b      	lsls	r3, r3, #28
+    5212:	d562      	bpl.n	52da <_vfiprintf_r+0xee>
+    5214:	693b      	ldr	r3, [r7, #16]
+    5216:	2b00      	cmp	r3, #0
+    5218:	d05f      	beq.n	52da <_vfiprintf_r+0xee>
+    521a:	2300      	movs	r3, #0
+    521c:	ad06      	add	r5, sp, #24
+    521e:	616b      	str	r3, [r5, #20]
+    5220:	3320      	adds	r3, #32
+    5222:	766b      	strb	r3, [r5, #25]
+    5224:	3310      	adds	r3, #16
+    5226:	76ab      	strb	r3, [r5, #26]
+    5228:	9402      	str	r4, [sp, #8]
+    522a:	9c02      	ldr	r4, [sp, #8]
+    522c:	7823      	ldrb	r3, [r4, #0]
+    522e:	2b00      	cmp	r3, #0
+    5230:	d15d      	bne.n	52ee <_vfiprintf_r+0x102>
+    5232:	9b02      	ldr	r3, [sp, #8]
+    5234:	1ae3      	subs	r3, r4, r3
+    5236:	9304      	str	r3, [sp, #16]
+    5238:	d00d      	beq.n	5256 <_vfiprintf_r+0x6a>
+    523a:	9b04      	ldr	r3, [sp, #16]
+    523c:	9a02      	ldr	r2, [sp, #8]
+    523e:	0039      	movs	r1, r7
+    5240:	0030      	movs	r0, r6
+    5242:	f7ff ffc0 	bl	51c6 <__sfputs_r>
+    5246:	1c43      	adds	r3, r0, #1
+    5248:	d100      	bne.n	524c <_vfiprintf_r+0x60>
+    524a:	e0cc      	b.n	53e6 <_vfiprintf_r+0x1fa>
+    524c:	696a      	ldr	r2, [r5, #20]
+    524e:	9b04      	ldr	r3, [sp, #16]
+    5250:	4694      	mov	ip, r2
+    5252:	4463      	add	r3, ip
+    5254:	616b      	str	r3, [r5, #20]
+    5256:	7823      	ldrb	r3, [r4, #0]
+    5258:	2b00      	cmp	r3, #0
+    525a:	d100      	bne.n	525e <_vfiprintf_r+0x72>
+    525c:	e0c3      	b.n	53e6 <_vfiprintf_r+0x1fa>
+    525e:	2201      	movs	r2, #1
+    5260:	2300      	movs	r3, #0
+    5262:	4252      	negs	r2, r2
+    5264:	606a      	str	r2, [r5, #4]
+    5266:	a902      	add	r1, sp, #8
+    5268:	3254      	adds	r2, #84	; 0x54
+    526a:	1852      	adds	r2, r2, r1
+    526c:	3401      	adds	r4, #1
+    526e:	602b      	str	r3, [r5, #0]
+    5270:	60eb      	str	r3, [r5, #12]
+    5272:	60ab      	str	r3, [r5, #8]
+    5274:	7013      	strb	r3, [r2, #0]
+    5276:	65ab      	str	r3, [r5, #88]	; 0x58
+    5278:	7821      	ldrb	r1, [r4, #0]
+    527a:	2205      	movs	r2, #5
+    527c:	4862      	ldr	r0, [pc, #392]	; (5408 <_vfiprintf_r+0x21c>)
+    527e:	f000 fb15 	bl	58ac <memchr>
+    5282:	1c63      	adds	r3, r4, #1
+    5284:	469c      	mov	ip, r3
+    5286:	2800      	cmp	r0, #0
+    5288:	d135      	bne.n	52f6 <_vfiprintf_r+0x10a>
+    528a:	6829      	ldr	r1, [r5, #0]
+    528c:	06cb      	lsls	r3, r1, #27
+    528e:	d504      	bpl.n	529a <_vfiprintf_r+0xae>
+    5290:	2353      	movs	r3, #83	; 0x53
+    5292:	aa02      	add	r2, sp, #8
+    5294:	3020      	adds	r0, #32
+    5296:	189b      	adds	r3, r3, r2
+    5298:	7018      	strb	r0, [r3, #0]
+    529a:	070b      	lsls	r3, r1, #28
+    529c:	d504      	bpl.n	52a8 <_vfiprintf_r+0xbc>
+    529e:	2353      	movs	r3, #83	; 0x53
+    52a0:	202b      	movs	r0, #43	; 0x2b
+    52a2:	aa02      	add	r2, sp, #8
+    52a4:	189b      	adds	r3, r3, r2
+    52a6:	7018      	strb	r0, [r3, #0]
+    52a8:	7823      	ldrb	r3, [r4, #0]
+    52aa:	2b2a      	cmp	r3, #42	; 0x2a
+    52ac:	d02c      	beq.n	5308 <_vfiprintf_r+0x11c>
+    52ae:	2000      	movs	r0, #0
+    52b0:	210a      	movs	r1, #10
+    52b2:	9b09      	ldr	r3, [sp, #36]	; 0x24
+    52b4:	7822      	ldrb	r2, [r4, #0]
+    52b6:	3a30      	subs	r2, #48	; 0x30
+    52b8:	2a09      	cmp	r2, #9
+    52ba:	d800      	bhi.n	52be <_vfiprintf_r+0xd2>
+    52bc:	e06b      	b.n	5396 <_vfiprintf_r+0x1aa>
+    52be:	2800      	cmp	r0, #0
+    52c0:	d02a      	beq.n	5318 <_vfiprintf_r+0x12c>
+    52c2:	9309      	str	r3, [sp, #36]	; 0x24
+    52c4:	e028      	b.n	5318 <_vfiprintf_r+0x12c>
+    52c6:	4b51      	ldr	r3, [pc, #324]	; (540c <_vfiprintf_r+0x220>)
+    52c8:	429f      	cmp	r7, r3
+    52ca:	d101      	bne.n	52d0 <_vfiprintf_r+0xe4>
+    52cc:	68b7      	ldr	r7, [r6, #8]
+    52ce:	e79e      	b.n	520e <_vfiprintf_r+0x22>
+    52d0:	4b4f      	ldr	r3, [pc, #316]	; (5410 <_vfiprintf_r+0x224>)
+    52d2:	429f      	cmp	r7, r3
+    52d4:	d19b      	bne.n	520e <_vfiprintf_r+0x22>
+    52d6:	68f7      	ldr	r7, [r6, #12]
+    52d8:	e799      	b.n	520e <_vfiprintf_r+0x22>
+    52da:	0039      	movs	r1, r7
+    52dc:	0030      	movs	r0, r6
+    52de:	f7ff fc3b 	bl	4b58 <__swsetup_r>
+    52e2:	2800      	cmp	r0, #0
+    52e4:	d099      	beq.n	521a <_vfiprintf_r+0x2e>
+    52e6:	2001      	movs	r0, #1
+    52e8:	4240      	negs	r0, r0
+    52ea:	b01f      	add	sp, #124	; 0x7c
+    52ec:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    52ee:	2b25      	cmp	r3, #37	; 0x25
+    52f0:	d09f      	beq.n	5232 <_vfiprintf_r+0x46>
+    52f2:	3401      	adds	r4, #1
+    52f4:	e79a      	b.n	522c <_vfiprintf_r+0x40>
+    52f6:	4b44      	ldr	r3, [pc, #272]	; (5408 <_vfiprintf_r+0x21c>)
+    52f8:	6829      	ldr	r1, [r5, #0]
+    52fa:	1ac0      	subs	r0, r0, r3
+    52fc:	2301      	movs	r3, #1
+    52fe:	4083      	lsls	r3, r0
+    5300:	430b      	orrs	r3, r1
+    5302:	602b      	str	r3, [r5, #0]
+    5304:	4664      	mov	r4, ip
+    5306:	e7b7      	b.n	5278 <_vfiprintf_r+0x8c>
+    5308:	9b05      	ldr	r3, [sp, #20]
+    530a:	1d18      	adds	r0, r3, #4
+    530c:	681b      	ldr	r3, [r3, #0]
+    530e:	9005      	str	r0, [sp, #20]
+    5310:	2b00      	cmp	r3, #0
+    5312:	db3a      	blt.n	538a <_vfiprintf_r+0x19e>
+    5314:	9309      	str	r3, [sp, #36]	; 0x24
+    5316:	4664      	mov	r4, ip
+    5318:	7823      	ldrb	r3, [r4, #0]
+    531a:	2b2e      	cmp	r3, #46	; 0x2e
+    531c:	d10b      	bne.n	5336 <_vfiprintf_r+0x14a>
+    531e:	7863      	ldrb	r3, [r4, #1]
+    5320:	1c62      	adds	r2, r4, #1
+    5322:	2b2a      	cmp	r3, #42	; 0x2a
+    5324:	d13f      	bne.n	53a6 <_vfiprintf_r+0x1ba>
+    5326:	9b05      	ldr	r3, [sp, #20]
+    5328:	3402      	adds	r4, #2
+    532a:	1d1a      	adds	r2, r3, #4
+    532c:	681b      	ldr	r3, [r3, #0]
+    532e:	9205      	str	r2, [sp, #20]
+    5330:	2b00      	cmp	r3, #0
+    5332:	db35      	blt.n	53a0 <_vfiprintf_r+0x1b4>
+    5334:	9307      	str	r3, [sp, #28]
+    5336:	7821      	ldrb	r1, [r4, #0]
+    5338:	2203      	movs	r2, #3
+    533a:	4836      	ldr	r0, [pc, #216]	; (5414 <_vfiprintf_r+0x228>)
+    533c:	f000 fab6 	bl	58ac <memchr>
+    5340:	2800      	cmp	r0, #0
+    5342:	d007      	beq.n	5354 <_vfiprintf_r+0x168>
+    5344:	4b33      	ldr	r3, [pc, #204]	; (5414 <_vfiprintf_r+0x228>)
+    5346:	682a      	ldr	r2, [r5, #0]
+    5348:	1ac0      	subs	r0, r0, r3
+    534a:	2340      	movs	r3, #64	; 0x40
+    534c:	4083      	lsls	r3, r0
+    534e:	4313      	orrs	r3, r2
+    5350:	602b      	str	r3, [r5, #0]
+    5352:	3401      	adds	r4, #1
+    5354:	7821      	ldrb	r1, [r4, #0]
+    5356:	1c63      	adds	r3, r4, #1
+    5358:	2206      	movs	r2, #6
+    535a:	482f      	ldr	r0, [pc, #188]	; (5418 <_vfiprintf_r+0x22c>)
+    535c:	9302      	str	r3, [sp, #8]
+    535e:	7629      	strb	r1, [r5, #24]
+    5360:	f000 faa4 	bl	58ac <memchr>
+    5364:	2800      	cmp	r0, #0
+    5366:	d044      	beq.n	53f2 <_vfiprintf_r+0x206>
+    5368:	4b2c      	ldr	r3, [pc, #176]	; (541c <_vfiprintf_r+0x230>)
+    536a:	2b00      	cmp	r3, #0
+    536c:	d12f      	bne.n	53ce <_vfiprintf_r+0x1e2>
+    536e:	6829      	ldr	r1, [r5, #0]
+    5370:	9b05      	ldr	r3, [sp, #20]
+    5372:	2207      	movs	r2, #7
+    5374:	05c9      	lsls	r1, r1, #23
+    5376:	d528      	bpl.n	53ca <_vfiprintf_r+0x1de>
+    5378:	189b      	adds	r3, r3, r2
+    537a:	4393      	bics	r3, r2
+    537c:	3308      	adds	r3, #8
+    537e:	9305      	str	r3, [sp, #20]
+    5380:	696b      	ldr	r3, [r5, #20]
+    5382:	9a03      	ldr	r2, [sp, #12]
+    5384:	189b      	adds	r3, r3, r2
+    5386:	616b      	str	r3, [r5, #20]
+    5388:	e74f      	b.n	522a <_vfiprintf_r+0x3e>
+    538a:	425b      	negs	r3, r3
+    538c:	60eb      	str	r3, [r5, #12]
+    538e:	2302      	movs	r3, #2
+    5390:	430b      	orrs	r3, r1
+    5392:	602b      	str	r3, [r5, #0]
+    5394:	e7bf      	b.n	5316 <_vfiprintf_r+0x12a>
+    5396:	434b      	muls	r3, r1
+    5398:	3401      	adds	r4, #1
+    539a:	189b      	adds	r3, r3, r2
+    539c:	2001      	movs	r0, #1
+    539e:	e789      	b.n	52b4 <_vfiprintf_r+0xc8>
+    53a0:	2301      	movs	r3, #1
+    53a2:	425b      	negs	r3, r3
+    53a4:	e7c6      	b.n	5334 <_vfiprintf_r+0x148>
+    53a6:	2300      	movs	r3, #0
+    53a8:	0014      	movs	r4, r2
+    53aa:	200a      	movs	r0, #10
+    53ac:	001a      	movs	r2, r3
+    53ae:	606b      	str	r3, [r5, #4]
+    53b0:	7821      	ldrb	r1, [r4, #0]
+    53b2:	3930      	subs	r1, #48	; 0x30
+    53b4:	2909      	cmp	r1, #9
+    53b6:	d903      	bls.n	53c0 <_vfiprintf_r+0x1d4>
+    53b8:	2b00      	cmp	r3, #0
+    53ba:	d0bc      	beq.n	5336 <_vfiprintf_r+0x14a>
+    53bc:	9207      	str	r2, [sp, #28]
+    53be:	e7ba      	b.n	5336 <_vfiprintf_r+0x14a>
+    53c0:	4342      	muls	r2, r0
+    53c2:	3401      	adds	r4, #1
+    53c4:	1852      	adds	r2, r2, r1
+    53c6:	2301      	movs	r3, #1
+    53c8:	e7f2      	b.n	53b0 <_vfiprintf_r+0x1c4>
+    53ca:	3307      	adds	r3, #7
+    53cc:	e7d5      	b.n	537a <_vfiprintf_r+0x18e>
+    53ce:	ab05      	add	r3, sp, #20
+    53d0:	9300      	str	r3, [sp, #0]
+    53d2:	003a      	movs	r2, r7
+    53d4:	4b12      	ldr	r3, [pc, #72]	; (5420 <_vfiprintf_r+0x234>)
+    53d6:	0029      	movs	r1, r5
+    53d8:	0030      	movs	r0, r6
+    53da:	e000      	b.n	53de <_vfiprintf_r+0x1f2>
+    53dc:	bf00      	nop
+    53de:	9003      	str	r0, [sp, #12]
+    53e0:	9b03      	ldr	r3, [sp, #12]
+    53e2:	3301      	adds	r3, #1
+    53e4:	d1cc      	bne.n	5380 <_vfiprintf_r+0x194>
+    53e6:	89bb      	ldrh	r3, [r7, #12]
+    53e8:	065b      	lsls	r3, r3, #25
+    53ea:	d500      	bpl.n	53ee <_vfiprintf_r+0x202>
+    53ec:	e77b      	b.n	52e6 <_vfiprintf_r+0xfa>
+    53ee:	980b      	ldr	r0, [sp, #44]	; 0x2c
+    53f0:	e77b      	b.n	52ea <_vfiprintf_r+0xfe>
+    53f2:	ab05      	add	r3, sp, #20
+    53f4:	9300      	str	r3, [sp, #0]
+    53f6:	003a      	movs	r2, r7
+    53f8:	4b09      	ldr	r3, [pc, #36]	; (5420 <_vfiprintf_r+0x234>)
+    53fa:	0029      	movs	r1, r5
+    53fc:	0030      	movs	r0, r6
+    53fe:	f000 f87f 	bl	5500 <_printf_i>
+    5402:	e7ec      	b.n	53de <_vfiprintf_r+0x1f2>
+    5404:	00005ac0 	.word	0x00005ac0
+    5408:	00005b00 	.word	0x00005b00
+    540c:	00005ae0 	.word	0x00005ae0
+    5410:	00005aa0 	.word	0x00005aa0
+    5414:	00005b06 	.word	0x00005b06
+    5418:	00005b0a 	.word	0x00005b0a
+    541c:	00000000 	.word	0x00000000
+    5420:	000051c7 	.word	0x000051c7
+
+00005424 <_printf_common>:
+    5424:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+    5426:	0015      	movs	r5, r2
+    5428:	9301      	str	r3, [sp, #4]
+    542a:	688a      	ldr	r2, [r1, #8]
+    542c:	690b      	ldr	r3, [r1, #16]
+    542e:	9000      	str	r0, [sp, #0]
+    5430:	000c      	movs	r4, r1
+    5432:	4293      	cmp	r3, r2
+    5434:	da00      	bge.n	5438 <_printf_common+0x14>
+    5436:	0013      	movs	r3, r2
+    5438:	0022      	movs	r2, r4
+    543a:	602b      	str	r3, [r5, #0]
+    543c:	3243      	adds	r2, #67	; 0x43
+    543e:	7812      	ldrb	r2, [r2, #0]
+    5440:	2a00      	cmp	r2, #0
+    5442:	d001      	beq.n	5448 <_printf_common+0x24>
+    5444:	3301      	adds	r3, #1
+    5446:	602b      	str	r3, [r5, #0]
+    5448:	6823      	ldr	r3, [r4, #0]
+    544a:	069b      	lsls	r3, r3, #26
+    544c:	d502      	bpl.n	5454 <_printf_common+0x30>
+    544e:	682b      	ldr	r3, [r5, #0]
+    5450:	3302      	adds	r3, #2
+    5452:	602b      	str	r3, [r5, #0]
+    5454:	2706      	movs	r7, #6
+    5456:	6823      	ldr	r3, [r4, #0]
+    5458:	401f      	ands	r7, r3
+    545a:	d027      	beq.n	54ac <_printf_common+0x88>
+    545c:	0023      	movs	r3, r4
+    545e:	3343      	adds	r3, #67	; 0x43
+    5460:	781b      	ldrb	r3, [r3, #0]
+    5462:	1e5a      	subs	r2, r3, #1
+    5464:	4193      	sbcs	r3, r2
+    5466:	6822      	ldr	r2, [r4, #0]
+    5468:	0692      	lsls	r2, r2, #26
+    546a:	d430      	bmi.n	54ce <_printf_common+0xaa>
+    546c:	0022      	movs	r2, r4
+    546e:	9901      	ldr	r1, [sp, #4]
+    5470:	3243      	adds	r2, #67	; 0x43
+    5472:	9800      	ldr	r0, [sp, #0]
+    5474:	9e08      	ldr	r6, [sp, #32]
+    5476:	47b0      	blx	r6
+    5478:	1c43      	adds	r3, r0, #1
+    547a:	d025      	beq.n	54c8 <_printf_common+0xa4>
+    547c:	2306      	movs	r3, #6
+    547e:	6820      	ldr	r0, [r4, #0]
+    5480:	682a      	ldr	r2, [r5, #0]
+    5482:	68e1      	ldr	r1, [r4, #12]
+    5484:	4003      	ands	r3, r0
+    5486:	2500      	movs	r5, #0
+    5488:	2b04      	cmp	r3, #4
+    548a:	d103      	bne.n	5494 <_printf_common+0x70>
+    548c:	1a8d      	subs	r5, r1, r2
+    548e:	43eb      	mvns	r3, r5
+    5490:	17db      	asrs	r3, r3, #31
+    5492:	401d      	ands	r5, r3
+    5494:	68a3      	ldr	r3, [r4, #8]
+    5496:	6922      	ldr	r2, [r4, #16]
+    5498:	4293      	cmp	r3, r2
+    549a:	dd01      	ble.n	54a0 <_printf_common+0x7c>
+    549c:	1a9b      	subs	r3, r3, r2
+    549e:	18ed      	adds	r5, r5, r3
+    54a0:	2700      	movs	r7, #0
+    54a2:	42bd      	cmp	r5, r7
+    54a4:	d120      	bne.n	54e8 <_printf_common+0xc4>
+    54a6:	2000      	movs	r0, #0
+    54a8:	e010      	b.n	54cc <_printf_common+0xa8>
+    54aa:	3701      	adds	r7, #1
+    54ac:	68e3      	ldr	r3, [r4, #12]
+    54ae:	682a      	ldr	r2, [r5, #0]
+    54b0:	1a9b      	subs	r3, r3, r2
+    54b2:	429f      	cmp	r7, r3
+    54b4:	dad2      	bge.n	545c <_printf_common+0x38>
+    54b6:	0022      	movs	r2, r4
+    54b8:	2301      	movs	r3, #1
+    54ba:	3219      	adds	r2, #25
+    54bc:	9901      	ldr	r1, [sp, #4]
+    54be:	9800      	ldr	r0, [sp, #0]
+    54c0:	9e08      	ldr	r6, [sp, #32]
+    54c2:	47b0      	blx	r6
+    54c4:	1c43      	adds	r3, r0, #1
+    54c6:	d1f0      	bne.n	54aa <_printf_common+0x86>
+    54c8:	2001      	movs	r0, #1
+    54ca:	4240      	negs	r0, r0
+    54cc:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+    54ce:	2030      	movs	r0, #48	; 0x30
+    54d0:	18e1      	adds	r1, r4, r3
+    54d2:	3143      	adds	r1, #67	; 0x43
+    54d4:	7008      	strb	r0, [r1, #0]
+    54d6:	0021      	movs	r1, r4
+    54d8:	1c5a      	adds	r2, r3, #1
+    54da:	3145      	adds	r1, #69	; 0x45
+    54dc:	7809      	ldrb	r1, [r1, #0]
+    54de:	18a2      	adds	r2, r4, r2
+    54e0:	3243      	adds	r2, #67	; 0x43
+    54e2:	3302      	adds	r3, #2
+    54e4:	7011      	strb	r1, [r2, #0]
+    54e6:	e7c1      	b.n	546c <_printf_common+0x48>
+    54e8:	0022      	movs	r2, r4
+    54ea:	2301      	movs	r3, #1
+    54ec:	321a      	adds	r2, #26
+    54ee:	9901      	ldr	r1, [sp, #4]
+    54f0:	9800      	ldr	r0, [sp, #0]
+    54f2:	9e08      	ldr	r6, [sp, #32]
+    54f4:	47b0      	blx	r6
+    54f6:	1c43      	adds	r3, r0, #1
+    54f8:	d0e6      	beq.n	54c8 <_printf_common+0xa4>
+    54fa:	3701      	adds	r7, #1
+    54fc:	e7d1      	b.n	54a2 <_printf_common+0x7e>
+	...
+
+00005500 <_printf_i>:
+    5500:	b5f0      	push	{r4, r5, r6, r7, lr}
+    5502:	b08b      	sub	sp, #44	; 0x2c
+    5504:	9206      	str	r2, [sp, #24]
+    5506:	000a      	movs	r2, r1
+    5508:	3243      	adds	r2, #67	; 0x43
+    550a:	9307      	str	r3, [sp, #28]
+    550c:	9005      	str	r0, [sp, #20]
+    550e:	9204      	str	r2, [sp, #16]
+    5510:	7e0a      	ldrb	r2, [r1, #24]
+    5512:	000c      	movs	r4, r1
+    5514:	9b10      	ldr	r3, [sp, #64]	; 0x40
+    5516:	2a6e      	cmp	r2, #110	; 0x6e
+    5518:	d100      	bne.n	551c <_printf_i+0x1c>
+    551a:	e08f      	b.n	563c <_printf_i+0x13c>
+    551c:	d817      	bhi.n	554e <_printf_i+0x4e>
+    551e:	2a63      	cmp	r2, #99	; 0x63
+    5520:	d02c      	beq.n	557c <_printf_i+0x7c>
+    5522:	d808      	bhi.n	5536 <_printf_i+0x36>
+    5524:	2a00      	cmp	r2, #0
+    5526:	d100      	bne.n	552a <_printf_i+0x2a>
+    5528:	e099      	b.n	565e <_printf_i+0x15e>
+    552a:	2a58      	cmp	r2, #88	; 0x58
+    552c:	d054      	beq.n	55d8 <_printf_i+0xd8>
+    552e:	0026      	movs	r6, r4
+    5530:	3642      	adds	r6, #66	; 0x42
+    5532:	7032      	strb	r2, [r6, #0]
+    5534:	e029      	b.n	558a <_printf_i+0x8a>
+    5536:	2a64      	cmp	r2, #100	; 0x64
+    5538:	d001      	beq.n	553e <_printf_i+0x3e>
+    553a:	2a69      	cmp	r2, #105	; 0x69
+    553c:	d1f7      	bne.n	552e <_printf_i+0x2e>
+    553e:	6821      	ldr	r1, [r4, #0]
+    5540:	681a      	ldr	r2, [r3, #0]
+    5542:	0608      	lsls	r0, r1, #24
+    5544:	d523      	bpl.n	558e <_printf_i+0x8e>
+    5546:	1d11      	adds	r1, r2, #4
+    5548:	6019      	str	r1, [r3, #0]
+    554a:	6815      	ldr	r5, [r2, #0]
+    554c:	e025      	b.n	559a <_printf_i+0x9a>
+    554e:	2a73      	cmp	r2, #115	; 0x73
+    5550:	d100      	bne.n	5554 <_printf_i+0x54>
+    5552:	e088      	b.n	5666 <_printf_i+0x166>
+    5554:	d808      	bhi.n	5568 <_printf_i+0x68>
+    5556:	2a6f      	cmp	r2, #111	; 0x6f
+    5558:	d029      	beq.n	55ae <_printf_i+0xae>
+    555a:	2a70      	cmp	r2, #112	; 0x70
+    555c:	d1e7      	bne.n	552e <_printf_i+0x2e>
+    555e:	2220      	movs	r2, #32
+    5560:	6809      	ldr	r1, [r1, #0]
+    5562:	430a      	orrs	r2, r1
+    5564:	6022      	str	r2, [r4, #0]
+    5566:	e003      	b.n	5570 <_printf_i+0x70>
+    5568:	2a75      	cmp	r2, #117	; 0x75
+    556a:	d020      	beq.n	55ae <_printf_i+0xae>
+    556c:	2a78      	cmp	r2, #120	; 0x78
+    556e:	d1de      	bne.n	552e <_printf_i+0x2e>
+    5570:	0022      	movs	r2, r4
+    5572:	2178      	movs	r1, #120	; 0x78
+    5574:	3245      	adds	r2, #69	; 0x45
+    5576:	7011      	strb	r1, [r2, #0]
+    5578:	4a6c      	ldr	r2, [pc, #432]	; (572c <_printf_i+0x22c>)
+    557a:	e030      	b.n	55de <_printf_i+0xde>
+    557c:	000e      	movs	r6, r1
+    557e:	681a      	ldr	r2, [r3, #0]
+    5580:	3642      	adds	r6, #66	; 0x42
+    5582:	1d11      	adds	r1, r2, #4
+    5584:	6019      	str	r1, [r3, #0]
+    5586:	6813      	ldr	r3, [r2, #0]
+    5588:	7033      	strb	r3, [r6, #0]
+    558a:	2301      	movs	r3, #1
+    558c:	e079      	b.n	5682 <_printf_i+0x182>
+    558e:	0649      	lsls	r1, r1, #25
+    5590:	d5d9      	bpl.n	5546 <_printf_i+0x46>
+    5592:	1d11      	adds	r1, r2, #4
+    5594:	6019      	str	r1, [r3, #0]
+    5596:	2300      	movs	r3, #0
+    5598:	5ed5      	ldrsh	r5, [r2, r3]
+    559a:	2d00      	cmp	r5, #0
+    559c:	da03      	bge.n	55a6 <_printf_i+0xa6>
+    559e:	232d      	movs	r3, #45	; 0x2d
+    55a0:	9a04      	ldr	r2, [sp, #16]
+    55a2:	426d      	negs	r5, r5
+    55a4:	7013      	strb	r3, [r2, #0]
+    55a6:	4b62      	ldr	r3, [pc, #392]	; (5730 <_printf_i+0x230>)
+    55a8:	270a      	movs	r7, #10
+    55aa:	9303      	str	r3, [sp, #12]
+    55ac:	e02f      	b.n	560e <_printf_i+0x10e>
+    55ae:	6820      	ldr	r0, [r4, #0]
+    55b0:	6819      	ldr	r1, [r3, #0]
+    55b2:	0605      	lsls	r5, r0, #24
+    55b4:	d503      	bpl.n	55be <_printf_i+0xbe>
+    55b6:	1d08      	adds	r0, r1, #4
+    55b8:	6018      	str	r0, [r3, #0]
+    55ba:	680d      	ldr	r5, [r1, #0]
+    55bc:	e005      	b.n	55ca <_printf_i+0xca>
+    55be:	0640      	lsls	r0, r0, #25
+    55c0:	d5f9      	bpl.n	55b6 <_printf_i+0xb6>
+    55c2:	680d      	ldr	r5, [r1, #0]
+    55c4:	1d08      	adds	r0, r1, #4
+    55c6:	6018      	str	r0, [r3, #0]
+    55c8:	b2ad      	uxth	r5, r5
+    55ca:	4b59      	ldr	r3, [pc, #356]	; (5730 <_printf_i+0x230>)
+    55cc:	2708      	movs	r7, #8
+    55ce:	9303      	str	r3, [sp, #12]
+    55d0:	2a6f      	cmp	r2, #111	; 0x6f
+    55d2:	d018      	beq.n	5606 <_printf_i+0x106>
+    55d4:	270a      	movs	r7, #10
+    55d6:	e016      	b.n	5606 <_printf_i+0x106>
+    55d8:	3145      	adds	r1, #69	; 0x45
+    55da:	700a      	strb	r2, [r1, #0]
+    55dc:	4a54      	ldr	r2, [pc, #336]	; (5730 <_printf_i+0x230>)
+    55de:	9203      	str	r2, [sp, #12]
+    55e0:	681a      	ldr	r2, [r3, #0]
+    55e2:	6821      	ldr	r1, [r4, #0]
+    55e4:	1d10      	adds	r0, r2, #4
+    55e6:	6018      	str	r0, [r3, #0]
+    55e8:	6815      	ldr	r5, [r2, #0]
+    55ea:	0608      	lsls	r0, r1, #24
+    55ec:	d522      	bpl.n	5634 <_printf_i+0x134>
+    55ee:	07cb      	lsls	r3, r1, #31
+    55f0:	d502      	bpl.n	55f8 <_printf_i+0xf8>
+    55f2:	2320      	movs	r3, #32
+    55f4:	4319      	orrs	r1, r3
+    55f6:	6021      	str	r1, [r4, #0]
+    55f8:	2710      	movs	r7, #16
+    55fa:	2d00      	cmp	r5, #0
+    55fc:	d103      	bne.n	5606 <_printf_i+0x106>
+    55fe:	2320      	movs	r3, #32
+    5600:	6822      	ldr	r2, [r4, #0]
+    5602:	439a      	bics	r2, r3
+    5604:	6022      	str	r2, [r4, #0]
+    5606:	0023      	movs	r3, r4
+    5608:	2200      	movs	r2, #0
+    560a:	3343      	adds	r3, #67	; 0x43
+    560c:	701a      	strb	r2, [r3, #0]
+    560e:	6863      	ldr	r3, [r4, #4]
+    5610:	60a3      	str	r3, [r4, #8]
+    5612:	2b00      	cmp	r3, #0
+    5614:	db5c      	blt.n	56d0 <_printf_i+0x1d0>
+    5616:	2204      	movs	r2, #4
+    5618:	6821      	ldr	r1, [r4, #0]
+    561a:	4391      	bics	r1, r2
+    561c:	6021      	str	r1, [r4, #0]
+    561e:	2d00      	cmp	r5, #0
+    5620:	d158      	bne.n	56d4 <_printf_i+0x1d4>
+    5622:	9e04      	ldr	r6, [sp, #16]
+    5624:	2b00      	cmp	r3, #0
+    5626:	d064      	beq.n	56f2 <_printf_i+0x1f2>
+    5628:	0026      	movs	r6, r4
+    562a:	9b03      	ldr	r3, [sp, #12]
+    562c:	3642      	adds	r6, #66	; 0x42
+    562e:	781b      	ldrb	r3, [r3, #0]
+    5630:	7033      	strb	r3, [r6, #0]
+    5632:	e05e      	b.n	56f2 <_printf_i+0x1f2>
+    5634:	0648      	lsls	r0, r1, #25
+    5636:	d5da      	bpl.n	55ee <_printf_i+0xee>
+    5638:	b2ad      	uxth	r5, r5
+    563a:	e7d8      	b.n	55ee <_printf_i+0xee>
+    563c:	6809      	ldr	r1, [r1, #0]
+    563e:	681a      	ldr	r2, [r3, #0]
+    5640:	0608      	lsls	r0, r1, #24
+    5642:	d505      	bpl.n	5650 <_printf_i+0x150>
+    5644:	1d11      	adds	r1, r2, #4
+    5646:	6019      	str	r1, [r3, #0]
+    5648:	6813      	ldr	r3, [r2, #0]
+    564a:	6962      	ldr	r2, [r4, #20]
+    564c:	601a      	str	r2, [r3, #0]
+    564e:	e006      	b.n	565e <_printf_i+0x15e>
+    5650:	0649      	lsls	r1, r1, #25
+    5652:	d5f7      	bpl.n	5644 <_printf_i+0x144>
+    5654:	1d11      	adds	r1, r2, #4
+    5656:	6019      	str	r1, [r3, #0]
+    5658:	6813      	ldr	r3, [r2, #0]
+    565a:	8aa2      	ldrh	r2, [r4, #20]
+    565c:	801a      	strh	r2, [r3, #0]
+    565e:	2300      	movs	r3, #0
+    5660:	9e04      	ldr	r6, [sp, #16]
+    5662:	6123      	str	r3, [r4, #16]
+    5664:	e054      	b.n	5710 <_printf_i+0x210>
+    5666:	681a      	ldr	r2, [r3, #0]
+    5668:	1d11      	adds	r1, r2, #4
+    566a:	6019      	str	r1, [r3, #0]
+    566c:	6816      	ldr	r6, [r2, #0]
+    566e:	2100      	movs	r1, #0
+    5670:	6862      	ldr	r2, [r4, #4]
+    5672:	0030      	movs	r0, r6
+    5674:	f000 f91a 	bl	58ac <memchr>
+    5678:	2800      	cmp	r0, #0
+    567a:	d001      	beq.n	5680 <_printf_i+0x180>
+    567c:	1b80      	subs	r0, r0, r6
+    567e:	6060      	str	r0, [r4, #4]
+    5680:	6863      	ldr	r3, [r4, #4]
+    5682:	6123      	str	r3, [r4, #16]
+    5684:	2300      	movs	r3, #0
+    5686:	9a04      	ldr	r2, [sp, #16]
+    5688:	7013      	strb	r3, [r2, #0]
+    568a:	e041      	b.n	5710 <_printf_i+0x210>
+    568c:	6923      	ldr	r3, [r4, #16]
+    568e:	0032      	movs	r2, r6
+    5690:	9906      	ldr	r1, [sp, #24]
+    5692:	9805      	ldr	r0, [sp, #20]
+    5694:	9d07      	ldr	r5, [sp, #28]
+    5696:	47a8      	blx	r5
+    5698:	1c43      	adds	r3, r0, #1
+    569a:	d043      	beq.n	5724 <_printf_i+0x224>
+    569c:	6823      	ldr	r3, [r4, #0]
+    569e:	2500      	movs	r5, #0
+    56a0:	079b      	lsls	r3, r3, #30
+    56a2:	d40f      	bmi.n	56c4 <_printf_i+0x1c4>
+    56a4:	9b09      	ldr	r3, [sp, #36]	; 0x24
+    56a6:	68e0      	ldr	r0, [r4, #12]
+    56a8:	4298      	cmp	r0, r3
+    56aa:	da3d      	bge.n	5728 <_printf_i+0x228>
+    56ac:	0018      	movs	r0, r3
+    56ae:	e03b      	b.n	5728 <_printf_i+0x228>
+    56b0:	0022      	movs	r2, r4
+    56b2:	2301      	movs	r3, #1
+    56b4:	3219      	adds	r2, #25
+    56b6:	9906      	ldr	r1, [sp, #24]
+    56b8:	9805      	ldr	r0, [sp, #20]
+    56ba:	9e07      	ldr	r6, [sp, #28]
+    56bc:	47b0      	blx	r6
+    56be:	1c43      	adds	r3, r0, #1
+    56c0:	d030      	beq.n	5724 <_printf_i+0x224>
+    56c2:	3501      	adds	r5, #1
+    56c4:	68e3      	ldr	r3, [r4, #12]
+    56c6:	9a09      	ldr	r2, [sp, #36]	; 0x24
+    56c8:	1a9b      	subs	r3, r3, r2
+    56ca:	429d      	cmp	r5, r3
+    56cc:	dbf0      	blt.n	56b0 <_printf_i+0x1b0>
+    56ce:	e7e9      	b.n	56a4 <_printf_i+0x1a4>
+    56d0:	2d00      	cmp	r5, #0
+    56d2:	d0a9      	beq.n	5628 <_printf_i+0x128>
+    56d4:	9e04      	ldr	r6, [sp, #16]
+    56d6:	0028      	movs	r0, r5
+    56d8:	0039      	movs	r1, r7
+    56da:	f7fc fdc5 	bl	2268 <__aeabi_uidivmod>
+    56de:	9b03      	ldr	r3, [sp, #12]
+    56e0:	3e01      	subs	r6, #1
+    56e2:	5c5b      	ldrb	r3, [r3, r1]
+    56e4:	0028      	movs	r0, r5
+    56e6:	7033      	strb	r3, [r6, #0]
+    56e8:	0039      	movs	r1, r7
+    56ea:	f7fc fd37 	bl	215c <__udivsi3>
+    56ee:	1e05      	subs	r5, r0, #0
+    56f0:	d1f1      	bne.n	56d6 <_printf_i+0x1d6>
+    56f2:	2f08      	cmp	r7, #8
+    56f4:	d109      	bne.n	570a <_printf_i+0x20a>
+    56f6:	6823      	ldr	r3, [r4, #0]
+    56f8:	07db      	lsls	r3, r3, #31
+    56fa:	d506      	bpl.n	570a <_printf_i+0x20a>
+    56fc:	6863      	ldr	r3, [r4, #4]
+    56fe:	6922      	ldr	r2, [r4, #16]
+    5700:	4293      	cmp	r3, r2
+    5702:	dc02      	bgt.n	570a <_printf_i+0x20a>
+    5704:	2330      	movs	r3, #48	; 0x30
+    5706:	3e01      	subs	r6, #1
+    5708:	7033      	strb	r3, [r6, #0]
+    570a:	9b04      	ldr	r3, [sp, #16]
+    570c:	1b9b      	subs	r3, r3, r6
+    570e:	6123      	str	r3, [r4, #16]
+    5710:	9b07      	ldr	r3, [sp, #28]
+    5712:	aa09      	add	r2, sp, #36	; 0x24
+    5714:	9300      	str	r3, [sp, #0]
+    5716:	0021      	movs	r1, r4
+    5718:	9b06      	ldr	r3, [sp, #24]
+    571a:	9805      	ldr	r0, [sp, #20]
+    571c:	f7ff fe82 	bl	5424 <_printf_common>
+    5720:	1c43      	adds	r3, r0, #1
+    5722:	d1b3      	bne.n	568c <_printf_i+0x18c>
+    5724:	2001      	movs	r0, #1
+    5726:	4240      	negs	r0, r0
+    5728:	b00b      	add	sp, #44	; 0x2c
+    572a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    572c:	00005b22 	.word	0x00005b22
+    5730:	00005b11 	.word	0x00005b11
+
+00005734 <_sbrk_r>:
+    5734:	2300      	movs	r3, #0
+    5736:	b570      	push	{r4, r5, r6, lr}
+    5738:	4c06      	ldr	r4, [pc, #24]	; (5754 <_sbrk_r+0x20>)
+    573a:	0005      	movs	r5, r0
+    573c:	0008      	movs	r0, r1
+    573e:	6023      	str	r3, [r4, #0]
+    5740:	f7fc f97c 	bl	1a3c <_sbrk>
+    5744:	1c43      	adds	r3, r0, #1
+    5746:	d103      	bne.n	5750 <_sbrk_r+0x1c>
+    5748:	6823      	ldr	r3, [r4, #0]
+    574a:	2b00      	cmp	r3, #0
+    574c:	d000      	beq.n	5750 <_sbrk_r+0x1c>
+    574e:	602b      	str	r3, [r5, #0]
+    5750:	bd70      	pop	{r4, r5, r6, pc}
+    5752:	46c0      	nop			; (mov r8, r8)
+    5754:	2000029c 	.word	0x2000029c
+
+00005758 <__sread>:
+    5758:	b570      	push	{r4, r5, r6, lr}
+    575a:	000c      	movs	r4, r1
+    575c:	250e      	movs	r5, #14
+    575e:	5f49      	ldrsh	r1, [r1, r5]
+    5760:	f000 f8b2 	bl	58c8 <_read_r>
+    5764:	2800      	cmp	r0, #0
+    5766:	db03      	blt.n	5770 <__sread+0x18>
+    5768:	6d63      	ldr	r3, [r4, #84]	; 0x54
+    576a:	181b      	adds	r3, r3, r0
+    576c:	6563      	str	r3, [r4, #84]	; 0x54
+    576e:	bd70      	pop	{r4, r5, r6, pc}
+    5770:	89a3      	ldrh	r3, [r4, #12]
+    5772:	4a02      	ldr	r2, [pc, #8]	; (577c <__sread+0x24>)
+    5774:	4013      	ands	r3, r2
+    5776:	81a3      	strh	r3, [r4, #12]
+    5778:	e7f9      	b.n	576e <__sread+0x16>
+    577a:	46c0      	nop			; (mov r8, r8)
+    577c:	ffffefff 	.word	0xffffefff
+
+00005780 <__swrite>:
+    5780:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    5782:	001f      	movs	r7, r3
+    5784:	898b      	ldrh	r3, [r1, #12]
+    5786:	0005      	movs	r5, r0
+    5788:	000c      	movs	r4, r1
+    578a:	0016      	movs	r6, r2
+    578c:	05db      	lsls	r3, r3, #23
+    578e:	d505      	bpl.n	579c <__swrite+0x1c>
+    5790:	230e      	movs	r3, #14
+    5792:	5ec9      	ldrsh	r1, [r1, r3]
+    5794:	2200      	movs	r2, #0
+    5796:	2302      	movs	r3, #2
+    5798:	f000 f874 	bl	5884 <_lseek_r>
+    579c:	89a3      	ldrh	r3, [r4, #12]
+    579e:	4a05      	ldr	r2, [pc, #20]	; (57b4 <__swrite+0x34>)
+    57a0:	0028      	movs	r0, r5
+    57a2:	4013      	ands	r3, r2
+    57a4:	81a3      	strh	r3, [r4, #12]
+    57a6:	0032      	movs	r2, r6
+    57a8:	230e      	movs	r3, #14
+    57aa:	5ee1      	ldrsh	r1, [r4, r3]
+    57ac:	003b      	movs	r3, r7
+    57ae:	f000 f81f 	bl	57f0 <_write_r>
+    57b2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    57b4:	ffffefff 	.word	0xffffefff
+
+000057b8 <__sseek>:
+    57b8:	b570      	push	{r4, r5, r6, lr}
+    57ba:	000c      	movs	r4, r1
+    57bc:	250e      	movs	r5, #14
+    57be:	5f49      	ldrsh	r1, [r1, r5]
+    57c0:	f000 f860 	bl	5884 <_lseek_r>
+    57c4:	89a3      	ldrh	r3, [r4, #12]
+    57c6:	1c42      	adds	r2, r0, #1
+    57c8:	d103      	bne.n	57d2 <__sseek+0x1a>
+    57ca:	4a05      	ldr	r2, [pc, #20]	; (57e0 <__sseek+0x28>)
+    57cc:	4013      	ands	r3, r2
+    57ce:	81a3      	strh	r3, [r4, #12]
+    57d0:	bd70      	pop	{r4, r5, r6, pc}
+    57d2:	2280      	movs	r2, #128	; 0x80
+    57d4:	0152      	lsls	r2, r2, #5
+    57d6:	4313      	orrs	r3, r2
+    57d8:	81a3      	strh	r3, [r4, #12]
+    57da:	6560      	str	r0, [r4, #84]	; 0x54
+    57dc:	e7f8      	b.n	57d0 <__sseek+0x18>
+    57de:	46c0      	nop			; (mov r8, r8)
+    57e0:	ffffefff 	.word	0xffffefff
+
+000057e4 <__sclose>:
+    57e4:	b510      	push	{r4, lr}
+    57e6:	230e      	movs	r3, #14
+    57e8:	5ec9      	ldrsh	r1, [r1, r3]
+    57ea:	f000 f815 	bl	5818 <_close_r>
+    57ee:	bd10      	pop	{r4, pc}
+
+000057f0 <_write_r>:
+    57f0:	b570      	push	{r4, r5, r6, lr}
+    57f2:	0005      	movs	r5, r0
+    57f4:	0008      	movs	r0, r1
+    57f6:	0011      	movs	r1, r2
+    57f8:	2200      	movs	r2, #0
+    57fa:	4c06      	ldr	r4, [pc, #24]	; (5814 <_write_r+0x24>)
+    57fc:	6022      	str	r2, [r4, #0]
+    57fe:	001a      	movs	r2, r3
+    5800:	f7fb f970 	bl	ae4 <_write>
+    5804:	1c43      	adds	r3, r0, #1
+    5806:	d103      	bne.n	5810 <_write_r+0x20>
+    5808:	6823      	ldr	r3, [r4, #0]
+    580a:	2b00      	cmp	r3, #0
+    580c:	d000      	beq.n	5810 <_write_r+0x20>
+    580e:	602b      	str	r3, [r5, #0]
+    5810:	bd70      	pop	{r4, r5, r6, pc}
+    5812:	46c0      	nop			; (mov r8, r8)
+    5814:	2000029c 	.word	0x2000029c
+
+00005818 <_close_r>:
+    5818:	2300      	movs	r3, #0
+    581a:	b570      	push	{r4, r5, r6, lr}
+    581c:	4c06      	ldr	r4, [pc, #24]	; (5838 <_close_r+0x20>)
+    581e:	0005      	movs	r5, r0
+    5820:	0008      	movs	r0, r1
+    5822:	6023      	str	r3, [r4, #0]
+    5824:	f7fc f91a 	bl	1a5c <_close>
+    5828:	1c43      	adds	r3, r0, #1
+    582a:	d103      	bne.n	5834 <_close_r+0x1c>
+    582c:	6823      	ldr	r3, [r4, #0]
+    582e:	2b00      	cmp	r3, #0
+    5830:	d000      	beq.n	5834 <_close_r+0x1c>
+    5832:	602b      	str	r3, [r5, #0]
+    5834:	bd70      	pop	{r4, r5, r6, pc}
+    5836:	46c0      	nop			; (mov r8, r8)
+    5838:	2000029c 	.word	0x2000029c
+
+0000583c <_fstat_r>:
+    583c:	2300      	movs	r3, #0
+    583e:	b570      	push	{r4, r5, r6, lr}
+    5840:	4c06      	ldr	r4, [pc, #24]	; (585c <_fstat_r+0x20>)
+    5842:	0005      	movs	r5, r0
+    5844:	0008      	movs	r0, r1
+    5846:	0011      	movs	r1, r2
+    5848:	6023      	str	r3, [r4, #0]
+    584a:	f7fc f90a 	bl	1a62 <_fstat>
+    584e:	1c43      	adds	r3, r0, #1
+    5850:	d103      	bne.n	585a <_fstat_r+0x1e>
+    5852:	6823      	ldr	r3, [r4, #0]
+    5854:	2b00      	cmp	r3, #0
+    5856:	d000      	beq.n	585a <_fstat_r+0x1e>
+    5858:	602b      	str	r3, [r5, #0]
+    585a:	bd70      	pop	{r4, r5, r6, pc}
+    585c:	2000029c 	.word	0x2000029c
+
+00005860 <_isatty_r>:
+    5860:	2300      	movs	r3, #0
+    5862:	b570      	push	{r4, r5, r6, lr}
+    5864:	4c06      	ldr	r4, [pc, #24]	; (5880 <_isatty_r+0x20>)
+    5866:	0005      	movs	r5, r0
+    5868:	0008      	movs	r0, r1
+    586a:	6023      	str	r3, [r4, #0]
+    586c:	f7fc f8fe 	bl	1a6c <_isatty>
+    5870:	1c43      	adds	r3, r0, #1
+    5872:	d103      	bne.n	587c <_isatty_r+0x1c>
+    5874:	6823      	ldr	r3, [r4, #0]
+    5876:	2b00      	cmp	r3, #0
+    5878:	d000      	beq.n	587c <_isatty_r+0x1c>
+    587a:	602b      	str	r3, [r5, #0]
+    587c:	bd70      	pop	{r4, r5, r6, pc}
+    587e:	46c0      	nop			; (mov r8, r8)
+    5880:	2000029c 	.word	0x2000029c
+
+00005884 <_lseek_r>:
+    5884:	b570      	push	{r4, r5, r6, lr}
+    5886:	0005      	movs	r5, r0
+    5888:	0008      	movs	r0, r1
+    588a:	0011      	movs	r1, r2
+    588c:	2200      	movs	r2, #0
+    588e:	4c06      	ldr	r4, [pc, #24]	; (58a8 <_lseek_r+0x24>)
+    5890:	6022      	str	r2, [r4, #0]
+    5892:	001a      	movs	r2, r3
+    5894:	f7fc f8ec 	bl	1a70 <_lseek>
+    5898:	1c43      	adds	r3, r0, #1
+    589a:	d103      	bne.n	58a4 <_lseek_r+0x20>
+    589c:	6823      	ldr	r3, [r4, #0]
+    589e:	2b00      	cmp	r3, #0
+    58a0:	d000      	beq.n	58a4 <_lseek_r+0x20>
+    58a2:	602b      	str	r3, [r5, #0]
+    58a4:	bd70      	pop	{r4, r5, r6, pc}
+    58a6:	46c0      	nop			; (mov r8, r8)
+    58a8:	2000029c 	.word	0x2000029c
+
+000058ac <memchr>:
+    58ac:	b2c9      	uxtb	r1, r1
+    58ae:	1882      	adds	r2, r0, r2
+    58b0:	4290      	cmp	r0, r2
+    58b2:	d101      	bne.n	58b8 <memchr+0xc>
+    58b4:	2000      	movs	r0, #0
+    58b6:	4770      	bx	lr
+    58b8:	7803      	ldrb	r3, [r0, #0]
+    58ba:	428b      	cmp	r3, r1
+    58bc:	d0fb      	beq.n	58b6 <memchr+0xa>
+    58be:	3001      	adds	r0, #1
+    58c0:	e7f6      	b.n	58b0 <memchr+0x4>
+
+000058c2 <__malloc_lock>:
+    58c2:	4770      	bx	lr
+
+000058c4 <__malloc_unlock>:
+    58c4:	4770      	bx	lr
+	...
+
+000058c8 <_read_r>:
+    58c8:	b570      	push	{r4, r5, r6, lr}
+    58ca:	0005      	movs	r5, r0
+    58cc:	0008      	movs	r0, r1
+    58ce:	0011      	movs	r1, r2
+    58d0:	2200      	movs	r2, #0
+    58d2:	4c06      	ldr	r4, [pc, #24]	; (58ec <_read_r+0x24>)
+    58d4:	6022      	str	r2, [r4, #0]
+    58d6:	001a      	movs	r2, r3
+    58d8:	f7fb f8e8 	bl	aac <_read>
+    58dc:	1c43      	adds	r3, r0, #1
+    58de:	d103      	bne.n	58e8 <_read_r+0x20>
+    58e0:	6823      	ldr	r3, [r4, #0]
+    58e2:	2b00      	cmp	r3, #0
+    58e4:	d000      	beq.n	58e8 <_read_r+0x20>
+    58e6:	602b      	str	r3, [r5, #0]
+    58e8:	bd70      	pop	{r4, r5, r6, pc}
+    58ea:	46c0      	nop			; (mov r8, r8)
+    58ec:	2000029c 	.word	0x2000029c
+    58f0:	00000002 	.word	0x00000002
+    58f4:	00000003 	.word	0x00000003
+    58f8:	00000028 	.word	0x00000028
+    58fc:	00000029 	.word	0x00000029
+    5900:	00000004 	.word	0x00000004
+    5904:	00000005 	.word	0x00000005
+    5908:	00000006 	.word	0x00000006
+    590c:	00000007 	.word	0x00000007
+    5910:	00000020 	.word	0x00000020
+    5914:	00000021 	.word	0x00000021
+    5918:	00000022 	.word	0x00000022
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+    5928:	00000026 	.word	0x00000026
+    592c:	00000027 	.word	0x00000027
+    5930:	00000008 	.word	0x00000008
+    5934:	00000009 	.word	0x00000009
+    5938:	0000000a 	.word	0x0000000a
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+    5940:	42000800 	.word	0x42000800
+    5944:	42000c00 	.word	0x42000c00
+    5948:	42001000 	.word	0x42001000
+    594c:	42001400 	.word	0x42001400
+    5950:	42001800 	.word	0x42001800
+    5954:	42001c00 	.word	0x42001c00
+    5958:	325b6325 	.word	0x325b6325
+    595c:	6325004a 	.word	0x6325004a
+    5960:	2000755b 	.word	0x2000755b
+    5964:	5b1b2d2d 	.word	0x5b1b2d2d
+    5968:	313b3133 	.word	0x313b3133
+    596c:	6550206d 	.word	0x6550206d
+    5970:	6975676e 	.word	0x6975676e
+    5974:	1b73276e 	.word	0x1b73276e
+    5978:	3b3b305b 	.word	0x3b3b305b
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+    5980:	444d4153 	.word	0x444d4153
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+    59b0:	6d655400 	.word	0x6d655400
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+    5a00:	000024ac 	.word	0x000024ac
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+    5a10:	000024bc 	.word	0x000024bc
+    5a14:	000024bc 	.word	0x000024bc
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+    5a1c:	00003294 	.word	0x00003294
+    5a20:	00003276 	.word	0x00003276
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+    5a28:	0000314e 	.word	0x0000314e
+    5a2c:	00003230 	.word	0x00003230
+    5a30:	00003268 	.word	0x00003268
+    5a34:	00003230 	.word	0x00003230
+    5a38:	0000314e 	.word	0x0000314e
+    5a3c:	00003276 	.word	0x00003276
+    5a40:	00003276 	.word	0x00003276
+    5a44:	00003268 	.word	0x00003268
+    5a48:	0000314e 	.word	0x0000314e
+    5a4c:	00003146 	.word	0x00003146
+    5a50:	00003146 	.word	0x00003146
+    5a54:	00003146 	.word	0x00003146
+    5a58:	000034ac 	.word	0x000034ac
+    5a5c:	00003af4 	.word	0x00003af4
+    5a60:	000039b4 	.word	0x000039b4
+    5a64:	000039b4 	.word	0x000039b4
+    5a68:	000039b0 	.word	0x000039b0
+    5a6c:	00003acc 	.word	0x00003acc
+    5a70:	00003acc 	.word	0x00003acc
+    5a74:	00003abe 	.word	0x00003abe
+    5a78:	000039b0 	.word	0x000039b0
+    5a7c:	00003acc 	.word	0x00003acc
+    5a80:	00003abe 	.word	0x00003abe
+    5a84:	00003acc 	.word	0x00003acc
+    5a88:	000039b0 	.word	0x000039b0
+    5a8c:	00003ad4 	.word	0x00003ad4
+    5a90:	00003ad4 	.word	0x00003ad4
+    5a94:	00003ad4 	.word	0x00003ad4
+    5a98:	00003cd8 	.word	0x00003cd8
+
+00005a9c <_global_impure_ptr>:
+    5a9c:	2000001c                                ... 
+
+00005aa0 <__sf_fake_stderr>:
+	...
+
+00005ac0 <__sf_fake_stdin>:
+	...
+
+00005ae0 <__sf_fake_stdout>:
+	...
+    5b00:	2b302d23 6c680020 6665004c 47464567     #-0+ .hlL.efgEFG
+    5b10:	32313000 36353433 41393837 45444342     .0123456789ABCDE
+    5b20:	31300046 35343332 39383736 64636261     F.0123456789abcd
+    5b30:	00006665                                ef..
+
+00005b34 <_init>:
+    5b34:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    5b36:	46c0      	nop			; (mov r8, r8)
+    5b38:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    5b3a:	bc08      	pop	{r3}
+    5b3c:	469e      	mov	lr, r3
+    5b3e:	4770      	bx	lr
+
+00005b40 <__init_array_start>:
+    5b40:	000000dd 	.word	0x000000dd
+
+00005b44 <_fini>:
+    5b44:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    5b46:	46c0      	nop			; (mov r8, r8)
+    5b48:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    5b4a:	bc08      	pop	{r3}
+    5b4c:	469e      	mov	lr, r3
+    5b4e:	4770      	bx	lr
+
+00005b50 <__fini_array_start>:
+    5b50:	000000b5 	.word	0x000000b5
diff --git a/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.map b/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.map
index 50616bb..90e9ab1 100644
--- a/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.map
+++ b/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.map
@@ -1,1868 +1,2151 @@
-Archive member included to satisfy reference by file (symbol)
-
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
-                              src/ASF/sam0/drivers/sercom/sercom.o (__gnu_thumb1_case_uqi)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
-                              src/ASF/common2/services/delay/sam0/systick_counter.o (__aeabi_uidiv)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) (__aeabi_idiv0)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_ashldi3.o)
-                              src/ASF/sam0/drivers/sercom/sercom.o (__aeabi_llsl)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_muldi3.o)
-                              src/ASF/sam0/drivers/sercom/sercom.o (__aeabi_lmul)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
-                              src/drivers/padc.o (__aeabi_fmul)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subsf3.o)
-                              src/main.o (__aeabi_fsub)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixsfsi.o)
-                              src/main.o (__aeabi_f2iz)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
-                              src/main.o (__aeabi_i2f)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsisf.o)
-                              src/drivers/padc.o (__aeabi_ui2f)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o) (__clzsi2)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (exit)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (__libc_init_array)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
-                              src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o (memcpy)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (memset)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
-                              src/main.o (printf)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o)
-                              src/main.o (puts)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
-                              src/drivers/pusart.o (setbuf)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o) (setvbuf)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wbuf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o) (__swbuf_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wsetup.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o) (__swsetup_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fflush.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (_fflush_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o) (__sinit)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fwalk.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_fwalk)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-makebuf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (__swhatbuf_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (malloc)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o) (_free_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_malloc_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o) (_vfprintf_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (_printf_i)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o) (_sbrk_r)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
-                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (__sread)
-c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
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-                0x00000000        0x1 src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
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-Cross Reference Table
-
-Symbol                                            File
-AC_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-ADC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-DAC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-DMAC_Handler                                      src/ASF/sam0/drivers/dma/dma.o
-Dummy_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-EIC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-EVSYS_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-HardFault_Handler                                 src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-I2S_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-NMI_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-NVMCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-PM_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-PTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-PendSV_Handler                                    src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-RTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-Reset_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SERCOM0_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM1_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM2_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM3_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM4_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SERCOM5_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-SVC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SYSCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SysTick_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-SystemCoreClock                                   src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
-SystemCoreClockUpdate                             src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
-SystemInit                                        src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
-TC3_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
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-TC5_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TC6_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TC7_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TCC0_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TCC1_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-TCC2_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-USB_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-WDT_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-_Jv_RegisterClasses                               c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
-__aeabi_f2iz                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixsfsi.o)
-                                                  src/main.o
-__aeabi_fmul                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
-                                                  src/main.o
-                                                  src/drivers/padc.o
-__aeabi_fsub                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subsf3.o)
-                                                  src/main.o
-__aeabi_i2f                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
-                                                  src/main.o
-__aeabi_idiv                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
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-_malloc_usable_size_r                             c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
-_printf_common                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
-_printf_float                                     c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-_printf_i                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-_printf_r                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
-_puts_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o)
-_read                                             src/ASF/sam0/utils/stdio/read.o
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
-_read_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
-_realloc_r                                        c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
-_reclaim_reent                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
-_sbrk                                             src/ASF/sam0/utils/syscalls/gcc/syscalls.o
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
-_sbrk_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
-_sercom_get_async_baud_val                        src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_sercom_get_default_pad                           src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_sercom_get_interrupt_vector                      src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-                                                  src/drivers/pusart.o
-_sercom_get_sercom_inst_index                     src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_sercom_get_sync_baud_val                         src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_sercom_instances                                 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_sercom_set_handler                               src/ASF/sam0/drivers/sercom/sercom_interrupt.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_sfixed                                           src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-_srelocate                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-_start                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-_system_divas_init                                src/ASF/sam0/drivers/system/system.o
-_system_dummy_init                                src/ASF/sam0/drivers/system/system.o
-_system_events_init                               src/ASF/sam0/drivers/system/system.o
-_system_extint_init                               src/ASF/sam0/drivers/system/system.o
-_szero                                            src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-_usart_interrupt_handler                          src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-_usart_read_buffer                                src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-_usart_write_buffer                               src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-_vfiprintf_r                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-_vfprintf_r                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
-_write                                            src/ASF/sam0/utils/stdio/write.o
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
-_write_r                                          c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
-adc_descriptor                                    src/drivers/padc.o
-adc_get_config_defaults                           src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
-                                                  src/drivers/padc.o
-adc_init                                          src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
-                                                  src/drivers/padc.o
-adc_regular_ain_channel                           src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
-adc_set_window_mode                               src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
-atexit                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-board_init                                        src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
-cleanup_glue                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
-cpu_irq_enter_critical                            src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-                                                  src/ASF/sam0/drivers/dma/dma.o
-cpu_irq_leave_critical                            src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
-                                                  src/ASF/sam0/drivers/dma/dma.o
-delay_cycles_ms                                   src/ASF/common2/services/delay/sam0/systick_counter.o
-                                                  src/main.o
-delay_cycles_us                                   src/ASF/common2/services/delay/sam0/systick_counter.o
-delay_init                                        src/ASF/common2/services/delay/sam0/systick_counter.o
-                                                  src/main.o
-descriptor_section                                src/ASF/sam0/drivers/dma/dma.o
-dma_abort_job                                     src/ASF/sam0/drivers/dma/dma.o
-dma_add_descriptor                                src/ASF/sam0/drivers/dma/dma.o
-                                                  src/drivers/padc.o
-dma_allocate                                      src/ASF/sam0/drivers/dma/dma.o
-                                                  src/drivers/padc.o
-dma_descriptor_create                             src/ASF/sam0/drivers/dma/dma.o
-                                                  src/drivers/padc.o
-dma_free                                          src/ASF/sam0/drivers/dma/dma.o
-dma_get_config_defaults                           src/ASF/sam0/drivers/dma/dma.o
-                                                  src/drivers/padc.o
-dma_resume_job                                    src/ASF/sam0/drivers/dma/dma.o
-dma_start_transfer_job                            src/ASF/sam0/drivers/dma/dma.o
-                                                  src/drivers/padc.o
-dma_suspend_job                                   src/ASF/sam0/drivers/dma/dma.o
-errno                                             c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-lseekr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isattyr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fstatr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-closer.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
-exception_table                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-exit                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-fflush                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fflush.o)
-free                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
-g_chan_interrupt_flag                             src/ASF/sam0/drivers/dma/dma.o
-g_interrupt_enabled                               src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
-                                                  src/main.o
-hardware_init_hook                                c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-iprintf                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
-link                                              src/ASF/sam0/utils/syscalls/gcc/syscalls.o
-main                                              src/main.o
-                                                  src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-malloc                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
-memchr                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
-memcpy                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
-                                                  src/ASF/sam0/drivers/dma/dma.o
-                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
-memmove                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
-memset                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
-padc_get_raw                                      src/drivers/padc.o
-padc_get_voltage                                  src/drivers/padc.o
-                                                  src/main.o
-padc_init                                         src/drivers/padc.o
-                                                  src/main.o
-padc_start                                        src/drivers/padc.o
-                                                  src/main.o
-port_group_set_config                             src/ASF/sam0/drivers/port/port.o
-port_pin_set_config                               src/ASF/sam0/drivers/port/port.o
-                                                  src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
-printf                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
-                                                  src/main.o
-ptr_get                                           src/ASF/sam0/utils/stdio/read.o
-                                                  src/drivers/pusart.o
-ptr_put                                           src/ASF/sam0/utils/stdio/write.o
-                                                  src/drivers/pusart.o
-pusart_init                                       src/drivers/pusart.o
-                                                  src/main.o
-puts                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o)
-                                                  src/main.o
-sercom_set_gclk_generator                         src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-setbuf                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
-                                                  src/drivers/pusart.o
-setvbuf                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
-                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
-software_init_hook                                c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
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-                                                  src/drivers/pusart.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
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-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-                                                  src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
-                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
-                                                  src/ASF/sam0/drivers/sercom/sercom.o
-                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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-                                                  src/ASF/common2/services/delay/sam0/systick_counter.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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-                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
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+ .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .text._malloc_usable_size_r
+                0x00000000       0x10 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .debug_frame   0x00000000       0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .ARM.attributes
+                0x00000000       0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .text          0x00000000      0x1d4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .debug_frame   0x00000000       0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .ARM.attributes
+                0x00000000       0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .text          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .eh_frame      0x00000000        0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .jcr           0x00000000        0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .ARM.attributes
+                0x00000000       0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .text          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+ .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+ .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+rom              0x00000000         0x00040000         xr
+ram              0x20000000         0x00008000         xrw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+LOAD src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+LOAD src/ASF/sam0/drivers/dma/dma.o
+LOAD src/ASF/sam0/drivers/sercom/sercom.o
+LOAD src/ASF/sam0/utils/stdio/read.o
+LOAD src/ASF/sam0/utils/stdio/write.o
+LOAD src/drivers/padc.o
+LOAD src/drivers/pusart.o
+LOAD src/ASF/sam0/drivers/sercom/usart/usart.o
+LOAD src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+LOAD src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+LOAD src/ASF/common2/services/delay/sam0/systick_counter.o
+LOAD src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+LOAD src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+LOAD src/ASF/sam0/drivers/port/port.o
+LOAD src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+LOAD src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+LOAD src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+LOAD src/ASF/sam0/drivers/system/pinmux/pinmux.o
+LOAD src/ASF/sam0/drivers/system/system.o
+LOAD src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+LOAD src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+LOAD src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+LOAD src/main.o
+START GROUP
+LOAD ../src/ASF/thirdparty/CMSIS/Lib/GCC\libarm_cortexM0l_math.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+                0x00002000                STACK_SIZE = DEFINED (STACK_SIZE)?STACK_SIZE:DEFINED (__stack_size__)?__stack_size__:0x2000
+
+.text           0x00000000     0x5b54
+                0x00000000                . = ALIGN (0x4)
+                0x00000000                _sfixed = .
+ *(.vectors .vectors.*)
+ .vectors       0x00000000       0xb4 src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+                0x00000000                exception_table
+ *(.text .text.* .gnu.linkonce.t.*)
+ .text          0x000000b4       0x60 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .text._adc_configure_ain_pin
+                0x00000114       0x40 src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+ .text.adc_get_config_defaults
+                0x00000154       0x42 src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                0x00000154                adc_get_config_defaults
+ *fill*         0x00000196        0x2 
+ .text.adc_init
+                0x00000198      0x2e0 src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                0x00000198                adc_init
+ .text.DMAC_Handler
+                0x00000478       0xa4 src/ASF/sam0/drivers/dma/dma.o
+                0x00000478                DMAC_Handler
+ .text.dma_get_config_defaults
+                0x0000051c       0x10 src/ASF/sam0/drivers/dma/dma.o
+                0x0000051c                dma_get_config_defaults
+ .text.dma_allocate
+                0x0000052c      0x12c src/ASF/sam0/drivers/dma/dma.o
+                0x0000052c                dma_allocate
+ .text.dma_start_transfer_job
+                0x00000658       0x8c src/ASF/sam0/drivers/dma/dma.o
+                0x00000658                dma_start_transfer_job
+ .text.dma_descriptor_create
+                0x000006e4       0xa8 src/ASF/sam0/drivers/dma/dma.o
+                0x000006e4                dma_descriptor_create
+ .text.dma_add_descriptor
+                0x0000078c       0x22 src/ASF/sam0/drivers/dma/dma.o
+                0x0000078c                dma_add_descriptor
+ *fill*         0x000007ae        0x2 
+ .text.long_division
+                0x000007b0       0x6c src/ASF/sam0/drivers/sercom/sercom.o
+ .text._sercom_get_sync_baud_val
+                0x0000081c       0x28 src/ASF/sam0/drivers/sercom/sercom.o
+                0x0000081c                _sercom_get_sync_baud_val
+ .text._sercom_get_async_baud_val
+                0x00000844       0x98 src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000844                _sercom_get_async_baud_val
+ .text.sercom_set_gclk_generator
+                0x000008dc       0x44 src/ASF/sam0/drivers/sercom/sercom.o
+                0x000008dc                sercom_set_gclk_generator
+ .text._sercom_get_default_pad
+                0x00000920      0x15c src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000920                _sercom_get_default_pad
+ .text._sercom_get_sercom_inst_index
+                0x00000a7c       0x30 src/ASF/sam0/drivers/sercom/sercom.o
+                0x00000a7c                _sercom_get_sercom_inst_index
+ .text._read    0x00000aac       0x38 src/ASF/sam0/utils/stdio/read.o
+                0x00000aac                _read
+ .text._write   0x00000ae4       0x34 src/ASF/sam0/utils/stdio/write.o
+                0x00000ae4                _write
+ .text.padc_init
+                0x00000b18       0xd8 src/drivers/padc.o
+                0x00000b18                padc_init
+ .text.padc_start
+                0x00000bf0       0x34 src/drivers/padc.o
+                0x00000bf0                padc_start
+ .text.padc_get_raw
+                0x00000c24       0x1c src/drivers/padc.o
+                0x00000c24                padc_get_raw
+ .text.padc_get_voltage
+                0x00000c40       0x24 src/drivers/padc.o
+                0x00000c40                padc_get_voltage
+ .text.usart_serial_getchar
+                0x00000c64       0x24 src/drivers/pusart.o
+ .text.usart_serial_putchar
+                0x00000c88       0x18 src/drivers/pusart.o
+ .text.pusart_init
+                0x00000ca0       0xf8 src/drivers/pusart.o
+                0x00000ca0                pusart_init
+ .text.usart_init
+                0x00000d98      0x2b8 src/ASF/sam0/drivers/sercom/usart/usart.o
+                0x00000d98                usart_init
+ .text.usart_write_wait
+                0x00001050       0x22 src/ASF/sam0/drivers/sercom/usart/usart.o
+                0x00001050                usart_write_wait
+ .text.usart_read_wait
+                0x00001072       0x68 src/ASF/sam0/drivers/sercom/usart/usart.o
+                0x00001072                usart_read_wait
+ *fill*         0x000010da        0x2 
+ .text._usart_interrupt_handler
+                0x000010dc      0x168 src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                0x000010dc                _usart_interrupt_handler
+ .text._sercom_default_handler
+                0x00001244        0x2 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+ *fill*         0x00001246        0x2 
+ .text._sercom_set_handler
+                0x00001248       0x38 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x00001248                _sercom_set_handler
+ .text._sercom_get_interrupt_vector
+                0x00001280       0x2c src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x00001280                _sercom_get_interrupt_vector
+ .text.SERCOM0_Handler
+                0x000012ac       0x10 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x000012ac                SERCOM0_Handler
+ .text.SERCOM1_Handler
+                0x000012bc       0x10 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x000012bc                SERCOM1_Handler
+ .text.SERCOM2_Handler
+                0x000012cc       0x10 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x000012cc                SERCOM2_Handler
+ .text.SERCOM3_Handler
+                0x000012dc       0x10 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x000012dc                SERCOM3_Handler
+ .text.SERCOM4_Handler
+                0x000012ec       0x10 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x000012ec                SERCOM4_Handler
+ .text.SERCOM5_Handler
+                0x000012fc       0x10 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                0x000012fc                SERCOM5_Handler
+ .text.delay_init
+                0x0000130c       0x40 src/ASF/common2/services/delay/sam0/systick_counter.o
+                0x0000130c                delay_init
+ .text.delay_cycles_ms
+                0x0000134c       0x2c src/ASF/common2/services/delay/sam0/systick_counter.o
+                0x0000134c                delay_cycles_ms
+ .text.cpu_irq_enter_critical
+                0x00001378       0x34 src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                0x00001378                cpu_irq_enter_critical
+ .text.cpu_irq_leave_critical
+                0x000013ac       0x30 src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                0x000013ac                cpu_irq_leave_critical
+ .text.system_board_init
+                0x000013dc       0x34 src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+                0x000013dc                board_init
+                0x000013dc                system_board_init
+ .text.port_pin_set_config
+                0x00001410       0x20 src/ASF/sam0/drivers/port/port.o
+                0x00001410                port_pin_set_config
+ .text._system_dfll_wait_for_sync
+                0x00001430       0x10 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+ .text.system_clock_source_get_hz
+                0x00001440       0x90 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                0x00001440                system_clock_source_get_hz
+ .text.system_clock_source_osc8m_set_config
+                0x000014d0       0x3c src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                0x000014d0                system_clock_source_osc8m_set_config
+ .text.system_clock_source_enable
+                0x0000150c       0x90 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                0x0000150c                system_clock_source_enable
+ .text.system_clock_init
+                0x0000159c       0x90 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                0x0000159c                system_clock_init
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+ .text.system_gclk_init
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+                0x00001638                system_gclk_init
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+                0x00001658       0xa4 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                0x00001658                system_gclk_gen_set_config
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+                0x000016fc       0x40 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                0x000016fc                system_gclk_gen_enable
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+                0x0000173c       0x88 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                0x0000173c                system_gclk_gen_get_hz
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+                0x000017c4                system_gclk_chan_enable
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+                0x000017f4       0x58 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                0x000017f4                system_gclk_chan_disable
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+                0x0000184c                system_gclk_chan_set_config
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+                0x00001868                system_gclk_chan_get_hz
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+ .text.system_pinmux_pin_set_config
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+                0x00001920                system_pinmux_pin_set_config
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+                0x0000194c                _system_extint_init
+                0x0000194c                _system_events_init
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+                0x00001950                system_init
+ .text.Dummy_Handler
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+                0x0000197c                HardFault_Handler
+                0x0000197c                AC_Handler
+                0x0000197c                SysTick_Handler
+                0x0000197c                PendSV_Handler
+                0x0000197c                NMI_Handler
+                0x0000197c                TC7_Handler
+                0x0000197c                ADC_Handler
+                0x0000197c                TCC1_Handler
+                0x0000197c                TCC0_Handler
+                0x0000197c                RTC_Handler
+                0x0000197c                EIC_Handler
+                0x0000197c                TC6_Handler
+                0x0000197c                WDT_Handler
+                0x0000197c                TC4_Handler
+                0x0000197c                USB_Handler
+                0x0000197c                TC3_Handler
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+                0x0000197c                PM_Handler
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+                0x0000197c                TCC2_Handler
+                0x0000197c                EVSYS_Handler
+                0x0000197c                I2S_Handler
+                0x0000197c                NVMCTRL_Handler
+                0x0000197c                DAC_Handler
+                0x0000197c                PTC_Handler
+                0x0000197c                TC5_Handler
+                0x0000197c                SYSCTRL_Handler
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+                0x00001980       0xbc src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+                0x00001980                Reset_Handler
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+                0x00001a5c                _close
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+                0x00001a6c                _isatty
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+                0x00001a70                _lseek
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+
+Cross Reference Table
+
+Symbol                                            File
+AC_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+ADC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+DAC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+DMAC_Handler                                      src/ASF/sam0/drivers/dma/dma.o
+Dummy_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+EIC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+EVSYS_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+HardFault_Handler                                 src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+I2S_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+NMI_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+NVMCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+PM_Handler                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+PTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+PendSV_Handler                                    src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+RTC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+Reset_Handler                                     src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SERCOM0_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM1_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM2_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM3_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM4_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SERCOM5_Handler                                   src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+SVC_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SYSCTRL_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SysTick_Handler                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+SystemCoreClock                                   src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+SystemCoreClockUpdate                             src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+SystemInit                                        src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o
+TC3_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC4_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC5_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC6_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TC7_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TCC0_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TCC1_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+TCC2_Handler                                      src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+USB_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+WDT_Handler                                       src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_Jv_RegisterClasses                               c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+__aeabi_cdcmpeq                                   c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_cdcmple                                   c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_cdrcmple                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_d2f                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+                                                  src/main.o
+__aeabi_d2iz                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+__aeabi_d2uiz                                     c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+                                                  src/main.o
+__aeabi_dadd                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-e_log.o)
+                                                  src/main.o
+__aeabi_dcmpeq                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-e_log.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-w_log.o)
+__aeabi_dcmpge                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+__aeabi_dcmpgt                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-w_log.o)
+__aeabi_dcmple                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_dcmplt                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_dcmpun                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-w_log.o)
+__aeabi_ddiv                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-e_log.o)
+                                                  src/main.o
+__aeabi_dmul                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-e_log.o)
+                                                  src/main.o
+__aeabi_dsub                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-e_log.o)
+                                                  src/main.o
+__aeabi_f2d                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+                                                  src/main.o
+__aeabi_f2iz                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixsfsi.o)
+                                                  src/main.o
+__aeabi_fmul                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+                                                  src/main.o
+                                                  src/drivers/padc.o
+__aeabi_fsub                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subsf3.o)
+                                                  src/main.o
+__aeabi_i2d                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-e_log.o)
+__aeabi_i2f                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+                                                  src/main.o
+__aeabi_idiv                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+__aeabi_idiv0                                     c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
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+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wsetup.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wbuf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-errno.o)
+                                                  src/drivers/pusart.o
+_init                                             c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+_iprintf_r                                        c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+_isatty                                           src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isattyr.o)
+_isatty_r                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isattyr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-makebuf.o)
+_kill                                             src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+_lseek                                            src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-lseekr.o)
+_lseek_r                                          c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-lseekr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
+_mainCRTStartup                                   c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+_malloc_r                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-makebuf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
+_malloc_usable_size_r                             c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+_printf_common                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+_printf_float                                     c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+_printf_i                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+_printf_r                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+_puts_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o)
+_read                                             src/ASF/sam0/utils/stdio/read.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
+_read_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
+_realloc_r                                        c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+_reclaim_reent                                    c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+_sbrk                                             src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+_sbrk_r                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+_sercom_get_async_baud_val                        src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_get_default_pad                           src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_get_interrupt_vector                      src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/drivers/pusart.o
+_sercom_get_sercom_inst_index                     src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_get_sync_baud_val                         src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_instances                                 src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sercom_set_handler                               src/ASF/sam0/drivers/sercom/sercom_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_sfixed                                           src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_srelocate                                        src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_start                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+_system_divas_init                                src/ASF/sam0/drivers/system/system.o
+_system_dummy_init                                src/ASF/sam0/drivers/system/system.o
+_system_events_init                               src/ASF/sam0/drivers/system/system.o
+_system_extint_init                               src/ASF/sam0/drivers/system/system.o
+_szero                                            src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+_usart_interrupt_handler                          src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+_usart_read_buffer                                src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+_usart_write_buffer                               src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+_vfiprintf_r                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+_vfprintf_r                                       c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+_write                                            src/ASF/sam0/utils/stdio/write.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+_write_r                                          c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
+adc_descriptor                                    src/drivers/padc.o
+adc_get_config_defaults                           src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                                                  src/drivers/padc.o
+adc_init                                          src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+                                                  src/drivers/padc.o
+adc_regular_ain_channel                           src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+adc_set_window_mode                               src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+atexit                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+board_init                                        src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+cleanup_glue                                      c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+cpu_irq_enter_critical                            src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/dma/dma.o
+cpu_irq_leave_critical                            src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+                                                  src/ASF/sam0/drivers/dma/dma.o
+delay_cycles_ms                                   src/ASF/common2/services/delay/sam0/systick_counter.o
+                                                  src/main.o
+delay_cycles_us                                   src/ASF/common2/services/delay/sam0/systick_counter.o
+delay_init                                        src/ASF/common2/services/delay/sam0/systick_counter.o
+                                                  src/main.o
+descriptor_section                                src/ASF/sam0/drivers/dma/dma.o
+dma_abort_job                                     src/ASF/sam0/drivers/dma/dma.o
+dma_add_descriptor                                src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_allocate                                      src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_descriptor_create                             src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_free                                          src/ASF/sam0/drivers/dma/dma.o
+dma_get_config_defaults                           src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_resume_job                                    src/ASF/sam0/drivers/dma/dma.o
+dma_start_transfer_job                            src/ASF/sam0/drivers/dma/dma.o
+                                                  src/drivers/padc.o
+dma_suspend_job                                   src/ASF/sam0/drivers/dma/dma.o
+errno                                             c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-readr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-lseekr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isattyr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fstatr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-closer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+exception_table                                   src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+exit                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+fflush                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fflush.o)
+free                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+g_chan_interrupt_flag                             src/ASF/sam0/drivers/dma/dma.o
+g_interrupt_enabled                               src/ASF/common/utils/interrupt/interrupt_sam_nvic.o
+                                                  src/main.o
+hardware_init_hook                                c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+iprintf                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+link                                              src/ASF/sam0/utils/syscalls/gcc/syscalls.o
+log                                               c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-w_log.o)
+                                                  src/main.o
+main                                              src/main.o
+                                                  src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+malloc                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
+matherr                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-s_matherr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-w_log.o)
+memchr                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+memcpy                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+                                                  src/ASF/sam0/drivers/dma/dma.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+memmove                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+memset                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+nan                                               c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-s_nan.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a(lib_a-w_log.o)
+padc_get_raw                                      src/drivers/padc.o
+padc_get_voltage                                  src/drivers/padc.o
+                                                  src/main.o
+padc_init                                         src/drivers/padc.o
+                                                  src/main.o
+padc_start                                        src/drivers/padc.o
+                                                  src/main.o
+port_group_set_config                             src/ASF/sam0/drivers/port/port.o
+port_pin_set_config                               src/ASF/sam0/drivers/port/port.o
+                                                  src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+printf                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+                                                  src/main.o
+ptr_get                                           src/ASF/sam0/utils/stdio/read.o
+                                                  src/drivers/pusart.o
+ptr_put                                           src/ASF/sam0/utils/stdio/write.o
+                                                  src/drivers/pusart.o
+pusart_init                                       src/drivers/pusart.o
+                                                  src/main.o
+puts                                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-puts.o)
+                                                  src/main.o
+sercom_set_gclk_generator                         src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+setbuf                                            c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
+                                                  src/drivers/pusart.o
+setvbuf                                           c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setvbuf.o)
+                                                  c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-setbuf.o)
+software_init_hook                                c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+stdio_base                                        src/ASF/sam0/utils/stdio/write.o
+                                                  src/drivers/pusart.o
+                                                  src/ASF/sam0/utils/stdio/read.o
+system_board_init                                 src/ASF/sam0/boards/samd21_xplained_pro/board_init.o
+system_clock_init                                 src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_dfll_set_config               src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_disable                       src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_dpll_set_config               src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_enable                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_get_hz                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_clock_source_is_ready                      src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_osc32k_set_config             src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_osc8m_set_config              src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_write_calibration             src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_xosc32k_set_config            src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_clock_source_xosc_set_config               src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_gclk_chan_disable                          src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_enable                           src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+system_gclk_chan_get_hz                           src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+system_gclk_chan_is_enabled                       src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_is_locked                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_lock                             src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_chan_set_config                       src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/ASF/sam0/drivers/sercom/sercom.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+system_gclk_gen_disable                           src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_gen_enable                            src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_gclk_gen_get_hz                            src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/common2/services/delay/sam0/systick_counter.o
+system_gclk_gen_is_enabled                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+system_gclk_gen_set_config                        src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_gclk_init                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o
+                                                  src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o
+system_init                                       src/ASF/sam0/drivers/system/system.o
+                                                  src/main.o
+system_interrupt_clear_pending                    src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_get_priority                     src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_is_pending                       src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_set_pending                      src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_interrupt_set_priority                     src/ASF/sam0/drivers/system/interrupt/system_interrupt.o
+system_pinmux_group_set_config                    src/ASF/sam0/drivers/system/pinmux/pinmux.o
+                                                  src/ASF/sam0/drivers/port/port.o
+system_pinmux_group_set_input_sample_mode         src/ASF/sam0/drivers/system/pinmux/pinmux.o
+system_pinmux_group_set_output_strength           src/ASF/sam0/drivers/system/pinmux/pinmux.o
+system_pinmux_pin_set_config                      src/ASF/sam0/drivers/system/pinmux/pinmux.o
+                                                  src/ASF/sam0/drivers/port/port.o
+                                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o
+umod                                              src/main.o
+                                                  src/drivers/pusart.o
+usart_abort_job                                   src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_get_job_status                              src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_init                                        src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/drivers/pusart.o
+usart_read_buffer_job                             src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_read_buffer_wait                            src/ASF/sam0/drivers/sercom/usart/usart.o
+usart_read_job                                    src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_read_wait                                   src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/drivers/pusart.o
+usart_register_callback                           src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_unregister_callback                         src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_write_buffer_job                            src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_write_buffer_wait                           src/ASF/sam0/drivers/sercom/usart/usart.o
+usart_write_job                                   src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o
+usart_write_wait                                  src/ASF/sam0/drivers/sercom/usart/usart.o
+                                                  src/drivers/pusart.o
+vfiprintf                                         c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+vfprintf                                          c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
diff --git a/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.srec b/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.srec
index 1714cb1..a6ac284 100644
--- a/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.srec
+++ b/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.srec
@@ -1,889 +1,1472 @@
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diff --git a/D21_ADC_with_DMA/Release/Makefile b/D21_ADC_with_DMA/Release/Makefile
index dfae8e3..9ff592b 100644
--- a/D21_ADC_with_DMA/Release/Makefile
+++ b/D21_ADC_with_DMA/Release/Makefile
@@ -1,459 +1,459 @@
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-SHELL := cmd.exe
-RM := rm -rf
-
-USER_OBJS :=
-
-LIBS := 
-PROJ := 
-
-O_SRCS := 
-C_SRCS := 
-S_SRCS := 
-S_UPPER_SRCS := 
-OBJ_SRCS := 
-ASM_SRCS := 
-PREPROCESSING_SRCS := 
-OBJS := 
-OBJS_AS_ARGS := 
-C_DEPS := 
-C_DEPS_AS_ARGS := 
-EXECUTABLES := 
-OUTPUT_FILE_PATH :=
-OUTPUT_FILE_PATH_AS_ARGS :=
-AVR_APP_PATH :=$$$AVR_APP_PATH$$$
-QUOTE := "
-ADDITIONAL_DEPENDENCIES:=
-OUTPUT_FILE_DEP:=
-LIB_DEP:=
-LINKER_SCRIPT_DEP:=
-
-# Every subdirectory with source files must be described here
-SUBDIRS :=  \
-../src/ \
-../src/ASF/ \
-../src/ASF/common2/ \
-../src/ASF/common2/services/ \
-../src/ASF/common2/services/delay/ \
-../src/ASF/common2/services/delay/sam0/ \
-../src/ASF/common/ \
-../src/ASF/common/boards/ \
-../src/ASF/common/services/ \
-../src/ASF/common/services/serial/ \
-../src/ASF/common/services/serial/sam0_usart/ \
-../src/ASF/common/utils/ \
-../src/ASF/common/utils/interrupt/ \
-../src/ASF/sam0/ \
-../src/ASF/sam0/boards/ \
-../src/ASF/sam0/boards/samd21_xplained_pro/ \
-../src/ASF/sam0/drivers/ \
-../src/ASF/sam0/drivers/adc/ \
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/ \
-../src/ASF/sam0/drivers/dma/ \
-../src/ASF/sam0/drivers/dma/quick_start/ \
-../src/ASF/sam0/drivers/port/ \
-../src/ASF/sam0/drivers/port/quick_start/ \
-../src/ASF/sam0/drivers/sercom/ \
-../src/ASF/sam0/drivers/sercom/usart/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start_callback/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start_dma/ \
-../src/ASF/sam0/drivers/sercom/usart/quick_start_lin/ \
-../src/ASF/sam0/drivers/system/ \
-../src/ASF/sam0/drivers/system/clock/ \
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ \
-../src/ASF/sam0/drivers/system/interrupt/ \
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/ \
-../src/ASF/sam0/drivers/system/pinmux/ \
-../src/ASF/sam0/drivers/system/pinmux/quick_start/ \
-../src/ASF/sam0/drivers/system/power/ \
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/ \
-../src/ASF/sam0/drivers/system/reset/ \
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/ \
-../src/ASF/sam0/utils/ \
-../src/ASF/sam0/utils/cmsis/ \
-../src/ASF/sam0/utils/cmsis/samd21/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ \
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/ \
-../src/ASF/sam0/utils/cmsis/samd21/source/ \
-../src/ASF/sam0/utils/cmsis/samd21/source/gcc/ \
-../src/ASF/sam0/utils/header_files/ \
-../src/ASF/sam0/utils/linker_scripts/ \
-../src/ASF/sam0/utils/linker_scripts/samd21/ \
-../src/ASF/sam0/utils/linker_scripts/samd21/gcc/ \
-../src/ASF/sam0/utils/make/ \
-../src/ASF/sam0/utils/preprocessor/ \
-../src/ASF/sam0/utils/stdio/ \
-../src/ASF/sam0/utils/stdio/stdio_serial/ \
-../src/ASF/sam0/utils/syscalls/ \
-../src/ASF/sam0/utils/syscalls/gcc/ \
-../src/ASF/thirdparty/ \
-../src/ASF/thirdparty/CMSIS/ \
-../src/ASF/thirdparty/CMSIS/Include/ \
-../src/ASF/thirdparty/CMSIS/Lib/ \
-../src/ASF/thirdparty/CMSIS/Lib/GCC/ \
-../src/config/ \
-../src/drivers
-
-
-# Add inputs and outputs from these tool invocations to the build variables 
-C_SRCS +=  \
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
-../src/ASF/sam0/drivers/dma/dma.c \
-../src/ASF/sam0/drivers/sercom/sercom.c \
-../src/ASF/sam0/utils/stdio/read.c \
-../src/ASF/sam0/utils/stdio/write.c \
-../src/drivers/padc.c \
-../src/drivers/pusart.c \
-../src/ASF/sam0/drivers/sercom/usart/usart.c \
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
-../src/ASF/common2/services/delay/sam0/systick_counter.c \
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
-../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
-../src/ASF/sam0/drivers/port/port.c \
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
-../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
-../src/ASF/sam0/drivers/system/system.c \
-../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
-../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
-../src/main.c
-
-
-PREPROCESSING_SRCS += 
-
-
-ASM_SRCS += 
-
-
-OBJS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
-src/ASF/sam0/drivers/dma/dma.o \
-src/ASF/sam0/drivers/sercom/sercom.o \
-src/ASF/sam0/utils/stdio/read.o \
-src/ASF/sam0/utils/stdio/write.o \
-src/drivers/padc.o \
-src/drivers/pusart.o \
-src/ASF/sam0/drivers/sercom/usart/usart.o \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
-src/ASF/common2/services/delay/sam0/systick_counter.o \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
-src/ASF/sam0/drivers/port/port.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
-src/ASF/sam0/drivers/system/pinmux/pinmux.o \
-src/ASF/sam0/drivers/system/system.o \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
-src/main.o
-
-OBJS_AS_ARGS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
-src/ASF/sam0/drivers/dma/dma.o \
-src/ASF/sam0/drivers/sercom/sercom.o \
-src/ASF/sam0/utils/stdio/read.o \
-src/ASF/sam0/utils/stdio/write.o \
-src/drivers/padc.o \
-src/drivers/pusart.o \
-src/ASF/sam0/drivers/sercom/usart/usart.o \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
-src/ASF/common2/services/delay/sam0/systick_counter.o \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
-src/ASF/sam0/drivers/port/port.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
-src/ASF/sam0/drivers/system/pinmux/pinmux.o \
-src/ASF/sam0/drivers/system/system.o \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
-src/main.o
-
-C_DEPS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
-src/ASF/sam0/drivers/dma/dma.d \
-src/ASF/sam0/drivers/sercom/sercom.d \
-src/ASF/sam0/utils/stdio/read.d \
-src/ASF/sam0/utils/stdio/write.d \
-src/drivers/padc.d \
-src/drivers/pusart.d \
-src/ASF/sam0/drivers/sercom/usart/usart.d \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
-src/ASF/common2/services/delay/sam0/systick_counter.d \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
-src/ASF/sam0/drivers/port/port.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
-src/ASF/sam0/drivers/system/pinmux/pinmux.d \
-src/ASF/sam0/drivers/system/system.d \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
-src/main.d
-
-C_DEPS_AS_ARGS +=  \
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
-src/ASF/sam0/drivers/dma/dma.d \
-src/ASF/sam0/drivers/sercom/sercom.d \
-src/ASF/sam0/utils/stdio/read.d \
-src/ASF/sam0/utils/stdio/write.d \
-src/drivers/padc.d \
-src/drivers/pusart.d \
-src/ASF/sam0/drivers/sercom/usart/usart.d \
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
-src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
-src/ASF/common2/services/delay/sam0/systick_counter.d \
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
-src/ASF/sam0/drivers/port/port.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
-src/ASF/sam0/drivers/system/pinmux/pinmux.d \
-src/ASF/sam0/drivers/system/system.d \
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
-src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
-src/main.d
-
-OUTPUT_FILE_PATH +=D21_ADC_with_DMA.elf
-
-OUTPUT_FILE_PATH_AS_ARGS +=D21_ADC_with_DMA.elf
-
-ADDITIONAL_DEPENDENCIES:=
-
-OUTPUT_FILE_DEP:= ./makedep.mk
-
-LIB_DEP+= 
-
-LINKER_SCRIPT_DEP+=  \
-../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
-
-
-# AVR32/GNU C Compiler
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/drivers/dma/dma.o: ../src/ASF/sam0/drivers/dma/dma.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/drivers/sercom/sercom.o: ../src/ASF/sam0/drivers/sercom/sercom.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-src/ASF/sam0/utils/stdio/read.o: ../src/ASF/sam0/utils/stdio/read.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
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-src/ASF/sam0/utils/stdio/write.o: ../src/ASF/sam0/utils/stdio/write.c
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-src/drivers/padc.o: ../src/drivers/padc.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/drivers/pusart.o: ../src/drivers/pusart.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/sercom/usart/usart.o: ../src/ASF/sam0/drivers/sercom/usart/usart.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
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-src/ASF/sam0/drivers/sercom/sercom_interrupt.o: ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/common2/services/delay/sam0/systick_counter.o: ../src/ASF/common2/services/delay/sam0/systick_counter.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/port/port.o: ../src/ASF/sam0/drivers/port/port.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/pinmux/pinmux.o: ../src/ASF/sam0/drivers/system/pinmux/pinmux.c
-	@echo Building file: $<
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-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
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-src/ASF/sam0/drivers/system/system.o: ../src/ASF/sam0/drivers/system/system.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
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-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
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-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
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-src/ASF/sam0/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c
-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
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-	@echo Building file: $<
-	@echo Invoking: ARM/GNU C Compiler : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
-	@echo Finished building: $<
-	
-
-
-
-
-# AVR32/GNU Preprocessing Assembler
-
-
-
-# AVR32/GNU Assembler
-
-
-
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-endif
-
-# Add inputs and outputs from these tool invocations to the build variables 
-
-# All Target
-all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
-
-$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
-	@echo Building target: $@
-	@echo Invoking: ARM/GNU Linker : 6.3.1
-	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="D21_ADC_with_DMA.map" --specs=nano.specs -Wl,--start-group -larm_cortexM0l_math -lm  -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC"  -Wl,--gc-sections -mcpu=cortex-m0plus -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld  
-	@echo Finished building target: $@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS := 
+PROJ := 
+
+O_SRCS := 
+C_SRCS := 
+S_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+PREPROCESSING_SRCS := 
+OBJS := 
+OBJS_AS_ARGS := 
+C_DEPS := 
+C_DEPS_AS_ARGS := 
+EXECUTABLES := 
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+LIB_DEP:=
+LINKER_SCRIPT_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS :=  \
+../src/ \
+../src/ASF/ \
+../src/ASF/common2/ \
+../src/ASF/common2/services/ \
+../src/ASF/common2/services/delay/ \
+../src/ASF/common2/services/delay/sam0/ \
+../src/ASF/common/ \
+../src/ASF/common/boards/ \
+../src/ASF/common/services/ \
+../src/ASF/common/services/serial/ \
+../src/ASF/common/services/serial/sam0_usart/ \
+../src/ASF/common/utils/ \
+../src/ASF/common/utils/interrupt/ \
+../src/ASF/sam0/ \
+../src/ASF/sam0/boards/ \
+../src/ASF/sam0/boards/samd21_xplained_pro/ \
+../src/ASF/sam0/drivers/ \
+../src/ASF/sam0/drivers/adc/ \
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/ \
+../src/ASF/sam0/drivers/dma/ \
+../src/ASF/sam0/drivers/dma/quick_start/ \
+../src/ASF/sam0/drivers/port/ \
+../src/ASF/sam0/drivers/port/quick_start/ \
+../src/ASF/sam0/drivers/sercom/ \
+../src/ASF/sam0/drivers/sercom/usart/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start_callback/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start_dma/ \
+../src/ASF/sam0/drivers/sercom/usart/quick_start_lin/ \
+../src/ASF/sam0/drivers/system/ \
+../src/ASF/sam0/drivers/system/clock/ \
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ \
+../src/ASF/sam0/drivers/system/interrupt/ \
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/ \
+../src/ASF/sam0/drivers/system/pinmux/ \
+../src/ASF/sam0/drivers/system/pinmux/quick_start/ \
+../src/ASF/sam0/drivers/system/power/ \
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/ \
+../src/ASF/sam0/drivers/system/reset/ \
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/ \
+../src/ASF/sam0/utils/ \
+../src/ASF/sam0/utils/cmsis/ \
+../src/ASF/sam0/utils/cmsis/samd21/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ \
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/ \
+../src/ASF/sam0/utils/cmsis/samd21/source/ \
+../src/ASF/sam0/utils/cmsis/samd21/source/gcc/ \
+../src/ASF/sam0/utils/header_files/ \
+../src/ASF/sam0/utils/linker_scripts/ \
+../src/ASF/sam0/utils/linker_scripts/samd21/ \
+../src/ASF/sam0/utils/linker_scripts/samd21/gcc/ \
+../src/ASF/sam0/utils/make/ \
+../src/ASF/sam0/utils/preprocessor/ \
+../src/ASF/sam0/utils/stdio/ \
+../src/ASF/sam0/utils/stdio/stdio_serial/ \
+../src/ASF/sam0/utils/syscalls/ \
+../src/ASF/sam0/utils/syscalls/gcc/ \
+../src/ASF/thirdparty/ \
+../src/ASF/thirdparty/CMSIS/ \
+../src/ASF/thirdparty/CMSIS/Include/ \
+../src/ASF/thirdparty/CMSIS/Lib/ \
+../src/ASF/thirdparty/CMSIS/Lib/GCC/ \
+../src/config/ \
+../src/drivers
+
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS +=  \
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
+../src/ASF/sam0/drivers/dma/dma.c \
+../src/ASF/sam0/drivers/sercom/sercom.c \
+../src/ASF/sam0/utils/stdio/read.c \
+../src/ASF/sam0/utils/stdio/write.c \
+../src/drivers/padc.c \
+../src/drivers/pusart.c \
+../src/ASF/sam0/drivers/sercom/usart/usart.c \
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
+../src/ASF/common2/services/delay/sam0/systick_counter.c \
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
+../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
+../src/ASF/sam0/drivers/port/port.c \
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
+../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
+../src/ASF/sam0/drivers/system/system.c \
+../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
+../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
+../src/main.c
+
+
+PREPROCESSING_SRCS += 
+
+
+ASM_SRCS += 
+
+
+OBJS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
+src/ASF/sam0/drivers/dma/dma.o \
+src/ASF/sam0/drivers/sercom/sercom.o \
+src/ASF/sam0/utils/stdio/read.o \
+src/ASF/sam0/utils/stdio/write.o \
+src/drivers/padc.o \
+src/drivers/pusart.o \
+src/ASF/sam0/drivers/sercom/usart/usart.o \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
+src/ASF/common2/services/delay/sam0/systick_counter.o \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
+src/ASF/sam0/drivers/port/port.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
+src/ASF/sam0/drivers/system/pinmux/pinmux.o \
+src/ASF/sam0/drivers/system/system.o \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
+src/main.o
+
+OBJS_AS_ARGS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o \
+src/ASF/sam0/drivers/dma/dma.o \
+src/ASF/sam0/drivers/sercom/sercom.o \
+src/ASF/sam0/utils/stdio/read.o \
+src/ASF/sam0/utils/stdio/write.o \
+src/drivers/padc.o \
+src/drivers/pusart.o \
+src/ASF/sam0/drivers/sercom/usart/usart.o \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.o \
+src/ASF/common2/services/delay/sam0/systick_counter.o \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.o \
+src/ASF/sam0/drivers/port/port.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.o \
+src/ASF/sam0/drivers/system/pinmux/pinmux.o \
+src/ASF/sam0/drivers/system/system.o \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.o \
+src/main.o
+
+C_DEPS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
+src/ASF/sam0/drivers/dma/dma.d \
+src/ASF/sam0/drivers/sercom/sercom.d \
+src/ASF/sam0/utils/stdio/read.d \
+src/ASF/sam0/utils/stdio/write.d \
+src/drivers/padc.d \
+src/drivers/pusart.d \
+src/ASF/sam0/drivers/sercom/usart/usart.d \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
+src/ASF/common2/services/delay/sam0/systick_counter.d \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
+src/ASF/sam0/drivers/port/port.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
+src/ASF/sam0/drivers/system/pinmux/pinmux.d \
+src/ASF/sam0/drivers/system/system.d \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
+src/main.d
+
+C_DEPS_AS_ARGS +=  \
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
+src/ASF/sam0/drivers/dma/dma.d \
+src/ASF/sam0/drivers/sercom/sercom.d \
+src/ASF/sam0/utils/stdio/read.d \
+src/ASF/sam0/utils/stdio/write.d \
+src/drivers/padc.d \
+src/drivers/pusart.d \
+src/ASF/sam0/drivers/sercom/usart/usart.d \
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
+src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
+src/ASF/common2/services/delay/sam0/systick_counter.d \
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
+src/ASF/sam0/drivers/port/port.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
+src/ASF/sam0/drivers/system/pinmux/pinmux.d \
+src/ASF/sam0/drivers/system/system.d \
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
+src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
+src/main.d
+
+OUTPUT_FILE_PATH +=D21_ADC_with_DMA.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +=D21_ADC_with_DMA.elf
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+LIB_DEP+= 
+
+LINKER_SCRIPT_DEP+=  \
+../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
+
+
+# AVR32/GNU C Compiler
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/dma/dma.o: ../src/ASF/sam0/drivers/dma/dma.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/sercom.o: ../src/ASF/sam0/drivers/sercom/sercom.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/stdio/read.o: ../src/ASF/sam0/utils/stdio/read.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/stdio/write.o: ../src/ASF/sam0/utils/stdio/write.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/drivers/padc.o: ../src/drivers/padc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/drivers/pusart.o: ../src/drivers/pusart.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/usart/usart.o: ../src/ASF/sam0/drivers/sercom/usart/usart.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/sercom/sercom_interrupt.o: ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/common2/services/delay/sam0/systick_counter.o: ../src/ASF/common2/services/delay/sam0/systick_counter.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/port/port.o: ../src/ASF/sam0/drivers/port/port.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/pinmux/pinmux.o: ../src/ASF/sam0/drivers/system/pinmux/pinmux.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/drivers/system/system.o: ../src/ASF/sam0/drivers/system/system.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/ASF/sam0/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+src/main.o: ../src/main.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAMD21J18A__ -DNDEBUG -DBOARD=SAMD21_XPLAINED_PRO -D__SAMD21J18A__ -DARM_MATH_CM0PLUS=true -DSYSTICK_MODE -DADC_CALLBACK_MODE=false -DUSART_CALLBACK_MODE=true  -I"../src/ASF/common/boards" -I"../src/ASF/sam0/utils" -I"../src/ASF/sam0/utils/header_files" -I"../src/ASF/sam0/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam0/utils/cmsis/samd21/include" -I"../src/ASF/sam0/utils/cmsis/samd21/source" -I"../src/ASF/sam0/drivers/port" -I"../src/ASF/sam0/drivers/system/pinmux" -I"../src/ASF/sam0/drivers/system" -I"../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1" -I"../src/ASF/sam0/drivers/system/clock" -I"../src/ASF/sam0/drivers/system/interrupt" -I"../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21" -I"../src/ASF/sam0/drivers/system/power" -I"../src/ASF/sam0/drivers/system/power/power_sam_d_r_h" -I"../src/ASF/sam0/drivers/system/reset" -I"../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h" -I"../src/ASF/sam0/boards/samd21_xplained_pro" -I"../src/ASF/sam0/boards" -I"../src" -I"../src/config" -I"../src/ASF/sam0/utils/stdio/stdio_serial" -I"../src/ASF/common/services/serial" -I"../src/ASF/common2/services/delay" -I"../src/ASF/common2/services/delay/sam0" -I"../src/ASF/sam0/drivers/adc" -I"../src/ASF/sam0/drivers/adc/adc_sam_d_r_h" -I"../src/ASF/sam0/drivers/dma" -I"../src/ASF/sam0/drivers/sercom" -I"../src/ASF/sam0/drivers/sercom/usart" -I"../src/drivers"  -Os -fdata-sections -ffunction-sections -ffast-math -mlong-calls -Wall -mcpu=cortex-m0plus -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return  -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables 
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
+	@echo Building target: $@
+	@echo Invoking: ARM/GNU Linker : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="D21_ADC_with_DMA.map" --specs=nano.specs -Wl,--start-group -larm_cortexM0l_math -lm  -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC"  -Wl,--gc-sections -mcpu=cortex-m0plus -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld  
+	@echo Finished building target: $@
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.bin"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature  "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.hex"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.eep" || exit 0
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "D21_ADC_with_DMA.elf" > "D21_ADC_with_DMA.lss"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature  "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.srec"
 	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "D21_ADC_with_DMA.elf"
-	
-	
-
-
-
-
-
-# Other Targets
-clean:
-	-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)  
-	-$(RM) $(C_DEPS_AS_ARGS)   
+	
+	
+
+
+
+
+
+# Other Targets
+clean:
+	-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)  
+	-$(RM) $(C_DEPS_AS_ARGS)   
 	rm -rf "D21_ADC_with_DMA.elf" "D21_ADC_with_DMA.a" "D21_ADC_with_DMA.hex" "D21_ADC_with_DMA.bin" "D21_ADC_with_DMA.lss" "D21_ADC_with_DMA.eep" "D21_ADC_with_DMA.map" "D21_ADC_with_DMA.srec"
 	
\ No newline at end of file
diff --git a/D21_ADC_with_DMA/Release/gdb.txt b/D21_ADC_with_DMA/Release/gdb.txt
new file mode 100644
index 0000000..93e2cca
--- /dev/null
+++ b/D21_ADC_with_DMA/Release/gdb.txt
@@ -0,0 +1,47 @@
+0x000011d0 in _usart_interrupt_handler ()
+0x000011d0 in _usart_interrupt_handler ()
+─── Assembly ─────────────────────────────────────────────────────────
+ 0x000011d0  ? blx    r3
+ 0x000011d2  ? ldr    r3, [pc, #16]    ; (0x11e4 <_usart_interrupt_handler+264>)
+ 0x000011d4  ? blx    r3
+ 0x000011d6  ? ldr    r0, [pc, #16]    ; (0x11e8 <_usart_interrupt_handler+268>)
+ 0x000011d8  ? ldr    r3, [pc, #16]    ; (0x11ec <_usart_interrupt_handler+272>)
+ 0x000011da  ? blx    r3
+ 0x000011dc  ? b.n    0x11dc <_usart_interrupt_handler+256>
+ 0x000011de  ? nop            ; (mov r8, r8)
+ 0x000011e0  ? adds    r1, r6, r6
+ 0x000011e2  ? movs    r0, r0
+─── Breakpoints ──────────────────────────────────────────────────────
+─── Expressions ──────────────────────────────────────────────────────
+─── History ──────────────────────────────────────────────────────────
+─── Memory ───────────────────────────────────────────────────────────
+─── Registers ────────────────────────────────────────────────────────
+          r0 0x00000028         r1 0x00000000         r2 0x41004000
+          r3 0x000019b1         r4 0x00000029         r5 0x0000000c
+          r6 0x00000005         r7 0xff7ffffb         r8 0xfbbbfffd
+          r9 0x55f5ff5b        r10 0xf7fcff7f        r11 0x57b3fffd
+         r12 0x00000000         sp 0x20002398         lr 0x000001c3
+          pc 0x000011d0       xPSR 0x61000000        msp 0x20002398
+         psp 0xff0bff7c    primask 0x00          basepri 0x00      
+   faultmask 0x00          control 0x00      
+─── Source ───────────────────────────────────────────────────────────
+─── Stack ────────────────────────────────────────────────────────────
+[0] from 0x000011d0 in _usart_interrupt_handler
+[1] from 0x1c1d826c
+─── Threads ──────────────────────────────────────────────────────────
+[1] id 0 from 0x000011d0 in _usart_interrupt_handler
+─── Variables ────────────────────────────────────────────────────────
+──────────────────────────────────────────────────────────────────────
+../../../ePenguin/ePK/software/build/scripts/push.gdb:7: Error in sourced command file:
+Error erasing flash with vFlashErase packet
+Detaching from program: /storage/Shared/Documents/Projects/D21_ADC_with_DMA/D21_ADC_with_DMA/Release/D21_ADC_with_DMA.elf, Remote target
+Remote connection closed
+../../../ePenguin/ePK/software/build/scripts/push.gdb:6: Error in sourced command file:
+Remote communication error.  Target disconnected.: Connection reset by peer.
+Quit
+Quit
+Quit
+Quit
+Quit
+Quit
+Quit
diff --git a/D21_ADC_with_DMA/Release/makedep.mk b/D21_ADC_with_DMA/Release/makedep.mk
index 7b7c3e4..fa4e86c 100644
--- a/D21_ADC_with_DMA/Release/makedep.mk
+++ b/D21_ADC_with_DMA/Release/makedep.mk
@@ -1,50 +1,50 @@
-################################################################################
-# Automatically-generated file. Do not edit or delete the file
-################################################################################
-
-src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc.c
-
-src\ASF\sam0\drivers\dma\dma.c
-
-src\ASF\sam0\drivers\sercom\sercom.c
-
-src\ASF\sam0\utils\stdio\read.c
-
-src\ASF\sam0\utils\stdio\write.c
-
-src\drivers\padc.c
-
-src\drivers\pusart.c
-
-src\ASF\sam0\drivers\sercom\usart\usart.c
-
-src\ASF\sam0\drivers\sercom\usart\usart_interrupt.c
-
-src\ASF\sam0\drivers\sercom\sercom_interrupt.c
-
-src\ASF\common2\services\delay\sam0\systick_counter.c
-
-src\ASF\common\utils\interrupt\interrupt_sam_nvic.c
-
-src\ASF\sam0\boards\samd21_xplained_pro\board_init.c
-
-src\ASF\sam0\drivers\port\port.c
-
-src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c
-
-src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c
-
-src\ASF\sam0\drivers\system\interrupt\system_interrupt.c
-
-src\ASF\sam0\drivers\system\pinmux\pinmux.c
-
-src\ASF\sam0\drivers\system\system.c
-
-src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c
-
-src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c
-
-src\ASF\sam0\utils\syscalls\gcc\syscalls.c
-
-src\main.c
-
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+src\ASF\sam0\drivers\adc\adc_sam_d_r_h\adc.c
+
+src\ASF\sam0\drivers\dma\dma.c
+
+src\ASF\sam0\drivers\sercom\sercom.c
+
+src\ASF\sam0\utils\stdio\read.c
+
+src\ASF\sam0\utils\stdio\write.c
+
+src\drivers\padc.c
+
+src\drivers\pusart.c
+
+src\ASF\sam0\drivers\sercom\usart\usart.c
+
+src\ASF\sam0\drivers\sercom\usart\usart_interrupt.c
+
+src\ASF\sam0\drivers\sercom\sercom_interrupt.c
+
+src\ASF\common2\services\delay\sam0\systick_counter.c
+
+src\ASF\common\utils\interrupt\interrupt_sam_nvic.c
+
+src\ASF\sam0\boards\samd21_xplained_pro\board_init.c
+
+src\ASF\sam0\drivers\port\port.c
+
+src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\clock.c
+
+src\ASF\sam0\drivers\system\clock\clock_samd21_r21_da_ha1\gclk.c
+
+src\ASF\sam0\drivers\system\interrupt\system_interrupt.c
+
+src\ASF\sam0\drivers\system\pinmux\pinmux.c
+
+src\ASF\sam0\drivers\system\system.c
+
+src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c
+
+src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c
+
+src\ASF\sam0\utils\syscalls\gcc\syscalls.c
+
+src\main.c
+
diff --git a/D21_ADC_with_DMA/Release/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d b/D21_ADC_with_DMA/Release/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d
index c53da4c..64e3741 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d
@@ -1,341 +1,341 @@
-src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
- src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
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- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
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- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \
+ src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/common2/services/delay/sam0/systick_counter.d b/D21_ADC_with_DMA/Release/src/ASF/common2/services/delay/sam0/systick_counter.d
index 328aef8..bf07fed 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/common2/services/delay/sam0/systick_counter.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/common2/services/delay/sam0/systick_counter.d
@@ -1,353 +1,353 @@
-src/ASF/common2/services/delay/sam0/systick_counter.d \
- src/ASF/common2/services/delay/sam0/systick_counter.o: \
- ../src/ASF/common2/services/delay/sam0/systick_counter.c \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+src/ASF/common2/services/delay/sam0/systick_counter.d \
+ src/ASF/common2/services/delay/sam0/systick_counter.o: \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.c \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d
index 9542e11..32d28ed 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/boards/samd21_xplained_pro/board_init.d
@@ -1,352 +1,352 @@
-src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
- src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: \
- ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+src/ASF/sam0/boards/samd21_xplained_pro/board_init.d \
+ src/ASF/sam0/boards/samd21_xplained_pro/board_init.o: \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/board_init.c \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d
index 6caa1fe..e5538f2 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d
@@ -1,364 +1,364 @@
-src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
- src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
- ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
-
-../src/ASF/sam0/drivers/adc/adc.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.d \
+ src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.o: \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c \
+ ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/dma/dma.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/dma/dma.d
index 2b6b8cc..df0de98 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/dma/dma.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/dma/dma.d
@@ -1,365 +1,365 @@
-src/ASF/sam0/drivers/dma/dma.d src/ASF/sam0/drivers/dma/dma.o: \
- ../src/ASF/sam0/drivers/dma/dma.c \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/ASF/sam0/utils/compiler.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/config/conf_dma.h ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/ASF/sam0/utils/compiler.h:
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-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+src/ASF/sam0/drivers/dma/dma.d src/ASF/sam0/drivers/dma/dma.o: \
+ ../src/ASF/sam0/drivers/dma/dma.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/ASF/sam0/utils/compiler.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/config/conf_dma.h ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/port/port.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/port/port.d
index 73cd629..0729ad9 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/port/port.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/port/port.d
@@ -1,342 +1,342 @@
-src/ASF/sam0/drivers/port/port.d src/ASF/sam0/drivers/port/port.o: \
- ../src/ASF/sam0/drivers/port/port.c ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+src/ASF/sam0/drivers/port/port.d src/ASF/sam0/drivers/port/port.o: \
+ ../src/ASF/sam0/drivers/port/port.c ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom.d
index d4455e7..1346355 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom.d
@@ -1,369 +1,369 @@
-src/ASF/sam0/drivers/sercom/sercom.d src/ASF/sam0/drivers/sercom/sercom.o: \
- ../src/ASF/sam0/drivers/sercom/sercom.c \
- ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
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-../src/ASF/common/utils/parts.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
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-../src/ASF/common/utils/interrupt.h:
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-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
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-../src/ASF/sam0/drivers/system/system.h:
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-../src/ASF/sam0/drivers/system/clock/clock.h:
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-../src/ASF/sam0/drivers/system/clock/gclk.h:
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-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
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-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
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-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
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-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
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-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
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-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+src/ASF/sam0/drivers/sercom/sercom.d src/ASF/sam0/drivers/sercom/sercom.o: \
+ ../src/ASF/sam0/drivers/sercom/sercom.c \
+ ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom_interrupt.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom_interrupt.d
index a97be0c..0985495 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom_interrupt.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/sercom_interrupt.d
@@ -1,373 +1,373 @@
-src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
- src/ASF/sam0/drivers/sercom/sercom_interrupt.o: \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+src/ASF/sam0/drivers/sercom/sercom_interrupt.d \
+ src/ASF/sam0/drivers/sercom/sercom_interrupt.o: \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart.d
index 0d07ee9..bf5875a 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart.d
@@ -1,383 +1,383 @@
-src/ASF/sam0/drivers/sercom/usart/usart.d \
- src/ASF/sam0/drivers/sercom/usart/usart.o: \
- ../src/ASF/sam0/drivers/sercom/usart/usart.c \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
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-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+src/ASF/sam0/drivers/sercom/usart/usart.d \
+ src/ASF/sam0/drivers/sercom/usart/usart.o: \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.c \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d
index 17c9fc9..fdd3779 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d
@@ -1,383 +1,383 @@
-src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
- src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
+src/ASF/sam0/drivers/sercom/usart/usart_interrupt.d \
+ src/ASF/sam0/drivers/sercom/usart/usart_interrupt.o: \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d
index cc2a874..db4524f 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d
@@ -1,364 +1,364 @@
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
- src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
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- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/config/conf_clocks.h ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/config/conf_clocks.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h:
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.d \
+ src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.o: \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/config/conf_clocks.h ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/config/conf_clocks.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d
index cfadc8a..49655f4 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d
@@ -1,353 +1,353 @@
-src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
- src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.d \
+ src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.o: \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d
index a33accd..a240975 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/interrupt/system_interrupt.d
@@ -1,344 +1,344 @@
-src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
- src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+src/ASF/sam0/drivers/system/interrupt/system_interrupt.d \
+ src/ASF/sam0/drivers/system/interrupt/system_interrupt.o: \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.c \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/pinmux/pinmux.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/pinmux/pinmux.d
index 6ff3783..d444102 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/pinmux/pinmux.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/pinmux/pinmux.d
@@ -1,341 +1,341 @@
-src/ASF/sam0/drivers/system/pinmux/pinmux.d \
- src/ASF/sam0/drivers/system/pinmux/pinmux.o: \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
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-
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-
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-
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-
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-
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-
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-
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-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
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-
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-
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-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
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-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
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-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/sam0/drivers/system/pinmux/pinmux.d \
+ src/ASF/sam0/drivers/system/pinmux/pinmux.o: \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.c \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/system.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/system.d
index 467fb4b..136d6ea 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/system.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/drivers/system/system.d
@@ -1,357 +1,357 @@
-src/ASF/sam0/drivers/system/system.d src/ASF/sam0/drivers/system/system.o: \
- ../src/ASF/sam0/drivers/system/system.c \
- ../src/ASF/sam0/drivers/system/system.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+src/ASF/sam0/drivers/system/system.d src/ASF/sam0/drivers/system/system.o: \
+ ../src/ASF/sam0/drivers/system/system.c \
+ ../src/ASF/sam0/drivers/system/system.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d
index 2765c20..e6d9221 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d
@@ -1,219 +1,219 @@
-src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
- src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: \
- ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.d \
+ src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.o: \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d
index 1e3c64c..b19e1e5 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d
@@ -1,219 +1,219 @@
-src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
- src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.d \
+ src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.o: \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/read.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/read.d
index c941e1d..bc96833 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/read.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/read.d
@@ -1,336 +1,336 @@
-src/ASF/sam0/utils/stdio/read.d src/ASF/sam0/utils/stdio/read.o: \
- ../src/ASF/sam0/utils/stdio/read.c ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/sam0/utils/stdio/read.d src/ASF/sam0/utils/stdio/read.o: \
+ ../src/ASF/sam0/utils/stdio/read.c ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/write.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/write.d
index 4a1d644..71aea27 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/write.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/stdio/write.d
@@ -1,336 +1,336 @@
-src/ASF/sam0/utils/stdio/write.d src/ASF/sam0/utils/stdio/write.o: \
- ../src/ASF/sam0/utils/stdio/write.c ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+src/ASF/sam0/utils/stdio/write.d src/ASF/sam0/utils/stdio/write.o: \
+ ../src/ASF/sam0/utils/stdio/write.c ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
diff --git a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/syscalls/gcc/syscalls.d b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/syscalls/gcc/syscalls.d
index 2ba412a..8c1aa09 100644
--- a/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/syscalls/gcc/syscalls.d
+++ b/D21_ADC_with_DMA/Release/src/ASF/sam0/utils/syscalls/gcc/syscalls.d
@@ -1,99 +1,99 @@
-src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
- src/ASF/sam0/utils/syscalls/gcc/syscalls.o: \
- ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
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-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+src/ASF/sam0/utils/syscalls/gcc/syscalls.d \
+ src/ASF/sam0/utils/syscalls/gcc/syscalls.o: \
+ ../src/ASF/sam0/utils/syscalls/gcc/syscalls.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
diff --git a/D21_ADC_with_DMA/Release/src/drivers/padc.d b/D21_ADC_with_DMA/Release/src/drivers/padc.d
index ef93217..fe3a318 100644
--- a/D21_ADC_with_DMA/Release/src/drivers/padc.d
+++ b/D21_ADC_with_DMA/Release/src/drivers/padc.d
@@ -1,428 +1,428 @@
-src/drivers/padc.d src/drivers/padc.o: ../src/drivers/padc.c \
- ../src/drivers/padc.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
- ../src/ASF/sam0/drivers/dma/dma_crc.h \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
- ../src/ASF/common/services/serial/serial.h \
- ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
-
-../src/drivers/padc.h:
-
-../src/asf.h:
-
-../src/ASF/sam0/drivers/adc/adc.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/dma/dma_crc.h:
-
-../src/ASF/common2/services/delay/delay.h:
-
-../src/ASF/common2/services/delay/sam0/systick_counter.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
-
-../src/ASF/common/services/serial/serial.h:
-
-../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
+src/drivers/padc.d src/drivers/padc.o: ../src/drivers/padc.c \
+ ../src/drivers/padc.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
+ ../src/ASF/sam0/drivers/dma/dma_crc.h \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
+ ../src/ASF/common/services/serial/serial.h \
+ ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
+
+../src/drivers/padc.h:
+
+../src/asf.h:
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/dma/dma_crc.h:
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
+
+../src/ASF/common/services/serial/serial.h:
+
+../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
diff --git a/D21_ADC_with_DMA/Release/src/drivers/pusart.d b/D21_ADC_with_DMA/Release/src/drivers/pusart.d
index 057b94e..c8504e2 100644
--- a/D21_ADC_with_DMA/Release/src/drivers/pusart.d
+++ b/D21_ADC_with_DMA/Release/src/drivers/pusart.d
@@ -1,428 +1,428 @@
-src/drivers/pusart.d src/drivers/pusart.o: ../src/drivers/pusart.c \
- ../src/drivers/pusart.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
- ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
- ../src/ASF/sam0/drivers/dma/dma_crc.h \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
- ../src/ASF/common/services/serial/serial.h \
- ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
-
-../src/drivers/pusart.h:
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-../src/asf.h:
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-../src/ASF/sam0/drivers/adc/adc.h:
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-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
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-../src/ASF/common/utils/parts.h:
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-../src/ASF/sam0/utils/status_codes.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/tpaste.h:
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-../src/ASF/sam0/utils/preprocessor/stringz.h:
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-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
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-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
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-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
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-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
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-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
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-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
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-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/dma/dma_crc.h:
-
-../src/ASF/common2/services/delay/delay.h:
-
-../src/ASF/common2/services/delay/sam0/systick_counter.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
-
-../src/ASF/common/services/serial/serial.h:
-
-../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
+src/drivers/pusart.d src/drivers/pusart.o: ../src/drivers/pusart.c \
+ ../src/drivers/pusart.h ../src/asf.h ../src/ASF/sam0/drivers/adc/adc.h \
+ ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
+ ../src/ASF/sam0/drivers/dma/dma_crc.h \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
+ ../src/ASF/common/services/serial/serial.h \
+ ../src/ASF/common/services/serial/sam0_usart/usart_serial.h
+
+../src/drivers/pusart.h:
+
+../src/asf.h:
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/dma/dma_crc.h:
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
+
+../src/ASF/common/services/serial/serial.h:
+
+../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
diff --git a/D21_ADC_with_DMA/Release/src/main.d b/D21_ADC_with_DMA/Release/src/main.d
index 61e4018..ea51603 100644
--- a/D21_ADC_with_DMA/Release/src/main.d
+++ b/D21_ADC_with_DMA/Release/src/main.d
@@ -1,430 +1,436 @@
-src/main.d src/main.o: ../src/main.c ../src/asf.h \
- ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
- ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/tpaste.h \
- ../src/ASF/sam0/utils/preprocessor/stringz.h \
- ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
- ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
- ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
- ../src/ASF/sam0/utils/header_files/io.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
- ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
- ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
- ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
- c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
- ../src/ASF/common/utils/interrupt.h \
- ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
- ../src/ASF/sam0/drivers/system/system.h \
- ../src/ASF/sam0/drivers/system/clock/clock.h \
- ../src/ASF/sam0/drivers/system/clock/gclk.h \
- ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
- ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
- ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
- ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
- ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
- ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
- ../src/ASF/sam0/drivers/dma/dma_crc.h \
- ../src/ASF/common2/services/delay/delay.h \
- ../src/ASF/common2/services/delay/sam0/systick_counter.h \
- ../src/ASF/common/boards/board.h \
- ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
- ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
- ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
- ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
- ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/sercom.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
- ../src/ASF/sam0/drivers/sercom/usart/usart.h \
- ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
- ../src/ASF/common/services/serial/serial.h \
- ../src/ASF/common/services/serial/sam0_usart/usart_serial.h \
- ../src/drivers/pusart.h ../src/drivers/padc.h
-
-../src/asf.h:
-
-../src/ASF/sam0/drivers/adc/adc.h:
-
-../src/ASF/sam0/utils/compiler.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
-
-../src/ASF/common/utils/parts.h:
-
-../src/ASF/sam0/utils/status_codes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/tpaste.h:
-
-../src/ASF/sam0/utils/preprocessor/stringz.h:
-
-../src/ASF/sam0/utils/preprocessor/mrepeat.h:
-
-../src/ASF/sam0/utils/preprocessor/preprocessor.h:
-
-../src/ASF/sam0/utils/preprocessor/mrecursion.h:
-
-../src/ASF/sam0/utils/header_files/io.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
-
-../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
-
-../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
-
-../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
-
-c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
-
-../src/ASF/common/utils/interrupt.h:
-
-../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
-
-../src/ASF/sam0/drivers/system/system.h:
-
-../src/ASF/sam0/drivers/system/clock/clock.h:
-
-../src/ASF/sam0/drivers/system/clock/gclk.h:
-
-../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
-
-../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
-
-../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
-
-../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
-
-../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
-
-../src/ASF/sam0/drivers/dma/dma.h:
-
-../src/config/conf_dma.h:
-
-../src/ASF/sam0/drivers/dma/dma_crc.h:
-
-../src/ASF/common2/services/delay/delay.h:
-
-../src/ASF/common2/services/delay/sam0/systick_counter.h:
-
-../src/ASF/common/boards/board.h:
-
-../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
-
-../src/config/conf_board.h:
-
-../src/ASF/sam0/drivers/port/port.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
-
-../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
-
-../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/sercom.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
-
-../src/ASF/sam0/drivers/sercom/usart/usart.h:
-
-../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
-
-../src/ASF/common/services/serial/serial.h:
-
-../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
-
-../src/drivers/pusart.h:
-
-../src/drivers/padc.h:
+src/main.d src/main.o: ../src/main.c ../src/asf.h \
+ ../src/ASF/sam0/drivers/adc/adc.h ../src/ASF/sam0/utils/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ../src/ASF/common/utils/parts.h ../src/ASF/sam0/utils/status_codes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/tpaste.h \
+ ../src/ASF/sam0/utils/preprocessor/stringz.h \
+ ../src/ASF/sam0/utils/preprocessor/mrepeat.h \
+ ../src/ASF/sam0/utils/preprocessor/preprocessor.h \
+ ../src/ASF/sam0/utils/preprocessor/mrecursion.h \
+ ../src/ASF/sam0/utils/header_files/io.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h \
+ ../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \
+ ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h \
+ ../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ ../src/ASF/common/utils/interrupt.h \
+ ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \
+ ../src/ASF/sam0/drivers/system/system.h \
+ ../src/ASF/sam0/drivers/system/clock/clock.h \
+ ../src/ASF/sam0/drivers/system/clock/gclk.h \
+ ../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h \
+ ../src/ASF/sam0/drivers/system/pinmux/pinmux.h \
+ ../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h \
+ ../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h \
+ ../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h \
+ ../src/ASF/sam0/drivers/dma/dma.h ../src/config/conf_dma.h \
+ ../src/ASF/sam0/drivers/dma/dma_crc.h \
+ ../src/ASF/common2/services/delay/delay.h \
+ ../src/ASF/common2/services/delay/sam0/systick_counter.h \
+ ../src/ASF/common/boards/board.h \
+ ../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h \
+ ../src/config/conf_board.h ../src/ASF/sam0/drivers/port/port.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h \
+ ../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_pinout.h \
+ ../src/ASF/sam0/drivers/sercom/sercom_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/sercom.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h \
+ ../src/ASF/sam0/drivers/sercom/usart/usart.h \
+ ../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h \
+ ../src/ASF/common/services/serial/serial.h \
+ ../src/ASF/common/services/serial/sam0_usart/usart_serial.h \
+ ../src/drivers/pusart.h ../src/drivers/padc.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\fastmath.h
+
+../src/asf.h:
+
+../src/ASF/sam0/drivers/adc/adc.h:
+
+../src/ASF/sam0/utils/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+../src/ASF/common/utils/parts.h:
+
+../src/ASF/sam0/utils/status_codes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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+
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+
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+
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+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/tpaste.h:
+
+../src/ASF/sam0/utils/preprocessor/stringz.h:
+
+../src/ASF/sam0/utils/preprocessor/mrepeat.h:
+
+../src/ASF/sam0/utils/preprocessor/preprocessor.h:
+
+../src/ASF/sam0/utils/preprocessor/mrecursion.h:
+
+../src/ASF/sam0/utils/header_files/io.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h:
+
+../src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h:
+
+../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h:
+
+../src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+../src/ASF/common/utils/interrupt.h:
+
+../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h:
+
+../src/ASF/sam0/drivers/system/system.h:
+
+../src/ASF/sam0/drivers/system/clock/clock.h:
+
+../src/ASF/sam0/drivers/system/clock/gclk.h:
+
+../src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h:
+
+../src/ASF/sam0/drivers/system/pinmux/pinmux.h:
+
+../src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h:
+
+../src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h:
+
+../src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h:
+
+../src/ASF/sam0/drivers/dma/dma.h:
+
+../src/config/conf_dma.h:
+
+../src/ASF/sam0/drivers/dma/dma_crc.h:
+
+../src/ASF/common2/services/delay/delay.h:
+
+../src/ASF/common2/services/delay/sam0/systick_counter.h:
+
+../src/ASF/common/boards/board.h:
+
+../src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h:
+
+../src/config/conf_board.h:
+
+../src/ASF/sam0/drivers/port/port.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:
+
+../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_pinout.h:
+
+../src/ASF/sam0/drivers/sercom/sercom_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/sercom.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h:
+
+../src/ASF/sam0/drivers/sercom/usart/usart.h:
+
+../src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h:
+
+../src/ASF/common/services/serial/serial.h:
+
+../src/ASF/common/services/serial/sam0_usart/usart_serial.h:
+
+../src/drivers/pusart.h:
+
+../src/drivers/padc.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\fastmath.h:
diff --git a/D21_ADC_with_DMA/Release/src/main.o b/D21_ADC_with_DMA/Release/src/main.o
index a22fb1f..f905866 100644
Binary files a/D21_ADC_with_DMA/Release/src/main.o and b/D21_ADC_with_DMA/Release/src/main.o differ
diff --git a/D21_ADC_with_DMA/src/ASF/common/boards/board.h b/D21_ADC_with_DMA/src/ASF/common/boards/board.h
index 54680c7..20529d0 100644
--- a/D21_ADC_with_DMA/src/ASF/common/boards/board.h
+++ b/D21_ADC_with_DMA/src/ASF/common/boards/board.h
@@ -1,450 +1,450 @@
-/**
- * \file
- *
- * \brief Standard board header file.
- *
- * This file includes the appropriate board header file according to the
- * defined board (parameter BOARD).
- *
- * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/**
- * \defgroup group_common_boards Generic board support
- *
- * The generic board support module includes board-specific definitions
- * and function prototypes, such as the board initialization function.
- *
- * \{
- */
-
-#include "compiler.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*! \name Base Boards
- */
-//! @{
-#define EVK1100                     1  //!< AT32UC3A EVK1100 board.
-#define EVK1101                     2  //!< AT32UC3B EVK1101 board.
-#define UC3C_EK                     3  //!< AT32UC3C UC3C-EK board.
-#define EVK1104                     4  //!< AT32UC3A3 EVK1104 board.
-#define EVK1105                     5  //!< AT32UC3A EVK1105 board.
-#define STK600_RCUC3L0              6  //!< STK600 RCUC3L0 board.
-#define UC3L_EK                     7  //!< AT32UC3L-EK board.
-#define XPLAIN                      8  //!< ATxmega128A1 Xplain board.
-#define STK600_RC064X              10  //!< ATxmega256A3 STK600 board.
-#define STK600_RC100X              11  //!< ATxmega128A1 STK600 board.
-#define UC3_A3_XPLAINED            13  //!< ATUC3A3 UC3-A3 Xplained board.
-#define UC3_L0_XPLAINED            15  //!< ATUC3L0 UC3-L0 Xplained board.
-#define STK600_RCUC3D              16  //!< STK600 RCUC3D board.
-#define STK600_RCUC3C0             17  //!< STK600 RCUC3C board.
-#define XMEGA_B1_XPLAINED          18  //!< ATxmega128B1 Xplained board.
-#define XMEGA_A1_XPLAINED          19  //!< ATxmega128A1 Xplain-A1 board.
-#define XMEGA_A1U_XPLAINED_PRO     20  //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
-#define STK600_RCUC3L4             21  //!< ATUCL4 STK600 board.
-#define UC3_L0_XPLAINED_BC         22  //!< ATUC3L0 UC3-L0 Xplained board controller board.
-#define MEGA1284P_XPLAINED_BC      23  //!< ATmega1284P-Xplained board controller board.
-#define STK600_RC044X              24  //!< STK600 with RC044X routing card board.
-#define STK600_RCUC3B0             25  //!< STK600 RCUC3B0 board.
-#define UC3_L0_QT600               26  //!< QT600 UC3L0 MCU board.
-#define XMEGA_A3BU_XPLAINED        27  //!< ATxmega256A3BU Xplained board.
-#define STK600_RC064X_LCDX         28  //!< XMEGAB3 STK600 RC064X LCDX board.
-#define STK600_RC100X_LCDX         29  //!< XMEGAB1 STK600 RC100X LCDX board.
-#define UC3B_BOARD_CONTROLLER      30  //!< AT32UC3B1 board controller for Atmel boards.
-#define RZ600                      31  //!< AT32UC3A RZ600 MCU board.
-#define SAM3S_EK                   32  //!< SAM3S-EK board.
-#define SAM3U_EK                   33  //!< SAM3U-EK board.
-#define SAM3X_EK                   34  //!< SAM3X-EK board.
-#define SAM3N_EK                   35  //!< SAM3N-EK board.
-#define SAM3S_EK2                  36  //!< SAM3S-EK2 board.
-#define SAM4S_EK                   37  //!< SAM4S-EK board.
-#define STK600_RCUC3A0             38  //!< STK600 RCUC3A0 board.
-#define STK600_MEGA                39  //!< STK600 MEGA board.
-#define MEGA_1284P_XPLAINED        40  //!< ATmega1284P Xplained board.
-#define SAM4S_XPLAINED             41  //!< SAM4S Xplained board.
-#define ATXMEGA128A1_QT600         42  //!< QT600 ATXMEGA128A1 MCU board.
-#define ARDUINO_DUE_X              43  //!< Arduino Due/X board.
-#define STK600_RCUC3L3             44  //!< ATUCL3 STK600 board.
-#define SAM4L_EK                   45  //!< SAM4L-EK board.
-#define STK600_MEGA_RF             46  //!< STK600 MEGA RF EVK board.
-#define XMEGA_C3_XPLAINED          47  //!< ATxmega384C3 Xplained board.
-#define STK600_RC032X              48  //!< STK600 with RC032X routing card board.
-#define SAM4S_EK2                  49  //!< SAM4S-EK2 board.
-#define XMEGA_E5_XPLAINED          50  //!< ATxmega32E5 Xplained board.
-#define SAM4E_EK                   51  //!< SAM4E-EK board.
-#define ATMEGA256RFR2_XPLAINED_PRO 52  //!< ATmega256RFR2 Xplained Pro board.
-#define SAM4S_XPLAINED_PRO         53  //!< SAM4S Xplained Pro board.
-#define SAM4L_XPLAINED_PRO         54  //!< SAM4L Xplained Pro board.
-#define ATMEGA256RFR2_ZIGBIT       55  //!< ATmega256RFR2 zigbit.
-#define XMEGA_RF233_ZIGBIT         56  //!< ATxmega256A3U with AT86RF233 Zigbit.
-#define XMEGA_RF212B_ZIGBIT        57  //!< ATxmega256A3U with AT86RF212B Zigbit.
-#define SAM4S_WPIR_RD              58  //!< SAM4S-WPIR-RD board.
-#define SAMD20_XPLAINED_PRO        59  //!< SAM D20 Xplained Pro board.
-#define SAM4L8_XPLAINED_PRO        60  //!< SAM4L8 Xplained Pro board.
-#define SAM4N_XPLAINED_PRO         61  //!< SAM4N Xplained Pro board.
-#define XMEGA_A3_REB_CBB           62  //!< XMEGA REB Controller Base board.
-#define ATMEGARFX_RCB              63  //!< RFR2 & RFA1 RCB.
-#define SAM4C_EK                   64  //!< SAM4C-EK board.
-#define RCB256RFR2_XPRO            65  //!< RFR2 RCB Xplained Pro board.
-#define SAMG53_XPLAINED_PRO        66  //!< SAMG53 Xplained Pro board.
-#define SAM4CP16BMB                67  //!< SAM4CP16BMB board.
-#define SAM4E_XPLAINED_PRO         68  //!< SAM4E Xplained Pro board.
-#define SAMD21_XPLAINED_PRO        69  //!< SAM D21 Xplained Pro board.
-#define SAMR21_XPLAINED_PRO        70  //!< SAM R21 Xplained Pro board.
-#define SAM4CMP_DB                 71  //!< SAM4CMP demo board.
-#define SAM4CMS_DB                 72  //!< SAM4CMS demo board.
-#define ATPL230AMB                 73  //!< ATPL230AMB board.
-#define SAMD11_XPLAINED_PRO        74  //!< SAM D11 Xplained Pro board.
-#define SAMG55_XPLAINED_PRO        75  //!< SAMG55 Xplained Pro board.
-#define SAML21_XPLAINED_PRO        76  //!< SAM L21 Xplained Pro board.
-#define SAMD10_XPLAINED_MINI       77  //!< SAM D10 Xplained Mini board.
-#define SAMDA1_XPLAINED_PRO        78  //!< SAM DA1 Xplained Pro board.
-#define SAMW25_XPLAINED_PRO        79  //!< SAMW25 Xplained Pro board.
-#define SAMC21_XPLAINED_PRO        80  //!< SAM C21 Xplained Pro board.
-#define SAMV71_XPLAINED_ULTRA      81  //!< SAMV71 Xplained Ultra board.
-#define ATMEGA328P_XPLAINED_MINI   82  //!< ATMEGA328P Xplained MINI board.
-#define ATMEGA328PB_XPLAINED_MINI  83  //!< ATMEGA328PB Xplained MINI board.
-#define SAMB11_XPLAINED_PRO        84  //!< SAM B11 Xplained Pro board.
-#define SAME70_XPLAINED            85  //!< SAME70 Xplained board.
-#define SAML22_XPLAINED_PRO        86  //!< SAM L22 Xplained Pro board.
-#define SAML22_XPLAINED_PRO_B      87  //!< SAM L22 Xplained Pro board.
-#define SAMR21ZLL_EK               88  //!< SAMR21ZLL-EK board.
-#define ATMEGA168PB_XPLAINED_MINI  89  //!< ATMEGA168PB Xplained MINI board.
-#define ATMEGA324PB_XPLAINED_PRO   90  //!< ATMEGA324PB Xplained Pro board.
-#define SAMB11ZR_XPLAINED_PRO      92  //!< SAM B11 ZR Xplained Pro board.
-#define SAMR30_XPLAINED_PRO        93  //!< SAM R30 Xplained Pro board.
-#define SAMHA1G16A_XPLAINED_PRO    94  //!< SAM HA1G16A Xplained Pro board.
-#define SAMR34_XPLAINED_PRO        95  //!< SAM R34 Xplained Pro board.
-#define SIMULATOR_XMEGA_A1         97  //!< Simulator for XMEGA A1 devices.
-#define AVR_SIMULATOR_UC3          98  //!< Simulator for the AVR UC3 device family.
-#define USER_BOARD                 99  //!< User-reserved board (if any).
-#define DUMMY_BOARD                100 //!< Dummy board to support board-independent applications (e.g. bootloader).
-#define SAMB11ZR_SENSOR_TAG        101 //!< SAMB11ZR sensor tag board
-#define SAMR30_MODULE_XPLAINED_PRO 102 //!< SAM R30 Module Xplained Pro board.
-#define SAMR21G18_MODULE           103 //!< SAMR21G18-MR210UA Module.
-#define SAMR21B18_MODULE           104 //!< SAMR21B18-MZ210PA Module.
-//! @}
-
-/*! \name Extension Boards
- */
-//! @{
-#define EXT1102                      1  //!< AT32UC3B EXT1102 board
-#define MC300                        2  //!< AT32UC3 MC300 board
-#define SENSORS_XPLAINED_INERTIAL_1  3  //!< Xplained inertial sensor board 1
-#define SENSORS_XPLAINED_INERTIAL_2  4  //!< Xplained inertial sensor board 2
-#define SENSORS_XPLAINED_PRESSURE_1  5  //!< Xplained pressure sensor board
-#define SENSORS_XPLAINED_LIGHTPROX_1 6  //!< Xplained light & proximity sensor board
-#define SENSORS_XPLAINED_INERTIAL_A1 7  //!< Xplained inertial sensor board "A"
-#define RZ600_AT86RF231              8  //!< AT86RF231 RF board in RZ600
-#define RZ600_AT86RF230B             9  //!< AT86RF230B RF board in RZ600
-#define RZ600_AT86RF212             10  //!< AT86RF212 RF board in RZ600
-#define SENSORS_XPLAINED_BREADBOARD 11  //!< Xplained sensor development breadboard
-#define SECURITY_XPLAINED           12  //!< Xplained ATSHA204 board
-#define USER_EXT_BOARD              99  //!< User-reserved extension board (if any).
-//! @}
-
-#if BOARD == EVK1100
-#  include "evk1100/evk1100.h"
-#elif BOARD == EVK1101
-#  include "evk1101/evk1101.h"
-#elif BOARD == UC3C_EK
-#  include "uc3c_ek/uc3c_ek.h"
-#elif BOARD == EVK1104
-#  include "evk1104/evk1104.h"
-#elif BOARD == EVK1105
-#  include "evk1105/evk1105.h"
-#elif BOARD == STK600_RCUC3L0
-#  include "stk600/rcuc3l0/stk600_rcuc3l0.h"
-#elif BOARD == UC3L_EK
-#  include "uc3l_ek/uc3l_ek.h"
-#elif BOARD == STK600_RCUC3L4
-#  include "stk600/rcuc3l4/stk600_rcuc3l4.h"
-#elif BOARD == XPLAIN
-#  include "xplain/xplain.h"
-#elif BOARD == STK600_MEGA
-  /*No header-file to include*/
-#elif BOARD == STK600_MEGA_RF
-#  include "stk600.h"
-#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
-#  include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
-#elif BOARD == ATMEGA256RFR2_ZIGBIT
-#  include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
-#elif BOARD == STK600_RC032X
-#  include "stk600/rc032x/stk600_rc032x.h"
-#elif BOARD == STK600_RC044X
-#  include "stk600/rc044x/stk600_rc044x.h"
-#elif BOARD == STK600_RC064X
-#  include "stk600/rc064x/stk600_rc064x.h"
-#elif BOARD == STK600_RC100X
-#  include "stk600/rc100x/stk600_rc100x.h"
-#elif BOARD == UC3_A3_XPLAINED
-#  include "uc3_a3_xplained/uc3_a3_xplained.h"
-#elif BOARD == UC3_L0_XPLAINED
-#  include "uc3_l0_xplained/uc3_l0_xplained.h"
-#elif BOARD == STK600_RCUC3B0
-#  include "stk600/rcuc3b0/stk600_rcuc3b0.h"
-#elif BOARD == STK600_RCUC3D
-#  include "stk600/rcuc3d/stk600_rcuc3d.h"
-#elif BOARD == STK600_RCUC3C0
-#  include "stk600/rcuc3c0/stk600_rcuc3c0.h"
-#elif BOARD == SAMG53_XPLAINED_PRO
-#  include "samg53_xplained_pro/samg53_xplained_pro.h"
-#elif BOARD == SAMG55_XPLAINED_PRO
-#  include "samg55_xplained_pro/samg55_xplained_pro.h"
-#elif BOARD == XMEGA_B1_XPLAINED
-#  include "xmega_b1_xplained/xmega_b1_xplained.h"
-#elif BOARD == STK600_RC064X_LCDX
-#  include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
-#elif BOARD == STK600_RC100X_LCDX
-#  include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
-#elif BOARD == XMEGA_A1_XPLAINED
-#  include "xmega_a1_xplained/xmega_a1_xplained.h"
-#elif BOARD == XMEGA_A1U_XPLAINED_PRO
-#  include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
-#elif BOARD == UC3_L0_XPLAINED_BC
-#  include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
-#elif BOARD == SAM3S_EK
-#  include "sam3s_ek/sam3s_ek.h"
-#  include "system_sam3s.h"
-#elif BOARD == SAM3S_EK2
-#  include "sam3s_ek2/sam3s_ek2.h"
-#  include "system_sam3sd8.h"
-#elif BOARD == SAM3U_EK
-#  include "sam3u_ek/sam3u_ek.h"
-#  include "system_sam3u.h"
-#elif BOARD == SAM3X_EK
-#  include "sam3x_ek/sam3x_ek.h"
-#  include "system_sam3x.h"
-#elif BOARD == SAM3N_EK
-#  include "sam3n_ek/sam3n_ek.h"
-#  include "system_sam3n.h"
-#elif BOARD == SAM4S_EK
-#  include "sam4s_ek/sam4s_ek.h"
-#  include "system_sam4s.h"
-#elif BOARD == SAM4S_WPIR_RD
-#  include "sam4s_wpir_rd/sam4s_wpir_rd.h"
-#  include "system_sam4s.h"
-#elif BOARD == SAM4S_XPLAINED
-#  include "sam4s_xplained/sam4s_xplained.h"
-#  include "system_sam4s.h"
-#elif BOARD == SAM4S_EK2
-#  include "sam4s_ek2/sam4s_ek2.h"
-#  include "system_sam4s.h"
-#elif BOARD == MEGA_1284P_XPLAINED
-  /*No header-file to include*/
-#elif BOARD == ARDUINO_DUE_X
-#  include "arduino_due_x/arduino_due_x.h"
-#  include "system_sam3x.h"
-#elif BOARD == SAM4L_EK
-#  include "sam4l_ek/sam4l_ek.h"
-#elif BOARD == SAM4E_EK
-#  include "sam4e_ek/sam4e_ek.h"
-#elif BOARD == SAMD20_XPLAINED_PRO
-#  include "samd20_xplained_pro/samd20_xplained_pro.h"
-#elif BOARD == SAMD21_XPLAINED_PRO
-#  include "samd21_xplained_pro/samd21_xplained_pro.h"
-#elif BOARD == SAMR21_XPLAINED_PRO
-#  include "samr21_xplained_pro/samr21_xplained_pro.h"
-#elif BOARD == SAMR30_XPLAINED_PRO && defined(__SAMR30G18A__)
-#  include "samr30_xplained_pro/samr30_xplained_pro.h"
-#elif BOARD == SAMR30_MODULE_XPLAINED_PRO && defined(__SAMR30E18A__)
-#  include "samr30_module_xplained_pro/samr30_module_xplained_pro.h"
-#elif BOARD == SAMR21ZLL_EK
-#  include "samr21zll_ek/samr21zll_ek.h"
-#elif BOARD == SAMD11_XPLAINED_PRO
-#  include "samd11_xplained_pro/samd11_xplained_pro.h"
-#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
-#  include "saml21_xplained_pro/saml21_xplained_pro.h"
-#elif BOARD == SAML22_XPLAINED_PRO
-#  include "saml22_xplained_pro/saml22_xplained_pro.h"
-#elif BOARD == SAML22_XPLAINED_PRO_B
-#  include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
-#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
-#  include "saml21_xplained_pro_b/saml21_xplained_pro.h"
-#elif BOARD == SAMD10_XPLAINED_MINI
-#  include "samd10_xplained_mini/samd10_xplained_mini.h"
-#elif BOARD == SAMDA1_XPLAINED_PRO
-#  include "samda1_xplained_pro/samda1_xplained_pro.h"
-#elif BOARD == SAMHA1G16A_XPLAINED_PRO
-#  include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
-#elif BOARD == SAMC21_XPLAINED_PRO
-#  include "samc21_xplained_pro/samc21_xplained_pro.h"
-#elif BOARD == SAM4N_XPLAINED_PRO
-#  include "sam4n_xplained_pro/sam4n_xplained_pro.h"
-#elif BOARD == SAMW25_XPLAINED_PRO
-#  include "samw25_xplained_pro/samw25_xplained_pro.h"
-#elif BOARD == SAMV71_XPLAINED_ULTRA
-#  include "samv71_xplained_ultra/samv71_xplained_ultra.h"
-#elif BOARD == MEGA1284P_XPLAINED_BC
-#  include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
-#elif BOARD == UC3_L0_QT600
-#  include "uc3_l0_qt600/uc3_l0_qt600.h"
-#elif BOARD == XMEGA_A3BU_XPLAINED
-#  include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
-#elif BOARD == XMEGA_E5_XPLAINED
-#  include "xmega_e5_xplained/xmega_e5_xplained.h"
-#elif BOARD == UC3B_BOARD_CONTROLLER
-#  include "uc3b_board_controller/uc3b_board_controller.h"
-#elif BOARD == RZ600
-#  include "rz600/rz600.h"
-#elif BOARD == STK600_RCUC3A0
-#  include "stk600/rcuc3a0/stk600_rcuc3a0.h"
-#elif BOARD == ATXMEGA128A1_QT600
-#  include "atxmega128a1_qt600/atxmega128a1_qt600.h"
-#elif BOARD == STK600_RCUC3L3
-#  include "stk600/rcuc3l3/stk600_rcuc3l3.h"
-#elif BOARD == SAM4S_XPLAINED_PRO
-#  include "sam4s_xplained_pro/sam4s_xplained_pro.h"
-#elif BOARD == SAM4L_XPLAINED_PRO
-#  include "sam4l_xplained_pro/sam4l_xplained_pro.h"
-#elif BOARD == SAM4L8_XPLAINED_PRO
-#  include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
-#elif BOARD == SAM4C_EK
-#  include "sam4c_ek/sam4c_ek.h"
-#elif BOARD == SAM4CMP_DB
-#  include "sam4cmp_db/sam4cmp_db.h"
-#elif BOARD == SAM4CMS_DB
-#  include "sam4cms_db/sam4cms_db.h"
-#elif BOARD == SAM4CP16BMB
-#  include "sam4cp16bmb/sam4cp16bmb.h"
-#elif BOARD == ATPL230AMB
-#  include "atpl230amb/atpl230amb.h"
-#elif BOARD == XMEGA_C3_XPLAINED
-#  include "xmega_c3_xplained/xmega_c3_xplained.h"
-#elif BOARD == XMEGA_RF233_ZIGBIT
-#  include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
-#elif BOARD == XMEGA_A3_REB_CBB
-#  include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
-#elif BOARD == ATMEGARFX_RCB
-#  include "atmegarfx_rcb/atmegarfx_rcb.h"
-#elif BOARD == RCB256RFR2_XPRO
-#  include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
-#elif BOARD == XMEGA_RF212B_ZIGBIT
-#  include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
-#elif BOARD == SAM4E_XPLAINED_PRO
-#  include "sam4e_xplained_pro/sam4e_xplained_pro.h"
-#elif BOARD == ATMEGA328P_XPLAINED_MINI
-#  include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
-#elif BOARD == ATMEGA328PB_XPLAINED_MINI
-#  include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
-#elif BOARD == SAMB11_XPLAINED_PRO
-#  include "samb11_xplained_pro/samb11_xplained_pro.h"
-#elif BOARD == SAME70_XPLAINED
-#  include "same70_xplained/same70_xplained.h"
-#elif BOARD == ATMEGA168PB_XPLAINED_MINI
-#  include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
-#elif BOARD == ATMEGA324PB_XPLAINED_PRO
-#  include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
-#elif BOARD == SAMB11ZR_XPLAINED_PRO
-#  include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
-#elif BOARD == SIMULATOR_XMEGA_A1
-#  include "simulator/xmega_a1/simulator_xmega_a1.h"
-#elif BOARD == AVR_SIMULATOR_UC3
-#  include "avr_simulator_uc3/avr_simulator_uc3.h"
-#elif BOARD == SAMR21G18_MODULE
-# include "samr21g18_module/samr21g18_module.h"
-#elif BOARD == SAMR21B18_MODULE
-# include "samr21b18_module/samr21b18_module.h"
-#elif BOARD == SAMR34_XPLAINED_PRO && defined(__SAMR34J18B__)
-#  include "samr34_xplained_pro/samr34_xplained_pro.h"
-#elif BOARD == USER_BOARD
-// User-reserved area: #include the header file of your board here (if any).
-#  include "user_board.h"
-#elif BOARD == DUMMY_BOARD
-#  include "dummy/dummy_board.h"
-#elif BOARD == SAMB11ZR_SENSOR_TAG
-#  include "samb11zr_sensor_tag/samb11zr_sensor_tag.h"
-#else
-#  error No known Atmel board defined
-#endif
-
-#if (defined EXT_BOARD)
-#  if EXT_BOARD == MC300
-#    include "mc300/mc300.h"
-#  elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)  || \
-        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)  || \
-        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
-        (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)  || \
-        (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
-        (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
-#    include "sensors_xplained/sensors_xplained.h"
-#  elif EXT_BOARD == RZ600_AT86RF231
-#     include "at86rf231/at86rf231.h"
-#  elif EXT_BOARD == RZ600_AT86RF230B
-#    include "at86rf230b/at86rf230b.h"
-#  elif EXT_BOARD == RZ600_AT86RF212
-#    include "at86rf212/at86rf212.h"
-#  elif EXT_BOARD == SECURITY_XPLAINED
-#    include "security_xplained.h"
-#  elif EXT_BOARD == USER_EXT_BOARD
-    // User-reserved area: #include the header file of your extension board here
-    // (if any).
-#  endif
-#endif
-
-
-#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
-#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
-
-/*! \brief This function initializes the board target resources
- *
- * This function should be called to ensure proper initialization of the target
- * board hardware connected to the part.
- */
-extern void board_init(void);
-
-#endif  // #ifdef __AVR32_ABI_COMPILER__
-#else
-/*! \brief This function initializes the board target resources
- *
- * This function should be called to ensure proper initialization of the target
- * board hardware connected to the part.
- */
-extern void board_init(void);
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * \}
- */
-
-#endif  // _BOARD_H_
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100                     1  //!< AT32UC3A EVK1100 board.
+#define EVK1101                     2  //!< AT32UC3B EVK1101 board.
+#define UC3C_EK                     3  //!< AT32UC3C UC3C-EK board.
+#define EVK1104                     4  //!< AT32UC3A3 EVK1104 board.
+#define EVK1105                     5  //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0              6  //!< STK600 RCUC3L0 board.
+#define UC3L_EK                     7  //!< AT32UC3L-EK board.
+#define XPLAIN                      8  //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X              10  //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X              11  //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED            13  //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED            15  //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D              16  //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0             17  //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED          18  //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED          19  //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO     20  //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4             21  //!< ATUCL4 STK600 board.
+#define UC3_L0_XPLAINED_BC         22  //!< ATUC3L0 UC3-L0 Xplained board controller board.
+#define MEGA1284P_XPLAINED_BC      23  //!< ATmega1284P-Xplained board controller board.
+#define STK600_RC044X              24  //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0             25  //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600               26  //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED        27  //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX         28  //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX         29  //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER      30  //!< AT32UC3B1 board controller for Atmel boards.
+#define RZ600                      31  //!< AT32UC3A RZ600 MCU board.
+#define SAM3S_EK                   32  //!< SAM3S-EK board.
+#define SAM3U_EK                   33  //!< SAM3U-EK board.
+#define SAM3X_EK                   34  //!< SAM3X-EK board.
+#define SAM3N_EK                   35  //!< SAM3N-EK board.
+#define SAM3S_EK2                  36  //!< SAM3S-EK2 board.
+#define SAM4S_EK                   37  //!< SAM4S-EK board.
+#define STK600_RCUC3A0             38  //!< STK600 RCUC3A0 board.
+#define STK600_MEGA                39  //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED        40  //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED             41  //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600         42  //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X              43  //!< Arduino Due/X board.
+#define STK600_RCUC3L3             44  //!< ATUCL3 STK600 board.
+#define SAM4L_EK                   45  //!< SAM4L-EK board.
+#define STK600_MEGA_RF             46  //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED          47  //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X              48  //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2                  49  //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED          50  //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK                   51  //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52  //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO         53  //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO         54  //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT       55  //!< ATmega256RFR2 zigbit.
+#define XMEGA_RF233_ZIGBIT         56  //!< ATxmega256A3U with AT86RF233 Zigbit.
+#define XMEGA_RF212B_ZIGBIT        57  //!< ATxmega256A3U with AT86RF212B Zigbit.
+#define SAM4S_WPIR_RD              58  //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO        59  //!< SAM D20 Xplained Pro board.
+#define SAM4L8_XPLAINED_PRO        60  //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO         61  //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB           62  //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB              63  //!< RFR2 & RFA1 RCB.
+#define SAM4C_EK                   64  //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO            65  //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO        66  //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB                67  //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO         68  //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO        69  //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO        70  //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB                 71  //!< SAM4CMP demo board.
+#define SAM4CMS_DB                 72  //!< SAM4CMS demo board.
+#define ATPL230AMB                 73  //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO        74  //!< SAM D11 Xplained Pro board.
+#define SAMG55_XPLAINED_PRO        75  //!< SAMG55 Xplained Pro board.
+#define SAML21_XPLAINED_PRO        76  //!< SAM L21 Xplained Pro board.
+#define SAMD10_XPLAINED_MINI       77  //!< SAM D10 Xplained Mini board.
+#define SAMDA1_XPLAINED_PRO        78  //!< SAM DA1 Xplained Pro board.
+#define SAMW25_XPLAINED_PRO        79  //!< SAMW25 Xplained Pro board.
+#define SAMC21_XPLAINED_PRO        80  //!< SAM C21 Xplained Pro board.
+#define SAMV71_XPLAINED_ULTRA      81  //!< SAMV71 Xplained Ultra board.
+#define ATMEGA328P_XPLAINED_MINI   82  //!< ATMEGA328P Xplained MINI board.
+#define ATMEGA328PB_XPLAINED_MINI  83  //!< ATMEGA328PB Xplained MINI board.
+#define SAMB11_XPLAINED_PRO        84  //!< SAM B11 Xplained Pro board.
+#define SAME70_XPLAINED            85  //!< SAME70 Xplained board.
+#define SAML22_XPLAINED_PRO        86  //!< SAM L22 Xplained Pro board.
+#define SAML22_XPLAINED_PRO_B      87  //!< SAM L22 Xplained Pro board.
+#define SAMR21ZLL_EK               88  //!< SAMR21ZLL-EK board.
+#define ATMEGA168PB_XPLAINED_MINI  89  //!< ATMEGA168PB Xplained MINI board.
+#define ATMEGA324PB_XPLAINED_PRO   90  //!< ATMEGA324PB Xplained Pro board.
+#define SAMB11ZR_XPLAINED_PRO      92  //!< SAM B11 ZR Xplained Pro board.
+#define SAMR30_XPLAINED_PRO        93  //!< SAM R30 Xplained Pro board.
+#define SAMHA1G16A_XPLAINED_PRO    94  //!< SAM HA1G16A Xplained Pro board.
+#define SAMR34_XPLAINED_PRO        95  //!< SAM R34 Xplained Pro board.
+#define SIMULATOR_XMEGA_A1         97  //!< Simulator for XMEGA A1 devices.
+#define AVR_SIMULATOR_UC3          98  //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD                 99  //!< User-reserved board (if any).
+#define DUMMY_BOARD                100 //!< Dummy board to support board-independent applications (e.g. bootloader).
+#define SAMB11ZR_SENSOR_TAG        101 //!< SAMB11ZR sensor tag board
+#define SAMR30_MODULE_XPLAINED_PRO 102 //!< SAM R30 Module Xplained Pro board.
+#define SAMR21G18_MODULE           103 //!< SAMR21G18-MR210UA Module.
+#define SAMR21B18_MODULE           104 //!< SAMR21B18-MZ210PA Module.
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102                      1  //!< AT32UC3B EXT1102 board
+#define MC300                        2  //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1  3  //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2  4  //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1  5  //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6  //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7  //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231              8  //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B             9  //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212             10  //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11  //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED           12  //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD              99  //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+#  include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+#  include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+#  include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+#  include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+#  include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+#  include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+#  include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+#  include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+#  include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+  /*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+#  include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+#  include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+#  include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+#  include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+#  include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+#  include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+#  include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+#  include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+#  include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+#  include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+#  include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+#  include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+#  include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == SAMG55_XPLAINED_PRO
+#  include "samg55_xplained_pro/samg55_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+#  include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+#  include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+#  include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+#  include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+#  include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+#  include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+#  include "sam3s_ek/sam3s_ek.h"
+#  include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+#  include "sam3s_ek2/sam3s_ek2.h"
+#  include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+#  include "sam3u_ek/sam3u_ek.h"
+#  include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+#  include "sam3x_ek/sam3x_ek.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+#  include "sam3n_ek/sam3n_ek.h"
+#  include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+#  include "sam4s_ek/sam4s_ek.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+#  include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+#  include "sam4s_xplained/sam4s_xplained.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+#  include "sam4s_ek2/sam4s_ek2.h"
+#  include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+  /*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+#  include "arduino_due_x/arduino_due_x.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+#  include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+#  include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+#  include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+#  include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+#  include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMR30_XPLAINED_PRO && defined(__SAMR30G18A__)
+#  include "samr30_xplained_pro/samr30_xplained_pro.h"
+#elif BOARD == SAMR30_MODULE_XPLAINED_PRO && defined(__SAMR30E18A__)
+#  include "samr30_module_xplained_pro/samr30_module_xplained_pro.h"
+#elif BOARD == SAMR21ZLL_EK
+#  include "samr21zll_ek/samr21zll_ek.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+#  include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
+#  include "saml21_xplained_pro/saml21_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO
+#  include "saml22_xplained_pro/saml22_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO_B
+#  include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
+#  include "saml21_xplained_pro_b/saml21_xplained_pro.h"
+#elif BOARD == SAMD10_XPLAINED_MINI
+#  include "samd10_xplained_mini/samd10_xplained_mini.h"
+#elif BOARD == SAMDA1_XPLAINED_PRO
+#  include "samda1_xplained_pro/samda1_xplained_pro.h"
+#elif BOARD == SAMHA1G16A_XPLAINED_PRO
+#  include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
+#elif BOARD == SAMC21_XPLAINED_PRO
+#  include "samc21_xplained_pro/samc21_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+#  include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == SAMW25_XPLAINED_PRO
+#  include "samw25_xplained_pro/samw25_xplained_pro.h"
+#elif BOARD == SAMV71_XPLAINED_ULTRA
+#  include "samv71_xplained_ultra/samv71_xplained_ultra.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+#  include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+#  include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+#  include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+#  include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+#  include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+#  include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+#  include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+#  include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+#  include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+#  include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+#  include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+#  include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+#  include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+#  include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+#  include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+#  include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+#  include "atpl230amb/atpl230amb.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+#  include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+#  include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+#  include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+#  include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+#  include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+#  include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+#  include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == ATMEGA328P_XPLAINED_MINI
+#  include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
+#elif BOARD == ATMEGA328PB_XPLAINED_MINI
+#  include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
+#elif BOARD == SAMB11_XPLAINED_PRO
+#  include "samb11_xplained_pro/samb11_xplained_pro.h"
+#elif BOARD == SAME70_XPLAINED
+#  include "same70_xplained/same70_xplained.h"
+#elif BOARD == ATMEGA168PB_XPLAINED_MINI
+#  include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
+#elif BOARD == ATMEGA324PB_XPLAINED_PRO
+#  include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
+#elif BOARD == SAMB11ZR_XPLAINED_PRO
+#  include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+#  include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+#  include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == SAMR21G18_MODULE
+# include "samr21g18_module/samr21g18_module.h"
+#elif BOARD == SAMR21B18_MODULE
+# include "samr21b18_module/samr21b18_module.h"
+#elif BOARD == SAMR34_XPLAINED_PRO && defined(__SAMR34J18B__)
+#  include "samr34_xplained_pro/samr34_xplained_pro.h"
+#elif BOARD == USER_BOARD
+// User-reserved area: #include the header file of your board here (if any).
+#  include "user_board.h"
+#elif BOARD == DUMMY_BOARD
+#  include "dummy/dummy_board.h"
+#elif BOARD == SAMB11ZR_SENSOR_TAG
+#  include "samb11zr_sensor_tag/samb11zr_sensor_tag.h"
+#else
+#  error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+#  if EXT_BOARD == MC300
+#    include "mc300/mc300.h"
+#  elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#    include "sensors_xplained/sensors_xplained.h"
+#  elif EXT_BOARD == RZ600_AT86RF231
+#     include "at86rf231/at86rf231.h"
+#  elif EXT_BOARD == RZ600_AT86RF230B
+#    include "at86rf230b/at86rf230b.h"
+#  elif EXT_BOARD == RZ600_AT86RF212
+#    include "at86rf212/at86rf212.h"
+#  elif EXT_BOARD == SECURITY_XPLAINED
+#    include "security_xplained.h"
+#  elif EXT_BOARD == USER_EXT_BOARD
+    // User-reserved area: #include the header file of your extension board here
+    // (if any).
+#  endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif  // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif  // _BOARD_H_
diff --git a/D21_ADC_with_DMA/src/ASF/common/services/serial/sam0_usart/usart_serial.h b/D21_ADC_with_DMA/src/ASF/common/services/serial/sam0_usart/usart_serial.h
index aa39c68..c8c9ebb 100644
--- a/D21_ADC_with_DMA/src/ASF/common/services/serial/sam0_usart/usart_serial.h
+++ b/D21_ADC_with_DMA/src/ASF/common/services/serial/sam0_usart/usart_serial.h
@@ -1,141 +1,141 @@
-/**
- * \file
- *
- * \brief USART Serial wrapper service for the SAM D/L/C/R devices.
- *
- * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef _USART_SERIAL_H_
-#define _USART_SERIAL_H_
-
-#include "compiler.h"
-#include "status_codes.h"
-#include "usart.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \name Serial Management Configuration */
-
-typedef Sercom * usart_inst_t;
-
-//struct usart_module usart;
-
-/*! \brief Initializes the Usart in serial mode.
- *
- * \param[in,out] module  Software instance of the USART to initialize.
- * \param[in]     hw      Base address of the hardware USART.
- * \param[in]     config  Configuration settings for the USART.
- *
- * \retval true if the initialization was successful
- * \retval false if initialization failed (error in baud rate calculation)
- */
-static inline bool usart_serial_init(
-		struct usart_module *const module,
-		usart_inst_t const hw,
-		const struct usart_config *const config)
-{
-	if (usart_init(module, hw, config) == STATUS_OK) {
-		return true;
-	}
-	else {
-		return false;
-	}
-}
-
-/** \brief Sends a character with the USART.
- *
- * \param[in,out] module  Software instance of the USART.
- * \param[in]     c       Character to write.
- *
- * \return Status code
- */
-static inline enum status_code usart_serial_putchar(
-		struct usart_module *const module,
-		uint8_t c)
-{
-	while(STATUS_OK !=usart_write_wait(module, c));
-
-	return STATUS_OK;
-}
-
-/** \brief Waits until a character is received, and returns it.
- *
- * \param[in,out] module  Software instance of the USART.
- * \param[out]    c       Destination for the read character.
- */
-static inline void usart_serial_getchar(
-		struct usart_module *const module,
-		uint8_t *c)
-{
-	uint16_t temp = 0;
-
-	while(STATUS_OK != usart_read_wait(module, &temp));
-
-	*c = temp;
-}
-
-/**
- * \brief Send a sequence of bytes to USART device
- *
- * \param[in,out] module   Software instance of the USART.
- * \param[in]     tx_data  Data buffer to read the data to write from.
- * \param[in]     length   Length of data to write.
- */
-static inline enum status_code usart_serial_write_packet(
-		struct usart_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length)
-{
-	return usart_write_buffer_wait(module, tx_data, length);
-}
-
-/**
- * \brief Receive a sequence of bytes from USART device
- *
- * \param[in,out] module   Software instance of the USART.
- * \param[out]    rx_data  Data buffer to store the read data into.
- * \param[in]     length   Length of data to read.
- */
-static inline enum status_code usart_serial_read_packet(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
-{
-	return usart_read_buffer_wait(module, rx_data, length);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  // _USART_SERIAL_H_
+/**
+ * \file
+ *
+ * \brief USART Serial wrapper service for the SAM D/L/C/R devices.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef _USART_SERIAL_H_
+#define _USART_SERIAL_H_
+
+#include "compiler.h"
+#include "status_codes.h"
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \name Serial Management Configuration */
+
+typedef Sercom * usart_inst_t;
+
+//struct usart_module usart;
+
+/*! \brief Initializes the Usart in serial mode.
+ *
+ * \param[in,out] module  Software instance of the USART to initialize.
+ * \param[in]     hw      Base address of the hardware USART.
+ * \param[in]     config  Configuration settings for the USART.
+ *
+ * \retval true if the initialization was successful
+ * \retval false if initialization failed (error in baud rate calculation)
+ */
+static inline bool usart_serial_init(
+		struct usart_module *const module,
+		usart_inst_t const hw,
+		const struct usart_config *const config)
+{
+	if (usart_init(module, hw, config) == STATUS_OK) {
+		return true;
+	}
+	else {
+		return false;
+	}
+}
+
+/** \brief Sends a character with the USART.
+ *
+ * \param[in,out] module  Software instance of the USART.
+ * \param[in]     c       Character to write.
+ *
+ * \return Status code
+ */
+static inline enum status_code usart_serial_putchar(
+		struct usart_module *const module,
+		uint8_t c)
+{
+	while(STATUS_OK !=usart_write_wait(module, c));
+
+	return STATUS_OK;
+}
+
+/** \brief Waits until a character is received, and returns it.
+ *
+ * \param[in,out] module  Software instance of the USART.
+ * \param[out]    c       Destination for the read character.
+ */
+static inline void usart_serial_getchar(
+		struct usart_module *const module,
+		uint8_t *c)
+{
+	uint16_t temp = 0;
+
+	while(STATUS_OK != usart_read_wait(module, &temp));
+
+	*c = temp;
+}
+
+/**
+ * \brief Send a sequence of bytes to USART device
+ *
+ * \param[in,out] module   Software instance of the USART.
+ * \param[in]     tx_data  Data buffer to read the data to write from.
+ * \param[in]     length   Length of data to write.
+ */
+static inline enum status_code usart_serial_write_packet(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	return usart_write_buffer_wait(module, tx_data, length);
+}
+
+/**
+ * \brief Receive a sequence of bytes from USART device
+ *
+ * \param[in,out] module   Software instance of the USART.
+ * \param[out]    rx_data  Data buffer to store the read data into.
+ * \param[in]     length   Length of data to read.
+ */
+static inline enum status_code usart_serial_read_packet(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	return usart_read_buffer_wait(module, rx_data, length);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _USART_SERIAL_H_
diff --git a/D21_ADC_with_DMA/src/ASF/common/services/serial/serial.h b/D21_ADC_with_DMA/src/ASF/common/services/serial/serial.h
index 21bb155..425d4eb 100644
--- a/D21_ADC_with_DMA/src/ASF/common/services/serial/serial.h
+++ b/D21_ADC_with_DMA/src/ASF/common/services/serial/serial.h
@@ -1,269 +1,269 @@
-/**
- * \file
- *
- * \brief Serial Mode management
- *
- * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SERIAL_H_INCLUDED
-#define SERIAL_H_INCLUDED
-
-#include <parts.h>
-#include "status_codes.h"
-
-/**
- * \typedef usart_if
- *
- * This type can be used independently to refer to USART module for the
- * architecture used. It refers to the correct type definition for the
- * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.
- */
-
-#if XMEGA
-# include "xmega_usart/usart_serial.h"
-#elif MEGA_RF
-# include "megarf_usart/usart_serial.h"
-#elif UC3
-# include "uc3_usart/usart_serial.h"
-#elif (SAMB)
-#include "samb_uart/uart_serial.h"
-#elif (SAM0)
-#include "sam0_usart/usart_serial.h"
-#elif SAM
-# include "sam_uart/uart_serial.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- *
- * \defgroup serial_group Serial Interface (Serial)
- *
- * See \ref serial_quickstart.
- *
- * This is the common API for serial interface. Additional features are available
- * in the documentation of the specific modules.
- *
- * \section serial_group_platform Platform Dependencies
- *
- * The serial API is partially chip- or platform-specific. While all
- * platforms provide mostly the same functionality, there are some
- * variations around how different bus types and clock tree structures
- * are handled.
- *
- * The following functions are available on all platforms, but there may
- * be variations in the function signature (i.e. parameters) and
- * behaviour. These functions are typically called by platform-specific
- * parts of drivers, and applications that aren't intended to be
- * portable:
- *   - usart_serial_init()
- *   - usart_serial_putchar()
- *   - usart_serial_getchar()
- *   - usart_serial_write_packet()
- *   - usart_serial_read_packet()
- *
- *
- * @{
- */
- 
-//! @}
-
-/**
- * \page serial_quickstart Quick start guide for Serial Interface service
- *
- * This is the quick start guide for the \ref serial_group "Serial Interface module", with
- * step-by-step instructions on how to configure and use the serial in a
- * selection of use cases.
- *
- * The use cases contain several code fragments. The code fragments in the
- * steps for setup can be copied into a custom initialization function, while
- * the steps for usage can be copied into, e.g., the main application function.
- *
- * \section serial_use_cases Serial use cases
- * - \ref serial_basic_use_case
- * - \subpage serial_use_case_1
- *
- * \section serial_basic_use_case Basic use case - transmit a character
- * In this use case, the serial module is configured for:
- * - Using USARTD0
- * - Baudrate: 9600
- * - Character length: 8 bit
- * - Parity mode: Disabled
- * - Stop bit: None
- * - RS232 mode
- *
- * The use case waits for a received character on the configured USART and
- * echoes the character back to the same USART.
- *
- * \section serial_basic_use_case_setup Setup steps
- *
- * \subsection serial_basic_use_case_setup_prereq Prerequisites
- * -# \ref sysclk_group "System Clock Management (sysclk)"
- *
- * \subsection serial_basic_use_case_setup_code Example code
- * The following configuration must be added to the project (typically to a 
- * conf_uart_serial.h file, but it can also be added to your main application file.)
- *
- * \note The following takes SAM3X configuration for example, other devices have similar
- * configuration, but their parameters may be different, refer to corresponding header files.
- *
- * \code
-	#define USART_SERIAL                     &USARTD0
-	#define USART_SERIAL_BAUDRATE            9600
-	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
-	#define USART_SERIAL_PARITY              US_MR_PAR_NO
-	#define USART_SERIAL_STOP_BIT            false
-\endcode
- *
- * A variable for the received byte must be added:
- * \code uint8_t received_byte; \endcode
- *
- * Add to application initialization:
- * \code
-	    sysclk_init();
-
-	    static usart_serial_options_t usart_options = {
-	       .baudrate = USART_SERIAL_BAUDRATE,
-	       .charlength = USART_SERIAL_CHAR_LENGTH,
-	       .paritytype = USART_SERIAL_PARITY,
-	       .stopbits = USART_SERIAL_STOP_BIT
-	    };
-
-	    usart_serial_init(USART_SERIAL, &usart_options);
-\endcode
- *
- * \subsection serial_basic_use_case_setup_flow Workflow
- * -# Initialize system clock:
- *   - \code sysclk_init(); \endcode
- * -# Create serial USART options struct:
- *   - \code
-	static usart_serial_options_t usart_options = {
-	   .baudrate = USART_SERIAL_BAUDRATE,
-	   .charlength = USART_SERIAL_CHAR_LENGTH,
-	   .paritytype = USART_SERIAL_PARITY,
-	   .stopbits = USART_SERIAL_STOP_BIT
-	};
-\endcode
- * -# Initialize the serial service:
- *   - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
- *
- * \section serial_basic_use_case_usage Usage steps
- *
- * \subsection serial_basic_use_case_usage_code Example code
- * Add to application C-file:
- * \code
-	usart_serial_getchar(USART_SERIAL, &received_byte);
-	usart_serial_putchar(USART_SERIAL, received_byte);
-\endcode
- *
- * \subsection serial_basic_use_case_usage_flow Workflow
- * -# Wait for reception of a character:
- *   - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode
- * -# Echo the character back:
- *   - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode
- */
-
-/**
- * \page serial_use_case_1 Advanced use case - Send a packet of serial data
- *
- * In this use case, the USART module is configured for:
- * - Using USARTD0
- * - Baudrate: 9600
- * - Character length: 8 bit
- * - Parity mode: Disabled
- * - Stop bit: None
- * - RS232 mode
- *
- * The use case sends a string of text through the USART.
- *
- * \section serial_use_case_1_setup Setup steps
- *
- * \subsection serial_use_case_1_setup_prereq Prerequisites
- * -# \ref sysclk_group "System Clock Management (sysclk)"
- *
- * \subsection serial_use_case_1_setup_code Example code
- * The following configuration must be added to the project (typically to a 
- * conf_uart_serial.h file, but it can also be added to your main application file.):
- *
- * \note The following takes SAM3X configuration for example, other devices have similar
- * configuration, but their parameters may be different, refer to corresponding header files.
- *
- * \code
-	#define USART_SERIAL                     &USARTD0
-	#define USART_SERIAL_BAUDRATE            9600
-	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
-	#define USART_SERIAL_PARITY              US_MR_PAR_NO
-	#define USART_SERIAL_STOP_BIT            false
-\endcode
- *
- * Add to application initialization:
- * \code
-	    sysclk_init();
-
-	    static usart_serial_options_t usart_options = {
-	       .baudrate = USART_SERIAL_BAUDRATE,
-	       .charlength = USART_SERIAL_CHAR_LENGTH,
-	       .paritytype = USART_SERIAL_PARITY,
-	       .stopbits = USART_SERIAL_STOP_BIT
-	    };
-
-	    usart_serial_init(USART_SERIAL, &usart_options);
-\endcode
- *
- * \subsection serial_use_case_1_setup_flow Workflow
- * -# Initialize system clock:
- *   - \code sysclk_init(); \endcode
- * -# Create USART options struct:
- *   - \code
-	static usart_serial_options_t usart_options = {
-	   .baudrate = USART_SERIAL_BAUDRATE,
-	   .charlength = USART_SERIAL_CHAR_LENGTH,
-	   .paritytype = USART_SERIAL_PARITY,
-	   .stopbits = USART_SERIAL_STOP_BIT
-	};
-\endcode
- * -# Initialize in RS232 mode:
- *   - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
- *
- * \section serial_use_case_1_usage Usage steps
- *
- * \subsection serial_use_case_1_usage_code Example code
- * Add to, e.g., main loop in application C-file:
- * \code
-	usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
-\endcode
- *
- * \subsection serial_use_case_1_usage_flow Workflow
- * -# Write a string of text to the USART:
- *   - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode
- */
-
-#endif /* SERIAL_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief Serial Mode management
+ *
+ * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SERIAL_H_INCLUDED
+#define SERIAL_H_INCLUDED
+
+#include <parts.h>
+#include "status_codes.h"
+
+/**
+ * \typedef usart_if
+ *
+ * This type can be used independently to refer to USART module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.
+ */
+
+#if XMEGA
+# include "xmega_usart/usart_serial.h"
+#elif MEGA_RF
+# include "megarf_usart/usart_serial.h"
+#elif UC3
+# include "uc3_usart/usart_serial.h"
+#elif (SAMB)
+#include "samb_uart/uart_serial.h"
+#elif (SAM0)
+#include "sam0_usart/usart_serial.h"
+#elif SAM
+# include "sam_uart/uart_serial.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup serial_group Serial Interface (Serial)
+ *
+ * See \ref serial_quickstart.
+ *
+ * This is the common API for serial interface. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section serial_group_platform Platform Dependencies
+ *
+ * The serial API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - usart_serial_init()
+ *   - usart_serial_putchar()
+ *   - usart_serial_getchar()
+ *   - usart_serial_write_packet()
+ *   - usart_serial_read_packet()
+ *
+ *
+ * @{
+ */
+ 
+//! @}
+
+/**
+ * \page serial_quickstart Quick start guide for Serial Interface service
+ *
+ * This is the quick start guide for the \ref serial_group "Serial Interface module", with
+ * step-by-step instructions on how to configure and use the serial in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section serial_use_cases Serial use cases
+ * - \ref serial_basic_use_case
+ * - \subpage serial_use_case_1
+ *
+ * \section serial_basic_use_case Basic use case - transmit a character
+ * In this use case, the serial module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case waits for a received character on the configured USART and
+ * echoes the character back to the same USART.
+ *
+ * \section serial_basic_use_case_setup Setup steps
+ *
+ * \subsection serial_basic_use_case_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_basic_use_case_setup_code Example code
+ * The following configuration must be added to the project (typically to a 
+ * conf_uart_serial.h file, but it can also be added to your main application file.)
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+	#define USART_SERIAL                     &USARTD0
+	#define USART_SERIAL_BAUDRATE            9600
+	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+	#define USART_SERIAL_PARITY              US_MR_PAR_NO
+	#define USART_SERIAL_STOP_BIT            false
+\endcode
+ *
+ * A variable for the received byte must be added:
+ * \code uint8_t received_byte; \endcode
+ *
+ * Add to application initialization:
+ * \code
+	    sysclk_init();
+
+	    static usart_serial_options_t usart_options = {
+	       .baudrate = USART_SERIAL_BAUDRATE,
+	       .charlength = USART_SERIAL_CHAR_LENGTH,
+	       .paritytype = USART_SERIAL_PARITY,
+	       .stopbits = USART_SERIAL_STOP_BIT
+	    };
+
+	    usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_basic_use_case_setup_flow Workflow
+ * -# Initialize system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Create serial USART options struct:
+ *   - \code
+	static usart_serial_options_t usart_options = {
+	   .baudrate = USART_SERIAL_BAUDRATE,
+	   .charlength = USART_SERIAL_CHAR_LENGTH,
+	   .paritytype = USART_SERIAL_PARITY,
+	   .stopbits = USART_SERIAL_STOP_BIT
+	};
+\endcode
+ * -# Initialize the serial service:
+ *   - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
+ *
+ * \section serial_basic_use_case_usage Usage steps
+ *
+ * \subsection serial_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+	usart_serial_getchar(USART_SERIAL, &received_byte);
+	usart_serial_putchar(USART_SERIAL, received_byte);
+\endcode
+ *
+ * \subsection serial_basic_use_case_usage_flow Workflow
+ * -# Wait for reception of a character:
+ *   - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode
+ * -# Echo the character back:
+ *   - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode
+ */
+
+/**
+ * \page serial_use_case_1 Advanced use case - Send a packet of serial data
+ *
+ * In this use case, the USART module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case sends a string of text through the USART.
+ *
+ * \section serial_use_case_1_setup Setup steps
+ *
+ * \subsection serial_use_case_1_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_use_case_1_setup_code Example code
+ * The following configuration must be added to the project (typically to a 
+ * conf_uart_serial.h file, but it can also be added to your main application file.):
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+	#define USART_SERIAL                     &USARTD0
+	#define USART_SERIAL_BAUDRATE            9600
+	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+	#define USART_SERIAL_PARITY              US_MR_PAR_NO
+	#define USART_SERIAL_STOP_BIT            false
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+	    sysclk_init();
+
+	    static usart_serial_options_t usart_options = {
+	       .baudrate = USART_SERIAL_BAUDRATE,
+	       .charlength = USART_SERIAL_CHAR_LENGTH,
+	       .paritytype = USART_SERIAL_PARITY,
+	       .stopbits = USART_SERIAL_STOP_BIT
+	    };
+
+	    usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_use_case_1_setup_flow Workflow
+ * -# Initialize system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Create USART options struct:
+ *   - \code
+	static usart_serial_options_t usart_options = {
+	   .baudrate = USART_SERIAL_BAUDRATE,
+	   .charlength = USART_SERIAL_CHAR_LENGTH,
+	   .paritytype = USART_SERIAL_PARITY,
+	   .stopbits = USART_SERIAL_STOP_BIT
+	};
+\endcode
+ * -# Initialize in RS232 mode:
+ *   - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
+ *
+ * \section serial_use_case_1_usage Usage steps
+ *
+ * \subsection serial_use_case_1_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+	usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
+\endcode
+ *
+ * \subsection serial_use_case_1_usage_flow Workflow
+ * -# Write a string of text to the USART:
+ *   - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode
+ */
+
+#endif /* SERIAL_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/common/utils/interrupt.h b/D21_ADC_with_DMA/src/ASF/common/utils/interrupt.h
index 450d0f9..e5154a6 100644
--- a/D21_ADC_with_DMA/src/ASF/common/utils/interrupt.h
+++ b/D21_ADC_with_DMA/src/ASF/common/utils/interrupt.h
@@ -1,132 +1,132 @@
-/**
- * \file
- *
- * \brief Global interrupt management for 8- and 32-bit AVR
- *
- * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef UTILS_INTERRUPT_H
-#define UTILS_INTERRUPT_H
-
-#include <parts.h>
-
-#if XMEGA || MEGA
-#  include "interrupt/interrupt_avr8.h"
-#elif UC3
-#  include "interrupt/interrupt_avr32.h"
-#elif SAM || SAMB
-#  include "interrupt/interrupt_sam_nvic.h"
-#else
-#  error Unsupported device.
-#endif
-
-/**
- * \defgroup interrupt_group Global interrupt management
- *
- * This is a driver for global enabling and disabling of interrupts.
- *
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * \def CONFIG_INTERRUPT_FORCE_INTC
- * \brief Force usage of the ASF INTC driver
- *
- * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
- * This is useful to ensure compatibility across compilers and shall be used only when required
- * by the application needs.
- */
-#  define CONFIG_INTERRUPT_FORCE_INTC
-#endif
-
-//! \name Global interrupt flags
-//@{
-/**
- * \typedef irqflags_t
- * \brief Type used for holding state of interrupt flag
- */
-
-/**
- * \def cpu_irq_enable
- * \brief Enable interrupts globally
- */
-
-/**
- * \def cpu_irq_disable
- * \brief Disable interrupts globally
- */
-
-/**
- * \fn irqflags_t cpu_irq_save(void)
- * \brief Get and clear the global interrupt flags
- *
- * Use in conjunction with \ref cpu_irq_restore.
- *
- * \return Current state of interrupt flags.
- *
- * \note This function leaves interrupts disabled.
- */
-
-/**
- * \fn void cpu_irq_restore(irqflags_t flags)
- * \brief Restore global interrupt flags
- *
- * Use in conjunction with \ref cpu_irq_save.
- *
- * \param flags State to set interrupt flag to.
- */
-
-/**
- * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
- * \brief Check if interrupts are globally enabled in supplied flags
- *
- * \param flags Currents state of interrupt flags.
- *
- * \return True if interrupts are enabled.
- */
-
-/**
- * \def cpu_irq_is_enabled
- * \brief Check if interrupts are globally enabled
- *
- * \return True if interrupts are enabled.
- */
-//@}
-
-//! @}
-
-/**
- * \ingroup interrupt_group
- * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
- */
-
-#endif /* UTILS_INTERRUPT_H */
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA
+#  include "interrupt/interrupt_avr8.h"
+#elif UC3
+#  include "interrupt/interrupt_avr32.h"
+#elif SAM || SAMB
+#  include "interrupt/interrupt_sam_nvic.h"
+#else
+#  error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+#  define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */
diff --git a/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
index 269b4ce..534f541 100644
--- a/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
+++ b/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
@@ -1,76 +1,76 @@
-/**
- * \file
- *
- * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "interrupt_sam_nvic.h"
-
-#if !defined(__DOXYGEN__)
-/* Deprecated - global flag to determine the global interrupt state. Required by
- * QTouch library, however new applications should use cpu_irq_is_enabled()
- * which probes the true global interrupt state from the CPU special registers.
- */
-volatile bool g_interrupt_enabled = true;
-#endif
-
-void cpu_irq_enter_critical(void)
-{
-	if (cpu_irq_critical_section_counter == 0) {
-		if (cpu_irq_is_enabled()) {
-			cpu_irq_disable();
-			cpu_irq_prev_interrupt_state = true;
-		} else {
-			/* Make sure the to save the prev state as false */
-			cpu_irq_prev_interrupt_state = false;
-		}
-
-	}
-
-	cpu_irq_critical_section_counter++;
-}
-
-void cpu_irq_leave_critical(void)
-{
-	/* Check if the user is trying to leave a critical section when not in a critical section */
-	Assert(cpu_irq_critical_section_counter > 0);
-
-	cpu_irq_critical_section_counter--;
-
-	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
-	   was enabled when entering critical state */
-	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
-		cpu_irq_enable();
-	}
-}
-
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+	if (cpu_irq_critical_section_counter == 0) {
+		if (cpu_irq_is_enabled()) {
+			cpu_irq_disable();
+			cpu_irq_prev_interrupt_state = true;
+		} else {
+			/* Make sure the to save the prev state as false */
+			cpu_irq_prev_interrupt_state = false;
+		}
+
+	}
+
+	cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+	/* Check if the user is trying to leave a critical section when not in a critical section */
+	Assert(cpu_irq_critical_section_counter > 0);
+
+	cpu_irq_critical_section_counter--;
+
+	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+	   was enabled when entering critical state */
+	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+		cpu_irq_enable();
+	}
+}
+
diff --git a/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
index 7d215cf..d7b3193 100644
--- a/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+++ b/D21_ADC_with_DMA/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
@@ -1,179 +1,179 @@
-/**
- * \file
- *
- * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef UTILS_INTERRUPT_INTERRUPT_H
-#define UTILS_INTERRUPT_INTERRUPT_H
-
-#include <compiler.h>
-#include <parts.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \weakgroup interrupt_group
- *
- * @{
- */
-
-/**
- * \name Interrupt Service Routine definition
- *
- * @{
- */
-
-/**
- * \brief Define service routine
- *
- * \note For NVIC devices the interrupt service routines are predefined to
- *       add to vector table in binary generation, so there is no service
- *       register at run time. The routine collections are in exceptions.h.
- *
- * Usage:
- * \code
-	ISR(foo_irq_handler)
-	{
-	     // Function definition
-	     ...
-	}
-\endcode
- *
- * \param func Name for the function.
- */
-#  define ISR(func)   \
-	void func (void)
-
-/**
- * \brief Initialize interrupt vectors
- *
- * For NVIC the interrupt vectors are put in vector table. So nothing
- * to do to initialize them, except defined the vector function with
- * right name.
- *
- * This must be called prior to \ref irq_register_handler.
- */
-#  define irq_initialize_vectors()   \
-	do {                             \
-	} while(0)
-
-/**
- * \brief Register handler for interrupt
- *
- * For NVIC the interrupt vectors are put in vector table. So nothing
- * to do to register them, except defined the vector function with
- * right name.
- *
- * Usage:
- * \code
-	irq_initialize_vectors();
-	irq_register_handler(foo_irq_handler);
-\endcode
- *
- * \note The function \a func must be defined with the \ref ISR macro.
- * \note The functions prototypes can be found in the device exception header
- *       files (exceptions.h).
- */
-#  define irq_register_handler(int_num, int_prio)                      \
-	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
-	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
-	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
-
-//@}
-
-#  define cpu_irq_enable()                     \
-	do {                                       \
-		g_interrupt_enabled = true;            \
-		__DMB();                               \
-		__enable_irq();                        \
-	} while (0)
-#  define cpu_irq_disable()                    \
-	do {                                       \
-		__disable_irq();                       \
-		__DMB();                               \
-		g_interrupt_enabled = false;           \
-	} while (0)
-
-typedef uint32_t irqflags_t;
-
-#if !defined(__DOXYGEN__)
-extern volatile bool g_interrupt_enabled;
-#endif
-
-#define cpu_irq_is_enabled()    (__get_PRIMASK() == 0)
-
-static volatile uint32_t cpu_irq_critical_section_counter;
-static volatile bool     cpu_irq_prev_interrupt_state;
-
-static inline irqflags_t cpu_irq_save(void)
-{
-	volatile irqflags_t flags = cpu_irq_is_enabled();
-	cpu_irq_disable();
-	return flags;
-}
-
-static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
-{
-	return (flags);
-}
-
-static inline void cpu_irq_restore(irqflags_t flags)
-{
-	if (cpu_irq_is_enabled_flags(flags))
-		cpu_irq_enable();
-}
-
-void cpu_irq_enter_critical(void);
-void cpu_irq_leave_critical(void);
-
-/**
- * \weakgroup interrupt_deprecated_group
- * @{
- */
-
-#define Enable_global_interrupt()            cpu_irq_enable()
-#define Disable_global_interrupt()           cpu_irq_disable()
-#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
-
-//@}
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* UTILS_INTERRUPT_INTERRUPT_H */
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ *       add to vector table in binary generation, so there is no service
+ *       register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+	ISR(foo_irq_handler)
+	{
+	     // Function definition
+	     ...
+	}
+\endcode
+ *
+ * \param func Name for the function.
+ */
+#  define ISR(func)   \
+	void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()   \
+	do {                             \
+	} while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+	irq_initialize_vectors();
+	irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ *       files (exceptions.h).
+ */
+#  define irq_register_handler(int_num, int_prio)                      \
+	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
+	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
+	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
+
+//@}
+
+#  define cpu_irq_enable()                     \
+	do {                                       \
+		g_interrupt_enabled = true;            \
+		__DMB();                               \
+		__enable_irq();                        \
+	} while (0)
+#  define cpu_irq_disable()                    \
+	do {                                       \
+		__disable_irq();                       \
+		__DMB();                               \
+		g_interrupt_enabled = false;           \
+	} while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled()    (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool     cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags = cpu_irq_is_enabled();
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	if (cpu_irq_is_enabled_flags(flags))
+		cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/D21_ADC_with_DMA/src/ASF/common/utils/parts.h b/D21_ADC_with_DMA/src/ASF/common/utils/parts.h
index 1c147bf..bcf7c7d 100644
--- a/D21_ADC_with_DMA/src/ASF/common/utils/parts.h
+++ b/D21_ADC_with_DMA/src/ASF/common/utils/parts.h
@@ -1,1754 +1,1754 @@
-/**
- * \file
- *
- * \brief Atmel part identification macros
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef ATMEL_PARTS_H
-#define ATMEL_PARTS_H
-
-/**
- * \defgroup part_macros_group Atmel part identification macros
- *
- * This collection of macros identify which series and families that the various
- * Atmel parts belong to. These can be used to select part-dependent sections of
- * code at compile time.
- *
- * @{
- */
-
-/**
- * \name Convenience macros for part checking
- * @{
- */
-/* ! Check GCC and IAR part definition for 8-bit AVR */
-#define AVR8_PART_IS_DEFINED(part) \
-	(defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
-
-/* ! Check GCC and IAR part definition for 32-bit AVR */
-#define AVR32_PART_IS_DEFINED(part) \
-	(defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
-
-/* ! Check GCC and IAR part definition for SAM */
-#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
-/** @} */
-
-/**
- * \defgroup uc3_part_macros_group AVR UC3 parts
- * @{
- */
-
-/**
- * \name AVR UC3 A series
- * @{
- */
-#define UC3A0 (	\
-		AVR32_PART_IS_DEFINED(UC3A0128) || \
-		AVR32_PART_IS_DEFINED(UC3A0256) || \
-		AVR32_PART_IS_DEFINED(UC3A0512)	\
-		)
-
-#define UC3A1 (	\
-		AVR32_PART_IS_DEFINED(UC3A1128) || \
-		AVR32_PART_IS_DEFINED(UC3A1256) || \
-		AVR32_PART_IS_DEFINED(UC3A1512)	\
-		)
-
-#define UC3A3 (	\
-		AVR32_PART_IS_DEFINED(UC3A364)   || \
-		AVR32_PART_IS_DEFINED(UC3A364S)  || \
-		AVR32_PART_IS_DEFINED(UC3A3128)  || \
-		AVR32_PART_IS_DEFINED(UC3A3128S) || \
-		AVR32_PART_IS_DEFINED(UC3A3256)  || \
-		AVR32_PART_IS_DEFINED(UC3A3256S) \
-		)
-
-#define UC3A4 (	\
-		AVR32_PART_IS_DEFINED(UC3A464)   || \
-		AVR32_PART_IS_DEFINED(UC3A464S)  || \
-		AVR32_PART_IS_DEFINED(UC3A4128)  || \
-		AVR32_PART_IS_DEFINED(UC3A4128S) || \
-		AVR32_PART_IS_DEFINED(UC3A4256)  || \
-		AVR32_PART_IS_DEFINED(UC3A4256S) \
-		)
-/** @} */
-
-/**
- * \name AVR UC3 B series
- * @{
- */
-#define UC3B0 (	\
-		AVR32_PART_IS_DEFINED(UC3B064)  || \
-		AVR32_PART_IS_DEFINED(UC3B0128) || \
-		AVR32_PART_IS_DEFINED(UC3B0256) || \
-		AVR32_PART_IS_DEFINED(UC3B0512)	\
-		)
-
-#define UC3B1 (	\
-		AVR32_PART_IS_DEFINED(UC3B164)  || \
-		AVR32_PART_IS_DEFINED(UC3B1128) || \
-		AVR32_PART_IS_DEFINED(UC3B1256) || \
-		AVR32_PART_IS_DEFINED(UC3B1512)	\
-		)
-/** @} */
-
-/**
- * \name AVR UC3 C series
- * @{
- */
-#define UC3C0 (	\
-		AVR32_PART_IS_DEFINED(UC3C064C)  || \
-		AVR32_PART_IS_DEFINED(UC3C0128C) || \
-		AVR32_PART_IS_DEFINED(UC3C0256C) || \
-		AVR32_PART_IS_DEFINED(UC3C0512C) \
-		)
-
-#define UC3C1 (	\
-		AVR32_PART_IS_DEFINED(UC3C164C)  || \
-		AVR32_PART_IS_DEFINED(UC3C1128C) || \
-		AVR32_PART_IS_DEFINED(UC3C1256C) || \
-		AVR32_PART_IS_DEFINED(UC3C1512C) \
-		)
-
-#define UC3C2 (	\
-		AVR32_PART_IS_DEFINED(UC3C264C)  || \
-		AVR32_PART_IS_DEFINED(UC3C2128C) || \
-		AVR32_PART_IS_DEFINED(UC3C2256C) || \
-		AVR32_PART_IS_DEFINED(UC3C2512C) \
-		)
-/** @} */
-
-/**
- * \name AVR UC3 D series
- * @{
- */
-#define UC3D3 (	\
-		AVR32_PART_IS_DEFINED(UC64D3)  || \
-		AVR32_PART_IS_DEFINED(UC128D3) \
-		)
-
-#define UC3D4 (	\
-		AVR32_PART_IS_DEFINED(UC64D4)  || \
-		AVR32_PART_IS_DEFINED(UC128D4) \
-		)
-/** @} */
-
-/**
- * \name AVR UC3 L series
- * @{
- */
-#define UC3L0 (	\
-		AVR32_PART_IS_DEFINED(UC3L016) || \
-		AVR32_PART_IS_DEFINED(UC3L032) || \
-		AVR32_PART_IS_DEFINED(UC3L064) \
-		)
-
-#define UC3L0128 ( \
-		AVR32_PART_IS_DEFINED(UC3L0128)	\
-		)
-
-#define UC3L0256 ( \
-		AVR32_PART_IS_DEFINED(UC3L0256)	\
-		)
-
-#define UC3L3 (	\
-		AVR32_PART_IS_DEFINED(UC64L3U)  || \
-		AVR32_PART_IS_DEFINED(UC128L3U) || \
-		AVR32_PART_IS_DEFINED(UC256L3U)	\
-		)
-
-#define UC3L4 (	\
-		AVR32_PART_IS_DEFINED(UC64L4U)  || \
-		AVR32_PART_IS_DEFINED(UC128L4U) || \
-		AVR32_PART_IS_DEFINED(UC256L4U)	\
-		)
-
-#define UC3L3_L4 (UC3L3 || UC3L4)
-/** @} */
-
-/**
- * \name AVR UC3 families
- * @{
- */
-/** AVR UC3 A family */
-#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
-
-/** AVR UC3 B family */
-#define UC3B (UC3B0 || UC3B1)
-
-/** AVR UC3 C family */
-#define UC3C (UC3C0 || UC3C1 || UC3C2)
-
-/** AVR UC3 D family */
-#define UC3D (UC3D3 || UC3D4)
-
-/** AVR UC3 L family */
-#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
-/** @} */
-
-/** AVR UC3 product line */
-#define UC3  (UC3A || UC3B || UC3C || UC3D || UC3L)
-
-/** @} */
-
-/**
- * \defgroup xmega_part_macros_group AVR XMEGA parts
- * @{
- */
-
-/**
- * \name AVR XMEGA A series
- * @{
- */
-#define XMEGA_A1 ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A1)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A1) \
-		)
-
-#define XMEGA_A3 ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A3) || \
-		AVR8_PART_IS_DEFINED(ATxmega192A3) || \
-		AVR8_PART_IS_DEFINED(ATxmega256A3) \
-		)
-
-#define XMEGA_A3B ( \
-		AVR8_PART_IS_DEFINED(ATxmega256A3B) \
-		)
-
-#define XMEGA_A4 ( \
-		AVR8_PART_IS_DEFINED(ATxmega16A4) || \
-		AVR8_PART_IS_DEFINED(ATxmega32A4) \
-		)
-/** @} */
-
-/**
- * \name AVR XMEGA AU series
- * @{
- */
-#define XMEGA_A1U ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A1U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A1U) \
-		)
-
-#define XMEGA_A3U ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A3U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
-		AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
-		AVR8_PART_IS_DEFINED(ATxmega256A3U) \
-		)
-
-#define XMEGA_A3BU ( \
-		AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
-		)
-
-#define XMEGA_A4U ( \
-		AVR8_PART_IS_DEFINED(ATxmega16A4U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega32A4U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64A4U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A4U) \
-		)
-/** @} */
-
-/**
- * \name AVR XMEGA B series
- * @{
- */
-#define XMEGA_B1  ( \
-		AVR8_PART_IS_DEFINED(ATxmega64B1)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128B1) \
-		)
-
-#define XMEGA_B3  ( \
-		AVR8_PART_IS_DEFINED(ATxmega64B3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128B3) \
-		)
-/** @} */
-
-/**
- * \name AVR XMEGA C series
- * @{
- */
-#define XMEGA_C3 ( \
-		AVR8_PART_IS_DEFINED(ATxmega384C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega256C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega192C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64C3)   || \
-		AVR8_PART_IS_DEFINED(ATxmega32C3) \
-		)
-
-#define XMEGA_C4 ( \
-		AVR8_PART_IS_DEFINED(ATxmega32C4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega16C4) \
-		)
-/** @} */
-
-/**
- * \name AVR XMEGA D series
- * @{
- */
-#define XMEGA_D3 ( \
-		AVR8_PART_IS_DEFINED(ATxmega32D3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64D3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128D3) || \
-		AVR8_PART_IS_DEFINED(ATxmega192D3) || \
-		AVR8_PART_IS_DEFINED(ATxmega256D3) || \
-		AVR8_PART_IS_DEFINED(ATxmega384D3) \
-		)
-
-#define XMEGA_D4 ( \
-		AVR8_PART_IS_DEFINED(ATxmega16D4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega32D4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64D4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128D4) \
-		)
-/** @} */
-
-/**
- * \name AVR XMEGA E series
- * @{
- */
-#define XMEGA_E5 ( \
-		AVR8_PART_IS_DEFINED(ATxmega8E5)   || \
-		AVR8_PART_IS_DEFINED(ATxmega16E5)  || \
-		AVR8_PART_IS_DEFINED(ATxmega32E5)     \
-	)
-/** @} */
-
-
-/**
- * \name AVR XMEGA families
- * @{
- */
-/** AVR XMEGA A family */
-#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
-
-/** AVR XMEGA AU family */
-#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
-
-/** AVR XMEGA B family */
-#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
-
-/** AVR XMEGA C family */
-#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
-
-/** AVR XMEGA D family */
-#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
-
-/** AVR XMEGA E family */
-#define XMEGA_E (XMEGA_E5)
-/** @} */
-
-
-/** AVR XMEGA product line */
-#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
-
-/** @} */
-
-/**
- * \defgroup mega_part_macros_group megaAVR parts
- *
- * \note These megaAVR groupings are based on the groups in AVR Libc for the
- * part header files. They are not names of official megaAVR device series or
- * families.
- *
- * @{
- */
-
-/**
- * \name ATmegaxx0/xx1 subgroups
- * @{
- */
-#define MEGA_XX0 ( \
-		AVR8_PART_IS_DEFINED(ATmega640)  || \
-		AVR8_PART_IS_DEFINED(ATmega1280) || \
-		AVR8_PART_IS_DEFINED(ATmega2560) \
-		)
-
-#define MEGA_XX1 ( \
-		AVR8_PART_IS_DEFINED(ATmega1281) || \
-		AVR8_PART_IS_DEFINED(ATmega2561) \
-		)
-/** @} */
-
-/**
- * \name megaAVR groups
- * @{
- */
-/** ATmegaxx0/xx1 group */
-#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
-
-/** ATmegaxx4 group */
-#define MEGA_XX4 ( \
-		AVR8_PART_IS_DEFINED(ATmega164A)  || \
-		AVR8_PART_IS_DEFINED(ATmega164PA) || \
-		AVR8_PART_IS_DEFINED(ATmega324A)  || \
-		AVR8_PART_IS_DEFINED(ATmega324PA) || \
-		AVR8_PART_IS_DEFINED(ATmega324PB) || \
-		AVR8_PART_IS_DEFINED(ATmega644)   || \
-		AVR8_PART_IS_DEFINED(ATmega644A)  || \
-		AVR8_PART_IS_DEFINED(ATmega644PA) || \
-		AVR8_PART_IS_DEFINED(ATmega1284P)   || \
-		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
-		)
-
-/** ATmegaxx4 group */
-#define MEGA_XX4_A ( \
-		AVR8_PART_IS_DEFINED(ATmega164A)  || \
-		AVR8_PART_IS_DEFINED(ATmega164PA) || \
-		AVR8_PART_IS_DEFINED(ATmega324A)  || \
-		AVR8_PART_IS_DEFINED(ATmega324PA) || \
-		AVR8_PART_IS_DEFINED(ATmega644A)  || \
-		AVR8_PART_IS_DEFINED(ATmega644PA) || \
-		AVR8_PART_IS_DEFINED(ATmega1284P) \
-		)
-
-/** ATmegaxx8 group */
-#define MEGA_XX8 ( \
-		AVR8_PART_IS_DEFINED(ATmega48)    || \
-		AVR8_PART_IS_DEFINED(ATmega48A)   || \
-		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega48PB)  || \
-		AVR8_PART_IS_DEFINED(ATmega88)    || \
-		AVR8_PART_IS_DEFINED(ATmega88A)   || \
-		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega88PB)  || \
-		AVR8_PART_IS_DEFINED(ATmega168)   || \
-		AVR8_PART_IS_DEFINED(ATmega168A)  || \
-		AVR8_PART_IS_DEFINED(ATmega168PA) || \
-		AVR8_PART_IS_DEFINED(ATmega168PB) || \
-		AVR8_PART_IS_DEFINED(ATmega328)   || \
-		AVR8_PART_IS_DEFINED(ATmega328P)  || \
-		AVR8_PART_IS_DEFINED(ATmega328PB) \
-		)
-
-/** ATmegaxx8A/P/PA group */
-#define MEGA_XX8_A ( \
-		AVR8_PART_IS_DEFINED(ATmega48A)   || \
-		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega88A)   || \
-		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega168A)  || \
-		AVR8_PART_IS_DEFINED(ATmega168PA) || \
-		AVR8_PART_IS_DEFINED(ATmega328P) \
-		)
-
-/** ATmegaxx group */
-#define MEGA_XX ( \
-		AVR8_PART_IS_DEFINED(ATmega16)   || \
-		AVR8_PART_IS_DEFINED(ATmega16A)  || \
-		AVR8_PART_IS_DEFINED(ATmega32)   || \
-		AVR8_PART_IS_DEFINED(ATmega32A)  || \
-		AVR8_PART_IS_DEFINED(ATmega64)   || \
-		AVR8_PART_IS_DEFINED(ATmega64A)  || \
-		AVR8_PART_IS_DEFINED(ATmega128)  || \
-		AVR8_PART_IS_DEFINED(ATmega128A) \
-		)
-
-/** ATmegaxxA/P/PA group */
-#define MEGA_XX_A ( \
-		AVR8_PART_IS_DEFINED(ATmega16A)  || \
-		AVR8_PART_IS_DEFINED(ATmega32A)  || \
-		AVR8_PART_IS_DEFINED(ATmega64A)  || \
-		AVR8_PART_IS_DEFINED(ATmega128A) \
-		)
-/** ATmegaxxRFA1 group */
-#define MEGA_RFA1 ( \
-		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
-		)
-
-/** ATmegaxxRFR2 group */
-#define MEGA_RFR2 ( \
-		AVR8_PART_IS_DEFINED(ATmega64RFR2)   || \
-		AVR8_PART_IS_DEFINED(ATmega128RFR2)  || \
-		AVR8_PART_IS_DEFINED(ATmega256RFR2)  || \
-		AVR8_PART_IS_DEFINED(ATmega644RFR2)  || \
-		AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
-		AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
-		)
-
-
-/** ATmegaxxRFxx group */
-#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
-
-/**
- * \name ATmegaxx_un0/un1/un2 subgroups
- * @{
- */
-#define MEGA_XX_UN0 ( \
-		AVR8_PART_IS_DEFINED(ATmega16)    || \
-		AVR8_PART_IS_DEFINED(ATmega16A)   || \
-		AVR8_PART_IS_DEFINED(ATmega32)    || \
-		AVR8_PART_IS_DEFINED(ATmega32A)	\
-		)
-
-/** ATmegaxx group without power reduction and
- *  And interrupt sense register.
- */
-#define MEGA_XX_UN1 ( \
-		AVR8_PART_IS_DEFINED(ATmega64)    || \
-		AVR8_PART_IS_DEFINED(ATmega64A)   || \
-		AVR8_PART_IS_DEFINED(ATmega128)   || \
-		AVR8_PART_IS_DEFINED(ATmega128A) \
-		)
-
-/** ATmegaxx group without power reduction and
- *  And interrupt sense register.
- */
-#define MEGA_XX_UN2 ( \
-		AVR8_PART_IS_DEFINED(ATmega169P)  || \
-		AVR8_PART_IS_DEFINED(ATmega169PA) || \
-		AVR8_PART_IS_DEFINED(ATmega329P)  || \
-		AVR8_PART_IS_DEFINED(ATmega329PA) \
-		)
-
-/** Devices added to complete megaAVR offering.
- *  Please do not use this group symbol as it is not intended
- *  to be permanent: the devices should be regrouped.
- */
-#define MEGA_UNCATEGORIZED ( \
-		AVR8_PART_IS_DEFINED(AT90CAN128)     || \
-		AVR8_PART_IS_DEFINED(AT90CAN32)      || \
-		AVR8_PART_IS_DEFINED(AT90CAN64)      || \
-		AVR8_PART_IS_DEFINED(AT90PWM1)       || \
-		AVR8_PART_IS_DEFINED(AT90PWM216)     || \
-		AVR8_PART_IS_DEFINED(AT90PWM2B)      || \
-		AVR8_PART_IS_DEFINED(AT90PWM316)     || \
-		AVR8_PART_IS_DEFINED(AT90PWM3B)      || \
-		AVR8_PART_IS_DEFINED(AT90PWM81)      || \
-		AVR8_PART_IS_DEFINED(AT90USB1286)    || \
-		AVR8_PART_IS_DEFINED(AT90USB1287)    || \
-		AVR8_PART_IS_DEFINED(AT90USB162)     || \
-		AVR8_PART_IS_DEFINED(AT90USB646)     || \
-		AVR8_PART_IS_DEFINED(AT90USB647)     || \
-		AVR8_PART_IS_DEFINED(AT90USB82)      || \
-		AVR8_PART_IS_DEFINED(ATmega1284)     || \
-		AVR8_PART_IS_DEFINED(ATmega162)      || \
-		AVR8_PART_IS_DEFINED(ATmega164P)     || \
-		AVR8_PART_IS_DEFINED(ATmega165A)     || \
-		AVR8_PART_IS_DEFINED(ATmega165P)     || \
-		AVR8_PART_IS_DEFINED(ATmega165PA)    || \
-		AVR8_PART_IS_DEFINED(ATmega168P)     || \
-		AVR8_PART_IS_DEFINED(ATmega169A)     || \
-		AVR8_PART_IS_DEFINED(ATmega16M1)     || \
-		AVR8_PART_IS_DEFINED(ATmega16U2)     || \
-		AVR8_PART_IS_DEFINED(ATmega16U4)     || \
-		AVR8_PART_IS_DEFINED(ATmega256RFA2)  || \
-		AVR8_PART_IS_DEFINED(ATmega324P)     || \
-		AVR8_PART_IS_DEFINED(ATmega325)      || \
-		AVR8_PART_IS_DEFINED(ATmega3250)     || \
-		AVR8_PART_IS_DEFINED(ATmega3250A)    || \
-		AVR8_PART_IS_DEFINED(ATmega3250P)    || \
-		AVR8_PART_IS_DEFINED(ATmega3250PA)   || \
-		AVR8_PART_IS_DEFINED(ATmega325A)     || \
-		AVR8_PART_IS_DEFINED(ATmega325P)     || \
-		AVR8_PART_IS_DEFINED(ATmega325PA)    || \
-		AVR8_PART_IS_DEFINED(ATmega329)      || \
-		AVR8_PART_IS_DEFINED(ATmega3290)     || \
-		AVR8_PART_IS_DEFINED(ATmega3290A)    || \
-		AVR8_PART_IS_DEFINED(ATmega3290P)    || \
-		AVR8_PART_IS_DEFINED(ATmega3290PA)   || \
-		AVR8_PART_IS_DEFINED(ATmega329A)     || \
-		AVR8_PART_IS_DEFINED(ATmega32M1)     || \
-		AVR8_PART_IS_DEFINED(ATmega32U2)     || \
-		AVR8_PART_IS_DEFINED(ATmega32U4)     || \
-		AVR8_PART_IS_DEFINED(ATmega48P)      || \
-		AVR8_PART_IS_DEFINED(ATmega644P)     || \
-		AVR8_PART_IS_DEFINED(ATmega645)      || \
-		AVR8_PART_IS_DEFINED(ATmega6450)     || \
-		AVR8_PART_IS_DEFINED(ATmega6450A)    || \
-		AVR8_PART_IS_DEFINED(ATmega6450P)    || \
-		AVR8_PART_IS_DEFINED(ATmega645A)     || \
-		AVR8_PART_IS_DEFINED(ATmega645P)     || \
-		AVR8_PART_IS_DEFINED(ATmega649)      || \
-		AVR8_PART_IS_DEFINED(ATmega6490)     || \
-		AVR8_PART_IS_DEFINED(ATmega6490A)    || \
-		AVR8_PART_IS_DEFINED(ATmega6490P)    || \
-		AVR8_PART_IS_DEFINED(ATmega649A)     || \
-		AVR8_PART_IS_DEFINED(ATmega649P)     || \
-		AVR8_PART_IS_DEFINED(ATmega64M1)     || \
-		AVR8_PART_IS_DEFINED(ATmega64RFA2)   || \
-		AVR8_PART_IS_DEFINED(ATmega8)        || \
-		AVR8_PART_IS_DEFINED(ATmega8515)     || \
-		AVR8_PART_IS_DEFINED(ATmega8535)     || \
-		AVR8_PART_IS_DEFINED(ATmega88P)      || \
-		AVR8_PART_IS_DEFINED(ATmega8A)       || \
-		AVR8_PART_IS_DEFINED(ATmega8U2)         \
-	)
-
-/** Unspecified group */
-#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
-	MEGA_UNCATEGORIZED)
-
-/** @} */
-
-/** megaAVR product line */
-#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
-	MEGA_UNSPECIFIED)
-
-/** @} */
-
-/**
- * \defgroup sam_part_macros_group SAM parts
- * @{
- */
-
-/**
- * \name SAM3S series
- * @{
- */
-#define SAM3S1 ( \
-		SAM_PART_IS_DEFINED(SAM3S1A) ||	\
-		SAM_PART_IS_DEFINED(SAM3S1B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S1C) \
-		)
-
-#define SAM3S2 ( \
-		SAM_PART_IS_DEFINED(SAM3S2A) ||	\
-		SAM_PART_IS_DEFINED(SAM3S2B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S2C) \
-		)
-
-#define SAM3S4 ( \
-		SAM_PART_IS_DEFINED(SAM3S4A) ||	\
-		SAM_PART_IS_DEFINED(SAM3S4B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S4C) \
-		)
-
-#define SAM3S8 ( \
-		SAM_PART_IS_DEFINED(SAM3S8B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S8C) \
-		)
-
-#define SAM3SD8 ( \
-		SAM_PART_IS_DEFINED(SAM3SD8B) || \
-		SAM_PART_IS_DEFINED(SAM3SD8C) \
-		)
-/** @} */
-
-/**
- * \name SAM3U series
- * @{
- */
-#define SAM3U1 ( \
-		SAM_PART_IS_DEFINED(SAM3U1C) ||	\
-		SAM_PART_IS_DEFINED(SAM3U1E) \
-		)
-
-#define SAM3U2 ( \
-		SAM_PART_IS_DEFINED(SAM3U2C) ||	\
-		SAM_PART_IS_DEFINED(SAM3U2E) \
-		)
-
-#define SAM3U4 ( \
-		SAM_PART_IS_DEFINED(SAM3U4C) ||	\
-		SAM_PART_IS_DEFINED(SAM3U4E) \
-		)
-/** @} */
-
-/**
- * \name SAM3N series
- * @{
- */
-#define SAM3N00 ( \
-		SAM_PART_IS_DEFINED(SAM3N00A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N00B) \
-		)
-
-#define SAM3N0 ( \
-		SAM_PART_IS_DEFINED(SAM3N0A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N0B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N0C) \
-		)
-
-#define SAM3N1 ( \
-		SAM_PART_IS_DEFINED(SAM3N1A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N1B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N1C) \
-		)
-
-#define SAM3N2 ( \
-		SAM_PART_IS_DEFINED(SAM3N2A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N2B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N2C) \
-		)
-
-#define SAM3N4 ( \
-		SAM_PART_IS_DEFINED(SAM3N4A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N4B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N4C) \
-		)
-/** @} */
-
-/**
- * \name SAM3X series
- * @{
- */
-#define SAM3X4 ( \
-		SAM_PART_IS_DEFINED(SAM3X4C) ||	\
-		SAM_PART_IS_DEFINED(SAM3X4E) \
-		)
-
-#define SAM3X8 ( \
-		SAM_PART_IS_DEFINED(SAM3X8C) ||	\
-		SAM_PART_IS_DEFINED(SAM3X8E) ||	\
-		SAM_PART_IS_DEFINED(SAM3X8H) \
-		)
-/** @} */
-
-/**
- * \name SAM3A series
- * @{
- */
-#define SAM3A4 ( \
-		SAM_PART_IS_DEFINED(SAM3A4C) \
-		)
-
-#define SAM3A8 ( \
-		SAM_PART_IS_DEFINED(SAM3A8C) \
-		)
-/** @} */
-
-/**
- * \name SAM4S series
- * @{
- */
-#define SAM4S2 ( \
-		SAM_PART_IS_DEFINED(SAM4S2A) || \
- 		SAM_PART_IS_DEFINED(SAM4S2B) || \
- 		SAM_PART_IS_DEFINED(SAM4S2C) \
- 		)
-
-#define SAM4S4 ( \
-		SAM_PART_IS_DEFINED(SAM4S4A) || \
- 		SAM_PART_IS_DEFINED(SAM4S4B) || \
- 		SAM_PART_IS_DEFINED(SAM4S4C) \
- 		)
-
-#define SAM4S8 ( \
-		SAM_PART_IS_DEFINED(SAM4S8B) ||	\
-		SAM_PART_IS_DEFINED(SAM4S8C) \
-		)
-
-#define SAM4S16 ( \
-		SAM_PART_IS_DEFINED(SAM4S16B) || \
-		SAM_PART_IS_DEFINED(SAM4S16C) \
-		)
-
-#define SAM4SA16 ( \
-		SAM_PART_IS_DEFINED(SAM4SA16B) || \
-		SAM_PART_IS_DEFINED(SAM4SA16C)    \
-	)
-
-#define SAM4SD16 ( \
-		SAM_PART_IS_DEFINED(SAM4SD16B) || \
-		SAM_PART_IS_DEFINED(SAM4SD16C)    \
-	)
-
-#define SAM4SD32 ( \
-		SAM_PART_IS_DEFINED(SAM4SD32B) || \
-		SAM_PART_IS_DEFINED(SAM4SD32C)    \
-	)
-/** @} */
-
-/**
- * \name SAM4L series
- * @{
- */
-#define SAM4LS ( \
-		SAM_PART_IS_DEFINED(SAM4LS2A) || \
-		SAM_PART_IS_DEFINED(SAM4LS2B) || \
-		SAM_PART_IS_DEFINED(SAM4LS2C) || \
-		SAM_PART_IS_DEFINED(SAM4LS4A) || \
-		SAM_PART_IS_DEFINED(SAM4LS4B) || \
-		SAM_PART_IS_DEFINED(SAM4LS4C) || \
-		SAM_PART_IS_DEFINED(SAM4LS8A) || \
-		SAM_PART_IS_DEFINED(SAM4LS8B) || \
-		SAM_PART_IS_DEFINED(SAM4LS8C)    \
-		)
-
-#define SAM4LC ( \
-		SAM_PART_IS_DEFINED(SAM4LC2A) || \
-		SAM_PART_IS_DEFINED(SAM4LC2B) || \
-		SAM_PART_IS_DEFINED(SAM4LC2C) || \
-		SAM_PART_IS_DEFINED(SAM4LC4A) || \
-		SAM_PART_IS_DEFINED(SAM4LC4B) || \
-		SAM_PART_IS_DEFINED(SAM4LC4C) || \
-		SAM_PART_IS_DEFINED(SAM4LC8A) || \
-		SAM_PART_IS_DEFINED(SAM4LC8B) || \
-		SAM_PART_IS_DEFINED(SAM4LC8C)    \
-		)
-/** @} */
-
-/**
- * \name SAMD20 series
- * @{
- */
-#define SAMD20J ( \
-		SAM_PART_IS_DEFINED(SAMD20J14) || \
-		SAM_PART_IS_DEFINED(SAMD20J15) || \
-		SAM_PART_IS_DEFINED(SAMD20J16) || \
-		SAM_PART_IS_DEFINED(SAMD20J14B) || \
-		SAM_PART_IS_DEFINED(SAMD20J15B) || \
-		SAM_PART_IS_DEFINED(SAMD20J16B) || \
-		SAM_PART_IS_DEFINED(SAMD20J17) || \
-		SAM_PART_IS_DEFINED(SAMD20J18) \
-	)
-
-#define SAMD20G ( \
-		SAM_PART_IS_DEFINED(SAMD20G14)  || \
-		SAM_PART_IS_DEFINED(SAMD20G15)  || \
-		SAM_PART_IS_DEFINED(SAMD20G16)  || \
-		SAM_PART_IS_DEFINED(SAMD20G14B)  || \
-		SAM_PART_IS_DEFINED(SAMD20G15B)  || \
-		SAM_PART_IS_DEFINED(SAMD20G16B)  || \
-		SAM_PART_IS_DEFINED(SAMD20G17)  || \
-		SAM_PART_IS_DEFINED(SAMD20G17U) || \
-		SAM_PART_IS_DEFINED(SAMD20G18)  || \
-		SAM_PART_IS_DEFINED(SAMD20G18U) \
-	)
-
-#define SAMD20E ( \
-		SAM_PART_IS_DEFINED(SAMD20E14) || \
-		SAM_PART_IS_DEFINED(SAMD20E15) || \
-		SAM_PART_IS_DEFINED(SAMD20E16) || \
-		SAM_PART_IS_DEFINED(SAMD20E14B) || \
-		SAM_PART_IS_DEFINED(SAMD20E15B) || \
-		SAM_PART_IS_DEFINED(SAMD20E16B) || \
-		SAM_PART_IS_DEFINED(SAMD20E17) || \
-		SAM_PART_IS_DEFINED(SAMD20E18) \
-	)
-
-/** @} */
-
-/**
- * \name SAMD21 series
- * @{
- */
-#define SAMD21J ( \
-		SAM_PART_IS_DEFINED(SAMD21J15A) || \
-		SAM_PART_IS_DEFINED(SAMD21J16A) || \
-		SAM_PART_IS_DEFINED(SAMD21J17A) || \
-		SAM_PART_IS_DEFINED(SAMD21J18A) || \
-		SAM_PART_IS_DEFINED(SAMD21J15B) || \
-		SAM_PART_IS_DEFINED(SAMD21J16B) || \
-		SAM_PART_IS_DEFINED(SAMD21J17D) \
-	)
-
-#define SAMD21G ( \
-		SAM_PART_IS_DEFINED(SAMD21G15A) || \
-		SAM_PART_IS_DEFINED(SAMD21G16A) || \
-		SAM_PART_IS_DEFINED(SAMD21G17A) || \
-		SAM_PART_IS_DEFINED(SAMD21G17AU) || \
-		SAM_PART_IS_DEFINED(SAMD21G18A) || \
-		SAM_PART_IS_DEFINED(SAMD21G18AU) || \
-		SAM_PART_IS_DEFINED(SAMD21G15B) || \
-		SAM_PART_IS_DEFINED(SAMD21G16B) || \
-		SAM_PART_IS_DEFINED(SAMD21G15L) || \
-		SAM_PART_IS_DEFINED(SAMD21G16L) || \
-		SAM_PART_IS_DEFINED(SAMD21G17D) || \
-		SAM_PART_IS_DEFINED(SAMD21G17L) \
-	)
-
-#define SAMD21GXXL ( \
-		SAM_PART_IS_DEFINED(SAMD21G15L) || \
-		SAM_PART_IS_DEFINED(SAMD21G16L) || \
-		SAM_PART_IS_DEFINED(SAMD21G17L) \
-		)
-
-#define SAMD21E ( \
-		SAM_PART_IS_DEFINED(SAMD21E15A) || \
-		SAM_PART_IS_DEFINED(SAMD21E16A) || \
-		SAM_PART_IS_DEFINED(SAMD21E17A) || \
-		SAM_PART_IS_DEFINED(SAMD21E18A) || \
-		SAM_PART_IS_DEFINED(SAMD21E15B) || \
-		SAM_PART_IS_DEFINED(SAMD21E15BU) || \
-		SAM_PART_IS_DEFINED(SAMD21E16B) || \
-		SAM_PART_IS_DEFINED(SAMD21E16BU) || \
-		SAM_PART_IS_DEFINED(SAMD21E15L) || \
-		SAM_PART_IS_DEFINED(SAMD21E16L) || \
-		SAM_PART_IS_DEFINED(SAMD21E17D) || \
-		SAM_PART_IS_DEFINED(SAMD21E17DU) || \
-		SAM_PART_IS_DEFINED(SAMD21E17L) \
-	)
-
-#define SAMD21EXXL ( \
-		SAM_PART_IS_DEFINED(SAMD21E15L) || \
-		SAM_PART_IS_DEFINED(SAMD21E16L) || \
-		SAM_PART_IS_DEFINED(SAMD21E17L) \
-		)
-
-/** @} */
-
-/**
- * \name SAMR21 series
- * @{
- */
-#define SAMR21G ( \
-		SAM_PART_IS_DEFINED(SAMR21G16A) || \
-		SAM_PART_IS_DEFINED(SAMR21G17A) || \
-		SAM_PART_IS_DEFINED(SAMR21G18A) \
-	)
-
-#define SAMR21E ( \
-		SAM_PART_IS_DEFINED(SAMR21E16A) || \
-		SAM_PART_IS_DEFINED(SAMR21E17A) || \
-		SAM_PART_IS_DEFINED(SAMR21E18A) || \
-		SAM_PART_IS_DEFINED(SAMR21E19A) \
-	)
-/** @} */
-
-/**
- * \name SAMR30 series
- * @{
- */
-#define SAMR30G ( \
-		SAM_PART_IS_DEFINED(SAMR30G18A) \
-	)
-
-#define SAMR30E ( \
-		SAM_PART_IS_DEFINED(SAMR30E18A) \
-	)
-/** @} */
-
-/**
- * \name SAMR34 series
- * @{
- */
-#define SAMR34J ( \
-		SAM_PART_IS_DEFINED(SAMR34J18A) || \
-		SAM_PART_IS_DEFINED(SAMR34J17A) || \
-		SAM_PART_IS_DEFINED(SAMR34J16A) || \
-		SAM_PART_IS_DEFINED(SAMR34J18B) || \
-		SAM_PART_IS_DEFINED(SAMR34J17B) || \
-		SAM_PART_IS_DEFINED(SAMR34J16B) \
-	)
-	
-/* Group for SAMR34 A variant: SAMR34J [16/17/18]A */
-#define SAMR34JXXA ( \
-		SAM_PART_IS_DEFINED(SAMR34J18A) || \
-		SAM_PART_IS_DEFINED(SAMR34J17A) || \
-		SAM_PART_IS_DEFINED(SAMR34J16A) \
-)
-/* Group for SAMR34 B variant: SAMR34J [16/17/18]B */
-#define SAMR34JXXB ( \
-		SAM_PART_IS_DEFINED(SAMR34J18B) || \
-		SAM_PART_IS_DEFINED(SAMR34J17B) || \
-		SAM_PART_IS_DEFINED(SAMR34J16B) \
-)
-
-/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */
-#define SAMR35J ( \
-		SAM_PART_IS_DEFINED(SAMR35J18B) || \
-		SAM_PART_IS_DEFINED(SAMR35J17B) || \
-		SAM_PART_IS_DEFINED(SAMR35J16B) \
-)
-/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */
-#define SAMR35JXXB ( \
-		SAM_PART_IS_DEFINED(SAMR35J18B) || \
-		SAM_PART_IS_DEFINED(SAMR35J17B) || \
-		SAM_PART_IS_DEFINED(SAMR35J16B) \
-)
-
-/**
- * \name SAMB11 series
- * @{
- */
-#define SAMB11G ( \
-		SAM_PART_IS_DEFINED(SAMB11G18A) || \
-		SAM_PART_IS_DEFINED(SAMB11ZR) \
-	)
-#define BTLC1000 ( \
-		SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
-	)
-
-/** @} */
-
-/**
- * \name SAMD09 series
- * @{
- */
-#define SAMD09C ( \
-		SAM_PART_IS_DEFINED(SAMD09C13A) \
-	)
-
-#define SAMD09D ( \
-		SAM_PART_IS_DEFINED(SAMD09D14A) \
-	)
-/** @} */
-
-/**
- * \name SAMD10 series
- * @{
- */
-#define SAMD10C ( \
-		SAM_PART_IS_DEFINED(SAMD10C12A) || \
-		SAM_PART_IS_DEFINED(SAMD10C13A) || \
-		SAM_PART_IS_DEFINED(SAMD10C14A) \
-	)
-
-#define SAMD10DS ( \
-		SAM_PART_IS_DEFINED(SAMD10D12AS) || \
-		SAM_PART_IS_DEFINED(SAMD10D13AS) || \
-		SAM_PART_IS_DEFINED(SAMD10D14AS) \
-	)
-
-#define SAMD10DM ( \
-		SAM_PART_IS_DEFINED(SAMD10D12AM) || \
-		SAM_PART_IS_DEFINED(SAMD10D13AM) || \
-		SAM_PART_IS_DEFINED(SAMD10D14AM) \
-	)
-
-#define SAMD10DU ( \
-		SAM_PART_IS_DEFINED(SAMD10D14AU) \
-	)
-/** @} */
-
-/**
- * \name SAMD11 series
- * @{
- */
-#define SAMD11C ( \
-		SAM_PART_IS_DEFINED(SAMD11C14A) \
-	)
-
-#define SAMD11DS ( \
-		SAM_PART_IS_DEFINED(SAMD11D14AS) \
-	)
-
-#define SAMD11DM ( \
-		SAM_PART_IS_DEFINED(SAMD11D14AM) \
-	)
-
-#define SAMD11DU ( \
-		SAM_PART_IS_DEFINED(SAMD11D14AU) \
-	)
-/** @} */
-
-/**
- * \name SAML21 series
- * @{
- */
-#define SAML21E ( \
-		SAM_PART_IS_DEFINED(SAML21E18A) || \
-		SAM_PART_IS_DEFINED(SAML21E15B) || \
-		SAM_PART_IS_DEFINED(SAML21E16B) || \
-		SAM_PART_IS_DEFINED(SAML21E17B) || \
-		SAM_PART_IS_DEFINED(SAML21E18B) \
-	)
-
-#define SAML21G ( \
-		SAM_PART_IS_DEFINED(SAML21G18A) || \
-		SAM_PART_IS_DEFINED(SAML21G16B) || \
-		SAM_PART_IS_DEFINED(SAML21G17B) || \
-		SAM_PART_IS_DEFINED(SAML21G18B) \
-	)
-
-#define SAML21J ( \
-		SAM_PART_IS_DEFINED(SAML21J18A) || \
-		SAM_PART_IS_DEFINED(SAML21J16B) || \
-		SAM_PART_IS_DEFINED(SAML21J17B) || \
-		SAM_PART_IS_DEFINED(SAML21J18B) \
-	)
-
-/* Group for SAML21 A variant: SAML21[E/G/J][18]A */
-#define SAML21XXXA ( \
-		SAM_PART_IS_DEFINED(SAML21E18A) || \
-		SAM_PART_IS_DEFINED(SAML21G18A) || \
-		SAM_PART_IS_DEFINED(SAML21J18A) \
-	)
-
-/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */
-#define SAML21XXXB ( \
-		SAM_PART_IS_DEFINED(SAML21E15B) || \
-		SAM_PART_IS_DEFINED(SAML21E16B) || \
-		SAM_PART_IS_DEFINED(SAML21E17B) || \
-		SAM_PART_IS_DEFINED(SAML21E18B) || \
-		SAM_PART_IS_DEFINED(SAML21G16B) || \
-		SAM_PART_IS_DEFINED(SAML21G17B) || \
-		SAM_PART_IS_DEFINED(SAML21G18B) || \
-		SAM_PART_IS_DEFINED(SAML21J16B) || \
-		SAM_PART_IS_DEFINED(SAML21J17B) || \
-		SAM_PART_IS_DEFINED(SAML21J18B) \
-	)
-
-/** @} */
-
-/**
- * \name SAML22 series
- * @{
- */
-#define SAML22N ( \
-		SAM_PART_IS_DEFINED(SAML22N16A) || \
-		SAM_PART_IS_DEFINED(SAML22N17A) || \
-		SAM_PART_IS_DEFINED(SAML22N18A) \
-	)
-
-#define SAML22G ( \
-		SAM_PART_IS_DEFINED(SAML22G16A) || \
-		SAM_PART_IS_DEFINED(SAML22G17A) || \
-		SAM_PART_IS_DEFINED(SAML22G18A) \
-	)
-
-#define SAML22J ( \
-		SAM_PART_IS_DEFINED(SAML22J16A) || \
-		SAM_PART_IS_DEFINED(SAML22J17A) || \
-		SAM_PART_IS_DEFINED(SAML22J18A) \
-	)
-/** @} */
-
-/**
- * \name SAMDA1 series
- * @{
- */
-#define SAMDA1J ( \
-		SAM_PART_IS_DEFINED(SAMDA1J14A) || \
-		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1J15A) || \
-		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1J16A) || \
-		SAM_PART_IS_DEFINED(SAMDA1J16B) \
-	)
-
-#define SAMDA1G ( \
-		SAM_PART_IS_DEFINED(SAMDA1G14A) || \
-		SAM_PART_IS_DEFINED(SAMDA1G14B) || \
-		SAM_PART_IS_DEFINED(SAMDA1G15A) || \
-		SAM_PART_IS_DEFINED(SAMDA1G15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1G16A) || \
-		SAM_PART_IS_DEFINED(SAMDA1G16B) \
-	)
-
-#define SAMDA1E ( \
-		SAM_PART_IS_DEFINED(SAMDA1E14A) || \
-		SAM_PART_IS_DEFINED(SAMDA1E14B) || \
-		SAM_PART_IS_DEFINED(SAMDA1E15A) || \
-		SAM_PART_IS_DEFINED(SAMDA1E15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1E16A) || \
-		SAM_PART_IS_DEFINED(SAMDA1E16B) \
-	)
-/** @} */
-
-/**
- * \name SAMHA1 series
- * @{
- */
-#define SAMHA1G ( \
-		SAM_PART_IS_DEFINED(SAMHA1G14A) || \
-		SAM_PART_IS_DEFINED(SAMHA1G15A) || \
-		SAM_PART_IS_DEFINED(SAMHA1G16A) || \
-		SAM_PART_IS_DEFINED(SAMHA1G14AB) || \
-		SAM_PART_IS_DEFINED(SAMHA1G15AB) || \
-		SAM_PART_IS_DEFINED(SAMHA1G16AB) \
-	)
-
-#define SAMHA1E ( \
-		SAM_PART_IS_DEFINED(SAMHA1E14A) || \
-		SAM_PART_IS_DEFINED(SAMHA1E15A) || \
-		SAM_PART_IS_DEFINED(SAMHA1E16A) || \
-		SAM_PART_IS_DEFINED(SAMHA1E14AB) || \
-		SAM_PART_IS_DEFINED(SAMHA1E15AB) || \
-		SAM_PART_IS_DEFINED(SAMHA1E16AB) \
-	)
-
-/** @} */
-
-/**
- * \name SAMHA0 series
- * @{
- */
-#define SAMHA0G ( \
-		SAM_PART_IS_DEFINED(SAMHA0G14AB) || \
-		SAM_PART_IS_DEFINED(SAMHA0G15AB) || \
-		SAM_PART_IS_DEFINED(SAMHA0G16AB) \
-	)
-
-#define SAMHA0E ( \
-		SAM_PART_IS_DEFINED(SAMHA0E14AB) || \
-		SAM_PART_IS_DEFINED(SAMHA0E15AB) || \
-		SAM_PART_IS_DEFINED(SAMHA0E16AB) \
-	)
-
-/** @} */
-
-/**
- * \name SAMC20 series
- * @{
- */
-#define SAMC20E ( \
-		SAM_PART_IS_DEFINED(SAMC20E15A) || \
-		SAM_PART_IS_DEFINED(SAMC20E16A) || \
-		SAM_PART_IS_DEFINED(SAMC20E17A) || \
-		SAM_PART_IS_DEFINED(SAMC20E18A) \
-	)
-
-#define SAMC20G ( \
-		SAM_PART_IS_DEFINED(SAMC20G15A) || \
-		SAM_PART_IS_DEFINED(SAMC20G16A) || \
-		SAM_PART_IS_DEFINED(SAMC20G17A) || \
-		SAM_PART_IS_DEFINED(SAMC20G18A) \
-	)
-
-#define SAMC20J ( \
-		SAM_PART_IS_DEFINED(SAMC20J15A) || \
-		SAM_PART_IS_DEFINED(SAMC20J16A) || \
-		SAM_PART_IS_DEFINED(SAMC20J17A) || \
-		SAM_PART_IS_DEFINED(SAMC20J18A) \
-	)
-/** @} */
-
-/**
- * \name SAMC21 series
- * @{
- */
-#define SAMC21E ( \
-		SAM_PART_IS_DEFINED(SAMC21E15A) || \
-		SAM_PART_IS_DEFINED(SAMC21E16A) || \
-		SAM_PART_IS_DEFINED(SAMC21E17A) || \
-		SAM_PART_IS_DEFINED(SAMC21E18A) \
-	)
-
-#define SAMC21G ( \
-		SAM_PART_IS_DEFINED(SAMC21G15A) || \
-		SAM_PART_IS_DEFINED(SAMC21G16A) || \
-		SAM_PART_IS_DEFINED(SAMC21G17A) || \
-		SAM_PART_IS_DEFINED(SAMC21G18A) \
-	)
-
-#define SAMC21J ( \
-		SAM_PART_IS_DEFINED(SAMC21J15A) || \
-		SAM_PART_IS_DEFINED(SAMC21J16A) || \
-		SAM_PART_IS_DEFINED(SAMC21J17A) || \
-		SAM_PART_IS_DEFINED(SAMC21J18A) \
-	)
-/** @} */
-
-/**
- * \name SAM4E series
- * @{
- */
-#define SAM4E8 ( \
-		SAM_PART_IS_DEFINED(SAM4E8C) || \
-		SAM_PART_IS_DEFINED(SAM4E8CB) || \
-		SAM_PART_IS_DEFINED(SAM4E8E) \
-		)
-
-#define SAM4E16 ( \
-		SAM_PART_IS_DEFINED(SAM4E16C) || \
-		SAM_PART_IS_DEFINED(SAM4E16CB) || \
-		SAM_PART_IS_DEFINED(SAM4E16E) \
-		)
-/** @} */
-
-/**
- * \name SAM4N series
- * @{
- */
-#define SAM4N8 ( \
-		SAM_PART_IS_DEFINED(SAM4N8A) || \
-		SAM_PART_IS_DEFINED(SAM4N8B) || \
-		SAM_PART_IS_DEFINED(SAM4N8C) \
-		)
-
-#define SAM4N16 ( \
-		SAM_PART_IS_DEFINED(SAM4N16B) || \
-		SAM_PART_IS_DEFINED(SAM4N16C) \
-		)
-/** @} */
-
-/**
- * \name SAM4C series
- * @{
- */
-#define SAM4C4_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C4C_0) \
-		)
-
-#define SAM4C4_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C4C_1) \
-		)
-
-#define SAM4C4 (SAM4C4_0 || SAM4C4_1)
-
-#define SAM4C8_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C8C_0) \
-		)
-
-#define SAM4C8_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C8C_1) \
-		)
-
-#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
-
-#define SAM4C16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C16C_0) \
-		)
-
-#define SAM4C16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C16C_1) \
-		)
-
-#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
-
-#define SAM4C32_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
-		SAM_PART_IS_DEFINED(SAM4C32E_0) \
-		)
-
-#define SAM4C32_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
-		SAM_PART_IS_DEFINED(SAM4C32E_1) \
-		)
-
-
-#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
-
-/** @} */
-
-/**
- * \name SAM4CM series
- * @{
- */
-#define SAM4CMP8_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
-		)
-
-#define SAM4CMP8_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
-		)
-
-#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
-
-#define SAM4CMP16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
-		)
-
-#define SAM4CMP16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
-		)
-
-#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
-
-#define SAM4CMP32_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
-		)
-
-#define SAM4CMP32_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
-		)
-
-#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
-
-#define SAM4CMS4_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
-		)
-
-#define SAM4CMS4_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
-		)
-
-#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1)
-
-#define SAM4CMS8_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
-		)
-
-#define SAM4CMS8_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
-		)
-
-#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
-
-#define SAM4CMS16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
-		)
-
-#define SAM4CMS16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
-		)
-
-#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
-
-#define SAM4CMS32_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
-		)
-
-#define SAM4CMS32_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
-		)
-
-#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
-
-/** @} */
-
-/**
- * \name SAM4CP series
- * @{
- */
-#define SAM4CP16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CP16B_0) \
-		)
-
-#define SAM4CP16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CP16B_1) \
-		)
-
-#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
-/** @} */
-
-/**
- * \name SAMG series
- * @{
- */
-#define SAMG51 ( \
-		SAM_PART_IS_DEFINED(SAMG51G18) \
-		)
-
-#define SAMG53 ( \
-		SAM_PART_IS_DEFINED(SAMG53G19) ||\
-		SAM_PART_IS_DEFINED(SAMG53N19) \
-		)
-
-#define SAMG54 ( \
-		SAM_PART_IS_DEFINED(SAMG54G19) ||\
-		SAM_PART_IS_DEFINED(SAMG54J19) ||\
-		SAM_PART_IS_DEFINED(SAMG54N19) \
-		)
-
-#define SAMG55 ( \
-		SAM_PART_IS_DEFINED(SAMG55G18) ||\
-		SAM_PART_IS_DEFINED(SAMG55G19) ||\
-		SAM_PART_IS_DEFINED(SAMG55J18) ||\
-		SAM_PART_IS_DEFINED(SAMG55J19) ||\
-		SAM_PART_IS_DEFINED(SAMG55N19) \
-		)
-/** @} */
-
-/**
- * \name SAMV71 series
- * @{
- */
-#define SAMV71J ( \
-		SAM_PART_IS_DEFINED(SAMV71J19) || \
-		SAM_PART_IS_DEFINED(SAMV71J20) || \
-		SAM_PART_IS_DEFINED(SAMV71J21) \
-	)
-
-#define SAMV71JB ( \
-		SAM_PART_IS_DEFINED(SAMV71J19B) || \
-		SAM_PART_IS_DEFINED(SAMV71J20B) || \
-		SAM_PART_IS_DEFINED(SAMV71J21B) \
-	)
-
-#define SAMV71N ( \
-		SAM_PART_IS_DEFINED(SAMV71N19) || \
-		SAM_PART_IS_DEFINED(SAMV71N20) || \
-		SAM_PART_IS_DEFINED(SAMV71N21) \
-	)
-
-#define SAMV71NB ( \
-		SAM_PART_IS_DEFINED(SAMV71N19B) || \
-		SAM_PART_IS_DEFINED(SAMV71N20B) || \
-		SAM_PART_IS_DEFINED(SAMV71N21B) \
-	)
-
-#define SAMV71Q ( \
-		SAM_PART_IS_DEFINED(SAMV71Q19) || \
-		SAM_PART_IS_DEFINED(SAMV71Q20) || \
-		SAM_PART_IS_DEFINED(SAMV71Q21) \
-	)
-
-#define SAMV71QB ( \
-		SAM_PART_IS_DEFINED(SAMV71Q19B) || \
-		SAM_PART_IS_DEFINED(SAMV71Q20B) || \
-		SAM_PART_IS_DEFINED(SAMV71Q21B) \
-	)
-
-/** @} */
-
-/**
- * \name SAMV70 series
- * @{
- */
-#define SAMV70J ( \
-		SAM_PART_IS_DEFINED(SAMV70J19) || \
-		SAM_PART_IS_DEFINED(SAMV70J20) \
-	)
-
-#define SAMV70JB ( \
-		SAM_PART_IS_DEFINED(SAMV70J19B) || \
-		SAM_PART_IS_DEFINED(SAMV70J20B) \
-	)
-
-#define SAMV70N ( \
-		SAM_PART_IS_DEFINED(SAMV70N19) || \
-		SAM_PART_IS_DEFINED(SAMV70N20) \
-	)
-
-#define SAMV70NB ( \
-		SAM_PART_IS_DEFINED(SAMV70N19B) || \
-		SAM_PART_IS_DEFINED(SAMV70N20B) \
-	)
-
-#define SAMV70Q ( \
-		SAM_PART_IS_DEFINED(SAMV70Q19) || \
-		SAM_PART_IS_DEFINED(SAMV70Q20) \
-	)
-#define SAMV70QB ( \
-		SAM_PART_IS_DEFINED(SAMV70Q19B) || \
-		SAM_PART_IS_DEFINED(SAMV70Q20B) \
-	)
-/** @} */
-
-/**
- * \name SAMS70 series
- * @{
- */
-#define SAMS70J ( \
-		SAM_PART_IS_DEFINED(SAMS70J19) || \
-		SAM_PART_IS_DEFINED(SAMS70J20) || \
-		SAM_PART_IS_DEFINED(SAMS70J21) \
-	)
-
-#define SAMS70JB ( \
-		SAM_PART_IS_DEFINED(SAMS70J19B) || \
-		SAM_PART_IS_DEFINED(SAMS70J20B) || \
-		SAM_PART_IS_DEFINED(SAMS70J21B) \
-	)
-
-#define SAMS70N ( \
-		SAM_PART_IS_DEFINED(SAMS70N19) || \
-		SAM_PART_IS_DEFINED(SAMS70N20) || \
-		SAM_PART_IS_DEFINED(SAMS70N21) \
-	)
-
-#define SAMS70NB ( \
-		SAM_PART_IS_DEFINED(SAMS70N19B) || \
-		SAM_PART_IS_DEFINED(SAMS70N20B) || \
-		SAM_PART_IS_DEFINED(SAMS70N21B) \
-	)
-
-#define SAMS70Q ( \
-		SAM_PART_IS_DEFINED(SAMS70Q19) || \
-		SAM_PART_IS_DEFINED(SAMS70Q20) || \
-		SAM_PART_IS_DEFINED(SAMS70Q21) \
-	)
-
-#define SAMS70QB ( \
-		SAM_PART_IS_DEFINED(SAMS70Q19B) || \
-		SAM_PART_IS_DEFINED(SAMS70Q20B) || \
-		SAM_PART_IS_DEFINED(SAMS70Q21B) \
-	)
-/** @} */
-
-/**
- * \name SAME70 series
- * @{
- */
-#define SAME70J ( \
-		SAM_PART_IS_DEFINED(SAME70J19) || \
-		SAM_PART_IS_DEFINED(SAME70J20) || \
-		SAM_PART_IS_DEFINED(SAME70J21) \
-	)
-
-#define SAME70JB ( \
-		SAM_PART_IS_DEFINED(SAME70J19B) || \
-		SAM_PART_IS_DEFINED(SAME70J20B) || \
-		SAM_PART_IS_DEFINED(SAME70J21B) \
-	)
-
-#define SAME70N ( \
-		SAM_PART_IS_DEFINED(SAME70N19) || \
-		SAM_PART_IS_DEFINED(SAME70N20) || \
-		SAM_PART_IS_DEFINED(SAME70N21) \
-	)
-
-#define SAME70NB ( \
-		SAM_PART_IS_DEFINED(SAME70N19B) || \
-		SAM_PART_IS_DEFINED(SAME70N20B) || \
-		SAM_PART_IS_DEFINED(SAME70N21B) \
-	)
-
-#define SAME70Q ( \
-		SAM_PART_IS_DEFINED(SAME70Q19) || \
-		SAM_PART_IS_DEFINED(SAME70Q20) || \
-		SAM_PART_IS_DEFINED(SAME70Q21)  \
-	)
-
-#define SAME70QB ( \
-		SAM_PART_IS_DEFINED(SAME70Q19B) || \
-		SAM_PART_IS_DEFINED(SAME70Q20B) || \
-		SAM_PART_IS_DEFINED(SAME70Q21B) \
-	)
-/** @} */
-
-/**
- * \name SAM families
- * @{
- */
-/** SAM3S Family */
-#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
-
-/** SAM3U Family */
-#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
-
-/** SAM3N Family */
-#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
-
-/** SAM3XA Family */
-#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
-
-/** SAM4S Family */
-#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
-
-/** SAM4L Family */
-#define SAM4L (SAM4LS || SAM4LC)
-
-/** SAMD20 Family */
-#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
-
-/** SAMD21 Family */
-#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
-
-/** SAMD09 Family */
-#define SAMD09 (SAMD09C || SAMD09D)
-
-/** SAMD10 Family */
-#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU)
-
-/** SAMD11 Family */
-#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU)
-
-/** SAMDA1 Family */
-#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E)
-
-/** SAMHA1 Family */
-#define SAMHA1 (SAMHA1G || SAMHA1E)
-
-/** SAMHA0 Family */
-#define SAMHA0 (SAMHA0G || SAMHA0E)
-
-/** SAMD Family */
-#define SAMD   (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1)
-
-/** SAMR21 Family */
-#define SAMR21 (SAMR21G || SAMR21E)
-
-/** SAMR30 Family */
-#define SAMR30 (SAMR30G || SAMR30E)
-
-/** SAMR34 Family */
-#define SAMR34 (SAMR34J)
-
-/** SAMR35 Family */
-#define SAMR35 (SAMR35J)
-
-/** SAMB11 Family */
-#define SAMB11 (SAMB11G || BTLC1000)
-
-/** SAML21 Family */
-#define SAML21 (SAML21J || SAML21G || SAML21E)
-
-/** SAML22 Family */
-#define SAML22 (SAML22J || SAML22G || SAML22N)
-/** SAMC20 Family */
-#define SAMC20 (SAMC20J || SAMC20G || SAMC20E)
-
-/** SAMC21 Family */
-#define SAMC21 (SAMC21J || SAMC21G || SAMC21E)
-
-/** SAM4E Family */
-#define SAM4E (SAM4E8 || SAM4E16)
-
-/** SAM4N Family */
-#define SAM4N (SAM4N8 || SAM4N16)
-
-/** SAM4C Family */
-#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
-#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
-#define SAM4C   (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32)
-
-/** SAM4CM Family */
-#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \
-			SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
-#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \
-			SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
-#define SAM4CM   (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \
-			SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
-
-/** SAM4CP Family */
-#define SAM4CP_0 (SAM4CP16_0)
-#define SAM4CP_1 (SAM4CP16_1)
-#define SAM4CP   (SAM4CP16)
-
-/** SAMG Family */
-#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55)
-
-/** SAMB Family */
-#define SAMB (SAMB11)
-
-/** SAMV71 Family */
-#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q || SAMV71JB || SAMV71NB || SAMV71QB)
-#define SAMV71B (SAMV71JB || SAMV71NB || SAMV71QB)
-
-/** SAMV70 Family */
-#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q || SAMV70JB || SAMV70NB || SAMV70QB)
-#define SAMV70B (SAMV70JB || SAMV70NB || SAMV70QB)
-
-/** SAME70 Family */
-#define SAME70 (SAME70J || SAME70N || SAME70Q || SAME70JB || SAME70NB || SAME70QB)
-#define SAME70B (SAME70JB || SAME70NB || SAME70QB)
-
-/** SAMS70 Family */
-#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q || SAMS70JB || SAMS70NB || SAMS70QB)
-#define SAMS70B (SAMS70JB || SAMS70NB || SAMS70QB)
-
-/** SAM0 product line (cortex-m0+) */
-#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\
-		SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1 ||\
-		SAMHA0 || SAMR34 || SAMR35)
-
-/** @} */
-
-/** SAM product line */
-#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
-		SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
-
-/** @} */
-
-/** @} */
-
-/** @} */
-
-#endif /* ATMEL_PARTS_H */
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+/**
+ * \defgroup part_macros_group Atmel part identification macros
+ *
+ * This collection of macros identify which series and families that the various
+ * Atmel parts belong to. These can be used to select part-dependent sections of
+ * code at compile time.
+ *
+ * @{
+ */
+
+/**
+ * \name Convenience macros for part checking
+ * @{
+ */
+/* ! Check GCC and IAR part definition for 8-bit AVR */
+#define AVR8_PART_IS_DEFINED(part) \
+	(defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for 32-bit AVR */
+#define AVR32_PART_IS_DEFINED(part) \
+	(defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for SAM */
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
+/** @} */
+
+/**
+ * \defgroup uc3_part_macros_group AVR UC3 parts
+ * @{
+ */
+
+/**
+ * \name AVR UC3 A series
+ * @{
+ */
+#define UC3A0 (	\
+		AVR32_PART_IS_DEFINED(UC3A0128) || \
+		AVR32_PART_IS_DEFINED(UC3A0256) || \
+		AVR32_PART_IS_DEFINED(UC3A0512)	\
+		)
+
+#define UC3A1 (	\
+		AVR32_PART_IS_DEFINED(UC3A1128) || \
+		AVR32_PART_IS_DEFINED(UC3A1256) || \
+		AVR32_PART_IS_DEFINED(UC3A1512)	\
+		)
+
+#define UC3A3 (	\
+		AVR32_PART_IS_DEFINED(UC3A364)   || \
+		AVR32_PART_IS_DEFINED(UC3A364S)  || \
+		AVR32_PART_IS_DEFINED(UC3A3128)  || \
+		AVR32_PART_IS_DEFINED(UC3A3128S) || \
+		AVR32_PART_IS_DEFINED(UC3A3256)  || \
+		AVR32_PART_IS_DEFINED(UC3A3256S) \
+		)
+
+#define UC3A4 (	\
+		AVR32_PART_IS_DEFINED(UC3A464)   || \
+		AVR32_PART_IS_DEFINED(UC3A464S)  || \
+		AVR32_PART_IS_DEFINED(UC3A4128)  || \
+		AVR32_PART_IS_DEFINED(UC3A4128S) || \
+		AVR32_PART_IS_DEFINED(UC3A4256)  || \
+		AVR32_PART_IS_DEFINED(UC3A4256S) \
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 B series
+ * @{
+ */
+#define UC3B0 (	\
+		AVR32_PART_IS_DEFINED(UC3B064)  || \
+		AVR32_PART_IS_DEFINED(UC3B0128) || \
+		AVR32_PART_IS_DEFINED(UC3B0256) || \
+		AVR32_PART_IS_DEFINED(UC3B0512)	\
+		)
+
+#define UC3B1 (	\
+		AVR32_PART_IS_DEFINED(UC3B164)  || \
+		AVR32_PART_IS_DEFINED(UC3B1128) || \
+		AVR32_PART_IS_DEFINED(UC3B1256) || \
+		AVR32_PART_IS_DEFINED(UC3B1512)	\
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 C series
+ * @{
+ */
+#define UC3C0 (	\
+		AVR32_PART_IS_DEFINED(UC3C064C)  || \
+		AVR32_PART_IS_DEFINED(UC3C0128C) || \
+		AVR32_PART_IS_DEFINED(UC3C0256C) || \
+		AVR32_PART_IS_DEFINED(UC3C0512C) \
+		)
+
+#define UC3C1 (	\
+		AVR32_PART_IS_DEFINED(UC3C164C)  || \
+		AVR32_PART_IS_DEFINED(UC3C1128C) || \
+		AVR32_PART_IS_DEFINED(UC3C1256C) || \
+		AVR32_PART_IS_DEFINED(UC3C1512C) \
+		)
+
+#define UC3C2 (	\
+		AVR32_PART_IS_DEFINED(UC3C264C)  || \
+		AVR32_PART_IS_DEFINED(UC3C2128C) || \
+		AVR32_PART_IS_DEFINED(UC3C2256C) || \
+		AVR32_PART_IS_DEFINED(UC3C2512C) \
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 D series
+ * @{
+ */
+#define UC3D3 (	\
+		AVR32_PART_IS_DEFINED(UC64D3)  || \
+		AVR32_PART_IS_DEFINED(UC128D3) \
+		)
+
+#define UC3D4 (	\
+		AVR32_PART_IS_DEFINED(UC64D4)  || \
+		AVR32_PART_IS_DEFINED(UC128D4) \
+		)
+/** @} */
+
+/**
+ * \name AVR UC3 L series
+ * @{
+ */
+#define UC3L0 (	\
+		AVR32_PART_IS_DEFINED(UC3L016) || \
+		AVR32_PART_IS_DEFINED(UC3L032) || \
+		AVR32_PART_IS_DEFINED(UC3L064) \
+		)
+
+#define UC3L0128 ( \
+		AVR32_PART_IS_DEFINED(UC3L0128)	\
+		)
+
+#define UC3L0256 ( \
+		AVR32_PART_IS_DEFINED(UC3L0256)	\
+		)
+
+#define UC3L3 (	\
+		AVR32_PART_IS_DEFINED(UC64L3U)  || \
+		AVR32_PART_IS_DEFINED(UC128L3U) || \
+		AVR32_PART_IS_DEFINED(UC256L3U)	\
+		)
+
+#define UC3L4 (	\
+		AVR32_PART_IS_DEFINED(UC64L4U)  || \
+		AVR32_PART_IS_DEFINED(UC128L4U) || \
+		AVR32_PART_IS_DEFINED(UC256L4U)	\
+		)
+
+#define UC3L3_L4 (UC3L3 || UC3L4)
+/** @} */
+
+/**
+ * \name AVR UC3 families
+ * @{
+ */
+/** AVR UC3 A family */
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
+
+/** AVR UC3 B family */
+#define UC3B (UC3B0 || UC3B1)
+
+/** AVR UC3 C family */
+#define UC3C (UC3C0 || UC3C1 || UC3C2)
+
+/** AVR UC3 D family */
+#define UC3D (UC3D3 || UC3D4)
+
+/** AVR UC3 L family */
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
+/** @} */
+
+/** AVR UC3 product line */
+#define UC3  (UC3A || UC3B || UC3C || UC3D || UC3L)
+
+/** @} */
+
+/**
+ * \defgroup xmega_part_macros_group AVR XMEGA parts
+ * @{
+ */
+
+/**
+ * \name AVR XMEGA A series
+ * @{
+ */
+#define XMEGA_A1 ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A1)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A1) \
+		)
+
+#define XMEGA_A3 ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A3) || \
+		AVR8_PART_IS_DEFINED(ATxmega192A3) || \
+		AVR8_PART_IS_DEFINED(ATxmega256A3) \
+		)
+
+#define XMEGA_A3B ( \
+		AVR8_PART_IS_DEFINED(ATxmega256A3B) \
+		)
+
+#define XMEGA_A4 ( \
+		AVR8_PART_IS_DEFINED(ATxmega16A4) || \
+		AVR8_PART_IS_DEFINED(ATxmega32A4) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA AU series
+ * @{
+ */
+#define XMEGA_A1U ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A1U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A1U) \
+		)
+
+#define XMEGA_A3U ( \
+		AVR8_PART_IS_DEFINED(ATxmega64A3U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
+		AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
+		AVR8_PART_IS_DEFINED(ATxmega256A3U) \
+		)
+
+#define XMEGA_A3BU ( \
+		AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
+		)
+
+#define XMEGA_A4U ( \
+		AVR8_PART_IS_DEFINED(ATxmega16A4U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega32A4U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64A4U)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128A4U) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA B series
+ * @{
+ */
+#define XMEGA_B1  ( \
+		AVR8_PART_IS_DEFINED(ATxmega64B1)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128B1) \
+		)
+
+#define XMEGA_B3  ( \
+		AVR8_PART_IS_DEFINED(ATxmega64B3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128B3) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA C series
+ * @{
+ */
+#define XMEGA_C3 ( \
+		AVR8_PART_IS_DEFINED(ATxmega384C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega256C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega192C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128C3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64C3)   || \
+		AVR8_PART_IS_DEFINED(ATxmega32C3) \
+		)
+
+#define XMEGA_C4 ( \
+		AVR8_PART_IS_DEFINED(ATxmega32C4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega16C4) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA D series
+ * @{
+ */
+#define XMEGA_D3 ( \
+		AVR8_PART_IS_DEFINED(ATxmega32D3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64D3)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128D3) || \
+		AVR8_PART_IS_DEFINED(ATxmega192D3) || \
+		AVR8_PART_IS_DEFINED(ATxmega256D3) || \
+		AVR8_PART_IS_DEFINED(ATxmega384D3) \
+		)
+
+#define XMEGA_D4 ( \
+		AVR8_PART_IS_DEFINED(ATxmega16D4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega32D4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega64D4)  || \
+		AVR8_PART_IS_DEFINED(ATxmega128D4) \
+		)
+/** @} */
+
+/**
+ * \name AVR XMEGA E series
+ * @{
+ */
+#define XMEGA_E5 ( \
+		AVR8_PART_IS_DEFINED(ATxmega8E5)   || \
+		AVR8_PART_IS_DEFINED(ATxmega16E5)  || \
+		AVR8_PART_IS_DEFINED(ATxmega32E5)     \
+	)
+/** @} */
+
+
+/**
+ * \name AVR XMEGA families
+ * @{
+ */
+/** AVR XMEGA A family */
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
+
+/** AVR XMEGA AU family */
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
+
+/** AVR XMEGA B family */
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
+
+/** AVR XMEGA C family */
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
+
+/** AVR XMEGA D family */
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
+
+/** AVR XMEGA E family */
+#define XMEGA_E (XMEGA_E5)
+/** @} */
+
+
+/** AVR XMEGA product line */
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
+
+/** @} */
+
+/**
+ * \defgroup mega_part_macros_group megaAVR parts
+ *
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the
+ * part header files. They are not names of official megaAVR device series or
+ * families.
+ *
+ * @{
+ */
+
+/**
+ * \name ATmegaxx0/xx1 subgroups
+ * @{
+ */
+#define MEGA_XX0 ( \
+		AVR8_PART_IS_DEFINED(ATmega640)  || \
+		AVR8_PART_IS_DEFINED(ATmega1280) || \
+		AVR8_PART_IS_DEFINED(ATmega2560) \
+		)
+
+#define MEGA_XX1 ( \
+		AVR8_PART_IS_DEFINED(ATmega1281) || \
+		AVR8_PART_IS_DEFINED(ATmega2561) \
+		)
+/** @} */
+
+/**
+ * \name megaAVR groups
+ * @{
+ */
+/** ATmegaxx0/xx1 group */
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
+
+/** ATmegaxx4 group */
+#define MEGA_XX4 ( \
+		AVR8_PART_IS_DEFINED(ATmega164A)  || \
+		AVR8_PART_IS_DEFINED(ATmega164PA) || \
+		AVR8_PART_IS_DEFINED(ATmega324A)  || \
+		AVR8_PART_IS_DEFINED(ATmega324PA) || \
+		AVR8_PART_IS_DEFINED(ATmega324PB) || \
+		AVR8_PART_IS_DEFINED(ATmega644)   || \
+		AVR8_PART_IS_DEFINED(ATmega644A)  || \
+		AVR8_PART_IS_DEFINED(ATmega644PA) || \
+		AVR8_PART_IS_DEFINED(ATmega1284P)   || \
+		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+		)
+
+/** ATmegaxx4 group */
+#define MEGA_XX4_A ( \
+		AVR8_PART_IS_DEFINED(ATmega164A)  || \
+		AVR8_PART_IS_DEFINED(ATmega164PA) || \
+		AVR8_PART_IS_DEFINED(ATmega324A)  || \
+		AVR8_PART_IS_DEFINED(ATmega324PA) || \
+		AVR8_PART_IS_DEFINED(ATmega644A)  || \
+		AVR8_PART_IS_DEFINED(ATmega644PA) || \
+		AVR8_PART_IS_DEFINED(ATmega1284P) \
+		)
+
+/** ATmegaxx8 group */
+#define MEGA_XX8 ( \
+		AVR8_PART_IS_DEFINED(ATmega48)    || \
+		AVR8_PART_IS_DEFINED(ATmega48A)   || \
+		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega48PB)  || \
+		AVR8_PART_IS_DEFINED(ATmega88)    || \
+		AVR8_PART_IS_DEFINED(ATmega88A)   || \
+		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega88PB)  || \
+		AVR8_PART_IS_DEFINED(ATmega168)   || \
+		AVR8_PART_IS_DEFINED(ATmega168A)  || \
+		AVR8_PART_IS_DEFINED(ATmega168PA) || \
+		AVR8_PART_IS_DEFINED(ATmega168PB) || \
+		AVR8_PART_IS_DEFINED(ATmega328)   || \
+		AVR8_PART_IS_DEFINED(ATmega328P)  || \
+		AVR8_PART_IS_DEFINED(ATmega328PB) \
+		)
+
+/** ATmegaxx8A/P/PA group */
+#define MEGA_XX8_A ( \
+		AVR8_PART_IS_DEFINED(ATmega48A)   || \
+		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega88A)   || \
+		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
+		AVR8_PART_IS_DEFINED(ATmega168A)  || \
+		AVR8_PART_IS_DEFINED(ATmega168PA) || \
+		AVR8_PART_IS_DEFINED(ATmega328P) \
+		)
+
+/** ATmegaxx group */
+#define MEGA_XX ( \
+		AVR8_PART_IS_DEFINED(ATmega16)   || \
+		AVR8_PART_IS_DEFINED(ATmega16A)  || \
+		AVR8_PART_IS_DEFINED(ATmega32)   || \
+		AVR8_PART_IS_DEFINED(ATmega32A)  || \
+		AVR8_PART_IS_DEFINED(ATmega64)   || \
+		AVR8_PART_IS_DEFINED(ATmega64A)  || \
+		AVR8_PART_IS_DEFINED(ATmega128)  || \
+		AVR8_PART_IS_DEFINED(ATmega128A) \
+		)
+
+/** ATmegaxxA/P/PA group */
+#define MEGA_XX_A ( \
+		AVR8_PART_IS_DEFINED(ATmega16A)  || \
+		AVR8_PART_IS_DEFINED(ATmega32A)  || \
+		AVR8_PART_IS_DEFINED(ATmega64A)  || \
+		AVR8_PART_IS_DEFINED(ATmega128A) \
+		)
+/** ATmegaxxRFA1 group */
+#define MEGA_RFA1 ( \
+		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+		)
+
+/** ATmegaxxRFR2 group */
+#define MEGA_RFR2 ( \
+		AVR8_PART_IS_DEFINED(ATmega64RFR2)   || \
+		AVR8_PART_IS_DEFINED(ATmega128RFR2)  || \
+		AVR8_PART_IS_DEFINED(ATmega256RFR2)  || \
+		AVR8_PART_IS_DEFINED(ATmega644RFR2)  || \
+		AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
+		AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
+		)
+
+
+/** ATmegaxxRFxx group */
+#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
+
+/**
+ * \name ATmegaxx_un0/un1/un2 subgroups
+ * @{
+ */
+#define MEGA_XX_UN0 ( \
+		AVR8_PART_IS_DEFINED(ATmega16)    || \
+		AVR8_PART_IS_DEFINED(ATmega16A)   || \
+		AVR8_PART_IS_DEFINED(ATmega32)    || \
+		AVR8_PART_IS_DEFINED(ATmega32A)	\
+		)
+
+/** ATmegaxx group without power reduction and
+ *  And interrupt sense register.
+ */
+#define MEGA_XX_UN1 ( \
+		AVR8_PART_IS_DEFINED(ATmega64)    || \
+		AVR8_PART_IS_DEFINED(ATmega64A)   || \
+		AVR8_PART_IS_DEFINED(ATmega128)   || \
+		AVR8_PART_IS_DEFINED(ATmega128A) \
+		)
+
+/** ATmegaxx group without power reduction and
+ *  And interrupt sense register.
+ */
+#define MEGA_XX_UN2 ( \
+		AVR8_PART_IS_DEFINED(ATmega169P)  || \
+		AVR8_PART_IS_DEFINED(ATmega169PA) || \
+		AVR8_PART_IS_DEFINED(ATmega329P)  || \
+		AVR8_PART_IS_DEFINED(ATmega329PA) \
+		)
+
+/** Devices added to complete megaAVR offering.
+ *  Please do not use this group symbol as it is not intended
+ *  to be permanent: the devices should be regrouped.
+ */
+#define MEGA_UNCATEGORIZED ( \
+		AVR8_PART_IS_DEFINED(AT90CAN128)     || \
+		AVR8_PART_IS_DEFINED(AT90CAN32)      || \
+		AVR8_PART_IS_DEFINED(AT90CAN64)      || \
+		AVR8_PART_IS_DEFINED(AT90PWM1)       || \
+		AVR8_PART_IS_DEFINED(AT90PWM216)     || \
+		AVR8_PART_IS_DEFINED(AT90PWM2B)      || \
+		AVR8_PART_IS_DEFINED(AT90PWM316)     || \
+		AVR8_PART_IS_DEFINED(AT90PWM3B)      || \
+		AVR8_PART_IS_DEFINED(AT90PWM81)      || \
+		AVR8_PART_IS_DEFINED(AT90USB1286)    || \
+		AVR8_PART_IS_DEFINED(AT90USB1287)    || \
+		AVR8_PART_IS_DEFINED(AT90USB162)     || \
+		AVR8_PART_IS_DEFINED(AT90USB646)     || \
+		AVR8_PART_IS_DEFINED(AT90USB647)     || \
+		AVR8_PART_IS_DEFINED(AT90USB82)      || \
+		AVR8_PART_IS_DEFINED(ATmega1284)     || \
+		AVR8_PART_IS_DEFINED(ATmega162)      || \
+		AVR8_PART_IS_DEFINED(ATmega164P)     || \
+		AVR8_PART_IS_DEFINED(ATmega165A)     || \
+		AVR8_PART_IS_DEFINED(ATmega165P)     || \
+		AVR8_PART_IS_DEFINED(ATmega165PA)    || \
+		AVR8_PART_IS_DEFINED(ATmega168P)     || \
+		AVR8_PART_IS_DEFINED(ATmega169A)     || \
+		AVR8_PART_IS_DEFINED(ATmega16M1)     || \
+		AVR8_PART_IS_DEFINED(ATmega16U2)     || \
+		AVR8_PART_IS_DEFINED(ATmega16U4)     || \
+		AVR8_PART_IS_DEFINED(ATmega256RFA2)  || \
+		AVR8_PART_IS_DEFINED(ATmega324P)     || \
+		AVR8_PART_IS_DEFINED(ATmega325)      || \
+		AVR8_PART_IS_DEFINED(ATmega3250)     || \
+		AVR8_PART_IS_DEFINED(ATmega3250A)    || \
+		AVR8_PART_IS_DEFINED(ATmega3250P)    || \
+		AVR8_PART_IS_DEFINED(ATmega3250PA)   || \
+		AVR8_PART_IS_DEFINED(ATmega325A)     || \
+		AVR8_PART_IS_DEFINED(ATmega325P)     || \
+		AVR8_PART_IS_DEFINED(ATmega325PA)    || \
+		AVR8_PART_IS_DEFINED(ATmega329)      || \
+		AVR8_PART_IS_DEFINED(ATmega3290)     || \
+		AVR8_PART_IS_DEFINED(ATmega3290A)    || \
+		AVR8_PART_IS_DEFINED(ATmega3290P)    || \
+		AVR8_PART_IS_DEFINED(ATmega3290PA)   || \
+		AVR8_PART_IS_DEFINED(ATmega329A)     || \
+		AVR8_PART_IS_DEFINED(ATmega32M1)     || \
+		AVR8_PART_IS_DEFINED(ATmega32U2)     || \
+		AVR8_PART_IS_DEFINED(ATmega32U4)     || \
+		AVR8_PART_IS_DEFINED(ATmega48P)      || \
+		AVR8_PART_IS_DEFINED(ATmega644P)     || \
+		AVR8_PART_IS_DEFINED(ATmega645)      || \
+		AVR8_PART_IS_DEFINED(ATmega6450)     || \
+		AVR8_PART_IS_DEFINED(ATmega6450A)    || \
+		AVR8_PART_IS_DEFINED(ATmega6450P)    || \
+		AVR8_PART_IS_DEFINED(ATmega645A)     || \
+		AVR8_PART_IS_DEFINED(ATmega645P)     || \
+		AVR8_PART_IS_DEFINED(ATmega649)      || \
+		AVR8_PART_IS_DEFINED(ATmega6490)     || \
+		AVR8_PART_IS_DEFINED(ATmega6490A)    || \
+		AVR8_PART_IS_DEFINED(ATmega6490P)    || \
+		AVR8_PART_IS_DEFINED(ATmega649A)     || \
+		AVR8_PART_IS_DEFINED(ATmega649P)     || \
+		AVR8_PART_IS_DEFINED(ATmega64M1)     || \
+		AVR8_PART_IS_DEFINED(ATmega64RFA2)   || \
+		AVR8_PART_IS_DEFINED(ATmega8)        || \
+		AVR8_PART_IS_DEFINED(ATmega8515)     || \
+		AVR8_PART_IS_DEFINED(ATmega8535)     || \
+		AVR8_PART_IS_DEFINED(ATmega88P)      || \
+		AVR8_PART_IS_DEFINED(ATmega8A)       || \
+		AVR8_PART_IS_DEFINED(ATmega8U2)         \
+	)
+
+/** Unspecified group */
+#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
+	MEGA_UNCATEGORIZED)
+
+/** @} */
+
+/** megaAVR product line */
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
+	MEGA_UNSPECIFIED)
+
+/** @} */
+
+/**
+ * \defgroup sam_part_macros_group SAM parts
+ * @{
+ */
+
+/**
+ * \name SAM3S series
+ * @{
+ */
+#define SAM3S1 ( \
+		SAM_PART_IS_DEFINED(SAM3S1A) ||	\
+		SAM_PART_IS_DEFINED(SAM3S1B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S1C) \
+		)
+
+#define SAM3S2 ( \
+		SAM_PART_IS_DEFINED(SAM3S2A) ||	\
+		SAM_PART_IS_DEFINED(SAM3S2B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S2C) \
+		)
+
+#define SAM3S4 ( \
+		SAM_PART_IS_DEFINED(SAM3S4A) ||	\
+		SAM_PART_IS_DEFINED(SAM3S4B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S4C) \
+		)
+
+#define SAM3S8 ( \
+		SAM_PART_IS_DEFINED(SAM3S8B) ||	\
+		SAM_PART_IS_DEFINED(SAM3S8C) \
+		)
+
+#define SAM3SD8 ( \
+		SAM_PART_IS_DEFINED(SAM3SD8B) || \
+		SAM_PART_IS_DEFINED(SAM3SD8C) \
+		)
+/** @} */
+
+/**
+ * \name SAM3U series
+ * @{
+ */
+#define SAM3U1 ( \
+		SAM_PART_IS_DEFINED(SAM3U1C) ||	\
+		SAM_PART_IS_DEFINED(SAM3U1E) \
+		)
+
+#define SAM3U2 ( \
+		SAM_PART_IS_DEFINED(SAM3U2C) ||	\
+		SAM_PART_IS_DEFINED(SAM3U2E) \
+		)
+
+#define SAM3U4 ( \
+		SAM_PART_IS_DEFINED(SAM3U4C) ||	\
+		SAM_PART_IS_DEFINED(SAM3U4E) \
+		)
+/** @} */
+
+/**
+ * \name SAM3N series
+ * @{
+ */
+#define SAM3N00 ( \
+		SAM_PART_IS_DEFINED(SAM3N00A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N00B) \
+		)
+
+#define SAM3N0 ( \
+		SAM_PART_IS_DEFINED(SAM3N0A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N0B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N0C) \
+		)
+
+#define SAM3N1 ( \
+		SAM_PART_IS_DEFINED(SAM3N1A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N1B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N1C) \
+		)
+
+#define SAM3N2 ( \
+		SAM_PART_IS_DEFINED(SAM3N2A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N2B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N2C) \
+		)
+
+#define SAM3N4 ( \
+		SAM_PART_IS_DEFINED(SAM3N4A) ||	\
+		SAM_PART_IS_DEFINED(SAM3N4B) ||	\
+		SAM_PART_IS_DEFINED(SAM3N4C) \
+		)
+/** @} */
+
+/**
+ * \name SAM3X series
+ * @{
+ */
+#define SAM3X4 ( \
+		SAM_PART_IS_DEFINED(SAM3X4C) ||	\
+		SAM_PART_IS_DEFINED(SAM3X4E) \
+		)
+
+#define SAM3X8 ( \
+		SAM_PART_IS_DEFINED(SAM3X8C) ||	\
+		SAM_PART_IS_DEFINED(SAM3X8E) ||	\
+		SAM_PART_IS_DEFINED(SAM3X8H) \
+		)
+/** @} */
+
+/**
+ * \name SAM3A series
+ * @{
+ */
+#define SAM3A4 ( \
+		SAM_PART_IS_DEFINED(SAM3A4C) \
+		)
+
+#define SAM3A8 ( \
+		SAM_PART_IS_DEFINED(SAM3A8C) \
+		)
+/** @} */
+
+/**
+ * \name SAM4S series
+ * @{
+ */
+#define SAM4S2 ( \
+		SAM_PART_IS_DEFINED(SAM4S2A) || \
+ 		SAM_PART_IS_DEFINED(SAM4S2B) || \
+ 		SAM_PART_IS_DEFINED(SAM4S2C) \
+ 		)
+
+#define SAM4S4 ( \
+		SAM_PART_IS_DEFINED(SAM4S4A) || \
+ 		SAM_PART_IS_DEFINED(SAM4S4B) || \
+ 		SAM_PART_IS_DEFINED(SAM4S4C) \
+ 		)
+
+#define SAM4S8 ( \
+		SAM_PART_IS_DEFINED(SAM4S8B) ||	\
+		SAM_PART_IS_DEFINED(SAM4S8C) \
+		)
+
+#define SAM4S16 ( \
+		SAM_PART_IS_DEFINED(SAM4S16B) || \
+		SAM_PART_IS_DEFINED(SAM4S16C) \
+		)
+
+#define SAM4SA16 ( \
+		SAM_PART_IS_DEFINED(SAM4SA16B) || \
+		SAM_PART_IS_DEFINED(SAM4SA16C)    \
+	)
+
+#define SAM4SD16 ( \
+		SAM_PART_IS_DEFINED(SAM4SD16B) || \
+		SAM_PART_IS_DEFINED(SAM4SD16C)    \
+	)
+
+#define SAM4SD32 ( \
+		SAM_PART_IS_DEFINED(SAM4SD32B) || \
+		SAM_PART_IS_DEFINED(SAM4SD32C)    \
+	)
+/** @} */
+
+/**
+ * \name SAM4L series
+ * @{
+ */
+#define SAM4LS ( \
+		SAM_PART_IS_DEFINED(SAM4LS2A) || \
+		SAM_PART_IS_DEFINED(SAM4LS2B) || \
+		SAM_PART_IS_DEFINED(SAM4LS2C) || \
+		SAM_PART_IS_DEFINED(SAM4LS4A) || \
+		SAM_PART_IS_DEFINED(SAM4LS4B) || \
+		SAM_PART_IS_DEFINED(SAM4LS4C) || \
+		SAM_PART_IS_DEFINED(SAM4LS8A) || \
+		SAM_PART_IS_DEFINED(SAM4LS8B) || \
+		SAM_PART_IS_DEFINED(SAM4LS8C)    \
+		)
+
+#define SAM4LC ( \
+		SAM_PART_IS_DEFINED(SAM4LC2A) || \
+		SAM_PART_IS_DEFINED(SAM4LC2B) || \
+		SAM_PART_IS_DEFINED(SAM4LC2C) || \
+		SAM_PART_IS_DEFINED(SAM4LC4A) || \
+		SAM_PART_IS_DEFINED(SAM4LC4B) || \
+		SAM_PART_IS_DEFINED(SAM4LC4C) || \
+		SAM_PART_IS_DEFINED(SAM4LC8A) || \
+		SAM_PART_IS_DEFINED(SAM4LC8B) || \
+		SAM_PART_IS_DEFINED(SAM4LC8C)    \
+		)
+/** @} */
+
+/**
+ * \name SAMD20 series
+ * @{
+ */
+#define SAMD20J ( \
+		SAM_PART_IS_DEFINED(SAMD20J14) || \
+		SAM_PART_IS_DEFINED(SAMD20J15) || \
+		SAM_PART_IS_DEFINED(SAMD20J16) || \
+		SAM_PART_IS_DEFINED(SAMD20J14B) || \
+		SAM_PART_IS_DEFINED(SAMD20J15B) || \
+		SAM_PART_IS_DEFINED(SAMD20J16B) || \
+		SAM_PART_IS_DEFINED(SAMD20J17) || \
+		SAM_PART_IS_DEFINED(SAMD20J18) \
+	)
+
+#define SAMD20G ( \
+		SAM_PART_IS_DEFINED(SAMD20G14)  || \
+		SAM_PART_IS_DEFINED(SAMD20G15)  || \
+		SAM_PART_IS_DEFINED(SAMD20G16)  || \
+		SAM_PART_IS_DEFINED(SAMD20G14B)  || \
+		SAM_PART_IS_DEFINED(SAMD20G15B)  || \
+		SAM_PART_IS_DEFINED(SAMD20G16B)  || \
+		SAM_PART_IS_DEFINED(SAMD20G17)  || \
+		SAM_PART_IS_DEFINED(SAMD20G17U) || \
+		SAM_PART_IS_DEFINED(SAMD20G18)  || \
+		SAM_PART_IS_DEFINED(SAMD20G18U) \
+	)
+
+#define SAMD20E ( \
+		SAM_PART_IS_DEFINED(SAMD20E14) || \
+		SAM_PART_IS_DEFINED(SAMD20E15) || \
+		SAM_PART_IS_DEFINED(SAMD20E16) || \
+		SAM_PART_IS_DEFINED(SAMD20E14B) || \
+		SAM_PART_IS_DEFINED(SAMD20E15B) || \
+		SAM_PART_IS_DEFINED(SAMD20E16B) || \
+		SAM_PART_IS_DEFINED(SAMD20E17) || \
+		SAM_PART_IS_DEFINED(SAMD20E18) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMD21 series
+ * @{
+ */
+#define SAMD21J ( \
+		SAM_PART_IS_DEFINED(SAMD21J15A) || \
+		SAM_PART_IS_DEFINED(SAMD21J16A) || \
+		SAM_PART_IS_DEFINED(SAMD21J17A) || \
+		SAM_PART_IS_DEFINED(SAMD21J18A) || \
+		SAM_PART_IS_DEFINED(SAMD21J15B) || \
+		SAM_PART_IS_DEFINED(SAMD21J16B) || \
+		SAM_PART_IS_DEFINED(SAMD21J17D) \
+	)
+
+#define SAMD21G ( \
+		SAM_PART_IS_DEFINED(SAMD21G15A) || \
+		SAM_PART_IS_DEFINED(SAMD21G16A) || \
+		SAM_PART_IS_DEFINED(SAMD21G17A) || \
+		SAM_PART_IS_DEFINED(SAMD21G17AU) || \
+		SAM_PART_IS_DEFINED(SAMD21G18A) || \
+		SAM_PART_IS_DEFINED(SAMD21G18AU) || \
+		SAM_PART_IS_DEFINED(SAMD21G15B) || \
+		SAM_PART_IS_DEFINED(SAMD21G16B) || \
+		SAM_PART_IS_DEFINED(SAMD21G15L) || \
+		SAM_PART_IS_DEFINED(SAMD21G16L) || \
+		SAM_PART_IS_DEFINED(SAMD21G17D) || \
+		SAM_PART_IS_DEFINED(SAMD21G17L) \
+	)
+
+#define SAMD21GXXL ( \
+		SAM_PART_IS_DEFINED(SAMD21G15L) || \
+		SAM_PART_IS_DEFINED(SAMD21G16L) || \
+		SAM_PART_IS_DEFINED(SAMD21G17L) \
+		)
+
+#define SAMD21E ( \
+		SAM_PART_IS_DEFINED(SAMD21E15A) || \
+		SAM_PART_IS_DEFINED(SAMD21E16A) || \
+		SAM_PART_IS_DEFINED(SAMD21E17A) || \
+		SAM_PART_IS_DEFINED(SAMD21E18A) || \
+		SAM_PART_IS_DEFINED(SAMD21E15B) || \
+		SAM_PART_IS_DEFINED(SAMD21E15BU) || \
+		SAM_PART_IS_DEFINED(SAMD21E16B) || \
+		SAM_PART_IS_DEFINED(SAMD21E16BU) || \
+		SAM_PART_IS_DEFINED(SAMD21E15L) || \
+		SAM_PART_IS_DEFINED(SAMD21E16L) || \
+		SAM_PART_IS_DEFINED(SAMD21E17D) || \
+		SAM_PART_IS_DEFINED(SAMD21E17DU) || \
+		SAM_PART_IS_DEFINED(SAMD21E17L) \
+	)
+
+#define SAMD21EXXL ( \
+		SAM_PART_IS_DEFINED(SAMD21E15L) || \
+		SAM_PART_IS_DEFINED(SAMD21E16L) || \
+		SAM_PART_IS_DEFINED(SAMD21E17L) \
+		)
+
+/** @} */
+
+/**
+ * \name SAMR21 series
+ * @{
+ */
+#define SAMR21G ( \
+		SAM_PART_IS_DEFINED(SAMR21G16A) || \
+		SAM_PART_IS_DEFINED(SAMR21G17A) || \
+		SAM_PART_IS_DEFINED(SAMR21G18A) \
+	)
+
+#define SAMR21E ( \
+		SAM_PART_IS_DEFINED(SAMR21E16A) || \
+		SAM_PART_IS_DEFINED(SAMR21E17A) || \
+		SAM_PART_IS_DEFINED(SAMR21E18A) || \
+		SAM_PART_IS_DEFINED(SAMR21E19A) \
+	)
+/** @} */
+
+/**
+ * \name SAMR30 series
+ * @{
+ */
+#define SAMR30G ( \
+		SAM_PART_IS_DEFINED(SAMR30G18A) \
+	)
+
+#define SAMR30E ( \
+		SAM_PART_IS_DEFINED(SAMR30E18A) \
+	)
+/** @} */
+
+/**
+ * \name SAMR34 series
+ * @{
+ */
+#define SAMR34J ( \
+		SAM_PART_IS_DEFINED(SAMR34J18A) || \
+		SAM_PART_IS_DEFINED(SAMR34J17A) || \
+		SAM_PART_IS_DEFINED(SAMR34J16A) || \
+		SAM_PART_IS_DEFINED(SAMR34J18B) || \
+		SAM_PART_IS_DEFINED(SAMR34J17B) || \
+		SAM_PART_IS_DEFINED(SAMR34J16B) \
+	)
+	
+/* Group for SAMR34 A variant: SAMR34J [16/17/18]A */
+#define SAMR34JXXA ( \
+		SAM_PART_IS_DEFINED(SAMR34J18A) || \
+		SAM_PART_IS_DEFINED(SAMR34J17A) || \
+		SAM_PART_IS_DEFINED(SAMR34J16A) \
+)
+/* Group for SAMR34 B variant: SAMR34J [16/17/18]B */
+#define SAMR34JXXB ( \
+		SAM_PART_IS_DEFINED(SAMR34J18B) || \
+		SAM_PART_IS_DEFINED(SAMR34J17B) || \
+		SAM_PART_IS_DEFINED(SAMR34J16B) \
+)
+
+/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */
+#define SAMR35J ( \
+		SAM_PART_IS_DEFINED(SAMR35J18B) || \
+		SAM_PART_IS_DEFINED(SAMR35J17B) || \
+		SAM_PART_IS_DEFINED(SAMR35J16B) \
+)
+/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */
+#define SAMR35JXXB ( \
+		SAM_PART_IS_DEFINED(SAMR35J18B) || \
+		SAM_PART_IS_DEFINED(SAMR35J17B) || \
+		SAM_PART_IS_DEFINED(SAMR35J16B) \
+)
+
+/**
+ * \name SAMB11 series
+ * @{
+ */
+#define SAMB11G ( \
+		SAM_PART_IS_DEFINED(SAMB11G18A) || \
+		SAM_PART_IS_DEFINED(SAMB11ZR) \
+	)
+#define BTLC1000 ( \
+		SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMD09 series
+ * @{
+ */
+#define SAMD09C ( \
+		SAM_PART_IS_DEFINED(SAMD09C13A) \
+	)
+
+#define SAMD09D ( \
+		SAM_PART_IS_DEFINED(SAMD09D14A) \
+	)
+/** @} */
+
+/**
+ * \name SAMD10 series
+ * @{
+ */
+#define SAMD10C ( \
+		SAM_PART_IS_DEFINED(SAMD10C12A) || \
+		SAM_PART_IS_DEFINED(SAMD10C13A) || \
+		SAM_PART_IS_DEFINED(SAMD10C14A) \
+	)
+
+#define SAMD10DS ( \
+		SAM_PART_IS_DEFINED(SAMD10D12AS) || \
+		SAM_PART_IS_DEFINED(SAMD10D13AS) || \
+		SAM_PART_IS_DEFINED(SAMD10D14AS) \
+	)
+
+#define SAMD10DM ( \
+		SAM_PART_IS_DEFINED(SAMD10D12AM) || \
+		SAM_PART_IS_DEFINED(SAMD10D13AM) || \
+		SAM_PART_IS_DEFINED(SAMD10D14AM) \
+	)
+
+#define SAMD10DU ( \
+		SAM_PART_IS_DEFINED(SAMD10D14AU) \
+	)
+/** @} */
+
+/**
+ * \name SAMD11 series
+ * @{
+ */
+#define SAMD11C ( \
+		SAM_PART_IS_DEFINED(SAMD11C14A) \
+	)
+
+#define SAMD11DS ( \
+		SAM_PART_IS_DEFINED(SAMD11D14AS) \
+	)
+
+#define SAMD11DM ( \
+		SAM_PART_IS_DEFINED(SAMD11D14AM) \
+	)
+
+#define SAMD11DU ( \
+		SAM_PART_IS_DEFINED(SAMD11D14AU) \
+	)
+/** @} */
+
+/**
+ * \name SAML21 series
+ * @{
+ */
+#define SAML21E ( \
+		SAM_PART_IS_DEFINED(SAML21E18A) || \
+		SAM_PART_IS_DEFINED(SAML21E15B) || \
+		SAM_PART_IS_DEFINED(SAML21E16B) || \
+		SAM_PART_IS_DEFINED(SAML21E17B) || \
+		SAM_PART_IS_DEFINED(SAML21E18B) \
+	)
+
+#define SAML21G ( \
+		SAM_PART_IS_DEFINED(SAML21G18A) || \
+		SAM_PART_IS_DEFINED(SAML21G16B) || \
+		SAM_PART_IS_DEFINED(SAML21G17B) || \
+		SAM_PART_IS_DEFINED(SAML21G18B) \
+	)
+
+#define SAML21J ( \
+		SAM_PART_IS_DEFINED(SAML21J18A) || \
+		SAM_PART_IS_DEFINED(SAML21J16B) || \
+		SAM_PART_IS_DEFINED(SAML21J17B) || \
+		SAM_PART_IS_DEFINED(SAML21J18B) \
+	)
+
+/* Group for SAML21 A variant: SAML21[E/G/J][18]A */
+#define SAML21XXXA ( \
+		SAM_PART_IS_DEFINED(SAML21E18A) || \
+		SAM_PART_IS_DEFINED(SAML21G18A) || \
+		SAM_PART_IS_DEFINED(SAML21J18A) \
+	)
+
+/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */
+#define SAML21XXXB ( \
+		SAM_PART_IS_DEFINED(SAML21E15B) || \
+		SAM_PART_IS_DEFINED(SAML21E16B) || \
+		SAM_PART_IS_DEFINED(SAML21E17B) || \
+		SAM_PART_IS_DEFINED(SAML21E18B) || \
+		SAM_PART_IS_DEFINED(SAML21G16B) || \
+		SAM_PART_IS_DEFINED(SAML21G17B) || \
+		SAM_PART_IS_DEFINED(SAML21G18B) || \
+		SAM_PART_IS_DEFINED(SAML21J16B) || \
+		SAM_PART_IS_DEFINED(SAML21J17B) || \
+		SAM_PART_IS_DEFINED(SAML21J18B) \
+	)
+
+/** @} */
+
+/**
+ * \name SAML22 series
+ * @{
+ */
+#define SAML22N ( \
+		SAM_PART_IS_DEFINED(SAML22N16A) || \
+		SAM_PART_IS_DEFINED(SAML22N17A) || \
+		SAM_PART_IS_DEFINED(SAML22N18A) \
+	)
+
+#define SAML22G ( \
+		SAM_PART_IS_DEFINED(SAML22G16A) || \
+		SAM_PART_IS_DEFINED(SAML22G17A) || \
+		SAM_PART_IS_DEFINED(SAML22G18A) \
+	)
+
+#define SAML22J ( \
+		SAM_PART_IS_DEFINED(SAML22J16A) || \
+		SAM_PART_IS_DEFINED(SAML22J17A) || \
+		SAM_PART_IS_DEFINED(SAML22J18A) \
+	)
+/** @} */
+
+/**
+ * \name SAMDA1 series
+ * @{
+ */
+#define SAMDA1J ( \
+		SAM_PART_IS_DEFINED(SAMDA1J14A) || \
+		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1J15A) || \
+		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1J16A) || \
+		SAM_PART_IS_DEFINED(SAMDA1J16B) \
+	)
+
+#define SAMDA1G ( \
+		SAM_PART_IS_DEFINED(SAMDA1G14A) || \
+		SAM_PART_IS_DEFINED(SAMDA1G14B) || \
+		SAM_PART_IS_DEFINED(SAMDA1G15A) || \
+		SAM_PART_IS_DEFINED(SAMDA1G15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1G16A) || \
+		SAM_PART_IS_DEFINED(SAMDA1G16B) \
+	)
+
+#define SAMDA1E ( \
+		SAM_PART_IS_DEFINED(SAMDA1E14A) || \
+		SAM_PART_IS_DEFINED(SAMDA1E14B) || \
+		SAM_PART_IS_DEFINED(SAMDA1E15A) || \
+		SAM_PART_IS_DEFINED(SAMDA1E15B) || \
+		SAM_PART_IS_DEFINED(SAMDA1E16A) || \
+		SAM_PART_IS_DEFINED(SAMDA1E16B) \
+	)
+/** @} */
+
+/**
+ * \name SAMHA1 series
+ * @{
+ */
+#define SAMHA1G ( \
+		SAM_PART_IS_DEFINED(SAMHA1G14A) || \
+		SAM_PART_IS_DEFINED(SAMHA1G15A) || \
+		SAM_PART_IS_DEFINED(SAMHA1G16A) || \
+		SAM_PART_IS_DEFINED(SAMHA1G14AB) || \
+		SAM_PART_IS_DEFINED(SAMHA1G15AB) || \
+		SAM_PART_IS_DEFINED(SAMHA1G16AB) \
+	)
+
+#define SAMHA1E ( \
+		SAM_PART_IS_DEFINED(SAMHA1E14A) || \
+		SAM_PART_IS_DEFINED(SAMHA1E15A) || \
+		SAM_PART_IS_DEFINED(SAMHA1E16A) || \
+		SAM_PART_IS_DEFINED(SAMHA1E14AB) || \
+		SAM_PART_IS_DEFINED(SAMHA1E15AB) || \
+		SAM_PART_IS_DEFINED(SAMHA1E16AB) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMHA0 series
+ * @{
+ */
+#define SAMHA0G ( \
+		SAM_PART_IS_DEFINED(SAMHA0G14AB) || \
+		SAM_PART_IS_DEFINED(SAMHA0G15AB) || \
+		SAM_PART_IS_DEFINED(SAMHA0G16AB) \
+	)
+
+#define SAMHA0E ( \
+		SAM_PART_IS_DEFINED(SAMHA0E14AB) || \
+		SAM_PART_IS_DEFINED(SAMHA0E15AB) || \
+		SAM_PART_IS_DEFINED(SAMHA0E16AB) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMC20 series
+ * @{
+ */
+#define SAMC20E ( \
+		SAM_PART_IS_DEFINED(SAMC20E15A) || \
+		SAM_PART_IS_DEFINED(SAMC20E16A) || \
+		SAM_PART_IS_DEFINED(SAMC20E17A) || \
+		SAM_PART_IS_DEFINED(SAMC20E18A) \
+	)
+
+#define SAMC20G ( \
+		SAM_PART_IS_DEFINED(SAMC20G15A) || \
+		SAM_PART_IS_DEFINED(SAMC20G16A) || \
+		SAM_PART_IS_DEFINED(SAMC20G17A) || \
+		SAM_PART_IS_DEFINED(SAMC20G18A) \
+	)
+
+#define SAMC20J ( \
+		SAM_PART_IS_DEFINED(SAMC20J15A) || \
+		SAM_PART_IS_DEFINED(SAMC20J16A) || \
+		SAM_PART_IS_DEFINED(SAMC20J17A) || \
+		SAM_PART_IS_DEFINED(SAMC20J18A) \
+	)
+/** @} */
+
+/**
+ * \name SAMC21 series
+ * @{
+ */
+#define SAMC21E ( \
+		SAM_PART_IS_DEFINED(SAMC21E15A) || \
+		SAM_PART_IS_DEFINED(SAMC21E16A) || \
+		SAM_PART_IS_DEFINED(SAMC21E17A) || \
+		SAM_PART_IS_DEFINED(SAMC21E18A) \
+	)
+
+#define SAMC21G ( \
+		SAM_PART_IS_DEFINED(SAMC21G15A) || \
+		SAM_PART_IS_DEFINED(SAMC21G16A) || \
+		SAM_PART_IS_DEFINED(SAMC21G17A) || \
+		SAM_PART_IS_DEFINED(SAMC21G18A) \
+	)
+
+#define SAMC21J ( \
+		SAM_PART_IS_DEFINED(SAMC21J15A) || \
+		SAM_PART_IS_DEFINED(SAMC21J16A) || \
+		SAM_PART_IS_DEFINED(SAMC21J17A) || \
+		SAM_PART_IS_DEFINED(SAMC21J18A) \
+	)
+/** @} */
+
+/**
+ * \name SAM4E series
+ * @{
+ */
+#define SAM4E8 ( \
+		SAM_PART_IS_DEFINED(SAM4E8C) || \
+		SAM_PART_IS_DEFINED(SAM4E8CB) || \
+		SAM_PART_IS_DEFINED(SAM4E8E) \
+		)
+
+#define SAM4E16 ( \
+		SAM_PART_IS_DEFINED(SAM4E16C) || \
+		SAM_PART_IS_DEFINED(SAM4E16CB) || \
+		SAM_PART_IS_DEFINED(SAM4E16E) \
+		)
+/** @} */
+
+/**
+ * \name SAM4N series
+ * @{
+ */
+#define SAM4N8 ( \
+		SAM_PART_IS_DEFINED(SAM4N8A) || \
+		SAM_PART_IS_DEFINED(SAM4N8B) || \
+		SAM_PART_IS_DEFINED(SAM4N8C) \
+		)
+
+#define SAM4N16 ( \
+		SAM_PART_IS_DEFINED(SAM4N16B) || \
+		SAM_PART_IS_DEFINED(SAM4N16C) \
+		)
+/** @} */
+
+/**
+ * \name SAM4C series
+ * @{
+ */
+#define SAM4C4_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C4C_0) \
+		)
+
+#define SAM4C4_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C4C_1) \
+		)
+
+#define SAM4C4 (SAM4C4_0 || SAM4C4_1)
+
+#define SAM4C8_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C8C_0) \
+		)
+
+#define SAM4C8_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C8C_1) \
+		)
+
+#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
+
+#define SAM4C16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C16C_0) \
+		)
+
+#define SAM4C16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C16C_1) \
+		)
+
+#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
+
+#define SAM4C32_0 ( \
+		SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
+		SAM_PART_IS_DEFINED(SAM4C32E_0) \
+		)
+
+#define SAM4C32_1 ( \
+		SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
+		SAM_PART_IS_DEFINED(SAM4C32E_1) \
+		)
+
+
+#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CM series
+ * @{
+ */
+#define SAM4CMP8_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
+		)
+
+#define SAM4CMP8_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
+		)
+
+#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
+
+#define SAM4CMP16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
+		)
+
+#define SAM4CMP16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
+		)
+
+#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
+
+#define SAM4CMP32_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
+		)
+
+#define SAM4CMP32_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
+		)
+
+#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
+
+#define SAM4CMS4_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
+		)
+
+#define SAM4CMS4_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
+		)
+
+#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1)
+
+#define SAM4CMS8_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
+		)
+
+#define SAM4CMS8_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
+		)
+
+#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
+
+#define SAM4CMS16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
+		)
+
+#define SAM4CMS16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
+		)
+
+#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
+
+#define SAM4CMS32_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
+		)
+
+#define SAM4CMS32_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
+		)
+
+#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CP series
+ * @{
+ */
+#define SAM4CP16_0 ( \
+		SAM_PART_IS_DEFINED(SAM4CP16B_0) \
+		)
+
+#define SAM4CP16_1 ( \
+		SAM_PART_IS_DEFINED(SAM4CP16B_1) \
+		)
+
+#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
+/** @} */
+
+/**
+ * \name SAMG series
+ * @{
+ */
+#define SAMG51 ( \
+		SAM_PART_IS_DEFINED(SAMG51G18) \
+		)
+
+#define SAMG53 ( \
+		SAM_PART_IS_DEFINED(SAMG53G19) ||\
+		SAM_PART_IS_DEFINED(SAMG53N19) \
+		)
+
+#define SAMG54 ( \
+		SAM_PART_IS_DEFINED(SAMG54G19) ||\
+		SAM_PART_IS_DEFINED(SAMG54J19) ||\
+		SAM_PART_IS_DEFINED(SAMG54N19) \
+		)
+
+#define SAMG55 ( \
+		SAM_PART_IS_DEFINED(SAMG55G18) ||\
+		SAM_PART_IS_DEFINED(SAMG55G19) ||\
+		SAM_PART_IS_DEFINED(SAMG55J18) ||\
+		SAM_PART_IS_DEFINED(SAMG55J19) ||\
+		SAM_PART_IS_DEFINED(SAMG55N19) \
+		)
+/** @} */
+
+/**
+ * \name SAMV71 series
+ * @{
+ */
+#define SAMV71J ( \
+		SAM_PART_IS_DEFINED(SAMV71J19) || \
+		SAM_PART_IS_DEFINED(SAMV71J20) || \
+		SAM_PART_IS_DEFINED(SAMV71J21) \
+	)
+
+#define SAMV71JB ( \
+		SAM_PART_IS_DEFINED(SAMV71J19B) || \
+		SAM_PART_IS_DEFINED(SAMV71J20B) || \
+		SAM_PART_IS_DEFINED(SAMV71J21B) \
+	)
+
+#define SAMV71N ( \
+		SAM_PART_IS_DEFINED(SAMV71N19) || \
+		SAM_PART_IS_DEFINED(SAMV71N20) || \
+		SAM_PART_IS_DEFINED(SAMV71N21) \
+	)
+
+#define SAMV71NB ( \
+		SAM_PART_IS_DEFINED(SAMV71N19B) || \
+		SAM_PART_IS_DEFINED(SAMV71N20B) || \
+		SAM_PART_IS_DEFINED(SAMV71N21B) \
+	)
+
+#define SAMV71Q ( \
+		SAM_PART_IS_DEFINED(SAMV71Q19) || \
+		SAM_PART_IS_DEFINED(SAMV71Q20) || \
+		SAM_PART_IS_DEFINED(SAMV71Q21) \
+	)
+
+#define SAMV71QB ( \
+		SAM_PART_IS_DEFINED(SAMV71Q19B) || \
+		SAM_PART_IS_DEFINED(SAMV71Q20B) || \
+		SAM_PART_IS_DEFINED(SAMV71Q21B) \
+	)
+
+/** @} */
+
+/**
+ * \name SAMV70 series
+ * @{
+ */
+#define SAMV70J ( \
+		SAM_PART_IS_DEFINED(SAMV70J19) || \
+		SAM_PART_IS_DEFINED(SAMV70J20) \
+	)
+
+#define SAMV70JB ( \
+		SAM_PART_IS_DEFINED(SAMV70J19B) || \
+		SAM_PART_IS_DEFINED(SAMV70J20B) \
+	)
+
+#define SAMV70N ( \
+		SAM_PART_IS_DEFINED(SAMV70N19) || \
+		SAM_PART_IS_DEFINED(SAMV70N20) \
+	)
+
+#define SAMV70NB ( \
+		SAM_PART_IS_DEFINED(SAMV70N19B) || \
+		SAM_PART_IS_DEFINED(SAMV70N20B) \
+	)
+
+#define SAMV70Q ( \
+		SAM_PART_IS_DEFINED(SAMV70Q19) || \
+		SAM_PART_IS_DEFINED(SAMV70Q20) \
+	)
+#define SAMV70QB ( \
+		SAM_PART_IS_DEFINED(SAMV70Q19B) || \
+		SAM_PART_IS_DEFINED(SAMV70Q20B) \
+	)
+/** @} */
+
+/**
+ * \name SAMS70 series
+ * @{
+ */
+#define SAMS70J ( \
+		SAM_PART_IS_DEFINED(SAMS70J19) || \
+		SAM_PART_IS_DEFINED(SAMS70J20) || \
+		SAM_PART_IS_DEFINED(SAMS70J21) \
+	)
+
+#define SAMS70JB ( \
+		SAM_PART_IS_DEFINED(SAMS70J19B) || \
+		SAM_PART_IS_DEFINED(SAMS70J20B) || \
+		SAM_PART_IS_DEFINED(SAMS70J21B) \
+	)
+
+#define SAMS70N ( \
+		SAM_PART_IS_DEFINED(SAMS70N19) || \
+		SAM_PART_IS_DEFINED(SAMS70N20) || \
+		SAM_PART_IS_DEFINED(SAMS70N21) \
+	)
+
+#define SAMS70NB ( \
+		SAM_PART_IS_DEFINED(SAMS70N19B) || \
+		SAM_PART_IS_DEFINED(SAMS70N20B) || \
+		SAM_PART_IS_DEFINED(SAMS70N21B) \
+	)
+
+#define SAMS70Q ( \
+		SAM_PART_IS_DEFINED(SAMS70Q19) || \
+		SAM_PART_IS_DEFINED(SAMS70Q20) || \
+		SAM_PART_IS_DEFINED(SAMS70Q21) \
+	)
+
+#define SAMS70QB ( \
+		SAM_PART_IS_DEFINED(SAMS70Q19B) || \
+		SAM_PART_IS_DEFINED(SAMS70Q20B) || \
+		SAM_PART_IS_DEFINED(SAMS70Q21B) \
+	)
+/** @} */
+
+/**
+ * \name SAME70 series
+ * @{
+ */
+#define SAME70J ( \
+		SAM_PART_IS_DEFINED(SAME70J19) || \
+		SAM_PART_IS_DEFINED(SAME70J20) || \
+		SAM_PART_IS_DEFINED(SAME70J21) \
+	)
+
+#define SAME70JB ( \
+		SAM_PART_IS_DEFINED(SAME70J19B) || \
+		SAM_PART_IS_DEFINED(SAME70J20B) || \
+		SAM_PART_IS_DEFINED(SAME70J21B) \
+	)
+
+#define SAME70N ( \
+		SAM_PART_IS_DEFINED(SAME70N19) || \
+		SAM_PART_IS_DEFINED(SAME70N20) || \
+		SAM_PART_IS_DEFINED(SAME70N21) \
+	)
+
+#define SAME70NB ( \
+		SAM_PART_IS_DEFINED(SAME70N19B) || \
+		SAM_PART_IS_DEFINED(SAME70N20B) || \
+		SAM_PART_IS_DEFINED(SAME70N21B) \
+	)
+
+#define SAME70Q ( \
+		SAM_PART_IS_DEFINED(SAME70Q19) || \
+		SAM_PART_IS_DEFINED(SAME70Q20) || \
+		SAM_PART_IS_DEFINED(SAME70Q21)  \
+	)
+
+#define SAME70QB ( \
+		SAM_PART_IS_DEFINED(SAME70Q19B) || \
+		SAM_PART_IS_DEFINED(SAME70Q20B) || \
+		SAM_PART_IS_DEFINED(SAME70Q21B) \
+	)
+/** @} */
+
+/**
+ * \name SAM families
+ * @{
+ */
+/** SAM3S Family */
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
+
+/** SAM3U Family */
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
+
+/** SAM3N Family */
+#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
+
+/** SAM3XA Family */
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
+
+/** SAM4S Family */
+#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
+
+/** SAM4L Family */
+#define SAM4L (SAM4LS || SAM4LC)
+
+/** SAMD20 Family */
+#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
+
+/** SAMD21 Family */
+#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
+
+/** SAMD09 Family */
+#define SAMD09 (SAMD09C || SAMD09D)
+
+/** SAMD10 Family */
+#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU)
+
+/** SAMD11 Family */
+#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU)
+
+/** SAMDA1 Family */
+#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E)
+
+/** SAMHA1 Family */
+#define SAMHA1 (SAMHA1G || SAMHA1E)
+
+/** SAMHA0 Family */
+#define SAMHA0 (SAMHA0G || SAMHA0E)
+
+/** SAMD Family */
+#define SAMD   (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1)
+
+/** SAMR21 Family */
+#define SAMR21 (SAMR21G || SAMR21E)
+
+/** SAMR30 Family */
+#define SAMR30 (SAMR30G || SAMR30E)
+
+/** SAMR34 Family */
+#define SAMR34 (SAMR34J)
+
+/** SAMR35 Family */
+#define SAMR35 (SAMR35J)
+
+/** SAMB11 Family */
+#define SAMB11 (SAMB11G || BTLC1000)
+
+/** SAML21 Family */
+#define SAML21 (SAML21J || SAML21G || SAML21E)
+
+/** SAML22 Family */
+#define SAML22 (SAML22J || SAML22G || SAML22N)
+/** SAMC20 Family */
+#define SAMC20 (SAMC20J || SAMC20G || SAMC20E)
+
+/** SAMC21 Family */
+#define SAMC21 (SAMC21J || SAMC21G || SAMC21E)
+
+/** SAM4E Family */
+#define SAM4E (SAM4E8 || SAM4E16)
+
+/** SAM4N Family */
+#define SAM4N (SAM4N8 || SAM4N16)
+
+/** SAM4C Family */
+#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
+#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
+#define SAM4C   (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32)
+
+/** SAM4CM Family */
+#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \
+			SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
+#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \
+			SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
+#define SAM4CM   (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \
+			SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
+
+/** SAM4CP Family */
+#define SAM4CP_0 (SAM4CP16_0)
+#define SAM4CP_1 (SAM4CP16_1)
+#define SAM4CP   (SAM4CP16)
+
+/** SAMG Family */
+#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55)
+
+/** SAMB Family */
+#define SAMB (SAMB11)
+
+/** SAMV71 Family */
+#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q || SAMV71JB || SAMV71NB || SAMV71QB)
+#define SAMV71B (SAMV71JB || SAMV71NB || SAMV71QB)
+
+/** SAMV70 Family */
+#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q || SAMV70JB || SAMV70NB || SAMV70QB)
+#define SAMV70B (SAMV70JB || SAMV70NB || SAMV70QB)
+
+/** SAME70 Family */
+#define SAME70 (SAME70J || SAME70N || SAME70Q || SAME70JB || SAME70NB || SAME70QB)
+#define SAME70B (SAME70JB || SAME70NB || SAME70QB)
+
+/** SAMS70 Family */
+#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q || SAMS70JB || SAMS70NB || SAMS70QB)
+#define SAMS70B (SAMS70JB || SAMS70NB || SAMS70QB)
+
+/** SAM0 product line (cortex-m0+) */
+#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\
+		SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1 ||\
+		SAMHA0 || SAMR34 || SAMR35)
+
+/** @} */
+
+/** SAM product line */
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
+		SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* ATMEL_PARTS_H */
diff --git a/D21_ADC_with_DMA/src/ASF/common2/services/delay/delay.h b/D21_ADC_with_DMA/src/ASF/common2/services/delay/delay.h
index ad7a533..2b227de 100644
--- a/D21_ADC_with_DMA/src/ASF/common2/services/delay/delay.h
+++ b/D21_ADC_with_DMA/src/ASF/common2/services/delay/delay.h
@@ -1,91 +1,91 @@
-/**
- * \file
- *
- * \brief Common Delay Service
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef DELAY_H_INCLUDED
-#define DELAY_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup group_common_services_delay Busy-Wait Delay Routines
- *
- * This module provides simple loop-based delay routines for those
- * applications requiring a brief wait during execution. Common for
- * API ver. 2.
- *
- * @{
- */
-
-#ifdef SYSTICK_MODE
-#include "sam0/systick_counter.h"
-#endif
-#ifdef CYCLE_MODE
-#include "sam0/cycle_counter.h"
-#endif
-
-void delay_init(void);
-
-/**
- * \def delay_s
- * \brief Delay in at least specified number of seconds.
- * \param delay Delay in seconds
- */
-#define delay_s(delay)          ((delay) ? cpu_delay_s(delay) : cpu_delay_us(1))
-
-/**
- * \def delay_ms
- * \brief Delay in at least specified number of milliseconds.
- * \param delay Delay in milliseconds
- */
-#define delay_ms(delay)         ((delay) ? cpu_delay_ms(delay) : cpu_delay_us(1))
-
-/**
- * \def delay_us
- * \brief Delay in at least specified number of microseconds.
- * \param delay Delay in microseconds
- */
-#define delay_us(delay)         ((delay) ? cpu_delay_us(delay) : cpu_delay_us(1))
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* DELAY_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief Common Delay Service
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef DELAY_H_INCLUDED
+#define DELAY_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup group_common_services_delay Busy-Wait Delay Routines
+ *
+ * This module provides simple loop-based delay routines for those
+ * applications requiring a brief wait during execution. Common for
+ * API ver. 2.
+ *
+ * @{
+ */
+
+#ifdef SYSTICK_MODE
+#include "sam0/systick_counter.h"
+#endif
+#ifdef CYCLE_MODE
+#include "sam0/cycle_counter.h"
+#endif
+
+void delay_init(void);
+
+/**
+ * \def delay_s
+ * \brief Delay in at least specified number of seconds.
+ * \param delay Delay in seconds
+ */
+#define delay_s(delay)          ((delay) ? cpu_delay_s(delay) : cpu_delay_us(1))
+
+/**
+ * \def delay_ms
+ * \brief Delay in at least specified number of milliseconds.
+ * \param delay Delay in milliseconds
+ */
+#define delay_ms(delay)         ((delay) ? cpu_delay_ms(delay) : cpu_delay_us(1))
+
+/**
+ * \def delay_us
+ * \brief Delay in at least specified number of microseconds.
+ * \param delay Delay in microseconds
+ */
+#define delay_us(delay)         ((delay) ? cpu_delay_us(delay) : cpu_delay_us(1))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* DELAY_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.c b/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.c
index 736d052..495dc48 100644
--- a/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.c
+++ b/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.c
@@ -1,86 +1,86 @@
-/**
- * \file
- *
- * \brief ARM functions for busy-wait delay loops
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "delay.h"
-
-/**
- * Value used to calculate ms delay. Default to be used with a 8MHz clock;
- */
-static uint32_t cycles_per_ms = 8000000UL / 1000;
-static uint32_t cycles_per_us = 8000000UL / 1000000;
-
-/**
- * \brief Initialize the delay driver.
- *
- * This must be called during start up to initialize the delay routine with
- * the current used main clock. It must run any time the main CPU clock is changed.
- */
-void delay_init(void)
-{
-	cycles_per_ms = system_gclk_gen_get_hz(0);
-	cycles_per_ms /= 1000;
-	cycles_per_us = cycles_per_ms / 1000;
-
-	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-}
-
-/**
- * \brief Delay loop to delay at least n number of microseconds
- *
- * \param n  Number of microseconds to wait
- */
-void delay_cycles_us(
-		uint32_t n)
-{
-	while (n--) {
-		/* Devide up to blocks of 10u */
-		delay_cycles(cycles_per_us);
-	}
-}
-
-/**
- * \brief Delay loop to delay at least n number of milliseconds
- *
- * \param n  Number of milliseconds to wait
- */
-void delay_cycles_ms(
-		uint32_t n)
-{
-	while (n--) {
-		/* Devide up to blocks of 1ms */
-		delay_cycles(cycles_per_ms);
-	}
-}
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "delay.h"
+
+/**
+ * Value used to calculate ms delay. Default to be used with a 8MHz clock;
+ */
+static uint32_t cycles_per_ms = 8000000UL / 1000;
+static uint32_t cycles_per_us = 8000000UL / 1000000;
+
+/**
+ * \brief Initialize the delay driver.
+ *
+ * This must be called during start up to initialize the delay routine with
+ * the current used main clock. It must run any time the main CPU clock is changed.
+ */
+void delay_init(void)
+{
+	cycles_per_ms = system_gclk_gen_get_hz(0);
+	cycles_per_ms /= 1000;
+	cycles_per_us = cycles_per_ms / 1000;
+
+	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * \brief Delay loop to delay at least n number of microseconds
+ *
+ * \param n  Number of microseconds to wait
+ */
+void delay_cycles_us(
+		uint32_t n)
+{
+	while (n--) {
+		/* Devide up to blocks of 10u */
+		delay_cycles(cycles_per_us);
+	}
+}
+
+/**
+ * \brief Delay loop to delay at least n number of milliseconds
+ *
+ * \param n  Number of milliseconds to wait
+ */
+void delay_cycles_ms(
+		uint32_t n)
+{
+	while (n--) {
+		/* Devide up to blocks of 1ms */
+		delay_cycles(cycles_per_ms);
+	}
+}
diff --git a/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.h b/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.h
index 3f37b9f..903908d 100644
--- a/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.h
+++ b/D21_ADC_with_DMA/src/ASF/common2/services/delay/sam0/systick_counter.h
@@ -1,103 +1,103 @@
-/**
- * \file
- *
- * \brief ARM functions for busy-wait delay loops
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef CYCLE_COUNTER_H_INCLUDED
-#define CYCLE_COUNTER_H_INCLUDED
-
-#include <compiler.h>
-#include <clock.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name Convenience functions for busy-wait delay loops
- *
- * @{
- */
-
-/**
- * \brief Delay loop to delay n number of cycles
- * Delay program execution for at least the specified number of CPU cycles.
- *
- * \param n  Number of cycles to delay
- */
-static inline void delay_cycles(
-		const uint32_t n)
-{
-	if (n > 0) {
-		SysTick->LOAD = n;
-		SysTick->VAL = 0;
-
-		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
-		};
-	}
-}
-
-void delay_cycles_us(uint32_t n);
-
-void delay_cycles_ms(uint32_t n);
-
-/**
- * \brief Delay program execution for at least the specified number of microseconds.
- *
- * \param delay  number of microseconds to wait
- */
-#define cpu_delay_us(delay)      delay_cycles_us(delay)
-
-/**
- * \brief Delay program execution for at least the specified number of milliseconds.
- *
- * \param delay  number of milliseconds to wait
- */
-#define cpu_delay_ms(delay)      delay_cycles_ms(delay)
-
-/**
- * \brief Delay program execution for at least the specified number of seconds.
- *
- * \param delay  number of seconds to wait
- */
-#define cpu_delay_s(delay)       delay_cycles_ms(1000 * delay)
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CYCLE_COUNTER_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef CYCLE_COUNTER_H_INCLUDED
+#define CYCLE_COUNTER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Convenience functions for busy-wait delay loops
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ * Delay program execution for at least the specified number of CPU cycles.
+ *
+ * \param n  Number of cycles to delay
+ */
+static inline void delay_cycles(
+		const uint32_t n)
+{
+	if (n > 0) {
+		SysTick->LOAD = n;
+		SysTick->VAL = 0;
+
+		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
+		};
+	}
+}
+
+void delay_cycles_us(uint32_t n);
+
+void delay_cycles_ms(uint32_t n);
+
+/**
+ * \brief Delay program execution for at least the specified number of microseconds.
+ *
+ * \param delay  number of microseconds to wait
+ */
+#define cpu_delay_us(delay)      delay_cycles_us(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of milliseconds.
+ *
+ * \param delay  number of milliseconds to wait
+ */
+#define cpu_delay_ms(delay)      delay_cycles_ms(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of seconds.
+ *
+ * \param delay  number of seconds to wait
+ */
+#define cpu_delay_s(delay)       delay_cycles_ms(1000 * delay)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CYCLE_COUNTER_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c b/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
index 2d36580..a4f5d2b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
@@ -1,80 +1,80 @@
-/**
- * \file
- *
- * \brief SAM D21 Xplained Pro board initialization
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include <compiler.h>
-#include <board.h>
-#include <conf_board.h>
-#include <port.h>
-
-#if defined(__GNUC__)
-void board_init(void) WEAK __attribute__((alias("system_board_init")));
-#elif defined(__ICCARM__)
-void board_init(void);
-#  pragma weak board_init=system_board_init
-#endif
-
-void system_board_init(void)
-{
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
-
-	/* Configure LEDs as outputs, turn them off */
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(LED_0_PIN, &pin_conf);
-	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
-
-	/* Set buttons as inputs */
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	pin_conf.input_pull = PORT_PIN_PULL_UP;
-	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
-	
-#ifdef CONF_BOARD_AT86RFX
-	port_get_config_defaults(&pin_conf);
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
-	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
-	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
-	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
-	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
-	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
-	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
-	port_pin_set_output_level(AT86RFX_SPI_CS, true);
-	port_pin_set_output_level(AT86RFX_RST_PIN, true);
-	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
-#endif	
-}
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board initialization
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <port.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(LED_0_PIN, &pin_conf);
+	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+	/* Set buttons as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+	
+#ifdef CONF_BOARD_AT86RFX
+	port_get_config_defaults(&pin_conf);
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+	port_pin_set_output_level(AT86RFX_SPI_CS, true);
+	port_pin_set_output_level(AT86RFX_RST_PIN, true);
+	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+#endif	
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h b/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
index f166cde..c5984c9 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
@@ -1,699 +1,699 @@
-/**
- * \file
- *
- * \brief SAM D21 Xplained Pro board definition
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
-#define SAMD21_XPLAINED_PRO_H_INCLUDED
-
-#include <conf_board.h>
-#include <compiler.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \ingroup group_common_boards
- * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
- *
- * @{
- */
-
-void system_board_init(void);
-
-/**
- * \defgroup samd21_xplained_pro_features_group Features
- *
- * Symbols that describe features and capabilities of the board.
- *
- * @{
- */
-
-/** Name string macro */
-#define BOARD_NAME                "SAMD21_XPLAINED_PRO"
-
-/** \name Resonator definitions
- *  @{ */
-#define BOARD_FREQ_SLCK_XTAL      (32768U)
-#define BOARD_FREQ_SLCK_BYPASS    (32768U)
-#define BOARD_FREQ_MAINCK_XTAL    0 /* Not Mounted */
-#define BOARD_FREQ_MAINCK_BYPASS  0 /* Not Mounted */
-#define BOARD_MCK                 CHIP_FREQ_CPU_MAX
-#define BOARD_OSC_STARTUP_US      15625
-/** @} */
-
-/** \name LED0 definitions
- *  @{ */
-#define LED0_PIN                  PIN_PB30
-#define LED0_ACTIVE               false
-#define LED0_INACTIVE             !LED0_ACTIVE
-/** @} */
-
-/** \name SW0 definitions
- *  @{ */
-#define SW0_PIN                   PIN_PA15
-#define SW0_ACTIVE                false
-#define SW0_INACTIVE              !SW0_ACTIVE
-#define SW0_EIC_PIN               PIN_PA15A_EIC_EXTINT15
-#define SW0_EIC_MUX               MUX_PA15A_EIC_EXTINT15
-#define SW0_EIC_PINMUX            PINMUX_PA15A_EIC_EXTINT15
-#define SW0_EIC_LINE              15
-/** @} */
-
-/**
- * \name LED #0 definitions
- *
- * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
- * boards.
- *
- *  @{ */
-#define LED_0_NAME                "LED0 (yellow)"
-#define LED_0_PIN                 LED0_PIN
-#define LED_0_ACTIVE              LED0_ACTIVE
-#define LED_0_INACTIVE            LED0_INACTIVE
-#define LED0_GPIO                 LED0_PIN
-#define LED0                      LED0_PIN
-
-#define LED_0_PWM4CTRL_MODULE     TCC0
-#define LED_0_PWM4CTRL_CHANNEL    0
-#define LED_0_PWM4CTRL_OUTPUT     0
-#define LED_0_PWM4CTRL_PIN        PIN_PB30E_TCC0_WO0
-#define LED_0_PWM4CTRL_MUX        MUX_PB30E_TCC0_WO0
-#define LED_0_PWM4CTRL_PINMUX     PINMUX_PB30E_TCC0_WO0
-/** @} */
-
-/** Number of on-board LEDs */
-#define LED_COUNT                 1
-
-/**
- * \name Serialflash definitions
- *
- * On board Serialflash definitions.
- *
- *  @{ */
-#define SERIALFLASH_SPI_MODULE      SERCOM5
-#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
-#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
-#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
-#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
-#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
-#define SERIALFLASH_SPI_CS PIN_PA13
-/** @} */
-
-/**
- * \name Button #0 definitions
- *
- * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
- * boards.
- *
- *  @{ */
-#define BUTTON_0_NAME             "SW0"
-#define BUTTON_0_PIN              SW0_PIN
-#define BUTTON_0_ACTIVE           SW0_ACTIVE
-#define BUTTON_0_INACTIVE         SW0_INACTIVE
-#define BUTTON_0_EIC_PIN          SW0_EIC_PIN
-#define BUTTON_0_EIC_MUX          SW0_EIC_MUX
-#define BUTTON_0_EIC_PINMUX       SW0_EIC_PINMUX
-#define BUTTON_0_EIC_LINE         SW0_EIC_LINE
-/** @} */
-
-/** Number of on-board buttons */
-#define BUTTON_COUNT 1
-
-/** \name Extension header #1 pin definitions
- *  @{
- */
-#define EXT1_PIN_3                PIN_PB00
-#define EXT1_PIN_4                PIN_PB01
-#define EXT1_PIN_5                PIN_PB06
-#define EXT1_PIN_6                PIN_PB07
-#define EXT1_PIN_7                PIN_PB02
-#define EXT1_PIN_8                PIN_PB03
-#define EXT1_PIN_9                PIN_PB04
-#define EXT1_PIN_10               PIN_PB05
-#define EXT1_PIN_11               PIN_PA08
-#define EXT1_PIN_12               PIN_PA09
-#define EXT1_PIN_13               PIN_PB09
-#define EXT1_PIN_14               PIN_PB08
-#define EXT1_PIN_15               PIN_PA05
-#define EXT1_PIN_16               PIN_PA06
-#define EXT1_PIN_17               PIN_PA04
-#define EXT1_PIN_18               PIN_PA07
-/** @} */
-
-/** \name Extension header #1 pin definitions by function
- *  @{
- */
-#define EXT1_PIN_ADC_0            EXT1_PIN_3
-#define EXT1_PIN_ADC_1            EXT1_PIN_4
-#define EXT1_PIN_GPIO_0           EXT1_PIN_5
-#define EXT1_PIN_GPIO_1           EXT1_PIN_6
-#define EXT1_PIN_PWM_0            EXT1_PIN_7
-#define EXT1_PIN_PWM_1            EXT1_PIN_8
-#define EXT1_PIN_IRQ              EXT1_PIN_9
-#define EXT1_PIN_I2C_SDA          EXT1_PIN_11
-#define EXT1_PIN_I2C_SCL          EXT1_PIN_12
-#define EXT1_PIN_UART_RX          EXT1_PIN_13
-#define EXT1_PIN_UART_TX          EXT1_PIN_14
-#define EXT1_PIN_SPI_SS_1         EXT1_PIN_10
-#define EXT1_PIN_SPI_SS_0         EXT1_PIN_15
-#define EXT1_PIN_SPI_MOSI         EXT1_PIN_16
-#define EXT1_PIN_SPI_MISO         EXT1_PIN_17
-#define EXT1_PIN_SPI_SCK          EXT1_PIN_18
-/** @} */
-
-/** \name Extension header #1 ADC definitions
- *  @{
- */
-#define EXT1_ADC_MODULE           ADC
-#define EXT1_ADC_0_CHANNEL        8
-#define EXT1_ADC_0_PIN            PIN_PB00B_ADC_AIN8
-#define EXT1_ADC_0_MUX            MUX_PB00B_ADC_AIN8
-#define EXT1_ADC_0_PINMUX         PINMUX_PB00B_ADC_AIN8
-#define EXT1_ADC_1_CHANNEL        9
-#define EXT1_ADC_1_PIN            PIN_PB01B_ADC_AIN9
-#define EXT1_ADC_1_MUX            MUX_PB01B_ADC_AIN9
-#define EXT1_ADC_1_PINMUX         PINMUX_PB01B_ADC_AIN9
-/** @} */
-
-/** \name Extension header #1 PWM definitions
- *  @{
- */
-#define EXT1_PWM_MODULE           TC6
-#define EXT1_PWM_0_CHANNEL        0
-#define EXT1_PWM_0_PIN            PIN_PB02E_TC6_WO0
-#define EXT1_PWM_0_MUX            MUX_PB02E_TC6_WO0
-#define EXT1_PWM_0_PINMUX         PINMUX_PB02E_TC6_WO0
-#define EXT1_PWM_1_CHANNEL        1
-#define EXT1_PWM_1_PIN            PIN_PB03E_TC6_WO1
-#define EXT1_PWM_1_MUX            MUX_PB03E_TC6_WO1
-#define EXT1_PWM_1_PINMUX         PINMUX_PB03E_TC6_WO1
-/** @} */
-
-/** \name Extension header #1 IRQ/External interrupt definitions
- *  @{
- */
-#define EXT1_IRQ_MODULE           EIC
-#define EXT1_IRQ_INPUT            4
-#define EXT1_IRQ_PIN              PIN_PB04A_EIC_EXTINT4
-#define EXT1_IRQ_MUX              MUX_PB04A_EIC_EXTINT4
-#define EXT1_IRQ_PINMUX           PINMUX_PB04A_EIC_EXTINT4
-/** @} */
-
-/** \name Extension header #1 I2C definitions
- *  @{
- */
-#define EXT1_I2C_MODULE              SERCOM2
-#define EXT1_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
-#define EXT1_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
-#define EXT1_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
-#define EXT1_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #1 UART definitions
- *  @{
- */
-#define EXT1_UART_MODULE              SERCOM4
-#define EXT1_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
-#define EXT1_UART_SERCOM_PINMUX_PAD0  PINMUX_PB08D_SERCOM4_PAD0
-#define EXT1_UART_SERCOM_PINMUX_PAD1  PINMUX_PB09D_SERCOM4_PAD1
-#define EXT1_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
-#define EXT1_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
-#define EXT1_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
-#define EXT1_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #1 SPI definitions
- *  @{
- */
-#define EXT1_SPI_MODULE              SERCOM0
-#define EXT1_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
-#define EXT1_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
-#define EXT1_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
-#define EXT1_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA06D_SERCOM0_PAD2
-#define EXT1_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA07D_SERCOM0_PAD3
-#define EXT1_SPI_SERCOM_DMAC_ID_TX   SERCOM0_DMAC_ID_TX
-#define EXT1_SPI_SERCOM_DMAC_ID_RX   SERCOM0_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #2 pin definitions
- *  @{
- */
-#define EXT2_PIN_3                PIN_PA10
-#define EXT2_PIN_4                PIN_PA11
-#define EXT2_PIN_5                PIN_PA20
-#define EXT2_PIN_6                PIN_PA21
-#define EXT2_PIN_7                PIN_PB12
-#define EXT2_PIN_8                PIN_PB13
-#define EXT2_PIN_9                PIN_PB14
-#define EXT2_PIN_10               PIN_PB15
-#define EXT2_PIN_11               PIN_PA08
-#define EXT2_PIN_12               PIN_PA09
-#define EXT2_PIN_13               PIN_PB11
-#define EXT2_PIN_14               PIN_PB10
-#define EXT2_PIN_15               PIN_PA17
-#define EXT2_PIN_16               PIN_PA18
-#define EXT2_PIN_17               PIN_PA16
-#define EXT2_PIN_18               PIN_PA19
-/** @} */
-
-/** \name Extension header #2 pin definitions by function
- *  @{
- */
-#define EXT2_PIN_ADC_0            EXT2_PIN_3
-#define EXT2_PIN_ADC_1            EXT2_PIN_4
-#define EXT2_PIN_GPIO_0           EXT2_PIN_5
-#define EXT2_PIN_GPIO_1           EXT2_PIN_6
-#define EXT2_PIN_PWM_0            EXT2_PIN_7
-#define EXT2_PIN_PWM_1            EXT2_PIN_8
-#define EXT2_PIN_IRQ              EXT2_PIN_9
-#define EXT2_PIN_I2C_SDA          EXT2_PIN_11
-#define EXT2_PIN_I2C_SCL          EXT2_PIN_12
-#define EXT2_PIN_UART_RX          EXT2_PIN_13
-#define EXT2_PIN_UART_TX          EXT2_PIN_14
-#define EXT2_PIN_SPI_SS_1         EXT2_PIN_10
-#define EXT2_PIN_SPI_SS_0         EXT2_PIN_15
-#define EXT2_PIN_SPI_MOSI         EXT2_PIN_16
-#define EXT2_PIN_SPI_MISO         EXT2_PIN_17
-#define EXT2_PIN_SPI_SCK          EXT2_PIN_18
-/** @} */
-
-/** \name Extension header #2 ADC definitions
- *  @{
- */
-#define EXT2_ADC_MODULE           ADC
-#define EXT2_ADC_0_CHANNEL        18
-#define EXT2_ADC_0_PIN            PIN_PA10B_ADC_AIN18
-#define EXT2_ADC_0_MUX            MUX_PA10B_ADC_AIN18
-#define EXT2_ADC_0_PINMUX         PINMUX_PA10B_ADC_AIN18
-#define EXT2_ADC_1_CHANNEL        19
-#define EXT2_ADC_1_PIN            PIN_PA11B_ADC_AIN19
-#define EXT2_ADC_1_MUX            MUX_PA11B_ADC_AIN19
-#define EXT2_ADC_1_PINMUX         PINMUX_PA11B_ADC_AIN19
-/** @} */
-
-/** \name Extension header #2 PWM definitions
- *  @{
- */
-#define EXT2_PWM_MODULE           TC4
-#define EXT2_PWM_0_CHANNEL        0
-#define EXT2_PWM_0_PIN            PIN_PB12E_TC4_WO0
-#define EXT2_PWM_0_MUX            MUX_PB12E_TC4_WO0
-#define EXT2_PWM_0_PINMUX         PINMUX_PB12E_TC4_WO0
-#define EXT2_PWM_1_CHANNEL        1
-#define EXT2_PWM_1_PIN            PIN_PB13E_TC4_WO1
-#define EXT2_PWM_1_MUX            MUX_PB13E_TC4_WO1
-#define EXT2_PWM_1_PINMUX         PINMUX_PB13E_TC4_WO1
-/** @} */
-
-/** \name Extension header #2 PWM for Control definitions
- *  @{
- */
-#define EXT2_PWM4CTRL_MODULE      TCC0
-#define EXT2_PWM4CTRL_0_CHANNEL   2
-#define EXT2_PWM4CTRL_0_OUTPUT    6
-#define EXT2_PWM4CTRL_0_PIN       PIN_PB12F_TCC0_WO6
-#define EXT2_PWM4CTRL_0_MUX       MUX_PB12F_TCC0_WO6
-#define EXT2_PWM4CTRL_0_PINMUX    PINMUX_PB12F_TCC0_WO6
-#define EXT2_PWM4CTRL_1_CHANNEL   3
-#define EXT2_PWM4CTRL_1_OUTPUT    7
-#define EXT2_PWM4CTRL_1_PIN       PIN_PB13F_TCC0_WO7
-#define EXT2_PWM4CTRL_1_MUX       MUX_PB13F_TCC0_WO7
-#define EXT2_PWM4CTRL_1_PINMUX    PINMUX_PB13F_TCC0_WO7
-/** @} */
-
-/** \name Extension header #2 IRQ/External interrupt definitions
- *  @{
- */
-#define EXT2_IRQ_MODULE           EIC
-#define EXT2_IRQ_INPUT            14
-#define EXT2_IRQ_PIN              PIN_PB14A_EIC_EXTINT14
-#define EXT2_IRQ_MUX              MUX_PB14A_EIC_EXTINT14
-#define EXT2_IRQ_PINMUX           PINMUX_PB14A_EIC_EXTINT14
-/** @} */
-
- /** \name Extension header #2 I2C definitions
- *  @{
- */
-#define EXT2_I2C_MODULE              SERCOM2
-#define EXT2_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
-#define EXT2_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
-#define EXT2_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
-#define EXT2_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #2 UART definitions
- *  @{
- */
-#define EXT2_UART_MODULE              SERCOM4
-#define EXT2_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
-#define EXT2_UART_SERCOM_PINMUX_PAD0  PINMUX_PB12C_SERCOM4_PAD0
-#define EXT2_UART_SERCOM_PINMUX_PAD1  PINMUX_PB13C_SERCOM4_PAD1
-#define EXT2_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
-#define EXT2_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
-#define EXT2_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
-#define EXT2_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #2 SPI definitions
- *  @{
- */
-#define EXT2_SPI_MODULE              SERCOM1
-#define EXT2_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
-#define EXT2_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
-#define EXT2_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
-#define EXT2_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA18C_SERCOM1_PAD2
-#define EXT2_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA19C_SERCOM1_PAD3
-#define EXT2_SPI_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
-#define EXT2_SPI_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #3 pin definitions
- *  @{
- */
-#define EXT3_PIN_3                PIN_PA02
-#define EXT3_PIN_4                PIN_PA03
-#define EXT3_PIN_5                PIN_PB30
-#define EXT3_PIN_6                PIN_PA15
-#define EXT3_PIN_7                PIN_PA12
-#define EXT3_PIN_8                PIN_PA13
-#define EXT3_PIN_9                PIN_PA28
-#define EXT3_PIN_10               PIN_PA27
-#define EXT3_PIN_11               PIN_PA08
-#define EXT3_PIN_12               PIN_PA09
-#define EXT3_PIN_13               PIN_PB11
-#define EXT3_PIN_14               PIN_PB10
-#define EXT3_PIN_15               PIN_PB17
-#define EXT3_PIN_16               PIN_PB22
-#define EXT3_PIN_17               PIN_PB16
-#define EXT3_PIN_18               PIN_PB23
-/** @} */
-
-/** \name Extension header #3 pin definitions by function
- *  @{
- */
-#define EXT3_PIN_ADC_0            EXT3_PIN_3
-#define EXT3_PIN_ADC_1            EXT3_PIN_4
-#define EXT3_PIN_GPIO_0           EXT3_PIN_5
-#define EXT3_PIN_GPIO_1           EXT3_PIN_6
-#define EXT3_PIN_PWM_0            EXT3_PIN_7
-#define EXT3_PIN_PWM_1            EXT3_PIN_8
-#define EXT3_PIN_IRQ              EXT3_PIN_9
-#define EXT3_PIN_I2C_SDA          EXT3_PIN_11
-#define EXT3_PIN_I2C_SCL          EXT3_PIN_12
-#define EXT3_PIN_UART_RX          EXT3_PIN_13
-#define EXT3_PIN_UART_TX          EXT3_PIN_14
-#define EXT3_PIN_SPI_SS_1         EXT3_PIN_10
-#define EXT3_PIN_SPI_SS_0         EXT3_PIN_15
-#define EXT3_PIN_SPI_MOSI         EXT3_PIN_16
-#define EXT3_PIN_SPI_MISO         EXT3_PIN_17
-#define EXT3_PIN_SPI_SCK          EXT3_PIN_18
-/** @} */
-
-/** \name Extension header #3 ADC definitions
- *  @{
- */
-#define EXT3_ADC_MODULE           ADC
-#define EXT3_ADC_0_CHANNEL        0
-#define EXT3_ADC_0_PIN            PIN_PA02B_ADC_AIN0
-#define EXT3_ADC_0_MUX            MUX_PA02B_ADC_AIN0
-#define EXT3_ADC_0_PINMUX         PINMUX_PA02B_ADC_AIN0
-#define EXT3_ADC_1_CHANNEL        1
-#define EXT3_ADC_1_PIN            PIN_PA03B_ADC_AIN1
-#define EXT3_ADC_1_MUX            MUX_PA03B_ADC_AIN1
-#define EXT3_ADC_1_PINMUX         PINMUX_PA03B_ADC_AIN1
-/** @} */
-
-/** \name Extension header #3 PWM for Control definitions
- *  @{
- */
-#define EXT3_PWM4CTRL_MODULE      TCC2
-#define EXT3_PWM4CTRL_0_CHANNEL   0
-#define EXT3_PWM4CTRL_0_OUTPUT    0
-#define EXT3_PWM4CTRL_0_PIN       PIN_PA12E_TCC2_WO0
-#define EXT3_PWM4CTRL_0_MUX       MUX_PA12E_TCC2_WO0
-#define EXT3_PWM4CTRL_0_PINMUX    PINMUX_PA12E_TCC2_WO0
-#define EXT3_PWM4CTRL_1_CHANNEL   1
-#define EXT3_PWM4CTRL_1_OUTPUT    1
-#define EXT3_PWM4CTRL_1_PIN       PIN_PA13E_TCC2_WO1
-#define EXT3_PWM4CTRL_1_MUX       MUX_PA13E_TCC2_WO1
-#define EXT3_PWM4CTRL_1_PINMUX    PINMUX_PA13E_TCC2_WO1
-/** @} */
-
-/** \name Extension header #3 IRQ/External interrupt definitions
- *  @{
- */
-#define EXT3_IRQ_MODULE           EIC
-#define EXT3_IRQ_INPUT            8
-#define EXT3_IRQ_PIN              PIN_PA28A_EIC_EXTINT8
-#define EXT3_IRQ_MUX              MUX_PA28A_EIC_EXTINT8
-#define EXT3_IRQ_PINMUX           PINMUX_PA28A_EIC_EXTINT8
-/** @} */
-
-/** \name Extension header #3 I2C definitions
- *  @{
- */
-#define EXT3_I2C_MODULE              SERCOM2
-#define EXT3_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
-#define EXT3_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
-#define EXT3_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
-#define EXT3_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #3 UART definitions
- *  @{
- */
-#define EXT3_UART_MODULE              SERCOM4
-#define EXT3_UART_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
-#define EXT3_UART_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
-#define EXT3_UART_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
-#define EXT3_UART_SERCOM_PINMUX_PAD2  PINMUX_PB10D_SERCOM4_PAD2
-#define EXT3_UART_SERCOM_PINMUX_PAD3  PINMUX_PB11D_SERCOM4_PAD3
-#define EXT3_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
-#define EXT3_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #3 SPI definitions
- *  @{
- */
-#define EXT3_SPI_MODULE              SERCOM5
-#define EXT3_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
-#define EXT3_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
-#define EXT3_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB17C_SERCOM5_PAD1
-#define EXT3_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
-#define EXT3_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
-#define EXT3_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
-#define EXT3_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
-/** @} */
-
-/** \name Extension header #3 Dataflash
- *  @{
- */
-#define EXT3_DATAFLASH_SPI_MODULE      EXT3_SPI_MODULE
-#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
-#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
-#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
-#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
-#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
-/** @} */
-
-/** \name USB definitions
- * @{
- */
-#define USB_ID
-#define USB_TARGET_DP_PIN            PIN_PA25G_USB_DP
-#define USB_TARGET_DP_MUX            MUX_PA25G_USB_DP
-#define USB_TARGET_DP_PINMUX         PINMUX_PA25G_USB_DP
-#define USB_TARGET_DM_PIN            PIN_PA24G_USB_DM
-#define USB_TARGET_DM_MUX            MUX_PA24G_USB_DM
-#define USB_TARGET_DM_PINMUX         PINMUX_PA24G_USB_DM
-#define USB_VBUS_PIN                 PIN_PA14
-#define USB_VBUS_EIC_LINE            14
-#define USB_VBUS_EIC_MUX             MUX_PA14A_EIC_EXTINT14
-#define USB_VBUS_EIC_PINMUX          PINMUX_PA14A_EIC_EXTINT14
-#define USB_ID_PIN                   PIN_PA03
-#define USB_ID_EIC_LINE              3
-#define USB_ID_EIC_MUX               MUX_PA03A_EIC_EXTINT3
-#define USB_ID_EIC_PINMUX            PINMUX_PA03A_EIC_EXTINT3
-/** @} */
-
-/** \name Embedded debugger GPIO interface definitions
- * @{
- */
-#define EDBG_GPIO0_PIN            PIN_PA27
-#define EDBG_GPIO1_PIN            PIN_PA28
-#define EDBG_GPIO2_PIN            PIN_PA20
-#define EDBG_GPIO3_PIN            PIN_PA21
-/** @} */
-
-/** \name Embedded debugger USART interface definitions
- * @{
- */
-#define EDBG_UART_MODULE          -1 /* Not available on this board */
-#define EDBG_UART_RX_PIN          -1 /* Not available on this board */
-#define EDBG_UART_RX_MUX          -1 /* Not available on this board */
-#define EDBG_UART_RX_PINMUX       -1 /* Not available on this board */
-#define EDBG_UART_RX_SERCOM_PAD   -1 /* Not available on this board */
-#define EDBG_UART_TX_PIN          -1 /* Not available on this board */
-#define EDBG_UART_TX_MUX          -1 /* Not available on this board */
-#define EDBG_UART_TX_PINMUX       -1 /* Not available on this board */
-#define EDBG_UART_TX_SERCOM_PAD   -1 /* Not available on this board */
-/** @} */
-
-/** \name Embedded debugger I2C interface definitions
- * @{
- */
-#define EDBG_I2C_MODULE              SERCOM2
-#define EDBG_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
-#define EDBG_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
-#define EDBG_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
-#define EDBG_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
-/** @} */
-
-/** \name Embedded debugger SPI interface definitions
- * @{
- */
-#define EDBG_SPI_MODULE              SERCOM5
-#define EDBG_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
-#define EDBG_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
-#define EDBG_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB31D_SERCOM5_PAD1
-#define EDBG_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
-#define EDBG_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
-#define EDBG_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
-#define EDBG_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
-/** @} */
-
-/** \name Embedded debugger CDC Gateway USART interface definitions
- * @{
- */
-#define EDBG_CDC_MODULE              SERCOM3
-#define EDBG_CDC_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
-#define EDBG_CDC_SERCOM_PINMUX_PAD0  PINMUX_PA22C_SERCOM3_PAD0
-#define EDBG_CDC_SERCOM_PINMUX_PAD1  PINMUX_PA23C_SERCOM3_PAD1
-#define EDBG_CDC_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
-#define EDBG_CDC_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
-#define EDBG_CDC_SERCOM_DMAC_ID_TX   SERCOM3_DMAC_ID_TX
-#define EDBG_CDC_SERCOM_DMAC_ID_RX   SERCOM3_DMAC_ID_RX
-/** @} */
-
-/** @} */
-
-/** \name 802.15.4 TRX Interface definitions
- * @{
- */
-#ifndef EXT2_CONFIG
-#define AT86RFX_SPI                  EXT1_SPI_MODULE
-#define AT86RFX_RST_PIN              EXT1_PIN_7
-#define AT86RFX_MISC_PIN             EXT1_PIN_12
-#define AT86RFX_IRQ_PIN              EXT1_PIN_9
-#define AT86RFX_SLP_PIN              EXT1_PIN_10
-#define AT86RFX_SPI_CS               EXT1_PIN_15
-#define AT86RFX_SPI_MOSI             EXT1_PIN_16
-#define AT86RFX_SPI_MISO             EXT1_PIN_17
-#define AT86RFX_SPI_SCK              EXT1_PIN_18
-#define AT86RFX_CSD                  EXT1_PIN_5
-#define AT86RFX_CPS                  EXT1_PIN_8
-
-#define AT86RFX_SPI_SERCOM_MUX_SETTING   EXT1_SPI_SERCOM_MUX_SETTING
-#define AT86RFX_SPI_SERCOM_PINMUX_PAD0   EXT1_SPI_SERCOM_PINMUX_PAD0
-#define AT86RFX_SPI_SERCOM_PINMUX_PAD1   PINMUX_UNUSED
-#define AT86RFX_SPI_SERCOM_PINMUX_PAD2   EXT1_SPI_SERCOM_PINMUX_PAD2
-#define AT86RFX_SPI_SERCOM_PINMUX_PAD3   EXT1_SPI_SERCOM_PINMUX_PAD3
-
-#define AT86RFX_IRQ_CHAN       EXT1_IRQ_INPUT
-#define AT86RFX_IRQ_PINMUX     EXT1_IRQ_PINMUX
-
-
-#endif
-/** Enables the transceiver main interrupt. */
-#define ENABLE_TRX_IRQ()     \
-		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
-
-/** Disables the transceiver main interrupt. */
-#define DISABLE_TRX_IRQ()    \
-		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
-
-/** Clears the transceiver main interrupt. */
-#define CLEAR_TRX_IRQ()      \
-		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
-
-/*
- * This macro saves the trx interrupt status and disables the trx interrupt.
- */
-#define ENTER_TRX_REGION()   \
-		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
-
-/*
- *  This macro restores the transceiver interrupt status
- */
-#define LEAVE_TRX_REGION()   \
-		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
-
-/** @} */
-
-/**
- * \brief Turns off the specified LEDs.
- *
- * \param led_gpio LED to turn off (LEDx_GPIO).
- *
- * \note The pins of the specified LEDs are set to GPIO output mode.
- */
-#define LED_Off(led_gpio)     port_pin_set_output_level(led_gpio,true)
-
-/**
- * \brief Turns on the specified LEDs.
- *
- * \param led_gpio LED to turn on (LEDx_GPIO).
- *
- * \note The pins of the specified LEDs are set to GPIO output mode.
- */
-#define LED_On(led_gpio)      port_pin_set_output_level(led_gpio,false)
-
-/**
- * \brief Toggles the specified LEDs.
- *
- * \param led_gpio LED to toggle (LEDx_GPIO).
- *
- * \note The pins of the specified LEDs are set to GPIO output mode.
- */
-#define LED_Toggle(led_gpio)  port_pin_toggle_output_level(led_gpio)
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* SAMD21_XPLAINED_PRO_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board definition
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
+#define SAMD21_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samd21_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME                "SAMD21_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ *  @{ */
+#define BOARD_FREQ_SLCK_XTAL      (32768U)
+#define BOARD_FREQ_SLCK_BYPASS    (32768U)
+#define BOARD_FREQ_MAINCK_XTAL    0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS  0 /* Not Mounted */
+#define BOARD_MCK                 CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US      15625
+/** @} */
+
+/** \name LED0 definitions
+ *  @{ */
+#define LED0_PIN                  PIN_PB30
+#define LED0_ACTIVE               false
+#define LED0_INACTIVE             !LED0_ACTIVE
+/** @} */
+
+/** \name SW0 definitions
+ *  @{ */
+#define SW0_PIN                   PIN_PA15
+#define SW0_ACTIVE                false
+#define SW0_INACTIVE              !SW0_ACTIVE
+#define SW0_EIC_PIN               PIN_PA15A_EIC_EXTINT15
+#define SW0_EIC_MUX               MUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_PINMUX            PINMUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_LINE              15
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define LED_0_NAME                "LED0 (yellow)"
+#define LED_0_PIN                 LED0_PIN
+#define LED_0_ACTIVE              LED0_ACTIVE
+#define LED_0_INACTIVE            LED0_INACTIVE
+#define LED0_GPIO                 LED0_PIN
+#define LED0                      LED0_PIN
+
+#define LED_0_PWM4CTRL_MODULE     TCC0
+#define LED_0_PWM4CTRL_CHANNEL    0
+#define LED_0_PWM4CTRL_OUTPUT     0
+#define LED_0_PWM4CTRL_PIN        PIN_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_MUX        MUX_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_PINMUX     PINMUX_PB30E_TCC0_WO0
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT                 1
+
+/**
+ * \name Serialflash definitions
+ *
+ * On board Serialflash definitions.
+ *
+ *  @{ */
+#define SERIALFLASH_SPI_MODULE      SERCOM5
+#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
+#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define SERIALFLASH_SPI_CS PIN_PA13
+/** @} */
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define BUTTON_0_NAME             "SW0"
+#define BUTTON_0_PIN              SW0_PIN
+#define BUTTON_0_ACTIVE           SW0_ACTIVE
+#define BUTTON_0_INACTIVE         SW0_INACTIVE
+#define BUTTON_0_EIC_PIN          SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX          SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX       SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE         SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ *  @{
+ */
+#define EXT1_PIN_3                PIN_PB00
+#define EXT1_PIN_4                PIN_PB01
+#define EXT1_PIN_5                PIN_PB06
+#define EXT1_PIN_6                PIN_PB07
+#define EXT1_PIN_7                PIN_PB02
+#define EXT1_PIN_8                PIN_PB03
+#define EXT1_PIN_9                PIN_PB04
+#define EXT1_PIN_10               PIN_PB05
+#define EXT1_PIN_11               PIN_PA08
+#define EXT1_PIN_12               PIN_PA09
+#define EXT1_PIN_13               PIN_PB09
+#define EXT1_PIN_14               PIN_PB08
+#define EXT1_PIN_15               PIN_PA05
+#define EXT1_PIN_16               PIN_PA06
+#define EXT1_PIN_17               PIN_PA04
+#define EXT1_PIN_18               PIN_PA07
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ *  @{
+ */
+#define EXT1_PIN_ADC_0            EXT1_PIN_3
+#define EXT1_PIN_ADC_1            EXT1_PIN_4
+#define EXT1_PIN_GPIO_0           EXT1_PIN_5
+#define EXT1_PIN_GPIO_1           EXT1_PIN_6
+#define EXT1_PIN_PWM_0            EXT1_PIN_7
+#define EXT1_PIN_PWM_1            EXT1_PIN_8
+#define EXT1_PIN_IRQ              EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA          EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL          EXT1_PIN_12
+#define EXT1_PIN_UART_RX          EXT1_PIN_13
+#define EXT1_PIN_UART_TX          EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1         EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0         EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI         EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO         EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK          EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ *  @{
+ */
+#define EXT1_ADC_MODULE           ADC
+#define EXT1_ADC_0_CHANNEL        8
+#define EXT1_ADC_0_PIN            PIN_PB00B_ADC_AIN8
+#define EXT1_ADC_0_MUX            MUX_PB00B_ADC_AIN8
+#define EXT1_ADC_0_PINMUX         PINMUX_PB00B_ADC_AIN8
+#define EXT1_ADC_1_CHANNEL        9
+#define EXT1_ADC_1_PIN            PIN_PB01B_ADC_AIN9
+#define EXT1_ADC_1_MUX            MUX_PB01B_ADC_AIN9
+#define EXT1_ADC_1_PINMUX         PINMUX_PB01B_ADC_AIN9
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ *  @{
+ */
+#define EXT1_PWM_MODULE           TC6
+#define EXT1_PWM_0_CHANNEL        0
+#define EXT1_PWM_0_PIN            PIN_PB02E_TC6_WO0
+#define EXT1_PWM_0_MUX            MUX_PB02E_TC6_WO0
+#define EXT1_PWM_0_PINMUX         PINMUX_PB02E_TC6_WO0
+#define EXT1_PWM_1_CHANNEL        1
+#define EXT1_PWM_1_PIN            PIN_PB03E_TC6_WO1
+#define EXT1_PWM_1_MUX            MUX_PB03E_TC6_WO1
+#define EXT1_PWM_1_PINMUX         PINMUX_PB03E_TC6_WO1
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT1_IRQ_MODULE           EIC
+#define EXT1_IRQ_INPUT            4
+#define EXT1_IRQ_PIN              PIN_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_MUX              MUX_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_PINMUX           PINMUX_PB04A_EIC_EXTINT4
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ *  @{
+ */
+#define EXT1_I2C_MODULE              SERCOM2
+#define EXT1_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ *  @{
+ */
+#define EXT1_UART_MODULE              SERCOM4
+#define EXT1_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0  PINMUX_PB08D_SERCOM4_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1  PINMUX_PB09D_SERCOM4_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ *  @{
+ */
+#define EXT1_SPI_MODULE              SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA07D_SERCOM0_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX   SERCOM0_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX   SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 pin definitions
+ *  @{
+ */
+#define EXT2_PIN_3                PIN_PA10
+#define EXT2_PIN_4                PIN_PA11
+#define EXT2_PIN_5                PIN_PA20
+#define EXT2_PIN_6                PIN_PA21
+#define EXT2_PIN_7                PIN_PB12
+#define EXT2_PIN_8                PIN_PB13
+#define EXT2_PIN_9                PIN_PB14
+#define EXT2_PIN_10               PIN_PB15
+#define EXT2_PIN_11               PIN_PA08
+#define EXT2_PIN_12               PIN_PA09
+#define EXT2_PIN_13               PIN_PB11
+#define EXT2_PIN_14               PIN_PB10
+#define EXT2_PIN_15               PIN_PA17
+#define EXT2_PIN_16               PIN_PA18
+#define EXT2_PIN_17               PIN_PA16
+#define EXT2_PIN_18               PIN_PA19
+/** @} */
+
+/** \name Extension header #2 pin definitions by function
+ *  @{
+ */
+#define EXT2_PIN_ADC_0            EXT2_PIN_3
+#define EXT2_PIN_ADC_1            EXT2_PIN_4
+#define EXT2_PIN_GPIO_0           EXT2_PIN_5
+#define EXT2_PIN_GPIO_1           EXT2_PIN_6
+#define EXT2_PIN_PWM_0            EXT2_PIN_7
+#define EXT2_PIN_PWM_1            EXT2_PIN_8
+#define EXT2_PIN_IRQ              EXT2_PIN_9
+#define EXT2_PIN_I2C_SDA          EXT2_PIN_11
+#define EXT2_PIN_I2C_SCL          EXT2_PIN_12
+#define EXT2_PIN_UART_RX          EXT2_PIN_13
+#define EXT2_PIN_UART_TX          EXT2_PIN_14
+#define EXT2_PIN_SPI_SS_1         EXT2_PIN_10
+#define EXT2_PIN_SPI_SS_0         EXT2_PIN_15
+#define EXT2_PIN_SPI_MOSI         EXT2_PIN_16
+#define EXT2_PIN_SPI_MISO         EXT2_PIN_17
+#define EXT2_PIN_SPI_SCK          EXT2_PIN_18
+/** @} */
+
+/** \name Extension header #2 ADC definitions
+ *  @{
+ */
+#define EXT2_ADC_MODULE           ADC
+#define EXT2_ADC_0_CHANNEL        18
+#define EXT2_ADC_0_PIN            PIN_PA10B_ADC_AIN18
+#define EXT2_ADC_0_MUX            MUX_PA10B_ADC_AIN18
+#define EXT2_ADC_0_PINMUX         PINMUX_PA10B_ADC_AIN18
+#define EXT2_ADC_1_CHANNEL        19
+#define EXT2_ADC_1_PIN            PIN_PA11B_ADC_AIN19
+#define EXT2_ADC_1_MUX            MUX_PA11B_ADC_AIN19
+#define EXT2_ADC_1_PINMUX         PINMUX_PA11B_ADC_AIN19
+/** @} */
+
+/** \name Extension header #2 PWM definitions
+ *  @{
+ */
+#define EXT2_PWM_MODULE           TC4
+#define EXT2_PWM_0_CHANNEL        0
+#define EXT2_PWM_0_PIN            PIN_PB12E_TC4_WO0
+#define EXT2_PWM_0_MUX            MUX_PB12E_TC4_WO0
+#define EXT2_PWM_0_PINMUX         PINMUX_PB12E_TC4_WO0
+#define EXT2_PWM_1_CHANNEL        1
+#define EXT2_PWM_1_PIN            PIN_PB13E_TC4_WO1
+#define EXT2_PWM_1_MUX            MUX_PB13E_TC4_WO1
+#define EXT2_PWM_1_PINMUX         PINMUX_PB13E_TC4_WO1
+/** @} */
+
+/** \name Extension header #2 PWM for Control definitions
+ *  @{
+ */
+#define EXT2_PWM4CTRL_MODULE      TCC0
+#define EXT2_PWM4CTRL_0_CHANNEL   2
+#define EXT2_PWM4CTRL_0_OUTPUT    6
+#define EXT2_PWM4CTRL_0_PIN       PIN_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_MUX       MUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_PINMUX    PINMUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_1_CHANNEL   3
+#define EXT2_PWM4CTRL_1_OUTPUT    7
+#define EXT2_PWM4CTRL_1_PIN       PIN_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_MUX       MUX_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_PINMUX    PINMUX_PB13F_TCC0_WO7
+/** @} */
+
+/** \name Extension header #2 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT2_IRQ_MODULE           EIC
+#define EXT2_IRQ_INPUT            14
+#define EXT2_IRQ_PIN              PIN_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_MUX              MUX_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_PINMUX           PINMUX_PB14A_EIC_EXTINT14
+/** @} */
+
+ /** \name Extension header #2 I2C definitions
+ *  @{
+ */
+#define EXT2_I2C_MODULE              SERCOM2
+#define EXT2_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT2_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT2_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT2_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 UART definitions
+ *  @{
+ */
+#define EXT2_UART_MODULE              SERCOM4
+#define EXT2_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT2_UART_SERCOM_PINMUX_PAD0  PINMUX_PB12C_SERCOM4_PAD0
+#define EXT2_UART_SERCOM_PINMUX_PAD1  PINMUX_PB13C_SERCOM4_PAD1
+#define EXT2_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT2_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 SPI definitions
+ *  @{
+ */
+#define EXT2_SPI_MODULE              SERCOM1
+#define EXT2_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT2_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EXT2_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EXT2_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA18C_SERCOM1_PAD2
+#define EXT2_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA19C_SERCOM1_PAD3
+#define EXT2_SPI_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EXT2_SPI_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ *  @{
+ */
+#define EXT3_PIN_3                PIN_PA02
+#define EXT3_PIN_4                PIN_PA03
+#define EXT3_PIN_5                PIN_PB30
+#define EXT3_PIN_6                PIN_PA15
+#define EXT3_PIN_7                PIN_PA12
+#define EXT3_PIN_8                PIN_PA13
+#define EXT3_PIN_9                PIN_PA28
+#define EXT3_PIN_10               PIN_PA27
+#define EXT3_PIN_11               PIN_PA08
+#define EXT3_PIN_12               PIN_PA09
+#define EXT3_PIN_13               PIN_PB11
+#define EXT3_PIN_14               PIN_PB10
+#define EXT3_PIN_15               PIN_PB17
+#define EXT3_PIN_16               PIN_PB22
+#define EXT3_PIN_17               PIN_PB16
+#define EXT3_PIN_18               PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ *  @{
+ */
+#define EXT3_PIN_ADC_0            EXT3_PIN_3
+#define EXT3_PIN_ADC_1            EXT3_PIN_4
+#define EXT3_PIN_GPIO_0           EXT3_PIN_5
+#define EXT3_PIN_GPIO_1           EXT3_PIN_6
+#define EXT3_PIN_PWM_0            EXT3_PIN_7
+#define EXT3_PIN_PWM_1            EXT3_PIN_8
+#define EXT3_PIN_IRQ              EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA          EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL          EXT3_PIN_12
+#define EXT3_PIN_UART_RX          EXT3_PIN_13
+#define EXT3_PIN_UART_TX          EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1         EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0         EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI         EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO         EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK          EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ *  @{
+ */
+#define EXT3_ADC_MODULE           ADC
+#define EXT3_ADC_0_CHANNEL        0
+#define EXT3_ADC_0_PIN            PIN_PA02B_ADC_AIN0
+#define EXT3_ADC_0_MUX            MUX_PA02B_ADC_AIN0
+#define EXT3_ADC_0_PINMUX         PINMUX_PA02B_ADC_AIN0
+#define EXT3_ADC_1_CHANNEL        1
+#define EXT3_ADC_1_PIN            PIN_PA03B_ADC_AIN1
+#define EXT3_ADC_1_MUX            MUX_PA03B_ADC_AIN1
+#define EXT3_ADC_1_PINMUX         PINMUX_PA03B_ADC_AIN1
+/** @} */
+
+/** \name Extension header #3 PWM for Control definitions
+ *  @{
+ */
+#define EXT3_PWM4CTRL_MODULE      TCC2
+#define EXT3_PWM4CTRL_0_CHANNEL   0
+#define EXT3_PWM4CTRL_0_OUTPUT    0
+#define EXT3_PWM4CTRL_0_PIN       PIN_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_MUX       MUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_PINMUX    PINMUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_1_CHANNEL   1
+#define EXT3_PWM4CTRL_1_OUTPUT    1
+#define EXT3_PWM4CTRL_1_PIN       PIN_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_MUX       MUX_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_PINMUX    PINMUX_PA13E_TCC2_WO1
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT3_IRQ_MODULE           EIC
+#define EXT3_IRQ_INPUT            8
+#define EXT3_IRQ_PIN              PIN_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_MUX              MUX_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_PINMUX           PINMUX_PA28A_EIC_EXTINT8
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ *  @{
+ */
+#define EXT3_I2C_MODULE              SERCOM2
+#define EXT3_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT3_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT3_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ *  @{
+ */
+#define EXT3_UART_MODULE              SERCOM4
+#define EXT3_UART_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2  PINMUX_PB10D_SERCOM4_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3  PINMUX_PB11D_SERCOM4_PAD3
+#define EXT3_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT3_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ *  @{
+ */
+#define EXT3_SPI_MODULE              SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB17C_SERCOM5_PAD1
+#define EXT3_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 Dataflash
+ *  @{
+ */
+#define EXT3_DATAFLASH_SPI_MODULE      EXT3_SPI_MODULE
+#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN            PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX            MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX         PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN            PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX            MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX         PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN                 PIN_PA14
+#define USB_VBUS_EIC_LINE            14
+#define USB_VBUS_EIC_MUX             MUX_PA14A_EIC_EXTINT14
+#define USB_VBUS_EIC_PINMUX          PINMUX_PA14A_EIC_EXTINT14
+#define USB_ID_PIN                   PIN_PA03
+#define USB_ID_EIC_LINE              3
+#define USB_ID_EIC_MUX               MUX_PA03A_EIC_EXTINT3
+#define USB_ID_EIC_PINMUX            PINMUX_PA03A_EIC_EXTINT3
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN            PIN_PA27
+#define EDBG_GPIO1_PIN            PIN_PA28
+#define EDBG_GPIO2_PIN            PIN_PA20
+#define EDBG_GPIO3_PIN            PIN_PA21
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE          -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD   -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD   -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE              SERCOM2
+#define EDBG_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE              SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB31D_SERCOM5_PAD1
+#define EDBG_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE              SERCOM3
+#define EDBG_CDC_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0  PINMUX_PA22C_SERCOM3_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1  PINMUX_PA23C_SERCOM3_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX   SERCOM3_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX   SERCOM3_DMAC_ID_RX
+/** @} */
+
+/** @} */
+
+/** \name 802.15.4 TRX Interface definitions
+ * @{
+ */
+#ifndef EXT2_CONFIG
+#define AT86RFX_SPI                  EXT1_SPI_MODULE
+#define AT86RFX_RST_PIN              EXT1_PIN_7
+#define AT86RFX_MISC_PIN             EXT1_PIN_12
+#define AT86RFX_IRQ_PIN              EXT1_PIN_9
+#define AT86RFX_SLP_PIN              EXT1_PIN_10
+#define AT86RFX_SPI_CS               EXT1_PIN_15
+#define AT86RFX_SPI_MOSI             EXT1_PIN_16
+#define AT86RFX_SPI_MISO             EXT1_PIN_17
+#define AT86RFX_SPI_SCK              EXT1_PIN_18
+#define AT86RFX_CSD                  EXT1_PIN_5
+#define AT86RFX_CPS                  EXT1_PIN_8
+
+#define AT86RFX_SPI_SERCOM_MUX_SETTING   EXT1_SPI_SERCOM_MUX_SETTING
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD0   EXT1_SPI_SERCOM_PINMUX_PAD0
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD1   PINMUX_UNUSED
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD2   EXT1_SPI_SERCOM_PINMUX_PAD2
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD3   EXT1_SPI_SERCOM_PINMUX_PAD3
+
+#define AT86RFX_IRQ_CHAN       EXT1_IRQ_INPUT
+#define AT86RFX_IRQ_PINMUX     EXT1_IRQ_PINMUX
+
+
+#endif
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ()     \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ()    \
+		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ()      \
+		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION()   \
+		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ *  This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION()   \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/** @} */
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio)     port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio)      port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio)  port_pin_toggle_output_level(led_gpio)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SAMD21_XPLAINED_PRO_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc.h
index 1236203..b24fd81 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc.h
@@ -1,1147 +1,1147 @@
-/**
- * \file
- *
- * \brief SAM Peripheral Analog-to-Digital Converter Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef ADC_H_INCLUDED
-#define ADC_H_INCLUDED
-
-/**
- * \defgroup asfdoc_sam0_adc_group SAM Analog-to-Digital Converter (ADC) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
- * and management of the device's Analog-to-Digital Converter functionality, for
- * the conversion of analog voltages into a corresponding digital form.
- * The following driver Application Programming Interface (API) modes are covered by this manual:
- * - Polled APIs
- * \if ADC_CALLBACK_MODE
- * - Callback APIs
- * \endif
- *
- * The following peripheral is used by this module:
- *  - ADC (Analog-to-Digital Converter)
- *
- * The following devices can use this module:
- * \if DEVICE_SAML21_SUPPORT
- *  - Atmel | SMART SAM L21/L22
- *  - Atmel | SMART SAM C20/C21
- *  - Atmel | SMART SAM R34/R35
- * \else
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM HA1
- * \endif
- *
- * The outline of this documentation is as follows:
- *  - \ref asfdoc_sam0_adc_prerequisites
- *  - \ref asfdoc_sam0_adc_module_overview
- *  - \ref asfdoc_sam0_adc_special_considerations
- *  - \ref asfdoc_sam0_adc_extra_info
- *  - \ref asfdoc_sam0_adc_examples
- *  - \ref asfdoc_sam0_adc_api_overview
- *
- *
- * \section asfdoc_sam0_adc_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_adc_module_overview Module Overview
- *
- * This driver provides an interface for the Analog-to-Digital conversion
- * functions on the device, to convert analog voltages to a corresponding
- * digital value. The ADC has up to 12-bit resolution, and is capable of
- * \if DEVICE_SAML21_SUPPORT
- * converting up to 1,000,000 samples per second (MSPS).
- * \else
- * converting up to 500K samples per second (KSPS).
- * \endif
- *
- * The ADC has a compare function for accurate monitoring of user defined
- * thresholds with minimum software intervention required.
- * The ADC may be configured for 8-, 10-, or 12-bit result, reducing the
- * conversion time. ADC conversion results are provided left or right adjusted
- * which eases calculation when the result is represented as a signed integer.
- *
- * The input selection is flexible, and both single-ended and differential
- * measurements can be made. For differential measurements, an optional gain
- * stage is available to increase the dynamic range. In addition, several
- * internal signal inputs are available. The ADC can provide both signed and
- * unsigned results.
- *
- * The ADC measurements can either be started by application software or an
- * incoming event from another peripheral in the device, and both internal and
- * external reference voltages can be selected.
- *
- * \note Internal references will be enabled by the driver, but not disabled.
- *       Any reference not used by the application should be disabled by the application.
- *
- * A simplified block diagram of the ADC can be seen in
- * \ref asfdoc_sam0_adc_module_block_diagram "the figure below".
- *
- * \anchor asfdoc_sam0_adc_module_block_diagram
- * \dot
- * digraph overview {
- * splines = false;
- * rankdir=LR;
- *
- * mux1 [label="Positive input", shape=box];
- * mux2 [label="Negative input", shape=box];
- *
- *
- * mux3 [label="Reference", shape=box];
- *
- * adc [label="ADC", shape=polygon, sides=5, orientation=90, distortion=-0.6, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
- * prescaler [label="PRESCALER", shape=box, style=filled, fillcolor=lightblue];
- *
- * mux1 -> adc;
- * mux2 -> adc;
- * mux3 -> adc:sw;
- * prescaler -> adc;
- *
- * postproc [label="Post processing", shape=box];
- * result [label="RESULT", shape=box, style=filled, fillcolor=lightblue];
- *
- * adc:e -> postproc:w;
- * postproc:e -> result:w;
- *
- * {rank=same; mux1 mux2}
- * {rank=same; prescaler adc}
- *
- * }
- * \enddot
- *
- *
- * \subsection asfdoc_sam0_adc_module_overview_prescaler Sample Clock Prescaler
- * The ADC features a prescaler, which enables conversion at lower clock rates
- * than the input Generic Clock to the ADC module. This feature can be used to
- * lower the synchronization time of the digital interface to the ADC module
- * via a high speed Generic Clock frequency, while still allowing the ADC
- * sampling rate to be reduced.
- *
- * \subsection asfdoc_sam0_adc_module_overview_resolution ADC Resolution
- * The ADC supports full 8-, 10-, or 12-bit resolution. Hardware
- * oversampling and decimation can be used to increase the
- * effective resolution at the expense of throughput. Using oversampling and
- * decimation mode the ADC resolution is increased from 12-bit to an effective
- * 13-, 14-, 15-, or 16-bit. In these modes the conversion rate is reduced, as
- * a greater number of samples is used to achieve the increased resolution. The
- * available resolutions and effective conversion rate is listed in
- * \ref asfdoc_sam0_adc_module_conversion_rate "the table below".
- *
- * \anchor asfdoc_sam0_adc_module_conversion_rate
- * <table>
- *	<caption>Effective ADC Conversion Speed Using Oversampling</caption>
- *	<tr>
- *		<th>Resolution</th>
- *		<th>Effective conversion rate</th>
- *	</tr>
- *	<tr>
- *		<td>13-bit</td>
- *		<td>Conversion rate divided by 4</td>
- *	</tr>
- *	<tr>
- *		<td>14-bit</td>
- *		<td>Conversion rate divided by 16</td>
- *	</tr>
- *	<tr>
- *		<td>15-bit</td>
- *		<td>Conversion rate divided by 64</td>
- *	</tr>
- *	<tr>
- *		<td>16-bit</td>
- *		<td>Conversion rate divided by 256</td>
- *	</tr>
- * </table>
- *
- * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes
- * ADC conversions can be software triggered on demand by the user application,
- * if continuous sampling is not required. It is also possible to configure the
- * ADC in free running mode, where new conversions are started as soon as the
- * previous conversion is completed, or configure the ADC to scan across a
- * number of input pins (see \ref asfdoc_sam0_adc_module_overview_pin_scan).
- *
- * \subsection asfdoc_sam0_adc_module_overview_diff_mode Differential and Single-ended Conversion
- * The ADC has two conversion modes; differential and single-ended. When
- * measuring signals where the positive input pin is always at a higher voltage
- * than the negative input pin, the single-ended conversion mode should be used
- * in order to achieve a full 12-bit output resolution.
- *
- * If however the positive input pin voltage may drop below the negative input
- * pin the signed differential mode should be used.
- *
- * \subsection asfdoc_sam0_adc_module_overview_sample_time Sample Time
- * The sample time for each ADC conversion is configurable as a number of half
- * prescaled ADC clock cycles (depending on the prescaler value), allowing the
- * user application to achieve faster or slower sampling depending on the
- * source impedance of the ADC input channels. For applications with high
- * impedance inputs the sample time can be increased to give the ADC an adequate
- * time to sample and convert the input channel.
- *
- * The resulting sampling time is given by the following equation:
- * \f[
- * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2}
- * \f]
- *
- * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging
- * The ADC can be configured to trade conversion speed for accuracy by averaging
- * multiple samples in hardware. This feature is suitable when operating in
- * noisy conditions.
- *
- * You can specify any number of samples to accumulate (up to 1024) and the
- * divide ratio to use (up to divide by 128). To modify these settings the
- * ADC_RESOLUTION_CUSTOM needs to be set as the resolution. When this is set
- * the number of samples to accumulate and the division ratio can be set by
- * the configuration struct members \ref adc_config.accumulate_samples and
- * \ref adc_config.divide_result. When using this mode the ADC result register
- * will be set to be 16-bit wide to accommodate the larger result sizes
- * produced by the accumulator.
- *
- * The effective ADC conversion rate will be reduced by a factor of the number
- * of accumulated samples;
- * however, the effective resolution will be increased according to
- * \ref asfdoc_sam0_adc_module_hw_av_resolution "the table below".
- *
- * \anchor asfdoc_sam0_adc_module_hw_av_resolution
- * <table>
- *   <caption>Effective ADC Resolution From Various Hardware Averaging Modes</caption>
- *   <tr>
- *     <th>Number of samples</tr>
- *     <th>Final result</tr>
- *   </tr>
- *   <tr>
- *     <td>1</td>
- *     <td>12-bit</td>
- *   </tr>
- *   <tr>
- *      <td>2</td>
- *      <td>13-bit</td>
- *   </tr>
- *   <tr>
- *      <td>4</td>
- *      <td>14-bit</td>
- *   </tr>
- *   <tr>
- *      <td>8</td>
- *      <td>15-bit</td>
- *   </tr>
- *   <tr>
- *      <td>16</td>
- *      <td>16-bit</td>
- *   </tr>
- *   <tr>
- *      <td>32</td>
- *      <td>16-bit</td>
- *   </tr>
- *   <tr>
- *      <td>64</td>
- *      <td>16-bit</td>
- *   </tr>
- *   <tr>
- *      <td>128</td>
- *      <td>16-bit</td>
- *   </tr>
- *   <tr>
- *      <td>256</td>
- *      <td>16-bit</td>
- *   </tr>
- *   <tr>
- *      <td>512</td>
- *      <td>16-bit</td>
- *   </tr>
- *   <tr>
- *      <td>1024</td>
- *      <td>16-bit</td>
- *   </tr>
- * </table>
- *
- *
- * \subsection asfdoc_sam0_adc_module_overview_offset_corr Offset and Gain Correction
- * Inherent gain and offset errors affect the absolute accuracy of the ADC.
- *
- * The offset error is defined as the deviation of the ADC's actual transfer
- * function from ideal straight line at zero input voltage.
- *
- * The gain error is defined as the deviation of the last output step's
- * midpoint from the ideal straight line, after compensating for offset error.
- *
- * The offset correction value is subtracted from the converted data before the
- * result is ready. The gain correction value is multiplied with the offset
- * corrected value.
- *
- * The equation for both offset and gain error compensation is shown below:
- * \f[
- * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN}
- * \f]
- *
- * When enabled, a given set of offset and gain correction values can be applied
- * to the sampled data in hardware, giving a corrected stream of sample data to
- * the user application at the cost of an increased sample latency.
- *
- * In single conversion, a latency of 13 ADC Generic Clock cycles is added for
- * the final sample result availability. As the correction time is always less
- * than the propagation delay, in free running mode this latency appears only
- * during the first conversion. After the first conversion is complete, future
- * conversion results are available at the defined sampling rate.
- *
- * \subsection asfdoc_sam0_adc_module_overview_pin_scan Pin Scan
- * In pin scan mode, the first ADC conversion will begin from the configured
- * positive channel, plus the requested starting offset. When the first
- * conversion is completed, the next conversion will start at the next positive
- * input channel and so on, until all requested pins to scan have been sampled
- * and converted.
- * SAM L21/L22 has automatic sequences feature instead of pin scan mode. In automatic
- * sequence mode, all of 32 positives inputs can be included in a sequence. The
- * sequence starts from the lowest input, and go to the next enabled input
- * automatically.
- *
- * Pin scanning gives a simple mechanism to sample a large number of physical
- * input channel samples, using a single physical ADC channel.
- *
- * \subsection asfdoc_sam0_adc_module_overview_window_monitor Window Monitor
- * The ADC module window monitor function can be used to automatically compare
- * the conversion result against a preconfigured pair of upper and lower
- * threshold values.
- *
- * The threshold values are evaluated differently, depending on whether
- * differential or single-ended mode is selected. In differential mode, the
- * upper and lower thresholds are evaluated as signed values for the comparison,
- * while in single-ended mode the comparisons are made as a set of unsigned
- * values.
- *
- * The significant bits of the lower window monitor threshold and upper window
- * monitor threshold values are user-configurable, and follow the overall ADC
- * sampling bit precision set when the ADC is configured by the user application.
- * For example, only the eight lower bits of the window threshold values will be
- * compared to the sampled data whilst the ADC is configured in 8-bit mode.
- * In addition, if using differential mode, the 8<SUP>th</SUP> bit will be considered as
- * the sign bit even if bit 9 is zero.
- *
- * \subsection asfdoc_sam0_adc_module_overview_events Events
- * Event generation and event actions are configurable in the ADC.
- *
- * The ADC has two actions that can be triggered upon event reception:
- * \li Start conversion
- * \li Flush pipeline and start conversion
- *
- * The ADC can generate two events:
- * \li Window monitor
- * \li Result ready
- *
- * If the event actions are enabled in the configuration, any incoming event
- * will trigger the action.
- *
- * If the window monitor event is enabled, an event will be generated
- * when the configured window condition is detected.
- *
- * If the result ready event is enabled, an event will be generated when a
- * conversion is completed.
- *
- * \note The connection of events between modules requires the use of the
- *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
- *       to route output event of one module to the input event of another.
- *       For more information on event routing, refer to the event driver
- *       documentation.
- *
- *
- * \section asfdoc_sam0_adc_special_considerations Special Considerations
- *
- * An integrated analog temperature sensor is available for use with the ADC.
- * The bandgap voltage, as well as the scaled I/O and core voltages can also be
- * measured by the ADC. For internal ADC inputs, the internal source(s) may need
- * to be manually enabled by the user application before they can be measured.
- *
- *
- * \section asfdoc_sam0_adc_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_adc_extra. This includes:
- *  - \ref asfdoc_sam0_adc_extra_acronyms
- *  - \ref asfdoc_sam0_adc_extra_dependencies
- *  - \ref asfdoc_sam0_adc_extra_errata
- *  - \ref asfdoc_sam0_adc_extra_history
- *
- *
- * \section asfdoc_sam0_adc_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_adc_exqsg.
- *
- *
- * \section asfdoc_sam0_adc_api_overview API Overview
- * @{
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <compiler.h>
-#include <system.h>
-#include <adc_feature.h>
-
-/**
- * \name Module Status Flags
- *
- * ADC status flags, returned by \ref adc_get_status() and cleared by
- * \ref adc_clear_status().
- *
- * @{
- */
-
-/** ADC result ready. */
-#define ADC_STATUS_RESULT_READY  (1UL << 0)
-/** Window monitor match. */
-#define ADC_STATUS_WINDOW        (1UL << 1)
-/** ADC result overwritten before read. */
-#define ADC_STATUS_OVERRUN       (1UL << 2)
-
-/** @} */
-
-#if ADC_CALLBACK_MODE == true
-#   if (ADC_INST_NUM > 1)
-#       define _ADC_INTERRUPT_VECT_NUM(n, unused) \
-			SYSTEM_INTERRUPT_MODULE_ADC##n,
-/**
- * \internal Get the interrupt vector for the given device instance
- *
- * \param[in] The ADC module instance number
- *
- * \return Interrupt vector for of the given ADC module instance.
- */
-static enum system_interrupt_vector _adc_interrupt_get_interrupt_vector(
-		uint32_t inst_num)
-{
-	static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = {
-		MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0)
-	};
-
-	return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num];
-}
-#   endif
-#endif
-
-#if !defined(__DOXYGEN__)
-uint8_t _adc_get_inst_index(
-		Adc *const hw);
-#endif
-
-/**
- * \name Driver Initialization and Configuration
- * @{
- */
-enum status_code adc_init(
-		struct adc_module *const module_inst,
-		Adc *hw,
-		struct adc_config *config);
-
-void adc_get_config_defaults(
-		struct adc_config *const config);
-
-#if (SAMD) || (SAMHA1) || (SAMHA0) || (SAMR21)
-void adc_regular_ain_channel(
-		uint32_t *pin_array, uint8_t size);
-#endif
-
-/** @} */
-
-/**
- * \name Status Management
- * @{
- */
-
-/**
- * \brief Retrieves the current module status.
- *
- * Retrieves the status of the module, giving overall state information.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- *
- * \return Bitmask of \c ADC_STATUS_* flags.
- *
- * \retval ADC_STATUS_RESULT_READY  ADC result is ready to be read
- * \retval ADC_STATUS_WINDOW        ADC has detected a value inside the set
- *                                  window range
- * \retval ADC_STATUS_OVERRUN       ADC result has overrun
- */
-static inline uint32_t adc_get_status(
-		struct adc_module *const module_inst)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	uint32_t int_flags = adc_module->INTFLAG.reg;
-
-	uint32_t status_flags = 0;
-
-	/* Check for ADC Result Ready */
-	if (int_flags & ADC_INTFLAG_RESRDY) {
-		status_flags |= ADC_STATUS_RESULT_READY;
-	}
-
-	/* Check for ADC Window Match */
-	if (int_flags & ADC_INTFLAG_WINMON) {
-		status_flags |= ADC_STATUS_WINDOW;
-	}
-
-	/* Check for ADC Overrun */
-	if (int_flags & ADC_INTFLAG_OVERRUN) {
-		status_flags |= ADC_STATUS_OVERRUN;
-	}
-
-	return status_flags;
-}
-
-/**
- * \brief Clears a module status flag.
- *
- * Clears the given status flag of the module.
- *
- * \param[in] module_inst   Pointer to the ADC software instance struct
- * \param[in] status_flags  Bitmask of \c ADC_STATUS_* flags to clear
- */
-static inline void adc_clear_status(
-		struct adc_module *const module_inst,
-		const uint32_t status_flags)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	uint32_t int_flags = 0;
-
-	/* Check for ADC Result Ready */
-	if (status_flags & ADC_STATUS_RESULT_READY) {
-		int_flags |= ADC_INTFLAG_RESRDY;
-	}
-
-	/* Check for ADC Window Match */
-	if (status_flags & ADC_STATUS_WINDOW) {
-		int_flags |= ADC_INTFLAG_WINMON;
-	}
-
-	/* Check for ADC Overrun */
-	if (status_flags & ADC_STATUS_OVERRUN) {
-		int_flags |= ADC_INTFLAG_OVERRUN;
-	}
-
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = int_flags;
-}
-/** @} */
-
-/**
- * \name Enable, Disable, and Reset ADC Module, Start Conversion and Read Result
- * @{
- */
-
-/**
- * \brief Enables the ADC module.
- *
- * Enables an ADC module that has previously been configured. If any internal reference
- * is selected it will be enabled.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- */
-static inline enum status_code adc_enable(
-		struct adc_module *const module_inst)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-#if ADC_CALLBACK_MODE == true
-#   if (ADC_INST_NUM > 1)
-	system_interrupt_enable(_adc_interrupt_get_interrupt_vector(
-			_adc_get_inst_index(adc_module)));
-#   elif (SAMC20)
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0);
-#	else
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
-#   endif
-#endif
-
-	/* Disbale interrupt */
-	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
-
-	adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
-}
-
-/**
- * \brief Disables the ADC module.
- *
- * Disables an ADC module that was previously enabled.
- *
- * \param[in] module_inst Pointer to the ADC software instance struct
- */
-static inline enum status_code adc_disable(
-		struct adc_module *const module_inst)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-#if ADC_CALLBACK_MODE == true
-#   if (ADC_INST_NUM > 1)
-	system_interrupt_disable(_adc_interrupt_get_interrupt_vector(
-			_adc_get_inst_index(adc_module)));
-#   elif (SAMC20)
-		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0);
-#	else
-		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
-#   endif
-#endif
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Disbale interrupt */
-	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
-
-	adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
-}
-
-/**
- * \brief Resets the ADC module.
- *
- * Resets an ADC module, clearing all module state, and registers to their
- * default values.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- */
-static inline enum status_code adc_reset(
-		struct adc_module *const module_inst)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	/* Disable to make sure the pipeline is flushed before reset */
-	adc_disable(module_inst);
-
-	/* Software reset the module */
-	adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
-}
-
-
-/**
- * \brief Enables an ADC event input or output.
- *
- *  Enables one or more input or output events to or from the ADC module. See
- *  \ref adc_events "Struct adc_events" for a list of events this module supports.
- *
- *  \note Events cannot be altered while the module is enabled.
- *
- *  \param[in] module_inst  Software instance for the ADC peripheral
- *  \param[in] events       Struct containing flags of events to enable
- */
-static inline void adc_enable_events(
-		struct adc_module *const module_inst,
-		struct adc_events *const events)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Adc *const adc_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= ADC_EVCTRL_WINMONEO;
-	}
-
-	/* Configure Result Ready event */
-	if (events->generate_event_on_conversion_done) {
-		event_mask |= ADC_EVCTRL_RESRDYEO;
-	}
-
-	adc_module->EVCTRL.reg |= event_mask;
-}
-
-/**
- * \brief Disables an ADC event input or output.
- *
- *  Disables one or more input or output events to or from the ADC module. See
- *  \ref adc_events "Struct adc_events" for a list of events this module supports.
- *
- *  \note Events cannot be altered while the module is enabled.
- *
- *  \param[in] module_inst  Software instance for the ADC peripheral
- *  \param[in] events       Struct containing flags of events to disable
- */
-static inline void adc_disable_events(
-		struct adc_module *const module_inst,
-		struct adc_events *const events)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Adc *const adc_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= ADC_EVCTRL_WINMONEO;
-	}
-
-	/* Configure Result Ready event */
-	if (events->generate_event_on_conversion_done) {
-		event_mask |= ADC_EVCTRL_RESRDYEO;
-	}
-
-	adc_module->EVCTRL.reg &= ~event_mask;
-}
-
-/**
- * \brief Starts an ADC conversion.
- *
- * Starts a new ADC conversion.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- */
-static inline void adc_start_conversion(
-		struct adc_module *const module_inst)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-}
-
-/**
- * \brief Reads the ADC result.
- *
- * Reads the result from an ADC conversion that was previously started.
- *
- * \param[in]  module_inst  Pointer to the ADC software instance struct
- * \param[out] result       Pointer to store the result value in
- *
- * \return Status of the ADC read request.
- * \retval STATUS_OK           The result was retrieved successfully
- * \retval STATUS_BUSY         A conversion result was not ready
- * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the
- *                             ADC module before the result was read by the software
- */
-static inline enum status_code adc_read(
-		struct adc_module *const module_inst,
-		uint16_t *result)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(result);
-
-	if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
-		/* Result not ready */
-		return STATUS_BUSY;
-	}
-
-	Adc *const adc_module = module_inst->hw;
-
-#if (SAMD) || (SAMHA1) || (SAMHA0) || (SAMR21)
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-#endif
-
-	/* Get ADC result */
-	*result = adc_module->RESULT.reg;
-
-	/* Reset ready flag */
-	adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
-
-	if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
-		adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
-		return STATUS_ERR_OVERFLOW;
-	}
-
-	return STATUS_OK;
-}
-
-/** @} */
-
-/**
- * \name Runtime Changes of ADC Module
- * @{
- */
-
-/**
- * \brief Flushes the ADC pipeline.
- *
- * Flushes the pipeline and restarts the ADC clock on the next peripheral clock
- * edge. All conversions in progress will be lost. When flush is complete, the
- * module will resume where it left off.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- */
-static inline void adc_flush(
-		struct adc_module *const module_inst)
-{
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-}
-void adc_set_window_mode(
-		struct adc_module *const module_inst,
-		const enum adc_window_mode window_mode,
-		const int16_t window_lower_value,
-		const int16_t window_upper_value);
-
-/**
- * \brief Sets positive ADC input pin.
- *
- * Sets the positive ADC input pin selection.
- *
- * \param[in] module_inst     Pointer to the ADC software instance struct
- * \param[in] positive_input  Positive input pin
- */
-static inline void adc_set_positive_input(
-		struct adc_module *const module_inst,
-		const enum adc_positive_input positive_input)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set positive input pin */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
-			(positive_input);
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-}
-
-
-/**
- * \brief Sets negative ADC input pin for differential mode.
- *
- * Sets the negative ADC input pin, when the ADC is configured in differential
- * mode.
- *
- * \param[in] module_inst     Pointer to the ADC software instance struct
- * \param[in] negative_input  Negative input pin
- */
-static inline void adc_set_negative_input(
-		struct adc_module *const module_inst,
-		const enum adc_negative_input negative_input)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set negative input pin */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
-			(negative_input);
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-}
-
-/** @} */
-
-#if ADC_CALLBACK_MODE == true
-/**
- * \name Enable and Disable Interrupts
- * @{
- */
-
-/**
- * \brief Enable interrupt.
- *
- * Enable the given interrupt request from the ADC module.
- *
- * \param[in] module_inst Pointer to the ADC software instance struct
- * \param[in] interrupt Interrupt to enable
- */
-static inline void adc_enable_interrupt(struct adc_module *const module_inst,
-		enum adc_interrupt_flag interrupt)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-	/* Enable interrupt */
-	adc_module->INTENSET.reg = interrupt;
-}
-
-/**
- * \brief Disable interrupt.
- *
- * Disable the given interrupt request from the ADC module.
- *
- * \param[in] module_inst Pointer to the ADC software instance struct
- * \param[in] interrupt Interrupt to disable
- */
-static inline void adc_disable_interrupt(struct adc_module *const module_inst,
-		enum adc_interrupt_flag interrupt)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-	/* Enable interrupt */
-	adc_module->INTENCLR.reg = interrupt;
-}
-
-/** @} */
-#endif /* ADC_CALLBACK_MODE == true */
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-
-/**
- * \page asfdoc_sam0_adc_extra Extra Information for ADC Driver
- *
- * \section asfdoc_sam0_adc_extra_acronyms Acronyms
- * Below is a table listing the acronyms used in this module, along with their
- * intended meanings.
- *
- * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *  <tr>
- *		<td>ADC</td>
- *		<td>Analog-to-Digital Converter</td>
- *	</tr>
- *  <tr>
- *		<td>DAC</td>
- *		<td>Digital-to-Analog Converter</td>
- *	</tr>
- *	<tr>
- *		<td>LSB</td>
- *		<td>Least Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>MSB</td>
- *		<td>Most Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
- * </table>
- *
- *
- * \section asfdoc_sam0_adc_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
- *
- *
- * \section asfdoc_sam0_adc_extra_errata Errata
- * There are no errata related to this driver.
- *
- *
- * \section asfdoc_sam0_adc_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- * \if DEVICE_SAML21_SUPPORT
- *  <tr>
- *		<td>Initial Release</td>
- * </tr>
- * \else
- *	<tr>
- *		<td>Added support for SAM R21</td>
- *	</tr>
- *	<tr>
- *		<td>Added support for SAM D21 and new DMA quick start guide</td>
- *	</tr>
- *	<tr>
- *		<td>Added ADC calibration constant loading from the device signature
- *          row when the module is initialized</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
- * \endif
- * </table>
- */
-
-/**
- * \page asfdoc_sam0_adc_exqsg Examples for ADC Driver
- *
- * This is a list of the available Quick Start guides (QSGs) and example
- * applications for \ref asfdoc_sam0_adc_group. QSGs are simple examples with
- * step-by-step instructions to configure and use this driver in a selection of
- * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.
- *
- *  - \subpage asfdoc_sam0_adc_basic_use_case
- * \if ADC_CALLBACK_MODE
- *  - \subpage asfdoc_sam0_adc_basic_use_case_callback
- * \endif
- *  - \subpage asfdoc_sam0_adc_dma_use_case
- *
- * \page asfdoc_sam0_adc_document_revision_history Document Revision History
- *
- * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- * \if DEVICE_SAML21_SUPPORT
- *	<tr>
- *		<td>42451B</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L22</td>
- *	</tr>
- *  <tr>
- *      <td>42451A</td>
- *      <td>07/2015</td>
- *      <td>Initial document release</td>
- * </tr>
- * \else
- *	<tr>
- *		<td>42109E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM DA1 and SAM D09</td>
- *	</tr>
- *	<tr>
- *		<td>42109D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42109C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42109B</td>
- *		<td>06/2013</td>
- *		<td>Added additional documentation on the event system. Corrected
- *          documentation typos.</td>
- *	</tr>
- *	<tr>
- *		<td>42109A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
- * \endif
- * </table>
- */
-
-#endif /* ADC_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef ADC_H_INCLUDED
+#define ADC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_adc_group SAM Analog-to-Digital Converter (ADC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Analog-to-Digital Converter functionality, for
+ * the conversion of analog voltages into a corresponding digital form.
+ * The following driver Application Programming Interface (API) modes are covered by this manual:
+ * - Polled APIs
+ * \if ADC_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - ADC (Analog-to-Digital Converter)
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SUPPORT
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM R34/R35
+ * \else
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM HA1
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_adc_prerequisites
+ *  - \ref asfdoc_sam0_adc_module_overview
+ *  - \ref asfdoc_sam0_adc_special_considerations
+ *  - \ref asfdoc_sam0_adc_extra_info
+ *  - \ref asfdoc_sam0_adc_examples
+ *  - \ref asfdoc_sam0_adc_api_overview
+ *
+ *
+ * \section asfdoc_sam0_adc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_adc_module_overview Module Overview
+ *
+ * This driver provides an interface for the Analog-to-Digital conversion
+ * functions on the device, to convert analog voltages to a corresponding
+ * digital value. The ADC has up to 12-bit resolution, and is capable of
+ * \if DEVICE_SAML21_SUPPORT
+ * converting up to 1,000,000 samples per second (MSPS).
+ * \else
+ * converting up to 500K samples per second (KSPS).
+ * \endif
+ *
+ * The ADC has a compare function for accurate monitoring of user defined
+ * thresholds with minimum software intervention required.
+ * The ADC may be configured for 8-, 10-, or 12-bit result, reducing the
+ * conversion time. ADC conversion results are provided left or right adjusted
+ * which eases calculation when the result is represented as a signed integer.
+ *
+ * The input selection is flexible, and both single-ended and differential
+ * measurements can be made. For differential measurements, an optional gain
+ * stage is available to increase the dynamic range. In addition, several
+ * internal signal inputs are available. The ADC can provide both signed and
+ * unsigned results.
+ *
+ * The ADC measurements can either be started by application software or an
+ * incoming event from another peripheral in the device, and both internal and
+ * external reference voltages can be selected.
+ *
+ * \note Internal references will be enabled by the driver, but not disabled.
+ *       Any reference not used by the application should be disabled by the application.
+ *
+ * A simplified block diagram of the ADC can be seen in
+ * \ref asfdoc_sam0_adc_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_adc_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Positive input", shape=box];
+ * mux2 [label="Negative input", shape=box];
+ *
+ *
+ * mux3 [label="Reference", shape=box];
+ *
+ * adc [label="ADC", shape=polygon, sides=5, orientation=90, distortion=-0.6, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * prescaler [label="PRESCALER", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> adc;
+ * mux2 -> adc;
+ * mux3 -> adc:sw;
+ * prescaler -> adc;
+ *
+ * postproc [label="Post processing", shape=box];
+ * result [label="RESULT", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * adc:e -> postproc:w;
+ * postproc:e -> result:w;
+ *
+ * {rank=same; mux1 mux2}
+ * {rank=same; prescaler adc}
+ *
+ * }
+ * \enddot
+ *
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_prescaler Sample Clock Prescaler
+ * The ADC features a prescaler, which enables conversion at lower clock rates
+ * than the input Generic Clock to the ADC module. This feature can be used to
+ * lower the synchronization time of the digital interface to the ADC module
+ * via a high speed Generic Clock frequency, while still allowing the ADC
+ * sampling rate to be reduced.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_resolution ADC Resolution
+ * The ADC supports full 8-, 10-, or 12-bit resolution. Hardware
+ * oversampling and decimation can be used to increase the
+ * effective resolution at the expense of throughput. Using oversampling and
+ * decimation mode the ADC resolution is increased from 12-bit to an effective
+ * 13-, 14-, 15-, or 16-bit. In these modes the conversion rate is reduced, as
+ * a greater number of samples is used to achieve the increased resolution. The
+ * available resolutions and effective conversion rate is listed in
+ * \ref asfdoc_sam0_adc_module_conversion_rate "the table below".
+ *
+ * \anchor asfdoc_sam0_adc_module_conversion_rate
+ * <table>
+ *	<caption>Effective ADC Conversion Speed Using Oversampling</caption>
+ *	<tr>
+ *		<th>Resolution</th>
+ *		<th>Effective conversion rate</th>
+ *	</tr>
+ *	<tr>
+ *		<td>13-bit</td>
+ *		<td>Conversion rate divided by 4</td>
+ *	</tr>
+ *	<tr>
+ *		<td>14-bit</td>
+ *		<td>Conversion rate divided by 16</td>
+ *	</tr>
+ *	<tr>
+ *		<td>15-bit</td>
+ *		<td>Conversion rate divided by 64</td>
+ *	</tr>
+ *	<tr>
+ *		<td>16-bit</td>
+ *		<td>Conversion rate divided by 256</td>
+ *	</tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes
+ * ADC conversions can be software triggered on demand by the user application,
+ * if continuous sampling is not required. It is also possible to configure the
+ * ADC in free running mode, where new conversions are started as soon as the
+ * previous conversion is completed, or configure the ADC to scan across a
+ * number of input pins (see \ref asfdoc_sam0_adc_module_overview_pin_scan).
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_diff_mode Differential and Single-ended Conversion
+ * The ADC has two conversion modes; differential and single-ended. When
+ * measuring signals where the positive input pin is always at a higher voltage
+ * than the negative input pin, the single-ended conversion mode should be used
+ * in order to achieve a full 12-bit output resolution.
+ *
+ * If however the positive input pin voltage may drop below the negative input
+ * pin the signed differential mode should be used.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_sample_time Sample Time
+ * The sample time for each ADC conversion is configurable as a number of half
+ * prescaled ADC clock cycles (depending on the prescaler value), allowing the
+ * user application to achieve faster or slower sampling depending on the
+ * source impedance of the ADC input channels. For applications with high
+ * impedance inputs the sample time can be increased to give the ADC an adequate
+ * time to sample and convert the input channel.
+ *
+ * The resulting sampling time is given by the following equation:
+ * \f[
+ * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2}
+ * \f]
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging
+ * The ADC can be configured to trade conversion speed for accuracy by averaging
+ * multiple samples in hardware. This feature is suitable when operating in
+ * noisy conditions.
+ *
+ * You can specify any number of samples to accumulate (up to 1024) and the
+ * divide ratio to use (up to divide by 128). To modify these settings the
+ * ADC_RESOLUTION_CUSTOM needs to be set as the resolution. When this is set
+ * the number of samples to accumulate and the division ratio can be set by
+ * the configuration struct members \ref adc_config.accumulate_samples and
+ * \ref adc_config.divide_result. When using this mode the ADC result register
+ * will be set to be 16-bit wide to accommodate the larger result sizes
+ * produced by the accumulator.
+ *
+ * The effective ADC conversion rate will be reduced by a factor of the number
+ * of accumulated samples;
+ * however, the effective resolution will be increased according to
+ * \ref asfdoc_sam0_adc_module_hw_av_resolution "the table below".
+ *
+ * \anchor asfdoc_sam0_adc_module_hw_av_resolution
+ * <table>
+ *   <caption>Effective ADC Resolution From Various Hardware Averaging Modes</caption>
+ *   <tr>
+ *     <th>Number of samples</tr>
+ *     <th>Final result</tr>
+ *   </tr>
+ *   <tr>
+ *     <td>1</td>
+ *     <td>12-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>2</td>
+ *      <td>13-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>4</td>
+ *      <td>14-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>8</td>
+ *      <td>15-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>16</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>32</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>64</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>128</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>256</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>512</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ *   <tr>
+ *      <td>1024</td>
+ *      <td>16-bit</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_offset_corr Offset and Gain Correction
+ * Inherent gain and offset errors affect the absolute accuracy of the ADC.
+ *
+ * The offset error is defined as the deviation of the ADC's actual transfer
+ * function from ideal straight line at zero input voltage.
+ *
+ * The gain error is defined as the deviation of the last output step's
+ * midpoint from the ideal straight line, after compensating for offset error.
+ *
+ * The offset correction value is subtracted from the converted data before the
+ * result is ready. The gain correction value is multiplied with the offset
+ * corrected value.
+ *
+ * The equation for both offset and gain error compensation is shown below:
+ * \f[
+ * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN}
+ * \f]
+ *
+ * When enabled, a given set of offset and gain correction values can be applied
+ * to the sampled data in hardware, giving a corrected stream of sample data to
+ * the user application at the cost of an increased sample latency.
+ *
+ * In single conversion, a latency of 13 ADC Generic Clock cycles is added for
+ * the final sample result availability. As the correction time is always less
+ * than the propagation delay, in free running mode this latency appears only
+ * during the first conversion. After the first conversion is complete, future
+ * conversion results are available at the defined sampling rate.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_pin_scan Pin Scan
+ * In pin scan mode, the first ADC conversion will begin from the configured
+ * positive channel, plus the requested starting offset. When the first
+ * conversion is completed, the next conversion will start at the next positive
+ * input channel and so on, until all requested pins to scan have been sampled
+ * and converted.
+ * SAM L21/L22 has automatic sequences feature instead of pin scan mode. In automatic
+ * sequence mode, all of 32 positives inputs can be included in a sequence. The
+ * sequence starts from the lowest input, and go to the next enabled input
+ * automatically.
+ *
+ * Pin scanning gives a simple mechanism to sample a large number of physical
+ * input channel samples, using a single physical ADC channel.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_window_monitor Window Monitor
+ * The ADC module window monitor function can be used to automatically compare
+ * the conversion result against a preconfigured pair of upper and lower
+ * threshold values.
+ *
+ * The threshold values are evaluated differently, depending on whether
+ * differential or single-ended mode is selected. In differential mode, the
+ * upper and lower thresholds are evaluated as signed values for the comparison,
+ * while in single-ended mode the comparisons are made as a set of unsigned
+ * values.
+ *
+ * The significant bits of the lower window monitor threshold and upper window
+ * monitor threshold values are user-configurable, and follow the overall ADC
+ * sampling bit precision set when the ADC is configured by the user application.
+ * For example, only the eight lower bits of the window threshold values will be
+ * compared to the sampled data whilst the ADC is configured in 8-bit mode.
+ * In addition, if using differential mode, the 8<SUP>th</SUP> bit will be considered as
+ * the sign bit even if bit 9 is zero.
+ *
+ * \subsection asfdoc_sam0_adc_module_overview_events Events
+ * Event generation and event actions are configurable in the ADC.
+ *
+ * The ADC has two actions that can be triggered upon event reception:
+ * \li Start conversion
+ * \li Flush pipeline and start conversion
+ *
+ * The ADC can generate two events:
+ * \li Window monitor
+ * \li Result ready
+ *
+ * If the event actions are enabled in the configuration, any incoming event
+ * will trigger the action.
+ *
+ * If the window monitor event is enabled, an event will be generated
+ * when the configured window condition is detected.
+ *
+ * If the result ready event is enabled, an event will be generated when a
+ * conversion is completed.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ *
+ * \section asfdoc_sam0_adc_special_considerations Special Considerations
+ *
+ * An integrated analog temperature sensor is available for use with the ADC.
+ * The bandgap voltage, as well as the scaled I/O and core voltages can also be
+ * measured by the ADC. For internal ADC inputs, the internal source(s) may need
+ * to be manually enabled by the user application before they can be measured.
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_adc_extra. This includes:
+ *  - \ref asfdoc_sam0_adc_extra_acronyms
+ *  - \ref asfdoc_sam0_adc_extra_dependencies
+ *  - \ref asfdoc_sam0_adc_extra_errata
+ *  - \ref asfdoc_sam0_adc_extra_history
+ *
+ *
+ * \section asfdoc_sam0_adc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_adc_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_adc_api_overview API Overview
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <system.h>
+#include <adc_feature.h>
+
+/**
+ * \name Module Status Flags
+ *
+ * ADC status flags, returned by \ref adc_get_status() and cleared by
+ * \ref adc_clear_status().
+ *
+ * @{
+ */
+
+/** ADC result ready. */
+#define ADC_STATUS_RESULT_READY  (1UL << 0)
+/** Window monitor match. */
+#define ADC_STATUS_WINDOW        (1UL << 1)
+/** ADC result overwritten before read. */
+#define ADC_STATUS_OVERRUN       (1UL << 2)
+
+/** @} */
+
+#if ADC_CALLBACK_MODE == true
+#   if (ADC_INST_NUM > 1)
+#       define _ADC_INTERRUPT_VECT_NUM(n, unused) \
+			SYSTEM_INTERRUPT_MODULE_ADC##n,
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] The ADC module instance number
+ *
+ * \return Interrupt vector for of the given ADC module instance.
+ */
+static enum system_interrupt_vector _adc_interrupt_get_interrupt_vector(
+		uint32_t inst_num)
+{
+	static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = {
+		MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0)
+	};
+
+	return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num];
+}
+#   endif
+#endif
+
+#if !defined(__DOXYGEN__)
+uint8_t _adc_get_inst_index(
+		Adc *const hw);
+#endif
+
+/**
+ * \name Driver Initialization and Configuration
+ * @{
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config);
+
+void adc_get_config_defaults(
+		struct adc_config *const config);
+
+#if (SAMD) || (SAMHA1) || (SAMHA0) || (SAMR21)
+void adc_regular_ain_channel(
+		uint32_t *pin_array, uint8_t size);
+#endif
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ *
+ * \return Bitmask of \c ADC_STATUS_* flags.
+ *
+ * \retval ADC_STATUS_RESULT_READY  ADC result is ready to be read
+ * \retval ADC_STATUS_WINDOW        ADC has detected a value inside the set
+ *                                  window range
+ * \retval ADC_STATUS_OVERRUN       ADC result has overrun
+ */
+static inline uint32_t adc_get_status(
+		struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t int_flags = adc_module->INTFLAG.reg;
+
+	uint32_t status_flags = 0;
+
+	/* Check for ADC Result Ready */
+	if (int_flags & ADC_INTFLAG_RESRDY) {
+		status_flags |= ADC_STATUS_RESULT_READY;
+	}
+
+	/* Check for ADC Window Match */
+	if (int_flags & ADC_INTFLAG_WINMON) {
+		status_flags |= ADC_STATUS_WINDOW;
+	}
+
+	/* Check for ADC Overrun */
+	if (int_flags & ADC_INTFLAG_OVERRUN) {
+		status_flags |= ADC_STATUS_OVERRUN;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module_inst   Pointer to the ADC software instance struct
+ * \param[in] status_flags  Bitmask of \c ADC_STATUS_* flags to clear
+ */
+static inline void adc_clear_status(
+		struct adc_module *const module_inst,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t int_flags = 0;
+
+	/* Check for ADC Result Ready */
+	if (status_flags & ADC_STATUS_RESULT_READY) {
+		int_flags |= ADC_INTFLAG_RESRDY;
+	}
+
+	/* Check for ADC Window Match */
+	if (status_flags & ADC_STATUS_WINDOW) {
+		int_flags |= ADC_INTFLAG_WINMON;
+	}
+
+	/* Check for ADC Overrun */
+	if (status_flags & ADC_STATUS_OVERRUN) {
+		int_flags |= ADC_INTFLAG_OVERRUN;
+	}
+
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = int_flags;
+}
+/** @} */
+
+/**
+ * \name Enable, Disable, and Reset ADC Module, Start Conversion and Read Result
+ * @{
+ */
+
+/**
+ * \brief Enables the ADC module.
+ *
+ * Enables an ADC module that has previously been configured. If any internal reference
+ * is selected it will be enabled.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_enable(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+#if ADC_CALLBACK_MODE == true
+#   if (ADC_INST_NUM > 1)
+	system_interrupt_enable(_adc_interrupt_get_interrupt_vector(
+			_adc_get_inst_index(adc_module)));
+#   elif (SAMC20)
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0);
+#	else
+		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
+#   endif
+#endif
+
+	/* Disbale interrupt */
+	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+
+	adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables the ADC module.
+ *
+ * Disables an ADC module that was previously enabled.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_disable(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+#if ADC_CALLBACK_MODE == true
+#   if (ADC_INST_NUM > 1)
+	system_interrupt_disable(_adc_interrupt_get_interrupt_vector(
+			_adc_get_inst_index(adc_module)));
+#   elif (SAMC20)
+		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0);
+#	else
+		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
+#   endif
+#endif
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+
+	adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Resets the ADC module.
+ *
+ * Resets an ADC module, clearing all module state, and registers to their
+ * default values.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline enum status_code adc_reset(
+		struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	/* Disable to make sure the pipeline is flushed before reset */
+	adc_disable(module_inst);
+
+	/* Software reset the module */
+	adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+
+/**
+ * \brief Enables an ADC event input or output.
+ *
+ *  Enables one or more input or output events to or from the ADC module. See
+ *  \ref adc_events "Struct adc_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the ADC peripheral
+ *  \param[in] events       Struct containing flags of events to enable
+ */
+static inline void adc_enable_events(
+		struct adc_module *const module_inst,
+		struct adc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= ADC_EVCTRL_WINMONEO;
+	}
+
+	/* Configure Result Ready event */
+	if (events->generate_event_on_conversion_done) {
+		event_mask |= ADC_EVCTRL_RESRDYEO;
+	}
+
+	adc_module->EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables an ADC event input or output.
+ *
+ *  Disables one or more input or output events to or from the ADC module. See
+ *  \ref adc_events "Struct adc_events" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] module_inst  Software instance for the ADC peripheral
+ *  \param[in] events       Struct containing flags of events to disable
+ */
+static inline void adc_disable_events(
+		struct adc_module *const module_inst,
+		struct adc_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(events);
+
+	Adc *const adc_module = module_inst->hw;
+
+	uint32_t event_mask = 0;
+
+	/* Configure Window Monitor event */
+	if (events->generate_event_on_window_monitor) {
+		event_mask |= ADC_EVCTRL_WINMONEO;
+	}
+
+	/* Configure Result Ready event */
+	if (events->generate_event_on_conversion_done) {
+		event_mask |= ADC_EVCTRL_RESRDYEO;
+	}
+
+	adc_module->EVCTRL.reg &= ~event_mask;
+}
+
+/**
+ * \brief Starts an ADC conversion.
+ *
+ * Starts a new ADC conversion.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_start_conversion(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Reads the ADC result.
+ *
+ * Reads the result from an ADC conversion that was previously started.
+ *
+ * \param[in]  module_inst  Pointer to the ADC software instance struct
+ * \param[out] result       Pointer to store the result value in
+ *
+ * \return Status of the ADC read request.
+ * \retval STATUS_OK           The result was retrieved successfully
+ * \retval STATUS_BUSY         A conversion result was not ready
+ * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the
+ *                             ADC module before the result was read by the software
+ */
+static inline enum status_code adc_read(
+		struct adc_module *const module_inst,
+		uint16_t *result)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(result);
+
+	if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
+		/* Result not ready */
+		return STATUS_BUSY;
+	}
+
+	Adc *const adc_module = module_inst->hw;
+
+#if (SAMD) || (SAMHA1) || (SAMHA0) || (SAMR21)
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+#endif
+
+	/* Get ADC result */
+	*result = adc_module->RESULT.reg;
+
+	/* Reset ready flag */
+	adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
+
+	if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
+		adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
+		return STATUS_ERR_OVERFLOW;
+	}
+
+	return STATUS_OK;
+}
+
+/** @} */
+
+/**
+ * \name Runtime Changes of ADC Module
+ * @{
+ */
+
+/**
+ * \brief Flushes the ADC pipeline.
+ *
+ * Flushes the pipeline and restarts the ADC clock on the next peripheral clock
+ * edge. All conversions in progress will be lost. When flush is complete, the
+ * module will resume where it left off.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_flush(
+		struct adc_module *const module_inst)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+void adc_set_window_mode(
+		struct adc_module *const module_inst,
+		const enum adc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value);
+
+/**
+ * \brief Sets positive ADC input pin.
+ *
+ * Sets the positive ADC input pin selection.
+ *
+ * \param[in] module_inst     Pointer to the ADC software instance struct
+ * \param[in] positive_input  Positive input pin
+ */
+static inline void adc_set_positive_input(
+		struct adc_module *const module_inst,
+		const enum adc_positive_input positive_input)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set positive input pin */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
+			(positive_input);
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+
+/**
+ * \brief Sets negative ADC input pin for differential mode.
+ *
+ * Sets the negative ADC input pin, when the ADC is configured in differential
+ * mode.
+ *
+ * \param[in] module_inst     Pointer to the ADC software instance struct
+ * \param[in] negative_input  Negative input pin
+ */
+static inline void adc_set_negative_input(
+		struct adc_module *const module_inst,
+		const enum adc_negative_input negative_input)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set negative input pin */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
+			(negative_input);
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+/** @} */
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * \name Enable and Disable Interrupts
+ * @{
+ */
+
+/**
+ * \brief Enable interrupt.
+ *
+ * Enable the given interrupt request from the ADC module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] interrupt Interrupt to enable
+ */
+static inline void adc_enable_interrupt(struct adc_module *const module_inst,
+		enum adc_interrupt_flag interrupt)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+	/* Enable interrupt */
+	adc_module->INTENSET.reg = interrupt;
+}
+
+/**
+ * \brief Disable interrupt.
+ *
+ * Disable the given interrupt request from the ADC module.
+ *
+ * \param[in] module_inst Pointer to the ADC software instance struct
+ * \param[in] interrupt Interrupt to disable
+ */
+static inline void adc_disable_interrupt(struct adc_module *const module_inst,
+		enum adc_interrupt_flag interrupt)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+	/* Enable interrupt */
+	adc_module->INTENCLR.reg = interrupt;
+}
+
+/** @} */
+#endif /* ADC_CALLBACK_MODE == true */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+/**
+ * \page asfdoc_sam0_adc_extra Extra Information for ADC Driver
+ *
+ * \section asfdoc_sam0_adc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *  <tr>
+ *		<td>ADC</td>
+ *		<td>Analog-to-Digital Converter</td>
+ *	</tr>
+ *  <tr>
+ *		<td>DAC</td>
+ *		<td>Digital-to-Analog Converter</td>
+ *	</tr>
+ *	<tr>
+ *		<td>LSB</td>
+ *		<td>Least Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MSB</td>
+ *		<td>Most Significant Bit</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_adc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ * \if DEVICE_SAML21_SUPPORT
+ *  <tr>
+ *		<td>Initial Release</td>
+ * </tr>
+ * \else
+ *	<tr>
+ *		<td>Added support for SAM R21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for SAM D21 and new DMA quick start guide</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added ADC calibration constant loading from the device signature
+ *          row when the module is initialized</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * \endif
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_adc_exqsg Examples for ADC Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_adc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_adc_basic_use_case
+ * \if ADC_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_adc_basic_use_case_callback
+ * \endif
+ *  - \subpage asfdoc_sam0_adc_dma_use_case
+ *
+ * \page asfdoc_sam0_adc_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ * \if DEVICE_SAML21_SUPPORT
+ *	<tr>
+ *		<td>42451B</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L22</td>
+ *	</tr>
+ *  <tr>
+ *      <td>42451A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * \else
+ *	<tr>
+ *		<td>42109E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM DA1 and SAM D09</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109B</td>
+ *		<td>06/2013</td>
+ *		<td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42109A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * \endif
+ * </table>
+ */
+
+#endif /* ADC_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
index 32ce661..186fe05 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc.c
@@ -1,726 +1,726 @@
-/**
- * \file
- *
- * \brief SAM Peripheral Analog-to-Digital Converter Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "adc.h"
-
-#if SAMD20
-/* The Die revision D number */
-#define REVISON_D_NUM    3
-#endif
-
-/**
- * \brief Initializes an ADC configuration structure to defaults
- *
- * Initializes a given ADC configuration struct to a set of known default
- * values. This function should be called on any new instance of the
- * configuration struct before being modified by the user application.
- *
- * The default configuration is as follows:
- *  \li GCLK generator 0 (GCLK main) clock source
- *  \li 1V from internal bandgap reference
- *  \li Div 4 clock prescaler
- *  \li 12-bit resolution
- *  \li Window monitor disabled
- *  \li No gain
- *  \li Positive input on ADC PIN 0
- *  \li Negative input on ADC PIN 1
- *  \li Averaging disabled
- *  \li Oversampling disabled
- *  \li Right adjust data
- *  \li Single-ended mode
- *  \li Free running disabled
- *  \li All events (input and generation) disabled
- *  \li Sleep operation disabled
- *  \li No reference compensation
- *  \li No gain/offset correction
- *  \li No added sampling time
- *  \li Pin scan mode disabled
- *
- * \param[out] config  Pointer to configuration struct to initialize to
- *                     default values
- */
-void adc_get_config_defaults(struct adc_config *const config)
-{
-	Assert(config);
-	config->clock_source                  = GCLK_GENERATOR_0;
-	config->reference                     = ADC_REFERENCE_INT1V;
-	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
-	config->resolution                    = ADC_RESOLUTION_12BIT;
-	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
-	config->window.window_upper_value     = 0;
-	config->window.window_lower_value     = 0;
-	config->gain_factor                   = ADC_GAIN_FACTOR_1X;
-#if SAMR21
-	config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
-#else
- 	config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
-#endif
-	config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
-	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
-	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
-	config->left_adjust                   = false;
-	config->differential_mode             = false;
-	config->freerunning                   = false;
-	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
-	config->run_in_standby                = false;
-	config->reference_compensation_enable = false;
-	config->correction.correction_enable  = false;
-	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
-	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
-	config->sample_length                 = 0;
-	config->pin_scan.offset_start_scan    = 0;
-	config->pin_scan.inputs_to_scan       = 0;
-}
-
-/**
- * \brief Sets the ADC window mode
- *
- * Sets the ADC window mode to a given mode and value range.
- *
- * \param[in] module_inst         Pointer to the ADC software instance struct
- * \param[in] window_mode         Window monitor mode to set
- * \param[in] window_lower_value  Lower window monitor threshold value
- * \param[in] window_upper_value  Upper window monitor threshold value
-  */
-void adc_set_window_mode(
-		struct adc_module *const module_inst,
-		const enum adc_window_mode window_mode,
-		const int16_t window_lower_value,
-		const int16_t window_upper_value)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set window mode */
-	adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set lower window monitor threshold value */
-	adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set upper window monitor threshold value */
-	adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
-}
-
-/**
-* \internal Configure MUX settings for the analog pins
-*
-* This function will set the given ADC input pins
-* to the analog function in the pinmux, giving
-* the ADC access to the analog signal
-*
-* \param [in] pin AINxx pin to configure
-*/
-static inline void _adc_configure_ain_pin(uint32_t pin)
-{
-#define PIN_INVALID_ADC_AIN    0xFFFFUL
-
-	/* Pinmapping table for AINxx -> GPIO pin number */
-	const uint32_t pinmapping[] = {
-#if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-#elif SAMR21E
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-#elif SAMR21G
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-#elif (SAMD09C) || (SAMD10C) || (SAMD11C)
-			PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-#elif (SAMD09D)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-#elif (SAMD10DS) || (SAMD10DU) || (SAMD11DS) || (SAMD11DU)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-#elif (SAMD10DM) || (SAMD11DM)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_PA10B_ADC_AIN8,  PIN_PA11B_ADC_AIN9,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-#elif (SAMHA1G) || (SAMHA0G)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-#elif (SAMHA1E) || (SAMHA0E)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-#else
-#  error ADC pin mappings are not defined for this device.
-#endif
-		};
-
-	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
-
-	if (pin <= ADC_EXTCHANNEL_MSB) {
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
-
-		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
-
-		struct system_pinmux_config config;
-		system_pinmux_get_config_defaults(&config);
-
-		/* Analog functions are all on MUX setting B */
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-		config.mux_position = 1;
-
-		system_pinmux_pin_set_config(pin_map_result, &config);
-	}
-}
-
-/**
- * \internal Writes an ADC configuration to the hardware module
- *
- * Writes out a given ADC module configuration to the hardware module.
- *
- * \param[out] module_inst  Pointer to the ADC software instance struct
- * \param[in]  config       Pointer to configuration struct
- *
- * \return Status of the configuration procedure
- * \retval STATUS_OK               The configuration was successful
- * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
- */
-static enum status_code _adc_set_config(
-		struct adc_module *const module_inst,
-		struct adc_config *const config)
-{
-	uint8_t adjres = 0;
-	uint32_t resolution = ADC_RESOLUTION_16BIT;
-	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
-#if SAMD20
-	uint8_t revision_num = ((REG_DSU_DID & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos);
-#endif
-
-	/* Get the hardware module pointer */
-	Adc *const adc_module = module_inst->hw;
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(ADC_GCLK_ID);
-
-	/* Setup pinmuxing for analog inputs */
-	if (config->pin_scan.inputs_to_scan != 0) {
-		uint8_t offset = config->pin_scan.offset_start_scan;
-		uint8_t start_pin =
-				offset +(uint8_t)config->positive_input;
-		uint8_t end_pin =
-				start_pin + config->pin_scan.inputs_to_scan;
-
-		while (start_pin < end_pin) {
-			_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
-			start_pin++;
-			offset++;
-		}
-		_adc_configure_ain_pin(config->negative_input);
-	} else {
-		_adc_configure_ain_pin(config->positive_input);
-		_adc_configure_ain_pin(config->negative_input);
-	}
-
-	/* Configure run in standby */
-	adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
-
-	/* Configure reference */
-	adc_module->REFCTRL.reg =
-			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
-			(config->reference);
-
-	/* Set adjusting result and number of samples */
-	switch (config->resolution) {
-
-	case ADC_RESOLUTION_CUSTOM:
-		adjres = config->divide_result;
-		accumulate = config->accumulate_samples;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_13BIT:
-		/* Increase resolution by 1 bit */
-		adjres = ADC_DIVIDE_RESULT_2;
-		accumulate = ADC_ACCUMULATE_SAMPLES_4;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_14BIT:
-		/* Increase resolution by 2 bit */
-		adjres = ADC_DIVIDE_RESULT_4;
-		accumulate = ADC_ACCUMULATE_SAMPLES_16;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-#if SAMD20
-	/* See $35.1.8 for ADC errata of SAM D20.
-	   The revisions before D have this issue.*/
-	case ADC_RESOLUTION_15BIT:
-		/* Increase resolution by 3 bit */
-		if(revision_num < REVISON_D_NUM) {
-			adjres = ADC_DIVIDE_RESULT_8;
-		} else {
-			adjres = ADC_DIVIDE_RESULT_2;
-		}
-		accumulate = ADC_ACCUMULATE_SAMPLES_64;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_16BIT:
-		if(revision_num < REVISON_D_NUM) {
-			/* Increase resolution by 4 bit */
-			adjres = ADC_DIVIDE_RESULT_16;
-		} else {
-			adjres = ADC_DIVIDE_RESULT_DISABLE;
-		}
-		accumulate = ADC_ACCUMULATE_SAMPLES_256;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-#else
-	case ADC_RESOLUTION_15BIT:
-		/* Increase resolution by 3 bit */
-		adjres = ADC_DIVIDE_RESULT_2;
-		accumulate = ADC_ACCUMULATE_SAMPLES_64;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_16BIT:
-		/* Increase resolution by 4 bit */
-		adjres = ADC_DIVIDE_RESULT_DISABLE;
-		accumulate = ADC_ACCUMULATE_SAMPLES_256;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-#endif
-	case ADC_RESOLUTION_8BIT:
-		/* 8-bit result register */
-		resolution = ADC_RESOLUTION_8BIT;
-		break;
-	case ADC_RESOLUTION_10BIT:
-		/* 10-bit result register */
-		resolution = ADC_RESOLUTION_10BIT;
-		break;
-	case ADC_RESOLUTION_12BIT:
-		/* 12-bit result register */
-		resolution = ADC_RESOLUTION_12BIT;
-		break;
-
-	default:
-		/* Unknown. Abort. */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
-
-	/* Check validity of sample length value */
-	if (config->sample_length > 63) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		/* Configure sample length */
-		adc_module->SAMPCTRL.reg =
-				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure CTRLB */
-	adc_module->CTRLB.reg =
-			config->clock_prescaler |
-			resolution |
-			(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
-			(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
-			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
-			(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
-
-	/* Check validity of window thresholds */
-	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
-		switch (resolution) {
-		case ADC_RESOLUTION_8BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 127 ||
-					config->window.window_lower_value < -128 ||
-					config->window.window_upper_value > 127 ||
-					config->window.window_upper_value < -128)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 255 ||
-					config->window.window_upper_value > 255){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_10BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 511 ||
-					config->window.window_lower_value < -512 ||
-					config->window.window_upper_value > 511 ||
-					config->window.window_upper_value < -512)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 1023 ||
-					config->window.window_upper_value > 1023){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_12BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 2047 ||
-					config->window.window_lower_value < -2048 ||
-					config->window.window_upper_value > 2047 ||
-					config->window.window_upper_value < -2048)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 4095 ||
-					config->window.window_upper_value > 4095){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_16BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 32767 ||
-					config->window.window_lower_value < -32768 ||
-					config->window.window_upper_value > 32767 ||
-					config->window.window_upper_value < -32768)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 65535 ||
-					config->window.window_upper_value > 65535){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		}
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure window mode */
-	adc_module->WINCTRL.reg = config->window.window_mode;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	adc_module->WINLT.reg =
-			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	adc_module->WINUT.reg = config->window.window_upper_value <<
-			ADC_WINUT_WINUT_Pos;
-
-	uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
-	if (inputs_to_scan > 0) {
-		/*
-		* Number of input sources included is the value written to INPUTSCAN
-		* plus 1.
-		*/
-		inputs_to_scan--;
-	}
-
-	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
-			config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
-		/* Invalid number of input pins or input offset */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure pin scan mode and positive and negative input pins */
-	adc_module->INPUTCTRL.reg =
-			config->gain_factor |
-			(config->pin_scan.offset_start_scan <<
-			ADC_INPUTCTRL_INPUTOFFSET_Pos) |
-			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
-			config->negative_input |
-			config->positive_input;
-
-	/* Configure events */
-	adc_module->EVCTRL.reg = config->event_action;
-
-	/* Disable all interrupts */
-	adc_module->INTENCLR.reg =
-			(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
-			(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
-
-	if (config->correction.correction_enable){
-		/* Make sure gain_correction value is valid */
-		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
-			return STATUS_ERR_INVALID_ARG;
-		} else {
-			/* Set gain correction value */
-			adc_module->GAINCORR.reg = config->correction.gain_correction <<
-					ADC_GAINCORR_GAINCORR_Pos;
-		}
-
-		/* Make sure offset correction value is valid */
-		if (config->correction.offset_correction > 2047 ||
-				config->correction.offset_correction < -2048) {
-			return STATUS_ERR_INVALID_ARG;
-		} else {
-			/* Set offset correction value */
-			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
-					ADC_OFFSETCORR_OFFSETCORR_Pos;
-		}
-	}
-
-	/* Load in the fixed device ADC calibration constants */
-	adc_module->CALIB.reg =
-			ADC_CALIB_BIAS_CAL(
-				(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
-			) |
-			ADC_CALIB_LINEARITY_CAL(
-				(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
-			);
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Initializes the ADC channel sequence
- *
- * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one
- * automatically after a conversion done, causing the next conversion
- * to be done with the positive input equal to MUXPOS + INPUTOFFSET,
- * it is scanning continuously one by one even ADC channels are not continuous.
- *
- * Initializes the ADC channel sequence by the sequence of pin_array.
- *
- * \param[in]  pin_array   The array of the Mux selection for the positive ADC input
- * \param[in]  size        The size of pin_array
- */
-void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
-{
-	for (int i = 0; i < size; i++) {
-		_adc_configure_ain_pin(pin_array[i]);
-  	}
-}
-
-/**
- * \brief Initializes the ADC
- *
- * Initializes the ADC device struct and the hardware module based on the
- * given configuration struct values.
- *
- * \param[out] module_inst Pointer to the ADC software instance struct
- * \param[in]  hw          Pointer to the ADC module instance
- * \param[in]  config      Pointer to the configuration struct
- *
- * \return Status of the initialization procedure.
- * \retval STATUS_OK                The initialization was successful
- * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
- * \retval STATUS_BUSY          The module is busy with a reset operation
- * \retval STATUS_ERR_DENIED        The module is enabled
- */
-enum status_code adc_init(
-		struct adc_module *const module_inst,
-		Adc *hw,
-		struct adc_config *config)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
-
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
-
-	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
-
-	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Store the selected reference for later use */
-	module_inst->reference = config->reference;
-
-	/* Make sure bandgap is enabled if requested by the config */
-	if (module_inst->reference == ADC_REFERENCE_INT1V) {
-		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
-	}
-
-#if ADC_CALLBACK_MODE == true
-	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	};
-
-	module_inst->registered_callback_mask = 0;
-	module_inst->enabled_callback_mask = 0;
-	module_inst->remaining_conversions = 0;
-	module_inst->job_status = STATUS_OK;
-
-	_adc_instances[0] = module_inst;
-
-	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
-			!config->freerunning) {
-		module_inst->software_trigger = true;
-	} else {
-		module_inst->software_trigger = false;
-	}
-#endif
-
-	/* Write configuration to module */
-	return _adc_set_config(module_inst, config);
-}
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "adc.h"
+
+#if SAMD20
+/* The Die revision D number */
+#define REVISON_D_NUM    3
+#endif
+
+/**
+ * \brief Initializes an ADC configuration structure to defaults
+ *
+ * Initializes a given ADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li 1V from internal bandgap reference
+ *  \li Div 4 clock prescaler
+ *  \li 12-bit resolution
+ *  \li Window monitor disabled
+ *  \li No gain
+ *  \li Positive input on ADC PIN 0
+ *  \li Negative input on ADC PIN 1
+ *  \li Averaging disabled
+ *  \li Oversampling disabled
+ *  \li Right adjust data
+ *  \li Single-ended mode
+ *  \li Free running disabled
+ *  \li All events (input and generation) disabled
+ *  \li Sleep operation disabled
+ *  \li No reference compensation
+ *  \li No gain/offset correction
+ *  \li No added sampling time
+ *  \li Pin scan mode disabled
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+	config->reference                     = ADC_REFERENCE_INT1V;
+	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
+	config->resolution                    = ADC_RESOLUTION_12BIT;
+	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+	config->window.window_upper_value     = 0;
+	config->window.window_lower_value     = 0;
+	config->gain_factor                   = ADC_GAIN_FACTOR_1X;
+#if SAMR21
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
+#else
+ 	config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
+#endif
+	config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
+	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+	config->left_adjust                   = false;
+	config->differential_mode             = false;
+	config->freerunning                   = false;
+	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+	config->run_in_standby                = false;
+	config->reference_compensation_enable = false;
+	config->correction.correction_enable  = false;
+	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+	config->sample_length                 = 0;
+	config->pin_scan.offset_start_scan    = 0;
+	config->pin_scan.inputs_to_scan       = 0;
+}
+
+/**
+ * \brief Sets the ADC window mode
+ *
+ * Sets the ADC window mode to a given mode and value range.
+ *
+ * \param[in] module_inst         Pointer to the ADC software instance struct
+ * \param[in] window_mode         Window monitor mode to set
+ * \param[in] window_lower_value  Lower window monitor threshold value
+ * \param[in] window_upper_value  Upper window monitor threshold value
+  */
+void adc_set_window_mode(
+		struct adc_module *const module_inst,
+		const enum adc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set window mode */
+	adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set lower window monitor threshold value */
+	adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set upper window monitor threshold value */
+	adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
+}
+
+/**
+* \internal Configure MUX settings for the analog pins
+*
+* This function will set the given ADC input pins
+* to the analog function in the pinmux, giving
+* the ADC access to the analog signal
+*
+* \param [in] pin AINxx pin to configure
+*/
+static inline void _adc_configure_ain_pin(uint32_t pin)
+{
+#define PIN_INVALID_ADC_AIN    0xFFFFUL
+
+	/* Pinmapping table for AINxx -> GPIO pin number */
+	const uint32_t pinmapping[] = {
+#if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif SAMR21E
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif SAMR21G
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD09C) || (SAMD10C) || (SAMD11C)
+			PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD09D)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10DS) || (SAMD10DU) || (SAMD11DS) || (SAMD11DU)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMD10DM) || (SAMD11DM)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+			PIN_PA10B_ADC_AIN8,  PIN_PA11B_ADC_AIN9,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAMHA1G) || (SAMHA0G)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+#elif (SAMHA1E) || (SAMHA0E)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+#else
+#  error ADC pin mappings are not defined for this device.
+#endif
+		};
+
+	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+
+	if (pin <= ADC_EXTCHANNEL_MSB) {
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+
+		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+
+		struct system_pinmux_config config;
+		system_pinmux_get_config_defaults(&config);
+
+		/* Analog functions are all on MUX setting B */
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+		config.mux_position = 1;
+
+		system_pinmux_pin_set_config(pin_map_result, &config);
+	}
+}
+
+/**
+ * \internal Writes an ADC configuration to the hardware module
+ *
+ * Writes out a given ADC module configuration to the hardware module.
+ *
+ * \param[out] module_inst  Pointer to the ADC software instance struct
+ * \param[in]  config       Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure
+ * \retval STATUS_OK               The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
+ */
+static enum status_code _adc_set_config(
+		struct adc_module *const module_inst,
+		struct adc_config *const config)
+{
+	uint8_t adjres = 0;
+	uint32_t resolution = ADC_RESOLUTION_16BIT;
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+#if SAMD20
+	uint8_t revision_num = ((REG_DSU_DID & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos);
+#endif
+
+	/* Get the hardware module pointer */
+	Adc *const adc_module = module_inst->hw;
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
+	system_gclk_chan_enable(ADC_GCLK_ID);
+
+	/* Setup pinmuxing for analog inputs */
+	if (config->pin_scan.inputs_to_scan != 0) {
+		uint8_t offset = config->pin_scan.offset_start_scan;
+		uint8_t start_pin =
+				offset +(uint8_t)config->positive_input;
+		uint8_t end_pin =
+				start_pin + config->pin_scan.inputs_to_scan;
+
+		while (start_pin < end_pin) {
+			_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
+			start_pin++;
+			offset++;
+		}
+		_adc_configure_ain_pin(config->negative_input);
+	} else {
+		_adc_configure_ain_pin(config->positive_input);
+		_adc_configure_ain_pin(config->negative_input);
+	}
+
+	/* Configure run in standby */
+	adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
+
+	/* Configure reference */
+	adc_module->REFCTRL.reg =
+			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
+			(config->reference);
+
+	/* Set adjusting result and number of samples */
+	switch (config->resolution) {
+
+	case ADC_RESOLUTION_CUSTOM:
+		adjres = config->divide_result;
+		accumulate = config->accumulate_samples;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_13BIT:
+		/* Increase resolution by 1 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_4;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_14BIT:
+		/* Increase resolution by 2 bit */
+		adjres = ADC_DIVIDE_RESULT_4;
+		accumulate = ADC_ACCUMULATE_SAMPLES_16;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+#if SAMD20
+	/* See $35.1.8 for ADC errata of SAM D20.
+	   The revisions before D have this issue.*/
+	case ADC_RESOLUTION_15BIT:
+		/* Increase resolution by 3 bit */
+		if(revision_num < REVISON_D_NUM) {
+			adjres = ADC_DIVIDE_RESULT_8;
+		} else {
+			adjres = ADC_DIVIDE_RESULT_2;
+		}
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_16BIT:
+		if(revision_num < REVISON_D_NUM) {
+			/* Increase resolution by 4 bit */
+			adjres = ADC_DIVIDE_RESULT_16;
+		} else {
+			adjres = ADC_DIVIDE_RESULT_DISABLE;
+		}
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+#else
+	case ADC_RESOLUTION_15BIT:
+		/* Increase resolution by 3 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_16BIT:
+		/* Increase resolution by 4 bit */
+		adjres = ADC_DIVIDE_RESULT_DISABLE;
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+#endif
+	case ADC_RESOLUTION_8BIT:
+		/* 8-bit result register */
+		resolution = ADC_RESOLUTION_8BIT;
+		break;
+	case ADC_RESOLUTION_10BIT:
+		/* 10-bit result register */
+		resolution = ADC_RESOLUTION_10BIT;
+		break;
+	case ADC_RESOLUTION_12BIT:
+		/* 12-bit result register */
+		resolution = ADC_RESOLUTION_12BIT;
+		break;
+
+	default:
+		/* Unknown. Abort. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+	/* Check validity of sample length value */
+	if (config->sample_length > 63) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		/* Configure sample length */
+		adc_module->SAMPCTRL.reg =
+				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure CTRLB */
+	adc_module->CTRLB.reg =
+			config->clock_prescaler |
+			resolution |
+			(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
+			(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
+			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+			(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
+
+	/* Check validity of window thresholds */
+	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
+		switch (resolution) {
+		case ADC_RESOLUTION_8BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 127 ||
+					config->window.window_lower_value < -128 ||
+					config->window.window_upper_value > 127 ||
+					config->window.window_upper_value < -128)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 255 ||
+					config->window.window_upper_value > 255){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_10BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 511 ||
+					config->window.window_lower_value < -512 ||
+					config->window.window_upper_value > 511 ||
+					config->window.window_upper_value < -512)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 1023 ||
+					config->window.window_upper_value > 1023){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_12BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 2047 ||
+					config->window.window_lower_value < -2048 ||
+					config->window.window_upper_value > 2047 ||
+					config->window.window_upper_value < -2048)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 4095 ||
+					config->window.window_upper_value > 4095){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_16BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 32767 ||
+					config->window.window_lower_value < -32768 ||
+					config->window.window_upper_value > 32767 ||
+					config->window.window_upper_value < -32768)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 65535 ||
+					config->window.window_upper_value > 65535){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		}
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure window mode */
+	adc_module->WINCTRL.reg = config->window.window_mode;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINLT.reg =
+			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINUT.reg = config->window.window_upper_value <<
+			ADC_WINUT_WINUT_Pos;
+
+	uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
+	if (inputs_to_scan > 0) {
+		/*
+		* Number of input sources included is the value written to INPUTSCAN
+		* plus 1.
+		*/
+		inputs_to_scan--;
+	}
+
+	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+			config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+		/* Invalid number of input pins or input offset */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure pin scan mode and positive and negative input pins */
+	adc_module->INPUTCTRL.reg =
+			config->gain_factor |
+			(config->pin_scan.offset_start_scan <<
+			ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
+			config->negative_input |
+			config->positive_input;
+
+	/* Configure events */
+	adc_module->EVCTRL.reg = config->event_action;
+
+	/* Disable all interrupts */
+	adc_module->INTENCLR.reg =
+			(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
+			(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
+
+	if (config->correction.correction_enable){
+		/* Make sure gain_correction value is valid */
+		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set gain correction value */
+			adc_module->GAINCORR.reg = config->correction.gain_correction <<
+					ADC_GAINCORR_GAINCORR_Pos;
+		}
+
+		/* Make sure offset correction value is valid */
+		if (config->correction.offset_correction > 2047 ||
+				config->correction.offset_correction < -2048) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set offset correction value */
+			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+					ADC_OFFSETCORR_OFFSETCORR_Pos;
+		}
+	}
+
+	/* Load in the fixed device ADC calibration constants */
+	adc_module->CALIB.reg =
+			ADC_CALIB_BIAS_CAL(
+				(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
+			) |
+			ADC_CALIB_LINEARITY_CAL(
+				(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
+			);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the ADC channel sequence
+ *
+ * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one
+ * automatically after a conversion done, causing the next conversion
+ * to be done with the positive input equal to MUXPOS + INPUTOFFSET,
+ * it is scanning continuously one by one even ADC channels are not continuous.
+ *
+ * Initializes the ADC channel sequence by the sequence of pin_array.
+ *
+ * \param[in]  pin_array   The array of the Mux selection for the positive ADC input
+ * \param[in]  size        The size of pin_array
+ */
+void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
+{
+	for (int i = 0; i < size; i++) {
+		_adc_configure_ain_pin(pin_array[i]);
+  	}
+}
+
+/**
+ * \brief Initializes the ADC
+ *
+ * Initializes the ADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[out] module_inst Pointer to the ADC software instance struct
+ * \param[in]  hw          Pointer to the ADC module instance
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK                The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
+ * \retval STATUS_BUSY          The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED        The module is enabled
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
+
+	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Store the selected reference for later use */
+	module_inst->reference = config->reference;
+
+	/* Make sure bandgap is enabled if requested by the config */
+	if (module_inst->reference == ADC_REFERENCE_INT1V) {
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
+	}
+
+#if ADC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	};
+
+	module_inst->registered_callback_mask = 0;
+	module_inst->enabled_callback_mask = 0;
+	module_inst->remaining_conversions = 0;
+	module_inst->job_status = STATUS_OK;
+
+	_adc_instances[0] = module_inst;
+
+	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+			!config->freerunning) {
+		module_inst->software_trigger = true;
+	} else {
+		module_inst->software_trigger = false;
+	}
+#endif
+
+	/* Write configuration to module */
+	return _adc_set_config(module_inst, config);
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
index d715b9d..df95a96 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
@@ -1,718 +1,718 @@
-/**
- * \file
- *
- * \brief SAM ADC functionality
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef ADC_FEATURE_H_INCLUDED
-#define ADC_FEATURE_H_INCLUDED
-
-/**
- * \addtogroup asfdoc_sam0_adc_group
- * @{
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if ADC_CALLBACK_MODE == true
-#  include <system_interrupt.h>
-
-#if !defined(__DOXYGEN__)
-extern struct adc_module *_adc_instances[ADC_INST_NUM];
-#endif
-
-/** Forward definition of the device instance. */
-struct adc_module;
-
-/** Type of the callback functions. */
-typedef void (*adc_callback_t)(struct adc_module *const module);
-
-/**
- * \brief ADC Callback enum
- *
- * Callback types for ADC callback driver.
- *
- */
-enum adc_callback {
-	/** Callback for buffer received */
-	ADC_CALLBACK_READ_BUFFER,
-	/** Callback when window is hit */
-	ADC_CALLBACK_WINDOW,
-	/** Callback for error */
-	ADC_CALLBACK_ERROR,
-#  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	ADC_CALLBACK_N,
-#  endif
-};
-
-#endif
-
-/**
- * \brief ADC reference voltage enum
- *
- * Enum for the possible reference voltages for the ADC.
- *
- */
-enum adc_reference {
-	/** 1.0V voltage reference */
-	ADC_REFERENCE_INT1V   = ADC_REFCTRL_REFSEL_INT1V,
-	/** 1/1.48V<SUB>CC</SUB> reference */
-	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
-	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
-	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
-	/** External reference A */
-	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
-	/** External reference B */
-	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
-};
-
-/**
- * \brief ADC clock prescaler enum
- *
- * Enum for the possible clock prescaler values for the ADC.
- *
- */
-enum adc_clock_prescaler {
-	/** ADC clock division factor 4 */
-	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
-	/** ADC clock division factor 8 */
-	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
-	/** ADC clock division factor 16 */
-	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
-	/** ADC clock division factor 32 */
-	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
-	/** ADC clock division factor 64 */
-	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
-	/** ADC clock division factor 128 */
-	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
-	/** ADC clock division factor 256 */
-	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
-	/** ADC clock division factor 512 */
-	ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
-};
-
-/**
- * \brief ADC resolution enum
- *
- * Enum for the possible resolution values for the ADC.
- *
- */
-enum adc_resolution {
-	/** ADC 12-bit resolution */
-	ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
-	/** ADC 16-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
-	/** ADC 10-bit resolution */
-	ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
-	/** ADC 8-bit resolution */
-	ADC_RESOLUTION_8BIT  = ADC_CTRLB_RESSEL_8BIT,
-	/** ADC 13-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_13BIT,
-	/** ADC 14-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_14BIT,
-	/** ADC 15-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_15BIT,
-	/** ADC 16-bit result register for use with averaging. When using this mode
-	  * the ADC result register will be set to 16-bit wide, and the number of
-	  * samples to accumulate and the division factor is configured by the
-	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
-	  * members in the configuration struct.
-	  */
-	ADC_RESOLUTION_CUSTOM,
-};
-
-/**
- * \brief ADC window monitor mode enum
- *
- * Enum for the possible window monitor modes for the ADC.
- *
- */
-enum adc_window_mode {
-	/** No window mode */
-	ADC_WINDOW_MODE_DISABLE          = ADC_WINCTRL_WINMODE_DISABLE,
-	/** RESULT > WINLT */
-	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_WINCTRL_WINMODE_MODE1,
-	/** RESULT < WINUT */
-	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_WINCTRL_WINMODE_MODE2,
-	/** WINLT < RESULT < WINUT */
-	ADC_WINDOW_MODE_BETWEEN          = ADC_WINCTRL_WINMODE_MODE3,
-	/** !(WINLT < RESULT < WINUT) */
-	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
-};
-
-/**
- * \brief ADC gain factor selection enum
- *
- * Enum for the possible gain factor values for the ADC.
- *
- */
-enum adc_gain_factor {
-	/** 1x gain */
-	ADC_GAIN_FACTOR_1X   = ADC_INPUTCTRL_GAIN_1X,
-	/** 2x gain */
-	ADC_GAIN_FACTOR_2X   = ADC_INPUTCTRL_GAIN_2X,
-	/** 4x gain */
-	ADC_GAIN_FACTOR_4X   = ADC_INPUTCTRL_GAIN_4X,
-	/** 8x gain */
-	ADC_GAIN_FACTOR_8X   = ADC_INPUTCTRL_GAIN_8X,
-	/** 16x gain */
-	ADC_GAIN_FACTOR_16X  = ADC_INPUTCTRL_GAIN_16X,
-	/** 1/2x gain */
-	ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
-};
-
-/**
- * \brief ADC event action enum
- *
- * Enum for the possible actions to take on an incoming event.
- *
- */
-enum adc_event_action {
-	/** Event action disabled */
-	ADC_EVENT_ACTION_DISABLED         = 0,
-	/** Flush ADC and start conversion */
-	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
-	/** Start conversion */
-	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
-};
-
-/**
- * \brief ADC positive MUX input selection enum
- *
- * Enum for the possible positive MUX input selections for the ADC.
- *
- */
-enum adc_positive_input {
-	/** ADC0 pin */
-	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_PIN0,
-	/** ADC1 pin */
-	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_PIN1,
-	/** ADC2 pin */
-	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_PIN2,
-	/** ADC3 pin */
-	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_PIN3,
-	/** ADC4 pin */
-	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_PIN4,
-	/** ADC5 pin */
-	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_PIN5,
-	/** ADC6 pin */
-	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_PIN6,
-	/** ADC7 pin */
-	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_PIN7,
-	/** ADC8 pin */
-	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_PIN8,
-	/** ADC9 pin */
-	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_PIN9,
-	/** ADC10 pin */
-	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_PIN10,
-	/** ADC11 pin */
-	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_PIN11,
-	/** ADC12 pin */
-	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_PIN12,
-	/** ADC13 pin */
-	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_PIN13,
-	/** ADC14 pin */
-	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_PIN14,
-	/** ADC15 pin */
-	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_PIN15,
-	/** ADC16 pin */
-	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_PIN16,
-	/** ADC17 pin */
-	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_PIN17,
-	/** ADC18 pin */
-	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_PIN18,
-	/** ADC19 pin */
-	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_PIN19,
-	/** Temperature reference */
-	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
-	/** Bandgap voltage */
-	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
-	/** 1/4 scaled core supply */
-	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
-	/** 1/4 scaled I/O supply */
-	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
-	/** DAC input */
-	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
-};
-
-/**
- * \brief ADC negative Multiplexer(MUX) input selection enum
- *
- * Enum for the possible negative Multiplexer(MUX) input selections for the ADC.
- *
- */
-enum adc_negative_input {
-	/** ADC0 pin */
-	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_PIN0,
-	/** ADC1 pin */
-	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_PIN1,
-	/** ADC2 pin */
-	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_PIN2,
-	/** ADC3 pin */
-	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_PIN3,
-	/** ADC4 pin */
-	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_PIN4,
-	/** ADC5 pin */
-	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_PIN5,
-	/** ADC6 pin */
-	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_PIN6,
-	/** ADC7 pin */
-	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_PIN7,
-	/** Internal ground */
-	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG_GND,
-	/** I/O ground */
-	ADC_NEGATIVE_INPUT_IOGND         = ADC_INPUTCTRL_MUXNEG_IOGND,
-};
-
-/**
- * \brief ADC number of accumulated samples enum
- *
- * Enum for the possible numbers of ADC samples to accumulate.
- * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
- * resolution setting is used.
- *
- */
-enum adc_accumulate_samples {
-	/** No averaging */
-	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
-	/** Average 2 samples */
-	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
-	/** Average 4 samples */
-	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
-	/** Average 8 samples */
-	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
-	/** Average 16 samples */
-	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
-	/** Average 32 samples */
-	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
-	/** Average 64 samples */
-	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
-	/** Average 128 samples */
-	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
-	/** Average 256 samples */
-	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
-	/** Average 512 samples */
-	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
-	/** Average 1024 samples */
-	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
-};
-
-/**
- * \brief ADC possible dividers for the result register
- *
- * Enum for the possible division factors to use when accumulating
- * multiple samples. To keep the same resolution for the averaged
- * result and the actual input value, the division factor must
- * be equal to the number of samples accumulated. This setting is only
- * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
- */
-enum adc_divide_result {
-	/** Don't divide result register after accumulation */
-	ADC_DIVIDE_RESULT_DISABLE = 0,
-	/** Divide result register by 2 after accumulation */
-	ADC_DIVIDE_RESULT_2       = 1,
-	/** Divide result register by 4 after accumulation */
-	ADC_DIVIDE_RESULT_4       = 2,
-	/** Divide result register by 8 after accumulation */
-	ADC_DIVIDE_RESULT_8       = 3,
-	/** Divide result register by 16 after accumulation */
-	ADC_DIVIDE_RESULT_16      = 4,
-	/** Divide result register by 32 after accumulation */
-	ADC_DIVIDE_RESULT_32      = 5,
-	/** Divide result register by 64 after accumulation */
-	ADC_DIVIDE_RESULT_64      = 6,
-	/** Divide result register by 128 after accumulation */
-	ADC_DIVIDE_RESULT_128     = 7,
-};
-
-#if ADC_CALLBACK_MODE == true
-/**
- * Enum for the possible ADC interrupt flags.
- */
-enum adc_interrupt_flag {
-	/** ADC result ready */
-	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
-	/** Window monitor match */
-	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
-	/** ADC result overwritten before read */
-	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
-};
-#endif
-
-/**
- * \brief ADC oversampling and decimation enum
- *
- * Enum for the possible numbers of bits resolution can be increased by when
- * using oversampling and decimation.
- *
- */
-enum adc_oversampling_and_decimation {
-	/** Don't use oversampling and decimation mode */
-	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
-	/** 1-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
-	/** 2-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
-	/** 3-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
-	/** 4-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
-};
-
-/**
- * \brief Window monitor configuration structure
- *
- * Window monitor configuration structure.
- */
-struct adc_window_config {
-	/** Selected window mode */
-	enum adc_window_mode window_mode;
-	/** Lower window value */
-	int32_t window_lower_value;
-	/** Upper window value */
-	int32_t window_upper_value;
-};
-
-/**
- * \brief ADC event enable/disable structure.
- *
- * Event flags for the ADC module. This is used to enable and
- * disable events via \ref adc_enable_events() and \ref adc_disable_events().
- */
-struct adc_events {
-	/** Enable event generation on conversion done */
-	bool generate_event_on_conversion_done;
-	/** Enable event generation on window monitor */
-	bool generate_event_on_window_monitor;
-};
-
-/**
- * \brief Gain and offset correction configuration structure
- *
- * Gain and offset correction configuration structure.
- * Part of the \ref adc_config struct and will  be initialized by
- * \ref adc_get_config_defaults.
- */
-struct adc_correction_config {
-	/**
-	 * Enables correction for gain and offset based on values of gain_correction and
-	 * offset_correction if set to true
-	 */
-	bool correction_enable;
-	/**
-	 * This value defines how the ADC conversion result is compensated for gain
-	 * error before written to the result register. This is a fractional value,
-	 * 1-bit integer plus an 11-bit fraction, therefore
-	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
-	 * \c 0b010000000000 to \c 0b111111111111.
-	 */
-	uint16_t gain_correction;
-	/**
-	 * This value defines how the ADC conversion result is compensated for
-	 * offset error before written to the result register. This is a 12-bit
-	 * value in two's complement format.
-	 */
-	int16_t offset_correction;
-};
-
-/**
- * \brief Pin scan configuration structure
- *
- * Pin scan configuration structure. Part of the \ref adc_config struct and will
- * be initialized by \ref adc_get_config_defaults.
- */
-struct adc_pin_scan_config {
-	/**
-	 * Offset (relative to selected positive input) of the first input pin to be
-	 * used in pin scan mode
-	 */
-	uint8_t offset_start_scan;
-	/**
-	 * Number of input pins to scan in pin scan mode. A value below two will
-	 * disable pin scan mode.
-	 */
-	uint8_t inputs_to_scan;
-};
-
-/**
- * \brief ADC configuration structure
- *
- * Configuration structure for an ADC instance. This structure should be
- * initialized by the \ref adc_get_config_defaults()
- * function before being modified by the user application.
- */
-struct adc_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** Voltage reference */
-	enum adc_reference reference;
-	/** Clock prescaler */
-	enum adc_clock_prescaler clock_prescaler;
-	/** Result resolution */
-	enum adc_resolution resolution;
-	/** Gain factor */
-	enum adc_gain_factor gain_factor;
-	/** Positive Multiplexer (MUX) input */
-	enum adc_positive_input positive_input;
-	/** Negative MUX input. For singled-ended conversion mode, the negative
-	 * input must be connected to ground. This ground could be the internal
-	 * GND, IOGND or an external ground connected to a pin. */
-	enum adc_negative_input negative_input;
-	/** Number of ADC samples to accumulate when using the
-	 *  \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases,
-	 *  result resolution will be changed accordingly.
-	 */
-	enum adc_accumulate_samples accumulate_samples;
-	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
-	enum adc_divide_result divide_result;
-	/** Left adjusted result */
-	bool left_adjust;
-	/** Enables differential mode if true. 
-	 * if false, ADC will run in singled-ended mode. */
-	bool differential_mode;
-	/** Enables free running mode if true */
-	bool freerunning;
-	/** Enables ADC in standby sleep mode if true */
-	bool run_in_standby;
-	/**
-	 * Enables reference buffer offset compensation if true.
-	 * This will increase the accuracy of the gain stage, but decreases the input
-	 * impedance; therefore the startup time of the reference must be increased.
-	 */
-	bool reference_compensation_enable;
-	/**
-	 * This value (0-63) control the ADC sampling time in number of half ADC
-	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
-	 * controlling the ADC input impedance. Sampling time is set according to
-	 * the formula:
-	 * Sample time = (sample_length+1) * (ADCclk / 2).
-	 */
-	uint8_t sample_length;
-	/** Window monitor configuration structure */
-	struct adc_window_config window;
-	/** Gain and offset correction configuration structure */
-	struct adc_correction_config correction;
-	/** Event action to take on incoming event */
-	enum adc_event_action event_action;
-	/** Pin scan configuration structure */
-	struct adc_pin_scan_config pin_scan;
-};
-
-/**
- * \brief ADC software device instance structure.
- *
- * ADC software instance structure, used to retain software state information
- * of an associated hardware module instance.
- *
- * \note The fields of this structure should not be altered by the user
- *       application; they are reserved for module-internal use only.
- */
-struct adc_module {
-#if !defined(__DOXYGEN__)
-	/** Pointer to ADC hardware module */
-	Adc *hw;
-	/** Keep reference configuration so we know when enable is called */
-	enum adc_reference reference;
-#  if ADC_CALLBACK_MODE == true
-	/** Array to store callback functions */
-	adc_callback_t callback[ADC_CALLBACK_N];
-	/** Pointer to buffer used for ADC results */
-	volatile uint16_t *job_buffer;
-	/** Remaining number of conversions in current job */
-	volatile uint16_t remaining_conversions;
-	/** Bit mask for callbacks registered */
-	uint8_t registered_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enabled_callback_mask;
-	/** Holds the status of the ongoing or last conversion job */
-	volatile enum status_code job_status;
-	/** If software triggering is needed */
-	bool software_trigger;
-#  endif
-#endif
-};
-
-#if !defined(__DOXYGEN__)
-
-/**
- * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
- *
- * Checks to see if the underlying hardware peripheral module(s) are currently
- * synchronizing across multiple clock domains to the hardware bus. This
- * function can be used to delay further operations on a module until such time
- * that it is ready, to prevent blocking delays for synchronization in the
- * user application.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- *
- * \return Synchronization status of the underlying hardware module(s).
- *
- * \retval true if the module synchronization is ongoing
- * \retval false if the module has completed synchronization
- */
-static inline bool adc_is_syncing(
-	struct adc_module *const module_inst)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	Adc *const adc_module = module_inst->hw;
-
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-		return true;
-	}
-
-	return false;
-}
-#endif
-
-/**
- * \name ADC Gain and Pin Scan Mode
- * @{
- */
-
-/**
- * \brief Sets ADC gain factor
- *
- * Sets the ADC gain factor to a specified gain setting.
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- * \param[in] gain_factor  Gain factor value to set
- */
-static inline void adc_set_gain(
-		struct adc_module *const module_inst,
-		const enum adc_gain_factor gain_factor)
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set new gain factor */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
-			(gain_factor);
-}
-
-/**
- * \brief Sets the ADC pin scan mode
- *
- * Configures the pin scan mode of the ADC module. In pin scan mode, the first
- * conversion will start at the configured positive input + start_offset. When
- * a conversion is done, a conversion will start on the next input, until
- * \c inputs_to_scan number of conversions are made.
- *
- * \param[in] module_inst     Pointer to the ADC software instance struct
- * \param[in] inputs_to_scan  Number of input pins to perform a conversion on
- *                            (must be two or more)
- * \param[in] start_offset    Offset of first pin to scan (relative to
- *                            configured positive input)
- *
- * \return Status of the pin scan configuration set request.
- *
- * \retval STATUS_OK               Pin scan mode has been set successfully
- * \retval STATUS_ERR_INVALID_ARG  Number of input pins to scan or offset has
- *                                 an invalid value
- */
-static inline enum status_code adc_set_pin_scan_mode(
-		struct adc_module *const module_inst,
-		uint8_t inputs_to_scan,
-		const uint8_t start_offset)
-
-{
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	if (inputs_to_scan > 0) {
-		/*
-		* Number of input sources included is the value written to INPUTSCAN
-		* plus 1.
-		*/
-		inputs_to_scan--;
-	}
-
-	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
-			start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
-		/* Invalid number of input pins */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set pin scan mode */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg &
-			~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
-			(start_offset   << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
-			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Disables pin scan mode
- *
- * Disables pin scan mode. The next conversion will be made on only one pin
- * (the configured positive input pin).
- *
- * \param[in] module_inst  Pointer to the ADC software instance struct
- */
-static inline void adc_disable_pin_scan_mode(
-		struct adc_module *const module_inst)
-{
-	/* Disable pin scan mode */
-	adc_set_pin_scan_mode(module_inst, 0, 0);
-}
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-#endif /* ADC_FEATURE_H_INCLUDED */
-
+/**
+ * \file
+ *
+ * \brief SAM ADC functionality
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef ADC_FEATURE_H_INCLUDED
+#define ADC_FEATURE_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if ADC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct adc_module *_adc_instances[ADC_INST_NUM];
+#endif
+
+/** Forward definition of the device instance. */
+struct adc_module;
+
+/** Type of the callback functions. */
+typedef void (*adc_callback_t)(struct adc_module *const module);
+
+/**
+ * \brief ADC Callback enum
+ *
+ * Callback types for ADC callback driver.
+ *
+ */
+enum adc_callback {
+	/** Callback for buffer received */
+	ADC_CALLBACK_READ_BUFFER,
+	/** Callback when window is hit */
+	ADC_CALLBACK_WINDOW,
+	/** Callback for error */
+	ADC_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	ADC_CALLBACK_N,
+#  endif
+};
+
+#endif
+
+/**
+ * \brief ADC reference voltage enum
+ *
+ * Enum for the possible reference voltages for the ADC.
+ *
+ */
+enum adc_reference {
+	/** 1.0V voltage reference */
+	ADC_REFERENCE_INT1V   = ADC_REFCTRL_REFSEL_INT1V,
+	/** 1/1.48V<SUB>CC</SUB> reference */
+	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
+	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+	/** External reference A */
+	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
+	/** External reference B */
+	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
+};
+
+/**
+ * \brief ADC clock prescaler enum
+ *
+ * Enum for the possible clock prescaler values for the ADC.
+ *
+ */
+enum adc_clock_prescaler {
+	/** ADC clock division factor 4 */
+	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
+	/** ADC clock division factor 8 */
+	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
+	/** ADC clock division factor 16 */
+	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
+	/** ADC clock division factor 32 */
+	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
+	/** ADC clock division factor 64 */
+	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
+	/** ADC clock division factor 128 */
+	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+	/** ADC clock division factor 256 */
+	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+	/** ADC clock division factor 512 */
+	ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
+};
+
+/**
+ * \brief ADC resolution enum
+ *
+ * Enum for the possible resolution values for the ADC.
+ *
+ */
+enum adc_resolution {
+	/** ADC 12-bit resolution */
+	ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
+	/** ADC 16-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
+	/** ADC 10-bit resolution */
+	ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
+	/** ADC 8-bit resolution */
+	ADC_RESOLUTION_8BIT  = ADC_CTRLB_RESSEL_8BIT,
+	/** ADC 13-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_13BIT,
+	/** ADC 14-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_14BIT,
+	/** ADC 15-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_15BIT,
+	/** ADC 16-bit result register for use with averaging. When using this mode
+	  * the ADC result register will be set to 16-bit wide, and the number of
+	  * samples to accumulate and the division factor is configured by the
+	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+	  * members in the configuration struct.
+	  */
+	ADC_RESOLUTION_CUSTOM,
+};
+
+/**
+ * \brief ADC window monitor mode enum
+ *
+ * Enum for the possible window monitor modes for the ADC.
+ *
+ */
+enum adc_window_mode {
+	/** No window mode */
+	ADC_WINDOW_MODE_DISABLE          = ADC_WINCTRL_WINMODE_DISABLE,
+	/** RESULT > WINLT */
+	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_WINCTRL_WINMODE_MODE1,
+	/** RESULT < WINUT */
+	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_WINCTRL_WINMODE_MODE2,
+	/** WINLT < RESULT < WINUT */
+	ADC_WINDOW_MODE_BETWEEN          = ADC_WINCTRL_WINMODE_MODE3,
+	/** !(WINLT < RESULT < WINUT) */
+	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
+};
+
+/**
+ * \brief ADC gain factor selection enum
+ *
+ * Enum for the possible gain factor values for the ADC.
+ *
+ */
+enum adc_gain_factor {
+	/** 1x gain */
+	ADC_GAIN_FACTOR_1X   = ADC_INPUTCTRL_GAIN_1X,
+	/** 2x gain */
+	ADC_GAIN_FACTOR_2X   = ADC_INPUTCTRL_GAIN_2X,
+	/** 4x gain */
+	ADC_GAIN_FACTOR_4X   = ADC_INPUTCTRL_GAIN_4X,
+	/** 8x gain */
+	ADC_GAIN_FACTOR_8X   = ADC_INPUTCTRL_GAIN_8X,
+	/** 16x gain */
+	ADC_GAIN_FACTOR_16X  = ADC_INPUTCTRL_GAIN_16X,
+	/** 1/2x gain */
+	ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
+};
+
+/**
+ * \brief ADC event action enum
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum adc_event_action {
+	/** Event action disabled */
+	ADC_EVENT_ACTION_DISABLED         = 0,
+	/** Flush ADC and start conversion */
+	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
+	/** Start conversion */
+	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief ADC positive MUX input selection enum
+ *
+ * Enum for the possible positive MUX input selections for the ADC.
+ *
+ */
+enum adc_positive_input {
+	/** ADC0 pin */
+	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_PIN0,
+	/** ADC1 pin */
+	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_PIN1,
+	/** ADC2 pin */
+	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_PIN2,
+	/** ADC3 pin */
+	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_PIN3,
+	/** ADC4 pin */
+	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_PIN4,
+	/** ADC5 pin */
+	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_PIN5,
+	/** ADC6 pin */
+	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_PIN6,
+	/** ADC7 pin */
+	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_PIN7,
+	/** ADC8 pin */
+	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_PIN8,
+	/** ADC9 pin */
+	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_PIN9,
+	/** ADC10 pin */
+	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_PIN10,
+	/** ADC11 pin */
+	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_PIN11,
+	/** ADC12 pin */
+	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_PIN12,
+	/** ADC13 pin */
+	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_PIN13,
+	/** ADC14 pin */
+	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_PIN14,
+	/** ADC15 pin */
+	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_PIN15,
+	/** ADC16 pin */
+	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_PIN16,
+	/** ADC17 pin */
+	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_PIN17,
+	/** ADC18 pin */
+	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_PIN18,
+	/** ADC19 pin */
+	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_PIN19,
+	/** Temperature reference */
+	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
+	/** Bandgap voltage */
+	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+	/** 1/4 scaled core supply */
+	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+	/** 1/4 scaled I/O supply */
+	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+	/** DAC input */
+	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
+};
+
+/**
+ * \brief ADC negative Multiplexer(MUX) input selection enum
+ *
+ * Enum for the possible negative Multiplexer(MUX) input selections for the ADC.
+ *
+ */
+enum adc_negative_input {
+	/** ADC0 pin */
+	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_PIN0,
+	/** ADC1 pin */
+	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_PIN1,
+	/** ADC2 pin */
+	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_PIN2,
+	/** ADC3 pin */
+	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_PIN3,
+	/** ADC4 pin */
+	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_PIN4,
+	/** ADC5 pin */
+	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_PIN5,
+	/** ADC6 pin */
+	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_PIN6,
+	/** ADC7 pin */
+	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_PIN7,
+	/** Internal ground */
+	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG_GND,
+	/** I/O ground */
+	ADC_NEGATIVE_INPUT_IOGND         = ADC_INPUTCTRL_MUXNEG_IOGND,
+};
+
+/**
+ * \brief ADC number of accumulated samples enum
+ *
+ * Enum for the possible numbers of ADC samples to accumulate.
+ * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
+ * resolution setting is used.
+ *
+ */
+enum adc_accumulate_samples {
+	/** No averaging */
+	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
+	/** Average 2 samples */
+	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
+	/** Average 4 samples */
+	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
+	/** Average 8 samples */
+	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
+	/** Average 16 samples */
+	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
+	/** Average 32 samples */
+	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
+	/** Average 64 samples */
+	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
+	/** Average 128 samples */
+	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
+	/** Average 256 samples */
+	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
+	/** Average 512 samples */
+	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
+	/** Average 1024 samples */
+	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+};
+
+/**
+ * \brief ADC possible dividers for the result register
+ *
+ * Enum for the possible division factors to use when accumulating
+ * multiple samples. To keep the same resolution for the averaged
+ * result and the actual input value, the division factor must
+ * be equal to the number of samples accumulated. This setting is only
+ * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
+ */
+enum adc_divide_result {
+	/** Don't divide result register after accumulation */
+	ADC_DIVIDE_RESULT_DISABLE = 0,
+	/** Divide result register by 2 after accumulation */
+	ADC_DIVIDE_RESULT_2       = 1,
+	/** Divide result register by 4 after accumulation */
+	ADC_DIVIDE_RESULT_4       = 2,
+	/** Divide result register by 8 after accumulation */
+	ADC_DIVIDE_RESULT_8       = 3,
+	/** Divide result register by 16 after accumulation */
+	ADC_DIVIDE_RESULT_16      = 4,
+	/** Divide result register by 32 after accumulation */
+	ADC_DIVIDE_RESULT_32      = 5,
+	/** Divide result register by 64 after accumulation */
+	ADC_DIVIDE_RESULT_64      = 6,
+	/** Divide result register by 128 after accumulation */
+	ADC_DIVIDE_RESULT_128     = 7,
+};
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * Enum for the possible ADC interrupt flags.
+ */
+enum adc_interrupt_flag {
+	/** ADC result ready */
+	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+	/** Window monitor match */
+	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
+	/** ADC result overwritten before read */
+	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
+};
+#endif
+
+/**
+ * \brief ADC oversampling and decimation enum
+ *
+ * Enum for the possible numbers of bits resolution can be increased by when
+ * using oversampling and decimation.
+ *
+ */
+enum adc_oversampling_and_decimation {
+	/** Don't use oversampling and decimation mode */
+	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+	/** 1-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+	/** 2-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+	/** 3-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+	/** 4-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+};
+
+/**
+ * \brief Window monitor configuration structure
+ *
+ * Window monitor configuration structure.
+ */
+struct adc_window_config {
+	/** Selected window mode */
+	enum adc_window_mode window_mode;
+	/** Lower window value */
+	int32_t window_lower_value;
+	/** Upper window value */
+	int32_t window_upper_value;
+};
+
+/**
+ * \brief ADC event enable/disable structure.
+ *
+ * Event flags for the ADC module. This is used to enable and
+ * disable events via \ref adc_enable_events() and \ref adc_disable_events().
+ */
+struct adc_events {
+	/** Enable event generation on conversion done */
+	bool generate_event_on_conversion_done;
+	/** Enable event generation on window monitor */
+	bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief Gain and offset correction configuration structure
+ *
+ * Gain and offset correction configuration structure.
+ * Part of the \ref adc_config struct and will  be initialized by
+ * \ref adc_get_config_defaults.
+ */
+struct adc_correction_config {
+	/**
+	 * Enables correction for gain and offset based on values of gain_correction and
+	 * offset_correction if set to true
+	 */
+	bool correction_enable;
+	/**
+	 * This value defines how the ADC conversion result is compensated for gain
+	 * error before written to the result register. This is a fractional value,
+	 * 1-bit integer plus an 11-bit fraction, therefore
+	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+	 * \c 0b010000000000 to \c 0b111111111111.
+	 */
+	uint16_t gain_correction;
+	/**
+	 * This value defines how the ADC conversion result is compensated for
+	 * offset error before written to the result register. This is a 12-bit
+	 * value in two's complement format.
+	 */
+	int16_t offset_correction;
+};
+
+/**
+ * \brief Pin scan configuration structure
+ *
+ * Pin scan configuration structure. Part of the \ref adc_config struct and will
+ * be initialized by \ref adc_get_config_defaults.
+ */
+struct adc_pin_scan_config {
+	/**
+	 * Offset (relative to selected positive input) of the first input pin to be
+	 * used in pin scan mode
+	 */
+	uint8_t offset_start_scan;
+	/**
+	 * Number of input pins to scan in pin scan mode. A value below two will
+	 * disable pin scan mode.
+	 */
+	uint8_t inputs_to_scan;
+};
+
+/**
+ * \brief ADC configuration structure
+ *
+ * Configuration structure for an ADC instance. This structure should be
+ * initialized by the \ref adc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Voltage reference */
+	enum adc_reference reference;
+	/** Clock prescaler */
+	enum adc_clock_prescaler clock_prescaler;
+	/** Result resolution */
+	enum adc_resolution resolution;
+	/** Gain factor */
+	enum adc_gain_factor gain_factor;
+	/** Positive Multiplexer (MUX) input */
+	enum adc_positive_input positive_input;
+	/** Negative MUX input. For singled-ended conversion mode, the negative
+	 * input must be connected to ground. This ground could be the internal
+	 * GND, IOGND or an external ground connected to a pin. */
+	enum adc_negative_input negative_input;
+	/** Number of ADC samples to accumulate when using the
+	 *  \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases,
+	 *  result resolution will be changed accordingly.
+	 */
+	enum adc_accumulate_samples accumulate_samples;
+	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
+	enum adc_divide_result divide_result;
+	/** Left adjusted result */
+	bool left_adjust;
+	/** Enables differential mode if true. 
+	 * if false, ADC will run in singled-ended mode. */
+	bool differential_mode;
+	/** Enables free running mode if true */
+	bool freerunning;
+	/** Enables ADC in standby sleep mode if true */
+	bool run_in_standby;
+	/**
+	 * Enables reference buffer offset compensation if true.
+	 * This will increase the accuracy of the gain stage, but decreases the input
+	 * impedance; therefore the startup time of the reference must be increased.
+	 */
+	bool reference_compensation_enable;
+	/**
+	 * This value (0-63) control the ADC sampling time in number of half ADC
+	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+	 * controlling the ADC input impedance. Sampling time is set according to
+	 * the formula:
+	 * Sample time = (sample_length+1) * (ADCclk / 2).
+	 */
+	uint8_t sample_length;
+	/** Window monitor configuration structure */
+	struct adc_window_config window;
+	/** Gain and offset correction configuration structure */
+	struct adc_correction_config correction;
+	/** Event action to take on incoming event */
+	enum adc_event_action event_action;
+	/** Pin scan configuration structure */
+	struct adc_pin_scan_config pin_scan;
+};
+
+/**
+ * \brief ADC software device instance structure.
+ *
+ * ADC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct adc_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to ADC hardware module */
+	Adc *hw;
+	/** Keep reference configuration so we know when enable is called */
+	enum adc_reference reference;
+#  if ADC_CALLBACK_MODE == true
+	/** Array to store callback functions */
+	adc_callback_t callback[ADC_CALLBACK_N];
+	/** Pointer to buffer used for ADC results */
+	volatile uint16_t *job_buffer;
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback_mask;
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status;
+	/** If software triggering is needed */
+	bool software_trigger;
+#  endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static inline bool adc_is_syncing(
+	struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+
+	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
+		return true;
+	}
+
+	return false;
+}
+#endif
+
+/**
+ * \name ADC Gain and Pin Scan Mode
+ * @{
+ */
+
+/**
+ * \brief Sets ADC gain factor
+ *
+ * Sets the ADC gain factor to a specified gain setting.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ * \param[in] gain_factor  Gain factor value to set
+ */
+static inline void adc_set_gain(
+		struct adc_module *const module_inst,
+		const enum adc_gain_factor gain_factor)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set new gain factor */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
+			(gain_factor);
+}
+
+/**
+ * \brief Sets the ADC pin scan mode
+ *
+ * Configures the pin scan mode of the ADC module. In pin scan mode, the first
+ * conversion will start at the configured positive input + start_offset. When
+ * a conversion is done, a conversion will start on the next input, until
+ * \c inputs_to_scan number of conversions are made.
+ *
+ * \param[in] module_inst     Pointer to the ADC software instance struct
+ * \param[in] inputs_to_scan  Number of input pins to perform a conversion on
+ *                            (must be two or more)
+ * \param[in] start_offset    Offset of first pin to scan (relative to
+ *                            configured positive input)
+ *
+ * \return Status of the pin scan configuration set request.
+ *
+ * \retval STATUS_OK               Pin scan mode has been set successfully
+ * \retval STATUS_ERR_INVALID_ARG  Number of input pins to scan or offset has
+ *                                 an invalid value
+ */
+static inline enum status_code adc_set_pin_scan_mode(
+		struct adc_module *const module_inst,
+		uint8_t inputs_to_scan,
+		const uint8_t start_offset)
+
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	if (inputs_to_scan > 0) {
+		/*
+		* Number of input sources included is the value written to INPUTSCAN
+		* plus 1.
+		*/
+		inputs_to_scan--;
+	}
+
+	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+			start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
+		/* Invalid number of input pins */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set pin scan mode */
+	adc_module->INPUTCTRL.reg =
+			(adc_module->INPUTCTRL.reg &
+			~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
+			(start_offset   << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables pin scan mode
+ *
+ * Disables pin scan mode. The next conversion will be made on only one pin
+ * (the configured positive input pin).
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_disable_pin_scan_mode(
+		struct adc_module *const module_inst)
+{
+	/* Disable pin scan mode */
+	adc_set_pin_scan_mode(module_inst, 0, 0);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_FEATURE_H_INCLUDED */
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.c
index 9a05a7e..23873ce 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.c
@@ -1,644 +1,644 @@
-/*
- * \file
- *
- * \brief SAM Direct Memory Access Controller Driver
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include <string.h>
-#include "dma.h"
-#include "clock.h"
-#include "system_interrupt.h"
-
-struct _dma_module {
-	volatile bool _dma_init;
-	volatile uint32_t allocated_channels;
-	uint8_t free_channels;
-};
-
-struct _dma_module _dma_inst = {
-	._dma_init = false,
-	.allocated_channels = 0,
-	.free_channels = CONF_MAX_USED_CHANNEL_NUM,
-};
-
-/** Maximum retry counter for resuming a job transfer. */
-#define MAX_JOB_RESUME_COUNT    10000
-
-/** DMA channel mask. */
-#define DMA_CHANNEL_MASK   (0x1f)
-
-COMPILER_ALIGNED(16)
-DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
-
-/** Initial write back memory section. */
-COMPILER_ALIGNED(16)
-static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
-
-/** Internal DMA resource pool. */
-static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
-
-/* DMA channel interrup flag. */
-uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]={0};
-
-/**
- * \brief Find a free channel for a DMA resource.
- *
- * Find a channel for the requested DMA resource.
- *
- * \return Status of channel allocation.
- * \retval DMA_INVALID_CHANNEL  No channel available
- * \retval count          Allocated channel for the DMA resource
- */
-static uint8_t _dma_find_first_free_channel_and_allocate(void)
-{
-	uint8_t count;
-	uint32_t tmp;
-	bool allocated = false;
-
-	system_interrupt_enter_critical_section();
-
-	tmp = _dma_inst.allocated_channels;
-
-	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
-		if (!(tmp & 0x00000001)) {
-			/* If free channel found, set as allocated and return
-			 *number */
-
-			_dma_inst.allocated_channels |= 1 << count;
-			_dma_inst.free_channels--;
-			allocated = true;
-
-			break;
-		}
-
-		tmp = tmp >> 1;
-	}
-
-	system_interrupt_leave_critical_section();
-
-	if (!allocated) {
-		return DMA_INVALID_CHANNEL;
-	} else {
-		return count;
-	}
-}
-
-/**
- * \brief Release an allocated DMA channel.
- *
- * \param[in]  channel  Channel id to be released
- *
- */
-static void _dma_release_channel(uint8_t channel)
-{
-	_dma_inst.allocated_channels &= ~(1 << channel);
-	_dma_inst.free_channels++;
-}
-
-/**
- * \brief Configure the DMA resource.
- *
- * \param[in]  dma_resource Pointer to a DMA resource instance
- * \param[out] resource_config Configurations of the DMA resource
- *
- */
-static void _dma_set_config(struct dma_resource *resource,
-		struct dma_resource_config *resource_config)
-{
-	Assert(resource);
-	Assert(resource_config);
-	uint32_t temp_CHCTRLB_reg;
-	system_interrupt_enter_critical_section();
-
-	/** Select the DMA channel and clear software trigger */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
-
-	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
-			DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
-			DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
-
-
-	if(resource_config->event_config.input_action){
-	temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
-				resource_config->event_config.input_action);
-	}
-
-	/** Enable event output, the event output selection is configured in
-	 * each transfer descriptor  */
-	if (resource_config->event_config.event_output_enable) {
-		temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
-	}
-
-	/* Write config to CTRLB register */
-	DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
-
-
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief DMA interrupt service routine.
- *
- */
-void DMAC_Handler( void )
-{
-	uint8_t active_channel;
-	struct dma_resource *resource;
-	uint8_t isr;
-	uint32_t write_size;
-	uint32_t total_size;
-
-	system_interrupt_enter_critical_section();
-
-	/* Get Pending channel */
-	active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
-
-	Assert(_dma_active_resource[active_channel]);
-
-	/* Get active DMA resource based on channel */
-	resource = _dma_active_resource[active_channel];
-
-	/* Select the active channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	isr = DMAC->CHINTFLAG.reg;
-
-	/* Calculate block transfer size of the DMA transfer */
-	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
-	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
-	resource->transfered_size = total_size - write_size;
-
-	/* DMA channel interrupt handler */
-	if (isr & DMAC_CHINTENCLR_TERR) {
-		/* Clear transfer error flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
-
-		/* Set I/O ERROR status */
-		resource->job_status = STATUS_ERR_IO;
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
-				(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
-			resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
-		}
-	} else if (isr & DMAC_CHINTENCLR_TCMPL) {
-		/* Clear the transfer complete flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
-
-		/* Set job status */
-		resource->job_status = STATUS_OK;
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
-				(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
-			resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
-		}
-	} else if (isr & DMAC_CHINTENCLR_SUSP) {
-		/* Clear channel suspend flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
-
-		/* Set job status */
-		resource->job_status = STATUS_SUSPEND;
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
-			(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
-			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
-		}
-	}
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Initializes config with predefined default values.
- *
- * This function will initialize a given DMA configuration structure to
- * a set of known default values. This function should be called on
- * any new instance of the configuration structure before being
- * modified by the user application.
- *
- * The default configuration is as follows:
- *  \li Software trigger is used as the transfer trigger
- *  \li Priority level 0
- *  \li Only software/event trigger
- *  \li Requires a trigger for each transaction
- *  \li No event input /output
- *  \li DMA channel is disabled during sleep mode (if has the feature)
- * \param[out] config Pointer to the configuration
- *
- */
-void dma_get_config_defaults(struct dma_resource_config *config)
-{
-	Assert(config);
-	/* Set as priority 0 */
-	config->priority = DMA_PRIORITY_LEVEL_0;
-	/* Only software/event trigger */
-	config->peripheral_trigger = 0;
-	/* Transaction trigger */
-	config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
-
-	/* Event configurations, no event input/output */
-	config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
-	config->event_config.event_output_enable = false;
-#ifdef FEATURE_DMA_CHANNEL_STANDBY
-	config->run_in_standby = false;
-#endif
-}
-
-/**
- * \brief Allocate a DMA with configurations.
- *
- * This function will allocate a proper channel for a DMA transfer request.
- *
- * \param[in,out]  dma_resource Pointer to a DMA resource instance
- * \param[in] transfer_config Configurations of the DMA transfer
- *
- * \return Status of the allocation procedure.
- *
- * \retval STATUS_OK The DMA resource was allocated successfully
- * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
- */
-enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config)
-{
-	uint8_t new_channel;
-
-	Assert(resource);
-
-	system_interrupt_enter_critical_section();
-
-	if (!_dma_inst._dma_init) {
-		/* Initialize clocks for DMA */
-#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35)
-		system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
-#else
-		system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
-				PM_APBBMASK_DMAC);
-#endif
-
-		/* Perform a software reset before enable DMA controller */
-		DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
-		DMAC->CTRL.reg = DMAC_CTRL_SWRST;
-
-		/* Setup descriptor base address and write back section base
-		 * address */
-		DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
-		DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
-
-		/* Enable all priority level at the same time */
-		DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
-
-		_dma_inst._dma_init = true;
-	}
-
-	/* Find the proper channel */
-	new_channel = _dma_find_first_free_channel_and_allocate();
-
-	/* If no channel available, return not found */
-	if (new_channel == DMA_INVALID_CHANNEL) {
-		system_interrupt_leave_critical_section();
-
-		return STATUS_ERR_NOT_FOUND;
-	}
-
-	/* Set the channel */
-	resource->channel_id = new_channel;
-
-	/** Perform a reset for the allocated channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
-	DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
-
-#ifdef FEATURE_DMA_CHANNEL_STANDBY
-	if(config->run_in_standby){
-		DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
-	}
-#endif
-
-	/** Configure the DMA control,channel registers and descriptors here */
-	_dma_set_config(resource, config);
-
-	resource->descriptor = NULL;
-
-	/* Log the DMA resource into the internal DMA resource pool */
-	_dma_active_resource[resource->channel_id] = resource;
-
-	system_interrupt_leave_critical_section();
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Free an allocated DMA resource.
- *
- * This function will free an allocated DMA resource.
- *
- * \param[in,out] resource Pointer to the DMA resource
- *
- * \return Status of the free procedure.
- *
- * \retval STATUS_OK The DMA resource was freed successfully
- * \retval STATUS_BUSY The DMA resource was busy and can't be freed
- * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
- */
-enum status_code dma_free(struct dma_resource *resource)
-{
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	system_interrupt_enter_critical_section();
-
-	/* Check if channel is busy */
-	if (dma_is_busy(resource)) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
-
-	/* Check if DMA resource was not allocated */
-	if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
-		system_interrupt_leave_critical_section();
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* Release the DMA resource */
-	_dma_release_channel(resource->channel_id);
-
-	/* Reset the item in the DMA resource pool */
-	_dma_active_resource[resource->channel_id] = NULL;
-
-	system_interrupt_leave_critical_section();
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Start a DMA transfer.
- *
- * This function will start a DMA transfer through an allocated DMA resource.
- *
- * \param[in,out] resource Pointer to the DMA resource
- *
- * \return Status of the transfer start procedure.
- *
- * \retval STATUS_OK The transfer was started successfully
- * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
- * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
- */
-enum status_code dma_start_transfer_job(struct dma_resource *resource)
-{
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	system_interrupt_enter_critical_section();
-
-	/* Check if resource was busy */
-	if (resource->job_status == STATUS_BUSY) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
-
-	/* Check if transfer size is valid */
-	if (resource->descriptor->BTCNT.reg == 0) {
-		system_interrupt_leave_critical_section();
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Enable DMA interrupt */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
-
-	/* Set the interrupt flag */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
-	/* Set job status */
-	resource->job_status = STATUS_BUSY;
-
-	/* Set channel x descriptor 0 to the descriptor base address */
-	memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
-						sizeof(DmacDescriptor));
-
-	/* Enable the transfer channel */
-	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
-
-	system_interrupt_leave_critical_section();
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Abort a DMA transfer.
- *
- * This function will abort a DMA transfer. The DMA channel used for the DMA
- * resource will be disabled.
- * The block transfer count will also be calculated and written to the DMA
- * resource structure.
- *
- * \note The DMA resource will not be freed after calling this function.
- *       The function \ref dma_free() can be used to free an allocated resource.
- *
- * \param[in,out] resource Pointer to the DMA resource
- *
- */
-void dma_abort_job(struct dma_resource *resource)
-{
-	uint32_t write_size;
-	uint32_t total_size;
-
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	system_interrupt_enter_critical_section();
-
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHCTRLA.reg = 0;
-
-	system_interrupt_leave_critical_section();
-
-	/* Get transferred size */
-	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
-	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
-	resource->transfered_size = total_size - write_size;
-
-	resource->job_status = STATUS_ABORTED;
-}
-
-/**
- * \brief Suspend a DMA transfer.
- *
- * This function will request to suspend the transfer of the DMA resource.
- * The channel is kept enabled, can receive transfer triggers (the transfer
- * pending bit will be set), but will be removed from the arbitration scheme.
- * The channel operation can be resumed by calling \ref dma_resume_job().
- *
- * \note This function sets the command to suspend the DMA channel
- * associated with a DMA resource. The channel suspend interrupt flag
- * indicates whether the transfer is truly suspended.
- *
- * \param[in] resource Pointer to the DMA resource
- *
- */
-void dma_suspend_job(struct dma_resource *resource)
-{
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-
-	/* Send the suspend request */
-	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Resume a suspended DMA transfer.
- *
- * This function try to resume a suspended transfer of a DMA resource.
- *
- * \param[in] resource Pointer to the DMA resource
- *
- */
-void dma_resume_job(struct dma_resource *resource)
-{
-	uint32_t bitmap_channel;
-	uint32_t count = 0;
-
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	/* Get bitmap of the allocated DMA channel */
-	bitmap_channel = (1 << resource->channel_id);
-
-	/* Check if channel was suspended */
-	if (resource->job_status != STATUS_SUSPEND) {
-		return;
-	}
-
-	system_interrupt_enter_critical_section();
-
-	/* Send resume request */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
-
-	system_interrupt_leave_critical_section();
-
-	/* Check if transfer job resumed */
-	for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
-		if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
-			break;
-		}
-	}
-
-	if (count < MAX_JOB_RESUME_COUNT) {
-		/* Job resumed */
-		resource->job_status = STATUS_BUSY;
-	} else {
-		/* Job resume timeout */
-		resource->job_status = STATUS_ERR_TIMEOUT;
-	}
-}
-
-/**
- * \brief Create a DMA transfer descriptor with configurations.
- *
- * This function will set the transfer configurations to the DMA transfer
- * descriptor.
- *
- * \param[in] descriptor Pointer to the DMA transfer descriptor
- * \param[in] config Pointer to the descriptor configuration structure
- *
- */
-void dma_descriptor_create(DmacDescriptor* descriptor,
-	struct dma_descriptor_config *config)
-{
-	/* Set block transfer control */
-	descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
-	descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
-	descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
-	descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
-	descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
-	descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
-	descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
-	descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
-
-	/* Set transfer size, source address and destination address */
-	descriptor->BTCNT.reg = config->block_transfer_count;
-	descriptor->SRCADDR.reg = config->source_address;
-	descriptor->DSTADDR.reg = config->destination_address;
-
-	/* Set next transfer descriptor address */
-	descriptor->DESCADDR.reg = config->next_descriptor_address;
-}
-
-/**
- * \brief Add a DMA transfer descriptor to a DMA resource.
- *
- * This function will add a DMA transfer descriptor to a DMA resource.
- * If there was a transfer descriptor already allocated to the DMA resource,
- * the descriptor will be linked to the next descriptor address.
- *
- * \param[in] resource Pointer to the DMA resource
- * \param[in] descriptor Pointer to the transfer descriptor
- *
- * \retval STATUS_OK The descriptor is added to the DMA resource
- * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
- */
-enum status_code dma_add_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor)
-{
-	DmacDescriptor* desc = resource->descriptor;
-
-	if (resource->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	/* Look up for an empty space for the descriptor */
-	if (desc == NULL) {
-		resource->descriptor = descriptor;
-	} else {
-		/* Looking for end of descriptor link */
-		while(desc->DESCADDR.reg != 0) {
-			desc = (DmacDescriptor*)(desc->DESCADDR.reg);
-		}
-
-		/* Set to the end of descriptor list */
-		desc->DESCADDR.reg = (uint32_t)descriptor;
-	}
-
-	return STATUS_OK;
-}
+/*
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller Driver
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <string.h>
+#include "dma.h"
+#include "clock.h"
+#include "system_interrupt.h"
+
+struct _dma_module {
+	volatile bool _dma_init;
+	volatile uint32_t allocated_channels;
+	uint8_t free_channels;
+};
+
+struct _dma_module _dma_inst = {
+	._dma_init = false,
+	.allocated_channels = 0,
+	.free_channels = CONF_MAX_USED_CHANNEL_NUM,
+};
+
+/** Maximum retry counter for resuming a job transfer. */
+#define MAX_JOB_RESUME_COUNT    10000
+
+/** DMA channel mask. */
+#define DMA_CHANNEL_MASK   (0x1f)
+
+COMPILER_ALIGNED(16)
+DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/** Initial write back memory section. */
+COMPILER_ALIGNED(16)
+static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/** Internal DMA resource pool. */
+static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
+
+/* DMA channel interrup flag. */
+uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]={0};
+
+/**
+ * \brief Find a free channel for a DMA resource.
+ *
+ * Find a channel for the requested DMA resource.
+ *
+ * \return Status of channel allocation.
+ * \retval DMA_INVALID_CHANNEL  No channel available
+ * \retval count          Allocated channel for the DMA resource
+ */
+static uint8_t _dma_find_first_free_channel_and_allocate(void)
+{
+	uint8_t count;
+	uint32_t tmp;
+	bool allocated = false;
+
+	system_interrupt_enter_critical_section();
+
+	tmp = _dma_inst.allocated_channels;
+
+	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
+		if (!(tmp & 0x00000001)) {
+			/* If free channel found, set as allocated and return
+			 *number */
+
+			_dma_inst.allocated_channels |= 1 << count;
+			_dma_inst.free_channels--;
+			allocated = true;
+
+			break;
+		}
+
+		tmp = tmp >> 1;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	if (!allocated) {
+		return DMA_INVALID_CHANNEL;
+	} else {
+		return count;
+	}
+}
+
+/**
+ * \brief Release an allocated DMA channel.
+ *
+ * \param[in]  channel  Channel id to be released
+ *
+ */
+static void _dma_release_channel(uint8_t channel)
+{
+	_dma_inst.allocated_channels &= ~(1 << channel);
+	_dma_inst.free_channels++;
+}
+
+/**
+ * \brief Configure the DMA resource.
+ *
+ * \param[in]  dma_resource Pointer to a DMA resource instance
+ * \param[out] resource_config Configurations of the DMA resource
+ *
+ */
+static void _dma_set_config(struct dma_resource *resource,
+		struct dma_resource_config *resource_config)
+{
+	Assert(resource);
+	Assert(resource_config);
+	uint32_t temp_CHCTRLB_reg;
+	system_interrupt_enter_critical_section();
+
+	/** Select the DMA channel and clear software trigger */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
+
+	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+			DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
+			DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
+
+
+	if(resource_config->event_config.input_action){
+	temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
+				resource_config->event_config.input_action);
+	}
+
+	/** Enable event output, the event output selection is configured in
+	 * each transfer descriptor  */
+	if (resource_config->event_config.event_output_enable) {
+		temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
+	}
+
+	/* Write config to CTRLB register */
+	DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
+
+
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief DMA interrupt service routine.
+ *
+ */
+void DMAC_Handler( void )
+{
+	uint8_t active_channel;
+	struct dma_resource *resource;
+	uint8_t isr;
+	uint32_t write_size;
+	uint32_t total_size;
+
+	system_interrupt_enter_critical_section();
+
+	/* Get Pending channel */
+	active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
+
+	Assert(_dma_active_resource[active_channel]);
+
+	/* Get active DMA resource based on channel */
+	resource = _dma_active_resource[active_channel];
+
+	/* Select the active channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	isr = DMAC->CHINTFLAG.reg;
+
+	/* Calculate block transfer size of the DMA transfer */
+	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+	resource->transfered_size = total_size - write_size;
+
+	/* DMA channel interrupt handler */
+	if (isr & DMAC_CHINTENCLR_TERR) {
+		/* Clear transfer error flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
+
+		/* Set I/O ERROR status */
+		resource->job_status = STATUS_ERR_IO;
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
+				(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
+			resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
+		}
+	} else if (isr & DMAC_CHINTENCLR_TCMPL) {
+		/* Clear the transfer complete flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
+
+		/* Set job status */
+		resource->job_status = STATUS_OK;
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
+				(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
+			resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
+		}
+	} else if (isr & DMAC_CHINTENCLR_SUSP) {
+		/* Clear channel suspend flag */
+		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
+
+		/* Set job status */
+		resource->job_status = STATUS_SUSPEND;
+
+		/* Execute the callback function */
+		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
+			(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
+			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
+		}
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Initializes config with predefined default values.
+ *
+ * This function will initialize a given DMA configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Software trigger is used as the transfer trigger
+ *  \li Priority level 0
+ *  \li Only software/event trigger
+ *  \li Requires a trigger for each transaction
+ *  \li No event input /output
+ *  \li DMA channel is disabled during sleep mode (if has the feature)
+ * \param[out] config Pointer to the configuration
+ *
+ */
+void dma_get_config_defaults(struct dma_resource_config *config)
+{
+	Assert(config);
+	/* Set as priority 0 */
+	config->priority = DMA_PRIORITY_LEVEL_0;
+	/* Only software/event trigger */
+	config->peripheral_trigger = 0;
+	/* Transaction trigger */
+	config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
+
+	/* Event configurations, no event input/output */
+	config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
+	config->event_config.event_output_enable = false;
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	config->run_in_standby = false;
+#endif
+}
+
+/**
+ * \brief Allocate a DMA with configurations.
+ *
+ * This function will allocate a proper channel for a DMA transfer request.
+ *
+ * \param[in,out]  dma_resource Pointer to a DMA resource instance
+ * \param[in] transfer_config Configurations of the DMA transfer
+ *
+ * \return Status of the allocation procedure.
+ *
+ * \retval STATUS_OK The DMA resource was allocated successfully
+ * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
+ */
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config)
+{
+	uint8_t new_channel;
+
+	Assert(resource);
+
+	system_interrupt_enter_critical_section();
+
+	if (!_dma_inst._dma_init) {
+		/* Initialize clocks for DMA */
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35)
+		system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
+#else
+		system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
+				PM_APBBMASK_DMAC);
+#endif
+
+		/* Perform a software reset before enable DMA controller */
+		DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+		DMAC->CTRL.reg = DMAC_CTRL_SWRST;
+
+		/* Setup descriptor base address and write back section base
+		 * address */
+		DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
+		DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
+
+		/* Enable all priority level at the same time */
+		DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
+
+		_dma_inst._dma_init = true;
+	}
+
+	/* Find the proper channel */
+	new_channel = _dma_find_first_free_channel_and_allocate();
+
+	/* If no channel available, return not found */
+	if (new_channel == DMA_INVALID_CHANNEL) {
+		system_interrupt_leave_critical_section();
+
+		return STATUS_ERR_NOT_FOUND;
+	}
+
+	/* Set the channel */
+	resource->channel_id = new_channel;
+
+	/** Perform a reset for the allocated channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	if(config->run_in_standby){
+		DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	}
+#endif
+
+	/** Configure the DMA control,channel registers and descriptors here */
+	_dma_set_config(resource, config);
+
+	resource->descriptor = NULL;
+
+	/* Log the DMA resource into the internal DMA resource pool */
+	_dma_active_resource[resource->channel_id] = resource;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Free an allocated DMA resource.
+ *
+ * This function will free an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the free procedure.
+ *
+ * \retval STATUS_OK The DMA resource was freed successfully
+ * \retval STATUS_BUSY The DMA resource was busy and can't be freed
+ * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
+ */
+enum status_code dma_free(struct dma_resource *resource)
+{
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if channel is busy */
+	if (dma_is_busy(resource)) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Check if DMA resource was not allocated */
+	if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
+		system_interrupt_leave_critical_section();
+		return STATUS_ERR_NOT_INITIALIZED;
+	}
+
+	/* Release the DMA resource */
+	_dma_release_channel(resource->channel_id);
+
+	/* Reset the item in the DMA resource pool */
+	_dma_active_resource[resource->channel_id] = NULL;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Start a DMA transfer.
+ *
+ * This function will start a DMA transfer through an allocated DMA resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ * \return Status of the transfer start procedure.
+ *
+ * \retval STATUS_OK The transfer was started successfully
+ * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
+ * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
+ */
+enum status_code dma_start_transfer_job(struct dma_resource *resource)
+{
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if resource was busy */
+	if (resource->job_status == STATUS_BUSY) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Check if transfer size is valid */
+	if (resource->descriptor->BTCNT.reg == 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Enable DMA interrupt */
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
+
+	/* Set the interrupt flag */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
+	/* Set job status */
+	resource->job_status = STATUS_BUSY;
+
+	/* Set channel x descriptor 0 to the descriptor base address */
+	memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
+						sizeof(DmacDescriptor));
+
+	/* Enable the transfer channel */
+	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+	system_interrupt_leave_critical_section();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Abort a DMA transfer.
+ *
+ * This function will abort a DMA transfer. The DMA channel used for the DMA
+ * resource will be disabled.
+ * The block transfer count will also be calculated and written to the DMA
+ * resource structure.
+ *
+ * \note The DMA resource will not be freed after calling this function.
+ *       The function \ref dma_free() can be used to free an allocated resource.
+ *
+ * \param[in,out] resource Pointer to the DMA resource
+ *
+ */
+void dma_abort_job(struct dma_resource *resource)
+{
+	uint32_t write_size;
+	uint32_t total_size;
+
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHCTRLA.reg = 0;
+
+	system_interrupt_leave_critical_section();
+
+	/* Get transferred size */
+	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+	resource->transfered_size = total_size - write_size;
+
+	resource->job_status = STATUS_ABORTED;
+}
+
+/**
+ * \brief Suspend a DMA transfer.
+ *
+ * This function will request to suspend the transfer of the DMA resource.
+ * The channel is kept enabled, can receive transfer triggers (the transfer
+ * pending bit will be set), but will be removed from the arbitration scheme.
+ * The channel operation can be resumed by calling \ref dma_resume_job().
+ *
+ * \note This function sets the command to suspend the DMA channel
+ * associated with a DMA resource. The channel suspend interrupt flag
+ * indicates whether the transfer is truly suspended.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ */
+void dma_suspend_job(struct dma_resource *resource)
+{
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the channel */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+
+	/* Send the suspend request */
+	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Resume a suspended DMA transfer.
+ *
+ * This function try to resume a suspended transfer of a DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ */
+void dma_resume_job(struct dma_resource *resource)
+{
+	uint32_t bitmap_channel;
+	uint32_t count = 0;
+
+	Assert(resource);
+	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+	/* Get bitmap of the allocated DMA channel */
+	bitmap_channel = (1 << resource->channel_id);
+
+	/* Check if channel was suspended */
+	if (resource->job_status != STATUS_SUSPEND) {
+		return;
+	}
+
+	system_interrupt_enter_critical_section();
+
+	/* Send resume request */
+	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if transfer job resumed */
+	for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
+		if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
+			break;
+		}
+	}
+
+	if (count < MAX_JOB_RESUME_COUNT) {
+		/* Job resumed */
+		resource->job_status = STATUS_BUSY;
+	} else {
+		/* Job resume timeout */
+		resource->job_status = STATUS_ERR_TIMEOUT;
+	}
+}
+
+/**
+ * \brief Create a DMA transfer descriptor with configurations.
+ *
+ * This function will set the transfer configurations to the DMA transfer
+ * descriptor.
+ *
+ * \param[in] descriptor Pointer to the DMA transfer descriptor
+ * \param[in] config Pointer to the descriptor configuration structure
+ *
+ */
+void dma_descriptor_create(DmacDescriptor* descriptor,
+	struct dma_descriptor_config *config)
+{
+	/* Set block transfer control */
+	descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
+	descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
+	descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
+	descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
+	descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
+	descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
+	descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
+	descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
+
+	/* Set transfer size, source address and destination address */
+	descriptor->BTCNT.reg = config->block_transfer_count;
+	descriptor->SRCADDR.reg = config->source_address;
+	descriptor->DSTADDR.reg = config->destination_address;
+
+	/* Set next transfer descriptor address */
+	descriptor->DESCADDR.reg = config->next_descriptor_address;
+}
+
+/**
+ * \brief Add a DMA transfer descriptor to a DMA resource.
+ *
+ * This function will add a DMA transfer descriptor to a DMA resource.
+ * If there was a transfer descriptor already allocated to the DMA resource,
+ * the descriptor will be linked to the next descriptor address.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] descriptor Pointer to the transfer descriptor
+ *
+ * \retval STATUS_OK The descriptor is added to the DMA resource
+ * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
+ */
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor)
+{
+	DmacDescriptor* desc = resource->descriptor;
+
+	if (resource->job_status == STATUS_BUSY) {
+		return STATUS_BUSY;
+	}
+
+	/* Look up for an empty space for the descriptor */
+	if (desc == NULL) {
+		resource->descriptor = descriptor;
+	} else {
+		/* Looking for end of descriptor link */
+		while(desc->DESCADDR.reg != 0) {
+			desc = (DmacDescriptor*)(desc->DESCADDR.reg);
+		}
+
+		/* Set to the end of descriptor list */
+		desc->DESCADDR.reg = (uint32_t)descriptor;
+	}
+
+	return STATUS_OK;
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.h
index ebf3b7a..1458cbc 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma.h
@@ -1,878 +1,878 @@
-/**
- * \file
- *
- * \brief SAM Direct Memory Access Controller Driver
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef DMA_H_INCLUDED
-#define DMA_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller (DMAC) Driver
- *
- * This driver for Atmel&reg; | SMART ARM®-based microcontrollers provides an interface for the configuration
- * and management of the Direct Memory Access Controller(DMAC) module within
- * the device. The DMAC can transfer data between memories and peripherals, and
- * thus off-load these tasks from the CPU. The module supports peripheral to
- * peripheral, peripheral to memory, memory to peripheral, and memory to memory
- * transfers.
- *
- * The following peripheral is used by the DMAC Driver:
- * - DMAC (Direct Memory Access Controller)
- *
- * The following devices can use this module:
- *  - Atmel | SMART SAM D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM L21/L22
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM C20/C21
- *  - Atmel | SMART SAM HA1
- *  - Atmel | SMART SAM R30
- *  - Atmel | SMART SAM R34/R35
- *
- * The outline of this documentation is as follows:
- * - \ref asfdoc_sam0_dma_prerequisites
- * - \ref asfdoc_sam0_dma_module_overview
- * - \ref asfdoc_sam0_dma_special_considerations
- * - \ref asfdoc_sam0_dma_extra_info
- * - \ref asfdoc_sam0_dma_examples
- * - \ref asfdoc_sam0_dma_api_overview
- *
- *
- * \section asfdoc_sam0_dma_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_dma_module_overview Module Overview
- *
- * SAM devices with DMAC enables high data transfer rates with minimum
- * CPU intervention and frees up CPU time. With access to all peripherals,
- * the DMAC can handle automatic transfer of data to/from modules.
- * It supports static and incremental addressing for both source and
- * destination.
- *
- * The DMAC when used with Event System or peripheral triggers, provides a
- * considerable advantage by reducing the power consumption and performing
- * data transfer in the background.
- * For example, if the ADC is configured to generate an event, it can trigger
- * the DMAC to transfer the data into another peripheral or SRAM.
- * The CPU can remain in sleep during this time to reduce the power consumption.
- *
- * <table>
- *    <tr>
- *      <th>Device</th>
- *      <th>Dma channel number</th>
- *    </tr>
- *    <tr>
- *      <td>SAM D21/R21/C20/C21</td>
- *      <td>12</td>
- *    </tr>
- *    <tr>
- *      <td>SAM D09/D10/D11</td>
- *      <td>6</td>
- *    </tr>
- *    <tr>
- *      <td>SAM L21,SAMR30/R34/R35</td>
- *      <td>16</td>
- *    </tr>
-  *   <tr>
- *      <td>SAM R34/R35</td>
- *      <td>12</td>
- *    </tr>
- * </table>
- * The DMA channel operation can be suspended at any time by software, by events
- * from event system, or after selectable descriptor execution. The operation
- * can be resumed by software or by events from the event system.
- * The DMAC driver for SAM supports four types of transfers such as
- * peripheral to peripheral, peripheral to memory, memory to peripheral, and
- * memory to memory.
- *
- * The basic transfer unit is a beat, which is defined as a single bus access.
- * There can be multiple beats in a single block transfer and multiple block
- * transfers in a DMA transaction.
- * DMA transfer is based on descriptors, which holds transfer properties
- * such as the source and destination addresses, transfer counter, and other
- * additional transfer control information.
- * The descriptors can be static or linked. When static, a single block transfer
- * is performed. When linked, a number of transfer descriptors can be used to
- * enable multiple block transfers within a single DMA transaction.
- *
- * The implementation of the DMA driver is based on the idea that the DMA channel
- * is a finite resource of entities with the same abilities. A DMA channel resource
- * is able to move a defined set of data from a source address to destination
- * address triggered by a transfer trigger. On the SAM devices there are 12
- * DMA resources available for allocation. Each of these DMA resources can trigger
- * interrupt callback routines and peripheral events.
- * The other main features are:
- *
- * - Selectable transfer trigger source
- *  - Software
- *  - Event System
- *  - Peripheral
- * - Event input and output is supported for the four lower channels
- * - Four level channel priority
- * - Optional interrupt generation on transfer complete, channel error, or channel suspend
- * - Supports multi-buffer or circular buffer mode by linking multiple descriptors
- * - Beat size configurable as 8-bit, 16-bit, or 32-bit
- *
- * A simplified block diagram of the DMA Resource can be seen in
- * \ref asfdoc_sam0_dma_module_block_diagram "the figure below".
- *
- * \anchor asfdoc_sam0_dma_module_block_diagram
- * \dot
- * digraph overview {
- * splines = false;
- * rankdir=LR;
- *
- * mux1 [label="Transfer Trigger", shape=box];
- *
- * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
- * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
- *
- * mux1 -> dma;
- * descriptor -> dma;
- *
- * interrupt [label="Interrupt", shape=box];
- * events [label="Events", shape=box];
- *
- * dma:e -> interrupt:w;
- * dma:e -> events:w;
- *
- * {rank=same; descriptor dma}
- *
- * }
- * \enddot
- *
- * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition
- * <table>
- *  <tr>
- *    <th>Driver Feature Macro</th>
- *    <th>Supported devices</th>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_DMA_CHANNEL_STANDBY</td>
- *    <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
- *  </tr>
- * </table>
- * \note The specific features are only available in the driver when the
- * selected device supports those features.
- *
- * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers
- *
- *   <table border="0" cellborder="1" cellspacing="0" >
- *    <tr>
- *        <th> Name </th> <th> Description </th>
- *    </tr>
- *    <tr>
- *     <td > Beat </td>
- *     <td > It is a single bus access by the DMAC.
- *           Configurable as 8-bit, 16-bit, or 32-bit.
- *     </td>
- *    </tr>
- *    <tr>
- *     <td > Burst </td>
- *     <td> It is a transfer of n-beats (n=1,4,8,16).
- *          For the DMAC module in SAM, the burst size is one beat.
- *          Arbitration takes place each time a burst transfer is completed.
- *     </td>
- *    </tr>
- *    <tr>
- *     <td > Block transfer </td>
- *     <td>  A single block transfer is a configurable number of (1 to 64k)
- *           beat transfers
- *     </td>
- *    </tr>
- *   </table>
- *
- * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels
- * The DMAC in each device consists of several DMA channels, which
- * along with the transfer descriptors defines the data transfer properties.
- * - The transfer control descriptor defines the source and destination
- * addresses, source and destination address increment settings, the
- * block transfer count, and event output condition selection
- * - Dedicated channel registers control the peripheral trigger source,
- * trigger mode settings, event input actions, and channel priority level
- * settings
- *
- * With a successful DMA resource allocation, a dedicated
- * DMA channel will be assigned. The channel will be occupied until the
- * DMA resource is freed. A DMA resource handle is used to identify the specific
- * DMA resource.
- * When there are multiple channels with active requests, the arbiter prioritizes
- * the channels requesting access to the bus.
- *
- * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers
- * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
- * transfer request can be triggered from software, peripheral, or an event. There
- * are dedicated source trigger selections for each DMA channel usage.
-
- *
- * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
- * The transfer descriptor resides in the SRAM and
- * defines these channel properties.
- *   <table border="0" cellborder="1" cellspacing="0" >
- *    <tr>
- *        <th> Field name </th> <th> Field width </th>
- *    </tr>
- *    <tr>
- *     <td > Descriptor Next Address </td> <td > 32 bits </td>
- *    </tr>
- *    <tr>
- *     <td > Destination Address </td> <td> 32 bits </td>
- *    </tr>
- *    <tr>
- *     <td > Source Address </td> <td> 32 bits </td>
- *    </tr>
- *    <tr>
- *     <td > Block Transfer Counter </td> <td> 16 bits </td>
- *    </tr>
- *    <tr>
- *     <td > Block Transfer Control </td> <td> 16 bits </td>
- *    </tr>
- *   </table>
- *
- * Before starting a transfer, at least one descriptor should be configured.
- * After a successful allocation of a DMA channel, the transfer descriptor can
- * be added with a call to \ref dma_add_descriptor(). If there is a transfer
- * descriptor already allocated to the DMA resource, the descriptor will
- * be linked to the next descriptor address.
- *
- * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events
- * Both an interrupt callback and an peripheral event can be triggered by the
- * DMA transfer. Three types of callbacks are supported by the DMA driver:
- * transfer complete, channel suspend, and transfer error. Each of these callback
- * types can be registered and enabled for each channel independently through
- * the DMA driver API.
- *
- * The DMAC module can also generate events on transfer complete. Event
- * generation is enabled through the DMA channel, event channel configuration,
- * and event user multiplexing is done through the events driver.
- *
- * The DMAC can generate events in the below cases:
- *
- * - When a block transfer is complete
- *
- * - When each beat transfer within a block transfer is complete
- *
- * \section asfdoc_sam0_dma_special_considerations Special Considerations
- *
- * There are no special considerations for this module.
- *
- *
- * \section asfdoc_sam0_dma_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_dma_extra. This includes:
- * - \ref asfdoc_sam0_dma_extra_acronyms
- * - \ref asfdoc_sam0_dma_extra_dependencies
- * - \ref asfdoc_sam0_dma_extra_errata
- * - \ref asfdoc_sam0_dma_extra_history
- *
- *
- * \section asfdoc_sam0_dma_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_dma_exqsg.
- *
- *
- * \section asfdoc_sam0_dma_api_overview API Overview
- * @{
- */
-
-#include <compiler.h>
-#include "conf_dma.h"
-
-#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
-#define FEATURE_DMA_CHANNEL_STANDBY
-#endif
-
-/** DMA invalid channel number. */
-#define DMA_INVALID_CHANNEL        0xff
-
-/** ExInitial description section. */
-extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM];
-
-/* DMA channel interrup flag. */
-extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM];
-
-/** DMA priority level. */
-enum dma_priority_level {
-	/** Priority level 0. */
-	DMA_PRIORITY_LEVEL_0,
-	/** Priority level 1. */
-	DMA_PRIORITY_LEVEL_1,
-	/** Priority level 2. */
-	DMA_PRIORITY_LEVEL_2,
-	/** Priority level 3. */
-	DMA_PRIORITY_LEVEL_3,
-};
-
-/** DMA input actions. */
-enum dma_event_input_action {
-	/** No action. */
-	DMA_EVENT_INPUT_NOACT,
-	/** Normal transfer and periodic transfer trigger. */
-	DMA_EVENT_INPUT_TRIG,
-	/** Conditional transfer trigger. */
-	DMA_EVENT_INPUT_CTRIG,
-	/** Conditional block transfer. */
-	DMA_EVENT_INPUT_CBLOCK,
-	/** Channel suspend operation. */
-	DMA_EVENT_INPUT_SUSPEND,
-	/** Channel resume operation. */
-	DMA_EVENT_INPUT_RESUME,
-	/** Skip next block suspend action. */
-	DMA_EVENT_INPUT_SSKIP,
-};
-
-/**
- * Address increment step size. These bits select the address increment step
- * size. The setting apply to source or destination address, depending on
- * STEPSEL setting.
- */
-enum dma_address_increment_stepsize {
-	/** The address is incremented by (beat size * 1). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
-	/** The address is incremented by (beat size * 2). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
-	/** The address is incremented by (beat size * 4). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
-	/** The address is incremented by (beat size * 8). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
-	/** The address is incremented by (beat size * 16). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
-	/** The address is incremented by (beat size * 32). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
-	/** The address is incremented by (beat size * 64). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
-	/** The address is incremented by (beat size * 128). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
-};
-
-/**
- * DMA step selection. This bit determines whether the step size setting
- * is applied to source or destination address.
- */
-enum dma_step_selection {
-	/** Step size settings apply to the destination address. */
-	DMA_STEPSEL_DST = 0,
-	/** Step size settings apply to the source address. */
-	DMA_STEPSEL_SRC,
-};
-
-/** The basic transfer unit in DMAC is a beat, which is defined as a
- *  single bus access. Its size is configurable and applies to both read
- *  and write. */
-enum dma_beat_size {
-	/** 8-bit access. */
-	DMA_BEAT_SIZE_BYTE = 0,
-	/** 16-bit access. */
-	DMA_BEAT_SIZE_HWORD,
-	/** 32-bit access. */
-	DMA_BEAT_SIZE_WORD,
-};
-
-/**
- * Block action definitions.
- */
-enum dma_block_action {
-	/** No action. */
-	DMA_BLOCK_ACTION_NOACT = 0,
-	/** Channel in normal operation and sets transfer complete interrupt flag
-	 *  after block transfer. */
-	DMA_BLOCK_ACTION_INT,
-	/** Trigger channel suspend after block transfer and sets channel
-	 *  suspend interrupt flag once the channel is suspended. */
-	DMA_BLOCK_ACTION_SUSPEND,
-	/** Sets transfer complete interrupt flag after a block transfer and
-	 *  trigger channel suspend. The channel suspend interrupt flag will be set
-	 *  once the channel is suspended. */
-	DMA_BLOCK_ACTION_BOTH,
-};
-
-/** Event output selection. */
-enum dma_event_output_selection {
-	/** Event generation disable. */
-	DMA_EVENT_OUTPUT_DISABLE = 0,
-	/** Event strobe when block transfer complete. */
-	DMA_EVENT_OUTPUT_BLOCK,
-	/** Event output reserved. */
-	DMA_EVENT_OUTPUT_RESERVED,
-	/** Event strobe when beat transfer complete. */
-	DMA_EVENT_OUTPUT_BEAT,
-};
-
-/** DMA trigger action type. */
-enum dma_transfer_trigger_action{
-	/** Perform a block transfer when triggered. */
-	DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
-	/** Perform a beat transfer when triggered. */
-	DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
-	/** Perform a transaction when triggered. */
-	DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
-};
-
-/**
- * Callback types for DMA callback driver.
- */
-enum dma_callback_type {
-	/** Callback for any of transfer errors. A transfer error is flagged
-     *	if a bus error is detected during an AHB access or when the DMAC
-	 *  fetches an invalid descriptor. */
-	DMA_CALLBACK_TRANSFER_ERROR,
-	/** Callback for transfer complete. */
-	DMA_CALLBACK_TRANSFER_DONE,
-	/** Callback for channel suspend. */
-	DMA_CALLBACK_CHANNEL_SUSPEND,
-	/** Number of available callbacks. */
-	DMA_CALLBACK_N,
-};
-
-/**
- * DMA transfer descriptor configuration. When the source or destination address
- * increment is enabled, the addresses stored into the configuration structure
- * must correspond to the end of the transfer.
- *
- */
-struct dma_descriptor_config {
-	/** Descriptor valid flag used to identify whether a descriptor is
-	    valid or not */
-	bool descriptor_valid;
-	/** This is used to generate an event on specific transfer action in
-	    a channel. Supported only in four lower channels. */
-	enum dma_event_output_selection event_output_selection;
-	/** Action taken when a block transfer is completed */
-	enum dma_block_action block_action;
-	/** Beat size is configurable as 8-bit, 16-bit, or 32-bit */
-	enum dma_beat_size beat_size;
-	/** Used for enabling the source address increment */
-	bool src_increment_enable;
-	/** Used for enabling the destination address increment */
-	bool dst_increment_enable;
-	/** This bit selects whether the source or destination address is
-	    using the step size settings */
-	enum dma_step_selection step_selection;
-	/** The step size for source/destination address increment.
-	    The next address is calculated
-	    as next_addr = addr + (2^step_size * beat size). */
-	enum dma_address_increment_stepsize step_size;
-	/** It is the number of beats in a block. This count value is
-	 * decremented by one after each beat data transfer. */
-	uint16_t block_transfer_count;
-	/** Transfer source address */
-	uint32_t source_address;
-	/** Transfer destination address */
-	uint32_t destination_address;
-	/** Set to zero for static descriptors. This must have a valid memory
-	    address for linked descriptors. */
-	uint32_t next_descriptor_address;
-};
-
-/** Configurations for DMA events. */
-struct dma_events_config {
-	/** Event input actions */
-	enum dma_event_input_action input_action;
-	/** Enable DMA event output */
-	bool event_output_enable;
-};
-
-/** DMA configurations for transfer. */
-struct dma_resource_config {
-	/** DMA transfer priority */
-	enum dma_priority_level priority;
-	/**DMA peripheral trigger index */
-	uint8_t peripheral_trigger;
-	/** DMA trigger action */
-	enum dma_transfer_trigger_action trigger_action;
-#ifdef FEATURE_DMA_CHANNEL_STANDBY
-	/** Keep DMA channel enabled in standby sleep mode if true */
-	bool run_in_standby;
-#endif
-	/** DMA events configurations */
-	struct dma_events_config event_config;
-};
-
-/** Forward definition of the DMA resource. */
-struct dma_resource;
-/** Type definition for a DMA resource callback function. */
-typedef void (*dma_callback_t)(struct dma_resource *const resource);
-
-/** Structure for DMA transfer resource. */
-struct dma_resource {
-	/** Allocated DMA channel ID */
-	uint8_t channel_id;
-	/** Array of callback functions for DMA transfer job */
-	dma_callback_t callback[DMA_CALLBACK_N];
-	/** Bit mask for enabled callbacks */
-	uint8_t callback_enable;
-	/** Status of the last job */
-	volatile enum status_code job_status;
-	/** Transferred data size */
-	uint32_t transfered_size;
-	/** DMA transfer descriptor */
-	DmacDescriptor* descriptor;
-};
-
-/**
- * \brief Get DMA resource status.
- *
- * \param[in] resource Pointer to the DMA resource
- *
- * \return Status of the DMA resource.
- */
-static inline enum status_code dma_get_job_status(struct dma_resource *resource)
-{
-	Assert(resource);
-
-	return resource->job_status;
-}
-
-/**
- * \brief Check if the given DMA resource is busy.
- *
- * \param[in] resource Pointer to the DMA resource
- *
- * \return Status which indicates whether the DMA resource is busy.
- *
- * \retval true The DMA resource has an on-going transfer
- * \retval false The DMA resource is not busy
- */
-static inline bool dma_is_busy(struct dma_resource *resource)
-{
-	Assert(resource);
-
-	return (resource->job_status == STATUS_BUSY);
-}
-
-/**
- * \brief Enable a callback function for a dedicated DMA resource.
- *
- * \param[in] resource Pointer to the DMA resource
- * \param[in] type Callback function type
- *
- */
-static inline void dma_enable_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
-{
-	Assert(resource);
-
-	resource->callback_enable |= 1 << type;
-	g_chan_interrupt_flag[resource->channel_id] |= (1UL << type);
-}
-
-/**
- * \brief Disable a callback function for a dedicated DMA resource.
- *
- * \param[in] resource Pointer to the DMA resource
- * \param[in] type Callback function type
- *
- */
-static inline void dma_disable_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
-{
-	Assert(resource);
-
-	resource->callback_enable &= ~(1 << type);
-	g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK);
-	DMAC->CHINTENCLR.reg = (1UL << type);
-}
-
-/**
- * \brief Register a callback function for a dedicated DMA resource.
- *
- * There are three types of callback functions, which can be registered:
- * - Callback for transfer complete
- * - Callback for transfer error
- * - Callback for channel suspend
- *
- * \param[in] resource Pointer to the DMA resource
- * \param[in] callback Pointer to the callback function
- * \param[in] type Callback function type
- *
- */
-static inline void dma_register_callback(struct dma_resource *resource,
-		dma_callback_t callback, enum dma_callback_type type)
-{
-	Assert(resource);
-
-	resource->callback[type] = callback;
-}
-
-/**
- * \brief Unregister a callback function for a dedicated DMA resource.
- *
- * There are three types of callback functions:
- * - Callback for transfer complete
- * - Callback for transfer error
- * - Callback for channel suspend
- *
- * The application can unregister any of the callback functions which
- * are already registered and are no longer needed.
- *
- * \param[in] resource Pointer to the DMA resource
- * \param[in] type Callback function type
- *
- */
-static inline void dma_unregister_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
-{
-	Assert(resource);
-
-	resource->callback[type] = NULL;
-}
-
-/**
- * \brief Will set a software trigger for resource.
- *
- * This function is used to set a software trigger on the DMA channel
- * associated with resource. If a trigger is already pending no new trigger
- * will be generated for the channel.
- *
- * \param[in] resource Pointer to the DMA resource
- */
-static inline void dma_trigger_transfer(struct dma_resource *resource) {
-	Assert(resource);
-
-	DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
-}
-
-/**
- * \brief Initializes DMA transfer configuration with predefined default values.
- *
- * This function will initialize a given DMA descriptor configuration structure to
- * a set of known default values. This function should be called on
- * any new instance of the configuration structure before being
- * modified by the user application.
- *
- * The default configuration is as follows:
- *  \li Set the descriptor as valid
- *  \li Disable event output
- *  \li No block action
- *  \li Set beat size as byte
- *  \li Enable source increment
- *  \li Enable destination increment
- *  \li Step size is applied to the destination address
- *  \li Address increment is beat size multiplied by 1
- *  \li Default transfer size is set to 0
- *  \li Default source address is set to NULL
- *  \li Default destination address is set to NULL
- *  \li Default next descriptor not available
- * \param[out] config Pointer to the configuration
- *
- */
-static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
-{
-	Assert(config);
-
-	/* Set descriptor as valid */
-	config->descriptor_valid = true;
-	/* Disable event output */
-	config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
-	/* No block action */
-	config->block_action = DMA_BLOCK_ACTION_NOACT;
-	/* Set beat size to one byte */
-	config->beat_size = DMA_BEAT_SIZE_BYTE;
-	/* Enable source increment */
-	config->src_increment_enable = true;
-	/* Enable destination increment */
-	config->dst_increment_enable = true;
-	/* Step size is applied to the destination address */
-	config->step_selection = DMA_STEPSEL_DST;
-	/* Address increment is beat size multiplied by 1*/
-	config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
-	/* Default transfer size is set to 0 */
-	config->block_transfer_count = 0;
-	/* Default source address is set to NULL */
-	config->source_address = (uint32_t)NULL;
-	/* Default destination address is set to NULL */
-	config->destination_address = (uint32_t)NULL;
-	/** Next descriptor address set to 0 */
-	config->next_descriptor_address = 0;
-}
-
-/**
- * \brief Update DMA descriptor.
- *
- * This function can update the descriptor of an allocated DMA resource.
- *
- */
-static inline void dma_update_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor)
-{
-	Assert(resource);
-
-	resource->descriptor = descriptor;
-}
-
-/**
- * \brief Reset DMA descriptor.
- *
- * This function will clear the DESCADDR register of an allocated DMA resource.
- *
- */
-static inline void dma_reset_descriptor(struct dma_resource *resource)
-{
-	Assert(resource);
-
-	resource->descriptor = NULL;
-}
-
-void dma_get_config_defaults(struct dma_resource_config *config);
-enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config);
-enum status_code dma_free(struct dma_resource *resource);
-enum status_code dma_start_transfer_job(struct dma_resource *resource);
-void dma_abort_job(struct dma_resource *resource);
-void dma_suspend_job(struct dma_resource *resource);
-void dma_resume_job(struct dma_resource *resource);
-void dma_descriptor_create(DmacDescriptor* descriptor,
-	struct dma_descriptor_config *config);
-enum status_code dma_add_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor);
-
-/** @} */
-
-/**
- * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver
- *
- * \section asfdoc_sam0_dma_extra_acronyms Acronyms
- * Below is a table listing the acronyms used in this module, along with their
- * intended meanings.
- *
- * <table>
- *   <tr>
- *     <th>Acronym</th>
- *     <th>Description</th>
- *   </tr>
- *   <tr>
- *     <td>DMA</td>
- *     <td>Direct Memory Access</td>
- *   </tr>
- *   <tr>
- *     <td>DMAC</td>
- *     <td>Direct Memory Access Controller </td>
- *   </tr>
- *   <tr>
- *     <td>CPU</td>
- *     <td>Central Processing Unit</td>
- *   </tr>
- * </table>
- *
- *
- * \section asfdoc_sam0_dma_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- * - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
- *
- *
- * \section asfdoc_sam0_dma_extra_errata Errata
- * There are no errata related to this driver.
- *
- *
- * \section asfdoc_sam0_dma_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *   <tr>
- *     <th>Changelog</th>
- *   </tr>
- *   <tr>
- *     <td>Add SAM C21 support</td>
- *   </tr>
- *   <tr>
- *     <td>Add SAM L21 support</td>
- *   </tr>
- *   <tr>
- *     <td>Add SAM R30 support</td>
- *   </tr>
- *   <tr>
- *     <td>Initial Release</td>
- *   </tr>
- * </table>
- */
-
- /**
- * \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
- *
- * This is a list of the available Quick Start Guides (QSGs) and example
- * applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
- * step-by-step instructions to configure and use this driver in a selection of
- * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.
- *
- * - \subpage asfdoc_sam0_dma_basic_use_case
- *
- * \note More DMA usage examples are available in peripheral QSGs.
- * A quick start guide for TC/TCC
- * shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
- * DMA transfer from peripheral to memory or from memory to peripheral;
- * ADC/DAC shows peripheral to peripheral transfer.
- *
- * \page asfdoc_sam0_dma_document_revision_history Document Revision History
- *
- * <table>
- *    <tr>
- *        <th>Doc. Rev.</th>
- *        <th>Date</th>
- *        <th>Comments</th>
- *    </tr>
- *    <tr>
- *        <td>42257C</td>
- *        <td>12/2015</td>
- *        <td>Added suppport for SAM L21/L22, SAM C21, SAM D09,SAMR30/R34 and SAM DA1</td>
- *    </tr>
- *    <tr>
- *        <td>42257B</td>
- *        <td>12/2014</td>
- *        <td>Added support for SAM R21 and SAM D10/D11</td>
- *    </tr>
- *    <tr>
- *        <td>42257A</td>
- *        <td>02/2014</td>
- *        <td>Initial release</td>
- *    </tr>
- * </table>
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* DMA_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller Driver
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef DMA_H_INCLUDED
+#define DMA_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller (DMAC) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM®-based microcontrollers provides an interface for the configuration
+ * and management of the Direct Memory Access Controller(DMAC) module within
+ * the device. The DMAC can transfer data between memories and peripherals, and
+ * thus off-load these tasks from the CPU. The module supports peripheral to
+ * peripheral, peripheral to memory, memory to peripheral, and memory to memory
+ * transfers.
+ *
+ * The following peripheral is used by the DMAC Driver:
+ * - DMAC (Direct Memory Access Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34/R35
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_dma_prerequisites
+ * - \ref asfdoc_sam0_dma_module_overview
+ * - \ref asfdoc_sam0_dma_special_considerations
+ * - \ref asfdoc_sam0_dma_extra_info
+ * - \ref asfdoc_sam0_dma_examples
+ * - \ref asfdoc_sam0_dma_api_overview
+ *
+ *
+ * \section asfdoc_sam0_dma_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_dma_module_overview Module Overview
+ *
+ * SAM devices with DMAC enables high data transfer rates with minimum
+ * CPU intervention and frees up CPU time. With access to all peripherals,
+ * the DMAC can handle automatic transfer of data to/from modules.
+ * It supports static and incremental addressing for both source and
+ * destination.
+ *
+ * The DMAC when used with Event System or peripheral triggers, provides a
+ * considerable advantage by reducing the power consumption and performing
+ * data transfer in the background.
+ * For example, if the ADC is configured to generate an event, it can trigger
+ * the DMAC to transfer the data into another peripheral or SRAM.
+ * The CPU can remain in sleep during this time to reduce the power consumption.
+ *
+ * <table>
+ *    <tr>
+ *      <th>Device</th>
+ *      <th>Dma channel number</th>
+ *    </tr>
+ *    <tr>
+ *      <td>SAM D21/R21/C20/C21</td>
+ *      <td>12</td>
+ *    </tr>
+ *    <tr>
+ *      <td>SAM D09/D10/D11</td>
+ *      <td>6</td>
+ *    </tr>
+ *    <tr>
+ *      <td>SAM L21,SAMR30/R34/R35</td>
+ *      <td>16</td>
+ *    </tr>
+  *   <tr>
+ *      <td>SAM R34/R35</td>
+ *      <td>12</td>
+ *    </tr>
+ * </table>
+ * The DMA channel operation can be suspended at any time by software, by events
+ * from event system, or after selectable descriptor execution. The operation
+ * can be resumed by software or by events from the event system.
+ * The DMAC driver for SAM supports four types of transfers such as
+ * peripheral to peripheral, peripheral to memory, memory to peripheral, and
+ * memory to memory.
+ *
+ * The basic transfer unit is a beat, which is defined as a single bus access.
+ * There can be multiple beats in a single block transfer and multiple block
+ * transfers in a DMA transaction.
+ * DMA transfer is based on descriptors, which holds transfer properties
+ * such as the source and destination addresses, transfer counter, and other
+ * additional transfer control information.
+ * The descriptors can be static or linked. When static, a single block transfer
+ * is performed. When linked, a number of transfer descriptors can be used to
+ * enable multiple block transfers within a single DMA transaction.
+ *
+ * The implementation of the DMA driver is based on the idea that the DMA channel
+ * is a finite resource of entities with the same abilities. A DMA channel resource
+ * is able to move a defined set of data from a source address to destination
+ * address triggered by a transfer trigger. On the SAM devices there are 12
+ * DMA resources available for allocation. Each of these DMA resources can trigger
+ * interrupt callback routines and peripheral events.
+ * The other main features are:
+ *
+ * - Selectable transfer trigger source
+ *  - Software
+ *  - Event System
+ *  - Peripheral
+ * - Event input and output is supported for the four lower channels
+ * - Four level channel priority
+ * - Optional interrupt generation on transfer complete, channel error, or channel suspend
+ * - Supports multi-buffer or circular buffer mode by linking multiple descriptors
+ * - Beat size configurable as 8-bit, 16-bit, or 32-bit
+ *
+ * A simplified block diagram of the DMA Resource can be seen in
+ * \ref asfdoc_sam0_dma_module_block_diagram "the figure below".
+ *
+ * \anchor asfdoc_sam0_dma_module_block_diagram
+ * \dot
+ * digraph overview {
+ * splines = false;
+ * rankdir=LR;
+ *
+ * mux1 [label="Transfer Trigger", shape=box];
+ *
+ * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1];
+ * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue];
+ *
+ * mux1 -> dma;
+ * descriptor -> dma;
+ *
+ * interrupt [label="Interrupt", shape=box];
+ * events [label="Events", shape=box];
+ *
+ * dma:e -> interrupt:w;
+ * dma:e -> events:w;
+ *
+ * {rank=same; descriptor dma}
+ *
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_DMA_CHANNEL_STANDBY</td>
+ *    <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers
+ *
+ *   <table border="0" cellborder="1" cellspacing="0" >
+ *    <tr>
+ *        <th> Name </th> <th> Description </th>
+ *    </tr>
+ *    <tr>
+ *     <td > Beat </td>
+ *     <td > It is a single bus access by the DMAC.
+ *           Configurable as 8-bit, 16-bit, or 32-bit.
+ *     </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Burst </td>
+ *     <td> It is a transfer of n-beats (n=1,4,8,16).
+ *          For the DMAC module in SAM, the burst size is one beat.
+ *          Arbitration takes place each time a burst transfer is completed.
+ *     </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Block transfer </td>
+ *     <td>  A single block transfer is a configurable number of (1 to 64k)
+ *           beat transfers
+ *     </td>
+ *    </tr>
+ *   </table>
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels
+ * The DMAC in each device consists of several DMA channels, which
+ * along with the transfer descriptors defines the data transfer properties.
+ * - The transfer control descriptor defines the source and destination
+ * addresses, source and destination address increment settings, the
+ * block transfer count, and event output condition selection
+ * - Dedicated channel registers control the peripheral trigger source,
+ * trigger mode settings, event input actions, and channel priority level
+ * settings
+ *
+ * With a successful DMA resource allocation, a dedicated
+ * DMA channel will be assigned. The channel will be occupied until the
+ * DMA resource is freed. A DMA resource handle is used to identify the specific
+ * DMA resource.
+ * When there are multiple channels with active requests, the arbiter prioritizes
+ * the channels requesting access to the bus.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers
+ * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A
+ * transfer request can be triggered from software, peripheral, or an event. There
+ * are dedicated source trigger selections for each DMA channel usage.
+
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor
+ * The transfer descriptor resides in the SRAM and
+ * defines these channel properties.
+ *   <table border="0" cellborder="1" cellspacing="0" >
+ *    <tr>
+ *        <th> Field name </th> <th> Field width </th>
+ *    </tr>
+ *    <tr>
+ *     <td > Descriptor Next Address </td> <td > 32 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Destination Address </td> <td> 32 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Source Address </td> <td> 32 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Block Transfer Counter </td> <td> 16 bits </td>
+ *    </tr>
+ *    <tr>
+ *     <td > Block Transfer Control </td> <td> 16 bits </td>
+ *    </tr>
+ *   </table>
+ *
+ * Before starting a transfer, at least one descriptor should be configured.
+ * After a successful allocation of a DMA channel, the transfer descriptor can
+ * be added with a call to \ref dma_add_descriptor(). If there is a transfer
+ * descriptor already allocated to the DMA resource, the descriptor will
+ * be linked to the next descriptor address.
+ *
+ * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events
+ * Both an interrupt callback and an peripheral event can be triggered by the
+ * DMA transfer. Three types of callbacks are supported by the DMA driver:
+ * transfer complete, channel suspend, and transfer error. Each of these callback
+ * types can be registered and enabled for each channel independently through
+ * the DMA driver API.
+ *
+ * The DMAC module can also generate events on transfer complete. Event
+ * generation is enabled through the DMA channel, event channel configuration,
+ * and event user multiplexing is done through the events driver.
+ *
+ * The DMAC can generate events in the below cases:
+ *
+ * - When a block transfer is complete
+ *
+ * - When each beat transfer within a block transfer is complete
+ *
+ * \section asfdoc_sam0_dma_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_dma_extra. This includes:
+ * - \ref asfdoc_sam0_dma_extra_acronyms
+ * - \ref asfdoc_sam0_dma_extra_dependencies
+ * - \ref asfdoc_sam0_dma_extra_errata
+ * - \ref asfdoc_sam0_dma_extra_history
+ *
+ *
+ * \section asfdoc_sam0_dma_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_dma_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_dma_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include "conf_dma.h"
+
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
+#define FEATURE_DMA_CHANNEL_STANDBY
+#endif
+
+/** DMA invalid channel number. */
+#define DMA_INVALID_CHANNEL        0xff
+
+/** ExInitial description section. */
+extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM];
+
+/* DMA channel interrup flag. */
+extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM];
+
+/** DMA priority level. */
+enum dma_priority_level {
+	/** Priority level 0. */
+	DMA_PRIORITY_LEVEL_0,
+	/** Priority level 1. */
+	DMA_PRIORITY_LEVEL_1,
+	/** Priority level 2. */
+	DMA_PRIORITY_LEVEL_2,
+	/** Priority level 3. */
+	DMA_PRIORITY_LEVEL_3,
+};
+
+/** DMA input actions. */
+enum dma_event_input_action {
+	/** No action. */
+	DMA_EVENT_INPUT_NOACT,
+	/** Normal transfer and periodic transfer trigger. */
+	DMA_EVENT_INPUT_TRIG,
+	/** Conditional transfer trigger. */
+	DMA_EVENT_INPUT_CTRIG,
+	/** Conditional block transfer. */
+	DMA_EVENT_INPUT_CBLOCK,
+	/** Channel suspend operation. */
+	DMA_EVENT_INPUT_SUSPEND,
+	/** Channel resume operation. */
+	DMA_EVENT_INPUT_RESUME,
+	/** Skip next block suspend action. */
+	DMA_EVENT_INPUT_SSKIP,
+};
+
+/**
+ * Address increment step size. These bits select the address increment step
+ * size. The setting apply to source or destination address, depending on
+ * STEPSEL setting.
+ */
+enum dma_address_increment_stepsize {
+	/** The address is incremented by (beat size * 1). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
+	/** The address is incremented by (beat size * 2). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
+	/** The address is incremented by (beat size * 4). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
+	/** The address is incremented by (beat size * 8). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
+	/** The address is incremented by (beat size * 16). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
+	/** The address is incremented by (beat size * 32). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
+	/** The address is incremented by (beat size * 64). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
+	/** The address is incremented by (beat size * 128). */
+	DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
+};
+
+/**
+ * DMA step selection. This bit determines whether the step size setting
+ * is applied to source or destination address.
+ */
+enum dma_step_selection {
+	/** Step size settings apply to the destination address. */
+	DMA_STEPSEL_DST = 0,
+	/** Step size settings apply to the source address. */
+	DMA_STEPSEL_SRC,
+};
+
+/** The basic transfer unit in DMAC is a beat, which is defined as a
+ *  single bus access. Its size is configurable and applies to both read
+ *  and write. */
+enum dma_beat_size {
+	/** 8-bit access. */
+	DMA_BEAT_SIZE_BYTE = 0,
+	/** 16-bit access. */
+	DMA_BEAT_SIZE_HWORD,
+	/** 32-bit access. */
+	DMA_BEAT_SIZE_WORD,
+};
+
+/**
+ * Block action definitions.
+ */
+enum dma_block_action {
+	/** No action. */
+	DMA_BLOCK_ACTION_NOACT = 0,
+	/** Channel in normal operation and sets transfer complete interrupt flag
+	 *  after block transfer. */
+	DMA_BLOCK_ACTION_INT,
+	/** Trigger channel suspend after block transfer and sets channel
+	 *  suspend interrupt flag once the channel is suspended. */
+	DMA_BLOCK_ACTION_SUSPEND,
+	/** Sets transfer complete interrupt flag after a block transfer and
+	 *  trigger channel suspend. The channel suspend interrupt flag will be set
+	 *  once the channel is suspended. */
+	DMA_BLOCK_ACTION_BOTH,
+};
+
+/** Event output selection. */
+enum dma_event_output_selection {
+	/** Event generation disable. */
+	DMA_EVENT_OUTPUT_DISABLE = 0,
+	/** Event strobe when block transfer complete. */
+	DMA_EVENT_OUTPUT_BLOCK,
+	/** Event output reserved. */
+	DMA_EVENT_OUTPUT_RESERVED,
+	/** Event strobe when beat transfer complete. */
+	DMA_EVENT_OUTPUT_BEAT,
+};
+
+/** DMA trigger action type. */
+enum dma_transfer_trigger_action{
+	/** Perform a block transfer when triggered. */
+	DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
+	/** Perform a beat transfer when triggered. */
+	DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
+	/** Perform a transaction when triggered. */
+	DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
+};
+
+/**
+ * Callback types for DMA callback driver.
+ */
+enum dma_callback_type {
+	/** Callback for any of transfer errors. A transfer error is flagged
+     *	if a bus error is detected during an AHB access or when the DMAC
+	 *  fetches an invalid descriptor. */
+	DMA_CALLBACK_TRANSFER_ERROR,
+	/** Callback for transfer complete. */
+	DMA_CALLBACK_TRANSFER_DONE,
+	/** Callback for channel suspend. */
+	DMA_CALLBACK_CHANNEL_SUSPEND,
+	/** Number of available callbacks. */
+	DMA_CALLBACK_N,
+};
+
+/**
+ * DMA transfer descriptor configuration. When the source or destination address
+ * increment is enabled, the addresses stored into the configuration structure
+ * must correspond to the end of the transfer.
+ *
+ */
+struct dma_descriptor_config {
+	/** Descriptor valid flag used to identify whether a descriptor is
+	    valid or not */
+	bool descriptor_valid;
+	/** This is used to generate an event on specific transfer action in
+	    a channel. Supported only in four lower channels. */
+	enum dma_event_output_selection event_output_selection;
+	/** Action taken when a block transfer is completed */
+	enum dma_block_action block_action;
+	/** Beat size is configurable as 8-bit, 16-bit, or 32-bit */
+	enum dma_beat_size beat_size;
+	/** Used for enabling the source address increment */
+	bool src_increment_enable;
+	/** Used for enabling the destination address increment */
+	bool dst_increment_enable;
+	/** This bit selects whether the source or destination address is
+	    using the step size settings */
+	enum dma_step_selection step_selection;
+	/** The step size for source/destination address increment.
+	    The next address is calculated
+	    as next_addr = addr + (2^step_size * beat size). */
+	enum dma_address_increment_stepsize step_size;
+	/** It is the number of beats in a block. This count value is
+	 * decremented by one after each beat data transfer. */
+	uint16_t block_transfer_count;
+	/** Transfer source address */
+	uint32_t source_address;
+	/** Transfer destination address */
+	uint32_t destination_address;
+	/** Set to zero for static descriptors. This must have a valid memory
+	    address for linked descriptors. */
+	uint32_t next_descriptor_address;
+};
+
+/** Configurations for DMA events. */
+struct dma_events_config {
+	/** Event input actions */
+	enum dma_event_input_action input_action;
+	/** Enable DMA event output */
+	bool event_output_enable;
+};
+
+/** DMA configurations for transfer. */
+struct dma_resource_config {
+	/** DMA transfer priority */
+	enum dma_priority_level priority;
+	/**DMA peripheral trigger index */
+	uint8_t peripheral_trigger;
+	/** DMA trigger action */
+	enum dma_transfer_trigger_action trigger_action;
+#ifdef FEATURE_DMA_CHANNEL_STANDBY
+	/** Keep DMA channel enabled in standby sleep mode if true */
+	bool run_in_standby;
+#endif
+	/** DMA events configurations */
+	struct dma_events_config event_config;
+};
+
+/** Forward definition of the DMA resource. */
+struct dma_resource;
+/** Type definition for a DMA resource callback function. */
+typedef void (*dma_callback_t)(struct dma_resource *const resource);
+
+/** Structure for DMA transfer resource. */
+struct dma_resource {
+	/** Allocated DMA channel ID */
+	uint8_t channel_id;
+	/** Array of callback functions for DMA transfer job */
+	dma_callback_t callback[DMA_CALLBACK_N];
+	/** Bit mask for enabled callbacks */
+	uint8_t callback_enable;
+	/** Status of the last job */
+	volatile enum status_code job_status;
+	/** Transferred data size */
+	uint32_t transfered_size;
+	/** DMA transfer descriptor */
+	DmacDescriptor* descriptor;
+};
+
+/**
+ * \brief Get DMA resource status.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status of the DMA resource.
+ */
+static inline enum status_code dma_get_job_status(struct dma_resource *resource)
+{
+	Assert(resource);
+
+	return resource->job_status;
+}
+
+/**
+ * \brief Check if the given DMA resource is busy.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ *
+ * \return Status which indicates whether the DMA resource is busy.
+ *
+ * \retval true The DMA resource has an on-going transfer
+ * \retval false The DMA resource is not busy
+ */
+static inline bool dma_is_busy(struct dma_resource *resource)
+{
+	Assert(resource);
+
+	return (resource->job_status == STATUS_BUSY);
+}
+
+/**
+ * \brief Enable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_enable_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback_enable |= 1 << type;
+	g_chan_interrupt_flag[resource->channel_id] |= (1UL << type);
+}
+
+/**
+ * \brief Disable a callback function for a dedicated DMA resource.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_disable_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback_enable &= ~(1 << type);
+	g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK);
+	DMAC->CHINTENCLR.reg = (1UL << type);
+}
+
+/**
+ * \brief Register a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions, which can be registered:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] callback Pointer to the callback function
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_register_callback(struct dma_resource *resource,
+		dma_callback_t callback, enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback[type] = callback;
+}
+
+/**
+ * \brief Unregister a callback function for a dedicated DMA resource.
+ *
+ * There are three types of callback functions:
+ * - Callback for transfer complete
+ * - Callback for transfer error
+ * - Callback for channel suspend
+ *
+ * The application can unregister any of the callback functions which
+ * are already registered and are no longer needed.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ * \param[in] type Callback function type
+ *
+ */
+static inline void dma_unregister_callback(struct dma_resource *resource,
+		enum dma_callback_type type)
+{
+	Assert(resource);
+
+	resource->callback[type] = NULL;
+}
+
+/**
+ * \brief Will set a software trigger for resource.
+ *
+ * This function is used to set a software trigger on the DMA channel
+ * associated with resource. If a trigger is already pending no new trigger
+ * will be generated for the channel.
+ *
+ * \param[in] resource Pointer to the DMA resource
+ */
+static inline void dma_trigger_transfer(struct dma_resource *resource) {
+	Assert(resource);
+
+	DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
+}
+
+/**
+ * \brief Initializes DMA transfer configuration with predefined default values.
+ *
+ * This function will initialize a given DMA descriptor configuration structure to
+ * a set of known default values. This function should be called on
+ * any new instance of the configuration structure before being
+ * modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li Set the descriptor as valid
+ *  \li Disable event output
+ *  \li No block action
+ *  \li Set beat size as byte
+ *  \li Enable source increment
+ *  \li Enable destination increment
+ *  \li Step size is applied to the destination address
+ *  \li Address increment is beat size multiplied by 1
+ *  \li Default transfer size is set to 0
+ *  \li Default source address is set to NULL
+ *  \li Default destination address is set to NULL
+ *  \li Default next descriptor not available
+ * \param[out] config Pointer to the configuration
+ *
+ */
+static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
+{
+	Assert(config);
+
+	/* Set descriptor as valid */
+	config->descriptor_valid = true;
+	/* Disable event output */
+	config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
+	/* No block action */
+	config->block_action = DMA_BLOCK_ACTION_NOACT;
+	/* Set beat size to one byte */
+	config->beat_size = DMA_BEAT_SIZE_BYTE;
+	/* Enable source increment */
+	config->src_increment_enable = true;
+	/* Enable destination increment */
+	config->dst_increment_enable = true;
+	/* Step size is applied to the destination address */
+	config->step_selection = DMA_STEPSEL_DST;
+	/* Address increment is beat size multiplied by 1*/
+	config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
+	/* Default transfer size is set to 0 */
+	config->block_transfer_count = 0;
+	/* Default source address is set to NULL */
+	config->source_address = (uint32_t)NULL;
+	/* Default destination address is set to NULL */
+	config->destination_address = (uint32_t)NULL;
+	/** Next descriptor address set to 0 */
+	config->next_descriptor_address = 0;
+}
+
+/**
+ * \brief Update DMA descriptor.
+ *
+ * This function can update the descriptor of an allocated DMA resource.
+ *
+ */
+static inline void dma_update_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor)
+{
+	Assert(resource);
+
+	resource->descriptor = descriptor;
+}
+
+/**
+ * \brief Reset DMA descriptor.
+ *
+ * This function will clear the DESCADDR register of an allocated DMA resource.
+ *
+ */
+static inline void dma_reset_descriptor(struct dma_resource *resource)
+{
+	Assert(resource);
+
+	resource->descriptor = NULL;
+}
+
+void dma_get_config_defaults(struct dma_resource_config *config);
+enum status_code dma_allocate(struct dma_resource *resource,
+		struct dma_resource_config *config);
+enum status_code dma_free(struct dma_resource *resource);
+enum status_code dma_start_transfer_job(struct dma_resource *resource);
+void dma_abort_job(struct dma_resource *resource);
+void dma_suspend_job(struct dma_resource *resource);
+void dma_resume_job(struct dma_resource *resource);
+void dma_descriptor_create(DmacDescriptor* descriptor,
+	struct dma_descriptor_config *config);
+enum status_code dma_add_descriptor(struct dma_resource *resource,
+		DmacDescriptor* descriptor);
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver
+ *
+ * \section asfdoc_sam0_dma_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Acronym</th>
+ *     <th>Description</th>
+ *   </tr>
+ *   <tr>
+ *     <td>DMA</td>
+ *     <td>Direct Memory Access</td>
+ *   </tr>
+ *   <tr>
+ *     <td>DMAC</td>
+ *     <td>Direct Memory Access Controller </td>
+ *   </tr>
+ *   <tr>
+ *     <td>CPU</td>
+ *     <td>Central Processing Unit</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Driver"
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_dma_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *   <tr>
+ *     <th>Changelog</th>
+ *   </tr>
+ *   <tr>
+ *     <td>Add SAM C21 support</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Add SAM L21 support</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Add SAM R30 support</td>
+ *   </tr>
+ *   <tr>
+ *     <td>Initial Release</td>
+ *   </tr>
+ * </table>
+ */
+
+ /**
+ * \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_dma_basic_use_case
+ *
+ * \note More DMA usage examples are available in peripheral QSGs.
+ * A quick start guide for TC/TCC
+ * shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
+ * DMA transfer from peripheral to memory or from memory to peripheral;
+ * ADC/DAC shows peripheral to peripheral transfer.
+ *
+ * \page asfdoc_sam0_dma_document_revision_history Document Revision History
+ *
+ * <table>
+ *    <tr>
+ *        <th>Doc. Rev.</th>
+ *        <th>Date</th>
+ *        <th>Comments</th>
+ *    </tr>
+ *    <tr>
+ *        <td>42257C</td>
+ *        <td>12/2015</td>
+ *        <td>Added suppport for SAM L21/L22, SAM C21, SAM D09,SAMR30/R34 and SAM DA1</td>
+ *    </tr>
+ *    <tr>
+ *        <td>42257B</td>
+ *        <td>12/2014</td>
+ *        <td>Added support for SAM R21 and SAM D10/D11</td>
+ *    </tr>
+ *    <tr>
+ *        <td>42257A</td>
+ *        <td>02/2014</td>
+ *        <td>Initial release</td>
+ *    </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma_crc.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma_crc.h
index 91f77f9..fb3478a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma_crc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/dma_crc.h
@@ -1,220 +1,220 @@
-/**
- * \file
- *
- * \brief SAM DMA cyclic redundancy check (CRC) Driver
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef DMA_CRC_H_INCLUDED
-#define DMA_CRC_H_INCLUDED
-
-#include <compiler.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** DMA channel n offset. */
-#define DMA_CRC_CHANNEL_N_OFFSET 0x20
-
-/** CRC Polynomial Type. */
-enum crc_polynomial_type {
-	/** CRC16 (CRC-CCITT). */
-	CRC_TYPE_16,
-	/** CRC32 (IEEE 802.3). */
-	CRC_TYPE_32,
-};
-
-/** CRC Beat Type. */
-enum crc_beat_size {
-	/** Byte bus access. */
-	CRC_BEAT_SIZE_BYTE,
-	/** Half-word bus access. */
-	CRC_BEAT_SIZE_HWORD,
-	/** Word bus access. */
-	CRC_BEAT_SIZE_WORD,
-};
-
-/** Configurations for CRC calculation. */
-struct dma_crc_config {
-	/** CRC polynomial type. */
-	enum crc_polynomial_type type;
-	/** CRC beat size. */
-	enum crc_beat_size size;
-};
-
-/**
- * \brief Get DMA CRC default configurations.
- *
- * The default configuration is as follows:
- *  \li Polynomial type is set to CRC-16(CRC-CCITT)
- *  \li CRC Beat size: BYTE
- *
- * \param[in] config default configurations
- */
-static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
-{
-	Assert(config);
-
-	config->type = CRC_TYPE_16;
-	config->size = CRC_BEAT_SIZE_BYTE;
-}
-
-/**
- * \brief Enable DMA CRC module with an DMA channel.
- *
- * This function enables a CRC calculation with an allocated DMA channel. This channel ID
- * can be gotten from a successful \ref dma_allocate.
- *
- * \param[in] channel_id DMA channel expected with CRC calculation
- * \param[in] config CRC calculation configurations
- *
- * \return Status of the DMC CRC.
- * \retval STATUS_OK Get the DMA CRC module
- * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
- */
-static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
-		struct dma_crc_config *config)
-{
-	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
-		return STATUS_BUSY;
-	}
-
-	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
-		DMAC_CRCCTRL_CRCPOLY(config->type) |
-		DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
-
-	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Disable DMA CRC module.
- *
- */
-static inline void dma_crc_disable(void)
-{
-	DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
-	DMAC->CRCCTRL.reg = 0;
-}
-
-/**
- * \brief Get DMA CRC checksum value.
- *
- * \return Calculated CRC checksum.
- */
-static inline uint32_t dma_crc_get_checksum(void)
-{
-	if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
-		DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
-	}
-
-	return DMAC->CRCCHKSUM.reg;
-}
-
-/**
- * \brief Enable DMA CRC module with I/O.
- *
- * This function enables a CRC calculation with I/O mode.
- *
- * \param[in] config CRC calculation configurations.
- *
- * \return Status of the DMC CRC.
- * \retval STATUS_OK Get the DMA CRC module
- * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
- */
-static inline enum status_code dma_crc_io_enable(
-		struct dma_crc_config *config)
-{
-	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
-		return STATUS_BUSY;
-	}
-
-	if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
-		return STATUS_BUSY;
-	}
-
-	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
-		DMAC_CRCCTRL_CRCPOLY(config->type) |
-		DMAC_CRCCTRL_CRCSRC_IO;
-
-	if (config->type == CRC_TYPE_32) {
-		DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
-	}
-
-	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Calculate CRC with I/O.
- *
- * This function calculate the CRC of the input data buffer.
- *
- * \param[in] buffer CRC Pointer to calculation buffer
- * \param[in] total_beat_size Total beat size to be calculated
- *
- * \return Calculated CRC checksum value.
- */
-static inline void dma_crc_io_calculation(void *buffer,
-		 uint32_t total_beat_size)
-{
-	uint32_t counter = total_beat_size;
-	uint8_t *buffer_8;
-	uint16_t *buffer_16;
-	uint32_t *buffer_32;
-
-	for (counter=0; counter<total_beat_size; counter++) {
-		if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
-			buffer_8 = buffer;
-			DMAC->CRCDATAIN.reg = buffer_8[counter];
-		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
-			buffer_16 = buffer;
-			DMAC->CRCDATAIN.reg = buffer_16[counter];
-		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
-			buffer_32 = buffer;
-			DMAC->CRCDATAIN.reg = buffer_32[counter];
-		}
-		/* Wait several cycle to make sure CRC complete */
-		nop();
-		nop();
-		nop();
-		nop();
-	}
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* DMA_CRC_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM DMA cyclic redundancy check (CRC) Driver
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef DMA_CRC_H_INCLUDED
+#define DMA_CRC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMA channel n offset. */
+#define DMA_CRC_CHANNEL_N_OFFSET 0x20
+
+/** CRC Polynomial Type. */
+enum crc_polynomial_type {
+	/** CRC16 (CRC-CCITT). */
+	CRC_TYPE_16,
+	/** CRC32 (IEEE 802.3). */
+	CRC_TYPE_32,
+};
+
+/** CRC Beat Type. */
+enum crc_beat_size {
+	/** Byte bus access. */
+	CRC_BEAT_SIZE_BYTE,
+	/** Half-word bus access. */
+	CRC_BEAT_SIZE_HWORD,
+	/** Word bus access. */
+	CRC_BEAT_SIZE_WORD,
+};
+
+/** Configurations for CRC calculation. */
+struct dma_crc_config {
+	/** CRC polynomial type. */
+	enum crc_polynomial_type type;
+	/** CRC beat size. */
+	enum crc_beat_size size;
+};
+
+/**
+ * \brief Get DMA CRC default configurations.
+ *
+ * The default configuration is as follows:
+ *  \li Polynomial type is set to CRC-16(CRC-CCITT)
+ *  \li CRC Beat size: BYTE
+ *
+ * \param[in] config default configurations
+ */
+static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
+{
+	Assert(config);
+
+	config->type = CRC_TYPE_16;
+	config->size = CRC_BEAT_SIZE_BYTE;
+}
+
+/**
+ * \brief Enable DMA CRC module with an DMA channel.
+ *
+ * This function enables a CRC calculation with an allocated DMA channel. This channel ID
+ * can be gotten from a successful \ref dma_allocate.
+ *
+ * \param[in] channel_id DMA channel expected with CRC calculation
+ * \param[in] config CRC calculation configurations
+ *
+ * \return Status of the DMC CRC.
+ * \retval STATUS_OK Get the DMA CRC module
+ * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
+ */
+static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
+		struct dma_crc_config *config)
+{
+	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
+		return STATUS_BUSY;
+	}
+
+	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+		DMAC_CRCCTRL_CRCPOLY(config->type) |
+		DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
+
+	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disable DMA CRC module.
+ *
+ */
+static inline void dma_crc_disable(void)
+{
+	DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+	DMAC->CRCCTRL.reg = 0;
+}
+
+/**
+ * \brief Get DMA CRC checksum value.
+ *
+ * \return Calculated CRC checksum.
+ */
+static inline uint32_t dma_crc_get_checksum(void)
+{
+	if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
+		DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	}
+
+	return DMAC->CRCCHKSUM.reg;
+}
+
+/**
+ * \brief Enable DMA CRC module with I/O.
+ *
+ * This function enables a CRC calculation with I/O mode.
+ *
+ * \param[in] config CRC calculation configurations.
+ *
+ * \return Status of the DMC CRC.
+ * \retval STATUS_OK Get the DMA CRC module
+ * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
+ */
+static inline enum status_code dma_crc_io_enable(
+		struct dma_crc_config *config)
+{
+	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
+		return STATUS_BUSY;
+	}
+
+	if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
+		return STATUS_BUSY;
+	}
+
+	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+		DMAC_CRCCTRL_CRCPOLY(config->type) |
+		DMAC_CRCCTRL_CRCSRC_IO;
+
+	if (config->type == CRC_TYPE_32) {
+		DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
+	}
+
+	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calculate CRC with I/O.
+ *
+ * This function calculate the CRC of the input data buffer.
+ *
+ * \param[in] buffer CRC Pointer to calculation buffer
+ * \param[in] total_beat_size Total beat size to be calculated
+ *
+ * \return Calculated CRC checksum value.
+ */
+static inline void dma_crc_io_calculation(void *buffer,
+		 uint32_t total_beat_size)
+{
+	uint32_t counter = total_beat_size;
+	uint8_t *buffer_8;
+	uint16_t *buffer_16;
+	uint32_t *buffer_32;
+
+	for (counter=0; counter<total_beat_size; counter++) {
+		if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
+			buffer_8 = buffer;
+			DMAC->CRCDATAIN.reg = buffer_8[counter];
+		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
+			buffer_16 = buffer;
+			DMAC->CRCDATAIN.reg = buffer_16[counter];
+		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
+			buffer_32 = buffer;
+			DMAC->CRCDATAIN.reg = buffer_32[counter];
+		}
+		/* Wait several cycle to make sure CRC complete */
+		nop();
+		nop();
+		nop();
+		nop();
+	}
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_CRC_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/quick_start/qs_dma_basic.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/quick_start/qs_dma_basic.h
index 5a50217..0c67f9b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/quick_start/qs_dma_basic.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/dma/quick_start/qs_dma_basic.h
@@ -1,148 +1,148 @@
-/**
- * \file
- *
- * \brief SAM Direct Memory Access Controller(DMAC) Driver Quick Start
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-/**
- * \page asfdoc_sam0_dma_basic_use_case Quick Start Guide for Memory to Memory Data Transfer Using DMAC
- *
- * The supported board list:
- *    - SAM D21 Xplained Pro
- *    - SAM R21 Xplained Pro
- *    - SAM D11 Xplained Pro
- *    - SAM L21 Xplained Pro
- *    - SAM L22 Xplained Pro
- *    - SAM DA1 Xplained Pro
- *    - SAM HA1G16A Xplained Pro
- *
- * In this use case, the DMAC is configured for:
- *  \li Moving data from memory to memory
- *  \li Using software trigger
- *  \li Using DMA priority level 0
- *  \li Transaction as DMA trigger action
- *  \li No action on input events
- *  \li Output event not enabled
- *
- * \section asfdoc_sam0_dma_basic_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_dma_basic_use_casesetup_prereq Prerequisites
- * There are no special setup requirements for this use-case.
- *
- * \subsection asfdoc_sam0_dma_basic_use_casesetup_code Code
- * Copy-paste the following setup code to your user application:
- * \snippet qs_dma_basic.c setup
- *
- * Add the below section to user application initialization (typically the
- * start of \c main()):
- * \snippet qs_dma_basic.c setup_init
- *
- * \subsection asfdoc_sam0_dma_basic_use_casesetup_flow Workflow
- * -# Create a DMA resource configuration structure, which can be filled out to
- *    adjust the configuration of a single DMA transfer.
- *    \snippet qs_dma_basic.c setup_1
- *    \br
- *
- * -# Initialize the DMA resource configuration struct with the module's
- *    default values.
- *    \snippet qs_dma_basic.c setup_2
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Allocate a DMA resource with the configurations.
- *    \snippet qs_dma_basic.c setup_3
- *    \br
-
- * -# Declare a DMA transfer descriptor configuration structure, which can be
- *    filled out to adjust the configuration of a single DMA transfer.
- *    \snippet qs_dma_basic.c setup_4
- *    \br
- *
- * -# Initialize the DMA transfer descriptor configuration struct with the
- * module's  default values.
- *    \snippet qs_dma_basic.c setup_5
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Set the specific parameters for a DMA transfer with transfer size, source
- *    address, and destination address. In this example, we have enabled the
- *    source and destination address increment.
- *    The source and destination addresses to be stored into descriptor_config
- *    must correspond to the end of the transfer.
- *
- *    \snippet qs_dma_basic.c setup_6
- *    \br
- *
- * -# Create the DMA transfer descriptor.
- *    \snippet qs_dma_basic.c setup_7
- *    \br
- *
- * -# Add the DMA transfer descriptor to the allocated DMA resource.
- *    \snippet qs_dma_basic.c add_descriptor_to_dma_resource
- *    \br
- *
- * -# Register a callback to indicate transfer status.
- *    \snippet qs_dma_basic.c setup_callback_register
- *    \br
- *
- * -# Set the transfer done flag in the registered callback function.
- *    \snippet qs_dma_basic.c _transfer_done
- *    \br
- *
- * -# Enable the registered callbacks.
- *    \snippet qs_dma_basic.c setup_enable_callback
- *    \br
- *
- * \section asfdoc_sam0_dma_basic_use_case_main Use Case
- *
- * \subsection asfdoc_sam0_dma_basic_use_casecode_code Code
- * Add the following code at the start of \c main():
- * \snippet qs_dma_basic.c sample_resource
- * Copy the following code to your user application:
- * \snippet qs_dma_basic.c main
- *
- * \subsection dma_basic_use_case_code_flow Workflow
- * -# Start the DMA transfer job with the allocated DMA resource and
- *    transfer descriptor.
- *    \snippet qs_dma_basic.c main_1
- *
- * -# Set the software trigger for the DMA channel. This can be done before
- *    or after the DMA job is started. Note that all transfers needs a trigger
- *    to start.
- *    \snippet qs_dma_basic.c main_1_1
- *
- * -# Waiting for the setting of the transfer done flag.
- *    \snippet qs_dma_basic.c main_2
- */
+/**
+ * \file
+ *
+ * \brief SAM Direct Memory Access Controller(DMAC) Driver Quick Start
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+/**
+ * \page asfdoc_sam0_dma_basic_use_case Quick Start Guide for Memory to Memory Data Transfer Using DMAC
+ *
+ * The supported board list:
+ *    - SAM D21 Xplained Pro
+ *    - SAM R21 Xplained Pro
+ *    - SAM D11 Xplained Pro
+ *    - SAM L21 Xplained Pro
+ *    - SAM L22 Xplained Pro
+ *    - SAM DA1 Xplained Pro
+ *    - SAM HA1G16A Xplained Pro
+ *
+ * In this use case, the DMAC is configured for:
+ *  \li Moving data from memory to memory
+ *  \li Using software trigger
+ *  \li Using DMA priority level 0
+ *  \li Transaction as DMA trigger action
+ *  \li No action on input events
+ *  \li Output event not enabled
+ *
+ * \section asfdoc_sam0_dma_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_dma_basic_use_casesetup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_dma_basic_use_casesetup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_dma_basic.c setup
+ *
+ * Add the below section to user application initialization (typically the
+ * start of \c main()):
+ * \snippet qs_dma_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_dma_basic_use_casesetup_flow Workflow
+ * -# Create a DMA resource configuration structure, which can be filled out to
+ *    adjust the configuration of a single DMA transfer.
+ *    \snippet qs_dma_basic.c setup_1
+ *    \br
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_dma_basic.c setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_dma_basic.c setup_3
+ *    \br
+
+ * -# Declare a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_dma_basic.c setup_4
+ *    \br
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the
+ * module's  default values.
+ *    \snippet qs_dma_basic.c setup_5
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address. In this example, we have enabled the
+ *    source and destination address increment.
+ *    The source and destination addresses to be stored into descriptor_config
+ *    must correspond to the end of the transfer.
+ *
+ *    \snippet qs_dma_basic.c setup_6
+ *    \br
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_dma_basic.c setup_7
+ *    \br
+ *
+ * -# Add the DMA transfer descriptor to the allocated DMA resource.
+ *    \snippet qs_dma_basic.c add_descriptor_to_dma_resource
+ *    \br
+ *
+ * -# Register a callback to indicate transfer status.
+ *    \snippet qs_dma_basic.c setup_callback_register
+ *    \br
+ *
+ * -# Set the transfer done flag in the registered callback function.
+ *    \snippet qs_dma_basic.c _transfer_done
+ *    \br
+ *
+ * -# Enable the registered callbacks.
+ *    \snippet qs_dma_basic.c setup_enable_callback
+ *    \br
+ *
+ * \section asfdoc_sam0_dma_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_dma_basic_use_casecode_code Code
+ * Add the following code at the start of \c main():
+ * \snippet qs_dma_basic.c sample_resource
+ * Copy the following code to your user application:
+ * \snippet qs_dma_basic.c main
+ *
+ * \subsection dma_basic_use_case_code_flow Workflow
+ * -# Start the DMA transfer job with the allocated DMA resource and
+ *    transfer descriptor.
+ *    \snippet qs_dma_basic.c main_1
+ *
+ * -# Set the software trigger for the DMA channel. This can be done before
+ *    or after the DMA job is started. Note that all transfers needs a trigger
+ *    to start.
+ *    \snippet qs_dma_basic.c main_1_1
+ *
+ * -# Waiting for the setting of the transfer done flag.
+ *    \snippet qs_dma_basic.c main_2
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.c
index d7a834f..87ef65a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.c
@@ -1,99 +1,99 @@
-/**
- * \file
- *
- * \brief SAM GPIO Port Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include <port.h>
-
-/**
- *  \brief Writes a Port pin configuration to the hardware module.
- *
- *  Writes out a given configuration of a Port pin configuration to the hardware
- *  module.
- *
- *  \note If the pin direction is set as an output, the pull-up/pull-down input
- *        configuration setting is ignored.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin to configure
- *  \param[in] config    Configuration settings for the pin
- */
-void port_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct port_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
-
-	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
-	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
-	pinmux_config.powersave    = config->powersave;
-
-	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
-}
-
-/**
- *  \brief Writes a Port group configuration group to the hardware module.
- *
- *  Writes out a given configuration of a Port group configuration to the
- *  hardware module.
- *
- *  \note If the pin direction is set as an output, the pull-up/pull-down input
- *        configuration setting is ignored.
- *
- *  \param[out] port    Base of the PORT module to write to
- *  \param[in]  mask    Mask of the port pin(s) to configure
- *  \param[in]  config  Configuration settings for the pin group
- */
-void port_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct port_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(port);
-	Assert(config);
-
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
-
-	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
-	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
-	pinmux_config.powersave    = config->powersave;
-
-	system_pinmux_group_set_config(port, mask, &pinmux_config);
-}
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <port.h>
+
+/**
+ *  \brief Writes a Port pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a Port pin configuration to the hardware
+ *  module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to configure
+ *  \param[in] config    Configuration settings for the pin
+ */
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ *  \brief Writes a Port group configuration group to the hardware module.
+ *
+ *  Writes out a given configuration of a Port group configuration to the
+ *  hardware module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[out] port    Base of the PORT module to write to
+ *  \param[in]  mask    Mask of the port pin(s) to configure
+ *  \param[in]  config  Configuration settings for the pin group
+ */
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(port);
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_group_set_config(port, mask, &pinmux_config);
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.h
index f3c50f6..2d30a03 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/port.h
@@ -1,785 +1,785 @@
-/**
- * \file
- *
- * \brief SAM GPIO Port Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef PORT_H_INCLUDED
-#define PORT_H_INCLUDED
-
-/**
- * \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
- * an interface for the configuration and management of the device's General
- * Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
- * and writing.
- *
- * The following peripheral is used by this module:
- *  - PORT (GPIO Management)
- *
- * The following devices can use this module:
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM L21/L22
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM C20/C21
- *  - Atmel | SMART SAM HA1
- *  - Atmel | SMART SAM R30
- *  - Atmel | SMART SAM R34
- *  - Atmel | SMART SAM R35
- *
- * The outline of this documentation is as follows:
- *  - \ref asfdoc_sam0_port_prerequisites
- *  - \ref asfdoc_sam0_port_module_overview
- *  - \ref asfdoc_sam0_port_special_considerations
- *  - \ref asfdoc_sam0_port_extra_info
- *  - \ref asfdoc_sam0_port_examples
- *  - \ref asfdoc_sam0_port_api_overview
- *
- *
- * \section asfdoc_sam0_port_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_port_module_overview Module Overview
- *
- * The device GPIO (PORT) module provides an interface between the user
- * application logic and external hardware peripherals, when general pin state
- * manipulation is required. This driver provides an easy-to-use interface to
- * the physical pin input samplers and output drivers, so that pins can be read
- * from or written to for general purpose external hardware control.
- *
- * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
- * <table>
- *  <tr>
- *    <th>Driver Feature Macro</th>
- *    <th>Supported devices</th>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_PORT_INPUT_EVENT</td>
- *    <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
- *  </tr>
- * </table>
- * \note The specific features are only available in the driver when the
- * selected device supports those features.
- *
- * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
- * SAM devices use two naming conventions for the I/O pins in the device; one
- * physical and one logical. Each physical pin on a device package is assigned
- * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
- * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
- * former is used to map physical pins to their physical internal device module
- * counterparts, for simplicity the design of this driver uses the logical GPIO
- * numbers instead.
- *
- * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
- *
- * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
- * this module is interconnected within the device.
- *
- * \anchor asfdoc_sam0_port_module_int_connections
- * \dot
- * digraph overview {
- *   node [label="Port Pad" shape=square] pad;
- *
- *   subgraph driver {
- *     node [label="Peripheral MUX" shape=trapezium] pinmux;
- *     node [label="GPIO Module" shape=ellipse] gpio;
- *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
- *   }
- *
- *   pinmux -> gpio;
- *   pad    -> pinmux;
- *   pinmux -> peripherals;
- * }
- * \enddot
- *
- *
- * \section asfdoc_sam0_port_special_considerations Special Considerations
- *
- * The SAM port pin input sampler can be disabled when the pin is configured
- * in pure output mode to save power; reading the pin state of a pin configured
- * in output-only mode will read the logical output state that was last set.
- *
- * \section asfdoc_sam0_port_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_port_extra. This includes:
- *  - \ref asfdoc_sam0_port_extra_acronyms
- *  - \ref asfdoc_sam0_port_extra_dependencies
- *  - \ref asfdoc_sam0_port_extra_errata
- *  - \ref asfdoc_sam0_port_extra_history
- *
- *
- * \section asfdoc_sam0_port_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_port_exqsg.
- *
- *
- * \section asfdoc_sam0_port_api_overview API Overview
- * @{
- */
-
-#include <compiler.h>
-#include <pinmux.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name Driver Feature Definition
- * Define port features set according to different device family.
- * @{
-*/
-#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
-/** Event input control feature support for PORT group. */
-#  define FEATURE_PORT_INPUT_EVENT
-#endif
-/*@}*/
-
-/** \name PORT Alias Macros
- * @{
- */
-
-/** Convenience definition for GPIO module group A on the device (if
- *  available). */
-#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
-#  define PORTA             PORT->Group[0]
-#endif
-
-#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
-/** Convenience definition for GPIO module group B on the device (if
- *  available). */
-#  define PORTB             PORT->Group[1]
-#endif
-
-#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
-/** Convenience definition for GPIO module group C on the device (if
- *  available). */
-#  define PORTC             PORT->Group[2]
-#endif
-
-#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
-/** Convenience definition for GPIO module group D on the device (if
- *  available). */
-#  define PORTD             PORT->Group[3]
-#endif
-
-/** @} */
-
-/**
- *  \brief Port pin direction configuration enum.
- *
- *  Enum for the possible pin direction settings of the port pin configuration
- *  structure, to indicate the direction the pin should use.
- */
-enum port_pin_dir {
-	/** The pin's input buffer should be enabled, so that the pin state can
-	 *  be read */
-	PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
-	/** The pin's output buffer should be enabled, so that the pin state can
-	 *  be set */
-	PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
-	/** The pin's output and input buffers should be enabled, so that the pin
-	 *  state can be set and read back */
-	PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
-};
-
-/**
- *  \brief Port pin input pull configuration enum.
- *
- *  Enum for the possible pin pull settings of the port pin configuration
- *  structure, to indicate the type of logic level pull the pin should use.
- */
-enum port_pin_pull {
-	/** No logical pull should be applied to the pin */
-	PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
-	/** Pin should be pulled up when idle */
-	PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
-	/** Pin should be pulled down when idle */
-	PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
-};
-
-#ifdef FEATURE_PORT_INPUT_EVENT
-/**
- *  \brief Port input event action.
- *
- *  List of port input events action on pin.
- */
-enum port_input_event_action {
-	/** Event out to pin */
-	PORT_INPUT_EVENT_ACTION_OUT = 0,
-	/** Set output register of pin on event */
-	PORT_INPUT_EVENT_ACTION_SET,
-	/** Clear output register pin on event */
-	PORT_INPUT_EVENT_ACTION_CLR,
-	/** Toggle output register pin on event */
-	PORT_INPUT_EVENT_ACTION_TGL,
-};
-
-/**
- *  \brief Port input event.
- *
- *  List of port input events.
- */
-enum port_input_event{
-	/** Port input event 0 */
-	PORT_INPUT_EVENT_0 = 0,
-	/** Port input event 1 */
-	PORT_INPUT_EVENT_1 = 1,
-	/** Port input event 2 */
-	PORT_INPUT_EVENT_2 = 2,
-	/** Port input event 3 */
-	PORT_INPUT_EVENT_3 = 3,
-};
-
-/**
- *  \brief Port input event configuration structure.
- *
- *  Configuration structure for a port input event.
- */
-struct port_input_event_config{
-	/** Port input event action */
-	enum port_input_event_action  action;
-	/** GPIO pin */
-	uint8_t gpio_pin;
-};
-#endif
-
-/**
- *  \brief Port pin configuration structure.
- *
- *  Configuration structure for a port pin instance. This structure should be
- *  initialized by the \ref port_get_config_defaults() function before being
- *  modified by the user application.
- */
-struct port_config {
-	/** Port buffer input/output direction */
-	enum port_pin_dir  direction;
-
-	/** Port pull-up/pull-down for input pins */
-	enum port_pin_pull input_pull;
-
-	/** Enable lowest possible powerstate on the pin
-	 *
-	 *  \note All other configurations will be ignored, the pin will be disabled.
-	 */
-	bool powersave;
-};
-
-/** \name State Reading/Writing (Physical Group Orientated)
- * @{
- */
-
-/**
- *  \brief Retrieves the PORT module group instance from a given GPIO pin number.
- *
- *  Retrieves the PORT module group instance associated with a given logical
- *  GPIO pin number.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin to convert
- *
- *  \return Base address of the associated PORT module.
- */
-static inline PortGroup* port_get_group_from_gpio_pin(
-		const uint8_t gpio_pin)
-{
-	return system_pinmux_get_group_from_gpio_pin(gpio_pin);
-}
-
-/**
- *  \brief Retrieves the state of a group of port pins that are configured as inputs.
- *
- *  Reads the current logic level of a port module's pins and returns the
- *  current levels as a bitmask.
- *
- *  \param[in] port  Base of the PORT module to read from
- *  \param[in] mask  Mask of the port pin(s) to read
- *
- *  \return Status of the port pin(s) input buffers.
- */
-static inline uint32_t port_group_get_input_level(
-		const PortGroup *const port,
-		const uint32_t mask)
-{
-	/* Sanity check arguments */
-	Assert(port);
-
-	return (port->IN.reg & mask);
-}
-
-/**
- *  \brief Retrieves the state of a group of port pins that are configured as outputs.
- *
- *  Reads the current logical output level of a port module's pins and returns
- *  the current levels as a bitmask.
- *
- *  \param[in] port  Base of the PORT module to read from
- *  \param[in] mask  Mask of the port pin(s) to read
- *
- *  \return Status of the port pin(s) output buffers.
- */
-static inline uint32_t port_group_get_output_level(
-		const PortGroup *const port,
-		const uint32_t mask)
-{
-	/* Sanity check arguments */
-	Assert(port);
-
-	return (port->OUT.reg & mask);
-}
-
-/**
- *  \brief Sets the state of a group of port pins that are configured as outputs.
- *
- *  Sets the current output level of a port module's pins to a given logic
- *  level.
- *
- *  \param[out] port        Base of the PORT module to write to
- *  \param[in]  mask        Mask of the port pin(s) to change
- *  \param[in]  level_mask  Mask of the port level(s) to set
- */
-static inline void port_group_set_output_level(
-		PortGroup *const port,
-		const uint32_t mask,
-		const uint32_t level_mask)
-{
-	/* Sanity check arguments */
-	Assert(port);
-
-	port->OUTSET.reg = (mask &  level_mask);
-	port->OUTCLR.reg = (mask & ~level_mask);
-}
-
-/**
- *  \brief Toggles the state of a group of port pins that are configured as an outputs.
- *
- *  Toggles the current output levels of a port module's pins.
- *
- *  \param[out] port  Base of the PORT module to write to
- *  \param[in]  mask  Mask of the port pin(s) to toggle
- */
-static inline void port_group_toggle_output_level(
-		PortGroup *const port,
-		const uint32_t mask)
-{
-	/* Sanity check arguments */
-	Assert(port);
-
-	port->OUTTGL.reg = mask;
-}
-
-/** @} */
-
-/** \name Configuration and Initialization
- * @{
- */
-
-/**
- *  \brief Initializes a Port pin/group configuration structure to defaults.
- *
- *  Initializes a given Port pin/group configuration structure to a set of
- *  known default values. This function should be called on all new
- *  instances of these configuration structures before being modified by the
- *  user application.
- *
- *  The default configuration is as follows:
- *   \li Input mode with internal pull-up enabled
- *
- *  \param[out] config  Configuration structure to initialize to default values
- */
-static inline void port_get_config_defaults(
-		struct port_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->direction  = PORT_PIN_DIR_INPUT;
-	config->input_pull = PORT_PIN_PULL_UP;
-	config->powersave  = false;
-}
-
-void port_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct port_config *const config);
-
-void port_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct port_config *const config);
-
-/** @} */
-
-/** \name State Reading/Writing (Logical Pin Orientated)
- * @{
- */
-
-/**
- *  \brief Retrieves the state of a port pin that is configured as an input.
- *
- *  Reads the current logic level of a port pin and returns the current
- *  level as a Boolean value.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin to read
- *
- *  \return Status of the port pin's input buffer.
- */
-static inline bool port_pin_get_input_level(
-		const uint8_t gpio_pin)
-{
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
-
-	return (port_base->IN.reg & pin_mask);
-}
-
-/**
- *  \brief Retrieves the state of a port pin that is configured as an output.
- *
- *  Reads the current logical output level of a port pin and returns the current
- *  level as a Boolean value.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin to read
- *
- *  \return Status of the port pin's output buffer.
- */
-static inline bool port_pin_get_output_level(
-		const uint8_t gpio_pin)
-{
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
-
-	return (port_base->OUT.reg & pin_mask);
-}
-
-/**
- *  \brief Sets the state of a port pin that is configured as an output.
- *
- *  Sets the current output level of a port pin to a given logic level.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin to write to
- *  \param[in] level     Logical level to set the given pin to
- */
-static inline void port_pin_set_output_level(
-		const uint8_t gpio_pin,
-		const bool level)
-{
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
-
-	/* Set the pin to high or low atomically based on the requested level */
-	if (level) {
-		port_base->OUTSET.reg = pin_mask;
-	} else {
-		port_base->OUTCLR.reg = pin_mask;
-	}
-}
-
-/**
- *  \brief Toggles the state of a port pin that is configured as an output.
- *
- *  Toggles the current output level of a port pin.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin to toggle
- */
-static inline void port_pin_toggle_output_level(
-		const uint8_t gpio_pin)
-{
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
-
-	/* Toggle pin output level */
-	port_base->OUTTGL.reg = pin_mask;
-}
-
-/** @} */
-
-#ifdef FEATURE_PORT_INPUT_EVENT
-
-/** \name Port Input Event
- * @{
- */
-
-/**
- *  \brief Enable the port event input.
- *
- *  Enable the port event input with the given pin and event.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin
- *  \param[in] n  Port input event
- *
- * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
- * \retval STATUS_OK               Successfully
- */
-static inline enum status_code port_enable_input_event(
-		const uint8_t gpio_pin,
-		const enum port_input_event n)
-{
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	switch (n) {
-		case PORT_INPUT_EVENT_0:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
-			break;
-		case PORT_INPUT_EVENT_1:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
-			break;
-		case PORT_INPUT_EVENT_2:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
-			break;
-		case PORT_INPUT_EVENT_3:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
-}
-
-/**
- *  \brief Disable the port event input.
- *
- *  Disable the port event input with the given pin and event.
- *
- *  \param[in] gpio_pin  Index of the GPIO pin
- *  \param[in] gpio_pin  Port input event
- *
- * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
- * \retval STATUS_OK               Successfully
- */
-static inline enum status_code port_disable_input_event(
-		const uint8_t gpio_pin,
-		const enum port_input_event n)
-{
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	switch (n) {
-		case PORT_INPUT_EVENT_0:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
-			break;
-		case PORT_INPUT_EVENT_1:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
-			break;
-		case PORT_INPUT_EVENT_2:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
-			break;
-		case PORT_INPUT_EVENT_3:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
-}
-
-/**
- * \brief Retrieve the default configuration for port input event.
- *
- * Fills a configuration structure with the default configuration for port input event:
- *   - Event output to pin
- *   - Event action to be executed on PIN 0
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void port_input_event_get_config_defaults(
-		struct port_input_event_config *const config)
-{
-	Assert(config);
-	config->action   = PORT_INPUT_EVENT_ACTION_OUT;
-	config->gpio_pin = 0;
-}
-
-/**
- * \brief Configure port input event.
- *
- * Configures port input event with the given configuration settings.
- *
- * \param[in] config  Port input even configuration structure containing the new config
- *
- * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
- * \retval STATUS_OK               Successfully
- */
-
-static inline enum status_code port_input_event_set_config(
-		const enum port_input_event n,
-		struct port_input_event_config *const config)
-{
-	Assert(config);
-	PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
-	uint8_t pin_index = config->gpio_pin % 32;
-	struct port_config pin_conf;
-
-	port_get_config_defaults(&pin_conf);
-	/* Configure the GPIO pin as outputs*/
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(config->gpio_pin, &pin_conf);
-
-	switch (n) {
-		case PORT_INPUT_EVENT_0:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
-									| PORT_EVCTRL_PID0(pin_index);
-			break;
-		case PORT_INPUT_EVENT_1:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
-						   		   | PORT_EVCTRL_PID1(pin_index);
-			break;
-		case PORT_INPUT_EVENT_2:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
-						   		   | PORT_EVCTRL_PID2(pin_index);
-			break;
-		case PORT_INPUT_EVENT_3:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
-						   		   | PORT_EVCTRL_PID3(pin_index);
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
-}
-
-/** @} */
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-/**
- * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
- *
- * \section asfdoc_sam0_port_extra_acronyms Acronyms
- * Below is a table listing the acronyms used in this module, along with their
- * intended meanings.
- *
- * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>GPIO</td>
- *		<td>General Purpose Input/Output</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
- * </table>
- *
- *
- * \section asfdoc_sam0_port_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
- *
- *
- * \section asfdoc_sam0_port_extra_errata Errata
- * There are no errata related to this driver.
- *
- *
- * \section asfdoc_sam0_port_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added input event feature</td>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
- * </table>
- */
-
-/**
- * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
- *
- * This is a list of the available Quick Start guides (QSGs) and example
- * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
- * step-by-step instructions to configure and use this driver in a selection of
- * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.
- *
- *  - \subpage asfdoc_sam0_port_basic_use_case
- *
- * \page asfdoc_sam0_port_document_revision_history Document Revision History
- *
- * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42113E</td>
- *		<td>12/2015</td>
- *		<td>Added input event feature.
- *			Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30/R34 and SAM DA1.</td>
- *	</tr>
- *	<tr>
- *		<td>42113D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42113C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42113B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42113A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
- * </table>
- */
-
-#endif
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef PORT_H_INCLUDED
+#define PORT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's General
+ * Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
+ * and writing.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (GPIO Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_port_prerequisites
+ *  - \ref asfdoc_sam0_port_module_overview
+ *  - \ref asfdoc_sam0_port_special_considerations
+ *  - \ref asfdoc_sam0_port_extra_info
+ *  - \ref asfdoc_sam0_port_examples
+ *  - \ref asfdoc_sam0_port_api_overview
+ *
+ *
+ * \section asfdoc_sam0_port_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_port_module_overview Module Overview
+ *
+ * The device GPIO (PORT) module provides an interface between the user
+ * application logic and external hardware peripherals, when general pin state
+ * manipulation is required. This driver provides an easy-to-use interface to
+ * the physical pin input samplers and output drivers, so that pins can be read
+ * from or written to for general purpose external hardware control.
+ *
+ * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_PORT_INPUT_EVENT</td>
+ *    <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_port_module_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_port_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampler can be disabled when the pin is configured
+ * in pure output mode to save power; reading the pin state of a pin configured
+ * in output-only mode will read the logical output state that was last set.
+ *
+ * \section asfdoc_sam0_port_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_port_extra. This includes:
+ *  - \ref asfdoc_sam0_port_extra_acronyms
+ *  - \ref asfdoc_sam0_port_extra_dependencies
+ *  - \ref asfdoc_sam0_port_extra_errata
+ *  - \ref asfdoc_sam0_port_extra_history
+ *
+ *
+ * \section asfdoc_sam0_port_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_port_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_port_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
+/** Event input control feature support for PORT group. */
+#  define FEATURE_PORT_INPUT_EVENT
+#endif
+/*@}*/
+
+/** \name PORT Alias Macros
+ * @{
+ */
+
+/** Convenience definition for GPIO module group A on the device (if
+ *  available). */
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
+#  define PORTA             PORT->Group[0]
+#endif
+
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group B on the device (if
+ *  available). */
+#  define PORTB             PORT->Group[1]
+#endif
+
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group C on the device (if
+ *  available). */
+#  define PORTC             PORT->Group[2]
+#endif
+
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group D on the device (if
+ *  available). */
+#  define PORTD             PORT->Group[3]
+#endif
+
+/** @} */
+
+/**
+ *  \brief Port pin direction configuration enum.
+ *
+ *  Enum for the possible pin direction settings of the port pin configuration
+ *  structure, to indicate the direction the pin should use.
+ */
+enum port_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set */
+	PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should be enabled, so that the pin
+	 *  state can be set and read back */
+	PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ *  \brief Port pin input pull configuration enum.
+ *
+ *  Enum for the possible pin pull settings of the port pin configuration
+ *  structure, to indicate the type of logic level pull the pin should use.
+ */
+enum port_pin_pull {
+	/** No logical pull should be applied to the pin */
+	PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+/**
+ *  \brief Port input event action.
+ *
+ *  List of port input events action on pin.
+ */
+enum port_input_event_action {
+	/** Event out to pin */
+	PORT_INPUT_EVENT_ACTION_OUT = 0,
+	/** Set output register of pin on event */
+	PORT_INPUT_EVENT_ACTION_SET,
+	/** Clear output register pin on event */
+	PORT_INPUT_EVENT_ACTION_CLR,
+	/** Toggle output register pin on event */
+	PORT_INPUT_EVENT_ACTION_TGL,
+};
+
+/**
+ *  \brief Port input event.
+ *
+ *  List of port input events.
+ */
+enum port_input_event{
+	/** Port input event 0 */
+	PORT_INPUT_EVENT_0 = 0,
+	/** Port input event 1 */
+	PORT_INPUT_EVENT_1 = 1,
+	/** Port input event 2 */
+	PORT_INPUT_EVENT_2 = 2,
+	/** Port input event 3 */
+	PORT_INPUT_EVENT_3 = 3,
+};
+
+/**
+ *  \brief Port input event configuration structure.
+ *
+ *  Configuration structure for a port input event.
+ */
+struct port_input_event_config{
+	/** Port input event action */
+	enum port_input_event_action  action;
+	/** GPIO pin */
+	uint8_t gpio_pin;
+};
+#endif
+
+/**
+ *  \brief Port pin configuration structure.
+ *
+ *  Configuration structure for a port pin instance. This structure should be
+ *  initialized by the \ref port_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct port_config {
+	/** Port buffer input/output direction */
+	enum port_pin_dir  direction;
+
+	/** Port pull-up/pull-down for input pins */
+	enum port_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name State Reading/Writing (Physical Group Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ *  Retrieves the PORT module group instance associated with a given logical
+ *  GPIO pin number.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ *  \return Base address of the associated PORT module.
+ */
+static inline PortGroup* port_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as inputs.
+ *
+ *  Reads the current logic level of a port module's pins and returns the
+ *  current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) input buffers.
+ */
+static inline uint32_t port_group_get_input_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->IN.reg & mask);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as outputs.
+ *
+ *  Reads the current logical output level of a port module's pins and returns
+ *  the current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) output buffers.
+ */
+static inline uint32_t port_group_get_output_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->OUT.reg & mask);
+}
+
+/**
+ *  \brief Sets the state of a group of port pins that are configured as outputs.
+ *
+ *  Sets the current output level of a port module's pins to a given logic
+ *  level.
+ *
+ *  \param[out] port        Base of the PORT module to write to
+ *  \param[in]  mask        Mask of the port pin(s) to change
+ *  \param[in]  level_mask  Mask of the port level(s) to set
+ */
+static inline void port_group_set_output_level(
+		PortGroup *const port,
+		const uint32_t mask,
+		const uint32_t level_mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTSET.reg = (mask &  level_mask);
+	port->OUTCLR.reg = (mask & ~level_mask);
+}
+
+/**
+ *  \brief Toggles the state of a group of port pins that are configured as an outputs.
+ *
+ *  Toggles the current output levels of a port module's pins.
+ *
+ *  \param[out] port  Base of the PORT module to write to
+ *  \param[in]  mask  Mask of the port pin(s) to toggle
+ */
+static inline void port_group_toggle_output_level(
+		PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTTGL.reg = mask;
+}
+
+/** @} */
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ *  \brief Initializes a Port pin/group configuration structure to defaults.
+ *
+ *  Initializes a given Port pin/group configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Input mode with internal pull-up enabled
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void port_get_config_defaults(
+		struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->direction  = PORT_PIN_DIR_INPUT;
+	config->input_pull = PORT_PIN_PULL_UP;
+	config->powersave  = false;
+}
+
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config);
+
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config);
+
+/** @} */
+
+/** \name State Reading/Writing (Logical Pin Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an input.
+ *
+ *  Reads the current logic level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's input buffer.
+ */
+static inline bool port_pin_get_input_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->IN.reg & pin_mask);
+}
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an output.
+ *
+ *  Reads the current logical output level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's output buffer.
+ */
+static inline bool port_pin_get_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->OUT.reg & pin_mask);
+}
+
+/**
+ *  \brief Sets the state of a port pin that is configured as an output.
+ *
+ *  Sets the current output level of a port pin to a given logic level.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to write to
+ *  \param[in] level     Logical level to set the given pin to
+ */
+static inline void port_pin_set_output_level(
+		const uint8_t gpio_pin,
+		const bool level)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Set the pin to high or low atomically based on the requested level */
+	if (level) {
+		port_base->OUTSET.reg = pin_mask;
+	} else {
+		port_base->OUTCLR.reg = pin_mask;
+	}
+}
+
+/**
+ *  \brief Toggles the state of a port pin that is configured as an output.
+ *
+ *  Toggles the current output level of a port pin.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to toggle
+ */
+static inline void port_pin_toggle_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Toggle pin output level */
+	port_base->OUTTGL.reg = pin_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+
+/** \name Port Input Event
+ * @{
+ */
+
+/**
+ *  \brief Enable the port event input.
+ *
+ *  Enable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] n  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_enable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ *  \brief Disable the port event input.
+ *
+ *  Disable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] gpio_pin  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_disable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieve the default configuration for port input event.
+ *
+ * Fills a configuration structure with the default configuration for port input event:
+ *   - Event output to pin
+ *   - Event action to be executed on PIN 0
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void port_input_event_get_config_defaults(
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	config->action   = PORT_INPUT_EVENT_ACTION_OUT;
+	config->gpio_pin = 0;
+}
+
+/**
+ * \brief Configure port input event.
+ *
+ * Configures port input event with the given configuration settings.
+ *
+ * \param[in] config  Port input even configuration structure containing the new config
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+
+static inline enum status_code port_input_event_set_config(
+		const enum port_input_event n,
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
+	uint8_t pin_index = config->gpio_pin % 32;
+	struct port_config pin_conf;
+
+	port_get_config_defaults(&pin_conf);
+	/* Configure the GPIO pin as outputs*/
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(config->gpio_pin, &pin_conf);
+
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+									| PORT_EVCTRL_PID0(pin_index);
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
+						   		   | PORT_EVCTRL_PID1(pin_index);
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
+						   		   | PORT_EVCTRL_PID2(pin_index);
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
+						   		   | PORT_EVCTRL_PID3(pin_index);
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/** @} */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
+ *
+ * \section asfdoc_sam0_port_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_port_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_port_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_port_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added input event feature</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_port_basic_use_case
+ *
+ * \page asfdoc_sam0_port_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113E</td>
+ *		<td>12/2015</td>
+ *		<td>Added input event feature.
+ *			Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30/R34 and SAM DA1.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h
index 5281e1a..b171c69 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h
@@ -1,98 +1,98 @@
-/**
- * \file
- *
- * \brief SAM GPIO Port Driver Quick Start
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-/**
- * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
- *
- * In this use case, the PORT module is configured for:
- *  \li One pin in input mode, with pull-up enabled
- *  \li One pin in output mode
- *
- * This use case sets up the PORT to read the current state of a GPIO pin set as
- * an input, and mirrors the opposite logical state on a pin configured as an
- * output.
- *
- * \section asfdoc_sam0_port_basic_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
- * There are no special setup requirements for this use-case.
- *
- * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
- * Copy-paste the following setup code to your user application:
- * \snippet qs_port_basic.c setup
- *
- * Add to user application initialization (typically the start of \c main()):
- * \snippet qs_port_basic.c setup_init
- *
- * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
- * -# Create a PORT module pin configuration struct, which can be filled out to
- *    adjust the configuration of a single port pin.
- *    \snippet qs_port_basic.c setup_1
- * -# Initialize the pin configuration struct with the module's default values.
- *    \snippet qs_port_basic.c setup_2
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Adjust the configuration struct to request an input pin.
- *    \snippet qs_port_basic.c setup_3
- * -# Configure push button pin with the initialized pin configuration struct, to enable
- *    the input sampler on the pin.
- *    \snippet qs_port_basic.c setup_4
- * -# Adjust the configuration struct to request an output pin.
- *    \snippet qs_port_basic.c setup_5
- *    \note The existing configuration struct may be re-used, as long as any
- *          values that have been altered from the default settings are taken
- *          into account by the user application.
- *
- * -# Configure LED pin with the initialized pin configuration struct, to enable
- *    the output driver on the pin.
- *    \snippet qs_port_basic.c setup_6
- *
- * \section asfdoc_sam0_port_basic_use_case_use_main Use Case
- *
- * \subsection asfdoc_sam0_port_basic_use_case_code Code
- * Copy-paste the following code to your user application:
- * \snippet qs_port_basic.c main
- *
- * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
- * -# Read in the current input sampler state of push button pin, which has been
- *    configured as an input in the use-case setup code.
- *    \snippet qs_port_basic.c main_1
- * -# Write the inverted pin level state to LED pin, which has been configured as
- *    an output in the use-case setup code.
- *    \snippet qs_port_basic.c main_2
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
+ *
+ * In this use case, the PORT module is configured for:
+ *  \li One pin in input mode, with pull-up enabled
+ *  \li One pin in output mode
+ *
+ * This use case sets up the PORT to read the current state of a GPIO pin set as
+ * an input, and mirrors the opposite logical state on a pin configured as an
+ * output.
+ *
+ * \section asfdoc_sam0_port_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_port_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_port_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
+ * -# Create a PORT module pin configuration struct, which can be filled out to
+ *    adjust the configuration of a single port pin.
+ *    \snippet qs_port_basic.c setup_1
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_port_basic.c setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin.
+ *    \snippet qs_port_basic.c setup_3
+ * -# Configure push button pin with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_port_basic.c setup_4
+ * -# Adjust the configuration struct to request an output pin.
+ *    \snippet qs_port_basic.c setup_5
+ *    \note The existing configuration struct may be re-used, as long as any
+ *          values that have been altered from the default settings are taken
+ *          into account by the user application.
+ *
+ * -# Configure LED pin with the initialized pin configuration struct, to enable
+ *    the output driver on the pin.
+ *    \snippet qs_port_basic.c setup_6
+ *
+ * \section asfdoc_sam0_port_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_port_basic.c main
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
+ * -# Read in the current input sampler state of push button pin, which has been
+ *    configured as an input in the use-case setup code.
+ *    \snippet qs_port_basic.c main_1
+ * -# Write the inverted pin level state to LED pin, which has been configured as
+ *    an output in the use-case setup code.
+ *    \snippet qs_port_basic.c main_2
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.c
index 4ec5611..0bcaa58 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.c
@@ -1,280 +1,280 @@
-/**
- * \file
- *
- * \brief SAM Serial Peripheral Interface Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include "sercom.h"
-
-#define SHIFT 32
-#define BAUD_INT_MAX   8192
-#define BAUD_FP_MAX     8
-
-#if !defined(__DOXYGEN__)
-/**
- * \internal Configuration structure to save current gclk status.
- */
-struct _sercom_conf {
-	/* Status of gclk generator initialization */
-	bool generator_is_set;
-	/* Sercom gclk generator used */
-	enum gclk_generator generator_source;
-};
-
-static struct _sercom_conf _sercom_config;
-
-
-/**
- * \internal Calculate 64 bit division, ref can be found in
- * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
- */
-static uint64_t long_division(uint64_t n, uint64_t d)
-{
-	int32_t i;
-	uint64_t q = 0, r = 0, bit_shift;
-	for (i = 63; i >= 0; i--) {
-		bit_shift = (uint64_t)1 << i;
-
-		r = r << 1;
-
-		if (n & bit_shift) {
-			r |= 0x01;
-		}
-
-		if (r >= d) {
-			r = r - d;
-			q |= bit_shift;
-		}
-	}
-
-	return q;
-}
-
-/**
- * \internal Calculate synchronous baudrate value (SPI/UART)
- */
-enum status_code _sercom_get_sync_baud_val(
-		const uint32_t baudrate,
-		const uint32_t external_clock,
-		uint16_t *const baudvalue)
-{
-	/* Baud value variable */
-	uint16_t baud_calculated = 0;
-	uint32_t clock_value = external_clock;
-
-
-	/* Check if baudrate is outside of valid range */
-	if (baudrate > (external_clock / 2)) {
-		/* Return with error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	}
-
-	/* Calculate BAUD value from clock frequency and baudrate */
-	clock_value = external_clock / 2;
-	while (clock_value >= baudrate) {
-		clock_value = clock_value - baudrate;
-		baud_calculated++;
-	}
-	baud_calculated = baud_calculated - 1;
-
-	/* Check if BAUD value is more than 255, which is maximum
-	 * for synchronous mode */
-	if (baud_calculated > 0xFF) {
-		/* Return with an error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	} else {
-		*baudvalue = baud_calculated;
-		return STATUS_OK;
-	}
-}
-
-/**
- * \internal Calculate asynchronous baudrate value (UART)
-*/
-enum status_code _sercom_get_async_baud_val(
-		const uint32_t baudrate,
-		const uint32_t peripheral_clock,
-		uint16_t *const baudval,
-		enum sercom_asynchronous_operation_mode mode,
-		enum sercom_asynchronous_sample_num sample_num)
-{
-	/* Temporary variables  */
-	uint64_t ratio = 0;
-	uint64_t scale = 0;
-	uint64_t baud_calculated = 0;
-	uint8_t baud_fp;
-	uint32_t baud_int = 0;
-	uint64_t temp1;
-
-	/* Check if the baudrate is outside of valid range */
-	if ((baudrate * sample_num) > peripheral_clock) {
-		/* Return with error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	}
-
-	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
-		/* Calculate the BAUD value */
-		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
-		ratio = long_division(temp1, peripheral_clock);
-		scale = ((uint64_t)1 << SHIFT) - ratio;
-		baud_calculated = (65536 * scale) >> SHIFT;
-	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
-		temp1 = ((uint64_t)baudrate * sample_num);
-		baud_int = long_division( peripheral_clock, temp1);
-		if(baud_int > BAUD_INT_MAX) {
-				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-		}
-		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
-		baud_fp = temp1 - 8 * baud_int;
-		baud_calculated = baud_int | (baud_fp << 13);
-	}
-
-	*baudval = baud_calculated;
-	return STATUS_OK;
-}
-#endif
-
-/**
- * \brief Set GCLK channel to generator.
- *
- * This will set the appropriate GCLK channel to the requested GCLK generator.
- * This will set the generator for all SERCOM instances, and the user will thus
- * only be able to set the same generator that has previously been set, if any.
- *
- * After the generator has been set the first time, the generator can be changed
- * using the \c force_change flag.
- *
- * \param[in]  generator_source The generator to use for SERCOM.
- * \param[in]  force_change     Force change the generator.
- *
- * \return Status code indicating the GCLK generator change operation.
- * \retval STATUS_OK                       If the generator update request was
- *                                         successful.
- * \retval STATUS_ERR_ALREADY_INITIALIZED  If a generator was already configured
- *                                         and the new configuration was not
- *                                         forced.
- */
-enum status_code sercom_set_gclk_generator(
-		const enum gclk_generator generator_source,
-		const bool force_change)
-{
-	/* Check if valid option */
-	if (!_sercom_config.generator_is_set || force_change) {
-		/* Create and fill a GCLK configuration structure for the new config */
-		struct system_gclk_chan_config gclk_chan_conf;
-		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-		gclk_chan_conf.source_generator = generator_source;
-		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
-		system_gclk_chan_enable(SERCOM_GCLK_ID);
-
-		/* Save config */
-		_sercom_config.generator_source = generator_source;
-		_sercom_config.generator_is_set = true;
-
-		return STATUS_OK;
-	} else if (generator_source == _sercom_config.generator_source) {
-		/* Return status OK if same config */
-		return STATUS_OK;
-	}
-
-	/* Return invalid config to already initialized GCLK */
-	return STATUS_ERR_ALREADY_INITIALIZED;
-}
-
-/** \internal
- * Creates a switch statement case entry to convert a SERCOM instance and pad
- * index to the default SERCOM pad MUX setting.
- */
-#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
-		case (uintptr_t)SERCOM##n: \
-			switch (pad) { \
-				case 0: \
-					return SERCOM##n##_PAD0_DEFAULT; \
-				case 1: \
-					return SERCOM##n##_PAD1_DEFAULT; \
-				case 2: \
-					return SERCOM##n##_PAD2_DEFAULT; \
-				case 3: \
-					return SERCOM##n##_PAD3_DEFAULT; \
-			} \
-			break;
-
-/**
- * \internal Gets the default PAD pinout for a given SERCOM.
- *
- * Returns the pinmux settings for the given SERCOM and pad. This is used
- * for default configuration of pins.
- *
- * \param[in]  sercom_module   Pointer to the SERCOM module
- * \param[in]  pad             PAD to get default pinout for
- *
- * \returns The default pinmux for the given SERCOM instance and PAD
- *
- */
-uint32_t _sercom_get_default_pad(
-		Sercom *const sercom_module,
-		const uint8_t pad)
-{
-	switch ((uintptr_t)sercom_module) {
-		/* Auto-generate a lookup table for the default SERCOM pad defaults */
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-	}
-
-	Assert(false);
-	return 0;
-}
-
-/**
- * \internal
- * Find index of given instance.
- *
- * \param[in] sercom_instance  Instance pointer.
- *
- * \return Index of given instance.
- */
-uint8_t _sercom_get_sercom_inst_index(
-		Sercom *const sercom_instance)
-{
-	/* Save all available SERCOM instances for compare */
-	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
-
-	/* Find index for sercom instance */
-	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given */
-	Assert(false);
-	return 0;
-}
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "sercom.h"
+
+#define SHIFT 32
+#define BAUD_INT_MAX   8192
+#define BAUD_FP_MAX     8
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Configuration structure to save current gclk status.
+ */
+struct _sercom_conf {
+	/* Status of gclk generator initialization */
+	bool generator_is_set;
+	/* Sercom gclk generator used */
+	enum gclk_generator generator_source;
+};
+
+static struct _sercom_conf _sercom_config;
+
+
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+	int32_t i;
+	uint64_t q = 0, r = 0, bit_shift;
+	for (i = 63; i >= 0; i--) {
+		bit_shift = (uint64_t)1 << i;
+
+		r = r << 1;
+
+		if (n & bit_shift) {
+			r |= 0x01;
+		}
+
+		if (r >= d) {
+			r = r - d;
+			q |= bit_shift;
+		}
+	}
+
+	return q;
+}
+
+/**
+ * \internal Calculate synchronous baudrate value (SPI/UART)
+ */
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudvalue)
+{
+	/* Baud value variable */
+	uint16_t baud_calculated = 0;
+	uint32_t clock_value = external_clock;
+
+
+	/* Check if baudrate is outside of valid range */
+	if (baudrate > (external_clock / 2)) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	/* Calculate BAUD value from clock frequency and baudrate */
+	clock_value = external_clock / 2;
+	while (clock_value >= baudrate) {
+		clock_value = clock_value - baudrate;
+		baud_calculated++;
+	}
+	baud_calculated = baud_calculated - 1;
+
+	/* Check if BAUD value is more than 255, which is maximum
+	 * for synchronous mode */
+	if (baud_calculated > 0xFF) {
+		/* Return with an error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	} else {
+		*baudvalue = baud_calculated;
+		return STATUS_OK;
+	}
+}
+
+/**
+ * \internal Calculate asynchronous baudrate value (UART)
+*/
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num)
+{
+	/* Temporary variables  */
+	uint64_t ratio = 0;
+	uint64_t scale = 0;
+	uint64_t baud_calculated = 0;
+	uint8_t baud_fp;
+	uint32_t baud_int = 0;
+	uint64_t temp1;
+
+	/* Check if the baudrate is outside of valid range */
+	if ((baudrate * sample_num) > peripheral_clock) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+		/* Calculate the BAUD value */
+		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+		ratio = long_division(temp1, peripheral_clock);
+		scale = ((uint64_t)1 << SHIFT) - ratio;
+		baud_calculated = (65536 * scale) >> SHIFT;
+	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+		temp1 = ((uint64_t)baudrate * sample_num);
+		baud_int = long_division( peripheral_clock, temp1);
+		if(baud_int > BAUD_INT_MAX) {
+				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+		}
+		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
+		baud_fp = temp1 - 8 * baud_int;
+		baud_calculated = baud_int | (baud_fp << 13);
+	}
+
+	*baudval = baud_calculated;
+	return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Set GCLK channel to generator.
+ *
+ * This will set the appropriate GCLK channel to the requested GCLK generator.
+ * This will set the generator for all SERCOM instances, and the user will thus
+ * only be able to set the same generator that has previously been set, if any.
+ *
+ * After the generator has been set the first time, the generator can be changed
+ * using the \c force_change flag.
+ *
+ * \param[in]  generator_source The generator to use for SERCOM.
+ * \param[in]  force_change     Force change the generator.
+ *
+ * \return Status code indicating the GCLK generator change operation.
+ * \retval STATUS_OK                       If the generator update request was
+ *                                         successful.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If a generator was already configured
+ *                                         and the new configuration was not
+ *                                         forced.
+ */
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change)
+{
+	/* Check if valid option */
+	if (!_sercom_config.generator_is_set || force_change) {
+		/* Create and fill a GCLK configuration structure for the new config */
+		struct system_gclk_chan_config gclk_chan_conf;
+		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+		gclk_chan_conf.source_generator = generator_source;
+		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(SERCOM_GCLK_ID);
+
+		/* Save config */
+		_sercom_config.generator_source = generator_source;
+		_sercom_config.generator_is_set = true;
+
+		return STATUS_OK;
+	} else if (generator_source == _sercom_config.generator_source) {
+		/* Return status OK if same config */
+		return STATUS_OK;
+	}
+
+	/* Return invalid config to already initialized GCLK */
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/** \internal
+ * Creates a switch statement case entry to convert a SERCOM instance and pad
+ * index to the default SERCOM pad MUX setting.
+ */
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
+		case (uintptr_t)SERCOM##n: \
+			switch (pad) { \
+				case 0: \
+					return SERCOM##n##_PAD0_DEFAULT; \
+				case 1: \
+					return SERCOM##n##_PAD1_DEFAULT; \
+				case 2: \
+					return SERCOM##n##_PAD2_DEFAULT; \
+				case 3: \
+					return SERCOM##n##_PAD3_DEFAULT; \
+			} \
+			break;
+
+/**
+ * \internal Gets the default PAD pinout for a given SERCOM.
+ *
+ * Returns the pinmux settings for the given SERCOM and pad. This is used
+ * for default configuration of pins.
+ *
+ * \param[in]  sercom_module   Pointer to the SERCOM module
+ * \param[in]  pad             PAD to get default pinout for
+ *
+ * \returns The default pinmux for the given SERCOM instance and PAD
+ *
+ */
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad)
+{
+	switch ((uintptr_t)sercom_module) {
+		/* Auto-generate a lookup table for the default SERCOM pad defaults */
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \internal
+ * Find index of given instance.
+ *
+ * \param[in] sercom_instance  Instance pointer.
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance)
+{
+	/* Save all available SERCOM instances for compare */
+	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+	/* Find index for sercom instance */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.h
index 58bd15f..7ac1963 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom.h
@@ -1,108 +1,108 @@
-/**
- * \file
- *
- * \brief SAM Serial Peripheral Interface Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef SERCOM_H_INCLUDED
-#define SERCOM_H_INCLUDED
-
-#include <compiler.h>
-#include <system.h>
-#include <clock.h>
-#include <system_interrupt.h>
-#include "sercom_pinout.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* SERCOM modules should share  same slow GCLK channel ID */
-#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
-
-#if (0x1ff >= REV_SERCOM)
-#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
-#elif (0x400 >= REV_SERCOM)
-#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
-#else
-#  error "Unknown SYNCBUSY scheme for this SERCOM revision"
-#endif
-
-/**
- * \brief sercom asynchronous operation mode
- *
- * Select sercom asynchronous operation mode
- */
-enum sercom_asynchronous_operation_mode {
-	SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
-	SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
-};
-
-/**
- * \brief sercom asynchronous samples per bit
- *
- * Select number of samples per bit
- */
-enum sercom_asynchronous_sample_num {
-	SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
-	SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
-	SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
-};
-
-enum status_code sercom_set_gclk_generator(
-		const enum gclk_generator generator_source,
-		const bool force_change);
-
-enum status_code _sercom_get_sync_baud_val(
-		const uint32_t baudrate,
-		const uint32_t external_clock,
-		uint16_t *const baudval);
-
-enum status_code _sercom_get_async_baud_val(
-		const uint32_t baudrate,
-		const uint32_t peripheral_clock,
-		uint16_t *const baudval,
-		enum sercom_asynchronous_operation_mode mode,
-		enum sercom_asynchronous_sample_num sample_num);
-
-uint32_t _sercom_get_default_pad(
-		Sercom *const sercom_module,
-		const uint8_t pad);
-
-uint8_t _sercom_get_sercom_inst_index(
-		Sercom *const sercom_instance);
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SERCOM_H_INCLUDED
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SERCOM_H_INCLUDED
+#define SERCOM_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <clock.h>
+#include <system_interrupt.h>
+#include "sercom_pinout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SERCOM modules should share  same slow GCLK channel ID */
+#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+
+#if (0x1ff >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
+#elif (0x400 >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
+#else
+#  error "Unknown SYNCBUSY scheme for this SERCOM revision"
+#endif
+
+/**
+ * \brief sercom asynchronous operation mode
+ *
+ * Select sercom asynchronous operation mode
+ */
+enum sercom_asynchronous_operation_mode {
+	SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+	SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+};
+
+/**
+ * \brief sercom asynchronous samples per bit
+ *
+ * Select number of samples per bit
+ */
+enum sercom_asynchronous_sample_num {
+	SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+	SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+	SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+};
+
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change);
+
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudval);
+
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num);
+
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad);
+
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SERCOM_H_INCLUDED
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.c
index 8b0032d..1c14ebe 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.c
@@ -1,131 +1,131 @@
-/**
- * \file
- *
- * \brief SAM Serial Peripheral Interface Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include "sercom_interrupt.h"
-
-void *_sercom_instances[SERCOM_INST_NUM];
-
-/** Save status of initialized handlers */
-static bool _handler_table_initialized = false;
-
-/** Void pointers for saving device instance structures */
-static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
-
-/**
- * \internal
- * Default interrupt handler.
- *
- * \param[in] instance SERCOM instance used.
- */
-static void _sercom_default_handler(
-		const uint8_t instance)
-{
-	Assert(false);
-}
-
-/**
- * \internal
- * Saves the given callback handler.
- *
- * \param[in]  instance           Instance index.
- * \param[in]  interrupt_handler  Pointer to instance callback handler.
- */
-void _sercom_set_handler(
-		const uint8_t instance,
-		const sercom_handler_t interrupt_handler)
-{
-	/* Initialize handlers with default handler and device instances with 0 */
-	if (_handler_table_initialized == false) {
-		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
-			_sercom_instances[i] = NULL;
-		}
-
-		_handler_table_initialized = true;
-	}
-
-	/* Save interrupt handler */
-	_sercom_interrupt_handlers[instance] = interrupt_handler;
-}
-
-
-/** \internal
- * Converts a given SERCOM index to its interrupt vector index.
- */
-#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
-		SYSTEM_INTERRUPT_MODULE_SERCOM##n,
-
-/** \internal
- * Generates a SERCOM interrupt handler function for a given SERCOM index.
- */
-#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
-		void SERCOM##n##_Handler(void) \
-		{ \
-			_sercom_interrupt_handlers[n](n); \
-		}
-
-/**
- * \internal
- * Returns the system interrupt vector.
- *
- * \param[in]  sercom_instance  Instance pointer
- *
- * \return Enum of system interrupt vector
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
- * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
- */
-enum system_interrupt_vector _sercom_get_interrupt_vector(
-		Sercom *const sercom_instance)
-{
-	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
-		{
-			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
-		};
-
-	/* Retrieve the index of the SERCOM being requested */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
-
-	/* Get the vector number from the lookup table for the requested SERCOM */
-	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
-}
-
-/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
-MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "sercom_interrupt.h"
+
+void *_sercom_instances[SERCOM_INST_NUM];
+
+/** Save status of initialized handlers */
+static bool _handler_table_initialized = false;
+
+/** Void pointers for saving device instance structures */
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
+
+/**
+ * \internal
+ * Default interrupt handler.
+ *
+ * \param[in] instance SERCOM instance used.
+ */
+static void _sercom_default_handler(
+		const uint8_t instance)
+{
+	Assert(false);
+}
+
+/**
+ * \internal
+ * Saves the given callback handler.
+ *
+ * \param[in]  instance           Instance index.
+ * \param[in]  interrupt_handler  Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler)
+{
+	/* Initialize handlers with default handler and device instances with 0 */
+	if (_handler_table_initialized == false) {
+		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
+			_sercom_instances[i] = NULL;
+		}
+
+		_handler_table_initialized = true;
+	}
+
+	/* Save interrupt handler */
+	_sercom_interrupt_handlers[instance] = interrupt_handler;
+}
+
+
+/** \internal
+ * Converts a given SERCOM index to its interrupt vector index.
+ */
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
+		SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
+		void SERCOM##n##_Handler(void) \
+		{ \
+			_sercom_interrupt_handlers[n](n); \
+		}
+
+/**
+ * \internal
+ * Returns the system interrupt vector.
+ *
+ * \param[in]  sercom_instance  Instance pointer
+ *
+ * \return Enum of system interrupt vector
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance)
+{
+	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+		{
+			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+		};
+
+	/* Retrieve the index of the SERCOM being requested */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+
+	/* Get the vector number from the lookup table for the requested SERCOM */
+	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+}
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.h
index 0c61efe..9bd9c7a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_interrupt.h
@@ -1,62 +1,62 @@
-/**
- * \file
- *
- * \brief SAM Serial Peripheral Interface Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SERCOM_INTERRUPT_H_INCLUDED
-#define SERCOM_INTERRUPT_H_INCLUDED
-
-#include "sercom.h"
-#include <system_interrupt.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Look-up table for device instances */
-extern void *_sercom_instances[SERCOM_INST_NUM];
-
-typedef void (*sercom_handler_t)(uint8_t instance);
-
-enum system_interrupt_vector _sercom_get_interrupt_vector(
-		Sercom *const sercom_instance);
-
-void _sercom_set_handler(
-		const uint8_t instance,
-		const sercom_handler_t interrupt_handler);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SERCOM_INTERRUPT_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SERCOM_INTERRUPT_H_INCLUDED
+#define SERCOM_INTERRUPT_H_INCLUDED
+
+#include "sercom.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Look-up table for device instances */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+typedef void (*sercom_handler_t)(uint8_t instance);
+
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance);
+
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_pinout.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_pinout.h
index e4cc8c6..4ad66f4 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_pinout.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/sercom_pinout.h
@@ -1,612 +1,612 @@
-/**
- * \file
- *
- * \brief SAM SERCOM Module Pinout Definitions
- *
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SERCOM_PINOUT_H_INCLUDED
-#define SERCOM_PINOUT_H_INCLUDED
-
-#include <compiler.h>
-
-#if SAMR21E
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-# if SAM_PART_IS_DEFINED(SAMR21E19A)
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-# else
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
-#endif
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
-
-	/* SERCOM4 */
-# if SAM_PART_IS_DEFINED(SAMR21E19A)
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-# else
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
-# endif
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
-
-#elif SAMR21G
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
-
-#elif (SAMD09)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
-
-#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) 
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
-
-#elif (SAMD10C) || (SAMD11C)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
-
-#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
-
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
-
-#elif (SAML22N)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
-
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
-#elif (SAML22J) || (SAML22G)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA12D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA13D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA14D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA15D_SERCOM3_PAD3
-#elif (SAMC20E) || (SAMC21E)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
-
-#elif (SAMC20G) || (SAMC21G)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
-
-  #ifdef ID_SERCOM4
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
-  #endif
-
-  #ifdef ID_SERCOM5
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
-  #endif
-
-#elif (SAMC20J) || (SAMC21J)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
-
-  #ifdef ID_SERCOM4
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
-  #endif
-
-  #ifdef ID_SERCOM5
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
-  #endif
-
-#elif (SAMDA1)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-  #if (SAMDA1E)
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-  #else
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-  #endif
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
-
-#elif   (SAMHA1E) || (SAMHA0E)
-	
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM5_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      0 /* No available pin */
-	
-#elif   (SAMHA1G) || (SAMHA0G)
-	
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
-   
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-    
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-    
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-    
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB16C_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB17C_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA21C_SERCOM5_PAD3
-
-#elif (SAML21E) || (SAMR34) || (SAMR35) 
-
-	/* SERCOM0 */
- 	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
- 	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-  #if !SAM_PART_IS_DEFINED(SAML21E18A) 
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-	
-    /* SERCOM5 */
-    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
-  #endif
-  
-#elif  (SAMR30E)
-
-   /* SERCOM0 */
-   #define SERCOM0_PAD0_DEFAULT      0 /* No available pin */
-   #define SERCOM0_PAD1_DEFAULT      0 /* No available pin */
-   #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-   #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-   /* SERCOM1 */
-   #define SERCOM1_PAD0_DEFAULT      0 /* No available pin */
-   #define SERCOM1_PAD1_DEFAULT      0 /* No available pin */
-   #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-   #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-   /* SERCOM2 */
-   #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-   #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-   #define SERCOM2_PAD2_DEFAULT      0 /* No available pin */
-   #define SERCOM2_PAD3_DEFAULT      0 /* No available pin */
-
-   /* SERCOM3 */
-   #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-   #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-   #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-   #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-  /* SERCOM4 */
-  #define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-  #define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-  #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-  #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-
-  /* SERCOM5 */
-  #define SERCOM5_PAD0_DEFAULT      0
-  #define SERCOM5_PAD1_DEFAULT      0
-  #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-  #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
-
-#else
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-#else
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-#endif
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-  #if !(SAMD20E || SAMD21E)
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
-  #endif
-  
-#endif
-#endif /* SERCOM_PINOUT_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM SERCOM Module Pinout Definitions
+ *
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SERCOM_PINOUT_H_INCLUDED
+#define SERCOM_PINOUT_H_INCLUDED
+
+#include <compiler.h>
+
+#if SAMR21E
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+# else
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
+#endif
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+# else
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+# endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif SAMR21G
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif (SAMD09)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) 
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
+
+#elif (SAMD10C) || (SAMD11C)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
+
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAML22N)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+#elif (SAML22J) || (SAML22G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA12D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA13D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA14D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA15D_SERCOM3_PAD3
+#elif (SAMC20E) || (SAMC21E)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAMC20G) || (SAMC21G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMC20J) || (SAMC21J)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMDA1)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if (SAMDA1E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #else
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif   (SAMHA1E) || (SAMHA0E)
+	
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM5_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      0 /* No available pin */
+	
+#elif   (SAMHA1G) || (SAMHA0G)
+	
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+   
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+    
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+    
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+    
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB16C_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB17C_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA21C_SERCOM5_PAD3
+
+#elif (SAML21E) || (SAMR34) || (SAMR35) 
+
+	/* SERCOM0 */
+ 	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+ 	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !SAM_PART_IS_DEFINED(SAML21E18A) 
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+	
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+  
+#elif  (SAMR30E)
+
+   /* SERCOM0 */
+   #define SERCOM0_PAD0_DEFAULT      0 /* No available pin */
+   #define SERCOM0_PAD1_DEFAULT      0 /* No available pin */
+   #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+   #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+   /* SERCOM1 */
+   #define SERCOM1_PAD0_DEFAULT      0 /* No available pin */
+   #define SERCOM1_PAD1_DEFAULT      0 /* No available pin */
+   #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+   #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+   /* SERCOM2 */
+   #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+   #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+   #define SERCOM2_PAD2_DEFAULT      0 /* No available pin */
+   #define SERCOM2_PAD3_DEFAULT      0 /* No available pin */
+
+   /* SERCOM3 */
+   #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+   #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+   #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+   #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  /* SERCOM4 */
+  #define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+  #define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+  #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+  #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+  /* SERCOM5 */
+  #define SERCOM5_PAD0_DEFAULT      0
+  #define SERCOM5_PAD1_DEFAULT      0
+  #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+  #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#else
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+#else
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+#endif
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !(SAMD20E || SAMD21E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+  
+#endif
+#endif /* SERCOM_PINOUT_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h
index a01f06c..834a213 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h
@@ -1,106 +1,106 @@
-/**
- * \file
- *
- * \brief SAM USART Quick Start
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-/**
- * \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
- *
- * This quick start will echo back characters typed into the terminal. In this
- * use case the USART will be configured with the following settings:
- * - Asynchronous mode
- * - 9600 Baudrate
- * - 8-bits, No Parity and one Stop Bit
- * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
- *
- * \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
- * There are no special setup requirements for this use-case.
- *
- * \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
- * Add to the main application source file, outside of any functions:
- * \snippet qs_usart_basic_use.c module_inst
- *
- * Copy-paste the following setup code to your user application:
- * \snippet qs_usart_basic_use.c setup
- *
- * Add to user application initialization (typically the start of \c main()):
- * \snippet qs_usart_basic_use.c setup_init
- *
- * \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
- * -# Create a module software instance structure for the USART module to store
- *    the USART driver state while it is in use.
- *    \snippet qs_usart_basic_use.c module_inst
- *    \note This should never go out of scope as long as the module is in use.
- *          In most cases, this should be global.
- *
- * -# Configure the USART module.
- *  -# Create a USART module configuration struct, which can be filled out to
- *     adjust the configuration of a physical USART peripheral.
- *     \snippet qs_usart_basic_use.c setup_config
- *  -# Initialize the USART configuration struct with the module's default values.
- *     \snippet qs_usart_basic_use.c setup_config_defaults
- *     \note This should always be performed before using the configuration
- *           struct to ensure that all values are initialized to known default
- *           settings.
- *
- *  -# Alter the USART settings to configure the physical pinout, baudrate, and
- *     other relevant parameters.
- *     \snippet qs_usart_basic_use.c setup_change_config
- *  -# Configure the USART module with the desired settings, retrying while the
- *     driver is busy until the configuration is stressfully set.
- *     \snippet qs_usart_basic_use.c setup_set_config
- *  -# Enable the USART module.
- *     \snippet qs_usart_basic_use.c setup_enable
- *
- *
- * \section asfdoc_sam0_usart_basic_use_case_main Use Case
- *
- * \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
- * Copy-paste the following code to your user application:
- * \snippet qs_usart_basic_use.c main
- *
- * \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
- * -# Send a string to the USART to show the demo is running, blocking until
- *    all characters have been sent.
- *    \snippet qs_usart_basic_use.c main_send_string
- * -# Enter an infinite loop to continuously echo received values on the USART.
- *    \snippet qs_usart_basic_use.c main_loop
- * -# Perform a blocking read of the USART, storing the received character into
- *    the previously declared temporary variable.
- *    \snippet qs_usart_basic_use.c main_read
- * -# Echo the received variable back to the USART via a blocking write.
- *    \snippet qs_usart_basic_use.c main_write
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
+ *
+ * This quick start will echo back characters typed into the terminal. In this
+ * use case the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_basic_use.c module_inst
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_basic_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_basic_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_basic_use.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ *  -# Create a USART module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical USART peripheral.
+ *     \snippet qs_usart_basic_use.c setup_config
+ *  -# Initialize the USART configuration struct with the module's default values.
+ *     \snippet qs_usart_basic_use.c setup_config_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ *  -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_usart_basic_use.c setup_change_config
+ *  -# Configure the USART module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_usart_basic_use.c setup_set_config
+ *  -# Enable the USART module.
+ *     \snippet qs_usart_basic_use.c setup_enable
+ *
+ *
+ * \section asfdoc_sam0_usart_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_basic_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
+ * -# Send a string to the USART to show the demo is running, blocking until
+ *    all characters have been sent.
+ *    \snippet qs_usart_basic_use.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ *    \snippet qs_usart_basic_use.c main_loop
+ * -# Perform a blocking read of the USART, storing the received character into
+ *    the previously declared temporary variable.
+ *    \snippet qs_usart_basic_use.c main_read
+ * -# Echo the received variable back to the USART via a blocking write.
+ *    \snippet qs_usart_basic_use.c main_write
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_callback/qs_usart_callback.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_callback/qs_usart_callback.h
index b399fed..9cb8dca 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_callback/qs_usart_callback.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_callback/qs_usart_callback.h
@@ -1,120 +1,120 @@
-/**
- * \file
- *
- * \brief SAM USART Quick Start
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-/**
- * \page asfdoc_sam0_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback
- *
- * This quick start will echo back characters typed into the terminal, using
- * asynchronous TX and RX callbacks from the USART peripheral. In this use case
- * the USART will be configured with the following settings:
- * - Asynchronous mode
- * - 9600 Baudrate
- * - 8-bits, No Parity and one Stop Bit
- * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
- *
- * \section asfdoc_sam0_sercom_usart_callback_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_sercom_usart_callback_use_case_prereq Prerequisites
- * There are no special setup requirements for this use-case.
- *
- * \subsection asfdoc_sam0_usart_callback_use_case_setup_code Code
- * Add to the main application source file, outside of any functions:
- * \snippet qs_usart_callback.c module_inst
- * \snippet qs_usart_callback.c rx_buffer_var
- *
- * Copy-paste the following callback function code to your user application:
- * \snippet qs_usart_callback.c callback_funcs
- *
- * Copy-paste the following setup code to your user application:
- * \snippet qs_usart_callback.c setup
- *
- * Add to user application initialization (typically the start of \c main()):
- * \snippet qs_usart_callback.c setup_init
- *
- * \subsection asfdoc_sam0_usart_callback_use_case_setup_flow Workflow
- * -# Create a module software instance structure for the USART module to store
- *    the USART driver state while it is in use.
- *    \snippet qs_usart_callback.c module_inst
- *    \note This should never go out of scope as long as the module is in use.
- *          In most cases, this should be global.
- *
- * -# Configure the USART module.
- *  -# Create a USART module configuration struct, which can be filled out to
- *     adjust the configuration of a physical USART peripheral.
- *     \snippet qs_usart_callback.c setup_config
- *  -# Initialize the USART configuration struct with the module's default values.
- *     \snippet qs_usart_callback.c setup_config_defaults
- *     \note This should always be performed before using the configuration
- *           struct to ensure that all values are initialized to known default
- *           settings.
- *
- *  -# Alter the USART settings to configure the physical pinout, baudrate, and
- *     other relevant parameters.
- *     \snippet qs_usart_callback.c setup_change_config
- *  -# Configure the USART module with the desired settings, retrying while the
- *     driver is busy until the configuration is stressfully set.
- *     \snippet qs_usart_callback.c setup_set_config
- *  -# Enable the USART module.
- *     \snippet qs_usart_callback.c setup_enable
- * -# Configure the USART callbacks.
- *  -# Register the TX and RX callback functions with the driver.
- *     \snippet qs_usart_callback.c setup_register_callbacks
- *  -# Enable the TX and RX callbacks so that they will be called by the driver
- *     when appropriate.
- *     \snippet qs_usart_callback.c setup_enable_callbacks
- *
- * \section asfdoc_sam0_usart_callback_use_case_main Use Case
- *
- * \subsection asfdoc_sam0_usart_callback_use_case_main_code Code
- * Copy-paste the following code to your user application:
- * \snippet qs_usart_callback.c main
- *
- * \subsection asfdoc_sam0_usart_callback_use_case_main_flow Workflow
- * -# Enable global interrupts, so that the callbacks can be fired.
- *    \snippet qs_usart_callback.c enable_global_interrupts
- * -# Send a string to the USART to show the demo is running, blocking until
- *    all characters have been sent.
- *    \snippet qs_usart_callback.c main_send_string
- * -# Enter an infinite loop to continuously echo received values on the USART.
- *    \snippet qs_usart_callback.c main_loop
- * -# Perform an asynchronous read of the USART, which will fire the registered
- *    callback when characters are received.
- *    \snippet qs_usart_callback.c main_read
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include <asf.h>
-#include <conf_clocks.h>
-
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback
+ *
+ * This quick start will echo back characters typed into the terminal, using
+ * asynchronous TX and RX callbacks from the USART peripheral. In this use case
+ * the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_callback_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_callback_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_callback.c module_inst
+ * \snippet qs_usart_callback.c rx_buffer_var
+ *
+ * Copy-paste the following callback function code to your user application:
+ * \snippet qs_usart_callback.c callback_funcs
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_callback.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_callback.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_callback.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ *  -# Create a USART module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical USART peripheral.
+ *     \snippet qs_usart_callback.c setup_config
+ *  -# Initialize the USART configuration struct with the module's default values.
+ *     \snippet qs_usart_callback.c setup_config_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ *  -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_usart_callback.c setup_change_config
+ *  -# Configure the USART module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_usart_callback.c setup_set_config
+ *  -# Enable the USART module.
+ *     \snippet qs_usart_callback.c setup_enable
+ * -# Configure the USART callbacks.
+ *  -# Register the TX and RX callback functions with the driver.
+ *     \snippet qs_usart_callback.c setup_register_callbacks
+ *  -# Enable the TX and RX callbacks so that they will be called by the driver
+ *     when appropriate.
+ *     \snippet qs_usart_callback.c setup_enable_callbacks
+ *
+ * \section asfdoc_sam0_usart_callback_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_callback.c main
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_main_flow Workflow
+ * -# Enable global interrupts, so that the callbacks can be fired.
+ *    \snippet qs_usart_callback.c enable_global_interrupts
+ * -# Send a string to the USART to show the demo is running, blocking until
+ *    all characters have been sent.
+ *    \snippet qs_usart_callback.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ *    \snippet qs_usart_callback.c main_loop
+ * -# Perform an asynchronous read of the USART, which will fire the registered
+ *    callback when characters are received.
+ *    \snippet qs_usart_callback.c main_read
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <asf.h>
+#include <conf_clocks.h>
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h
index 862fcfe..f2f56fc 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h
@@ -1,208 +1,208 @@
-/**
- * \file
- *
- * \brief SAM Quick Start Guide for Using Usart driver with DMA
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-/**
- * \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
- *
- * The supported board list:
- *    - SAM D21 Xplained Pro
- *    - SAM R21 Xplained Pro
- *    - SAM D11 Xplained Pro
- *    - SAM DA1 Xplained Pro
- *    - SAM HA1G16A Xplained Pro
- *    - SAM L21 Xplained Pro
- *    - SAM L22 Xplained Pro
- *    - SAM C21 Xplained Pro
- *
- * This quick start will receive eight bytes of data from the PC terminal and transmit back the string
- * to the terminal through DMA. In this use case the USART will be configured with the following
- * settings:
- * - Asynchronous mode
- * - 9600 Baudrate
- * - 8-bits, No Parity and one Stop Bit
- * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
- *
- * \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
- * There are no special setup requirements for this use-case.
- *
- * \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
- * Add to the main application source file, outside of any functions:
- * \snippet qs_usart_dma_use.c module_inst
- * \snippet qs_usart_dma_use.c dma_resource
- * \snippet qs_usart_dma_use.c usart_buffer
- * \snippet qs_usart_dma_use.c transfer_descriptor
- *
- * Copy-paste the following setup code to your user application:
- * \snippet qs_usart_dma_use.c setup
- *
- * Add to user application initialization (typically the start of \c main()):
- * \snippet qs_usart_dma_use.c setup_init
- *
- * \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
- *
- * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
- * -# Create a module software instance structure for the USART module to store
- *    the USART driver state while it is in use.
- *    \snippet qs_usart_dma_use.c module_inst
- *    \note This should never go out of scope as long as the module is in use.
- *          In most cases, this should be global.
- *
- * -# Create module software instance structures for DMA resources to store
- *    the DMA resource state while it is in use.
- *    \snippet qs_usart_dma_use.c dma_resource
- *    \note This should never go out of scope as long as the module is in use.
- *          In most cases, this should be global.
- *
- * -# Create a buffer to store the data to be transferred /received.
- *    \snippet qs_usart_dma_use.c usart_buffer
- * -# Create DMA transfer descriptors for RX/TX.
- *    \snippet qs_usart_dma_use.c transfer_descriptor
- *
- * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
- * -# Create a USART module configuration struct, which can be filled out to
- *    adjust the configuration of a physical USART peripheral.
- *    \snippet qs_usart_dma_use.c setup_config
- * -# Initialize the USART configuration struct with the module's default values.
- *    \snippet qs_usart_dma_use.c setup_config_defaults
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Alter the USART settings to configure the physical pinout, baudrate, and
- *    other relevant parameters.
- *    \snippet qs_usart_dma_use.c setup_change_config
- * -# Configure the USART module with the desired settings, retrying while the
- *    driver is busy until the configuration is stressfully set.
- *    \snippet qs_usart_dma_use.c setup_set_config
- * -# Enable the USART module.
- *    \snippet qs_usart_dma_use.c setup_enable
- *
- * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
- * -# Create a callback function of receiver done.
- *    \snippet qs_usart_dma_use.c transfer_done_rx
- *
- * -# Create a callback function of transmission done.
- *    \snippet qs_usart_dma_use.c transfer_done_tx
- *
- * -# Create a DMA resource configuration structure, which can be filled out to
- *    adjust the configuration of a single DMA transfer.
- *    \snippet qs_usart_dma_use.c setup_rx_1
- *
- * -# Initialize the DMA resource configuration struct with the module's
- *    default values.
- *    \snippet qs_usart_dma_use.c setup_rx_2
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Set extra configurations for the DMA resource. It is using peripheral
- *    trigger. SERCOM TX empty trigger causes a beat transfer in
- *    this example.
- *    \snippet qs_usart_dma_use.c setup_rx_3
- *
- * -# Allocate a DMA resource with the configurations.
- *    \snippet qs_usart_dma_use.c setup_rx_4
- *
- * -# Create a DMA transfer descriptor configuration structure, which can be
- *    filled out to adjust the configuration of a single DMA transfer.
- *    \snippet qs_usart_dma_use.c setup_rx_5
- *
- * -# Initialize the DMA transfer descriptor configuration struct with the module's
- *    default values.
- *    \snippet qs_usart_dma_use.c setup_rx_6
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Set the specific parameters for a DMA transfer with transfer size, source
- *    address, and destination address.
- *    \snippet qs_usart_dma_use.c setup_rx_7
- *
- * -# Create the DMA transfer descriptor.
- *    \snippet qs_usart_dma_use.c setup_rx_8
- *
- * -# Create a DMA resource configuration structure for TX, which can be filled
- *    out to adjust the configuration of a single DMA transfer.
- *    \snippet qs_usart_dma_use.c setup_tx_1
- *
- * -# Initialize the DMA resource configuration struct with the module's
- *    default values.
- *    \snippet qs_usart_dma_use.c setup_tx_2
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Set extra configurations for the DMA resource. It is using peripheral
- *    trigger. SERCOM RX Ready trigger causes a beat transfer in
- *    this example.
- *    \snippet qs_usart_dma_use.c setup_tx_3
- *
- * -# Allocate a DMA resource with the configurations.
- *    \snippet qs_usart_dma_use.c setup_tx_4
- *
- * -# Create a DMA transfer descriptor configuration structure, which can be
- *    filled out to adjust the configuration of a single DMA transfer.
- *    \snippet qs_usart_dma_use.c setup_tx_5
- *
- * -# Initialize the DMA transfer descriptor configuration struct with the module's
- *    default values.
- *    \snippet qs_usart_dma_use.c setup_tx_6
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Set the specific parameters for a DMA transfer with transfer size, source
- *    address, and destination address.
- *    \snippet qs_usart_dma_use.c setup_tx_7
- *
- * -# Create the DMA transfer descriptor.
- *    \snippet qs_usart_dma_use.c setup_tx_8
- *
- * \section asfdoc_sam0_usart_dma_use_case_main Use Case
- *
- * \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
- * Copy-paste the following code to your user application:
- * \snippet qs_usart_dma_use.c main
- *
- * \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
- * -# Wait for receiving data.
- *    \snippet qs_usart_dma_use.c main_1
- *
- * -# Enter endless loop.
- *    \snippet qs_usart_dma_use.c endless_loop
- */
+/**
+ * \file
+ *
+ * \brief SAM Quick Start Guide for Using Usart driver with DMA
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
+ *
+ * The supported board list:
+ *    - SAM D21 Xplained Pro
+ *    - SAM R21 Xplained Pro
+ *    - SAM D11 Xplained Pro
+ *    - SAM DA1 Xplained Pro
+ *    - SAM HA1G16A Xplained Pro
+ *    - SAM L21 Xplained Pro
+ *    - SAM L22 Xplained Pro
+ *    - SAM C21 Xplained Pro
+ *
+ * This quick start will receive eight bytes of data from the PC terminal and transmit back the string
+ * to the terminal through DMA. In this use case the USART will be configured with the following
+ * settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_dma_use.c module_inst
+ * \snippet qs_usart_dma_use.c dma_resource
+ * \snippet qs_usart_dma_use.c usart_buffer
+ * \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_dma_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_dma_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_dma_use.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create module software instance structures for DMA resources to store
+ *    the DMA resource state while it is in use.
+ *    \snippet qs_usart_dma_use.c dma_resource
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create a buffer to store the data to be transferred /received.
+ *    \snippet qs_usart_dma_use.c usart_buffer
+ * -# Create DMA transfer descriptors for RX/TX.
+ *    \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
+ * -# Create a USART module configuration struct, which can be filled out to
+ *    adjust the configuration of a physical USART peripheral.
+ *    \snippet qs_usart_dma_use.c setup_config
+ * -# Initialize the USART configuration struct with the module's default values.
+ *    \snippet qs_usart_dma_use.c setup_config_defaults
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *    other relevant parameters.
+ *    \snippet qs_usart_dma_use.c setup_change_config
+ * -# Configure the USART module with the desired settings, retrying while the
+ *    driver is busy until the configuration is stressfully set.
+ *    \snippet qs_usart_dma_use.c setup_set_config
+ * -# Enable the USART module.
+ *    \snippet qs_usart_dma_use.c setup_enable
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
+ * -# Create a callback function of receiver done.
+ *    \snippet qs_usart_dma_use.c transfer_done_rx
+ *
+ * -# Create a callback function of transmission done.
+ *    \snippet qs_usart_dma_use.c transfer_done_tx
+ *
+ * -# Create a DMA resource configuration structure, which can be filled out to
+ *    adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_rx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_rx_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM TX empty trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_usart_dma_use.c setup_rx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_usart_dma_use.c setup_rx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_rx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_rx_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_usart_dma_use.c setup_rx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_usart_dma_use.c setup_rx_8
+ *
+ * -# Create a DMA resource configuration structure for TX, which can be filled
+ *    out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_tx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_tx_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM RX Ready trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_usart_dma_use.c setup_tx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_usart_dma_use.c setup_tx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_tx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_tx_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_usart_dma_use.c setup_tx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_usart_dma_use.c setup_tx_8
+ *
+ * \section asfdoc_sam0_usart_dma_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_dma_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
+ * -# Wait for receiving data.
+ *    \snippet qs_usart_dma_use.c main_1
+ *
+ * -# Enter endless loop.
+ *    \snippet qs_usart_dma_use.c endless_loop
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_lin/qs_lin.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_lin/qs_lin.h
index 79c8162..0a59d06 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_lin/qs_lin.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/quick_start_lin/qs_lin.h
@@ -1,94 +1,94 @@
-/**
- * \file
- *
- * \brief SAM USART LIN Quick Start
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-/**
- * \page asfdoc_sam0_sercom_usart_lin_use_case Quick Start Guide for SERCOM USART LIN
- *
- * The supported board list:
- *    - SAMC21 Xplained Pro
- *
- * This quick start will set up LIN frame format transmission according to your
- * configuration \c CONF_LIN_NODE_TYPE.
- * For LIN master, it will send LIN command after startup.
- * For LIN salve, once received a format from LIN master with ID \c LIN_ID_FIELD_VALUE,
- * it will reply four data bytes plus a checksum.
- *
- * \section asfdoc_sam0_sercom_usart_lin_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_sercom_usart_lin_use_case_prereq Prerequisites
- * When verify data transmission between LIN master and slave, two boards are needed:
- * one is for LIN master and the other is for LIN slave.
- * connect LIN master LIN PIN with LIN slave LIN PIN.
- *
- * \subsection asfdoc_sam0_usart_lin_use_case_setup_code Code
- * Add to the main application source file, outside of any functions:
- * \snippet qs_lin.c module_var
- *
- * Copy-paste the following setup code to your user application:
- * \snippet qs_lin.c setup
- *
- * Add to user application initialization (typically the start of \c main()):
- * \snippet qs_lin.c setup_init
- *
- * \subsection asfdoc_sam0_usart_lin_use_case_setup_flow Workflow
- * -# Create USART CDC and LIN module software instance structure for the USART module to store
- *    the USART driver state while it is in use.
- *    \snippet qs_lin.c module_inst
- * -# Define LIN ID field for header format.
- *    \snippet qs_lin.c lin_id
- *    \note The ID \c LIN_ID_FIELD_VALUE is eight bits as [P1,P0,ID5...ID0], when it's 0x64, the
- * 		data field length is four bytes plus a checksum byte.
- *
- * -# Define LIN RX/TX buffer.
- *    \snippet qs_lin.c lin_buffer
- *    \note For \c tx_buffer and \c rx_buffer, the last byte is for checksum.
- *
- * -# Configure the USART CDC for output message.
- *     \snippet qs_lin.c CDC_setup
- *
- * -# Configure the USART LIN module.
- *     \snippet qs_lin.c lin_setup
- *    \note The LIN frame format can be configured as master or slave, refer to \c CONF_LIN_NODE_TYPE .
- *
- * \section asfdoc_sam0_usart_lin_use_case_main Use Case
- *
- * \subsection asfdoc_sam0_usart_lin_use_case_main_code Code
- * Copy-paste the following code to your user application:
- * \snippet qs_lin.c main_setup
- *
- * \subsection asfdoc_sam0_usart_lin_use_case_main_flow Workflow
- * -# Set up USART LIN module.
- *     \snippet qs_lin.c configure_lin
- * -# For LIN master, sending LIN command. For LIN slaver, start reading data .
- *     \snippet qs_lin.c lin_master_cmd
- */
+/**
+ * \file
+ *
+ * \brief SAM USART LIN Quick Start
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_lin_use_case Quick Start Guide for SERCOM USART LIN
+ *
+ * The supported board list:
+ *    - SAMC21 Xplained Pro
+ *
+ * This quick start will set up LIN frame format transmission according to your
+ * configuration \c CONF_LIN_NODE_TYPE.
+ * For LIN master, it will send LIN command after startup.
+ * For LIN salve, once received a format from LIN master with ID \c LIN_ID_FIELD_VALUE,
+ * it will reply four data bytes plus a checksum.
+ *
+ * \section asfdoc_sam0_sercom_usart_lin_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_lin_use_case_prereq Prerequisites
+ * When verify data transmission between LIN master and slave, two boards are needed:
+ * one is for LIN master and the other is for LIN slave.
+ * connect LIN master LIN PIN with LIN slave LIN PIN.
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_lin.c module_var
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_lin.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_lin.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_setup_flow Workflow
+ * -# Create USART CDC and LIN module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_lin.c module_inst
+ * -# Define LIN ID field for header format.
+ *    \snippet qs_lin.c lin_id
+ *    \note The ID \c LIN_ID_FIELD_VALUE is eight bits as [P1,P0,ID5...ID0], when it's 0x64, the
+ * 		data field length is four bytes plus a checksum byte.
+ *
+ * -# Define LIN RX/TX buffer.
+ *    \snippet qs_lin.c lin_buffer
+ *    \note For \c tx_buffer and \c rx_buffer, the last byte is for checksum.
+ *
+ * -# Configure the USART CDC for output message.
+ *     \snippet qs_lin.c CDC_setup
+ *
+ * -# Configure the USART LIN module.
+ *     \snippet qs_lin.c lin_setup
+ *    \note The LIN frame format can be configured as master or slave, refer to \c CONF_LIN_NODE_TYPE .
+ *
+ * \section asfdoc_sam0_usart_lin_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_lin.c main_setup
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_main_flow Workflow
+ * -# Set up USART LIN module.
+ *     \snippet qs_lin.c configure_lin
+ * -# For LIN master, sending LIN command. For LIN slaver, start reading data .
+ *     \snippet qs_lin.c lin_master_cmd
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.c
index f2faa8d..4f451e8 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.c
@@ -1,806 +1,806 @@
-/**
- * \file
- *
- * \brief SAM SERCOM USART Driver
- *
- * Copyright (c) 2012-2019 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include "usart.h"
-#include <pinmux.h>
-#if USART_CALLBACK_MODE == true
-#  include "usart_interrupt.h"
-#endif
-
-/**
- * \internal
- * Set Configuration of the USART module
- */
-static enum status_code _usart_set_config(
-		struct usart_module *const module,
-		const struct usart_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Index for generic clock */
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t gclk_index;
-
-#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (SAMC21)
-	if (sercom_index == 5) {
-		gclk_index   = SERCOM5_GCLK_ID_CORE;
-	} else {
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
-#else
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-#endif
-
-	/* Cache new register values to minimize the number of register writes */
-	uint32_t ctrla = 0;
-	uint32_t ctrlb = 0;
-#ifdef FEATURE_USART_ISO7816
-	uint32_t ctrlc = 0;
-#endif
-	uint16_t baud  = 0;
-	uint32_t transfer_mode;
-
-	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-
-#ifdef FEATURE_USART_OVER_SAMPLE
-	switch (config->sample_rate) {
-		case USART_SAMPLE_RATE_16X_ARITHMETIC:
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-			break;
-		case USART_SAMPLE_RATE_8X_ARITHMETIC:
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
-			break;
-		case USART_SAMPLE_RATE_3X_ARITHMETIC:
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
-			break;
-		case USART_SAMPLE_RATE_16X_FRACTIONAL:
-			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-			break;
-		case USART_SAMPLE_RATE_8X_FRACTIONAL:
-			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
-			break;
-	}
-#endif
-
-	/* Set data order, internal muxing, and clock polarity */
-	ctrla = (uint32_t)config->data_order |
-		(uint32_t)config->mux_setting |
-	#ifdef FEATURE_USART_OVER_SAMPLE
-		config->sample_adjustment |
-		config->sample_rate |
-	#endif
-	#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
-	#endif
-		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
-
-	enum status_code status_code = STATUS_OK;
-
-	transfer_mode = (uint32_t)config->transfer_mode;
-#ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		transfer_mode = config->iso7816_config.protocol_t;
-	}
-#endif
-	/* Get baud value from mode and clock */
-#ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		baud = config->baudrate;
-	} else {
-#endif
-	switch (transfer_mode)
-	{
-		case USART_TRANSFER_SYNCHRONOUSLY:
-			if (!config->use_external_clock) {
-				status_code = _sercom_get_sync_baud_val(config->baudrate,
-						system_gclk_chan_get_hz(gclk_index), &baud);
-			}
-
-			break;
-
-		case USART_TRANSFER_ASYNCHRONOUSLY:
-			if (config->use_external_clock) {
-				status_code =
-						_sercom_get_async_baud_val(config->baudrate,
-							config->ext_clock_freq, &baud, mode, sample_num);
-			} else {
-				status_code =
-						_sercom_get_async_baud_val(config->baudrate,
-							system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
-			}
-
-			break;
-	}
-
-	/* Check if calculating the baudrate failed */
-	if (status_code != STATUS_OK) {
-		/* Abort */
-		return status_code;
-	}
-#ifdef FEATURE_USART_ISO7816
-	}
-#endif
-
-#ifdef FEATURE_USART_IRDA
-	if(config->encoding_format_enable) {
-		usart_hw->RXPL.reg = config->receive_pulse_length;
-	}
-#endif
-
-	/*Set baud val */
-	usart_hw->BAUD.reg = baud;
-
-	/* Set sample mode */
-	ctrla |= transfer_mode;
-
-	if (config->use_external_clock == false) {
-		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
-	}
-	else {
-		ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
-	}
-
-	/* Set stopbits and enable transceivers */
-	ctrlb =  
-		#ifdef FEATURE_USART_IRDA
-			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
-		#endif
-		#ifdef FEATURE_USART_START_FRAME_DECTION
-			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
-		#endif
-		#ifdef FEATURE_USART_COLLISION_DECTION
-			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
-		#endif
-			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
-			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
-
-#ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
-		if (config->iso7816_config.enable_inverse) {
-			ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
-		}
-		ctrlb |=  USART_CHARACTER_SIZE_8BIT;
-		
-		switch(config->iso7816_config.protocol_t) {
-			case ISO7816_PROTOCOL_T_0:
-				ctrlb |= (uint32_t)config->stopbits;	
-				ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
-						(config->iso7816_config.inhibit_nack) | \
-						(config->iso7816_config.successive_recv_nack) | \
-						SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
-				break;	
-			case ISO7816_PROTOCOL_T_1:
-				ctrlb |= USART_STOPBITS_1;
-				break;		
-		}
-	} else {
-#endif
-	ctrlb |= (uint32_t)config->stopbits;
-	ctrlb |= (uint32_t)config->character_size;
-	/* Check parity mode bits */
-	if (config->parity != USART_PARITY_NONE) {
-		ctrla |= SERCOM_USART_CTRLA_FORM(1);
-		ctrlb |= config->parity;
-	} else {
-#ifdef FEATURE_USART_LIN_SLAVE
-		if(config->lin_slave_enable) {
-			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
-		} else {
-			ctrla |= SERCOM_USART_CTRLA_FORM(0);
-		}
-#else
-		ctrla |= SERCOM_USART_CTRLA_FORM(0);
-#endif
-	}
-#ifdef FEATURE_USART_ISO7816
-	}
-#endif
-
-#ifdef FEATURE_USART_LIN_MASTER
-	usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
-						| config->lin_header_delay
-						| config->lin_break_length;
-
-	if (config->lin_node != LIN_INVALID_MODE) {
-		ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
-		ctrla |= config->lin_node;
-	}
-#endif
-
-	/* Set whether module should run in standby. */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
-	}
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Write configuration to CTRLB */
-	usart_hw->CTRLB.reg = ctrlb;
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Write configuration to CTRLA */
-	usart_hw->CTRLA.reg = ctrla;
-
-#ifdef FEATURE_USART_RS485
-	if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
-		SERCOM_USART_CTRLA_FORM(0x07)) {
-		usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
-		usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
-	}
-#endif
-
-#ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		_usart_wait_for_sync(module);
-		usart_hw->CTRLC.reg = ctrlc;
-	}
-#endif
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Initializes the device
- *
- * Initializes the USART device based on the setting specified in the
- * configuration struct.
- *
- * \param[out] module  Pointer to USART device
- * \param[in]  hw      Pointer to USART hardware instance
- * \param[in]  config  Pointer to configuration struct
- *
- * \return Status of the initialization.
- *
- * \retval STATUS_OK                       The initialization was successful
- * \retval STATUS_BUSY                     The USART module is busy
- *                                         resetting
- * \retval STATUS_ERR_DENIED               The USART has not been disabled in
- *                                         advance of initialization
- * \retval STATUS_ERR_INVALID_ARG          The configuration struct contains
- *                                         invalid configuration
- * \retval STATUS_ERR_ALREADY_INITIALIZED  The SERCOM instance has already been
- *                                         initialized with different clock
- *                                         configuration
- * \retval STATUS_ERR_BAUD_UNAVAILABLE     The BAUD rate given by the
- *                                         configuration
- *                                         struct cannot be reached with
- *                                         the current clock configuration
- */
-enum status_code usart_init(
-		struct usart_module *const module,
-		Sercom *const hw,
-		const struct usart_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
-
-	enum status_code status_code = STATUS_OK;
-
-	/* Assign module pointer to software instance struct */
-	module->hw = hw;
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index, gclk_index; 
-#if (SAML22) || (SAMC20) 
-	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
-#elif (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
-	if (sercom_index == 5) {
-		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
-		gclk_index   = SERCOM5_GCLK_ID_CORE;
-	} else {
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
-#elif (SAMC21)
-	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	
-	if (sercom_index == 5){
-		gclk_index	= SERCOM5_GCLK_ID_CORE;
-    } else {
-    	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
-    }
-#else
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-#endif
-
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
-		/* The module is busy resetting itself */
-		return STATUS_BUSY;
-	}
-
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
-		/* Check the module is enabled */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Turn on module in PM */
-#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
-	if (sercom_index == 5) {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
-	} else {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
-	}
-#else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-#endif
-
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
-
-	/* Set character size */
-	module->character_size = config->character_size;
-
-	/* Set transmitter and receiver status */
-	module->receiver_enabled = config->receiver_enable;
-	module->transmitter_enabled = config->transmitter_enable;
-
-#ifdef FEATURE_USART_LIN_SLAVE
-	module->lin_slave_enabled = config->lin_slave_enable;
-#endif
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	module->start_frame_detection_enabled = config->start_frame_detection_enable;
-#endif
-#ifdef FEATURE_USART_ISO7816
-	module->iso7816_mode_enabled = config->iso7816_config.enabled;
-#endif
-	/* Set configuration according to the config struct */
-	status_code = _usart_set_config(module, config);
-	if(status_code != STATUS_OK) {
-		return status_code;
-	}
-
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
-
-	uint32_t pad_pinmuxes[] = {
-			config->pinmux_pad0, config->pinmux_pad1,
-			config->pinmux_pad2, config->pinmux_pad3
-		};
-
-	/* Configure the SERCOM pins according to the user configuration */
-	for (uint8_t pad = 0; pad < 4; pad++) {
-		uint32_t current_pinmux = pad_pinmuxes[pad];
-
-		if (current_pinmux == PINMUX_DEFAULT) {
-			current_pinmux = _sercom_get_default_pad(hw, pad);
-		}
-
-		if (current_pinmux != PINMUX_UNUSED) {
-			pin_conf.mux_position = current_pinmux & 0xFFFF;
-			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
-		}
-	}
-
-#if USART_CALLBACK_MODE == true
-	/* Initialize parameters */
-	for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
-		module->callback[i]            = NULL;
-	}
-
-	module->tx_buffer_ptr              = NULL;
-	module->rx_buffer_ptr              = NULL;
-	module->remaining_tx_buffer_length = 0x0000;
-	module->remaining_rx_buffer_length = 0x0000;
-	module->callback_reg_mask          = 0x00;
-	module->callback_enable_mask       = 0x00;
-	module->rx_status                  = STATUS_OK;
-	module->tx_status                  = STATUS_OK;
-
-	/* Set interrupt handler and register USART software module struct in
-	 * look-up table */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
-	_sercom_set_handler(instance_index, _usart_interrupt_handler);
-	_sercom_instances[instance_index] = module;
-#endif
-
-	return status_code;
-}
-
-/**
- * \brief Transmit a character via the USART
- *
- * This blocking function will transmit a single character via the
- * USART.
- *
- * \param[in]  module   Pointer to the software instance struct
- * \param[in]  tx_data  Data to transfer
- *
- * \return Status of the operation.
- * \retval STATUS_OK         If the operation was completed
- * \retval STATUS_BUSY       If the operation was not completed, due to the USART
- *                           module being busy
- * \retval STATUS_ERR_DENIED If the transmitter is not enabled
- */
-enum status_code usart_write_wait(
-		struct usart_module *const module,
-		const uint16_t tx_data)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-#if USART_CALLBACK_MODE == true
-	/* Check if the USART is busy doing asynchronous operation. */
-	if (module->remaining_tx_buffer_length > 0) {
-		return STATUS_BUSY;
-	}
-
-#else
-	/* Check if USART is ready for new data */
-	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
-		/* Return error code */
-		return STATUS_BUSY;
-	}
-#endif
-
-	/* Write data to USART module */
-	usart_hw->DATA.reg = tx_data;
-
-	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
-		/* Wait until data is sent */
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Receive a character via the USART
- *
- * This blocking function will receive a character via the USART.
- *
- * \param[in]   module   Pointer to the software instance struct
- * \param[out]  rx_data  Pointer to received data
- *
- * \return Status of the operation.
- * \retval STATUS_OK                If the operation was completed
- * \retval STATUS_BUSY              If the operation was not completed,
- *                                  due to the USART module being busy
- * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
- *                                  due to configuration mismatch between USART
- *                                  and the sender
- * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
- *                                  due to the baudrate being too low or the
- *                                  system frequency being too high
- * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due to
- *                                  data being corrupted
- * \retval STATUS_ERR_DENIED        If the receiver is not enabled
- */
-enum status_code usart_read_wait(
-		struct usart_module *const module,
-		uint16_t *const rx_data)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Error variable */
-	uint8_t error_code;
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-#if USART_CALLBACK_MODE == true
-	/* Check if the USART is busy doing asynchronous operation. */
-	if (module->remaining_rx_buffer_length > 0) {
-		return STATUS_BUSY;
-	}
-#endif
-
-	/* Check if USART has new data */
-	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
-		/* Return error code */
-		return STATUS_BUSY;
-	}
-
-	/* Read out the status code and mask away all but the 3 LSBs*/
-	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
-
-	/* Check if an error has occurred during the receiving */
-	if (error_code) {
-		/* Check which error occurred */
-		if (error_code & SERCOM_USART_STATUS_FERR) {
-			/* Clear flag by writing a 1 to it and
-			 * return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-
-			return STATUS_ERR_BAD_FORMAT;
-		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
-			/* Clear flag by writing a 1 to it and
-			 * return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-
-			return STATUS_ERR_OVERFLOW;
-		} else if (error_code & SERCOM_USART_STATUS_PERR) {
-			/* Clear flag by writing a 1 to it and
-			 * return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
-
-			return STATUS_ERR_BAD_DATA;
-		}
-#ifdef FEATURE_USART_LIN_SLAVE
-		else if (error_code & SERCOM_USART_STATUS_ISF) {
-			/* Clear flag by writing 1 to it  and
-			 *  return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
-
-			return STATUS_ERR_PROTOCOL;
-		}
-#endif
-#ifdef FEATURE_USART_COLLISION_DECTION
-		else if (error_code & SERCOM_USART_STATUS_COLL) {
-			/* Clear flag by writing 1 to it
-			 *  return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-
-			return STATUS_ERR_PACKET_COLLISION;
-		}
-#endif
-	}
-
-	/* Read data from USART module */
-	*rx_data = usart_hw->DATA.reg;
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Transmit a buffer of characters via the USART
- *
- * This blocking function will transmit a block of \c length characters
- * via the USART.
- *
- * \note Using this function in combination with the interrupt (\c _job) functions is
- *       not recommended as it has no functionality to check if there is an
- *       ongoing interrupt driven operation running or not.
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[in]  tx_data  Pointer to data to transmit
- * \param[in]  length   Number of characters to transmit
- *
- * \note If using 9-bit data, the array that *tx_data point to should be defined 
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
- *       is an address pointer, the highest byte is not discarded. For example:
- *   \code
-          #define TX_LEN 3
-          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
-          usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
-    \endcode
- *
- * \return Status of the operation.
- * \retval STATUS_OK              If operation was completed
- * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
- *                                arguments
- * \retval STATUS_ERR_TIMEOUT     If operation was not completed, due to USART
- *                                module timing out
- * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
- */
-enum status_code usart_write_buffer_wait(
-		struct usart_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Check if the buffer length is valid */
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	uint16_t tx_pos = 0;
-
-	/* Blocks while buffer is being transferred */
-	while (length--) {
-		/* Wait for the USART to be ready for new data and abort
-		* operation if it doesn't get ready within the timeout*/
-		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
-			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
-				break;
-			} else if (i == USART_TIMEOUT) {
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-
-		/* Data to send is at least 8 bits long */
-		uint16_t data_to_send = tx_data[tx_pos++];
-
-		/* Check if the character size exceeds 8 bit */
-		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-			data_to_send |= (tx_data[tx_pos++] << 8);
-		}
-
-		/* Send the data through the USART module */
-		usart_write_wait(module, data_to_send);
-	}
-
-	/* Wait until Transmit is complete or timeout */
-	for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
-		if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
-			break;
-		} else if (i == USART_TIMEOUT) {
-			return STATUS_ERR_TIMEOUT;
-		}
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Receive a buffer of \c length characters via the USART
- *
- * This blocking function will receive a block of \c length characters
- * via the USART.
- *
- * \note Using this function in combination with the interrupt (\c *_job)
- *       functions is not recommended as it has no functionality to check if
- *       there is an ongoing interrupt driven operation running or not.
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[out] rx_data  Pointer to receive buffer
- * \param[in]  length   Number of characters to receive
- *
- * \note If using 9-bit data, the array that *rx_data point to should be defined 
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
- *       is an address pointer, the highest byte is not discarded. For example:
- *   \code
-          #define RX_LEN 3
-          uint16_t rx_buf[RX_LEN] = {0x0,};
-          usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
-    \endcode
- *
- * \return Status of the operation.
- * \retval STATUS_OK                If operation was completed
- * \retval STATUS_ERR_INVALID_ARG   If operation was not completed, due to an
- *                                  invalid argument being supplied
- * \retval STATUS_ERR_TIMEOUT       If operation was not completed, due
- *                                  to USART module timing out
- * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
- *                                  due to a configuration mismatch
- *                                  between USART and the sender
- * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
- *                                  due to the baudrate being too low or the
- *                                  system frequency being too high
- * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due
- *                                  to data being corrupted
- * \retval STATUS_ERR_DENIED        If the receiver is not enabled
- */
-enum status_code usart_read_buffer_wait(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Check if the buffer length is valid */
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	uint16_t rx_pos = 0;
-
-	/* Blocks while buffer is being received */
-	while (length--) {
-		/* Wait for the USART to have new data and abort operation if it
-		 * doesn't get ready within the timeout*/
-		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
-			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
-				break;
-			} else if (i == USART_TIMEOUT) {
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-
-		enum status_code retval;
-		uint16_t received_data = 0;
-
-		retval = usart_read_wait(module, &received_data);
-
-		if (retval != STATUS_OK) {
-			/* Overflow, abort */
-			return retval;
-		}
-
-		/* Read value will be at least 8-bits long */
-		rx_data[rx_pos++] = received_data;
-
-		/* If 9-bit data, write next received byte to the buffer */
-		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-			rx_data[rx_pos++] = (received_data >> 8);
-		}
-	}
-
-	return STATUS_OK;
-}
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (c) 2012-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "usart.h"
+#include <pinmux.h>
+#if USART_CALLBACK_MODE == true
+#  include "usart_interrupt.h"
+#endif
+
+/**
+ * \internal
+ * Set Configuration of the USART module
+ */
+static enum status_code _usart_set_config(
+		struct usart_module *const module,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Index for generic clock */
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t gclk_index;
+
+#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (SAMC21)
+	if (sercom_index == 5) {
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#else
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	/* Cache new register values to minimize the number of register writes */
+	uint32_t ctrla = 0;
+	uint32_t ctrlb = 0;
+#ifdef FEATURE_USART_ISO7816
+	uint32_t ctrlc = 0;
+#endif
+	uint16_t baud  = 0;
+	uint32_t transfer_mode;
+
+	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+	switch (config->sample_rate) {
+		case USART_SAMPLE_RATE_16X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+		case USART_SAMPLE_RATE_3X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+			break;
+		case USART_SAMPLE_RATE_16X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+	}
+#endif
+
+	/* Set data order, internal muxing, and clock polarity */
+	ctrla = (uint32_t)config->data_order |
+		(uint32_t)config->mux_setting |
+	#ifdef FEATURE_USART_OVER_SAMPLE
+		config->sample_adjustment |
+		config->sample_rate |
+	#endif
+	#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+	#endif
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+	enum status_code status_code = STATUS_OK;
+
+	transfer_mode = (uint32_t)config->transfer_mode;
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		transfer_mode = config->iso7816_config.protocol_t;
+	}
+#endif
+	/* Get baud value from mode and clock */
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		baud = config->baudrate;
+	} else {
+#endif
+	switch (transfer_mode)
+	{
+		case USART_TRANSFER_SYNCHRONOUSLY:
+			if (!config->use_external_clock) {
+				status_code = _sercom_get_sync_baud_val(config->baudrate,
+						system_gclk_chan_get_hz(gclk_index), &baud);
+			}
+
+			break;
+
+		case USART_TRANSFER_ASYNCHRONOUSLY:
+			if (config->use_external_clock) {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							config->ext_clock_freq, &baud, mode, sample_num);
+			} else {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+			}
+
+			break;
+	}
+
+	/* Check if calculating the baudrate failed */
+	if (status_code != STATUS_OK) {
+		/* Abort */
+		return status_code;
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_IRDA
+	if(config->encoding_format_enable) {
+		usart_hw->RXPL.reg = config->receive_pulse_length;
+	}
+#endif
+
+	/*Set baud val */
+	usart_hw->BAUD.reg = baud;
+
+	/* Set sample mode */
+	ctrla |= transfer_mode;
+
+	if (config->use_external_clock == false) {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+	}
+	else {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
+	}
+
+	/* Set stopbits and enable transceivers */
+	ctrlb =  
+		#ifdef FEATURE_USART_IRDA
+			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+		#endif
+		#ifdef FEATURE_USART_START_FRAME_DECTION
+			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+		#endif
+		#ifdef FEATURE_USART_COLLISION_DECTION
+			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+		#endif
+			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
+		if (config->iso7816_config.enable_inverse) {
+			ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
+		}
+		ctrlb |=  USART_CHARACTER_SIZE_8BIT;
+		
+		switch(config->iso7816_config.protocol_t) {
+			case ISO7816_PROTOCOL_T_0:
+				ctrlb |= (uint32_t)config->stopbits;	
+				ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
+						(config->iso7816_config.inhibit_nack) | \
+						(config->iso7816_config.successive_recv_nack) | \
+						SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
+				break;	
+			case ISO7816_PROTOCOL_T_1:
+				ctrlb |= USART_STOPBITS_1;
+				break;		
+		}
+	} else {
+#endif
+	ctrlb |= (uint32_t)config->stopbits;
+	ctrlb |= (uint32_t)config->character_size;
+	/* Check parity mode bits */
+	if (config->parity != USART_PARITY_NONE) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(1);
+		ctrlb |= config->parity;
+	} else {
+#ifdef FEATURE_USART_LIN_SLAVE
+		if(config->lin_slave_enable) {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+		} else {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0);
+		}
+#else
+		ctrla |= SERCOM_USART_CTRLA_FORM(0);
+#endif
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
+						| config->lin_header_delay
+						| config->lin_break_length;
+
+	if (config->lin_node != LIN_INVALID_MODE) {
+		ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
+		ctrla |= config->lin_node;
+	}
+#endif
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+	}
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLB */
+	usart_hw->CTRLB.reg = ctrlb;
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLA */
+	usart_hw->CTRLA.reg = ctrla;
+
+#ifdef FEATURE_USART_RS485
+	if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
+		SERCOM_USART_CTRLA_FORM(0x07)) {
+		usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
+		usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
+	}
+#endif
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		_usart_wait_for_sync(module);
+		usart_hw->CTRLC.reg = ctrlc;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the USART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[out] module  Pointer to USART device
+ * \param[in]  hw      Pointer to USART hardware instance
+ * \param[in]  config  Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK                       The initialization was successful
+ * \retval STATUS_BUSY                     The USART module is busy
+ *                                         resetting
+ * \retval STATUS_ERR_DENIED               The USART has not been disabled in
+ *                                         advance of initialization
+ * \retval STATUS_ERR_INVALID_ARG          The configuration struct contains
+ *                                         invalid configuration
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  The SERCOM instance has already been
+ *                                         initialized with different clock
+ *                                         configuration
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE     The BAUD rate given by the
+ *                                         configuration
+ *                                         struct cannot be reached with
+ *                                         the current clock configuration
+ */
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	enum status_code status_code = STATUS_OK;
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index; 
+#if (SAML22) || (SAMC20) 
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+#elif (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
+	if (sercom_index == 5) {
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC21)
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	
+	if (sercom_index == 5){
+		gclk_index	= SERCOM5_GCLK_ID_CORE;
+    } else {
+    	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+		/* The module is busy resetting itself */
+		return STATUS_BUSY;
+	}
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+		/* Check the module is enabled */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35)
+	if (sercom_index == 5) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+	/* Set character size */
+	module->character_size = config->character_size;
+
+	/* Set transmitter and receiver status */
+	module->receiver_enabled = config->receiver_enable;
+	module->transmitter_enabled = config->transmitter_enable;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	module->lin_slave_enabled = config->lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	module->start_frame_detection_enabled = config->start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	module->iso7816_mode_enabled = config->iso7816_config.enabled;
+#endif
+	/* Set configuration according to the config struct */
+	status_code = _usart_set_config(module, config);
+	if(status_code != STATUS_OK) {
+		return status_code;
+	}
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+	uint32_t pad_pinmuxes[] = {
+			config->pinmux_pad0, config->pinmux_pad1,
+			config->pinmux_pad2, config->pinmux_pad3
+		};
+
+	/* Configure the SERCOM pins according to the user configuration */
+	for (uint8_t pad = 0; pad < 4; pad++) {
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+
+		if (current_pinmux == PINMUX_DEFAULT) {
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+		}
+
+		if (current_pinmux != PINMUX_UNUSED) {
+			pin_conf.mux_position = current_pinmux & 0xFFFF;
+			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+		}
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
+		module->callback[i]            = NULL;
+	}
+
+	module->tx_buffer_ptr              = NULL;
+	module->rx_buffer_ptr              = NULL;
+	module->remaining_tx_buffer_length = 0x0000;
+	module->remaining_rx_buffer_length = 0x0000;
+	module->callback_reg_mask          = 0x00;
+	module->callback_enable_mask       = 0x00;
+	module->rx_status                  = STATUS_OK;
+	module->tx_status                  = STATUS_OK;
+
+	/* Set interrupt handler and register USART software module struct in
+	 * look-up table */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _usart_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+#endif
+
+	return status_code;
+}
+
+/**
+ * \brief Transmit a character via the USART
+ *
+ * This blocking function will transmit a single character via the
+ * USART.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK         If the operation was completed
+ * \retval STATUS_BUSY       If the operation was not completed, due to the USART
+ *                           module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_wait(
+		struct usart_module *const module,
+		const uint16_t tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_tx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+
+#else
+	/* Check if USART is ready for new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Write data to USART module */
+	usart_hw->DATA.reg = tx_data;
+
+	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a character via the USART
+ *
+ * This blocking function will receive a character via the USART.
+ *
+ * \param[in]   module   Pointer to the software instance struct
+ * \param[out]  rx_data  Pointer to received data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If the operation was completed
+ * \retval STATUS_BUSY              If the operation was not completed,
+ *                                  due to the USART module being busy
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to configuration mismatch between USART
+ *                                  and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due to
+ *                                  data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_wait(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Error variable */
+	uint8_t error_code;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_rx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Check if USART has new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+
+	/* Read out the status code and mask away all but the 3 LSBs*/
+	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+	/* Check if an error has occurred during the receiving */
+	if (error_code) {
+		/* Check which error occurred */
+		if (error_code & SERCOM_USART_STATUS_FERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+			return STATUS_ERR_BAD_FORMAT;
+		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+			return STATUS_ERR_OVERFLOW;
+		} else if (error_code & SERCOM_USART_STATUS_PERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+			return STATUS_ERR_BAD_DATA;
+		}
+#ifdef FEATURE_USART_LIN_SLAVE
+		else if (error_code & SERCOM_USART_STATUS_ISF) {
+			/* Clear flag by writing 1 to it  and
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+
+			return STATUS_ERR_PROTOCOL;
+		}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+		else if (error_code & SERCOM_USART_STATUS_COLL) {
+			/* Clear flag by writing 1 to it
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+
+			return STATUS_ERR_PACKET_COLLISION;
+		}
+#endif
+	}
+
+	/* Read data from USART module */
+	*rx_data = usart_hw->DATA.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Transmit a buffer of characters via the USART
+ *
+ * This blocking function will transmit a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c _job) functions is
+ *       not recommended as it has no functionality to check if there is an
+ *       ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to transmit
+ * \param[in]  length   Number of characters to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_TIMEOUT     If operation was not completed, due to USART
+ *                                module timing out
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_wait(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint16_t tx_pos = 0;
+
+	/* Blocks while buffer is being transferred */
+	while (length--) {
+		/* Wait for the USART to be ready for new data and abort
+		* operation if it doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		/* Data to send is at least 8 bits long */
+		uint16_t data_to_send = tx_data[tx_pos++];
+
+		/* Check if the character size exceeds 8 bit */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			data_to_send |= (tx_data[tx_pos++] << 8);
+		}
+
+		/* Send the data through the USART module */
+		usart_write_wait(module, data_to_send);
+	}
+
+	/* Wait until Transmit is complete or timeout */
+	for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+		if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
+			break;
+		} else if (i == USART_TIMEOUT) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the USART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ *       functions is not recommended as it has no functionality to check if
+ *       there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to receive buffer
+ * \param[in]  length   Number of characters to receive
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define RX_LEN 3
+          uint16_t rx_buf[RX_LEN] = {0x0,};
+          usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG   If operation was not completed, due to an
+ *                                  invalid argument being supplied
+ * \retval STATUS_ERR_TIMEOUT       If operation was not completed, due
+ *                                  to USART module timing out
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to a configuration mismatch
+ *                                  between USART and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due
+ *                                  to data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_buffer_wait(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint16_t rx_pos = 0;
+
+	/* Blocks while buffer is being received */
+	while (length--) {
+		/* Wait for the USART to have new data and abort operation if it
+		 * doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		enum status_code retval;
+		uint16_t received_data = 0;
+
+		retval = usart_read_wait(module, &received_data);
+
+		if (retval != STATUS_OK) {
+			/* Overflow, abort */
+			return retval;
+		}
+
+		/* Read value will be at least 8-bits long */
+		rx_data[rx_pos++] = received_data;
+
+		/* If 9-bit data, write next received byte to the buffer */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			rx_data[rx_pos++] = (received_data >> 8);
+		}
+	}
+
+	return STATUS_OK;
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.h
index 9b8070b..db1dbf1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart.h
@@ -1,1589 +1,1589 @@
-/**
- *
- * \file
- *
- * \brief SAM SERCOM USART Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef USART_H_INCLUDED
-#define USART_H_INCLUDED
-
-/**
- * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART (SERCOM USART) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
- * an interface for the configuration and management of the SERCOM module in
- * its USART mode to transfer or receive USART data frames. The following driver
- * API modes are covered by this manual:
- *
- *  - Polled APIs
- * \if USART_CALLBACK_MODE
- *  - Callback APIs
- * \endif
- *
- * The following peripheral is used by this module:
- * - SERCOM (Serial Communication Interface)
- *
- * The following devices can use this module:
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM D10/D11
- *  - Atmel | SMART SAM L21/L22
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM C20/C21
- *  - Atmel | SMART SAM HA1
- *  - Atmel | SMART SAM R30
- *  - Atmel | SMART SAM R34
- *  - Atmel | SMART SAM R35
- *
- * The outline of this documentation is as follows:
- * - \ref asfdoc_sam0_sercom_usart_prerequisites
- * - \ref asfdoc_sam0_sercom_usart_overview
- * - \ref asfdoc_sam0_sercom_usart_special_considerations
- * - \ref asfdoc_sam0_sercom_usart_extra_info
- * - \ref asfdoc_sam0_sercom_usart_examples
- * - \ref asfdoc_sam0_sercom_usart_api_overview
- *
- * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites
- *
- * To use the USART you need to have a GCLK generator enabled and running
- * that can be used as the SERCOM clock source. This can either be configured
- * in conf_clocks.h or by using the system clock driver.
- *
- * \section asfdoc_sam0_sercom_usart_overview Module Overview
- *
- * This driver will use one (or more) SERCOM interface(s) in the system
- * and configure it to run as a USART interface in either synchronous
- * or asynchronous mode.
- *
- * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition
- * <table>
- *  <tr>
- *    <th>Driver Feature Macro</th>
- *    <th>Supported devices</th>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_SYNC_SCHEME_V2</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_OVER_SAMPLE</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_HARDWARE_FLOW_CONTROL</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_IRDA</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_LIN_SLAVE</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_COLLISION_DECTION</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_START_FRAME_DECTION</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION</td>
- *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_USART_RS485</td>
- *    <td>SAM C20/C21</td>
- *  </tr>
- * <tr>
- *    <td>FEATURE_USART_LIN_MASTER</td>
- *    <td>SAM L22/C20/C21</td>
- *  </tr>
- * </table>
- * \note The specific features are only available in the driver when the
- * selected device supports those features.
- *
- * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format
- *
- * Communication is based on frames, where the frame format can be customized
- * to accommodate a wide range of standards. A frame consists of a start bit,
- * a number of data bits, an optional parity bit for error detection as well
- * as a configurable length stop bit(s) - see
- * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below".
- * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the
- * available parameters you can change in a frame.
- *
- * \anchor asfdoc_sam0_sercom_usart_frame_params
- * <table>
- *  <caption>USART Frame Parameters</caption>
- *  <tr>
- *      <th>Parameter</th>
- *      <th>Options</th>
- *  </tr>
- *  <tr>
- *      <td>Start bit</td>
- *      <td>1</td>
- *  </tr>
- *  <tr>
- *      <td>Data bits</td>
- *      <td>5, 6, 7, 8, 9</td>
- *  </tr>
- *  <tr>
- *      <td>Parity bit</td>
- *      <td>None, Even, Odd</td>
- *  </tr>
- *  <tr>
- *      <td>Stop bits</td>
- *      <td>1, 2</td>
- *  </tr>
- * </table>
- *
- * \anchor asfdoc_sam0_sercom_usart_frame_diagram
- * \image html usart_frame.svg "USART Frame Overview" width=100%
- *
- * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous Mode
- *
- * In synchronous mode a dedicated clock line is provided; either by the USART
- * itself if in master mode, or by an external master if in slave mode.
- * Maximum transmission speed is the same as the GCLK clocking the USART
- * peripheral when in slave mode, and the GCLK divided by two if in
- * master mode. In synchronous mode the interface needs three lines to
- * communicate:
- * - TX (Transmit pin)
- * - RX (Receive pin)
- * - XCK (Clock pin)
- *
- * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data Sampling
- * In synchronous mode the data is sampled on either the rising or falling edge
- * of the clock signal. This is configured by setting the clock polarity in the
- * configuration struct.
- *
- * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous Mode
- *
- * In asynchronous mode no dedicated clock line is used, and the communication
- * is based on matching the clock speed on the transmitter and receiver. The
- * clock is generated from the internal SERCOM baudrate generator, and the
- * frames are synchronized by using the frame start bits. Maximum transmission
- * speed is limited to the SERCOM GCLK divided by 16.
- * In asynchronous mode the interface only needs two lines to communicate:
- * - TX (Transmit pin)
- * - RX (Receive pin)
- *
- * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver Clock Matching
- *
- * For successful transmit and receive using the asynchronous mode the receiver
- * and transmitter clocks needs to be closely matched. When receiving a frame
- * that does not match the selected baudrate closely enough the receiver will
- * be unable to synchronize the frame(s), and garbage transmissions will
- * result.
- *
- * \subsection asfdoc_sam0_sercom_usart_parity Parity
- * Parity can be enabled to detect if a transmission was in error. This is done
- * by counting the number of "1" bits in the frame. When using even parity the
- * parity bit will be set if the total number of "1"s in the frame are an even
- * number. If using odd parity the parity bit will be set if the total number
- * of "1"s are odd.
- *
- * When receiving a character the receiver will count the number of "1"s in the
- * frame and give an error if the received frame and parity bit disagree.
- *
- * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO Configuration
- *
- * The SERCOM module has four internal pads; the RX pin can be placed freely on
- * any one of the four pads, and the TX and XCK pins have two predefined
- * positions that can be selected as a pair. The pads can then be routed to an
- * external GPIO pin using the normal pin multiplexing scheme on the SAM.
- *
- * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations
- *
- * \if USART_CALLBACK_MODE
- * Never execute large portions of code in the callbacks. These
- * are run from the interrupt routine, and thus having long callbacks will
- * keep the processor in the interrupt handler for an equally long time.
- * A common way to handle this is to use global flags signaling the
- * main application that an interrupt event has happened, and only do the
- * minimal needed processing in the callback.
- * \else
- * No special considerations.
- * \endif
- *
- * \section asfdoc_sam0_sercom_usart_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_sercom_usart_extra. This includes:
- * - \ref asfdoc_sam0_sercom_usart_extra_acronyms
- * - \ref asfdoc_sam0_sercom_usart_extra_dependencies
- * - \ref asfdoc_sam0_sercom_usart_extra_errata
- * - \ref asfdoc_sam0_sercom_usart_extra_history
- *
- * \section asfdoc_sam0_sercom_usart_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_sercom_usart_exqsg.
- *
- * \section asfdoc_sam0_sercom_usart_api_overview API Overview
- * @{
- */
-
-#include <compiler.h>
-#include <sercom.h>
-#include <pinmux.h>
-
-#if USART_CALLBACK_MODE == true
-#  include <sercom_interrupt.h>
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name Driver Feature Definition
- * Define SERCOM USART features set according to different device family.
- * @{
- */
-
-#if (SAMD21) || (SAMR21) || (SAMD09) || (SAMD10) || (SAMD11) || \
-	(SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || \
-	(SAMR30) || (SAMHA1) || (SAMHA0) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
-/** USART sync scheme version 2. */
-#  define FEATURE_USART_SYNC_SCHEME_V2
-/** USART oversampling. */
-#  define FEATURE_USART_OVER_SAMPLE
-/** USART hardware control flow. */
-#  define FEATURE_USART_HARDWARE_FLOW_CONTROL
-/** IrDA mode. */
-#  define FEATURE_USART_IRDA
-/** LIN slave mode. */
-#  define FEATURE_USART_LIN_SLAVE
-/** USART collision detection. */
-#  define FEATURE_USART_COLLISION_DECTION
-/** USART start frame detection. */
-#  define FEATURE_USART_START_FRAME_DECTION
-/** USART start buffer overflow notification. */
-#  define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-#endif
-
-#if (SAML22) || defined(__DOXYGEN__)
-/** ISO7816 for smart card interfacing. */
-#define FEATURE_USART_ISO7816
-#endif
-#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
-/** LIN master mode. */
-#define FEATURE_USART_LIN_MASTER
-#endif
-#if (SAML22) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
-/** RS485 mode. */
-#  define FEATURE_USART_RS485
-#endif
-/*@}*/
-
-#ifdef FEATURE_USART_LIN_MASTER
-/**
- * \brief LIN node type
- *
- * LIN node type.
- */
-enum lin_node_type {
-	/** LIN master mode */
-	LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02),
-	/** LIN slave mode */
-	LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04),
-	/** Neither LIN master nor LIN slave mode */
-	LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00),
-};
-
-/**
- * \brief LIN master command enum
- *
- * LIN master command enum.
- */
-enum lin_master_cmd {
-	/** LIN master software control transmission command */
-	LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01),
-	/** LIN master automatically transmission command */
-	LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02),
-};
-
-/**
- * \brief LIN master header delay
- *
- * LIN master header delay between break and sync transmission,
- * and between the sync and identifier (ID) fields.
- * This field is only valid when using automatically transmission command
- */
-enum lin_master_header_delay {
-	/** Delay between break and sync transmission is 1 bit time.
-		Delay between sync and ID transmission is 1 bit time. */
-	LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0),
-	/** Delay between break and sync transmission is 4 bit time.
-		Delay between sync and ID transmission is 4 bit time. */
-	LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01),
-	/** Delay between break and sync transmission is 8 bit time.
-		Delay between sync and ID transmission is 4 bit time. */
-	LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02),
-	/** Delay between break and sync transmission is 14 bit time.
-		Delay between sync and ID transmission is 4 bit time. */
-	LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03),
-};
-
-/**
- * \brief LIN master break length
- *
- * Length of the break field transmitted when in LIN master mode
- */
-enum lin_master_break_length {
-	/** Break field transmission is 13 bit times */
-	LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0),
-	/** Break field transmission is 17 bit times */
-	LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1),
-	/** Break field transmission is 21 bit times */
-	LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2),
-	/** Break field transmission is 26 bit times */
-	LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3),
-};
-#endif
-#ifdef FEATURE_USART_ISO7816
-/**
- * \brief ISO7816 protocol type
- *
- * ISO7816 protocol type.
- */
-enum iso7816_protocol_type {
-	/** ISO7816 protocol type 0 */
-	ISO7816_PROTOCOL_T_0 = SERCOM_USART_CTRLA_CMODE,
-	/** ISO7816 protocol type 1 */
-	ISO7816_PROTOCOL_T_1 = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
-};
-
-/**
- * \brief ISO7816 guard time
- *
- * The value of ISO7816 guard time.
- */
-enum iso7816_guard_time {
-	/** The guard time is 2-bit times */
-	ISO7816_GUARD_TIME_2_BIT = 2,
-	/** The guard time is 3-bit times */
-	ISO7816_GUARD_TIME_3_BIT,
-	/** The guard time is 4-bit times */
-	ISO7816_GUARD_TIME_4_BIT,
-	/** The guard time is 5-bit times */
-	ISO7816_GUARD_TIME_5_BIT,
-	/** The guard time is 6-bit times */
-	ISO7816_GUARD_TIME_6_BIT,
-	/** The guard time is 7-bit times */
-	ISO7816_GUARD_TIME_7_BIT,
-};
-
-/**
- * \brief ISO7816 receive NACK inhibit
- *
- * The value of ISO7816 receive NACK inhibit.
- */
-enum iso7816_inhibit_nack {
-	/** The NACK is generated */
-	ISO7816_INHIBIT_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
-	/** The NACK is not generated */
-	ISO7816_INHIBIT_NACK_ENABLE = SERCOM_USART_CTRLC_INACK,
-};
-
-/**
- * \brief ISO7816 disable successive receive NACK
- *
- * The value of ISO7816 disable successive receive NACK.
- */
-enum iso7816_successive_recv_nack {
-	/** The successive receive NACK is enable. */
-	ISO7816_SUCCESSIVE_RECV_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
-	/** The successive receive NACK is disable. */
-	ISO7816_SUCCESSIVE_RECV_NACK_ENABLE = SERCOM_USART_CTRLC_DSNACK,
-};
-
-/**
- * \brief ISO7816 configuration struct
- *
- * ISO7816 configuration structure.
- */
-struct iso7816_config_t {
-	/* ISO7816 mode enable */
-	bool enabled;
-	/** ISO7816 protocol type */
-	enum iso7816_protocol_type protocol_t;
-	/** Enable inverse transmission and reception */
-	bool enable_inverse;
-	/** Guard time, which lasts two bit times */
-	enum iso7816_guard_time guard_time;
-	/**
-	 * Inhibit Non Acknowledge:
-	 *   - 0: the NACK is generated;
-	 *   - 1: the NACK is not generated.
-	 */
-	enum iso7816_inhibit_nack inhibit_nack;
-	/**
-	 * Disable successive NACKs.
-	 *  - 0: NACK is sent on the ISO line as soon as a parity error occurs
-	 * in the received character. Successive parity errors are counted up to
-	 * the value in the max_iterations field. These parity errors generate
-	 * a NACK on the ISO line. As soon as this value is reached, no additional
-	 * NACK is sent on the ISO line. The ITERATION flag is asserted.
-	 */
-	enum iso7816_successive_recv_nack successive_recv_nack;
-	/* Max number of repetitions */
-	uint32_t max_iterations;
-};
-#endif
-
-#ifndef PINMUX_DEFAULT
-/** Default pinmux */
-#  define PINMUX_DEFAULT 0
-#endif
-
-#ifndef PINMUX_UNUSED
-/** Unused pinmux */
-#  define PINMUX_UNUSED 0xFFFFFFFF
-#endif
-
-#ifndef USART_TIMEOUT
-/** USART timeout value */
-#  define USART_TIMEOUT 0xFFFF
-#endif
-
-#if USART_CALLBACK_MODE == true
-/**
- * \brief USART callback enum
- *
- * Callbacks for the Asynchronous USART driver.
- */
-enum usart_callback {
-	/** Callback for buffer transmitted */
-	USART_CALLBACK_BUFFER_TRANSMITTED,
-	/** Callback for buffer received */
-	USART_CALLBACK_BUFFER_RECEIVED,
-	/** Callback for error */
-	USART_CALLBACK_ERROR,
-#ifdef FEATURE_USART_LIN_SLAVE
-	/** Callback for break character is received */
-	USART_CALLBACK_BREAK_RECEIVED,
-#endif
-#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	/** Callback for a change is detected on the CTS pin */
-	USART_CALLBACK_CTS_INPUT_CHANGE,
-#endif
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	/** Callback for a start condition is detected on the RxD line */
-	USART_CALLBACK_START_RECEIVED,
-#endif
-#  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	USART_CALLBACK_N,
-#  endif
-};
-#endif
-
-/**
- * \brief USART Data Order enum
- *
- * The data order decides which MSB or LSB is shifted out first when data is
- * transferred.
- */
-enum usart_dataorder {
-	/** The MSB will be shifted out first during transmission,
-	 *  and shifted in first during reception */
-	USART_DATAORDER_MSB = 0,
-	/** The LSB will be shifted out first during transmission,
-	 *  and shifted in first during reception */
-	USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
-};
-
-/**
- * \brief USART Transfer mode enum
- *
- * Select USART transfer mode.
- */
-enum usart_transfer_mode {
-	/** Transfer of data is done synchronously */
-	USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
-	/** Transfer of data is done asynchronously */
-	USART_TRANSFER_ASYNCHRONOUSLY = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
-};
-
-/**
- * \brief USART Parity enum
- *
- * Select parity USART parity mode.
- */
-enum usart_parity {
-	/** For odd parity checking, the parity bit will be set if number of
-	 *  ones being transferred is even */
-	USART_PARITY_ODD  = SERCOM_USART_CTRLB_PMODE,
-
-	/** For even parity checking, the parity bit will be set if number of
-	 *  ones being received is odd */
-	USART_PARITY_EVEN = 0,
-
-	/** No parity checking will be executed, and there will be no parity bit
-	 *  in the received frame */
-	USART_PARITY_NONE = 0xFF,
-};
-
-/**
- * \brief USART signal MUX settings
- *
- * Set the functionality of the SERCOM pins.
- *
- * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the
- * various MUX setting options.
- */
-enum usart_signal_mux_settings {
-#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	/** MUX setting RX_0_TX_0_XCK_1 */
-	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_0_TX_2_XCK_3 */
-	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */
-	USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
-	/** MUX setting RX_1_TX_0_XCK_1 */
-	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_1_TX_2_XCK_3 */
-	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */
-	USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
-	/** MUX setting RX_2_TX_0_XCK_1 */
-	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_2_TX_2_XCK_3 */
-	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */
-	USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
-	/** MUX setting RX_3_TX_0_XCK_1 */
-	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_3_TX_2_XCK_3 */
-	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */
-	USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
-#ifdef FEATURE_USART_RS485
-	/** MUX setting USART_RX_0_TX_0_XCK_1_TE_2 */
-	USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)),
-	/** MUX setting USART_RX_1_TX_0_XCK_1_TE_2 */
-	USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)),
-	/** MUX setting USART_RX_2_TX_0_XCK_1_TE_2 */
-	USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)),
-	/** MUX setting USART_RX_3_TX_0_XCK_1_TE_2 */
-	USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)),
-#endif
-#else
-	/** MUX setting RX_0_TX_0_XCK_1 */
-	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
-	/** MUX setting RX_0_TX_2_XCK_3 */
-	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
-	/** MUX setting RX_1_TX_0_XCK_1 */
-	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
-	/** MUX setting RX_1_TX_2_XCK_3 */
-	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
-	/** MUX setting RX_2_TX_0_XCK_1 */
-	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
-	/** MUX setting RX_2_TX_2_XCK_3 */
-	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
-	/** MUX setting RX_3_TX_0_XCK_1 */
-	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
-	/** MUX setting RX_3_TX_2_XCK_3 */
-	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
-#endif
-};
-
-/**
- * \brief USART Stop Bits enum
- *
- * Number of stop bits for a frame.
- */
-enum usart_stopbits {
-	/** Each transferred frame contains one stop bit */
-	USART_STOPBITS_1 = 0,
-	/** Each transferred frame contains two stop bits */
-	USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
-};
-
-/**
- * \brief USART Character Size
- *
- * Number of bits for the character sent in a frame.
- */
-enum usart_character_size {
-	/** The char being sent in a frame is five bits long */
-	USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
-	/** The char being sent in a frame is six bits long */
-	USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
-	/** The char being sent in a frame is seven bits long */
-	USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
-	/** The char being sent in a frame is eight bits long */
-	USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
-	/** The char being sent in a frame is nine bits long */
-	USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
-};
-
-#ifdef FEATURE_USART_OVER_SAMPLE
-/**
- * \brief USART Sample Rate
- *
- * The value of sample rate and baudrate generation mode.
- */
-enum usart_sample_rate {
-	/** 16x over-sampling using arithmetic baudrate generation */
-	USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
-	/** 16x over-sampling using fractional baudrate generation */
-	USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
-	/** 8x over-sampling using arithmetic baudrate generation */
-	USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
-	/** 8x over-sampling using fractional baudrate generation */
-	USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
-	/** 3x over-sampling using arithmetic baudrate generation */
-	USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
-};
-
-/**
- * \brief USART Sample Adjustment
- *
- * The value of sample number used for majority voting.
- */
-enum usart_sample_adjustment {
-	/** The first, middle and last sample number used for majority voting is 7-8-9 */
-	USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
-	/** The first, middle and last sample number used for majority voting is 9-10-11 */
-	USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
-	/** The first, middle and last sample number used for majority voting is 11-12-13 */
-	USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
-	/** The first, middle and last sample number used for majority voting is 13-14-15 */
-	USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
-};
-#endif
-
-#ifdef FEATURE_USART_RS485
-/**
- * \brief RS485 Guard Time
- *
- * The value of RS485 guard time.
- */
-enum rs485_guard_time {
-	/** The guard time is 0-bit time */
-	RS485_GUARD_TIME_0_BIT = 0,
-	/** The guard time is 1-bit time */
-	RS485_GUARD_TIME_1_BIT,
-	/** The guard time is 2-bit times */
-	RS485_GUARD_TIME_2_BIT,
-	/** The guard time is 3-bit times */
-	RS485_GUARD_TIME_3_BIT,
-	/** The guard time is 4-bit times */
-	RS485_GUARD_TIME_4_BIT,
-	/** The guard time is 5-bit times */
-	RS485_GUARD_TIME_5_BIT,
-	/** The guard time is 6-bit times */
-	RS485_GUARD_TIME_6_BIT,
-	/** The guard time is 7-bit times */
-	RS485_GUARD_TIME_7_BIT,
-};
-#endif
-
-/**
- * \brief USART Transceiver
- *
- * Select Receiver or Transmitter.
- */
-enum usart_transceiver_type {
-	/** The parameter is for the Receiver */
-	USART_TRANSCEIVER_RX,
-	/** The parameter is for the Transmitter */
-	USART_TRANSCEIVER_TX,
-};
-
-/**
- * \brief USART configuration struct
- *
- * Configuration options for USART.
- */
-struct usart_config {
-	/** USART bit order (MSB or LSB first) */
-	enum usart_dataorder data_order;
-	/** USART in asynchronous or synchronous mode */
-	enum usart_transfer_mode transfer_mode;
-	/** USART parity */
-	enum usart_parity parity;
-	/** Number of stop bits */
-	enum usart_stopbits stopbits;
-	/** USART character size */
-	enum usart_character_size character_size;
-	/** USART pin out */
-	enum usart_signal_mux_settings mux_setting;
-#ifdef FEATURE_USART_OVER_SAMPLE
-	/** USART sample rate */
-	enum usart_sample_rate sample_rate;
-	/** USART sample adjustment */
-	enum usart_sample_adjustment sample_adjustment;
-#endif
-#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-	/** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs */
-	bool immediate_buffer_overflow_notification;
-#endif
-#ifdef FEATURE_USART_IRDA
-	/** Enable IrDA encoding format */
-	bool encoding_format_enable;
-	/** The minimum pulse length required for a pulse to be accepted by the IrDA receiver */
-	uint8_t receive_pulse_length;
-#endif
-#ifdef FEATURE_USART_LIN_SLAVE
-	/** Enable LIN Slave Support */
-	bool lin_slave_enable;
-#endif
-
-#ifdef FEATURE_USART_LIN_MASTER
-	/** LIN node type */
-	enum lin_node_type lin_node;
-	/** LIN master header delay */
-	enum lin_master_header_delay lin_header_delay;
-	/** LIN Master Break Length */
-	enum lin_master_break_length lin_break_length;
-#endif
-
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	/** Enable start of frame dection */
-	bool start_frame_detection_enable;
-#endif
-#ifdef FEATURE_USART_ISO7816
-	/** Enable ISO7816 for smart card interfacing */
-	struct iso7816_config_t iso7816_config;
-#endif
-#ifdef FEATURE_USART_RS485
-	/** RS485 guard time */
-	enum rs485_guard_time rs485_guard_time;
-#endif
-#ifdef FEATURE_USART_COLLISION_DECTION
-	/** Enable collision dection */
-	bool collision_detection_enable;
-#endif
-	/** USART baudrate */
-	uint32_t baudrate;
-	/** Enable receiver */
-	bool receiver_enable;
-	/** Enable transmitter */
-	bool transmitter_enable;
-
-	/** USART Clock Polarity.
-	 * If true, data changes on falling XCK edge and
-	 * is sampled at rising edge.
-	 * If false, data changes on rising XCK edge and
-	 * is sampled at falling edge.
-	 * */
-	bool clock_polarity_inverted;
-
-	/** States whether to use the external clock applied to the XCK pin.
-	 * In synchronous mode the shift register will act directly on the XCK clock.
-	 * In asynchronous mode the XCK will be the input to the USART hardware module.
-	 */
-	bool use_external_clock;
-	/** External clock frequency in synchronous mode.
-	 * This must be set if \c use_external_clock is true. */
-	uint32_t ext_clock_freq;
-	/** If true the USART will be kept running in Standby sleep mode */
-	bool run_in_standby;
-	/** GCLK generator source */
-	enum gclk_generator generator_source;
-	/** PAD0 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD0, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD0.
-	 */
-	uint32_t pinmux_pad0;
-	/** PAD1 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD1, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD1.
-	 */
-	uint32_t pinmux_pad1;
-	/** PAD2 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD2, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD2.
-	 */
-	uint32_t pinmux_pad2;
-	/** PAD3 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD3, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD3.
-	 */
-	uint32_t pinmux_pad3;
-};
-
-#if USART_CALLBACK_MODE == true
-/**
- * \brief USART module instance
- *
- * Forward Declaration for the device instance.
- */
-struct usart_module;
-
-/**
- * \brief USART callback type
- *
- * Type of the callback functions.
- */
-typedef void (*usart_callback_t)(struct usart_module *const module);
-#endif
-
-/**
- * \brief SERCOM USART driver software device instance structure.
- *
- * SERCOM USART driver software instance structure, used to retain software
- * state information of an associated hardware module instance.
- *
- * \note The fields of this structure should not be altered by the user
- *       application; they are reserved for module-internal use only.
- */
-struct usart_module {
-#if !defined(__DOXYGEN__)
-	/** Pointer to the hardware instance */
-	Sercom *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** Character size of the data being transferred */
-	enum usart_character_size character_size;
-	/** Receiver enabled */
-	bool receiver_enabled;
-	/** Transmitter enabled */
-	bool transmitter_enabled;
-#ifdef FEATURE_USART_LIN_SLAVE
-	/** LIN Slave Support enabled */
-	bool lin_slave_enabled;
-#endif
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	/** Start of frame dection enabled */
-	bool start_frame_detection_enabled;
-#endif
-#ifdef FEATURE_USART_ISO7816
-	/** ISO7816 mode enable */
-	bool iso7816_mode_enabled;
-#endif
-#  if USART_CALLBACK_MODE == true
-	/** Array to store callback function pointers in */
-	usart_callback_t callback[USART_CALLBACK_N];
-	/** Buffer pointer to where the next received character will be put */
-	volatile uint8_t *rx_buffer_ptr;
-
-	/** Buffer pointer to where the next character will be transmitted from
-	**/
-	volatile uint8_t *tx_buffer_ptr;
-	/** Remaining characters to receive */
-	volatile uint16_t remaining_rx_buffer_length;
-	/** Remaining characters to transmit */
-	volatile uint16_t remaining_tx_buffer_length;
-	/** Bit mask for callbacks registered */
-	uint8_t callback_reg_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t callback_enable_mask;
-	/** Holds the status of the ongoing or last read operation */
-	volatile enum status_code rx_status;
-	/** Holds the status of the ongoing or last write operation */
-	volatile enum status_code tx_status;
-#  endif
-#endif
-};
-
- /**
- * \name Lock/Unlock
- * @{
- */
-
-/**
- * \brief Attempt to get lock on driver instance
- *
- * This function checks the instance's lock, which indicates whether or not it
- * is currently in use, and sets the lock if it was not already set.
- *
- * The purpose of this is to enable exclusive access to driver instances, so
- * that, e.g., transactions by different services will not interfere with each
- * other.
- *
- * \param[in,out] module Pointer to the driver instance to lock
- *
- * \retval STATUS_OK If the module was locked
- * \retval STATUS_BUSY If the module was already locked
- */
-static inline enum status_code usart_lock(
-		struct usart_module *const module)
-{
-	enum status_code status;
-
-	system_interrupt_enter_critical_section();
-
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
-
-	system_interrupt_leave_critical_section();
-
-	return status;
-}
-
-/**
- * \brief Unlock driver instance
- *
- * This function clears the instance lock, indicating that it is available for
- * use.
- *
- * \param[in,out] module Pointer to the driver instance to lock
- *
- */
-static inline void usart_unlock(struct usart_module *const module)
-{
-	module->locked = false;
-}
-
-/** @} */
-
-/**
- * \brief Check if peripheral is busy syncing registers across clock domains
- *
- * Return peripheral synchronization status. If doing a non-blocking
- * implementation this function can be used to check the sync state and hold of
- * any new actions until sync is complete. If this function is not run; the
- * functions will block until the sync has completed.
- *
- * \param[in]  module  Pointer to peripheral module
- *
- * \return Peripheral sync status.
- *
- * \retval true   Peripheral is busy syncing
- * \retval false  Peripheral is not busy syncing and can be read/written without
- *                stalling the bus
- */
-static inline bool usart_is_syncing(
-		const struct usart_module *const module)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-#ifdef FEATURE_USART_SYNC_SCHEME_V2
-	return (usart_hw->SYNCBUSY.reg);
-#else
-	return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
-#endif
-}
-
-#if !defined (__DOXYGEN__)
-/**
- * \internal
- * Waits until synchronization is complete
- */
-static inline void _usart_wait_for_sync(
-		const struct usart_module *const module)
-{
-	/* Sanity check */
-	Assert(module);
-
-	while (usart_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
-}
-#endif
-
-/**
- * \brief Initializes the device to predefined defaults
- *
- * Initialize the USART device to predefined defaults:
- * - 8-bit asynchronous USART
- * - No parity
- * - One stop bit
- * - 9600 baud
- * - Transmitter enabled
- * - Receiver enabled
- * - GCLK generator 0 as clock source
- * - Default pin configuration
- *
- * The configuration struct will be updated with the default
- * configuration.
- *
- * \param[in,out] config  Pointer to configuration struct
- */
-static inline void usart_get_config_defaults(
-		struct usart_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Set default config in the config struct */
-	config->data_order       = USART_DATAORDER_LSB;
-	config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
-	config->parity           = USART_PARITY_NONE;
-	config->stopbits         = USART_STOPBITS_1;
-	config->character_size   = USART_CHARACTER_SIZE_8BIT;
-	config->baudrate         = 9600;
-	config->receiver_enable  = true;
-	config->transmitter_enable = true;
-	config->clock_polarity_inverted = false;
-	config->use_external_clock = false;
-	config->ext_clock_freq   = 0;
-	config->mux_setting      = USART_RX_1_TX_2_XCK_3;
-	config->run_in_standby   = false;
-	config->generator_source = GCLK_GENERATOR_0;
-	config->pinmux_pad0      = PINMUX_DEFAULT;
-	config->pinmux_pad1      = PINMUX_DEFAULT;
-	config->pinmux_pad2      = PINMUX_DEFAULT;
-	config->pinmux_pad3      = PINMUX_DEFAULT;
-#ifdef FEATURE_USART_OVER_SAMPLE
-	config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
-	config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
-#endif
-#ifdef FEATURE_USART_LIN_SLAVE
-	config->lin_slave_enable      = false;
-#endif
-
-#ifdef FEATURE_USART_LIN_MASTER
-	config->lin_node = LIN_INVALID_MODE;
-	config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
-	config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
-#endif
-
-#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-	config->immediate_buffer_overflow_notification  = false;
-#endif
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	config->start_frame_detection_enable            = false;
-#endif
-#ifdef FEATURE_USART_IRDA
-	config->encoding_format_enable                  = false;
-	config->receive_pulse_length                    = 19;
-#endif
-#ifdef FEATURE_USART_ISO7816
-	config->iso7816_config.enabled                  = false;
-	config->iso7816_config.guard_time               = ISO7816_GUARD_TIME_2_BIT;
-	config->iso7816_config.protocol_t               = ISO7816_PROTOCOL_T_0;
-	config->iso7816_config.enable_inverse           = false;
-	config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
-	config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
-	config->iso7816_config.max_iterations           = 7;
-#endif
-#ifdef FEATURE_USART_COLLISION_DECTION
-	config->collision_detection_enable              = false;
-#endif
-#ifdef FEATURE_USART_RS485
-	config->rs485_guard_time = RS485_GUARD_TIME_0_BIT;
-#endif
-}
-
-enum status_code usart_init(
-		struct usart_module *const module,
-		Sercom *const hw,
-		const struct usart_config *const config);
-
-/**
- * \brief Enable the module
- *
- * Enables the USART module.
- *
- * \param[in]  module  Pointer to USART software instance struct
- */
-static inline void usart_enable(
-		const struct usart_module *const module)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-#if USART_CALLBACK_MODE == true
-	/* Enable Global interrupt for module */
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
-#endif
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Enable USART module */
-	usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
-}
-
-/**
- * \brief Disable module
- *
- * Disables the USART module.
- *
- * \param[in]  module  Pointer to USART software instance struct
- */
-static inline void usart_disable(
-		const struct usart_module *const module)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-#if USART_CALLBACK_MODE == true
-	/* Disable Global interrupt for module */
-	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
-#endif
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Disable USART module */
-	usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
-}
-
-/**
- * \brief Resets the USART module
- *
- * Disables and resets the USART module.
- *
- * \param[in]  module  Pointer to the USART software instance struct
- */
-static inline void usart_reset(
-		const struct usart_module *const module)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	usart_disable(module);
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Reset module */
-	usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
-}
-
-/**
- * \name Writing and Reading
- * @{
- */
-enum status_code usart_write_wait(
-		struct usart_module *const module,
-		const uint16_t tx_data);
-
-enum status_code usart_read_wait(
-		struct usart_module *const module,
-		uint16_t *const rx_data);
-
-enum status_code usart_write_buffer_wait(
-		struct usart_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length);
-
-enum status_code usart_read_buffer_wait(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length);
-/** @} */
-
-/**
- * \name Enabling/Disabling Receiver and Transmitter
- * @{
- */
-
-/**
- * \brief Enable Transceiver
- *
- * Enable the given transceiver. Either RX or TX.
- *
- * \param[in]  module            Pointer to USART software instance struct
- * \param[in]  transceiver_type  Transceiver type
- */
-static inline void usart_enable_transceiver(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	switch (transceiver_type) {
-		case USART_TRANSCEIVER_RX:
-			/* Enable RX */
-			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
-			module->receiver_enabled = true;
-			break;
-
-		case USART_TRANSCEIVER_TX:
-			/* Enable TX */
-			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
-			module->transmitter_enabled = true;
-			break;
-	}
-	_usart_wait_for_sync(module);
-}
-
-/**
- * \brief Disable Transceiver
- *
- * Disable the given transceiver (RX or TX).
- *
- * \param[in]  module            Pointer to USART software instance struct
- * \param[in]  transceiver_type  Transceiver type
- */
-static inline void usart_disable_transceiver(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	switch (transceiver_type) {
-		case USART_TRANSCEIVER_RX:
-			/* Disable RX */
-			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
-			module->receiver_enabled = false;
-			break;
-
-		case USART_TRANSCEIVER_TX:
-			/* Disable TX */
-			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
-			module->transmitter_enabled = false;
-			break;
-	}
-}
-
-/** @} */
-
-#ifdef FEATURE_USART_LIN_MASTER
-/**
- * \name LIN Master Command and Status
- * @{
- */
-
-/**
- * \brief Sending LIN command.
- *
- * Sending LIN command.
- *
- * \param[in]  module Pointer to USART software instance struct
- * \param[in]  cmd  Cammand type
- */
-static inline void lin_master_send_cmd(
-		struct usart_module *const module,
-		enum lin_master_cmd cmd)
-{
-	SercomUsart *const usart_hw = &(module->hw->USART);
-	_usart_wait_for_sync(module);
-	usart_hw->CTRLB.reg |= cmd;
-}
-
-/**
- * \brief Get LIN transmission status
- *
- * Get LIN transmission status.
- *
- * \param[in]  module Pointer to USART software instance struct
- *
- * \return Status of LIN master transmission.
- * \retval true   Data transmission completed
- * \retval false  Transmission is ongoing
- */
-static inline bool lin_master_transmission_status(struct usart_module *const module)
-{
-	SercomUsart *const usart_hw = &(module->hw->USART);
-	return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false);
-}
-
-/** @} */
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-/**
-* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver
-*
-* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms
-*
-* Below is a table listing the acronyms used in this module, along with their
-* intended meanings.
-*
-* <table>
-* <tr>
-* <th>Acronym</th>
-* <th>Description</th>
-* </tr>
-* <tr>
-* <td>SERCOM</td>
-* <td>Serial Communication Interface</td>
-* </tr>
-* <tr>
-* <td>USART</td>
-* <td>Universal Synchronous and Asynchronous Serial Receiver and Transmitter</td>
-* </tr>
-* <tr>
-* <td>LSB</td>
-* <td>Least Significant Bit</td>
-* </tr>
-* <tr>
-* <td>MSB</td>
-* <td>Most Significant Bit</td>
-* </tr>
-* <tr>
-* <td>DMA</td>
-* <td>Direct Memory Access</td>
-* </tr>
-* </table>
-*
-*
-* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies
-* This driver has the following dependencies:
-*
-* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
-* - \ref asfdoc_sam0_system_clock_group "System clock configuration"
-*
-*
-* \section asfdoc_sam0_sercom_usart_extra_errata Errata
-* There are no errata related to this driver.
-*
-*
-* \section asfdoc_sam0_sercom_usart_extra_history Module History
-* An overview of the module history is presented in the table below, with
-* details on the enhancements and fixes made to the module since its first
-* release. The current version of this corresponds to the newest version in
-* the table.
-*
- * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added new feature as below:
- *          \li ISO7816
- *	</tr>
- *	<tr>
- *		<td>Added new features as below:
- *          \li LIN master
- *          \li RS485
- *	</tr>
- *	<tr>
- *		<td>Added new features as below:
- *          \li Oversample
- *          \li Buffer overflow notification
- *          \li Irda
- *          \li Lin slave
- *          \li Start frame detection
- *          \li Hardware flow control
- *          \li Collision detection
- *          \li DMA support </td>
- *	</tr>
- *	<tr>
- *		<td>\li Added new \c transmitter_enable and \c receiver_enable Boolean
- *              values to \c struct usart_config
- *          \li Altered \c usart_write_* and usart_read_* functions to abort with
- *              an error code if the relevant transceiver is not enabled
- *          \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()
- *              not aborting correctly when a timeout condition occurs</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
- * </table>
-*/
-
-/**
- * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver
- *
- * This is a list of the available Quick Start guides (QSGs) and example
- * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with
- * step-by-step instructions to configure and use this driver in a selection of
- * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.
- *
- * - \subpage asfdoc_sam0_sercom_usart_basic_use_case
- * \if USART_CALLBACK_MODE
- * - \subpage asfdoc_sam0_sercom_usart_callback_use_case
- * \endif
- * - \subpage asfdoc_sam0_sercom_usart_dma_use_case
- * - \subpage asfdoc_sam0_sercom_usart_lin_use_case
- */
-
-/**
- * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings
- *
- * The following lists the possible internal SERCOM module pad function
- * assignments, for the four SERCOM pads when in USART mode. Note that this is
- * in addition to the physical GPIO pin MUX of the device, and can be used in
- * conjunction to optimize the serial data pin-out.
- *
- * When TX and RX are connected to the same pin, the USART will operate in
- * half-duplex mode if both one transmitter and several receivers are enabled.
- *
- * \note When RX and XCK are connected to the same pin, the receiver must not
- *       be enabled if the USART is configured to use an external clock.
- *
- *
- * <table>
- *		<tr>
- *			<th>MUX/Pad</th>
- *			<th>PAD 0</th>
- *			<th>PAD 1</th>
- *			<th>PAD 2</th>
- *			<th>PAD 3</th>
- *		</tr>
- *		<tr>
- *			<td>RX_0_TX_0_XCK_1</td>
- *			<td>TX / RX</td>
- *			<td>XCK</td>
- *			<td>-</td>
- *			<td>-</td>
- *		</tr>
- *		<tr>
- *			<td>RX_0_TX_2_XCK_3</td>
- *			<td>RX</td>
- *			<td>-</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *		</tr>
- *		<tr>
- *			<td>RX_1_TX_0_XCK_1</td>
- *			<td>TX</td>
- *			<td>RX / XCK</td>
- *			<td>-</td>
- *			<td>-</td>
- *		</tr>
- *		<tr>
- *			<td>RX_1_TX_2_XCK_3</td>
- *			<td>-</td>
- *			<td>RX</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *		</tr>
- *		<tr>
- *			<td>RX_2_TX_0_XCK_1</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *			<td>RX</td>
- *			<td>-</td>
- *		</tr>
- *		<tr>
- *			<td>RX_2_TX_2_XCK_3</td>
- *			<td>-</td>
- *			<td>-</td>
- *			<td>TX / RX</td>
- *			<td>XCK</td>
- *		</tr>
- *		<tr>
- *			<td>RX_3_TX_0_XCK_1</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *			<td>-</td>
- *			<td>RX</td>
- *		</tr>
- *		<tr>
- *			<td>RX_3_TX_2_XCK_3</td>
- *			<td>-</td>
- *			<td>-</td>
- *			<td>TX</td>
- *			<td>RX / XCK</td>
- *		</tr>
- * </table>
- *
- * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History
- *
- * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42118F</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAMR30/R34 and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42118E</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42118D</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42118C</td>
- *		<td>10/2013</td>
- *		<td>Replaced the pad multiplexing documentation with a condensed table</td>
- *	</tr>
- *	<tr>
- *		<td>42118B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42118A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
- * </table>
- */
-#endif /* USART_H_INCLUDED */
+/**
+ *
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef USART_H_INCLUDED
+#define USART_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART (SERCOM USART) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the SERCOM module in
+ * its USART mode to transfer or receive USART data frames. The following driver
+ * API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ * \if USART_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_usart_prerequisites
+ * - \ref asfdoc_sam0_sercom_usart_overview
+ * - \ref asfdoc_sam0_sercom_usart_special_considerations
+ * - \ref asfdoc_sam0_sercom_usart_extra_info
+ * - \ref asfdoc_sam0_sercom_usart_examples
+ * - \ref asfdoc_sam0_sercom_usart_api_overview
+ *
+ * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites
+ *
+ * To use the USART you need to have a GCLK generator enabled and running
+ * that can be used as the SERCOM clock source. This can either be configured
+ * in conf_clocks.h or by using the system clock driver.
+ *
+ * \section asfdoc_sam0_sercom_usart_overview Module Overview
+ *
+ * This driver will use one (or more) SERCOM interface(s) in the system
+ * and configure it to run as a USART interface in either synchronous
+ * or asynchronous mode.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_SYNC_SCHEME_V2</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_OVER_SAMPLE</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_HARDWARE_FLOW_CONTROL</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_IRDA</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_LIN_SLAVE</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_COLLISION_DECTION</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_START_FRAME_DECTION</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION</td>
+ *    <td>SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_USART_RS485</td>
+ *    <td>SAM C20/C21</td>
+ *  </tr>
+ * <tr>
+ *    <td>FEATURE_USART_LIN_MASTER</td>
+ *    <td>SAM L22/C20/C21</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format
+ *
+ * Communication is based on frames, where the frame format can be customized
+ * to accommodate a wide range of standards. A frame consists of a start bit,
+ * a number of data bits, an optional parity bit for error detection as well
+ * as a configurable length stop bit(s) - see
+ * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below".
+ * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the
+ * available parameters you can change in a frame.
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_params
+ * <table>
+ *  <caption>USART Frame Parameters</caption>
+ *  <tr>
+ *      <th>Parameter</th>
+ *      <th>Options</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Start bit</td>
+ *      <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Data bits</td>
+ *      <td>5, 6, 7, 8, 9</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Parity bit</td>
+ *      <td>None, Even, Odd</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Stop bits</td>
+ *      <td>1, 2</td>
+ *  </tr>
+ * </table>
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_diagram
+ * \image html usart_frame.svg "USART Frame Overview" width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous Mode
+ *
+ * In synchronous mode a dedicated clock line is provided; either by the USART
+ * itself if in master mode, or by an external master if in slave mode.
+ * Maximum transmission speed is the same as the GCLK clocking the USART
+ * peripheral when in slave mode, and the GCLK divided by two if in
+ * master mode. In synchronous mode the interface needs three lines to
+ * communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ * - XCK (Clock pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data Sampling
+ * In synchronous mode the data is sampled on either the rising or falling edge
+ * of the clock signal. This is configured by setting the clock polarity in the
+ * configuration struct.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous Mode
+ *
+ * In asynchronous mode no dedicated clock line is used, and the communication
+ * is based on matching the clock speed on the transmitter and receiver. The
+ * clock is generated from the internal SERCOM baudrate generator, and the
+ * frames are synchronized by using the frame start bits. Maximum transmission
+ * speed is limited to the SERCOM GCLK divided by 16.
+ * In asynchronous mode the interface only needs two lines to communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver Clock Matching
+ *
+ * For successful transmit and receive using the asynchronous mode the receiver
+ * and transmitter clocks needs to be closely matched. When receiving a frame
+ * that does not match the selected baudrate closely enough the receiver will
+ * be unable to synchronize the frame(s), and garbage transmissions will
+ * result.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_parity Parity
+ * Parity can be enabled to detect if a transmission was in error. This is done
+ * by counting the number of "1" bits in the frame. When using even parity the
+ * parity bit will be set if the total number of "1"s in the frame are an even
+ * number. If using odd parity the parity bit will be set if the total number
+ * of "1"s are odd.
+ *
+ * When receiving a character the receiver will count the number of "1"s in the
+ * frame and give an error if the received frame and parity bit disagree.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO Configuration
+ *
+ * The SERCOM module has four internal pads; the RX pin can be placed freely on
+ * any one of the four pads, and the TX and XCK pins have two predefined
+ * positions that can be selected as a pair. The pads can then be routed to an
+ * external GPIO pin using the normal pin multiplexing scheme on the SAM.
+ *
+ * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations
+ *
+ * \if USART_CALLBACK_MODE
+ * Never execute large portions of code in the callbacks. These
+ * are run from the interrupt routine, and thus having long callbacks will
+ * keep the processor in the interrupt handler for an equally long time.
+ * A common way to handle this is to use global flags signaling the
+ * main application that an interrupt event has happened, and only do the
+ * minimal needed processing in the callback.
+ * \else
+ * No special considerations.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_usart_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_sercom_usart_extra. This includes:
+ * - \ref asfdoc_sam0_sercom_usart_extra_acronyms
+ * - \ref asfdoc_sam0_sercom_usart_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_usart_extra_errata
+ * - \ref asfdoc_sam0_sercom_usart_extra_history
+ *
+ * \section asfdoc_sam0_sercom_usart_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_usart_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_usart_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <sercom.h>
+#include <pinmux.h>
+
+#if USART_CALLBACK_MODE == true
+#  include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM USART features set according to different device family.
+ * @{
+ */
+
+#if (SAMD21) || (SAMR21) || (SAMD09) || (SAMD10) || (SAMD11) || \
+	(SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || \
+	(SAMR30) || (SAMHA1) || (SAMHA0) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
+/** USART sync scheme version 2. */
+#  define FEATURE_USART_SYNC_SCHEME_V2
+/** USART oversampling. */
+#  define FEATURE_USART_OVER_SAMPLE
+/** USART hardware control flow. */
+#  define FEATURE_USART_HARDWARE_FLOW_CONTROL
+/** IrDA mode. */
+#  define FEATURE_USART_IRDA
+/** LIN slave mode. */
+#  define FEATURE_USART_LIN_SLAVE
+/** USART collision detection. */
+#  define FEATURE_USART_COLLISION_DECTION
+/** USART start frame detection. */
+#  define FEATURE_USART_START_FRAME_DECTION
+/** USART start buffer overflow notification. */
+#  define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+#endif
+
+#if (SAML22) || defined(__DOXYGEN__)
+/** ISO7816 for smart card interfacing. */
+#define FEATURE_USART_ISO7816
+#endif
+#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
+/** LIN master mode. */
+#define FEATURE_USART_LIN_MASTER
+#endif
+#if (SAML22) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
+/** RS485 mode. */
+#  define FEATURE_USART_RS485
+#endif
+/*@}*/
+
+#ifdef FEATURE_USART_LIN_MASTER
+/**
+ * \brief LIN node type
+ *
+ * LIN node type.
+ */
+enum lin_node_type {
+	/** LIN master mode */
+	LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02),
+	/** LIN slave mode */
+	LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04),
+	/** Neither LIN master nor LIN slave mode */
+	LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00),
+};
+
+/**
+ * \brief LIN master command enum
+ *
+ * LIN master command enum.
+ */
+enum lin_master_cmd {
+	/** LIN master software control transmission command */
+	LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01),
+	/** LIN master automatically transmission command */
+	LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02),
+};
+
+/**
+ * \brief LIN master header delay
+ *
+ * LIN master header delay between break and sync transmission,
+ * and between the sync and identifier (ID) fields.
+ * This field is only valid when using automatically transmission command
+ */
+enum lin_master_header_delay {
+	/** Delay between break and sync transmission is 1 bit time.
+		Delay between sync and ID transmission is 1 bit time. */
+	LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0),
+	/** Delay between break and sync transmission is 4 bit time.
+		Delay between sync and ID transmission is 4 bit time. */
+	LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01),
+	/** Delay between break and sync transmission is 8 bit time.
+		Delay between sync and ID transmission is 4 bit time. */
+	LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02),
+	/** Delay between break and sync transmission is 14 bit time.
+		Delay between sync and ID transmission is 4 bit time. */
+	LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03),
+};
+
+/**
+ * \brief LIN master break length
+ *
+ * Length of the break field transmitted when in LIN master mode
+ */
+enum lin_master_break_length {
+	/** Break field transmission is 13 bit times */
+	LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0),
+	/** Break field transmission is 17 bit times */
+	LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1),
+	/** Break field transmission is 21 bit times */
+	LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2),
+	/** Break field transmission is 26 bit times */
+	LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3),
+};
+#endif
+#ifdef FEATURE_USART_ISO7816
+/**
+ * \brief ISO7816 protocol type
+ *
+ * ISO7816 protocol type.
+ */
+enum iso7816_protocol_type {
+	/** ISO7816 protocol type 0 */
+	ISO7816_PROTOCOL_T_0 = SERCOM_USART_CTRLA_CMODE,
+	/** ISO7816 protocol type 1 */
+	ISO7816_PROTOCOL_T_1 = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
+};
+
+/**
+ * \brief ISO7816 guard time
+ *
+ * The value of ISO7816 guard time.
+ */
+enum iso7816_guard_time {
+	/** The guard time is 2-bit times */
+	ISO7816_GUARD_TIME_2_BIT = 2,
+	/** The guard time is 3-bit times */
+	ISO7816_GUARD_TIME_3_BIT,
+	/** The guard time is 4-bit times */
+	ISO7816_GUARD_TIME_4_BIT,
+	/** The guard time is 5-bit times */
+	ISO7816_GUARD_TIME_5_BIT,
+	/** The guard time is 6-bit times */
+	ISO7816_GUARD_TIME_6_BIT,
+	/** The guard time is 7-bit times */
+	ISO7816_GUARD_TIME_7_BIT,
+};
+
+/**
+ * \brief ISO7816 receive NACK inhibit
+ *
+ * The value of ISO7816 receive NACK inhibit.
+ */
+enum iso7816_inhibit_nack {
+	/** The NACK is generated */
+	ISO7816_INHIBIT_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
+	/** The NACK is not generated */
+	ISO7816_INHIBIT_NACK_ENABLE = SERCOM_USART_CTRLC_INACK,
+};
+
+/**
+ * \brief ISO7816 disable successive receive NACK
+ *
+ * The value of ISO7816 disable successive receive NACK.
+ */
+enum iso7816_successive_recv_nack {
+	/** The successive receive NACK is enable. */
+	ISO7816_SUCCESSIVE_RECV_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
+	/** The successive receive NACK is disable. */
+	ISO7816_SUCCESSIVE_RECV_NACK_ENABLE = SERCOM_USART_CTRLC_DSNACK,
+};
+
+/**
+ * \brief ISO7816 configuration struct
+ *
+ * ISO7816 configuration structure.
+ */
+struct iso7816_config_t {
+	/* ISO7816 mode enable */
+	bool enabled;
+	/** ISO7816 protocol type */
+	enum iso7816_protocol_type protocol_t;
+	/** Enable inverse transmission and reception */
+	bool enable_inverse;
+	/** Guard time, which lasts two bit times */
+	enum iso7816_guard_time guard_time;
+	/**
+	 * Inhibit Non Acknowledge:
+	 *   - 0: the NACK is generated;
+	 *   - 1: the NACK is not generated.
+	 */
+	enum iso7816_inhibit_nack inhibit_nack;
+	/**
+	 * Disable successive NACKs.
+	 *  - 0: NACK is sent on the ISO line as soon as a parity error occurs
+	 * in the received character. Successive parity errors are counted up to
+	 * the value in the max_iterations field. These parity errors generate
+	 * a NACK on the ISO line. As soon as this value is reached, no additional
+	 * NACK is sent on the ISO line. The ITERATION flag is asserted.
+	 */
+	enum iso7816_successive_recv_nack successive_recv_nack;
+	/* Max number of repetitions */
+	uint32_t max_iterations;
+};
+#endif
+
+#ifndef PINMUX_DEFAULT
+/** Default pinmux */
+#  define PINMUX_DEFAULT 0
+#endif
+
+#ifndef PINMUX_UNUSED
+/** Unused pinmux */
+#  define PINMUX_UNUSED 0xFFFFFFFF
+#endif
+
+#ifndef USART_TIMEOUT
+/** USART timeout value */
+#  define USART_TIMEOUT 0xFFFF
+#endif
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART callback enum
+ *
+ * Callbacks for the Asynchronous USART driver.
+ */
+enum usart_callback {
+	/** Callback for buffer transmitted */
+	USART_CALLBACK_BUFFER_TRANSMITTED,
+	/** Callback for buffer received */
+	USART_CALLBACK_BUFFER_RECEIVED,
+	/** Callback for error */
+	USART_CALLBACK_ERROR,
+#ifdef FEATURE_USART_LIN_SLAVE
+	/** Callback for break character is received */
+	USART_CALLBACK_BREAK_RECEIVED,
+#endif
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	/** Callback for a change is detected on the CTS pin */
+	USART_CALLBACK_CTS_INPUT_CHANGE,
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/** Callback for a start condition is detected on the RxD line */
+	USART_CALLBACK_START_RECEIVED,
+#endif
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	USART_CALLBACK_N,
+#  endif
+};
+#endif
+
+/**
+ * \brief USART Data Order enum
+ *
+ * The data order decides which MSB or LSB is shifted out first when data is
+ * transferred.
+ */
+enum usart_dataorder {
+	/** The MSB will be shifted out first during transmission,
+	 *  and shifted in first during reception */
+	USART_DATAORDER_MSB = 0,
+	/** The LSB will be shifted out first during transmission,
+	 *  and shifted in first during reception */
+	USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
+};
+
+/**
+ * \brief USART Transfer mode enum
+ *
+ * Select USART transfer mode.
+ */
+enum usart_transfer_mode {
+	/** Transfer of data is done synchronously */
+	USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
+	/** Transfer of data is done asynchronously */
+	USART_TRANSFER_ASYNCHRONOUSLY = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
+};
+
+/**
+ * \brief USART Parity enum
+ *
+ * Select parity USART parity mode.
+ */
+enum usart_parity {
+	/** For odd parity checking, the parity bit will be set if number of
+	 *  ones being transferred is even */
+	USART_PARITY_ODD  = SERCOM_USART_CTRLB_PMODE,
+
+	/** For even parity checking, the parity bit will be set if number of
+	 *  ones being received is odd */
+	USART_PARITY_EVEN = 0,
+
+	/** No parity checking will be executed, and there will be no parity bit
+	 *  in the received frame */
+	USART_PARITY_NONE = 0xFF,
+};
+
+/**
+ * \brief USART signal MUX settings
+ *
+ * Set the functionality of the SERCOM pins.
+ *
+ * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the
+ * various MUX setting options.
+ */
+enum usart_signal_mux_settings {
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	/** MUX setting RX_0_TX_0_XCK_1 */
+	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_0_TX_2_XCK_3 */
+	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */
+	USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
+	/** MUX setting RX_1_TX_0_XCK_1 */
+	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_1_TX_2_XCK_3 */
+	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */
+	USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
+	/** MUX setting RX_2_TX_0_XCK_1 */
+	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_2_TX_2_XCK_3 */
+	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */
+	USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
+	/** MUX setting RX_3_TX_0_XCK_1 */
+	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
+	/** MUX setting RX_3_TX_2_XCK_3 */
+	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
+	/** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */
+	USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
+#ifdef FEATURE_USART_RS485
+	/** MUX setting USART_RX_0_TX_0_XCK_1_TE_2 */
+	USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)),
+	/** MUX setting USART_RX_1_TX_0_XCK_1_TE_2 */
+	USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)),
+	/** MUX setting USART_RX_2_TX_0_XCK_1_TE_2 */
+	USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)),
+	/** MUX setting USART_RX_3_TX_0_XCK_1_TE_2 */
+	USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)),
+#endif
+#else
+	/** MUX setting RX_0_TX_0_XCK_1 */
+	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
+	/** MUX setting RX_0_TX_2_XCK_3 */
+	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
+	/** MUX setting RX_1_TX_0_XCK_1 */
+	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
+	/** MUX setting RX_1_TX_2_XCK_3 */
+	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
+	/** MUX setting RX_2_TX_0_XCK_1 */
+	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
+	/** MUX setting RX_2_TX_2_XCK_3 */
+	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
+	/** MUX setting RX_3_TX_0_XCK_1 */
+	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
+	/** MUX setting RX_3_TX_2_XCK_3 */
+	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
+#endif
+};
+
+/**
+ * \brief USART Stop Bits enum
+ *
+ * Number of stop bits for a frame.
+ */
+enum usart_stopbits {
+	/** Each transferred frame contains one stop bit */
+	USART_STOPBITS_1 = 0,
+	/** Each transferred frame contains two stop bits */
+	USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
+};
+
+/**
+ * \brief USART Character Size
+ *
+ * Number of bits for the character sent in a frame.
+ */
+enum usart_character_size {
+	/** The char being sent in a frame is five bits long */
+	USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
+	/** The char being sent in a frame is six bits long */
+	USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
+	/** The char being sent in a frame is seven bits long */
+	USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
+	/** The char being sent in a frame is eight bits long */
+	USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
+	/** The char being sent in a frame is nine bits long */
+	USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
+};
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+/**
+ * \brief USART Sample Rate
+ *
+ * The value of sample rate and baudrate generation mode.
+ */
+enum usart_sample_rate {
+	/** 16x over-sampling using arithmetic baudrate generation */
+	USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
+	/** 16x over-sampling using fractional baudrate generation */
+	USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
+	/** 8x over-sampling using arithmetic baudrate generation */
+	USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
+	/** 8x over-sampling using fractional baudrate generation */
+	USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
+	/** 3x over-sampling using arithmetic baudrate generation */
+	USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
+};
+
+/**
+ * \brief USART Sample Adjustment
+ *
+ * The value of sample number used for majority voting.
+ */
+enum usart_sample_adjustment {
+	/** The first, middle and last sample number used for majority voting is 7-8-9 */
+	USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
+	/** The first, middle and last sample number used for majority voting is 9-10-11 */
+	USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
+	/** The first, middle and last sample number used for majority voting is 11-12-13 */
+	USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
+	/** The first, middle and last sample number used for majority voting is 13-14-15 */
+	USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
+};
+#endif
+
+#ifdef FEATURE_USART_RS485
+/**
+ * \brief RS485 Guard Time
+ *
+ * The value of RS485 guard time.
+ */
+enum rs485_guard_time {
+	/** The guard time is 0-bit time */
+	RS485_GUARD_TIME_0_BIT = 0,
+	/** The guard time is 1-bit time */
+	RS485_GUARD_TIME_1_BIT,
+	/** The guard time is 2-bit times */
+	RS485_GUARD_TIME_2_BIT,
+	/** The guard time is 3-bit times */
+	RS485_GUARD_TIME_3_BIT,
+	/** The guard time is 4-bit times */
+	RS485_GUARD_TIME_4_BIT,
+	/** The guard time is 5-bit times */
+	RS485_GUARD_TIME_5_BIT,
+	/** The guard time is 6-bit times */
+	RS485_GUARD_TIME_6_BIT,
+	/** The guard time is 7-bit times */
+	RS485_GUARD_TIME_7_BIT,
+};
+#endif
+
+/**
+ * \brief USART Transceiver
+ *
+ * Select Receiver or Transmitter.
+ */
+enum usart_transceiver_type {
+	/** The parameter is for the Receiver */
+	USART_TRANSCEIVER_RX,
+	/** The parameter is for the Transmitter */
+	USART_TRANSCEIVER_TX,
+};
+
+/**
+ * \brief USART configuration struct
+ *
+ * Configuration options for USART.
+ */
+struct usart_config {
+	/** USART bit order (MSB or LSB first) */
+	enum usart_dataorder data_order;
+	/** USART in asynchronous or synchronous mode */
+	enum usart_transfer_mode transfer_mode;
+	/** USART parity */
+	enum usart_parity parity;
+	/** Number of stop bits */
+	enum usart_stopbits stopbits;
+	/** USART character size */
+	enum usart_character_size character_size;
+	/** USART pin out */
+	enum usart_signal_mux_settings mux_setting;
+#ifdef FEATURE_USART_OVER_SAMPLE
+	/** USART sample rate */
+	enum usart_sample_rate sample_rate;
+	/** USART sample adjustment */
+	enum usart_sample_adjustment sample_adjustment;
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+	/** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs */
+	bool immediate_buffer_overflow_notification;
+#endif
+#ifdef FEATURE_USART_IRDA
+	/** Enable IrDA encoding format */
+	bool encoding_format_enable;
+	/** The minimum pulse length required for a pulse to be accepted by the IrDA receiver */
+	uint8_t receive_pulse_length;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+	/** Enable LIN Slave Support */
+	bool lin_slave_enable;
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	/** LIN node type */
+	enum lin_node_type lin_node;
+	/** LIN master header delay */
+	enum lin_master_header_delay lin_header_delay;
+	/** LIN Master Break Length */
+	enum lin_master_break_length lin_break_length;
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/** Enable start of frame dection */
+	bool start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	/** Enable ISO7816 for smart card interfacing */
+	struct iso7816_config_t iso7816_config;
+#endif
+#ifdef FEATURE_USART_RS485
+	/** RS485 guard time */
+	enum rs485_guard_time rs485_guard_time;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+	/** Enable collision dection */
+	bool collision_detection_enable;
+#endif
+	/** USART baudrate */
+	uint32_t baudrate;
+	/** Enable receiver */
+	bool receiver_enable;
+	/** Enable transmitter */
+	bool transmitter_enable;
+
+	/** USART Clock Polarity.
+	 * If true, data changes on falling XCK edge and
+	 * is sampled at rising edge.
+	 * If false, data changes on rising XCK edge and
+	 * is sampled at falling edge.
+	 * */
+	bool clock_polarity_inverted;
+
+	/** States whether to use the external clock applied to the XCK pin.
+	 * In synchronous mode the shift register will act directly on the XCK clock.
+	 * In asynchronous mode the XCK will be the input to the USART hardware module.
+	 */
+	bool use_external_clock;
+	/** External clock frequency in synchronous mode.
+	 * This must be set if \c use_external_clock is true. */
+	uint32_t ext_clock_freq;
+	/** If true the USART will be kept running in Standby sleep mode */
+	bool run_in_standby;
+	/** GCLK generator source */
+	enum gclk_generator generator_source;
+	/** PAD0 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD0, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD0.
+	 */
+	uint32_t pinmux_pad0;
+	/** PAD1 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD1, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD1.
+	 */
+	uint32_t pinmux_pad1;
+	/** PAD2 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD2, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD2.
+	 */
+	uint32_t pinmux_pad2;
+	/** PAD3 pinmux.
+	 *
+	 * If current USARTx has several alternative multiplexing I/O pins for PAD3, then
+	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3
+	 * function. Make sure that no other alternative multiplexing I/O is associated
+	 * with the same USARTx PAD3.
+	 */
+	uint32_t pinmux_pad3;
+};
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART module instance
+ *
+ * Forward Declaration for the device instance.
+ */
+struct usart_module;
+
+/**
+ * \brief USART callback type
+ *
+ * Type of the callback functions.
+ */
+typedef void (*usart_callback_t)(struct usart_module *const module);
+#endif
+
+/**
+ * \brief SERCOM USART driver software device instance structure.
+ *
+ * SERCOM USART driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct usart_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to the hardware instance */
+	Sercom *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** Character size of the data being transferred */
+	enum usart_character_size character_size;
+	/** Receiver enabled */
+	bool receiver_enabled;
+	/** Transmitter enabled */
+	bool transmitter_enabled;
+#ifdef FEATURE_USART_LIN_SLAVE
+	/** LIN Slave Support enabled */
+	bool lin_slave_enabled;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/** Start of frame dection enabled */
+	bool start_frame_detection_enabled;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	/** ISO7816 mode enable */
+	bool iso7816_mode_enabled;
+#endif
+#  if USART_CALLBACK_MODE == true
+	/** Array to store callback function pointers in */
+	usart_callback_t callback[USART_CALLBACK_N];
+	/** Buffer pointer to where the next received character will be put */
+	volatile uint8_t *rx_buffer_ptr;
+
+	/** Buffer pointer to where the next character will be transmitted from
+	**/
+	volatile uint8_t *tx_buffer_ptr;
+	/** Remaining characters to receive */
+	volatile uint16_t remaining_rx_buffer_length;
+	/** Remaining characters to transmit */
+	volatile uint16_t remaining_tx_buffer_length;
+	/** Bit mask for callbacks registered */
+	uint8_t callback_reg_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t callback_enable_mask;
+	/** Holds the status of the ongoing or last read operation */
+	volatile enum status_code rx_status;
+	/** Holds the status of the ongoing or last write operation */
+	volatile enum status_code tx_status;
+#  endif
+#endif
+};
+
+ /**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code usart_lock(
+		struct usart_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ */
+static inline void usart_unlock(struct usart_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \brief Check if peripheral is busy syncing registers across clock domains
+ *
+ * Return peripheral synchronization status. If doing a non-blocking
+ * implementation this function can be used to check the sync state and hold of
+ * any new actions until sync is complete. If this function is not run; the
+ * functions will block until the sync has completed.
+ *
+ * \param[in]  module  Pointer to peripheral module
+ *
+ * \return Peripheral sync status.
+ *
+ * \retval true   Peripheral is busy syncing
+ * \retval false  Peripheral is not busy syncing and can be read/written without
+ *                stalling the bus
+ */
+static inline bool usart_is_syncing(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+#ifdef FEATURE_USART_SYNC_SCHEME_V2
+	return (usart_hw->SYNCBUSY.reg);
+#else
+	return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
+#endif
+}
+
+#if !defined (__DOXYGEN__)
+/**
+ * \internal
+ * Waits until synchronization is complete
+ */
+static inline void _usart_wait_for_sync(
+		const struct usart_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+
+	while (usart_is_syncing(module)) {
+		/* Wait until the synchronization is complete */
+	}
+}
+#endif
+
+/**
+ * \brief Initializes the device to predefined defaults
+ *
+ * Initialize the USART device to predefined defaults:
+ * - 8-bit asynchronous USART
+ * - No parity
+ * - One stop bit
+ * - 9600 baud
+ * - Transmitter enabled
+ * - Receiver enabled
+ * - GCLK generator 0 as clock source
+ * - Default pin configuration
+ *
+ * The configuration struct will be updated with the default
+ * configuration.
+ *
+ * \param[in,out] config  Pointer to configuration struct
+ */
+static inline void usart_get_config_defaults(
+		struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Set default config in the config struct */
+	config->data_order       = USART_DATAORDER_LSB;
+	config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
+	config->parity           = USART_PARITY_NONE;
+	config->stopbits         = USART_STOPBITS_1;
+	config->character_size   = USART_CHARACTER_SIZE_8BIT;
+	config->baudrate         = 9600;
+	config->receiver_enable  = true;
+	config->transmitter_enable = true;
+	config->clock_polarity_inverted = false;
+	config->use_external_clock = false;
+	config->ext_clock_freq   = 0;
+	config->mux_setting      = USART_RX_1_TX_2_XCK_3;
+	config->run_in_standby   = false;
+	config->generator_source = GCLK_GENERATOR_0;
+	config->pinmux_pad0      = PINMUX_DEFAULT;
+	config->pinmux_pad1      = PINMUX_DEFAULT;
+	config->pinmux_pad2      = PINMUX_DEFAULT;
+	config->pinmux_pad3      = PINMUX_DEFAULT;
+#ifdef FEATURE_USART_OVER_SAMPLE
+	config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
+	config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+	config->lin_slave_enable      = false;
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	config->lin_node = LIN_INVALID_MODE;
+	config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
+	config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
+#endif
+
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+	config->immediate_buffer_overflow_notification  = false;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	config->start_frame_detection_enable            = false;
+#endif
+#ifdef FEATURE_USART_IRDA
+	config->encoding_format_enable                  = false;
+	config->receive_pulse_length                    = 19;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	config->iso7816_config.enabled                  = false;
+	config->iso7816_config.guard_time               = ISO7816_GUARD_TIME_2_BIT;
+	config->iso7816_config.protocol_t               = ISO7816_PROTOCOL_T_0;
+	config->iso7816_config.enable_inverse           = false;
+	config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
+	config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
+	config->iso7816_config.max_iterations           = 7;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+	config->collision_detection_enable              = false;
+#endif
+#ifdef FEATURE_USART_RS485
+	config->rs485_guard_time = RS485_GUARD_TIME_0_BIT;
+#endif
+}
+
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config);
+
+/**
+ * \brief Enable the module
+ *
+ * Enables the USART module.
+ *
+ * \param[in]  module  Pointer to USART software instance struct
+ */
+static inline void usart_enable(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+	/* Enable Global interrupt for module */
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Enable USART module */
+	usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disable module
+ *
+ * Disables the USART module.
+ *
+ * \param[in]  module  Pointer to USART software instance struct
+ */
+static inline void usart_disable(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+	/* Disable Global interrupt for module */
+	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Disable USART module */
+	usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Resets the USART module
+ *
+ * Disables and resets the USART module.
+ *
+ * \param[in]  module  Pointer to the USART software instance struct
+ */
+static inline void usart_reset(
+		const struct usart_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	usart_disable(module);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Reset module */
+	usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
+}
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_wait(
+		struct usart_module *const module,
+		const uint16_t tx_data);
+
+enum status_code usart_read_wait(
+		struct usart_module *const module,
+		uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_wait(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code usart_read_buffer_wait(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+/** @} */
+
+/**
+ * \name Enabling/Disabling Receiver and Transmitter
+ * @{
+ */
+
+/**
+ * \brief Enable Transceiver
+ *
+ * Enable the given transceiver. Either RX or TX.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transceiver type
+ */
+static inline void usart_enable_transceiver(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	switch (transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Enable RX */
+			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+			module->receiver_enabled = true;
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Enable TX */
+			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+			module->transmitter_enabled = true;
+			break;
+	}
+	_usart_wait_for_sync(module);
+}
+
+/**
+ * \brief Disable Transceiver
+ *
+ * Disable the given transceiver (RX or TX).
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transceiver type
+ */
+static inline void usart_disable_transceiver(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	switch (transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Disable RX */
+			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+			module->receiver_enabled = false;
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Disable TX */
+			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+			module->transmitter_enabled = false;
+			break;
+	}
+}
+
+/** @} */
+
+#ifdef FEATURE_USART_LIN_MASTER
+/**
+ * \name LIN Master Command and Status
+ * @{
+ */
+
+/**
+ * \brief Sending LIN command.
+ *
+ * Sending LIN command.
+ *
+ * \param[in]  module Pointer to USART software instance struct
+ * \param[in]  cmd  Cammand type
+ */
+static inline void lin_master_send_cmd(
+		struct usart_module *const module,
+		enum lin_master_cmd cmd)
+{
+	SercomUsart *const usart_hw = &(module->hw->USART);
+	_usart_wait_for_sync(module);
+	usart_hw->CTRLB.reg |= cmd;
+}
+
+/**
+ * \brief Get LIN transmission status
+ *
+ * Get LIN transmission status.
+ *
+ * \param[in]  module Pointer to USART software instance struct
+ *
+ * \return Status of LIN master transmission.
+ * \retval true   Data transmission completed
+ * \retval false  Transmission is ongoing
+ */
+static inline bool lin_master_transmission_status(struct usart_module *const module)
+{
+	SercomUsart *const usart_hw = &(module->hw->USART);
+	return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false);
+}
+
+/** @} */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver
+*
+* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms
+*
+* Below is a table listing the acronyms used in this module, along with their
+* intended meanings.
+*
+* <table>
+* <tr>
+* <th>Acronym</th>
+* <th>Description</th>
+* </tr>
+* <tr>
+* <td>SERCOM</td>
+* <td>Serial Communication Interface</td>
+* </tr>
+* <tr>
+* <td>USART</td>
+* <td>Universal Synchronous and Asynchronous Serial Receiver and Transmitter</td>
+* </tr>
+* <tr>
+* <td>LSB</td>
+* <td>Least Significant Bit</td>
+* </tr>
+* <tr>
+* <td>MSB</td>
+* <td>Most Significant Bit</td>
+* </tr>
+* <tr>
+* <td>DMA</td>
+* <td>Direct Memory Access</td>
+* </tr>
+* </table>
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies
+* This driver has the following dependencies:
+*
+* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+* - \ref asfdoc_sam0_system_clock_group "System clock configuration"
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_errata Errata
+* There are no errata related to this driver.
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_history Module History
+* An overview of the module history is presented in the table below, with
+* details on the enhancements and fixes made to the module since its first
+* release. The current version of this corresponds to the newest version in
+* the table.
+*
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added new feature as below:
+ *          \li ISO7816
+ *	</tr>
+ *	<tr>
+ *		<td>Added new features as below:
+ *          \li LIN master
+ *          \li RS485
+ *	</tr>
+ *	<tr>
+ *		<td>Added new features as below:
+ *          \li Oversample
+ *          \li Buffer overflow notification
+ *          \li Irda
+ *          \li Lin slave
+ *          \li Start frame detection
+ *          \li Hardware flow control
+ *          \li Collision detection
+ *          \li DMA support </td>
+ *	</tr>
+ *	<tr>
+ *		<td>\li Added new \c transmitter_enable and \c receiver_enable Boolean
+ *              values to \c struct usart_config
+ *          \li Altered \c usart_write_* and usart_read_* functions to abort with
+ *              an error code if the relevant transceiver is not enabled
+ *          \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()
+ *              not aborting correctly when a timeout condition occurs</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+*/
+
+/**
+ * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_sercom_usart_basic_use_case
+ * \if USART_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_usart_callback_use_case
+ * \endif
+ * - \subpage asfdoc_sam0_sercom_usart_dma_use_case
+ * - \subpage asfdoc_sam0_sercom_usart_lin_use_case
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings
+ *
+ * The following lists the possible internal SERCOM module pad function
+ * assignments, for the four SERCOM pads when in USART mode. Note that this is
+ * in addition to the physical GPIO pin MUX of the device, and can be used in
+ * conjunction to optimize the serial data pin-out.
+ *
+ * When TX and RX are connected to the same pin, the USART will operate in
+ * half-duplex mode if both one transmitter and several receivers are enabled.
+ *
+ * \note When RX and XCK are connected to the same pin, the receiver must not
+ *       be enabled if the USART is configured to use an external clock.
+ *
+ *
+ * <table>
+ *		<tr>
+ *			<th>MUX/Pad</th>
+ *			<th>PAD 0</th>
+ *			<th>PAD 1</th>
+ *			<th>PAD 2</th>
+ *			<th>PAD 3</th>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_0_TX_0_XCK_1</td>
+ *			<td>TX / RX</td>
+ *			<td>XCK</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_0_TX_2_XCK_3</td>
+ *			<td>RX</td>
+ *			<td>-</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_1_TX_0_XCK_1</td>
+ *			<td>TX</td>
+ *			<td>RX / XCK</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_1_TX_2_XCK_3</td>
+ *			<td>-</td>
+ *			<td>RX</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_2_TX_0_XCK_1</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *			<td>RX</td>
+ *			<td>-</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_2_TX_2_XCK_3</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *			<td>TX / RX</td>
+ *			<td>XCK</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_3_TX_0_XCK_1</td>
+ *			<td>TX</td>
+ *			<td>XCK</td>
+ *			<td>-</td>
+ *			<td>RX</td>
+ *		</tr>
+ *		<tr>
+ *			<td>RX_3_TX_2_XCK_3</td>
+ *			<td>-</td>
+ *			<td>-</td>
+ *			<td>TX</td>
+ *			<td>RX / XCK</td>
+ *		</tr>
+ * </table>
+ *
+ * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAMR30/R34 and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118C</td>
+ *		<td>10/2013</td>
+ *		<td>Replaced the pad multiplexing documentation with a condensed table</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42118A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+#endif /* USART_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
index 151dba2..39df7d7 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c
@@ -1,656 +1,656 @@
-/**
- * \file
- *
- * \brief SAM SERCOM USART Asynchronous Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "usart_interrupt.h"
-
-/**
- * \internal
- * Asynchronous write of a buffer with a given length
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[in]  tx_data  Pointer to data to be transmitted
- * \param[in]  length   Length of data buffer
- *
- */
-enum status_code _usart_write_buffer(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(tx_data);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	system_interrupt_enter_critical_section();
-
-	/* Check if the USART transmitter is busy */
-	if (module->remaining_tx_buffer_length > 0) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
-
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
-
-	system_interrupt_leave_critical_section();
-
-	module->tx_buffer_ptr              = tx_data;
-	module->tx_status                  = STATUS_BUSY;
-
-	/* Enable the Data Register Empty Interrupt */
-	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
-
-	return STATUS_OK;
-}
-
-/**
- * \internal
- * Asynchronous read of a buffer with a given length
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[in]  rx_data  Pointer to data to be received
- * \param[in]  length   Length of data buffer
- *
- */
-enum status_code _usart_read_buffer(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(rx_data);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	system_interrupt_enter_critical_section();
-
-	/* Check if the USART receiver is busy */
-	if (module->remaining_rx_buffer_length > 0) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
-
-	/* Set length for the buffer and the pointer, and let
-	 * the interrupt handler do the rest */
-	module->remaining_rx_buffer_length = length;
-
-	system_interrupt_leave_critical_section();
-
-	module->rx_buffer_ptr              = rx_data;
-	module->rx_status                  = STATUS_BUSY;
-
-	/* Enable the RX Complete Interrupt */
-	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
-
-#ifdef FEATURE_USART_LIN_SLAVE
-	/* Enable the break character is received Interrupt */
-	if(module->lin_slave_enabled) {
-		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
-	}
-#endif
-
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	/* Enable a start condition is detected Interrupt */
-	if(module->start_frame_detection_enabled) {
-		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
-	}
-#endif
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Registers a callback
- *
- * Registers a callback function, which is implemented by the user.
- *
- * \note The callback must be enabled by \ref usart_enable_callback
- *       in order for the interrupt handler to call it when the conditions for
- *       the callback type are met.
- *
- * \param[in]  module         Pointer to USART software instance struct
- * \param[in]  callback_func  Pointer to callback function
- * \param[in]  callback_type  Callback type given by an enum
- *
- */
-void usart_register_callback(
-		struct usart_module *const module,
-		usart_callback_t callback_func,
-		enum usart_callback callback_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
-
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
-
-	/* Set the bit corresponding to the callback_type */
-	module->callback_reg_mask |= (1 << callback_type);
-}
-
-/**
- * \brief Unregisters a callback
- *
- * Unregisters a callback function, which is implemented by the user.
- *
- * \param[in,out]  module         Pointer to USART software instance struct
- * \param[in]      callback_type  Callback type given by an enum
- *
- */
-void usart_unregister_callback(
-		struct usart_module *const module,
-		enum usart_callback callback_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
-
-	/* Clear the bit corresponding to the callback_type */
-	module->callback_reg_mask &= ~(1 << callback_type);
-}
-
-/**
- * \brief Asynchronous write a single char
- *
- * Sets up the driver to write the data given. If registered and enabled,
- * a callback function will be called when the transmit is completed.
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[in]  tx_data  Data to transfer
- *
- * \returns Status of the operation.
- * \retval STATUS_OK         If operation was completed
- * \retval STATUS_BUSY       If operation was not completed, due to the
- *                           USART module being busy
- * \retval STATUS_ERR_DENIED If the transmitter is not enabled
- */
-enum status_code usart_write_job(
-		struct usart_module *const module,
-		const uint16_t *tx_data)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(tx_data);
-
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Call internal write buffer function with length 1 */
-	return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
-}
-
-/**
- * \brief Asynchronous read a single char
- *
- * Sets up the driver to read data from the USART module to the data
- * pointer given. If registered and enabled, a callback will be called
- * when the receiving is completed.
- *
- * \param[in]   module   Pointer to USART software instance struct
- * \param[out]  rx_data  Pointer to where received data should be put
- *
- * \returns Status of the operation.
- * \retval  STATUS_OK    If operation was completed
- * \retval  STATUS_BUSY  If operation was not completed
- */
-enum status_code usart_read_job(
-		struct usart_module *const module,
-		uint16_t *const rx_data)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	/* Call internal read buffer function with length 1 */
-	return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
-}
-
-/**
- * \brief Asynchronous buffer write
- *
- * Sets up the driver to write a given buffer over the USART. If registered and
- * enabled, a callback function will be called.
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[in]  tx_data  Pointer do data buffer to transmit
- * \param[in]  length   Length of the data to transmit
- *
- * \note If using 9-bit data, the array that *tx_data point to should be defined 
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
- *       is an address pointer, the highest byte is not discarded. For example:
- *   \code
-          #define TX_LEN 3
-          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
-          usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
-    \endcode
- *
- * \returns Status of the operation.
- * \retval STATUS_OK              If operation was completed successfully.
- * \retval STATUS_BUSY            If operation was not completed, due to the
- *                                USART module being busy
- * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
- *                                arguments
- * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
- */
-enum status_code usart_write_buffer_job(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(tx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Issue internal asynchronous write */
-	return _usart_write_buffer(module, tx_data, length);
-}
-
-/**
- * \brief Asynchronous buffer read
- *
- * Sets up the driver to read from the USART to a given buffer. If registered
- * and enabled, a callback function will be called.
- *
- * \param[in]  module   Pointer to USART software instance struct
- * \param[out] rx_data  Pointer to data buffer to receive
- * \param[in]  length   Data buffer length
- *
- * \note If using 9-bit data, the array that *rx_data point to should be defined
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
- *       is an address pointer, the highest byte is not discarded. For example:
- *   \code
-           #define RX_LEN 3
-           uint16_t rx_buf[RX_LEN] = {0x0,};
-           usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
-    \endcode
- *
- * \returns Status of the operation.
- * \retval STATUS_OK              If operation was completed
- * \retval STATUS_BUSY            If operation was not completed, due to the
- *                                USART module being busy
- * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
- *                                arguments
- * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
- */
-enum status_code usart_read_buffer_job(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Issue internal asynchronous read */
-	return _usart_read_buffer(module, rx_data, length);
-}
-
-/**
- * \brief Cancels ongoing read/write operation
- *
- * Cancels the ongoing read/write operation modifying parameters in the
- * USART software struct.
- *
- * \param[in]  module            Pointer to USART software instance struct
- * \param[in]  transceiver_type  Transfer type to cancel
- */
-void usart_abort_job(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	switch(transceiver_type) {
-		case USART_TRANSCEIVER_RX:
-			/* Clear the interrupt flag in order to prevent the receive
-			 * complete callback to fire */
-			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
-
-			/* Clear the software reception buffer */
-			module->remaining_rx_buffer_length = 0;
-
-			break;
-
-		case USART_TRANSCEIVER_TX:
-			/* Clear the interrupt flag in order to prevent the receive
-			 * complete callback to fire */
-			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
-
-			/* Clear the software reception buffer */
-			module->remaining_tx_buffer_length = 0;
-
-			break;
-	}
-}
-
-/**
- * \brief Get status from the ongoing or last asynchronous transfer operation
- *
- * Returns the error from a given ongoing or last asynchronous transfer operation.
- * Either from a read or write transfer.
- *
- * \param[in]  module            Pointer to USART software instance struct
- * \param[in]  transceiver_type  Transfer type to check
-  *
- * \return Status of the given job.
- * \retval STATUS_OK               No error occurred during the last transfer
- * \retval STATUS_BUSY             A transfer is ongoing
- * \retval STATUS_ERR_BAD_DATA     The last operation was aborted due to a
- *                                 parity error. The transfer could be affected
- *                                 by external noise
- * \retval STATUS_ERR_BAD_FORMAT   The last operation was aborted due to a
- *                                 frame error
- * \retval STATUS_ERR_OVERFLOW     The last operation was aborted due to a
- *                                 buffer overflow
- * \retval STATUS_ERR_INVALID_ARG  An invalid transceiver enum given
- */
-enum status_code usart_get_job_status(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Variable for status code */
-	enum status_code status_code;
-
-	switch(transceiver_type) {
-	case USART_TRANSCEIVER_RX:
-			status_code = module->rx_status;
-			break;
-
-	case USART_TRANSCEIVER_TX:
-			status_code = module->tx_status;
-			break;
-
-	default:
-			status_code = STATUS_ERR_INVALID_ARG;
-			break;
-	}
-
-	return status_code;
-}
-
-/**
- * \internal
- * Handles interrupts as they occur, and it will run callback functions
- * which are registered and enabled.
- *
- * \param[in]  instance  ID of the SERCOM instance calling the interrupt
- *                       handler.
- */
-void _usart_interrupt_handler(
-		uint8_t instance)
-{
-	/* Temporary variables */
-	uint16_t interrupt_status;
-	uint16_t callback_status;
-	uint8_t error_code;
-
-
-	/* Get device instance from the look-up table */
-	struct usart_module *module
-		= (struct usart_module *)_sercom_instances[instance];
-
-	/* Pointer to the hardware module instance */
-	SercomUsart *const usart_hw
-		= &(module->hw->USART);
-
-	/* Wait for the synchronization to complete */
-	_usart_wait_for_sync(module);
-
-	/* Read and mask interrupt flag register */
-	interrupt_status = usart_hw->INTFLAG.reg;
-	interrupt_status &= usart_hw->INTENSET.reg;
-	callback_status = module->callback_reg_mask &
-			module->callback_enable_mask;
-
-	/* Check if a DATA READY interrupt has occurred,
-	 * and if there is more to transfer */
-	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
-		if (module->remaining_tx_buffer_length) {
-			/* Write value will be at least 8-bits long */
-			uint16_t data_to_send = *(module->tx_buffer_ptr);
-			/* Increment 8-bit pointer */
-			(module->tx_buffer_ptr)++;
-
-			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-				data_to_send |= (*(module->tx_buffer_ptr) << 8);
-				/* Increment 8-bit pointer */
-				(module->tx_buffer_ptr)++;
-			}
-			/* Write the data to send */
-			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
-
-			if (--(module->remaining_tx_buffer_length) == 0) {
-				/* Disable the Data Register Empty Interrupt */
-				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
-				/* Enable Transmission Complete interrupt */
-				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
-
-			}
-		} else {
-			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
-		}
-	}
-
-	/* Check if the Transmission Complete interrupt has occurred and
-	 * that the transmit buffer is empty */
-	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
-
-		/* Disable TX Complete Interrupt, and set STATUS_OK */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
-		module->tx_status = STATUS_OK;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
-			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
-		}
-	}
-
-	/* Check if the Receive Complete interrupt has occurred, and that
-	 * there's more data to receive */
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
-
-		if (module->remaining_rx_buffer_length) {
-			/* Read out the status code and mask away all but the 4 LSBs*/
-			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
-#if !SAMD20
-			/* CTS status should not be considered as an error */
-			if(error_code & SERCOM_USART_STATUS_CTS) {
-				error_code &= ~SERCOM_USART_STATUS_CTS;
-			}
-#endif
-#ifdef FEATURE_USART_LIN_MASTER
-			/* TXE status should not be considered as an error */
-			if(error_code & SERCOM_USART_STATUS_TXE) {
-				error_code &= ~SERCOM_USART_STATUS_TXE;
-			}
-#endif
-			/* Check if an error has occurred during the receiving */
-			if (error_code) {
-				/* Check which error occurred */
-				if (error_code & SERCOM_USART_STATUS_FERR) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_BAD_FORMAT;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_OVERFLOW;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-				} else if (error_code & SERCOM_USART_STATUS_PERR) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_BAD_DATA;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
-				}
-#ifdef FEATURE_USART_LIN_SLAVE
-				else if (error_code & SERCOM_USART_STATUS_ISF) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_PROTOCOL;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
-				}
-#endif
-#ifdef FEATURE_USART_COLLISION_DECTION
-				else if (error_code & SERCOM_USART_STATUS_COLL) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_PACKET_COLLISION;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-				}
-#endif
-
-				/* Run callback if registered and enabled */
-				if (callback_status
-						& (1 << USART_CALLBACK_ERROR)) {
-					(*(module->callback[USART_CALLBACK_ERROR]))(module);
-				}
-
-			} else {
-
-				/* Read current packet from DATA register,
-				 * increment buffer pointer and decrement buffer length */
-				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
-
-				/* Read value will be at least 8-bits long */
-				*(module->rx_buffer_ptr) = received_data;
-				/* Increment 8-bit pointer */
-				module->rx_buffer_ptr += 1;
-
-				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-					/* 9-bit data, write next received byte to the buffer */
-					*(module->rx_buffer_ptr) = (received_data >> 8);
-					/* Increment 8-bit pointer */
-					module->rx_buffer_ptr += 1;
-				}
-
-				/* Check if the last character have been received */
-				if(--(module->remaining_rx_buffer_length) == 0) {
-					/* Disable RX Complete Interrupt,
-					 * and set STATUS_OK */
-					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
-					module->rx_status = STATUS_OK;
-
-					/* Run callback if registered and enabled */
-					if (callback_status
-							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
-						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
-					}
-				}
-			}
-		} else {
-			/* This should not happen. Disable Receive Complete interrupt. */
-			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
-		}
-	}
-
-#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
-			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
-		}
-	}
-#endif
-
-#ifdef FEATURE_USART_LIN_SLAVE
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
-			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
-		}
-	}
-#endif
-
-#ifdef FEATURE_USART_START_FRAME_DECTION
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
-			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
-		}
-	}
-#endif
-}
-
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "usart_interrupt.h"
+
+/**
+ * \internal
+ * Asynchronous write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART transmitter is busy */
+	if (module->remaining_tx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->tx_buffer_ptr              = tx_data;
+	module->tx_status                  = STATUS_BUSY;
+
+	/* Enable the Data Register Empty Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Asynchronous read of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(rx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART receiver is busy */
+	if (module->remaining_rx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->rx_buffer_ptr              = rx_data;
+	module->rx_status                  = STATUS_BUSY;
+
+	/* Enable the RX Complete Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	/* Enable the break character is received Interrupt */
+	if(module->lin_slave_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/* Enable a start condition is detected Interrupt */
+	if(module->start_frame_detection_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function, which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usart_enable_callback
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function, which is implemented by the user.
+ *
+ * \param[in,out]  module         Pointer to USART software instance struct
+ * \param[in]      callback_type  Callback type given by an enum
+ *
+ */
+void usart_unregister_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Asynchronous write a single char
+ *
+ * Sets up the driver to write the data given. If registered and enabled,
+ * a callback function will be called when the transmit is completed.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK         If operation was completed
+ * \retval STATUS_BUSY       If operation was not completed, due to the
+ *                           USART module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Call internal write buffer function with length 1 */
+	return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
+}
+
+/**
+ * \brief Asynchronous read a single char
+ *
+ * Sets up the driver to read data from the USART module to the data
+ * pointer given. If registered and enabled, a callback will be called
+ * when the receiving is completed.
+ *
+ * \param[in]   module   Pointer to USART software instance struct
+ * \param[out]  rx_data  Pointer to where received data should be put
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK    If operation was completed
+ * \retval  STATUS_BUSY  If operation was not completed
+ */
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	/* Call internal read buffer function with length 1 */
+	return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write a given buffer over the USART. If registered and
+ * enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer do data buffer to transmit
+ * \param[in]  length   Length of the data to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed successfully.
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous write */
+	return _usart_write_buffer(module, tx_data, length);
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the USART to a given buffer. If registered
+ * and enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+           #define RX_LEN 3
+           uint16_t rx_buf[RX_LEN] = {0x0,};
+           usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous read */
+	return _usart_read_buffer(module, rx_data, length);
+}
+
+/**
+ * \brief Cancels ongoing read/write operation
+ *
+ * Cancels the ongoing read/write operation modifying parameters in the
+ * USART software struct.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to cancel
+ */
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	switch(transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_rx_buffer_length = 0;
+
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_tx_buffer_length = 0;
+
+			break;
+	}
+}
+
+/**
+ * \brief Get status from the ongoing or last asynchronous transfer operation
+ *
+ * Returns the error from a given ongoing or last asynchronous transfer operation.
+ * Either from a read or write transfer.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to check
+  *
+ * \return Status of the given job.
+ * \retval STATUS_OK               No error occurred during the last transfer
+ * \retval STATUS_BUSY             A transfer is ongoing
+ * \retval STATUS_ERR_BAD_DATA     The last operation was aborted due to a
+ *                                 parity error. The transfer could be affected
+ *                                 by external noise
+ * \retval STATUS_ERR_BAD_FORMAT   The last operation was aborted due to a
+ *                                 frame error
+ * \retval STATUS_ERR_OVERFLOW     The last operation was aborted due to a
+ *                                 buffer overflow
+ * \retval STATUS_ERR_INVALID_ARG  An invalid transceiver enum given
+ */
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Variable for status code */
+	enum status_code status_code;
+
+	switch(transceiver_type) {
+	case USART_TRANSCEIVER_RX:
+			status_code = module->rx_status;
+			break;
+
+	case USART_TRANSCEIVER_TX:
+			status_code = module->tx_status;
+			break;
+
+	default:
+			status_code = STATUS_ERR_INVALID_ARG;
+			break;
+	}
+
+	return status_code;
+}
+
+/**
+ * \internal
+ * Handles interrupts as they occur, and it will run callback functions
+ * which are registered and enabled.
+ *
+ * \param[in]  instance  ID of the SERCOM instance calling the interrupt
+ *                       handler.
+ */
+void _usart_interrupt_handler(
+		uint8_t instance)
+{
+	/* Temporary variables */
+	uint16_t interrupt_status;
+	uint16_t callback_status;
+	uint8_t error_code;
+
+
+	/* Get device instance from the look-up table */
+	struct usart_module *module
+		= (struct usart_module *)_sercom_instances[instance];
+
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw
+		= &(module->hw->USART);
+
+	/* Wait for the synchronization to complete */
+	_usart_wait_for_sync(module);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+	interrupt_status &= usart_hw->INTENSET.reg;
+	callback_status = module->callback_reg_mask &
+			module->callback_enable_mask;
+
+	/* Check if a DATA READY interrupt has occurred,
+	 * and if there is more to transfer */
+	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+		if (module->remaining_tx_buffer_length) {
+			/* Write value will be at least 8-bits long */
+			uint16_t data_to_send = *(module->tx_buffer_ptr);
+			/* Increment 8-bit pointer */
+			(module->tx_buffer_ptr)++;
+
+			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+				data_to_send |= (*(module->tx_buffer_ptr) << 8);
+				/* Increment 8-bit pointer */
+				(module->tx_buffer_ptr)++;
+			}
+			/* Write the data to send */
+			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+
+			if (--(module->remaining_tx_buffer_length) == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+				/* Enable Transmission Complete interrupt */
+				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+
+			}
+		} else {
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+		}
+	}
+
+	/* Check if the Transmission Complete interrupt has occurred and
+	 * that the transmit buffer is empty */
+	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+
+		/* Disable TX Complete Interrupt, and set STATUS_OK */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+		module->tx_status = STATUS_OK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
+			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+		}
+	}
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+
+		if (module->remaining_rx_buffer_length) {
+			/* Read out the status code and mask away all but the 4 LSBs*/
+			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+			/* CTS status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_CTS) {
+				error_code &= ~SERCOM_USART_STATUS_CTS;
+			}
+#endif
+#ifdef FEATURE_USART_LIN_MASTER
+			/* TXE status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_TXE) {
+				error_code &= ~SERCOM_USART_STATUS_TXE;
+			}
+#endif
+			/* Check if an error has occurred during the receiving */
+			if (error_code) {
+				/* Check which error occurred */
+				if (error_code & SERCOM_USART_STATUS_FERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_FORMAT;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_OVERFLOW;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+				} else if (error_code & SERCOM_USART_STATUS_PERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_DATA;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+				}
+#ifdef FEATURE_USART_LIN_SLAVE
+				else if (error_code & SERCOM_USART_STATUS_ISF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PROTOCOL;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+				}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+				else if (error_code & SERCOM_USART_STATUS_COLL) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PACKET_COLLISION;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+				}
+#endif
+
+				/* Run callback if registered and enabled */
+				if (callback_status
+						& (1 << USART_CALLBACK_ERROR)) {
+					(*(module->callback[USART_CALLBACK_ERROR]))(module);
+				}
+
+			} else {
+
+				/* Read current packet from DATA register,
+				 * increment buffer pointer and decrement buffer length */
+				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+
+				/* Read value will be at least 8-bits long */
+				*(module->rx_buffer_ptr) = received_data;
+				/* Increment 8-bit pointer */
+				module->rx_buffer_ptr += 1;
+
+				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+					/* 9-bit data, write next received byte to the buffer */
+					*(module->rx_buffer_ptr) = (received_data >> 8);
+					/* Increment 8-bit pointer */
+					module->rx_buffer_ptr += 1;
+				}
+
+				/* Check if the last character have been received */
+				if(--(module->remaining_rx_buffer_length) == 0) {
+					/* Disable RX Complete Interrupt,
+					 * and set STATUS_OK */
+					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+					module->rx_status = STATUS_OK;
+
+					/* Run callback if registered and enabled */
+					if (callback_status
+							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
+						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+					}
+				}
+			}
+		} else {
+			/* This should not happen. Disable Receive Complete interrupt. */
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+		}
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
+			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+		}
+	}
+#endif
+}
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
index 9dcbbae..5026372 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h
@@ -1,167 +1,167 @@
-/**
- * \file
- *
- * \brief SAM SERCOM USART Asynchronous Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef USART_INTERRUPT_H_INCLUDED
-#define USART_INTERRUPT_H_INCLUDED
-
-#include "usart.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(__DOXYGEN__)
-enum status_code _usart_write_buffer(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
-
-enum status_code _usart_read_buffer(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length);
-
-void _usart_interrupt_handler(
-		uint8_t instance);
-#endif
-
-/**
- * \addtogroup asfdoc_sam0_sercom_usart_group
- *
- * @{
- */
-
-/**
- * \name Callback Management
- * @{
- */
-void usart_register_callback(
-		struct usart_module *const module,
-		usart_callback_t callback_func,
-		enum usart_callback callback_type);
-
-void usart_unregister_callback(
-		struct usart_module *module,
-		enum usart_callback callback_type);
-
-/**
- * \brief Enables callback
- *
- * Enables the callback function registered by the \ref usart_register_callback.
- * The callback function will be called from the interrupt handler when the
- * conditions for the callback type are met.
- *
- * \param[in]  module         Pointer to USART software instance struct
- * \param[in]  callback_type  Callback type given by an enum
- */
-static inline void usart_enable_callback(
-		struct usart_module *const module,
-		enum usart_callback callback_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Enable callback */
-	module->callback_enable_mask |= (1 << callback_type);
-
-}
-
-/**
- * \brief Disable callback
- *
- * Disables the callback function registered by the \ref usart_register_callback,
- * and the callback will not be called from the interrupt routine.
- *
- * \param[in]  module         Pointer to USART software instance struct
- * \param[in]  callback_type  Callback type given by an enum
- */
-static inline void usart_disable_callback(
-		struct usart_module *const module,
-		enum usart_callback callback_type)
-{
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Disable callback */
-	module->callback_enable_mask &= ~(1 << callback_type);
-}
-
-/**
- * @}
- */
-
-/**
- * \name Writing and Reading
- * @{
- */
-enum status_code usart_write_job(
-		struct usart_module *const module,
-		const uint16_t *tx_data);
-
-enum status_code usart_read_job(
-		struct usart_module *const module,
-		uint16_t *const rx_data);
-
-enum status_code usart_write_buffer_job(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
-
-enum status_code usart_read_buffer_job(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length);
-
-void usart_abort_job(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type);
-
-enum status_code usart_get_job_status(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* USART_INTERRUPT_H_INCLUDED */
-
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef USART_INTERRUPT_H_INCLUDED
+#define USART_INTERRUPT_H_INCLUDED
+
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void _usart_interrupt_handler(
+		uint8_t instance);
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_usart_group
+ *
+ * @{
+ */
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type);
+
+void usart_unregister_callback(
+		struct usart_module *module,
+		enum usart_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_enable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->callback_enable_mask |= (1 << callback_type);
+
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_disable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->callback_enable_mask &= ~(1 << callback_type);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data);
+
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USART_INTERRUPT_H_INCLUDED */
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock.h
index 9abd168..f75b951 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock.h
@@ -1,43 +1,43 @@
-/**
- * \file
- *
- * \brief SAM Clock Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SYSTEM_CLOCK_H_INCLUDED
-#define SYSTEM_CLOCK_H_INCLUDED
-
-#include <compiler.h>
-#include <gclk.h>
-#include <clock_feature.h>
-
-#endif /* SYSTEM_CLOCK_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_CLOCK_H_INCLUDED
+#define SYSTEM_CLOCK_H_INCLUDED
+
+#include <compiler.h>
+#include <gclk.h>
+#include <clock_feature.h>
+
+#endif /* SYSTEM_CLOCK_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
index ecbf122..638437a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
@@ -1,1031 +1,1031 @@
-/**
- * \file
- *
- * \brief SAM D21/R21/DA/HA Clock Driver
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include <clock.h>
-#include <conf_clocks.h>
-#include <system.h>
-
-#ifndef SYSCTRL_FUSES_OSC32K_ADDR
-#if (SAMR21) || (SAMD) || (SAMHA1) || (SAMHA0)
-#  define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR
-#  define SYSCTRL_FUSES_OSC32K_Pos  FUSES_OSC32K_CAL_Pos
-#elif (SAML21)
-#  define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4
-#  define SYSCTRL_FUSES_OSC32K_Pos  6
-
-#else
-#  define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
-#  define SYSCTRL_FUSES_OSC32K_Pos  SYSCTRL_FUSES_OSC32K_CAL_Pos
-#endif
-#endif
-
-/**
- * \internal
- * \brief DFLL-specific data container.
- */
-struct _system_clock_dfll_config {
-	uint32_t control;
-	uint32_t val;
-	uint32_t mul;
-};
-
-/**
- * \internal
- * \brief DPLL-specific data container.
- */
-struct _system_clock_dpll_config {
-	uint32_t frequency;
-};
-
-
-/**
- * \internal
- * \brief XOSC-specific data container.
- */
-struct _system_clock_xosc_config {
-	uint32_t frequency;
-};
-
-/**
- * \internal
- * \brief System clock module data container.
- */
-struct _system_clock_module {
-	volatile struct _system_clock_dfll_config dfll;
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	volatile struct _system_clock_dpll_config dpll;
-#endif
-
-	volatile struct _system_clock_xosc_config xosc;
-	volatile struct _system_clock_xosc_config xosc32k;
-};
-
-/**
- * \internal
- * \brief Internal module instance to cache configuration values.
- */
-static struct _system_clock_module _system_clock_inst = {
-		.dfll = {
-			.control     = 0,
-			.val     = 0,
-			.mul     = 0,
-		},
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-		.dpll = {
-			.frequency   = 0,
-		},
-#endif
-		.xosc = {
-			.frequency   = 0,
-		},
-		.xosc32k = {
-			.frequency   = 0,
-		},
-	};
-
-/**
- * \internal
- * \brief Wait for sync to the DFLL control registers.
- */
-static inline void _system_dfll_wait_for_sync(void)
-{
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
-		/* Wait for DFLL sync */
-	}
-}
-
-/**
- * \internal
- * \brief Wait for sync to the OSC32K control registers.
- */
-static inline void _system_osc32k_wait_for_sync(void)
-{
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
-		/* Wait for OSC32K sync */
-	}
-}
-
-static inline void _system_clock_source_dfll_set_config_errata_9905(void)
-{
-
-	/* Disable ONDEMAND mode while writing configurations */
-	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
-	_system_dfll_wait_for_sync();
-
-	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
-	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
-
-	/* Write full configuration to DFLL control register */
-	SYSCTRL->DFLLCTRL.reg = 0;
-	_system_dfll_wait_for_sync();
-	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
-}
-
-/**
- * \brief Retrieve the frequency of a clock source.
- *
- * Determines the current operating frequency of a given clock source.
- *
- * \param[in] clock_source  Clock source to get the frequency
- *
- * \returns Frequency of the given clock source, in Hz.
- */
-uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clock_source)
-{
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		return _system_clock_inst.xosc.frequency;
-
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		return 32768UL;
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		return 32768UL;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		return _system_clock_inst.xosc32k.frequency;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-
-		/* Check if the DFLL has been configured */
-		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
-			return 0;
-
-		/* Make sure that the DFLL module is ready */
-		_system_dfll_wait_for_sync();
-
-		/* Check if operating in closed loop (USB) mode */
-		switch(_system_clock_inst.dfll.control &
-				(SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_USBCRM)) {
-		case SYSCTRL_DFLLCTRL_MODE:
-			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
-					(_system_clock_inst.dfll.mul & 0xffff);
-		default:
-			return 48000000UL;
-		}
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
-			return 0;
-		}
-
-		return _system_clock_inst.dpll.frequency;
-#endif
-
-	default:
-		return 0;
-	}
-}
-
-/**
- * \brief Configure the internal OSC8M oscillator clock source.
- *
- * Configures the 8MHz (nominal) internal RC oscillator with the given
- * configuration settings.
- *
- * \param[in] config  OSC8M configuration structure containing the new config
- */
-void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config)
-{
-	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
-
-	/* Use temporary struct to reduce register access */
-	temp.bit.PRESC    = config->prescaler;
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-
-	SYSCTRL->OSC8M = temp;
-}
-
-/**
- * \brief Configure the internal OSC32K oscillator clock source.
- *
- * Configures the 32KHz (nominal) internal RC oscillator with the given
- * configuration settings.
- *
- * \param[in] config  OSC32K configuration structure containing the new config
- */
-void system_clock_source_osc32k_set_config(
-		struct system_clock_source_osc32k_config *const config)
-{
-	SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
-
-	/* Update settings via a temporary struct to reduce register access */
-	temp.bit.EN1K     = config->enable_1khz_output;
-	temp.bit.EN32K    = config->enable_32khz_output;
-	temp.bit.STARTUP  = config->startup_time;
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-	temp.bit.WRTLOCK  = config->write_once;
-
-	SYSCTRL->OSC32K  = temp;
-}
-
-/**
- * \brief Configure the external oscillator clock source.
- *
- * Configures the external oscillator clock source with the given configuration
- * settings.
- *
- * \param[in] config  External oscillator configuration structure containing
- *                    the new config
- */
-void system_clock_source_xosc_set_config(
-		struct system_clock_source_xosc_config *const config)
-{
-	SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
-
-	temp.bit.STARTUP = config->startup_time;
-
-	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
-		temp.bit.XTALEN = 1;
-	} else {
-		temp.bit.XTALEN = 0;
-	}
-
-	temp.bit.AMPGC = config->auto_gain_control;
-
-	/* Set gain */
-	if (config->frequency <= 2000000) {
-		temp.bit.GAIN = 0;
-	} else if (config->frequency <= 4000000) {
-		temp.bit.GAIN = 1;
-	} else if (config->frequency <= 8000000) {
-		temp.bit.GAIN = 2;
-	} else if (config->frequency <= 16000000) {
-		temp.bit.GAIN = 3;
-	} else if (config->frequency <= 32000000) {
-		temp.bit.GAIN = 4;
-	}
-
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-
-	/* Store XOSC frequency for internal use */
-	_system_clock_inst.xosc.frequency = config->frequency;
-
-	SYSCTRL->XOSC = temp;
-}
-
-/**
- * \brief Configure the XOSC32K external 32KHz oscillator clock source.
- *
- * Configures the external 32KHz oscillator clock source with the given
- * configuration settings.
- *
- * \param[in] config  XOSC32K configuration structure containing the new config
- */
-void system_clock_source_xosc32k_set_config(
-		struct system_clock_source_xosc32k_config *const config)
-{
-	SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
-
-	temp.bit.STARTUP = config->startup_time;
-
-	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
-		temp.bit.XTALEN = 1;
-	} else {
-		temp.bit.XTALEN = 0;
-	}
-
-	temp.bit.AAMPEN = config->auto_gain_control;
-	temp.bit.EN1K = config->enable_1khz_output;
-	temp.bit.EN32K = config->enable_32khz_output;
-
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-	temp.bit.WRTLOCK  = config->write_once;
-
-	/* Cache the new frequency in case the user needs to check the current
-	 * operating frequency later */
-	_system_clock_inst.xosc32k.frequency = config->frequency;
-
-	SYSCTRL->XOSC32K = temp;
-}
-
-/**
- * \brief Configure the DFLL clock source.
- *
- * Configures the Digital Frequency Locked Loop clock source with the given
- * configuration settings.
- *
- * \note The DFLL will be running when this function returns, as the DFLL module
- *       needs to be enabled in order to perform the module configuration.
- *
- * \param[in] config  DFLL configuration structure containing the new config
- */
-void system_clock_source_dfll_set_config(
-		struct system_clock_source_dfll_config *const config)
-{
-	_system_clock_inst.dfll.val =
-			SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
-			SYSCTRL_DFLLVAL_FINE(config->fine_value);
-
-	_system_clock_inst.dfll.control =
-			(uint32_t)config->wakeup_lock     |
-			(uint32_t)config->stable_tracking |
-			(uint32_t)config->quick_lock      |
-			(uint32_t)config->chill_cycle     |
-			((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
-
-	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-
-		_system_clock_inst.dfll.mul =
-				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
-				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
-				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
-
-		/* Enable the closed loop mode */
-		_system_clock_inst.dfll.control |= config->loop_mode;
-	}
-	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
-
-		_system_clock_inst.dfll.mul =
-				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
-				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
-				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
-
-		/* Enable the USB recovery mode */
-		_system_clock_inst.dfll.control |= config->loop_mode |
-				SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_BPLCKC;
-	}
-}
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-/**
- * \brief Configure the DPLL clock source.
- *
- * Configures the Digital Phase-Locked Loop clock source with the given
- * configuration settings.
- *
- * \note The DPLL will be running when this function returns, as the DPLL module
- *       needs to be enabled in order to perform the module configuration.
- *
- * \param[in] config  DPLL configuration structure containing the new config
- */
-void system_clock_source_dpll_set_config(
-		struct system_clock_source_dpll_config *const config)
-{
-
-	uint32_t tmpldr;
-	uint8_t  tmpldrfrac;
-	uint32_t refclk;
-
-	refclk = config->reference_frequency;
-
-	/* Only reference clock REF1 can be divided */
-	if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
-		refclk = refclk / (2 * (config->reference_divider + 1));
-	}
-
-	/* Calculate LDRFRAC and LDR */
-	tmpldr = (config->output_frequency << 4) / refclk;
-	tmpldrfrac = tmpldr & 0x0f;
-	tmpldr = (tmpldr >> 4) - 1;
-
-	SYSCTRL->DPLLCTRLA.reg =
-			((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
-			((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
-
-	SYSCTRL->DPLLRATIO.reg =
-			SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
-			SYSCTRL_DPLLRATIO_LDR(tmpldr);
-
-	SYSCTRL->DPLLCTRLB.reg =
-			SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
-			((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
-			SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
-			SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
-			((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
-			((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
-			SYSCTRL_DPLLCTRLB_FILTER(config->filter);
-
-	/*
-	 * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
-	 */
-	_system_clock_inst.dpll.frequency =
-			(refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4;
-}
-#endif
-
-/**
- * \brief Writes the calibration values for a given oscillator clock source.
- *
- * Writes an oscillator calibration value to the given oscillator control
- * registers. The acceptable ranges are:
- *
- * For OSC32K:
- *  - 7 bits (max value 128)
- * For OSC8MHZ:
- *  - 8 bits (Max value 255)
- * For OSCULP:
- *  - 5 bits (Max value 32)
- *
- * \note The frequency range parameter applies only when configuring the 8MHz
- *       oscillator and will be ignored for the other oscillators.
- *
- * \param[in] clock_source       Clock source to calibrate
- * \param[in] calibration_value  Calibration value to write
- * \param[in] freq_range         Frequency range (8MHz oscillator only)
- *
- * \retval STATUS_OK               The calibration value was written
- *                                 successfully.
- * \retval STATUS_ERR_INVALID_ARG  The setting is not valid for selected clock
- *                                 source.
- */
-enum status_code system_clock_source_write_calibration(
-		const enum system_clock_source clock_source,
-		const uint16_t calibration_value,
-		const uint8_t freq_range)
-{
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-
-		if (calibration_value > 0xfff || freq_range > 4) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-
-		SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
-		SYSCTRL->OSC8M.bit.FRANGE = freq_range;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-
-		if (calibration_value > 128) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-
-		_system_osc32k_wait_for_sync();
-		SYSCTRL->OSC32K.bit.CALIB = calibration_value;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-
-		if (calibration_value > 32) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-
-		SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
-		break;
-
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-		break;
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Enables a clock source.
- *
- * Enables a clock source which has been previously configured.
- *
- * \param[in] clock_source       Clock source to enable
- *
- * \retval STATUS_OK               Clock source was enabled successfully and
- *                                 is ready
- * \retval STATUS_ERR_INVALID_ARG  The clock source is not available on this
- *                                 device
- */
-enum status_code system_clock_source_enable(
-		const enum system_clock_source clock_source)
-{
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
-		return STATUS_OK;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
-		_system_clock_source_dfll_set_config_errata_9905();
-		break;
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
-		break;
-#endif
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Always enabled */
-		return STATUS_OK;
-
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Disables a clock source.
- *
- * Disables a clock source that was previously enabled.
- *
- * \param[in] clock_source  Clock source to disable
- *
- * \retval STATUS_OK               Clock source was disabled successfully
- * \retval STATUS_ERR_INVALID_ARG  An invalid or unavailable clock source was
- *                                 given
- */
-enum status_code system_clock_source_disable(
-		const enum system_clock_source clock_source)
-{
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
-		SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
-		break;
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
-		break;
-#endif
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Not possible to disable */
-
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Checks if a clock source is ready.
- *
- * Checks if a given clock source is ready to be used.
- *
- * \param[in] clock_source  Clock source to check if ready
- *
- * \returns Ready state of the given clock source.
- *
- * \retval true   Clock source is enabled and ready
- * \retval false  Clock source is disabled or not yet ready
- */
-bool system_clock_source_is_ready(
-		const enum system_clock_source clock_source)
-{
-	uint32_t mask = 0;
-
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		mask = SYSCTRL_PCLKSR_OSC8MRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		mask = SYSCTRL_PCLKSR_OSC32KRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		mask = SYSCTRL_PCLKSR_XOSCRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		mask = SYSCTRL_PCLKSR_XOSC32KRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-			mask = (SYSCTRL_PCLKSR_DFLLRDY |
-			        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
-		} else {
-			mask = SYSCTRL_PCLKSR_DFLLRDY;
-		}
-		break;
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		return ((SYSCTRL->DPLLSTATUS.reg &
-				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
-				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
-#endif
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Not possible to disable */
-		return true;
-
-	default:
-		return false;
-	}
-
-	return ((SYSCTRL->PCLKSR.reg & mask) == mask);
-}
-
-/* Include some checks for conf_clocks.h validation */
-#include "clock_config_check.h"
-
-#if !defined(__DOXYGEN__)
-/** \internal
- *
- * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
- */
-#  define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
-	if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
-		struct system_gclk_gen_config gclk_conf;                          \
-		system_gclk_gen_get_config_defaults(&gclk_conf);                  \
-		gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
-		gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
-		gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
-		gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
-		system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
-		system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
-	}
-
-/** \internal
- *
- * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
- * provided that it is not the main Generic Clock Generator channel.
- */
-#  define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
-		if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
-#endif
-
-/** \internal
- *
- * Switch all peripheral clock to a not enabled general clock
- * to save power.
- */
-static void _switch_peripheral_gclk(void)
-{
-	uint32_t gclk_id;
-	struct system_gclk_chan_config gclk_conf;
-
-#if CONF_CLOCK_GCLK_1_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_1;
-#elif CONF_CLOCK_GCLK_2_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_2;
-#elif CONF_CLOCK_GCLK_3_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_3;
-#elif CONF_CLOCK_GCLK_4_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_4;
-#elif CONF_CLOCK_GCLK_5_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_5;
-#elif CONF_CLOCK_GCLK_6_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_6;
-#elif CONF_CLOCK_GCLK_7_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_7;
-#else
-	gclk_conf.source_generator = GCLK_GENERATOR_7;
-#endif
-
-	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
-		system_gclk_chan_set_config(gclk_id, &gclk_conf);
-	}
-}
-
-/**
- * \brief Initialize clock system based on the configuration in conf_clocks.h.
- *
- * This function will apply the settings in conf_clocks.h when run from the user
- * application. All clock sources and GCLK generators are running when this function
- * returns.
- *
- * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
- * the OSC8M default enable can be disabled after system_clock_init. Make sure the
- * clock switch successfully before disabling OSC8M.
- */
-void system_clock_init(void)
-{
-	/* Various bits in the INTFLAG register can be set to one at startup.
-	   This will ensure that these bits are cleared */
-	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
-			SYSCTRL_INTFLAG_DFLLRDY;
-
-	system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
-
-	/* Switch all peripheral clock to a not enabled general clock to save power. */
-	_switch_peripheral_gclk();
-
-	/* XOSC */
-#if CONF_CLOCK_XOSC_ENABLE == true
-	struct system_clock_source_xosc_config xosc_conf;
-	system_clock_source_xosc_get_config_defaults(&xosc_conf);
-
-	xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
-	xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
-	xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
-	xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
-
-	system_clock_source_xosc_set_config(&xosc_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC));
-	if (CONF_CLOCK_XOSC_ON_DEMAND || CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) {
-		SYSCTRL->XOSC.reg |=
-			(CONF_CLOCK_XOSC_ON_DEMAND << SYSCTRL_XOSC_ONDEMAND_Pos) |
-			(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL << SYSCTRL_XOSC_AMPGC_Pos);
-	}
-#endif
-
-
-	/* XOSC32K */
-#if CONF_CLOCK_XOSC32K_ENABLE == true
-	struct system_clock_source_xosc32k_config xosc32k_conf;
-	system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
-
-	xosc32k_conf.frequency           = 32768UL;
-	xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
-	xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
-	xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
-	xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
-	xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
-	xosc32k_conf.on_demand           = false;
-	xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
-
-	system_clock_source_xosc32k_set_config(&xosc32k_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
-	if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
-		SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
-	}
-#endif
-
-
-	/* OSCK32K */
-#if CONF_CLOCK_OSC32K_ENABLE == true
-	SYSCTRL->OSC32K.bit.CALIB =
-			((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >>
-			SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful);
-
-	struct system_clock_source_osc32k_config osc32k_conf;
-	system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
-
-	osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
-	osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
-	osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
-	osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
-	osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
-
-	system_clock_source_osc32k_set_config(&osc32k_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
-#endif
-
-
-	/* DFLL Config (Open and Closed Loop) */
-#if CONF_CLOCK_DFLL_ENABLE == true
-	struct system_clock_source_dfll_config dfll_conf;
-	system_clock_source_dfll_get_config_defaults(&dfll_conf);
-
-	dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
-	dfll_conf.on_demand      = false;
-
-	/* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping
-	   in DFLL.COARSE helps to output a frequency close to 48 MHz.*/
-#define NVM_DFLL_COARSE_POS    58 /* DFLL48M Coarse calibration value bit position.*/
-#define NVM_DFLL_COARSE_SIZE   6  /* DFLL48M Coarse calibration value bit size.*/
-
-	uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_DFLL_COARSE_POS / 32))
-		>> (NVM_DFLL_COARSE_POS % 32))
-		& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
-	/* In some revision chip, the coarse calibration value is not correct. */
-	if (coarse == 0x3f) {
-		coarse = 0x1f;
-	}
-	dfll_conf.coarse_value = coarse;
-
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
-		dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
-	}
-
-#  if CONF_CLOCK_DFLL_QUICK_LOCK == true
-	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
-#  else
-	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
-#  endif
-
-#  if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
-	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
-#  else
-	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
-#  endif
-
-#  if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
-	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
-#  else
-	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
-#  endif
-
-#  if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
-	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
-#  else
-	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
-#  endif
-
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-		dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
-	}
-
-	dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
-	dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
-
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
-		dfll_conf.fine_max_step   = 10;
-		dfll_conf.fine_value   = 0x1ff;
-		dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
-		dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
-		dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
-		dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
-
-		dfll_conf.multiply_factor = 48000;
-	}
-
-	system_clock_source_dfll_set_config(&dfll_conf);
-#endif
-
-
-	/* OSC8M */
-	struct system_clock_source_osc8m_config osc8m_conf;
-	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
-
-	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
-	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
-	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
-
-	system_clock_source_osc8m_set_config(&osc8m_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
-
-
-	/* GCLK */
-#if CONF_CLOCK_CONFIGURE_GCLK == true
-	system_gclk_init();
-
-	/* Configure all GCLK generators except for the main generator, which
-	 * is configured later after all other clock systems are set up */
-	MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
-
-#  if CONF_CLOCK_DFLL_ENABLE == true
-	/* Enable DFLL reference clock if in closed loop mode */
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-		struct system_gclk_chan_config dfll_gclk_chan_conf;
-
-		system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
-		dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
-	}
-#  endif
-
-#  if CONF_CLOCK_DPLL_ENABLE == true
-	/* Enable DPLL internal lock timer and reference clock */
-	struct system_gclk_chan_config dpll_gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf);
-	if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) {
-		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K);
-	}
-
-	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
-		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL);
-	}
-#  endif
-#endif
-
-
-	/* DFLL Enable (Open and Closed Loop) */
-#if CONF_CLOCK_DFLL_ENABLE == true
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
-	if (CONF_CLOCK_DFLL_ON_DEMAND) {
-		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
-	}
-#endif
-
-	/* DPLL */
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-#  if (CONF_CLOCK_DPLL_ENABLE == true)
-
-	/* Enable DPLL reference clock */
-	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) {
-		/* XOSC32K should have been enabled for DPLL_REF0 */
-		Assert(CONF_CLOCK_XOSC32K_ENABLE);
-	} else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
-		/* XOSC should have been enabled for DPLL_REF1 */
-		Assert(CONF_CLOCK_XOSC_ENABLE);
-	}
-	else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
-		/* GCLK should have been enabled */
-		Assert(CONF_CLOCK_CONFIGURE_GCLK);
-	}
-	else {
-		Assert(false);
-	}
-
-	struct system_clock_source_dpll_config dpll_config;
-	system_clock_source_dpll_get_config_defaults(&dpll_config);
-
-	dpll_config.on_demand        = false;
-	dpll_config.run_in_standby   = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
-	dpll_config.lock_bypass      = CONF_CLOCK_DPLL_LOCK_BYPASS;
-	dpll_config.wake_up_fast     = CONF_CLOCK_DPLL_WAKE_UP_FAST;
-	dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
-
-	dpll_config.filter           = CONF_CLOCK_DPLL_FILTER;
-	dpll_config.lock_time        = CONF_CLOCK_DPLL_LOCK_TIME;
-
-	dpll_config.reference_clock     = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
-	dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
-	dpll_config.reference_divider   = CONF_CLOCK_DPLL_REFERENCE_DIVIDER;
-	dpll_config.output_frequency    = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
-
-	system_clock_source_dpll_set_config(&dpll_config);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
-	if (CONF_CLOCK_DPLL_ON_DEMAND) {
-		SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
-	}
-
-#  endif
-#endif
-
-	/* CPU and BUS clocks */
-	system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
-
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
-
-	/* GCLK 0 */
-#if CONF_CLOCK_CONFIGURE_GCLK == true
-	/* Configure the main GCLK last as it might depend on other generators */
-	_CONF_CLOCK_GCLK_CONFIG(0, ~);
-#endif
-}
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock Driver
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <clock.h>
+#include <conf_clocks.h>
+#include <system.h>
+
+#ifndef SYSCTRL_FUSES_OSC32K_ADDR
+#if (SAMR21) || (SAMD) || (SAMHA1) || (SAMHA0)
+#  define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR
+#  define SYSCTRL_FUSES_OSC32K_Pos  FUSES_OSC32K_CAL_Pos
+#elif (SAML21)
+#  define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4
+#  define SYSCTRL_FUSES_OSC32K_Pos  6
+
+#else
+#  define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
+#  define SYSCTRL_FUSES_OSC32K_Pos  SYSCTRL_FUSES_OSC32K_CAL_Pos
+#endif
+#endif
+
+/**
+ * \internal
+ * \brief DFLL-specific data container.
+ */
+struct _system_clock_dfll_config {
+	uint32_t control;
+	uint32_t val;
+	uint32_t mul;
+};
+
+/**
+ * \internal
+ * \brief DPLL-specific data container.
+ */
+struct _system_clock_dpll_config {
+	uint32_t frequency;
+};
+
+
+/**
+ * \internal
+ * \brief XOSC-specific data container.
+ */
+struct _system_clock_xosc_config {
+	uint32_t frequency;
+};
+
+/**
+ * \internal
+ * \brief System clock module data container.
+ */
+struct _system_clock_module {
+	volatile struct _system_clock_dfll_config dfll;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	volatile struct _system_clock_dpll_config dpll;
+#endif
+
+	volatile struct _system_clock_xosc_config xosc;
+	volatile struct _system_clock_xosc_config xosc32k;
+};
+
+/**
+ * \internal
+ * \brief Internal module instance to cache configuration values.
+ */
+static struct _system_clock_module _system_clock_inst = {
+		.dfll = {
+			.control     = 0,
+			.val     = 0,
+			.mul     = 0,
+		},
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+		.dpll = {
+			.frequency   = 0,
+		},
+#endif
+		.xosc = {
+			.frequency   = 0,
+		},
+		.xosc32k = {
+			.frequency   = 0,
+		},
+	};
+
+/**
+ * \internal
+ * \brief Wait for sync to the DFLL control registers.
+ */
+static inline void _system_dfll_wait_for_sync(void)
+{
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+		/* Wait for DFLL sync */
+	}
+}
+
+/**
+ * \internal
+ * \brief Wait for sync to the OSC32K control registers.
+ */
+static inline void _system_osc32k_wait_for_sync(void)
+{
+	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
+		/* Wait for OSC32K sync */
+	}
+}
+
+static inline void _system_clock_source_dfll_set_config_errata_9905(void)
+{
+
+	/* Disable ONDEMAND mode while writing configurations */
+	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+	_system_dfll_wait_for_sync();
+
+	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+
+	/* Write full configuration to DFLL control register */
+	SYSCTRL->DFLLCTRL.reg = 0;
+	_system_dfll_wait_for_sync();
+	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+}
+
+/**
+ * \brief Retrieve the frequency of a clock source.
+ *
+ * Determines the current operating frequency of a given clock source.
+ *
+ * \param[in] clock_source  Clock source to get the frequency
+ *
+ * \returns Frequency of the given clock source, in Hz.
+ */
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		return _system_clock_inst.xosc.frequency;
+
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		return 32768UL;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		return 32768UL;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		return _system_clock_inst.xosc32k.frequency;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+
+		/* Check if the DFLL has been configured */
+		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+			return 0;
+
+		/* Make sure that the DFLL module is ready */
+		_system_dfll_wait_for_sync();
+
+		/* Check if operating in closed loop (USB) mode */
+		switch(_system_clock_inst.dfll.control &
+				(SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_USBCRM)) {
+		case SYSCTRL_DFLLCTRL_MODE:
+			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+					(_system_clock_inst.dfll.mul & 0xffff);
+		default:
+			return 48000000UL;
+		}
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
+			return 0;
+		}
+
+		return _system_clock_inst.dpll.frequency;
+#endif
+
+	default:
+		return 0;
+	}
+}
+
+/**
+ * \brief Configure the internal OSC8M oscillator clock source.
+ *
+ * Configures the 8MHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config  OSC8M configuration structure containing the new config
+ */
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config)
+{
+	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+
+	/* Use temporary struct to reduce register access */
+	temp.bit.PRESC    = config->prescaler;
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	SYSCTRL->OSC8M = temp;
+}
+
+/**
+ * \brief Configure the internal OSC32K oscillator clock source.
+ *
+ * Configures the 32KHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config  OSC32K configuration structure containing the new config
+ */
+void system_clock_source_osc32k_set_config(
+		struct system_clock_source_osc32k_config *const config)
+{
+	SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+
+	/* Update settings via a temporary struct to reduce register access */
+	temp.bit.EN1K     = config->enable_1khz_output;
+	temp.bit.EN32K    = config->enable_32khz_output;
+	temp.bit.STARTUP  = config->startup_time;
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+	temp.bit.WRTLOCK  = config->write_once;
+
+	SYSCTRL->OSC32K  = temp;
+}
+
+/**
+ * \brief Configure the external oscillator clock source.
+ *
+ * Configures the external oscillator clock source with the given configuration
+ * settings.
+ *
+ * \param[in] config  External oscillator configuration structure containing
+ *                    the new config
+ */
+void system_clock_source_xosc_set_config(
+		struct system_clock_source_xosc_config *const config)
+{
+	SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+	temp.bit.STARTUP = config->startup_time;
+
+	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+		temp.bit.XTALEN = 1;
+	} else {
+		temp.bit.XTALEN = 0;
+	}
+
+	temp.bit.AMPGC = config->auto_gain_control;
+
+	/* Set gain */
+	if (config->frequency <= 2000000) {
+		temp.bit.GAIN = 0;
+	} else if (config->frequency <= 4000000) {
+		temp.bit.GAIN = 1;
+	} else if (config->frequency <= 8000000) {
+		temp.bit.GAIN = 2;
+	} else if (config->frequency <= 16000000) {
+		temp.bit.GAIN = 3;
+	} else if (config->frequency <= 32000000) {
+		temp.bit.GAIN = 4;
+	}
+
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+
+	/* Store XOSC frequency for internal use */
+	_system_clock_inst.xosc.frequency = config->frequency;
+
+	SYSCTRL->XOSC = temp;
+}
+
+/**
+ * \brief Configure the XOSC32K external 32KHz oscillator clock source.
+ *
+ * Configures the external 32KHz oscillator clock source with the given
+ * configuration settings.
+ *
+ * \param[in] config  XOSC32K configuration structure containing the new config
+ */
+void system_clock_source_xosc32k_set_config(
+		struct system_clock_source_xosc32k_config *const config)
+{
+	SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+
+	temp.bit.STARTUP = config->startup_time;
+
+	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+		temp.bit.XTALEN = 1;
+	} else {
+		temp.bit.XTALEN = 0;
+	}
+
+	temp.bit.AAMPEN = config->auto_gain_control;
+	temp.bit.EN1K = config->enable_1khz_output;
+	temp.bit.EN32K = config->enable_32khz_output;
+
+	temp.bit.ONDEMAND = config->on_demand;
+	temp.bit.RUNSTDBY = config->run_in_standby;
+	temp.bit.WRTLOCK  = config->write_once;
+
+	/* Cache the new frequency in case the user needs to check the current
+	 * operating frequency later */
+	_system_clock_inst.xosc32k.frequency = config->frequency;
+
+	SYSCTRL->XOSC32K = temp;
+}
+
+/**
+ * \brief Configure the DFLL clock source.
+ *
+ * Configures the Digital Frequency Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DFLL will be running when this function returns, as the DFLL module
+ *       needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config  DFLL configuration structure containing the new config
+ */
+void system_clock_source_dfll_set_config(
+		struct system_clock_source_dfll_config *const config)
+{
+	_system_clock_inst.dfll.val =
+			SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
+			SYSCTRL_DFLLVAL_FINE(config->fine_value);
+
+	_system_clock_inst.dfll.control =
+			(uint32_t)config->wakeup_lock     |
+			(uint32_t)config->stable_tracking |
+			(uint32_t)config->quick_lock      |
+			(uint32_t)config->chill_cycle     |
+			((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+
+		_system_clock_inst.dfll.mul =
+				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
+				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+		/* Enable the closed loop mode */
+		_system_clock_inst.dfll.control |= config->loop_mode;
+	}
+	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+
+		_system_clock_inst.dfll.mul =
+				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
+				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+		/* Enable the USB recovery mode */
+		_system_clock_inst.dfll.control |= config->loop_mode |
+				SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_BPLCKC;
+	}
+}
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Configure the DPLL clock source.
+ *
+ * Configures the Digital Phase-Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DPLL will be running when this function returns, as the DPLL module
+ *       needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config  DPLL configuration structure containing the new config
+ */
+void system_clock_source_dpll_set_config(
+		struct system_clock_source_dpll_config *const config)
+{
+
+	uint32_t tmpldr;
+	uint8_t  tmpldrfrac;
+	uint32_t refclk;
+
+	refclk = config->reference_frequency;
+
+	/* Only reference clock REF1 can be divided */
+	if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
+		refclk = refclk / (2 * (config->reference_divider + 1));
+	}
+
+	/* Calculate LDRFRAC and LDR */
+	tmpldr = (config->output_frequency << 4) / refclk;
+	tmpldrfrac = tmpldr & 0x0f;
+	tmpldr = (tmpldr >> 4) - 1;
+
+	SYSCTRL->DPLLCTRLA.reg =
+			((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
+			((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
+
+	SYSCTRL->DPLLRATIO.reg =
+			SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
+			SYSCTRL_DPLLRATIO_LDR(tmpldr);
+
+	SYSCTRL->DPLLCTRLB.reg =
+			SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
+			((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
+			SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
+			SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
+			((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
+			((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
+			SYSCTRL_DPLLCTRLB_FILTER(config->filter);
+
+	/*
+	 * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
+	 */
+	_system_clock_inst.dpll.frequency =
+			(refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4;
+}
+#endif
+
+/**
+ * \brief Writes the calibration values for a given oscillator clock source.
+ *
+ * Writes an oscillator calibration value to the given oscillator control
+ * registers. The acceptable ranges are:
+ *
+ * For OSC32K:
+ *  - 7 bits (max value 128)
+ * For OSC8MHZ:
+ *  - 8 bits (Max value 255)
+ * For OSCULP:
+ *  - 5 bits (Max value 32)
+ *
+ * \note The frequency range parameter applies only when configuring the 8MHz
+ *       oscillator and will be ignored for the other oscillators.
+ *
+ * \param[in] clock_source       Clock source to calibrate
+ * \param[in] calibration_value  Calibration value to write
+ * \param[in] freq_range         Frequency range (8MHz oscillator only)
+ *
+ * \retval STATUS_OK               The calibration value was written
+ *                                 successfully.
+ * \retval STATUS_ERR_INVALID_ARG  The setting is not valid for selected clock
+ *                                 source.
+ */
+enum status_code system_clock_source_write_calibration(
+		const enum system_clock_source clock_source,
+		const uint16_t calibration_value,
+		const uint8_t freq_range)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+
+		if (calibration_value > 0xfff || freq_range > 4) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
+		SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+
+		if (calibration_value > 128) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		_system_osc32k_wait_for_sync();
+		SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+
+		if (calibration_value > 32) {
+			return STATUS_ERR_INVALID_ARG;
+		}
+
+		SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+		break;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+		break;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables a clock source.
+ *
+ * Enables a clock source which has been previously configured.
+ *
+ * \param[in] clock_source       Clock source to enable
+ *
+ * \retval STATUS_OK               Clock source was enabled successfully and
+ *                                 is ready
+ * \retval STATUS_ERR_INVALID_ARG  The clock source is not available on this
+ *                                 device
+ */
+enum status_code system_clock_source_enable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+		return STATUS_OK;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+		_system_clock_source_dfll_set_config_errata_9905();
+		break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+		break;
+#endif
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Always enabled */
+		return STATUS_OK;
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables a clock source.
+ *
+ * Disables a clock source that was previously enabled.
+ *
+ * \param[in] clock_source  Clock source to disable
+ *
+ * \retval STATUS_OK               Clock source was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid or unavailable clock source was
+ *                                 given
+ */
+enum status_code system_clock_source_disable(
+		const enum system_clock_source clock_source)
+{
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+		SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+		break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+		break;
+#endif
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Not possible to disable */
+
+	default:
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Checks if a clock source is ready.
+ *
+ * Checks if a given clock source is ready to be used.
+ *
+ * \param[in] clock_source  Clock source to check if ready
+ *
+ * \returns Ready state of the given clock source.
+ *
+ * \retval true   Clock source is enabled and ready
+ * \retval false  Clock source is disabled or not yet ready
+ */
+bool system_clock_source_is_ready(
+		const enum system_clock_source clock_source)
+{
+	uint32_t mask = 0;
+
+	switch (clock_source) {
+	case SYSTEM_CLOCK_SOURCE_OSC8M:
+		mask = SYSCTRL_PCLKSR_OSC8MRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_OSC32K:
+		mask = SYSCTRL_PCLKSR_OSC32KRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC:
+		mask = SYSCTRL_PCLKSR_XOSCRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_XOSC32K:
+		mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+		break;
+
+	case SYSTEM_CLOCK_SOURCE_DFLL:
+		if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+			mask = (SYSCTRL_PCLKSR_DFLLRDY |
+			        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+		} else {
+			mask = SYSCTRL_PCLKSR_DFLLRDY;
+		}
+		break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	case SYSTEM_CLOCK_SOURCE_DPLL:
+		return ((SYSCTRL->DPLLSTATUS.reg &
+				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
+				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
+#endif
+
+	case SYSTEM_CLOCK_SOURCE_ULP32K:
+		/* Not possible to disable */
+		return true;
+
+	default:
+		return false;
+	}
+
+	return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+}
+
+/* Include some checks for conf_clocks.h validation */
+#include "clock_config_check.h"
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
+ */
+#  define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
+	if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
+		struct system_gclk_gen_config gclk_conf;                          \
+		system_gclk_gen_get_config_defaults(&gclk_conf);                  \
+		gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
+		gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
+		gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+		gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
+		system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
+		system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
+	}
+
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
+ * provided that it is not the main Generic Clock Generator channel.
+ */
+#  define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
+		if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+#endif
+
+/** \internal
+ *
+ * Switch all peripheral clock to a not enabled general clock
+ * to save power.
+ */
+static void _switch_peripheral_gclk(void)
+{
+	uint32_t gclk_id;
+	struct system_gclk_chan_config gclk_conf;
+
+#if CONF_CLOCK_GCLK_1_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_1;
+#elif CONF_CLOCK_GCLK_2_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_2;
+#elif CONF_CLOCK_GCLK_3_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_3;
+#elif CONF_CLOCK_GCLK_4_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_4;
+#elif CONF_CLOCK_GCLK_5_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_5;
+#elif CONF_CLOCK_GCLK_6_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_6;
+#elif CONF_CLOCK_GCLK_7_ENABLE == false
+	gclk_conf.source_generator = GCLK_GENERATOR_7;
+#else
+	gclk_conf.source_generator = GCLK_GENERATOR_7;
+#endif
+
+	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
+		system_gclk_chan_set_config(gclk_id, &gclk_conf);
+	}
+}
+
+/**
+ * \brief Initialize clock system based on the configuration in conf_clocks.h.
+ *
+ * This function will apply the settings in conf_clocks.h when run from the user
+ * application. All clock sources and GCLK generators are running when this function
+ * returns.
+ *
+ * \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
+ * the OSC8M default enable can be disabled after system_clock_init. Make sure the
+ * clock switch successfully before disabling OSC8M.
+ */
+void system_clock_init(void)
+{
+	/* Various bits in the INTFLAG register can be set to one at startup.
+	   This will ensure that these bits are cleared */
+	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+			SYSCTRL_INTFLAG_DFLLRDY;
+
+	system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+
+	/* Switch all peripheral clock to a not enabled general clock to save power. */
+	_switch_peripheral_gclk();
+
+	/* XOSC */
+#if CONF_CLOCK_XOSC_ENABLE == true
+	struct system_clock_source_xosc_config xosc_conf;
+	system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+	xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+	xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
+	xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+	xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+	system_clock_source_xosc_set_config(&xosc_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC));
+	if (CONF_CLOCK_XOSC_ON_DEMAND || CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) {
+		SYSCTRL->XOSC.reg |=
+			(CONF_CLOCK_XOSC_ON_DEMAND << SYSCTRL_XOSC_ONDEMAND_Pos) |
+			(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL << SYSCTRL_XOSC_AMPGC_Pos);
+	}
+#endif
+
+
+	/* XOSC32K */
+#if CONF_CLOCK_XOSC32K_ENABLE == true
+	struct system_clock_source_xosc32k_config xosc32k_conf;
+	system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+	xosc32k_conf.frequency           = 32768UL;
+	xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+	xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+	xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+	xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+	xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+	xosc32k_conf.on_demand           = false;
+	xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+	system_clock_source_xosc32k_set_config(&xosc32k_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+	if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
+		SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+	}
+#endif
+
+
+	/* OSCK32K */
+#if CONF_CLOCK_OSC32K_ENABLE == true
+	SYSCTRL->OSC32K.bit.CALIB =
+			((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >>
+			SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful);
+
+	struct system_clock_source_osc32k_config osc32k_conf;
+	system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+
+	osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
+	osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+	osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+	osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
+	osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+
+	system_clock_source_osc32k_set_config(&osc32k_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+#endif
+
+
+	/* DFLL Config (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+	struct system_clock_source_dfll_config dfll_conf;
+	system_clock_source_dfll_get_config_defaults(&dfll_conf);
+
+	dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
+	dfll_conf.on_demand      = false;
+
+	/* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping
+	   in DFLL.COARSE helps to output a frequency close to 48 MHz.*/
+#define NVM_DFLL_COARSE_POS    58 /* DFLL48M Coarse calibration value bit position.*/
+#define NVM_DFLL_COARSE_SIZE   6  /* DFLL48M Coarse calibration value bit size.*/
+
+	uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+			+ (NVM_DFLL_COARSE_POS / 32))
+		>> (NVM_DFLL_COARSE_POS % 32))
+		& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+	/* In some revision chip, the coarse calibration value is not correct. */
+	if (coarse == 0x3f) {
+		coarse = 0x1f;
+	}
+	dfll_conf.coarse_value = coarse;
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
+		dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
+	}
+
+#  if CONF_CLOCK_DFLL_QUICK_LOCK == true
+	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+#  else
+	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+#  endif
+
+#  if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
+	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+#  else
+	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+#  endif
+
+#  if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
+	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+#  else
+	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+#  endif
+
+#  if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
+	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+#  else
+	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+#  endif
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+		dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+	}
+
+	dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+	dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+		dfll_conf.fine_max_step   = 10;
+		dfll_conf.fine_value   = 0x1ff;
+		dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+		dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+		dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+		dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+
+		dfll_conf.multiply_factor = 48000;
+	}
+
+	system_clock_source_dfll_set_config(&dfll_conf);
+#endif
+
+
+	/* OSC8M */
+	struct system_clock_source_osc8m_config osc8m_conf;
+	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+
+	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
+	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
+	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+
+	system_clock_source_osc8m_set_config(&osc8m_conf);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+
+
+	/* GCLK */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	system_gclk_init();
+
+	/* Configure all GCLK generators except for the main generator, which
+	 * is configured later after all other clock systems are set up */
+	MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+
+#  if CONF_CLOCK_DFLL_ENABLE == true
+	/* Enable DFLL reference clock if in closed loop mode */
+	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+		struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+		system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+		dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+	}
+#  endif
+
+#  if CONF_CLOCK_DPLL_ENABLE == true
+	/* Enable DPLL internal lock timer and reference clock */
+	struct system_gclk_chan_config dpll_gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf);
+	if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) {
+		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K);
+	}
+
+	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
+		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR;
+		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf);
+		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL);
+	}
+#  endif
+#endif
+
+
+	/* DFLL Enable (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+	if (CONF_CLOCK_DFLL_ON_DEMAND) {
+		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+	}
+#endif
+
+	/* DPLL */
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+#  if (CONF_CLOCK_DPLL_ENABLE == true)
+
+	/* Enable DPLL reference clock */
+	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) {
+		/* XOSC32K should have been enabled for DPLL_REF0 */
+		Assert(CONF_CLOCK_XOSC32K_ENABLE);
+	} else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
+		/* XOSC should have been enabled for DPLL_REF1 */
+		Assert(CONF_CLOCK_XOSC_ENABLE);
+	}
+	else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
+		/* GCLK should have been enabled */
+		Assert(CONF_CLOCK_CONFIGURE_GCLK);
+	}
+	else {
+		Assert(false);
+	}
+
+	struct system_clock_source_dpll_config dpll_config;
+	system_clock_source_dpll_get_config_defaults(&dpll_config);
+
+	dpll_config.on_demand        = false;
+	dpll_config.run_in_standby   = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
+	dpll_config.lock_bypass      = CONF_CLOCK_DPLL_LOCK_BYPASS;
+	dpll_config.wake_up_fast     = CONF_CLOCK_DPLL_WAKE_UP_FAST;
+	dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
+
+	dpll_config.filter           = CONF_CLOCK_DPLL_FILTER;
+	dpll_config.lock_time        = CONF_CLOCK_DPLL_LOCK_TIME;
+
+	dpll_config.reference_clock     = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
+	dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
+	dpll_config.reference_divider   = CONF_CLOCK_DPLL_REFERENCE_DIVIDER;
+	dpll_config.output_frequency    = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
+
+	system_clock_source_dpll_set_config(&dpll_config);
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
+	if (CONF_CLOCK_DPLL_ON_DEMAND) {
+		SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
+	}
+
+#  endif
+#endif
+
+	/* CPU and BUS clocks */
+	system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
+
+	/* GCLK 0 */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+	/* Configure the main GCLK last as it might depend on other generators */
+	_CONF_CLOCK_GCLK_CONFIG(0, ~);
+#endif
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
index a18e31b..a5572dc 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_config_check.h
@@ -1,444 +1,444 @@
-/**
- * \file
- *
- * \brief SAM D21/R21/DA/HA Clock Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef CLOCK_CONFIG_CHECK_H
-#  define CLOCK_CONFIG_CHECK_H
-
-#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
-#  error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_CPU_DIVIDER)
-#  error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_APBA_DIVIDER)
-#  error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_APBB_DIVIDER)
-#  error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_APBC_DIVIDER)
-#  error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
-#  error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
-#  error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
-#  error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_ENABLE)
-#  error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
-#  error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
-#  error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
-#  error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
-#  error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
-#  error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
-#  error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
-#  error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
-#  error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
-#  error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
-#  error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
-#  error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
-#  error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
-#  error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
-#  error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC32K_ENABLE)
-#  error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
-#  error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
-#  error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
-#  error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
-#  error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
-#  error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_ENABLE)
-#  error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
-#  error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
-#  error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
-#  error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
-#  error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
-#  error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
-#  error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
-#  error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
-#  error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
-#  error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
-#  error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
-#  error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_ENABLE)
-#  error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
-#  error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
-#  error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
-#  error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
-#  error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
-#  error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
-#  error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
-#  error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_FILTER)
-#  error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
-#  error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER)
-#  error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
-#  error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR)
-#  error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR)
-#  error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
-#  error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
-#  error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
-#  error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
-#  error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
-#  error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
-#  error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
-#  error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
-#  error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
-#  error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
-#  error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
-#  error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
-#  error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
-#  error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
-#  error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
-#  error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
-#  error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
-#  error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_8_ENABLE)
-#  error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY)
-#  error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE)
-#  error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_8_PRESCALER)
-#  error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h
-#endif
-
-#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE)
-#  error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h
-#endif
-
-#endif /* CLOCK_CONFIG_CHECK_H */
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef CLOCK_CONFIG_CHECK_H
+#  define CLOCK_CONFIG_CHECK_H
+
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
+#  error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CPU_DIVIDER)
+#  error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBA_DIVIDER)
+#  error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBB_DIVIDER)
+#  error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBC_DIVIDER)
+#  error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
+#  error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
+#  error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ENABLE)
+#  error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
+#  error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
+#  error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
+#  error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
+#  error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
+#  error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
+#  error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)
+#  error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
+#  error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE)
+#  error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
+#  error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
+#  error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
+#  error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
+#  error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
+#  error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
+#  error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
+#  error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
+#  error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ENABLE)
+#  error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
+#  error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
+#  error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
+#  error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
+#  error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
+#  error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
+#  error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
+#  error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_FILTER)
+#  error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
+#  error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER)
+#  error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
+#  error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
+#  error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
+#  error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
+#  error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
+#  error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
+#  error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
+#  error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
+#  error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
+#  error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
+#  error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
+#  error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
+#  error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
+#  error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
+#  error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
+#  error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
+#  error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
+#  error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
+#  error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_ENABLE)
+#  error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_PRESCALER)
+#  error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#endif /* CLOCK_CONFIG_CHECK_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
index 425581d..5de2204 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
@@ -1,1483 +1,1483 @@
-/**
- * \file
- *
- * \brief SAM Clock Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
-#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
- * and management of the device's clocking related functions. This includes
- * the various clock sources, bus clocks, and generic clocks within the device,
- * with functions to manage the enabling, disabling, source selection, and
- * prescaling of clocks to various internal peripherals.
- *
- * The following peripherals are used by this module:
- *
- * - GCLK (Generic Clock Management)
- * - PM (Power Management)
- * - SYSCTRL (Clock Source Control)
- *
- * The following devices can use this module:
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM HA1
- *
- * The outline of this documentation is as follows:
- *  - \ref asfdoc_sam0_system_clock_prerequisites
- *  - \ref asfdoc_sam0_system_clock_module_overview
- *  - \ref asfdoc_sam0_system_clock_special_considerations
- *  - \ref asfdoc_sam0_system_clock_extra_info
- *  - \ref asfdoc_sam0_system_clock_examples
- *  - \ref asfdoc_sam0_system_clock_api_overview
- *
- *
- * \section asfdoc_sam0_system_clock_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_system_clock_module_overview Module Overview
- * The SAM devices contain a sophisticated clocking system, which is designed
- * to give the maximum flexibility to the user application. This system allows
- * a system designer to tune the performance and power consumption of the device
- * in a dynamic manner, to achieve the best trade-off between the two for a
- * particular application.
- *
- * This driver provides a set of functions for the configuration and management
- * of the various clock related functionality within the device.
- *
- * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
- * <table>
- *	<tr>
- *		<th>Driver Feature Macro</th>
- *		<th>Supported devices</th>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_SYSTEM_CLOCK_DPLL</td>
- *		<td>SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1</td>
- *	</tr>
- * </table>
- * \note The specific features are only available in the driver when the
- * selected device supports those features.
- *
- * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
- * The SAM devices have a number of master clock source modules, each of
- * which being capable of producing a stabilized output frequency, which can then
- * be fed into the various peripherals and modules within the device.
- *
- * Possible clock source modules include internal R/C oscillators, internal
- * DFLL modules, as well as external crystal oscillators and/or clock inputs.
- *
- * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
- * The CPU and AHB/APBx buses are clocked by the same physical clock source
- * (referred in this module as the Main Clock), however the APBx buses may
- * have additional prescaler division ratios set to give each peripheral bus a
- * different clock speed.
- *
- * The general main clock tree for the CPU and associated buses is shown in
- * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
- *
- * \anchor asfdoc_sam0_system_clock_module_clock_tree
- * \dot
- * digraph overview {
- *   rankdir=LR;
- *   clk_src [label="Clock Sources", shape=none, height=0];
- *   node [label="CPU Bus" shape=ellipse] cpu_bus;
- *   node [label="AHB Bus" shape=ellipse] ahb_bus;
- *   node [label="APBA Bus" shape=ellipse] apb_a_bus;
- *   node [label="APBB Bus" shape=ellipse] apb_b_bus;
- *   node [label="APBC Bus" shape=ellipse] apb_c_bus;
- *   node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
- *   node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
- *   node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
- *   node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
- *   node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
- *
- *   clk_src         -> main_clock_mux;
- *   main_clock_mux  -> main_prescaler;
- *   main_prescaler  -> cpu_bus;
- *   main_prescaler  -> ahb_bus;
- *   main_prescaler  -> apb_a_prescaler;
- *   main_prescaler  -> apb_b_prescaler;
- *   main_prescaler  -> apb_c_prescaler;
- *   apb_a_prescaler -> apb_a_bus;
- *   apb_b_prescaler -> apb_b_bus;
- *   apb_c_prescaler -> apb_c_bus;
- * }
- * \enddot
- *
- * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
- * To save power, the input clock to one or more peripherals on the AHB and APBx
- * buses can be masked away - when masked, no clock is passed into the module.
- * Disabling of clocks of unused modules will prevent all access to the masked
- * module, but will reduce the overall device power consumption.
- *
- * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
- * Within the SAM devices there are a number of Generic Clocks; these are used to
- * provide clocks to the various peripheral clock domains in the device in a
- * standardized manner. One or more master source clocks can be selected as the
- * input clock to a Generic Clock Generator, which can prescale down the input
- * frequency to a slower rate for use in a peripheral.
- *
- * Additionally, a number of individually selectable Generic Clock Channels are
- * provided, which multiplex and gate the various generator outputs for one or
- * more peripherals within the device. This setup allows for a single common
- * generator to feed one or more channels, which can then be enabled or disabled
- * individually as required.
- *
- * \anchor asfdoc_sam0_system_clock_module_chain_overview
- * \dot
- * digraph overview {
- *   rankdir=LR;
- *   node [label="Clock\nSource a" shape=square] system_clock_source;
- *   node [label="Generator 1" shape=square] clock_gen;
- *   node [label="Channel x" shape=square] clock_chan0;
- *   node [label="Channel y" shape=square] clock_chan1;
- *   node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
- *   node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
- *
- *   system_clock_source -> clock_gen;
- *   clock_gen   -> clock_chan0;
- *   clock_chan0 -> peripheral0;
- *   clock_gen   -> clock_chan1;
- *   clock_chan1 -> peripheral1;
- * }
- * \enddot
- *
- * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
- * An example setup of a complete clock chain within the device is shown in
- * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
- *
- * \anchor asfdoc_sam0_system_clock_module_chain_example_fig
- * \dot
- * digraph overview {
- *   rankdir=LR;
- *   node [label="External\nOscillator" shape=square] system_clock_source0;
- *   node [label="Generator 0" shape=square] clock_gen0;
- *   node [label="Channel x" shape=square] clock_chan0;
- *   node [label="Core CPU" shape=ellipse  style=filled fillcolor=lightgray] peripheral0;
- *
- *   system_clock_source0 -> clock_gen0;
- *   clock_gen0    -> clock_chan0;
- *   clock_chan0   -> peripheral0;
- *   node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
- *   node [label="Generator 1" shape=square] clock_gen1;
- *   node [label="Channel y" shape=square] clock_chan1;
- *   node [label="Channel z" shape=square] clock_chan2;
- *   node [label="SERCOM\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral1;
- *   node [label="Timer\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral2;
- *
- *   system_clock_source1 -> clock_gen1;
- *   clock_gen1    -> clock_chan1;
- *   clock_gen1    -> clock_chan2;
- *   clock_chan1   -> peripheral1;
- *   clock_chan2   -> peripheral2;
- * }
- * \enddot
- *
- * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
- * Each Generic Clock generator within the device can source its input clock
- * from one of the provided Source Clocks, and prescale the output for one or
- * more Generic Clock Channels in a one-to-many relationship. The generators
- * thus allow for several clocks to be generated of different frequencies,
- * power usages, and accuracies, which can be turned on and off individually to
- * disable the clocks to multiple peripherals as a group.
- *
- * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
- * To connect a Generic Clock Generator to a peripheral within the
- * device, a Generic Clock Channel is used. Each peripheral or
- * peripheral group has an associated Generic Clock Channel, which serves as the
- * clock input for the peripheral(s). To supply a clock to the peripheral
- * module(s), the associated channel must be connected to a running Generic
- * Clock Generator and the channel enabled.
- *
- * \section asfdoc_sam0_system_clock_special_considerations Special Considerations
- *
- * There are no special considerations for this module.
- *
- *
- * \section asfdoc_sam0_system_clock_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
- *  - \ref asfdoc_sam0_system_clock_extra_acronyms
- *  - \ref asfdoc_sam0_system_clock_extra_dependencies
- *  - \ref asfdoc_sam0_system_clock_extra_errata
- *  - \ref asfdoc_sam0_system_clock_extra_history
- *
- *
- * \section asfdoc_sam0_system_clock_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_system_clock_exqsg.
- *
- *
- * \section asfdoc_sam0_system_clock_api_overview API Overview
- * @{
- */
-
-#include <compiler.h>
-#include <gclk.h>
-
-/**
- * \name Driver Feature Definition
- * Define system clock features set according to different device family.
- * @{
- */
-#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || (SAMHA1) || (SAMHA0) || defined(__DOXYGEN__)
-/** Digital Phase Locked Loop (DPLL) feature support. */
-#  define FEATURE_SYSTEM_CLOCK_DPLL
-#endif
-/*@}*/
-
-/**
- * \brief Available start-up times for the XOSC32K.
- *
- * Available external 32KHz oscillator start-up times, as a number of external
- * clock cycles.
- */
-enum system_xosc32k_startup {
-	/** Wait zero clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_0,
-	/** Wait 32 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_32,
-	/** Wait 2048 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_2048,
-	/** Wait 4096 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_4096,
-	/** Wait 16384 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_16384,
-	/** Wait 32768 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_32768,
-	/** Wait 65536 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_65536,
-	/** Wait 131072 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_131072,
-};
-
-/**
- * \brief Available start-up times for the XOSC.
- *
- * Available external oscillator start-up times, as a number of external clock
- * cycles.
- */
-enum system_xosc_startup {
-	/** Wait one clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_1,
-	/** Wait two clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_2,
-	/** Wait four clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_4,
-	/** Wait eight clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_8,
-	/** Wait 16 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_16,
-	/** Wait 32 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_32,
-	/** Wait 64 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_64,
-	/** Wait 128 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_128,
-	/** Wait 256 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_256,
-	/** Wait 512 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_512,
-	/** Wait 1024 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_1024,
-	/** Wait 2048 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_2048,
-	/** Wait 4096 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_4096,
-	/** Wait 8192 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_8192,
-	/** Wait 16384 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_16384,
-	/** Wait 32768 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_32768,
-};
-
-/**
- * \brief Available start-up times for the OSC32K.
- *
- * Available internal 32KHz oscillator start-up times, as a number of internal
- * OSC32K clock cycles.
- */
-enum system_osc32k_startup {
-	/** Wait three clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_3,
-	/** Wait four clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_4,
-	/** Wait six clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_6,
-	/** Wait ten clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_10,
-	/** Wait 18 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_18,
-	/** Wait 34 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_34,
-	/** Wait 66 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_66,
-	/** Wait 130 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_130,
-};
-
-/**
- * \brief Division prescalers for the internal 8MHz system clock.
- *
- * Available prescalers for the internal 8MHz (nominal) system clock.
- */
-enum system_osc8m_div {
-	/** Do not divide the 8MHz RC oscillator output */
-	SYSTEM_OSC8M_DIV_1,
-	/** Divide the 8MHz RC oscillator output by two */
-	SYSTEM_OSC8M_DIV_2,
-	/** Divide the 8MHz RC oscillator output by four */
-	SYSTEM_OSC8M_DIV_4,
-	/** Divide the 8MHz RC oscillator output by eight */
-	SYSTEM_OSC8M_DIV_8,
-};
-
-/**
- * \brief Frequency range for the internal 8MHz RC oscillator.
- *
- * Internal 8MHz RC oscillator frequency range setting.
- */
-enum system_osc8m_frequency_range {
-	/** Frequency range 4MHz to 6MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
-	/** Frequency range 6MHz to 8MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
-	/** Frequency range 8MHz to 11MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
-	/** Frequency range 11MHz to 15MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
-};
-
-/**
- * \brief Main CPU and APB/AHB bus clock source prescaler values.
- *
- * Available division ratios for the CPU and APB/AHB bus clocks.
- */
-enum system_main_clock_div {
-	/** Divide Main clock by one */
-	SYSTEM_MAIN_CLOCK_DIV_1,
-	/** Divide Main clock by two */
-	SYSTEM_MAIN_CLOCK_DIV_2,
-	/** Divide Main clock by four */
-	SYSTEM_MAIN_CLOCK_DIV_4,
-	/** Divide Main clock by eight */
-	SYSTEM_MAIN_CLOCK_DIV_8,
-	/** Divide Main clock by 16 */
-	SYSTEM_MAIN_CLOCK_DIV_16,
-	/** Divide Main clock by 32 */
-	SYSTEM_MAIN_CLOCK_DIV_32,
-	/** Divide Main clock by 64 */
-	SYSTEM_MAIN_CLOCK_DIV_64,
-	/** Divide Main clock by 128 */
-	SYSTEM_MAIN_CLOCK_DIV_128,
-};
-
-/**
- * \brief External clock source types.
- *
- * Available external clock source types.
- */
-enum system_clock_external {
-	/** The external clock source is a crystal oscillator */
-	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
-	/** The connected clock source is an external logic level clock signal */
-	SYSTEM_CLOCK_EXTERNAL_CLOCK,
-};
-
-/**
- * \brief Operating modes of the DFLL clock source.
- *
- * Available operating modes of the DFLL clock source module.
- */
-enum system_clock_dfll_loop_mode {
-	/** The DFLL is operating in open loop mode with no feedback */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
-	/** The DFLL is operating in closed loop mode with frequency feedback from
-	 *  a low frequency reference clock
-	 */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
-
-#ifdef SYSCTRL_DFLLCTRL_USBCRM
-	/** The DFLL is operating in USB recovery mode with frequency feedback
-	 *  from USB SOF.
-	 */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
-#endif
-};
-
-/**
- * \brief Locking behavior for the DFLL during device wake-up.
- *
- * DFLL lock behavior modes on device wake-up from sleep.
- */
-enum system_clock_dfll_wakeup_lock {
-	/** Keep DFLL lock when the device wakes from sleep */
-	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
-	/** Lose DFLL lock when the devices wakes from sleep */
-	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
-};
-
-/**
- * \brief Fine tracking behavior for the DFLL once a lock has been acquired.
- *
- * DFLL fine tracking behavior modes after a lock has been acquired.
- */
-enum system_clock_dfll_stable_tracking {
-	/** Keep tracking after the DFLL has gotten a fine lock */
-	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
-	/** Stop tracking after the DFLL has gotten a fine lock */
-	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
-};
-
-/**
- * \brief Chill-cycle behavior of the DFLL module.
- *
- * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
- * of time when the DFLL output frequency is not measured by the unit, to allow
- * the output to stabilize after a change in the input clock source.
- */
-enum system_clock_dfll_chill_cycle {
-	/** Enable a chill cycle, where the DFLL output frequency is not measured */
-	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
-	/** Disable a chill cycle, where the DFLL output frequency is not measured */
-	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
-};
-
-/**
- * \brief QuickLock settings for the DFLL module.
- *
- * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
- * the DFLL output frequency at the expense of accuracy.
- */
-enum system_clock_dfll_quick_lock {
-	/** Enable the QuickLock feature for looser lock requirements on the DFLL */
-	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
-	/** Disable the QuickLock feature for strict lock requirements on the DFLL */
-	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
-};
-
-/**
- * \brief Available clock sources in the system.
- *
- * Clock sources available to the GCLK generators.
- */
-enum system_clock_source {
-	/** Internal 8MHz RC oscillator */
-	SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
-	/** Internal 32KHz RC oscillator */
-	SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
-	/** External oscillator */
-	SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
-	/** External 32KHz oscillator */
-	SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
-	/** Digital Frequency Locked Loop (DFLL) */
-	SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
-	/** Internal Ultra Low Power 32KHz oscillator */
-	SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
-	/** Generator input pad */
-	SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
-	/** Generic clock generator one output */
-	SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	/** Digital Phase Locked Loop (DPLL).
-	 * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
-	 */
-	SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
-#endif
-};
-
-/**
- * \brief List of APB peripheral buses.
- *
- * Available bus clock domains on the APB bus.
- */
-enum system_clock_apb_bus {
-	/** Peripheral bus A on the APB bus */
-	SYSTEM_CLOCK_APB_APBA,
-	/** Peripheral bus B on the APB bus */
-	SYSTEM_CLOCK_APB_APBB,
-	/** Peripheral bus C on the APB bus */
-	SYSTEM_CLOCK_APB_APBC,
-};
-
-/**
- * \brief Configuration structure for XOSC.
- *
- * External oscillator clock configuration structure.
- */
-struct system_clock_source_xosc_config {
-	/** External clock type */
-	enum system_clock_external external_clock;
-	/** Crystal oscillator start-up time */
-	enum system_xosc_startup startup_time;
-	/** Enable automatic amplitude gain control */
-	bool auto_gain_control;
-	/** External clock/crystal frequency */
-	uint32_t frequency;
-	/** Keep the XOSC enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the XOSC won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-};
-
-/**
- * \brief Configuration structure for XOSC32K.
- *
- * External 32KHz oscillator clock configuration structure.
- */
-struct system_clock_source_xosc32k_config {
-	/** External clock type */
-	enum system_clock_external external_clock;
-	/** Crystal oscillator start-up time */
-	enum system_xosc32k_startup startup_time;
-	/** Enable automatic amplitude control */
-	bool auto_gain_control;
-	/** Enable 1KHz output */
-	bool enable_1khz_output;
-	/** Enable 32KHz output */
-	bool enable_32khz_output;
-	/** External clock/crystal frequency */
-	uint32_t frequency;
-	/** Keep the XOSC32K enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the XOSC32K won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Lock configuration after it has been written,
-	 *  a device reset will release the lock */
-	bool write_once;
-};
-
-/**
- * \brief Configuration structure for OSC8M.
- *
- * Internal 8MHz (nominal) oscillator configuration structure.
- */
-struct system_clock_source_osc8m_config {
-	/** Internal 8MHz RC oscillator prescaler */
-	enum system_osc8m_div prescaler;
-	/** Keep the OSC8M enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the OSC8M won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-};
-
-/**
- * \brief Configuration structure for OSC32K.
- *
- * Internal 32KHz (nominal) oscillator configuration structure.
- */
-struct system_clock_source_osc32k_config {
-	/** Startup time */
-	enum system_osc32k_startup startup_time;
-	/** Enable 1KHz output */
-	bool enable_1khz_output;
-	/** Enable 32KHz output */
-	bool enable_32khz_output;
-	/** Keep the OSC32K enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the OSC32K won't run
-	 * until requested by a peripheral */
-	bool on_demand;
-	/** Lock configuration after it has been written,
-	 *  a device reset will release the lock */
-	bool write_once;
-};
-
-/**
- * \brief Configuration structure for DFLL.
- *
- * DFLL oscillator configuration structure.
- */
-struct system_clock_source_dfll_config {
-	/** Loop mode */
-	enum system_clock_dfll_loop_mode loop_mode;
-	/** Run On Demand. If this is set the DFLL won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Enable Quick Lock */
-	enum system_clock_dfll_quick_lock quick_lock;
-	/** Enable Chill Cycle */
-	enum system_clock_dfll_chill_cycle chill_cycle;
-	/** DFLL lock state on wakeup */
-	enum system_clock_dfll_wakeup_lock wakeup_lock;
-	/** DFLL tracking after fine lock */
-	enum system_clock_dfll_stable_tracking stable_tracking;
-	/** Coarse calibration value (Open loop mode) */
-	uint8_t coarse_value;
-	/** Fine calibration value (Open loop mode) */
-	uint16_t fine_value;
-	/** Coarse adjustment maximum step size (Closed loop mode) */
-	uint8_t coarse_max_step;
-	/** Fine adjustment maximum step size (Closed loop mode) */
-	uint16_t fine_max_step;
-	/** DFLL multiply factor (Closed loop mode */
-	uint16_t multiply_factor;
-};
-
-/**
- * \name External Oscillator Management
- * @{
- */
-
-/**
- * \brief Retrieve the default configuration for XOSC.
- *
- * Fills a configuration structure with the default configuration for an
- * external oscillator module:
- *   - External Crystal
- *   - Start-up time of 16384 external clock cycles
- *   - Automatic crystal gain control mode disabled
- *   - Frequency of 12MHz
- *   - Don't run in STANDBY sleep mode
- *   - Run when it's enabled (not on demand)
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void system_clock_source_xosc_get_config_defaults(
-		struct system_clock_source_xosc_config *const config)
-{
-	Assert(config);
-
-	config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
-	config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
-	config->auto_gain_control = false;
-	config->frequency         = 12000000UL;
-	config->run_in_standby    = false;
-	config->on_demand         = false;
-}
-
-void system_clock_source_xosc_set_config(
-		struct system_clock_source_xosc_config *const config);
-
-/**
- * @}
- */
-
-
-/**
- * \name External 32KHz Oscillator Management
- * @{
- */
-
-/**
- * \brief Retrieve the default configuration for XOSC32K.
- *
- * Fills a configuration structure with the default configuration for an
- * external 32KHz oscillator module:
- *   - External Crystal
- *   - Start-up time of 16384 external clock cycles
- *   - Automatic crystal gain control mode disabled
- *   - Frequency of 32.768KHz
- *   - 1KHz clock output disabled
- *   - 32KHz clock output enabled
- *   - Don't run in STANDBY sleep mode
- *   - Run only when requested by peripheral (on demand)
- *   - Don't lock registers after configuration has been written
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void system_clock_source_xosc32k_get_config_defaults(
-		struct system_clock_source_xosc32k_config *const config)
-{
-	Assert(config);
-
-	config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
-	config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
-	config->auto_gain_control   = false;
-	config->frequency           = 32768UL;
-	config->enable_1khz_output  = false;
-	config->enable_32khz_output = true;
-	config->run_in_standby      = false;
-	config->on_demand           = true;
-	config->write_once          = false;
-}
-
-void system_clock_source_xosc32k_set_config(
-		struct system_clock_source_xosc32k_config *const config);
-/**
- * @}
- */
-
-
-/**
- * \name Internal 32KHz Oscillator Management
- * @{
- */
-
-/**
- * \brief Retrieve the default configuration for OSC32K.
- *
- * Fills a configuration structure with the default configuration for an
- * internal 32KHz oscillator module:
- *   - 1KHz clock output enabled
- *   - 32KHz clock output enabled
- *   - Don't run in STANDBY sleep mode
- *   - Run only when requested by peripheral (on demand)
- *   - Set startup time to 130 cycles
- *   - Don't lock registers after configuration has been written
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void system_clock_source_osc32k_get_config_defaults(
-		struct system_clock_source_osc32k_config *const config)
-{
-	Assert(config);
-
-	config->enable_1khz_output  = true;
-	config->enable_32khz_output = true;
-	config->run_in_standby      = false;
-	config->on_demand           = true;
-	config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
-	config->write_once          = false;
-}
-
-void system_clock_source_osc32k_set_config(
-		struct system_clock_source_osc32k_config *const config);
-
-/**
- * @}
- */
-
-
-/**
- * \name Internal 8MHz Oscillator Management
- * @{
- */
-
-/**
- * \brief Retrieve the default configuration for OSC8M.
- *
- * Fills a configuration structure with the default configuration for an
- * internal 8MHz (nominal) oscillator module:
- *   - Clock output frequency divided by a factor of eight
- *   - Don't run in STANDBY sleep mode
- *   - Run only when requested by peripheral (on demand)
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void system_clock_source_osc8m_get_config_defaults(
-		struct system_clock_source_osc8m_config *const config)
-{
-	Assert(config);
-
-	config->prescaler       = SYSTEM_OSC8M_DIV_8;
-	config->run_in_standby  = false;
-	config->on_demand       = true;
-}
-
-void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config);
-
-/**
- * @}
- */
-
-
-/**
- * \name Internal DFLL Management
- * @{
- */
-
-/**
- * \brief Retrieve the default configuration for DFLL.
- *
- * Fills a configuration structure with the default configuration for a
- * DFLL oscillator module:
- *   - Open loop mode
- *   - QuickLock mode enabled
- *   - Chill cycle enabled
- *   - Output frequency lock maintained during device wake-up
- *   - Continuous tracking of the output frequency
- *   - Default tracking values at the mid-points for both coarse and fine
- *     tracking parameters
- *   - Don't run in STANDBY sleep mode
- *   - Run only when requested by peripheral (on demand)
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void system_clock_source_dfll_get_config_defaults(
-		struct system_clock_source_dfll_config *const config)
-{
-	Assert(config);
-
-	config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
-	config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
-	config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
-	config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
-	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
-	config->on_demand       = true;
-
-	/* Open loop mode calibration value */
-	config->coarse_value    = 0x1f / 4; /* Midpoint */
-	config->fine_value      = 0xff / 4; /* Midpoint */
-
-	/* Closed loop mode */
-	config->coarse_max_step = 1;
-	config->fine_max_step   = 1;
-	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
-}
-
-void system_clock_source_dfll_set_config(
-		struct system_clock_source_dfll_config *const config);
-
-/**
- * @}
- */
-
-/**
- * \name Clock Source Management
- * @{
- */
-enum status_code system_clock_source_write_calibration(
-		const enum system_clock_source system_clock_source,
-		const uint16_t calibration_value,
-		const uint8_t freq_range);
-
-enum status_code system_clock_source_enable(
-		const enum system_clock_source system_clock_source);
-
-enum status_code system_clock_source_disable(
-		const enum system_clock_source clk_source);
-
-bool system_clock_source_is_ready(
-		const enum system_clock_source clk_source);
-
-uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clk_source);
-
-/**
- * @}
- */
-
-/**
- * \name Main Clock Management
- * @{
- */
-
-/**
- * \brief Set main CPU clock divider.
- *
- * Sets the clock divider used on the main clock to provide the CPU clock.
- *
- * \param[in] divider  CPU clock divider to set
- */
-static inline void system_cpu_clock_set_divider(
-		const enum system_main_clock_div divider)
-{
-	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
-	PM->CPUSEL.reg = (uint32_t)divider;
-}
-
-/**
- * \brief Retrieves the current frequency of the CPU core.
- *
- * Retrieves the operating frequency of the CPU core, obtained from the main
- * generic clock and the set CPU bus divider.
- *
- * \return Current CPU frequency in Hz.
- */
-static inline uint32_t system_cpu_clock_get_hz(void)
-{
-	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
-}
-
-/**
- * \brief Set APBx clock divider.
- *
- * Set the clock divider used on the main clock to provide the clock for the
- * given APBx bus.
- *
- * \param[in] divider  APBx bus divider to set
- * \param[in] bus      APBx bus to set divider
- *
- * \returns Status of the clock division change operation.
- *
- * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
- * \retval STATUS_OK               The APBx clock was set successfully
- */
-static inline enum status_code system_apb_clock_set_divider(
-		const enum system_clock_apb_bus bus,
-		const enum system_main_clock_div divider)
-{
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBASEL.reg = (uint32_t)divider;
-			break;
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBSEL.reg = (uint32_t)divider;
-			break;
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCSEL.reg = (uint32_t)divider;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Retrieves the current frequency of a ABPx.
- *
- * Retrieves the operating frequency of an APBx bus, obtained from the main
- * generic clock and the set APBx bus divider.
- *
- * \return Current APBx bus frequency in Hz.
- */
-static inline uint32_t system_apb_clock_get_hz(
-		const enum system_clock_apb_bus bus)
-{
-	uint16_t bus_divider = 0;
-
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			bus_divider = PM->APBASEL.reg;
-			break;
-		case SYSTEM_CLOCK_APB_APBB:
-			bus_divider = PM->APBBSEL.reg;
-			break;
-		case SYSTEM_CLOCK_APB_APBC:
-			bus_divider = PM->APBCSEL.reg;
-			break;
-		default:
-			Assert(false);
-			return 0;
-	}
-
-	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
-}
-
-
-/**
- * @}
- */
-
-/**
- * \name Bus Clock Masking
- * @{
- */
-
-/**
- * \brief Set bits in the clock mask for the AHB bus.
- *
- * This function will set bits in the clock mask for the AHB bus.
- * Any bits set to 1 will enable that clock, 0 bits in the mask
- * will be ignored.
- *
- * \param[in] ahb_mask  AHB clock mask to enable
- */
-static inline void system_ahb_clock_set_mask(
-		const uint32_t ahb_mask)
-{
-	PM->AHBMASK.reg |= ahb_mask;
-}
-
-/**
- * \brief Clear bits in the clock mask for the AHB bus.
- *
- * This function will clear bits in the clock mask for the AHB bus.
- * Any bits set to 1 will disable that clock, 0 bits in the mask
- * will be ignored.
- *
- * \param[in] ahb_mask  AHB clock mask to disable
- */
-static inline void system_ahb_clock_clear_mask(
-		const uint32_t ahb_mask)
-{
-	PM->AHBMASK.reg &= ~ahb_mask;
-}
-
-/**
- * \brief Set bits in the clock mask for an APBx bus.
- *
- * This function will set bits in the clock mask for an APBx bus.
- * Any bits set to 1 will enable the corresponding module clock, zero bits in
- * the mask will be ignored.
- *
- * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
- *                  the device header files
- * \param[in] bus   Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
- *                  constants from the device header files
- *
- * \returns Status indicating the result of the clock mask change operation.
- *
- * \retval STATUS_ERR_INVALID_ARG  Invalid bus given
- * \retval STATUS_OK               The clock mask was set successfully
- */
-static inline enum status_code system_apb_clock_set_mask(
-		const enum system_clock_apb_bus bus,
-		const uint32_t mask)
-{
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBAMASK.reg |= mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg |= mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg |= mask;
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Clear bits in the clock mask for an APBx bus.
- *
- * This function will clear bits in the clock mask for an APBx bus.
- * Any bits set to 1 will disable the corresponding module clock, zero bits in
- * the mask will be ignored.
- *
- * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
- *                  the device header files
- * \param[in] bus   Bus to clear clock mask bits
- *
- * \returns Status indicating the result of the clock mask change operation.
- *
- * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
- * \retval STATUS_OK               The clock mask was changed successfully
- */
-static inline enum status_code system_apb_clock_clear_mask(
-		const enum system_clock_apb_bus bus,
-		const uint32_t mask)
-{
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBAMASK.reg &= ~mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg &= ~mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg &= ~mask;
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * @}
- */
-
-#ifdef FEATURE_SYSTEM_CLOCK_DPLL
-/**
- * \brief Reference clock source of the DPLL module.
- */
-enum system_clock_source_dpll_reference_clock {
-	/** Select XOSC32K as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
-	/** Select XOSC as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
-	/** Select GCLK as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
-};
-
-/**
- * \brief Lock time-out value of the DPLL module.
- */
-enum system_clock_source_dpll_lock_time {
-	/** Set no time-out as default. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
-	/** Set time-out if no lock within 8ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
-	/** Set time-out if no lock within 9ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
-	/** Set time-out if no lock within 10ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
-	/** Set time-out if no lock within 11ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
-};
-
-/**
- * \brief Filter type of the DPLL module.
- */
-enum system_clock_source_dpll_filter {
-	/** Default filter mode. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
-	/** Low bandwidth filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
-	/** High bandwidth filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
-	/** High damping filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
-};
-
-/**
- * \brief Configuration structure for DPLL.
- *
- * DPLL oscillator configuration structure.
- */
-struct system_clock_source_dpll_config {
-	/** Run On Demand. If this is set the DPLL won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Keep the DPLL enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Bypass lock signal. */
-	bool lock_bypass;
-	/** Wake up fast. If this is set DPLL output clock is enabled after
-	 * the startup time. */
-	bool wake_up_fast;
-	/** Enable low power mode.  */
-	bool low_power_enable;
-
-	/** Output frequency of the clock. */
-	uint32_t output_frequency;
-	/** Reference frequency of the clock. */
-	uint32_t reference_frequency;
-	/** Devider of reference clock. */
-	uint16_t reference_divider;
-
-	/** Filter type of the DPLL module. */
-	enum system_clock_source_dpll_filter          filter;
-	/** Lock time-out value of the DPLL module. */
-	enum system_clock_source_dpll_lock_time       lock_time;
-	/** Reference clock source of the DPLL module. */
-	enum system_clock_source_dpll_reference_clock reference_clock;
-};
-
-/**
- * \name Internal DPLL Management
- * @{
- */
-
-/**
- * \brief Retrieve the default configuration for DPLL.
- *
- * Fills a configuration structure with the default configuration for a
- * DPLL oscillator module:
- *   - Run only when requested by peripheral (on demand)
- *   - Don't run in STANDBY sleep mode
- *   - Lock bypass disabled
- *   - Fast wake up disabled
- *   - Low power mode disabled
- *   - Output frequency is 48MHz
- *   - Reference clock frequency is 32768Hz
- *   - Not divide reference clock
- *   - Select REF0 as reference clock
- *   - Set lock time to default mode
- *   - Use default filter
- *
- * \param[out] config  Configuration structure to fill with default values
- */
-static inline void system_clock_source_dpll_get_config_defaults(
-		struct system_clock_source_dpll_config *const config)
-{
-	config->on_demand           = true;
-	config->run_in_standby      = false;
-	config->lock_bypass         = false;
-	config->wake_up_fast        = false;
-	config->low_power_enable    = false;
-
-	config->output_frequency    = 48000000;
-	config->reference_frequency = 32768;
-	config->reference_divider   = 1;
-	config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
-
-	config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
-	config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
-};
-
-void system_clock_source_dpll_set_config(
-		struct system_clock_source_dpll_config *const config);
-
-/* @} */
-#endif
-
-/**
- * \name System Clock Initialization
- * @{
- */
-
-void system_clock_init(void);
-
-/**
- * @}
- */
-
-/**
- * \name System Flash Wait States
- * @{
- */
-
-/**
- * \brief Set flash controller wait states.
- *
- * Will set the number of wait states that are used by the onboard
- * flash memory. The number of wait states depend on both device
- * supply voltage and CPU speed. The required number of wait states
- * can be found in the electrical characteristics of the device.
- *
- * \param[in] wait_states Number of wait states to use for internal flash
- */
-static inline void system_flash_set_waitstates(uint8_t wait_states)
-{
-	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
-			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
-
-	NVMCTRL->CTRLB.bit.RWS = wait_states;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
- *
- * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
- * Below is a table listing the acronyms used in this module, along with their
- * intended meanings.
- *
- * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>DFLL</td>
- *		<td>Digital Frequency Locked Loop</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
- *	<tr>
- *		<td>OSC32K</td>
- *		<td>Internal 32KHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>OSC8M</td>
- *		<td>Internal 8MHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>PLL</td>
- *		<td>Phase Locked Loop</td>
- *	</tr>
- *	<tr>
- *		<td>OSC</td>
- *		<td>Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>XOSC</td>
- *		<td>External Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>XOSC32K</td>
- *		<td>External 32KHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>AHB</td>
- *		<td>Advanced High-performance Bus</td>
- *	</tr>
- *	<tr>
- *		<td>APB</td>
- *		<td>Advanced Peripheral Bus</td>
- *	</tr>
- *	<tr>
- *		<td>DPLL</td>
- *		<td>Digital Phase Locked Loop</td>
- *	</tr>
- * </table>
- *
- *
- * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- *  - None
- *
- *
- * \section asfdoc_sam0_system_clock_extra_errata Errata
- *
- *	- This driver implements experimental workaround for errata 9905
- *
- *	  "The DFLL clock must be requested before being configured otherwise a
- *	  write access to a DFLL register can freeze the device."
- *	  This driver will enable and configure the DFLL before the ONDEMAND bit is set.
- *
- *
- * \section asfdoc_sam0_system_clock_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>
- *			\li Corrected OSC32K startup time definitions
- *			\li Support locking of OSC32K and XOSC32K config register (default: false)
- *			\li Added DPLL support, functions added:
- *			    \c system_clock_source_dpll_get_config_defaults() and
- *		        \c system_clock_source_dpll_set_config()
- *			\li Moved gclk channel locking feature out of the config struct
- *			    functions added:
- *			    \c system_gclk_chan_lock(),
- *			    \c system_gclk_chan_is_locked()
- *			    \c system_gclk_chan_is_enabled() and
- *			    \c system_gclk_gen_is_enabled()
- *		</td>
- *	</tr>
- *  <tr>
- *		<td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
- *		    and configured to a failed/not running clock generator</td>
- *  </tr>
- *	<tr>
- *		<td>
- *			\li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
- *			\li Fixed system_flash_set_waitstates() failing with an assertion
- *			    if an odd number of wait states provided
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>
- *			\li Updated DFLL configuration function to implement workaround for
- *			    errata 9905 in the DFLL module
- *			\li Updated \c system_clock_init() to reset interrupt flags before
- *			    they are used
- *			\li Fixed \c system_clock_source_get_hz() to return correcy DFLL
- *			    frequency number
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>\li Fixed \c system_clock_source_is_ready not returning the correct
- *              state for \c SYSTEM_CLOCK_SOURCE_OSC8M
- *          \li Renamed the various \c system_clock_source_*_get_default_config()
- *              functions to \c system_clock_source_*_get_config_defaults() to
- *              match the remainder of ASF
- *          \li Added OSC8M calibration constant loading from the device signature
- *              row when the oscillator is initialized
- *          \li Updated default configuration of the XOSC32 to disable Automatic
- *              Gain Control due to silicon errata
- *      </td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
- * </table>
- */
-
-/**
- * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
- *
- * This is a list of the available Quick Start guides (QSGs) and example
- * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
- * examples with step-by-step instructions to configure and use this driver in
- * a selection of use cases. Note that a QSG can be compiled as a standalone
- * application or be added to the user application.
- *
- *  - \subpage asfdoc_sam0_system_clock_basic_use_case
- *  - \subpage asfdoc_sam0_system_gclk_basic_use_case
- *
- * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
- *
- * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42119E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM DA1 and SAM D09</td>
- *	</tr>
- *	<tr>
- *		<td>42119D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42119C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42119B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos. Fixed missing steps in the Basic
- *          Use Case Quick Start Guide</td>
- *	</tr>
- *	<tr>
- *		<td>42119A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
- * </table>
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
+#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's clocking related functions. This includes
+ * the various clock sources, bus clocks, and generic clocks within the device,
+ * with functions to manage the enabling, disabling, source selection, and
+ * prescaling of clocks to various internal peripherals.
+ *
+ * The following peripherals are used by this module:
+ *
+ * - GCLK (Generic Clock Management)
+ * - PM (Power Management)
+ * - SYSCTRL (Clock Source Control)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM HA1
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_clock_prerequisites
+ *  - \ref asfdoc_sam0_system_clock_module_overview
+ *  - \ref asfdoc_sam0_system_clock_special_considerations
+ *  - \ref asfdoc_sam0_system_clock_extra_info
+ *  - \ref asfdoc_sam0_system_clock_examples
+ *  - \ref asfdoc_sam0_system_clock_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_clock_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_module_overview Module Overview
+ * The SAM devices contain a sophisticated clocking system, which is designed
+ * to give the maximum flexibility to the user application. This system allows
+ * a system designer to tune the performance and power consumption of the device
+ * in a dynamic manner, to achieve the best trade-off between the two for a
+ * particular application.
+ *
+ * This driver provides a set of functions for the configuration and management
+ * of the various clock related functionality within the device.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
+ * <table>
+ *	<tr>
+ *		<th>Driver Feature Macro</th>
+ *		<th>Supported devices</th>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ *		<td>SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1</td>
+ *	</tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
+ * The SAM devices have a number of master clock source modules, each of
+ * which being capable of producing a stabilized output frequency, which can then
+ * be fed into the various peripherals and modules within the device.
+ *
+ * Possible clock source modules include internal R/C oscillators, internal
+ * DFLL modules, as well as external crystal oscillators and/or clock inputs.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
+ * The CPU and AHB/APBx buses are clocked by the same physical clock source
+ * (referred in this module as the Main Clock), however the APBx buses may
+ * have additional prescaler division ratios set to give each peripheral bus a
+ * different clock speed.
+ *
+ * The general main clock tree for the CPU and associated buses is shown in
+ * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_clock_tree
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   clk_src [label="Clock Sources", shape=none, height=0];
+ *   node [label="CPU Bus" shape=ellipse] cpu_bus;
+ *   node [label="AHB Bus" shape=ellipse] ahb_bus;
+ *   node [label="APBA Bus" shape=ellipse] apb_a_bus;
+ *   node [label="APBB Bus" shape=ellipse] apb_b_bus;
+ *   node [label="APBC Bus" shape=ellipse] apb_c_bus;
+ *   node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
+ *   node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
+ *   node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
+ *   node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
+ *   node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
+ *
+ *   clk_src         -> main_clock_mux;
+ *   main_clock_mux  -> main_prescaler;
+ *   main_prescaler  -> cpu_bus;
+ *   main_prescaler  -> ahb_bus;
+ *   main_prescaler  -> apb_a_prescaler;
+ *   main_prescaler  -> apb_b_prescaler;
+ *   main_prescaler  -> apb_c_prescaler;
+ *   apb_a_prescaler -> apb_a_bus;
+ *   apb_b_prescaler -> apb_b_bus;
+ *   apb_c_prescaler -> apb_c_bus;
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
+ * To save power, the input clock to one or more peripherals on the AHB and APBx
+ * buses can be masked away - when masked, no clock is passed into the module.
+ * Disabling of clocks of unused modules will prevent all access to the masked
+ * module, but will reduce the overall device power consumption.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
+ * Within the SAM devices there are a number of Generic Clocks; these are used to
+ * provide clocks to the various peripheral clock domains in the device in a
+ * standardized manner. One or more master source clocks can be selected as the
+ * input clock to a Generic Clock Generator, which can prescale down the input
+ * frequency to a slower rate for use in a peripheral.
+ *
+ * Additionally, a number of individually selectable Generic Clock Channels are
+ * provided, which multiplex and gate the various generator outputs for one or
+ * more peripherals within the device. This setup allows for a single common
+ * generator to feed one or more channels, which can then be enabled or disabled
+ * individually as required.
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_overview
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="Clock\nSource a" shape=square] system_clock_source;
+ *   node [label="Generator 1" shape=square] clock_gen;
+ *   node [label="Channel x" shape=square] clock_chan0;
+ *   node [label="Channel y" shape=square] clock_chan1;
+ *   node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ *   node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ *
+ *   system_clock_source -> clock_gen;
+ *   clock_gen   -> clock_chan0;
+ *   clock_chan0 -> peripheral0;
+ *   clock_gen   -> clock_chan1;
+ *   clock_chan1 -> peripheral1;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
+ * An example setup of a complete clock chain within the device is shown in
+ * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_example_fig
+ * \dot
+ * digraph overview {
+ *   rankdir=LR;
+ *   node [label="External\nOscillator" shape=square] system_clock_source0;
+ *   node [label="Generator 0" shape=square] clock_gen0;
+ *   node [label="Channel x" shape=square] clock_chan0;
+ *   node [label="Core CPU" shape=ellipse  style=filled fillcolor=lightgray] peripheral0;
+ *
+ *   system_clock_source0 -> clock_gen0;
+ *   clock_gen0    -> clock_chan0;
+ *   clock_chan0   -> peripheral0;
+ *   node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
+ *   node [label="Generator 1" shape=square] clock_gen1;
+ *   node [label="Channel y" shape=square] clock_chan1;
+ *   node [label="Channel z" shape=square] clock_chan2;
+ *   node [label="SERCOM\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral1;
+ *   node [label="Timer\nModule" shape=ellipse  style=filled fillcolor=lightgray] peripheral2;
+ *
+ *   system_clock_source1 -> clock_gen1;
+ *   clock_gen1    -> clock_chan1;
+ *   clock_gen1    -> clock_chan2;
+ *   clock_chan1   -> peripheral1;
+ *   clock_chan2   -> peripheral2;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
+ * Each Generic Clock generator within the device can source its input clock
+ * from one of the provided Source Clocks, and prescale the output for one or
+ * more Generic Clock Channels in a one-to-many relationship. The generators
+ * thus allow for several clocks to be generated of different frequencies,
+ * power usages, and accuracies, which can be turned on and off individually to
+ * disable the clocks to multiple peripherals as a group.
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
+ * To connect a Generic Clock Generator to a peripheral within the
+ * device, a Generic Clock Channel is used. Each peripheral or
+ * peripheral group has an associated Generic Clock Channel, which serves as the
+ * clock input for the peripheral(s). To supply a clock to the peripheral
+ * module(s), the associated channel must be connected to a running Generic
+ * Clock Generator and the channel enabled.
+ *
+ * \section asfdoc_sam0_system_clock_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
+ *  - \ref asfdoc_sam0_system_clock_extra_acronyms
+ *  - \ref asfdoc_sam0_system_clock_extra_dependencies
+ *  - \ref asfdoc_sam0_system_clock_extra_errata
+ *  - \ref asfdoc_sam0_system_clock_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_clock_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_clock_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <gclk.h>
+
+/**
+ * \name Driver Feature Definition
+ * Define system clock features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || (SAMHA1) || (SAMHA0) || defined(__DOXYGEN__)
+/** Digital Phase Locked Loop (DPLL) feature support. */
+#  define FEATURE_SYSTEM_CLOCK_DPLL
+#endif
+/*@}*/
+
+/**
+ * \brief Available start-up times for the XOSC32K.
+ *
+ * Available external 32KHz oscillator start-up times, as a number of external
+ * clock cycles.
+ */
+enum system_xosc32k_startup {
+	/** Wait zero clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_0,
+	/** Wait 32 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_32,
+	/** Wait 2048 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_2048,
+	/** Wait 4096 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_4096,
+	/** Wait 16384 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_16384,
+	/** Wait 32768 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_32768,
+	/** Wait 65536 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_65536,
+	/** Wait 131072 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC32K_STARTUP_131072,
+};
+
+/**
+ * \brief Available start-up times for the XOSC.
+ *
+ * Available external oscillator start-up times, as a number of external clock
+ * cycles.
+ */
+enum system_xosc_startup {
+	/** Wait one clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_1,
+	/** Wait two clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_2,
+	/** Wait four clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_4,
+	/** Wait eight clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_8,
+	/** Wait 16 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_16,
+	/** Wait 32 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_32,
+	/** Wait 64 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_64,
+	/** Wait 128 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_128,
+	/** Wait 256 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_256,
+	/** Wait 512 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_512,
+	/** Wait 1024 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_1024,
+	/** Wait 2048 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_2048,
+	/** Wait 4096 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_4096,
+	/** Wait 8192 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_8192,
+	/** Wait 16384 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_16384,
+	/** Wait 32768 clock cycles until the clock source is considered stable */
+	SYSTEM_XOSC_STARTUP_32768,
+};
+
+/**
+ * \brief Available start-up times for the OSC32K.
+ *
+ * Available internal 32KHz oscillator start-up times, as a number of internal
+ * OSC32K clock cycles.
+ */
+enum system_osc32k_startup {
+	/** Wait three clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_3,
+	/** Wait four clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_4,
+	/** Wait six clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_6,
+	/** Wait ten clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_10,
+	/** Wait 18 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_18,
+	/** Wait 34 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_34,
+	/** Wait 66 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_66,
+	/** Wait 130 clock cycles until the clock source is considered stable */
+	SYSTEM_OSC32K_STARTUP_130,
+};
+
+/**
+ * \brief Division prescalers for the internal 8MHz system clock.
+ *
+ * Available prescalers for the internal 8MHz (nominal) system clock.
+ */
+enum system_osc8m_div {
+	/** Do not divide the 8MHz RC oscillator output */
+	SYSTEM_OSC8M_DIV_1,
+	/** Divide the 8MHz RC oscillator output by two */
+	SYSTEM_OSC8M_DIV_2,
+	/** Divide the 8MHz RC oscillator output by four */
+	SYSTEM_OSC8M_DIV_4,
+	/** Divide the 8MHz RC oscillator output by eight */
+	SYSTEM_OSC8M_DIV_8,
+};
+
+/**
+ * \brief Frequency range for the internal 8MHz RC oscillator.
+ *
+ * Internal 8MHz RC oscillator frequency range setting.
+ */
+enum system_osc8m_frequency_range {
+	/** Frequency range 4MHz to 6MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+	/** Frequency range 6MHz to 8MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+	/** Frequency range 8MHz to 11MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+	/** Frequency range 11MHz to 15MHz */
+	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+};
+
+/**
+ * \brief Main CPU and APB/AHB bus clock source prescaler values.
+ *
+ * Available division ratios for the CPU and APB/AHB bus clocks.
+ */
+enum system_main_clock_div {
+	/** Divide Main clock by one */
+	SYSTEM_MAIN_CLOCK_DIV_1,
+	/** Divide Main clock by two */
+	SYSTEM_MAIN_CLOCK_DIV_2,
+	/** Divide Main clock by four */
+	SYSTEM_MAIN_CLOCK_DIV_4,
+	/** Divide Main clock by eight */
+	SYSTEM_MAIN_CLOCK_DIV_8,
+	/** Divide Main clock by 16 */
+	SYSTEM_MAIN_CLOCK_DIV_16,
+	/** Divide Main clock by 32 */
+	SYSTEM_MAIN_CLOCK_DIV_32,
+	/** Divide Main clock by 64 */
+	SYSTEM_MAIN_CLOCK_DIV_64,
+	/** Divide Main clock by 128 */
+	SYSTEM_MAIN_CLOCK_DIV_128,
+};
+
+/**
+ * \brief External clock source types.
+ *
+ * Available external clock source types.
+ */
+enum system_clock_external {
+	/** The external clock source is a crystal oscillator */
+	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+	/** The connected clock source is an external logic level clock signal */
+	SYSTEM_CLOCK_EXTERNAL_CLOCK,
+};
+
+/**
+ * \brief Operating modes of the DFLL clock source.
+ *
+ * Available operating modes of the DFLL clock source module.
+ */
+enum system_clock_dfll_loop_mode {
+	/** The DFLL is operating in open loop mode with no feedback */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+	/** The DFLL is operating in closed loop mode with frequency feedback from
+	 *  a low frequency reference clock
+	 */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+
+#ifdef SYSCTRL_DFLLCTRL_USBCRM
+	/** The DFLL is operating in USB recovery mode with frequency feedback
+	 *  from USB SOF.
+	 */
+	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+#endif
+};
+
+/**
+ * \brief Locking behavior for the DFLL during device wake-up.
+ *
+ * DFLL lock behavior modes on device wake-up from sleep.
+ */
+enum system_clock_dfll_wakeup_lock {
+	/** Keep DFLL lock when the device wakes from sleep */
+	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+	/** Lose DFLL lock when the devices wakes from sleep */
+	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+};
+
+/**
+ * \brief Fine tracking behavior for the DFLL once a lock has been acquired.
+ *
+ * DFLL fine tracking behavior modes after a lock has been acquired.
+ */
+enum system_clock_dfll_stable_tracking {
+	/** Keep tracking after the DFLL has gotten a fine lock */
+	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+	/** Stop tracking after the DFLL has gotten a fine lock */
+	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+};
+
+/**
+ * \brief Chill-cycle behavior of the DFLL module.
+ *
+ * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
+ * of time when the DFLL output frequency is not measured by the unit, to allow
+ * the output to stabilize after a change in the input clock source.
+ */
+enum system_clock_dfll_chill_cycle {
+	/** Enable a chill cycle, where the DFLL output frequency is not measured */
+	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+	/** Disable a chill cycle, where the DFLL output frequency is not measured */
+	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+};
+
+/**
+ * \brief QuickLock settings for the DFLL module.
+ *
+ * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
+ * the DFLL output frequency at the expense of accuracy.
+ */
+enum system_clock_dfll_quick_lock {
+	/** Enable the QuickLock feature for looser lock requirements on the DFLL */
+	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+	/** Disable the QuickLock feature for strict lock requirements on the DFLL */
+	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+};
+
+/**
+ * \brief Available clock sources in the system.
+ *
+ * Clock sources available to the GCLK generators.
+ */
+enum system_clock_source {
+	/** Internal 8MHz RC oscillator */
+	SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
+	/** Internal 32KHz RC oscillator */
+	SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
+	/** External oscillator */
+	SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
+	/** External 32KHz oscillator */
+	SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
+	/** Digital Frequency Locked Loop (DFLL) */
+	SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
+	/** Internal Ultra Low Power 32KHz oscillator */
+	SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
+	/** Generator input pad */
+	SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
+	/** Generic clock generator one output */
+	SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+	/** Digital Phase Locked Loop (DPLL).
+	 * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+	 */
+	SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
+#endif
+};
+
+/**
+ * \brief List of APB peripheral buses.
+ *
+ * Available bus clock domains on the APB bus.
+ */
+enum system_clock_apb_bus {
+	/** Peripheral bus A on the APB bus */
+	SYSTEM_CLOCK_APB_APBA,
+	/** Peripheral bus B on the APB bus */
+	SYSTEM_CLOCK_APB_APBB,
+	/** Peripheral bus C on the APB bus */
+	SYSTEM_CLOCK_APB_APBC,
+};
+
+/**
+ * \brief Configuration structure for XOSC.
+ *
+ * External oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc_config {
+	/** External clock type */
+	enum system_clock_external external_clock;
+	/** Crystal oscillator start-up time */
+	enum system_xosc_startup startup_time;
+	/** Enable automatic amplitude gain control */
+	bool auto_gain_control;
+	/** External clock/crystal frequency */
+	uint32_t frequency;
+	/** Keep the XOSC enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the XOSC won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for XOSC32K.
+ *
+ * External 32KHz oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc32k_config {
+	/** External clock type */
+	enum system_clock_external external_clock;
+	/** Crystal oscillator start-up time */
+	enum system_xosc32k_startup startup_time;
+	/** Enable automatic amplitude control */
+	bool auto_gain_control;
+	/** Enable 1KHz output */
+	bool enable_1khz_output;
+	/** Enable 32KHz output */
+	bool enable_32khz_output;
+	/** External clock/crystal frequency */
+	uint32_t frequency;
+	/** Keep the XOSC32K enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the XOSC32K won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Lock configuration after it has been written,
+	 *  a device reset will release the lock */
+	bool write_once;
+};
+
+/**
+ * \brief Configuration structure for OSC8M.
+ *
+ * Internal 8MHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc8m_config {
+	/** Internal 8MHz RC oscillator prescaler */
+	enum system_osc8m_div prescaler;
+	/** Keep the OSC8M enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the OSC8M won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for OSC32K.
+ *
+ * Internal 32KHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc32k_config {
+	/** Startup time */
+	enum system_osc32k_startup startup_time;
+	/** Enable 1KHz output */
+	bool enable_1khz_output;
+	/** Enable 32KHz output */
+	bool enable_32khz_output;
+	/** Keep the OSC32K enabled in standby sleep mode */
+	bool run_in_standby;
+	/** Run On Demand. If this is set the OSC32K won't run
+	 * until requested by a peripheral */
+	bool on_demand;
+	/** Lock configuration after it has been written,
+	 *  a device reset will release the lock */
+	bool write_once;
+};
+
+/**
+ * \brief Configuration structure for DFLL.
+ *
+ * DFLL oscillator configuration structure.
+ */
+struct system_clock_source_dfll_config {
+	/** Loop mode */
+	enum system_clock_dfll_loop_mode loop_mode;
+	/** Run On Demand. If this is set the DFLL won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Enable Quick Lock */
+	enum system_clock_dfll_quick_lock quick_lock;
+	/** Enable Chill Cycle */
+	enum system_clock_dfll_chill_cycle chill_cycle;
+	/** DFLL lock state on wakeup */
+	enum system_clock_dfll_wakeup_lock wakeup_lock;
+	/** DFLL tracking after fine lock */
+	enum system_clock_dfll_stable_tracking stable_tracking;
+	/** Coarse calibration value (Open loop mode) */
+	uint8_t coarse_value;
+	/** Fine calibration value (Open loop mode) */
+	uint16_t fine_value;
+	/** Coarse adjustment maximum step size (Closed loop mode) */
+	uint8_t coarse_max_step;
+	/** Fine adjustment maximum step size (Closed loop mode) */
+	uint16_t fine_max_step;
+	/** DFLL multiply factor (Closed loop mode */
+	uint16_t multiply_factor;
+};
+
+/**
+ * \name External Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external oscillator module:
+ *   - External Crystal
+ *   - Start-up time of 16384 external clock cycles
+ *   - Automatic crystal gain control mode disabled
+ *   - Frequency of 12MHz
+ *   - Don't run in STANDBY sleep mode
+ *   - Run when it's enabled (not on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc_get_config_defaults(
+		struct system_clock_source_xosc_config *const config)
+{
+	Assert(config);
+
+	config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+	config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
+	config->auto_gain_control = false;
+	config->frequency         = 12000000UL;
+	config->run_in_standby    = false;
+	config->on_demand         = false;
+}
+
+void system_clock_source_xosc_set_config(
+		struct system_clock_source_xosc_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name External 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external 32KHz oscillator module:
+ *   - External Crystal
+ *   - Start-up time of 16384 external clock cycles
+ *   - Automatic crystal gain control mode disabled
+ *   - Frequency of 32.768KHz
+ *   - 1KHz clock output disabled
+ *   - 32KHz clock output enabled
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *   - Don't lock registers after configuration has been written
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc32k_get_config_defaults(
+		struct system_clock_source_xosc32k_config *const config)
+{
+	Assert(config);
+
+	config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+	config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
+	config->auto_gain_control   = false;
+	config->frequency           = 32768UL;
+	config->enable_1khz_output  = false;
+	config->enable_32khz_output = true;
+	config->run_in_standby      = false;
+	config->on_demand           = true;
+	config->write_once          = false;
+}
+
+void system_clock_source_xosc32k_set_config(
+		struct system_clock_source_xosc32k_config *const config);
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 32KHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC32K.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 32KHz oscillator module:
+ *   - 1KHz clock output enabled
+ *   - 32KHz clock output enabled
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *   - Set startup time to 130 cycles
+ *   - Don't lock registers after configuration has been written
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc32k_get_config_defaults(
+		struct system_clock_source_osc32k_config *const config)
+{
+	Assert(config);
+
+	config->enable_1khz_output  = true;
+	config->enable_32khz_output = true;
+	config->run_in_standby      = false;
+	config->on_demand           = true;
+	config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
+	config->write_once          = false;
+}
+
+void system_clock_source_osc32k_set_config(
+		struct system_clock_source_osc32k_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 8MHz Oscillator Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC8M.
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 8MHz (nominal) oscillator module:
+ *   - Clock output frequency divided by a factor of eight
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc8m_get_config_defaults(
+		struct system_clock_source_osc8m_config *const config)
+{
+	Assert(config);
+
+	config->prescaler       = SYSTEM_OSC8M_DIV_8;
+	config->run_in_standby  = false;
+	config->on_demand       = true;
+}
+
+void system_clock_source_osc8m_set_config(
+		struct system_clock_source_osc8m_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal DFLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DFLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DFLL oscillator module:
+ *   - Open loop mode
+ *   - QuickLock mode enabled
+ *   - Chill cycle enabled
+ *   - Output frequency lock maintained during device wake-up
+ *   - Continuous tracking of the output frequency
+ *   - Default tracking values at the mid-points for both coarse and fine
+ *     tracking parameters
+ *   - Don't run in STANDBY sleep mode
+ *   - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dfll_get_config_defaults(
+		struct system_clock_source_dfll_config *const config)
+{
+	Assert(config);
+
+	config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+	config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+	config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+	config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+	config->on_demand       = true;
+
+	/* Open loop mode calibration value */
+	config->coarse_value    = 0x1f / 4; /* Midpoint */
+	config->fine_value      = 0xff / 4; /* Midpoint */
+
+	/* Closed loop mode */
+	config->coarse_max_step = 1;
+	config->fine_max_step   = 1;
+	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+}
+
+void system_clock_source_dfll_set_config(
+		struct system_clock_source_dfll_config *const config);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Clock Source Management
+ * @{
+ */
+enum status_code system_clock_source_write_calibration(
+		const enum system_clock_source system_clock_source,
+		const uint16_t calibration_value,
+		const uint8_t freq_range);
+
+enum status_code system_clock_source_enable(
+		const enum system_clock_source system_clock_source);
+
+enum status_code system_clock_source_disable(
+		const enum system_clock_source clk_source);
+
+bool system_clock_source_is_ready(
+		const enum system_clock_source clk_source);
+
+uint32_t system_clock_source_get_hz(
+		const enum system_clock_source clk_source);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Main Clock Management
+ * @{
+ */
+
+/**
+ * \brief Set main CPU clock divider.
+ *
+ * Sets the clock divider used on the main clock to provide the CPU clock.
+ *
+ * \param[in] divider  CPU clock divider to set
+ */
+static inline void system_cpu_clock_set_divider(
+		const enum system_main_clock_div divider)
+{
+	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+	PM->CPUSEL.reg = (uint32_t)divider;
+}
+
+/**
+ * \brief Retrieves the current frequency of the CPU core.
+ *
+ * Retrieves the operating frequency of the CPU core, obtained from the main
+ * generic clock and the set CPU bus divider.
+ *
+ * \return Current CPU frequency in Hz.
+ */
+static inline uint32_t system_cpu_clock_get_hz(void)
+{
+	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+}
+
+/**
+ * \brief Set APBx clock divider.
+ *
+ * Set the clock divider used on the main clock to provide the clock for the
+ * given APBx bus.
+ *
+ * \param[in] divider  APBx bus divider to set
+ * \param[in] bus      APBx bus to set divider
+ *
+ * \returns Status of the clock division change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
+ * \retval STATUS_OK               The APBx clock was set successfully
+ */
+static inline enum status_code system_apb_clock_set_divider(
+		const enum system_clock_apb_bus bus,
+		const enum system_main_clock_div divider)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBASEL.reg = (uint32_t)divider;
+			break;
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBSEL.reg = (uint32_t)divider;
+			break;
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCSEL.reg = (uint32_t)divider;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the current frequency of a ABPx.
+ *
+ * Retrieves the operating frequency of an APBx bus, obtained from the main
+ * generic clock and the set APBx bus divider.
+ *
+ * \return Current APBx bus frequency in Hz.
+ */
+static inline uint32_t system_apb_clock_get_hz(
+		const enum system_clock_apb_bus bus)
+{
+	uint16_t bus_divider = 0;
+
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			bus_divider = PM->APBASEL.reg;
+			break;
+		case SYSTEM_CLOCK_APB_APBB:
+			bus_divider = PM->APBBSEL.reg;
+			break;
+		case SYSTEM_CLOCK_APB_APBC:
+			bus_divider = PM->APBCSEL.reg;
+			break;
+		default:
+			Assert(false);
+			return 0;
+	}
+
+	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * \name Bus Clock Masking
+ * @{
+ */
+
+/**
+ * \brief Set bits in the clock mask for the AHB bus.
+ *
+ * This function will set bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will enable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask  AHB clock mask to enable
+ */
+static inline void system_ahb_clock_set_mask(
+		const uint32_t ahb_mask)
+{
+	PM->AHBMASK.reg |= ahb_mask;
+}
+
+/**
+ * \brief Clear bits in the clock mask for the AHB bus.
+ *
+ * This function will clear bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will disable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask  AHB clock mask to disable
+ */
+static inline void system_ahb_clock_clear_mask(
+		const uint32_t ahb_mask)
+{
+	PM->AHBMASK.reg &= ~ahb_mask;
+}
+
+/**
+ * \brief Set bits in the clock mask for an APBx bus.
+ *
+ * This function will set bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will enable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ *                  the device header files
+ * \param[in] bus   Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
+ *                  constants from the device header files
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus given
+ * \retval STATUS_OK               The clock mask was set successfully
+ */
+static inline enum status_code system_apb_clock_set_mask(
+		const enum system_clock_apb_bus bus,
+		const uint32_t mask)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBAMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg |= mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg |= mask;
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Clear bits in the clock mask for an APBx bus.
+ *
+ * This function will clear bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will disable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask  APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ *                  the device header files
+ * \param[in] bus   Bus to clear clock mask bits
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid bus ID was given
+ * \retval STATUS_OK               The clock mask was changed successfully
+ */
+static inline enum status_code system_apb_clock_clear_mask(
+		const enum system_clock_apb_bus bus,
+		const uint32_t mask)
+{
+	switch (bus) {
+		case SYSTEM_CLOCK_APB_APBA:
+			PM->APBAMASK.reg &= ~mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBB:
+			PM->APBBMASK.reg &= ~mask;
+			break;
+
+		case SYSTEM_CLOCK_APB_APBC:
+			PM->APBCMASK.reg &= ~mask;
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * @}
+ */
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Reference clock source of the DPLL module.
+ */
+enum system_clock_source_dpll_reference_clock {
+	/** Select XOSC32K as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
+	/** Select XOSC as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
+	/** Select GCLK as clock reference. */
+	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+};
+
+/**
+ * \brief Lock time-out value of the DPLL module.
+ */
+enum system_clock_source_dpll_lock_time {
+	/** Set no time-out as default. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+	/** Set time-out if no lock within 8ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+	/** Set time-out if no lock within 9ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+	/** Set time-out if no lock within 10ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+	/** Set time-out if no lock within 11ms. */
+	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+};
+
+/**
+ * \brief Filter type of the DPLL module.
+ */
+enum system_clock_source_dpll_filter {
+	/** Default filter mode. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+	/** Low bandwidth filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+	/** High bandwidth filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+	/** High damping filter. */
+	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+};
+
+/**
+ * \brief Configuration structure for DPLL.
+ *
+ * DPLL oscillator configuration structure.
+ */
+struct system_clock_source_dpll_config {
+	/** Run On Demand. If this is set the DPLL won't run
+	 * until requested by a peripheral. */
+	bool on_demand;
+	/** Keep the DPLL enabled in standby sleep mode. */
+	bool run_in_standby;
+	/** Bypass lock signal. */
+	bool lock_bypass;
+	/** Wake up fast. If this is set DPLL output clock is enabled after
+	 * the startup time. */
+	bool wake_up_fast;
+	/** Enable low power mode.  */
+	bool low_power_enable;
+
+	/** Output frequency of the clock. */
+	uint32_t output_frequency;
+	/** Reference frequency of the clock. */
+	uint32_t reference_frequency;
+	/** Devider of reference clock. */
+	uint16_t reference_divider;
+
+	/** Filter type of the DPLL module. */
+	enum system_clock_source_dpll_filter          filter;
+	/** Lock time-out value of the DPLL module. */
+	enum system_clock_source_dpll_lock_time       lock_time;
+	/** Reference clock source of the DPLL module. */
+	enum system_clock_source_dpll_reference_clock reference_clock;
+};
+
+/**
+ * \name Internal DPLL Management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DPLL.
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DPLL oscillator module:
+ *   - Run only when requested by peripheral (on demand)
+ *   - Don't run in STANDBY sleep mode
+ *   - Lock bypass disabled
+ *   - Fast wake up disabled
+ *   - Low power mode disabled
+ *   - Output frequency is 48MHz
+ *   - Reference clock frequency is 32768Hz
+ *   - Not divide reference clock
+ *   - Select REF0 as reference clock
+ *   - Set lock time to default mode
+ *   - Use default filter
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dpll_get_config_defaults(
+		struct system_clock_source_dpll_config *const config)
+{
+	config->on_demand           = true;
+	config->run_in_standby      = false;
+	config->lock_bypass         = false;
+	config->wake_up_fast        = false;
+	config->low_power_enable    = false;
+
+	config->output_frequency    = 48000000;
+	config->reference_frequency = 32768;
+	config->reference_divider   = 1;
+	config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
+
+	config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+	config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+};
+
+void system_clock_source_dpll_set_config(
+		struct system_clock_source_dpll_config *const config);
+
+/* @} */
+#endif
+
+/**
+ * \name System Clock Initialization
+ * @{
+ */
+
+void system_clock_init(void);
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Flash Wait States
+ * @{
+ */
+
+/**
+ * \brief Set flash controller wait states.
+ *
+ * Will set the number of wait states that are used by the onboard
+ * flash memory. The number of wait states depend on both device
+ * supply voltage and CPU speed. The required number of wait states
+ * can be found in the electrical characteristics of the device.
+ *
+ * \param[in] wait_states Number of wait states to use for internal flash
+ */
+static inline void system_flash_set_waitstates(uint8_t wait_states)
+{
+	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+
+	NVMCTRL->CTRLB.bit.RWS = wait_states;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
+ *
+ * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>DFLL</td>
+ *		<td>Digital Frequency Locked Loop</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC32K</td>
+ *		<td>Internal 32KHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC8M</td>
+ *		<td>Internal 8MHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>PLL</td>
+ *		<td>Phase Locked Loop</td>
+ *	</tr>
+ *	<tr>
+ *		<td>OSC</td>
+ *		<td>Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>XOSC</td>
+ *		<td>External Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>XOSC32K</td>
+ *		<td>External 32KHz Oscillator</td>
+ *	</tr>
+ *	<tr>
+ *		<td>AHB</td>
+ *		<td>Advanced High-performance Bus</td>
+ *	</tr>
+ *	<tr>
+ *		<td>APB</td>
+ *		<td>Advanced Peripheral Bus</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DPLL</td>
+ *		<td>Digital Phase Locked Loop</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_errata Errata
+ *
+ *	- This driver implements experimental workaround for errata 9905
+ *
+ *	  "The DFLL clock must be requested before being configured otherwise a
+ *	  write access to a DFLL register can freeze the device."
+ *	  This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			\li Corrected OSC32K startup time definitions
+ *			\li Support locking of OSC32K and XOSC32K config register (default: false)
+ *			\li Added DPLL support, functions added:
+ *			    \c system_clock_source_dpll_get_config_defaults() and
+ *		        \c system_clock_source_dpll_set_config()
+ *			\li Moved gclk channel locking feature out of the config struct
+ *			    functions added:
+ *			    \c system_gclk_chan_lock(),
+ *			    \c system_gclk_chan_is_locked()
+ *			    \c system_gclk_chan_is_enabled() and
+ *			    \c system_gclk_gen_is_enabled()
+ *		</td>
+ *	</tr>
+ *  <tr>
+ *		<td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ *		    and configured to a failed/not running clock generator</td>
+ *  </tr>
+ *	<tr>
+ *		<td>
+ *			\li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
+ *			\li Fixed system_flash_set_waitstates() failing with an assertion
+ *			    if an odd number of wait states provided
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *			\li Updated DFLL configuration function to implement workaround for
+ *			    errata 9905 in the DFLL module
+ *			\li Updated \c system_clock_init() to reset interrupt flags before
+ *			    they are used
+ *			\li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ *			    frequency number
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ *              state for \c SYSTEM_CLOCK_SOURCE_OSC8M
+ *          \li Renamed the various \c system_clock_source_*_get_default_config()
+ *              functions to \c system_clock_source_*_get_config_defaults() to
+ *              match the remainder of ASF
+ *          \li Added OSC8M calibration constant loading from the device signature
+ *              row when the oscillator is initialized
+ *          \li Updated default configuration of the XOSC32 to disable Automatic
+ *              Gain Control due to silicon errata
+ *      </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in
+ * a selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_clock_basic_use_case
+ *  - \subpage asfdoc_sam0_system_gclk_basic_use_case
+ *
+ * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42119E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM DA1 and SAM D09</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Fixed missing steps in the Basic
+ *          Use Case Quick Start Guide</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42119A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
index 61c2084..d52425b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
@@ -1,512 +1,512 @@
-/**
- * \file
- *
- * \brief SAM D21/R21/DA/HA Generic Clock Driver
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include <gclk.h>
-#include <clock.h>
-#include <system_interrupt.h>
-
-/**
- * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
- *
- * Checks to see if the underlying hardware peripheral module(s) are currently
- * synchronizing across multiple clock domains to the hardware bus, This
- * function can be used to delay further operations on a module until such time
- * that it is ready, to prevent blocking delays for synchronization in the
- * user application.
- *
- * \return Synchronization status of the underlying hardware module(s).
- *
- * \retval false if the module has completed synchronization
- * \retval true if the module synchronization is ongoing
- */
-static inline bool system_gclk_is_syncing(void)
-{
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-		return true;
-	}
-
-	return false;
-}
-
-/**
- * \brief Initializes the GCLK driver.
- *
- * Initializes the Generic Clock module, disabling and resetting all active
- * Generic Clock Generators and Channels to their power-on default values.
- */
-void system_gclk_init(void)
-{
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
-
-	/* Software reset the module to ensure it is re-initialized correctly */
-	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
-	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
-		/* Wait for reset to complete */
-	}
-}
-
-/**
- * \brief Writes a Generic Clock Generator configuration to the hardware module.
- *
- * Writes out a given configuration of a Generic Clock Generator configuration
- * to the hardware module.
- *
- * \note Changing the clock source on the fly (on a running
- *       generator) can take additional time if the clock source is configured
- *       to only run on-demand (ONDEMAND bit is set) and it is not currently
- *       running (no peripheral is requesting the clock source). In this case
- *       the GCLK will request the new clock while still keeping a request to
- *       the old clock source until the new clock source is ready.
- *
- * \note This function will not start a generator that is not already running;
- *       to start the generator, call \ref system_gclk_gen_enable()
- *       after configuring a generator.
- *
- * \param[in] generator  Generic Clock Generator index to configure
- * \param[in] config     Configuration settings for the generator
- */
-void system_gclk_gen_set_config(
-		const uint8_t generator,
-		struct system_gclk_gen_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Cache new register configurations to minimize sync requirements. */
-	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
-	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
-
-	/* Select the requested source clock for the generator */
-	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
-
-	/* Configure the clock to be either high or low when disabled */
-	if (config->high_when_disabled) {
-		new_genctrl_config |= GCLK_GENCTRL_OOV;
-	}
-
-	/* Configure if the clock output to I/O pin should be enabled. */
-	if (config->output_enable) {
-		new_genctrl_config |= GCLK_GENCTRL_OE;
-	}
-
-	/* Set division factor */
-	if (config->division_factor > 1) {
-		/* Check if division is a power of two */
-		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
-			/* Determine the index of the highest bit set to get the
-			 * division factor that must be loaded into the division
-			 * register */
-
-			uint32_t div2_count = 0;
-
-			uint32_t mask;
-			for (mask = (1UL << 1); mask < config->division_factor;
-						mask <<= 1) {
-				div2_count++;
-			}
-
-			/* Set binary divider power of 2 division factor */
-			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
-			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
-		} else {
-			/* Set integer division factor */
-
-			new_gendiv_config  |=
-					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
-
-			/* Enable non-binary division with increased duty cycle accuracy */
-			new_genctrl_config |= GCLK_GENCTRL_IDC;
-		}
-
-	}
-
-	/* Enable or disable the clock in standby mode */
-	if (config->run_in_standby) {
-		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
-	}
-
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the correct generator */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-
-	/* Write the new generator configuration */
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-	GCLK->GENDIV.reg  = new_gendiv_config;
-
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Enables a Generic Clock Generator that was previously configured.
- *
- * Starts the clock generation of a Generic Clock Generator that was previously
- * configured via a call to \ref system_gclk_gen_set_config().
- *
- * \param[in] generator  Generic Clock Generator index to enable
- */
-void system_gclk_gen_enable(
-		const uint8_t generator)
-{
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	/* Enable generator */
-	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Disables a Generic Clock Generator that was previously enabled.
- *
- * Stops the clock generation of a Generic Clock Generator that was previously
- * started via a call to \ref system_gclk_gen_enable().
- *
- * \param[in] generator  Generic Clock Generator index to disable
- */
-void system_gclk_gen_disable(
-		const uint8_t generator)
-{
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	/* Disable generator */
-	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
-	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
-		/* Wait for clock to become disabled */
-	}
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Determins if the specified Generic Clock Generator is enabled.
- *
- * \param[in] generator  Generic Clock Generator index to check
- *
- * \return The enabled status.
- * \retval true The Generic Clock Generator is enabled
- * \retval false The Generic Clock Generator is disabled
- */
-bool system_gclk_gen_is_enabled(
-		const uint8_t generator)
-{
-	bool enabled;
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	/* Obtain the enabled status */
-	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
-
-	system_interrupt_leave_critical_section();
-
-	return enabled;
-}
-
-/**
- * \brief Retrieves the clock frequency of a Generic Clock generator.
- *
- * Determines the clock frequency (in Hz) of a specified Generic Clock
- * generator, used as a source to a Generic Clock Channel module.
- *
- * \param[in] generator  Generic Clock Generator index
- *
- * \return The frequency of the generic clock generator, in Hz.
- */
-uint32_t system_gclk_gen_get_hz(
-		const uint8_t generator)
-{
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the appropriate generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	/* Get the frequency of the source connected to the GCLK generator */
-	uint32_t gen_input_hz = system_clock_source_get_hz(
-			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
-
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-
-	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
-
-	/* Select the appropriate generator division register */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	uint32_t divider = GCLK->GENDIV.bit.DIV;
-
-	system_interrupt_leave_critical_section();
-
-	/* Check if the generator is using fractional or binary division */
-	if (!divsel && divider > 1) {
-		gen_input_hz /= divider;
-	} else if (divsel) {
-		gen_input_hz >>= (divider+1);
-	}
-
-	return gen_input_hz;
-}
-
-/**
- * \brief Writes a Generic Clock configuration to the hardware module.
- *
- * Writes out a given configuration of a Generic Clock configuration to the
- * hardware module. If the clock is currently running, it will be stopped.
- *
- * \note Once called the clock will not be running; to start the clock,
- *       call \ref system_gclk_chan_enable() after configuring a clock channel.
- *
- * \param[in] channel   Generic Clock channel to configure
- * \param[in] config    Configuration settings for the clock
- *
- */
-void system_gclk_chan_set_config(
-		const uint8_t channel,
-		struct system_gclk_chan_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Cache the new config to reduce sync requirements */
-	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
-
-	/* Select the desired generic clock generator */
-	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
-
-	/* Disable generic clock channel */
-	system_gclk_chan_disable(channel);
-
-	/* Write the new configuration */
-	GCLK->CLKCTRL.reg = new_clkctrl_config;
-}
-
-/**
- * \brief Enables a Generic Clock that was previously configured.
- *
- * Starts the clock generation of a Generic Clock that was previously
- * configured via a call to \ref system_gclk_chan_set_config().
- *
- * \param[in] channel   Generic Clock channel to enable
- */
-void system_gclk_chan_enable(
-		const uint8_t channel)
-{
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-
-	/* Enable the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Disables a Generic Clock that was previously enabled.
- *
- * Stops the clock generation of a Generic Clock that was previously started
- * via a call to \ref system_gclk_chan_enable().
- *
- * \param[in] channel  Generic Clock channel to disable
- */
-void system_gclk_chan_disable(
-		const uint8_t channel)
-{
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-
-	/* Sanity check WRTLOCK */
-	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
-
-	/* Switch to known-working source so that the channel can be disabled */
-	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
-	GCLK->CLKCTRL.bit.GEN = 0;
-
-	/* Disable the generic clock */
-	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
-	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
-		/* Wait for clock to become disabled */
-	}
-
-	/* Restore previous configured clock generator */
-	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Determins if the specified Generic Clock channel is enabled.
- *
- * \param[in] channel  Generic Clock Channel index
- *
- * \return The enabled status.
- * \retval true The Generic Clock channel is enabled
- * \retval false The Generic Clock channel is disabled
- */
-bool system_gclk_chan_is_enabled(
-		const uint8_t channel)
-{
-	bool enabled;
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	enabled = GCLK->CLKCTRL.bit.CLKEN;
-
-	system_interrupt_leave_critical_section();
-
-	return enabled;
-}
-
-/**
- * \brief Locks a Generic Clock channel from further configuration writes.
- *
- * Locks a generic clock channel from further configuration writes. It is only
- * possible to unlock the channel configuration through a power on reset.
- *
- * \param[in] channel   Generic Clock channel to enable
- */
-void system_gclk_chan_lock(
-		const uint8_t channel)
-{
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-
-	/* Lock the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
-
-	system_interrupt_leave_critical_section();
-}
-
-/**
- * \brief Determins if the specified Generic Clock channel is locked.
- *
- * \param[in] channel  Generic Clock Channel index
- *
- * \return The lock status.
- * \retval true The Generic Clock channel is locked
- * \retval false The Generic Clock channel is not locked
- */
-bool system_gclk_chan_is_locked(
-		const uint8_t channel)
-{
-	bool locked;
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	locked = GCLK->CLKCTRL.bit.WRTLOCK;
-
-	system_interrupt_leave_critical_section();
-
-	return locked;
-}
-
-/**
- * \brief Retrieves the clock frequency of a Generic Clock channel.
- *
- * Determines the clock frequency (in Hz) of a specified Generic Clock
- * channel, used as a source to a device peripheral module.
- *
- * \param[in] channel  Generic Clock Channel index
- *
- * \return The frequency of the generic clock channel, in Hz.
- */
-uint32_t system_gclk_chan_get_hz(
-		const uint8_t channel)
-{
-	uint8_t gen_id;
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	gen_id = GCLK->CLKCTRL.bit.GEN;
-
-	system_interrupt_leave_critical_section();
-
-	/* Return the clock speed of the associated GCLK generator */
-	return system_gclk_gen_get_hz(gen_id);
-}
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Generic Clock Driver
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false if the module has completed synchronization
+ * \retval true if the module synchronization is ongoing
+ */
+static inline bool system_gclk_is_syncing(void)
+{
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+	/* Software reset the module to ensure it is re-initialized correctly */
+	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+		/* Wait for reset to complete */
+	}
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ *       generator) can take additional time if the clock source is configured
+ *       to only run on-demand (ONDEMAND bit is set) and it is not currently
+ *       running (no peripheral is requesting the clock source). In this case
+ *       the GCLK will request the new clock while still keeping a request to
+ *       the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ *       to start the generator, call \ref system_gclk_gen_enable()
+ *       after configuring a generator.
+ *
+ * \param[in] generator  Generic Clock Generator index to configure
+ * \param[in] config     Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache new register configurations to minimize sync requirements. */
+	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+	/* Select the requested source clock for the generator */
+	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+	/* Configure the clock to be either high or low when disabled */
+	if (config->high_when_disabled) {
+		new_genctrl_config |= GCLK_GENCTRL_OOV;
+	}
+
+	/* Configure if the clock output to I/O pin should be enabled. */
+	if (config->output_enable) {
+		new_genctrl_config |= GCLK_GENCTRL_OE;
+	}
+
+	/* Set division factor */
+	if (config->division_factor > 1) {
+		/* Check if division is a power of two */
+		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+			/* Determine the index of the highest bit set to get the
+			 * division factor that must be loaded into the division
+			 * register */
+
+			uint32_t div2_count = 0;
+
+			uint32_t mask;
+			for (mask = (1UL << 1); mask < config->division_factor;
+						mask <<= 1) {
+				div2_count++;
+			}
+
+			/* Set binary divider power of 2 division factor */
+			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+		} else {
+			/* Set integer division factor */
+
+			new_gendiv_config  |=
+					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+			/* Enable non-binary division with increased duty cycle accuracy */
+			new_genctrl_config |= GCLK_GENCTRL_IDC;
+		}
+
+	}
+
+	/* Enable or disable the clock in standby mode */
+	if (config->run_in_standby) {
+		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+	}
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the correct generator */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+	/* Write the new generator configuration */
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENDIV.reg  = new_gendiv_config;
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator  Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Enable generator */
+	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator  Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Disable generator */
+	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled.
+ *
+ * \param[in] generator  Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled
+ * \retval false The Generic Clock Generator is disabled
+ */
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	/* Obtain the enabled status */
+	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator  Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the appropriate generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Get the frequency of the source connected to the GCLK generator */
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+
+	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+
+	/* Select the appropriate generator division register */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	uint32_t divider = GCLK->GENDIV.bit.DIV;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if the generator is using fractional or binary division */
+	if (!divsel && divider > 1) {
+		gen_input_hz /= divider;
+	} else if (divsel) {
+		gen_input_hz >>= (divider+1);
+	}
+
+	return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ *       call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel   Generic Clock channel to configure
+ * \param[in] config    Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache the new config to reduce sync requirements */
+	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+
+	/* Select the desired generic clock generator */
+	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+
+	/* Disable generic clock channel */
+	system_gclk_chan_disable(channel);
+
+	/* Write the new configuration */
+	GCLK->CLKCTRL.reg = new_clkctrl_config;
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Enable the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel  Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Sanity check WRTLOCK */
+	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+	/* Switch to known-working source so that the channel can be disabled */
+	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+	GCLK->CLKCTRL.bit.GEN = 0;
+
+	/* Disable the generic clock */
+	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	/* Restore previous configured clock generator */
+	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled
+ * \retval false The Generic Clock channel is disabled
+ */
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	enabled = GCLK->CLKCTRL.bit.CLKEN;
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Lock the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked
+ * \retval false The Generic Clock channel is not locked
+ */
+bool system_gclk_chan_is_locked(
+		const uint8_t channel)
+{
+	bool locked;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	locked = GCLK->CLKCTRL.bit.WRTLOCK;
+
+	system_interrupt_leave_critical_section();
+
+	return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel)
+{
+	uint8_t gen_id;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	gen_id = GCLK->CLKCTRL.bit.GEN;
+
+	system_interrupt_leave_critical_section();
+
+	/* Return the clock speed of the associated GCLK generator */
+	return system_gclk_gen_get_hz(gen_id);
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/gclk.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/gclk.h
index 874b050..fc8511d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/gclk.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/clock/gclk.h
@@ -1,297 +1,297 @@
-/**
- * \file
- *
- * \brief SAM Generic Clock Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
-#define SYSTEM_CLOCK_GCLK_H_INCLUDED
-
-/**
- * \addtogroup asfdoc_sam0_system_clock_group
- *
- * @{
- */
-
-#include <compiler.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief List of available GCLK generators.
- *
- * List of Available GCLK generators. This enum is used in the peripheral
- * device drivers to select the GCLK generator to be used for its operation.
- *
- * The number of GCLK generators available is device dependent.
- */
-enum gclk_generator {
-	/** GCLK generator channel 0 */
-	GCLK_GENERATOR_0,
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
-	/** GCLK generator channel 1 */
-	GCLK_GENERATOR_1,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
-	/** GCLK generator channel 2 */
-	GCLK_GENERATOR_2,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
-	/** GCLK generator channel 3 */
-	GCLK_GENERATOR_3,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
-	/** GCLK generator channel 4 */
-	GCLK_GENERATOR_4,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
-	/** GCLK generator channel 5 */
-	GCLK_GENERATOR_5,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
-	/** GCLK generator channel 6 */
-	GCLK_GENERATOR_6,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
-	/** GCLK generator channel 7 */
-	GCLK_GENERATOR_7,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
-	/** GCLK generator channel 8 */
-	GCLK_GENERATOR_8,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
-	/** GCLK generator channel 9 */
-	GCLK_GENERATOR_9,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
-	/** GCLK generator channel 10 */
-	GCLK_GENERATOR_10,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
-	/** GCLK generator channel 11 */
-	GCLK_GENERATOR_11,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
-	/** GCLK generator channel 12 */
-	GCLK_GENERATOR_12,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
-	/** GCLK generator channel 13 */
-	GCLK_GENERATOR_13,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
-	/** GCLK generator channel 14 */
-	GCLK_GENERATOR_14,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
-	/** GCLK generator channel 15 */
-	GCLK_GENERATOR_15,
-#endif
-#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
-	/** GCLK generator channel 16 */
-	GCLK_GENERATOR_16,
-#endif
-};
-
-/**
- * \brief Generic Clock Generator configuration structure.
- *
- * Configuration structure for a Generic Clock Generator channel. This
- * structure should be initialized by the
- * \ref system_gclk_gen_get_config_defaults() function before being modified by
- * the user application.
- */
-struct system_gclk_gen_config {
-	/** Source clock input channel index, see the \ref system_clock_source */
-	uint8_t source_clock;
-	/** If \c true, the generator output level is high when disabled */
-	bool high_when_disabled;
-	/** Integer division factor of the clock output compared to the input */
-	uint32_t division_factor;
-	/** If \c true, the clock is kept enabled during device standby mode */
-	bool run_in_standby;
-	/** If \c true, enables GCLK generator clock output to a GPIO pin */
-	bool output_enable;
-};
-
-/**
- * \brief Generic Clock configuration structure.
- *
- * Configuration structure for a Generic Clock channel. This structure
- * should be initialized by the \ref system_gclk_chan_get_config_defaults()
- * function before being modified by the user application.
- */
-struct system_gclk_chan_config {
-	/** Generic Clock Generator source channel */
-	enum gclk_generator source_generator;
-};
-
-/** \name Generic Clock Management
- * @{
- */
-void system_gclk_init(void);
-
-/** @} */
-
-
-/**
- * \name Generic Clock Management (Generators)
- * @{
- */
-
-/**
- * \brief Initializes a Generic Clock Generator configuration structure to defaults.
- *
- * Initializes a given Generic Clock Generator configuration structure to
- * a set of known default values. This function should be called on all
- * new instances of these configuration structures before being modified
- * by the user application.
- *
- * The default configuration is:
- *  \li The clock is generated undivided from the source frequency
- *  \li The clock generator output is low when the generator is disabled
- *  \li The input clock is sourced from input clock channel 0
- *  \li The clock will be disabled during sleep
- *  \li The clock output will not be routed to a physical GPIO pin
- *
- * \param[out] config  Configuration structure to initialize to default values
- */
-static inline void system_gclk_gen_get_config_defaults(
-		struct system_gclk_gen_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->division_factor    = 1;
-	config->high_when_disabled = false;
-#if SAML21 || SAML22  || SAMR30 || SAMR34 || SAMR35
-	config->source_clock       = GCLK_SOURCE_OSC16M;
-#elif (SAMC20) || (SAMC21)
-	config->source_clock       = GCLK_SOURCE_OSC48M;
-#else
-	config->source_clock       = GCLK_SOURCE_OSC8M;
-#endif
-	config->run_in_standby     = false;
-	config->output_enable      = false;
-}
-
-void system_gclk_gen_set_config(
-		const uint8_t generator,
-		struct system_gclk_gen_config *const config);
-
-void system_gclk_gen_enable(
-		const uint8_t generator);
-
-void system_gclk_gen_disable(
-		const uint8_t generator);
-
-bool system_gclk_gen_is_enabled(
-		const uint8_t generator);
-
-/** @} */
-
-
-/**
- * \name Generic Clock Management (Channels)
- * @{
- */
-
-/**
- * \brief Initializes a Generic Clock configuration structure to defaults.
- *
- * Initializes a given Generic Clock configuration structure to a set of
- * known default values. This function should be called on all new
- * instances of these configuration structures before being modified by the
- * user application.
- *
- * The default configuration is as follows:
- *  \li The clock is sourced from the Generic Clock Generator channel 0
- *  \li The clock configuration will not be write-locked when set
- *
- * \param[out] config  Configuration structure to initialize to default values
- */
-static inline void system_gclk_chan_get_config_defaults(
-		struct system_gclk_chan_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->source_generator = GCLK_GENERATOR_0;
-}
-
-void system_gclk_chan_set_config(
-		const uint8_t channel,
-		struct system_gclk_chan_config *const config);
-
-void system_gclk_chan_enable(
-		const uint8_t channel);
-
-void system_gclk_chan_disable(
-		const uint8_t channel);
-
-bool system_gclk_chan_is_enabled(
-		const uint8_t channel);
-
-void system_gclk_chan_lock(
-		const uint8_t channel);
-
-bool system_gclk_chan_is_locked(
-		const uint8_t channel);
-
-/** @} */
-
-
-/**
- * \name Generic Clock Frequency Retrieval
- * @{
- */
-
-uint32_t system_gclk_gen_get_hz(
-		const uint8_t generator);
-
-uint32_t system_gclk_chan_get_hz(
-		const uint8_t channel);
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-#endif
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_system_clock_group
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief List of available GCLK generators.
+ *
+ * List of Available GCLK generators. This enum is used in the peripheral
+ * device drivers to select the GCLK generator to be used for its operation.
+ *
+ * The number of GCLK generators available is device dependent.
+ */
+enum gclk_generator {
+	/** GCLK generator channel 0 */
+	GCLK_GENERATOR_0,
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
+	/** GCLK generator channel 1 */
+	GCLK_GENERATOR_1,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
+	/** GCLK generator channel 2 */
+	GCLK_GENERATOR_2,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
+	/** GCLK generator channel 3 */
+	GCLK_GENERATOR_3,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
+	/** GCLK generator channel 4 */
+	GCLK_GENERATOR_4,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
+	/** GCLK generator channel 5 */
+	GCLK_GENERATOR_5,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
+	/** GCLK generator channel 6 */
+	GCLK_GENERATOR_6,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
+	/** GCLK generator channel 7 */
+	GCLK_GENERATOR_7,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
+	/** GCLK generator channel 8 */
+	GCLK_GENERATOR_8,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
+	/** GCLK generator channel 9 */
+	GCLK_GENERATOR_9,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
+	/** GCLK generator channel 10 */
+	GCLK_GENERATOR_10,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
+	/** GCLK generator channel 11 */
+	GCLK_GENERATOR_11,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
+	/** GCLK generator channel 12 */
+	GCLK_GENERATOR_12,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
+	/** GCLK generator channel 13 */
+	GCLK_GENERATOR_13,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
+	/** GCLK generator channel 14 */
+	GCLK_GENERATOR_14,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
+	/** GCLK generator channel 15 */
+	GCLK_GENERATOR_15,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
+	/** GCLK generator channel 16 */
+	GCLK_GENERATOR_16,
+#endif
+};
+
+/**
+ * \brief Generic Clock Generator configuration structure.
+ *
+ * Configuration structure for a Generic Clock Generator channel. This
+ * structure should be initialized by the
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_gclk_gen_config {
+	/** Source clock input channel index, see the \ref system_clock_source */
+	uint8_t source_clock;
+	/** If \c true, the generator output level is high when disabled */
+	bool high_when_disabled;
+	/** Integer division factor of the clock output compared to the input */
+	uint32_t division_factor;
+	/** If \c true, the clock is kept enabled during device standby mode */
+	bool run_in_standby;
+	/** If \c true, enables GCLK generator clock output to a GPIO pin */
+	bool output_enable;
+};
+
+/**
+ * \brief Generic Clock configuration structure.
+ *
+ * Configuration structure for a Generic Clock channel. This structure
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct system_gclk_chan_config {
+	/** Generic Clock Generator source channel */
+	enum gclk_generator source_generator;
+};
+
+/** \name Generic Clock Management
+ * @{
+ */
+void system_gclk_init(void);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Generators)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock Generator configuration structure to
+ * a set of known default values. This function should be called on all
+ * new instances of these configuration structures before being modified
+ * by the user application.
+ *
+ * The default configuration is:
+ *  \li The clock is generated undivided from the source frequency
+ *  \li The clock generator output is low when the generator is disabled
+ *  \li The input clock is sourced from input clock channel 0
+ *  \li The clock will be disabled during sleep
+ *  \li The clock output will not be routed to a physical GPIO pin
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_gen_get_config_defaults(
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->division_factor    = 1;
+	config->high_when_disabled = false;
+#if SAML21 || SAML22  || SAMR30 || SAMR34 || SAMR35
+	config->source_clock       = GCLK_SOURCE_OSC16M;
+#elif (SAMC20) || (SAMC21)
+	config->source_clock       = GCLK_SOURCE_OSC48M;
+#else
+	config->source_clock       = GCLK_SOURCE_OSC8M;
+#endif
+	config->run_in_standby     = false;
+	config->output_enable      = false;
+}
+
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config);
+
+void system_gclk_gen_enable(
+		const uint8_t generator);
+
+void system_gclk_gen_disable(
+		const uint8_t generator);
+
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Channels)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li The clock is sourced from the Generic Clock Generator channel 0
+ *  \li The clock configuration will not be write-locked when set
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_chan_get_config_defaults(
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->source_generator = GCLK_GENERATOR_0;
+}
+
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config);
+
+void system_gclk_chan_enable(
+		const uint8_t channel);
+
+void system_gclk_chan_disable(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel);
+
+void system_gclk_chan_lock(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_locked(
+		const uint8_t channel);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Frequency Retrieval
+ * @{
+ */
+
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator);
+
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
index 348a774..126f7d4 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
@@ -1,207 +1,207 @@
-/**
- * \file
- *
- * \brief SAM System Interrupt Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include "system_interrupt.h"
-
-/**
- * \brief Check if a interrupt line is pending.
- *
- * Checks if the requested interrupt vector is pending.
- *
- * \param[in] vector  Interrupt vector number to check
- *
- * \returns A boolean identifying if the requested interrupt vector is pending.
- *
- * \retval true   Specified interrupt vector is pending
- * \retval false  Specified interrupt vector is not pending
- *
- */
-bool system_interrupt_is_pending(
-		const enum system_interrupt_vector vector)
-{
-	bool result;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
-	} else {
-		Assert(false);
-		result = false;
-	}
-
-	return result;
-}
-
-/**
- * \brief Set a interrupt vector as pending.
- *
- * Set the requested interrupt vector as pending (i.e. issues a software
- * interrupt request for the specified vector). The software handler will be
- * handled (if enabled) in a priority order based on vector number and
- * configured priority settings.
- *
- * \param[in] vector  Interrupt vector number which is set as pending
- *
- * \returns Status code identifying if the vector was successfully set as
- *          pending.
- *
- * \retval STATUS_OK           If no error was detected
- * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
- */
-enum status_code system_interrupt_set_pending(
-		const enum system_interrupt_vector vector)
-{
-	enum status_code status = STATUS_OK;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		NVIC->ISPR[0] = (1 << vector);
-	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
-		/* Note: Because NMI has highest priority it will be executed
-		 * immediately after it has been set pending */
-		SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
-	} else {
-		/* The user want to set something unsupported as pending */
-		Assert(false);
-		status = STATUS_ERR_INVALID_ARG;
-	}
-
-	return status;
-}
-
-/**
- * \brief Clear pending interrupt vector.
- *
- * Clear a pending interrupt vector, so the software handler is not executed.
- *
- * \param[in] vector  Interrupt vector number to clear
- *
- * \returns A status code identifying if the interrupt pending state was
- *          successfully cleared.
- *
- * \retval STATUS_OK           If no error was detected
- * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
- */
-enum status_code system_interrupt_clear_pending(
-		const enum system_interrupt_vector vector)
-{
-	enum status_code status = STATUS_OK;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		NVIC->ICPR[0] = (1 << vector);
-	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
-		/* Note: Clearing of NMI pending interrupts does not make sense and is
-		 * not supported by the device, as it has the highest priority and will
-		 * always be executed at the moment it is set */
-		return STATUS_ERR_INVALID_ARG;
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
-	} else {
-		Assert(false);
-		status = STATUS_ERR_INVALID_ARG;
-	}
-
-	return status;
-}
-
-/**
- * \brief Set interrupt vector priority level.
- *
- * Set the priority level of an external interrupt or exception.
- *
- * \param[in] vector          Interrupt vector to change
- * \param[in] priority_level  New vector priority level to set
- *
- * \returns Status code indicating if the priority level of the interrupt was
- *          successfully set.
- *
- * \retval STATUS_OK           If no error was detected
- * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
- */
-enum status_code system_interrupt_set_priority(
-		const enum system_interrupt_vector vector,
-		const enum system_interrupt_priority_level priority_level)
-{
-	enum status_code status = STATUS_OK;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		uint8_t register_num = vector / 4;
-		uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
-
-		NVIC->IP[register_num] =
-				(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
-				(priority_level << priority_pos);
-
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
-	} else {
-		Assert(false);
-		status = STATUS_ERR_INVALID_ARG;
-	}
-
-	return status;
-}
-
-/**
- * \brief Get interrupt vector priority level.
- *
- * Retrieves the priority level of the requested external interrupt or exception.
- *
- * \param[in] vector  Interrupt vector of which the priority level will be read
- *
- * \return Currently configured interrupt priority level of the given interrupt
- *         vector.
- */
-enum system_interrupt_priority_level system_interrupt_get_priority(
-		const enum system_interrupt_vector vector)
-{
-	uint8_t register_num = vector / 4;
-	uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
-
-	enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
-
-	if (vector >= 0) {
-		priority = (enum system_interrupt_priority_level)
-				((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		priority = (enum system_interrupt_priority_level)
-				((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
-	}
-
-	return priority;
-}
-
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "system_interrupt.h"
+
+/**
+ * \brief Check if a interrupt line is pending.
+ *
+ * Checks if the requested interrupt vector is pending.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A boolean identifying if the requested interrupt vector is pending.
+ *
+ * \retval true   Specified interrupt vector is pending
+ * \retval false  Specified interrupt vector is not pending
+ *
+ */
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector)
+{
+	bool result;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+	} else {
+		Assert(false);
+		result = false;
+	}
+
+	return result;
+}
+
+/**
+ * \brief Set a interrupt vector as pending.
+ *
+ * Set the requested interrupt vector as pending (i.e. issues a software
+ * interrupt request for the specified vector). The software handler will be
+ * handled (if enabled) in a priority order based on vector number and
+ * configured priority settings.
+ *
+ * \param[in] vector  Interrupt vector number which is set as pending
+ *
+ * \returns Status code identifying if the vector was successfully set as
+ *          pending.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ISPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Because NMI has highest priority it will be executed
+		 * immediately after it has been set pending */
+		SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+	} else {
+		/* The user want to set something unsupported as pending */
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Clear pending interrupt vector.
+ *
+ * Clear a pending interrupt vector, so the software handler is not executed.
+ *
+ * \param[in] vector  Interrupt vector number to clear
+ *
+ * \returns A status code identifying if the interrupt pending state was
+ *          successfully cleared.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ICPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Clearing of NMI pending interrupts does not make sense and is
+		 * not supported by the device, as it has the highest priority and will
+		 * always be executed at the moment it is set */
+		return STATUS_ERR_INVALID_ARG;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Set interrupt vector priority level.
+ *
+ * Set the priority level of an external interrupt or exception.
+ *
+ * \param[in] vector          Interrupt vector to change
+ * \param[in] priority_level  New vector priority level to set
+ *
+ * \returns Status code indicating if the priority level of the interrupt was
+ *          successfully set.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		uint8_t register_num = vector / 4;
+		uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+		NVIC->IP[register_num] =
+				(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
+				(priority_level << priority_pos);
+
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Get interrupt vector priority level.
+ *
+ * Retrieves the priority level of the requested external interrupt or exception.
+ *
+ * \param[in] vector  Interrupt vector of which the priority level will be read
+ *
+ * \return Currently configured interrupt priority level of the given interrupt
+ *         vector.
+ */
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector)
+{
+	uint8_t register_num = vector / 4;
+	uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+	enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+	if (vector >= 0) {
+		priority = (enum system_interrupt_priority_level)
+				((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		priority = (enum system_interrupt_priority_level)
+				((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	}
+
+	return priority;
+}
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h
index 76ee5e6..6cbe534 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h
@@ -1,423 +1,423 @@
-/**
- * \file
- *
- * \brief SAM System Interrupt Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SYSTEM_INTERRUPT_H_INCLUDED
-#define SYSTEM_INTERRUPT_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
- * an interface for the configuration and management of internal software and
- * hardware interrupts/exceptions.
- *
- * The following peripheral is used by this module:
- *  - NVIC (Nested Vector Interrupt Controller)
- *
- * The following devices can use this module:
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM L21/L22
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM C20/C21
- *  - Atmel | SMART SAM HA1
- *  - Atmel | SMART SAM R30
- *  - Atmel | SMART SAM R34
- *  - Atmel | SMART SAM R35
- *
- * The outline of this documentation is as follows:
- *  - \ref asfdoc_sam0_system_interrupt_prerequisites
- *  - \ref asfdoc_sam0_system_interrupt_module_overview
- *  - \ref asfdoc_sam0_system_interrupt_special_considerations
- *  - \ref asfdoc_sam0_system_interrupt_extra_info
- *  - \ref asfdoc_sam0_system_interrupt_examples
- *  - \ref asfdoc_sam0_system_interrupt_api_overview
- *
- *
- * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
- *
- * The ARM&reg; Cortex&reg; M0+ core contains an interrupt and exception vector table, which
- * can be used to configure the device's interrupt handlers; individual
- * interrupts and exceptions can be enabled and disabled, as well as configured
- * with a variable priority.
- *
- * This driver provides a set of wrappers around the core interrupt functions,
- * to expose a simple API for the management of global and individual interrupts
- * within the device.
- *
- * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
- * In some applications it is important to ensure that no interrupts may be
- * executed by the system whilst a critical portion of code is being run; for
- * example, a buffer may be copied from one context to another - during which
- * interrupts must be disabled to avoid corruption of the source buffer contents
- * until the copy has completed. This driver provides a basic API to enter and
- * exit nested critical sections, so that global interrupts can be kept disabled
- * for as long as necessary to complete a critical application code section.
- *
- * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
- * For some applications, it may be desirable to raise a module or core
- * interrupt via software. For this reason, a set of APIs to set an interrupt or
- * exception as pending are provided to the user application.
- *
- * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
- *
- * Interrupts from peripherals in the SAM devices are on a per-module basis;
- * an interrupt raised from any source within a module will cause a single,
- * module-common handler to execute. It is the user application or driver's
- * responsibility to de-multiplex the module-common interrupt to determine the
- * exact interrupt cause.
- *
- * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
- *  - \ref asfdoc_sam0_system_interrupt_extra_acronyms
- *  - \ref asfdoc_sam0_system_interrupt_extra_dependencies
- *  - \ref asfdoc_sam0_system_interrupt_extra_errata
- *  - \ref asfdoc_sam0_system_interrupt_extra_history
- *
- *
- * \section asfdoc_sam0_system_interrupt_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_system_interrupt_exqsg.
- *
- * \section asfdoc_sam0_system_interrupt_api_overview API Overview
- * @{
- */
-
-#include <compiler.h>
-#include <core_cm0plus.h>
-#include "system_interrupt_features.h"
-
-/**
- * \brief Table of possible system interrupt/exception vector priorities.
- *
- * Table of all possible interrupt and exception vector priorities within the
- * device.
- */
-enum system_interrupt_priority_level {
-	/** Priority level 0, the highest possible interrupt priority */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
-	/** Priority level 1 */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
-	/** Priority level 2 */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
-	/** Priority level 3, the lowest possible interrupt priority */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
-};
-
-/**
- * \name Critical Section Management
- * @{
- */
-
-/**
- * \brief Enters a critical section.
- *
- * Disables global interrupts. To support nested critical sections, an internal
- * count of the critical section nesting will be kept, so that global interrupts
- * are only re-enabled upon leaving the outermost nested critical section.
- *
- */
-static inline void system_interrupt_enter_critical_section(void)
-{
-	cpu_irq_enter_critical();
-}
-
-/**
- * \brief Leaves a critical section.
- *
- * Enables global interrupts. To support nested critical sections, an internal
- * count of the critical section nesting will be kept, so that global interrupts
- * are only re-enabled upon leaving the outermost nested critical section.
- *
- */
-static inline void system_interrupt_leave_critical_section(void)
-{
-	cpu_irq_leave_critical();
-}
-
-/** @} */
-
-/**
- * \name Interrupt Enabling/Disabling
- * @{
- */
-
-/**
- * \brief Check if global interrupts are enabled.
- *
- * Checks if global interrupts are currently enabled.
- *
- * \returns A boolean that identifies if the global interrupts are enabled or not.
- *
- * \retval true   Global interrupts are currently enabled
- * \retval false  Global interrupts are currently disabled
- *
- */
-static inline bool system_interrupt_is_global_enabled(void)
-{
-	return cpu_irq_is_enabled();
-}
-
-/**
- * \brief Enables global interrupts.
- *
- * Enables global interrupts in the device to fire any enabled interrupt handlers.
- */
-static inline void system_interrupt_enable_global(void)
-{
-	cpu_irq_enable();
-}
-
-/**
- * \brief Disables global interrupts.
- *
- * Disabled global interrupts in the device, preventing any enabled interrupt
- * handlers from executing.
- */
-static inline void system_interrupt_disable_global(void)
-{
-	cpu_irq_disable();
-}
-
-/**
- * \brief Checks if an interrupt vector is enabled or not.
- *
- * Checks if a specific interrupt vector is currently enabled.
- *
- * \param[in] vector  Interrupt vector number to check
- *
- * \returns A variable identifying if the requested interrupt vector is enabled.
- *
- * \retval true   Specified interrupt vector is currently enabled
- * \retval false  Specified interrupt vector is currently disabled
- *
- */
-static inline bool system_interrupt_is_enabled(
-		const enum system_interrupt_vector vector)
-{
-	return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
-}
-
-/**
- * \brief Enable interrupt vector.
- *
- * Enables execution of the software handler for the requested interrupt vector.
- *
- * \param[in] vector Interrupt vector to enable
- */
-static inline void system_interrupt_enable(
-		const enum system_interrupt_vector vector)
-{
-	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
-}
-
-/**
- * \brief Disable interrupt vector.
- *
- * Disables execution of the software handler for the requested interrupt vector.
- *
- * \param[in] vector  Interrupt vector to disable
- */
-static inline void system_interrupt_disable(
-		const enum system_interrupt_vector vector)
-{
-	NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
-}
-
-/** @} */
-
-/**
- * \name Interrupt State Management
- * @{
- */
-
-/**
- * \brief Get active interrupt (if any).
- *
- * Return the vector number for the current executing software handler, if any.
- *
- * \return Interrupt number that is currently executing.
- */
-static inline enum system_interrupt_vector system_interrupt_get_active(void)
-{
-	uint32_t IPSR = __get_IPSR();
-	/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
-	return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
-}
-
-bool system_interrupt_is_pending(
-		const enum system_interrupt_vector vector);
-
-enum status_code system_interrupt_set_pending(
-		const enum system_interrupt_vector vector);
-
-enum status_code system_interrupt_clear_pending(
-		const enum system_interrupt_vector vector);
-
-/** @} */
-
-/**
- * \name Interrupt Priority Management
- * @{
- */
-
-enum status_code system_interrupt_set_priority(
-		const enum system_interrupt_vector vector,
-		const enum system_interrupt_priority_level priority_level);
-
-enum system_interrupt_priority_level system_interrupt_get_priority(
-		const enum system_interrupt_vector vector);
-
-/** @} */
-
-/** @} */
-
-/**
- * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
- *
- * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
- * The table below presents the acronyms used in this module:
- *
- * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>ISR</td>
- *		<td>Interrupt Service Routine</td>
- *	</tr>
- *	<tr>
- *		<td>NMI</td>
- *		<td>Non-maskable Interrupt</td>
- *	</tr>
- *	<tr>
- *		<td>SERCOM</td>
- *		<td>Serial Communication Interface</td>
- *	</tr>
- * </table>
- *
- *
- * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- *  - None
- *
- *
- * \section asfdoc_sam0_system_interrupt_extra_errata Errata
- * There are no errata related to this driver.
- *
- *
- * \section asfdoc_sam0_system_interrupt_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
- * </table>
- */
-
-/**
- * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
- *
- * This is a list of the available Quick Start guides (QSGs) and example
- * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
- * step-by-step instructions to configure and use this driver in a selection of
- * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.
- *
- *  - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
- *  - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
- *
- * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
- *
- * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42122E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42122D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42122C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42122B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42122A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
- * </table>
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#define SYSTEM_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of internal software and
+ * hardware interrupts/exceptions.
+ *
+ * The following peripheral is used by this module:
+ *  - NVIC (Nested Vector Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_interrupt_prerequisites
+ *  - \ref asfdoc_sam0_system_interrupt_module_overview
+ *  - \ref asfdoc_sam0_system_interrupt_special_considerations
+ *  - \ref asfdoc_sam0_system_interrupt_extra_info
+ *  - \ref asfdoc_sam0_system_interrupt_examples
+ *  - \ref asfdoc_sam0_system_interrupt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
+ *
+ * The ARM&reg; Cortex&reg; M0+ core contains an interrupt and exception vector table, which
+ * can be used to configure the device's interrupt handlers; individual
+ * interrupts and exceptions can be enabled and disabled, as well as configured
+ * with a variable priority.
+ *
+ * This driver provides a set of wrappers around the core interrupt functions,
+ * to expose a simple API for the management of global and individual interrupts
+ * within the device.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
+ * In some applications it is important to ensure that no interrupts may be
+ * executed by the system whilst a critical portion of code is being run; for
+ * example, a buffer may be copied from one context to another - during which
+ * interrupts must be disabled to avoid corruption of the source buffer contents
+ * until the copy has completed. This driver provides a basic API to enter and
+ * exit nested critical sections, so that global interrupts can be kept disabled
+ * for as long as necessary to complete a critical application code section.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
+ * For some applications, it may be desirable to raise a module or core
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or
+ * exception as pending are provided to the user application.
+ *
+ * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
+ *
+ * Interrupts from peripherals in the SAM devices are on a per-module basis;
+ * an interrupt raised from any source within a module will cause a single,
+ * module-common handler to execute. It is the user application or driver's
+ * responsibility to de-multiplex the module-common interrupt to determine the
+ * exact interrupt cause.
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
+ *  - \ref asfdoc_sam0_system_interrupt_extra_acronyms
+ *  - \ref asfdoc_sam0_system_interrupt_extra_dependencies
+ *  - \ref asfdoc_sam0_system_interrupt_extra_errata
+ *  - \ref asfdoc_sam0_system_interrupt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_interrupt_exqsg.
+ *
+ * \section asfdoc_sam0_system_interrupt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <core_cm0plus.h>
+#include "system_interrupt_features.h"
+
+/**
+ * \brief Table of possible system interrupt/exception vector priorities.
+ *
+ * Table of all possible interrupt and exception vector priorities within the
+ * device.
+ */
+enum system_interrupt_priority_level {
+	/** Priority level 0, the highest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
+	/** Priority level 1 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
+	/** Priority level 2 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
+	/** Priority level 3, the lowest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
+};
+
+/**
+ * \name Critical Section Management
+ * @{
+ */
+
+/**
+ * \brief Enters a critical section.
+ *
+ * Disables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+	cpu_irq_enter_critical();
+}
+
+/**
+ * \brief Leaves a critical section.
+ *
+ * Enables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+	cpu_irq_leave_critical();
+}
+
+/** @} */
+
+/**
+ * \name Interrupt Enabling/Disabling
+ * @{
+ */
+
+/**
+ * \brief Check if global interrupts are enabled.
+ *
+ * Checks if global interrupts are currently enabled.
+ *
+ * \returns A boolean that identifies if the global interrupts are enabled or not.
+ *
+ * \retval true   Global interrupts are currently enabled
+ * \retval false  Global interrupts are currently disabled
+ *
+ */
+static inline bool system_interrupt_is_global_enabled(void)
+{
+	return cpu_irq_is_enabled();
+}
+
+/**
+ * \brief Enables global interrupts.
+ *
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.
+ */
+static inline void system_interrupt_enable_global(void)
+{
+	cpu_irq_enable();
+}
+
+/**
+ * \brief Disables global interrupts.
+ *
+ * Disabled global interrupts in the device, preventing any enabled interrupt
+ * handlers from executing.
+ */
+static inline void system_interrupt_disable_global(void)
+{
+	cpu_irq_disable();
+}
+
+/**
+ * \brief Checks if an interrupt vector is enabled or not.
+ *
+ * Checks if a specific interrupt vector is currently enabled.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A variable identifying if the requested interrupt vector is enabled.
+ *
+ * \retval true   Specified interrupt vector is currently enabled
+ * \retval false  Specified interrupt vector is currently disabled
+ *
+ */
+static inline bool system_interrupt_is_enabled(
+		const enum system_interrupt_vector vector)
+{
+	return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+}
+
+/**
+ * \brief Enable interrupt vector.
+ *
+ * Enables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/**
+ * \brief Disable interrupt vector.
+ *
+ * Disables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector  Interrupt vector to disable
+ */
+static inline void system_interrupt_disable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/** @} */
+
+/**
+ * \name Interrupt State Management
+ * @{
+ */
+
+/**
+ * \brief Get active interrupt (if any).
+ *
+ * Return the vector number for the current executing software handler, if any.
+ *
+ * \return Interrupt number that is currently executing.
+ */
+static inline enum system_interrupt_vector system_interrupt_get_active(void)
+{
+	uint32_t IPSR = __get_IPSR();
+	/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
+	return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
+}
+
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/**
+ * \name Interrupt Priority Management
+ * @{
+ */
+
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level);
+
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>ISR</td>
+ *		<td>Interrupt Service Routine</td>
+ *	</tr>
+ *	<tr>
+ *		<td>NMI</td>
+ *		<td>Non-maskable Interrupt</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
+ *  - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
+ *
+ * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42122E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
index 7c40bf6..cd66d99 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
@@ -1,185 +1,185 @@
-/**
- * \file
- *
- * \brief SAM D21 System Interrupt Driver
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
-#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
-
-#if !defined(__DOXYGEN__)
-
-/* Generates a interrupt vector table enum list entry for a given module type
-   and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
-#  define _MODULE_IRQn(n, module) \
-		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
-
-/* Generates interrupt vector table enum list entries for all instances of a
-   given module type on the selected device. */
-#  define _SYSTEM_INTERRUPT_MODULES(name) \
-		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
-
-#  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
-#  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
-
-#  define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START  0
-
-#  define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS        30
-#endif
-
-/**
- * \addtogroup asfdoc_sam0_system_interrupt_group
- * @{
- */
-
-/**
- * \brief Table of possible system interrupt/exception vector numbers.
- *
- * Table of all possible interrupt and exception vector indexes within the
- * SAM D21 device. Check peripherals configuration in SAM D21 datasheet for
- * available vector index for specific device.
- *
- */
-#if defined(__DOXYGEN__)
-/** \note The actual enumeration name is "system_interrupt_vector". */
-enum system_interrupt_vector_samd21 {
-#else
-enum system_interrupt_vector {
-#endif
-	/** Interrupt vector index for a NMI interrupt */
-	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
-	/** Interrupt vector index for a Hard Fault memory access exception */
-	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
-	/** Interrupt vector index for a Supervisor Call exception */
-	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
-	/** Interrupt vector index for a Pending Supervisor interrupt */
-	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
-	/** Interrupt vector index for a System Tick interrupt */
-	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
-
-	/** Interrupt vector index for a Power Manager peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
-	/** Interrupt vector index for a System Control peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
-	/** Interrupt vector index for a Watch Dog peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
-	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
-	/** Interrupt vector index for an External Interrupt peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
-	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
-	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
-	/** Interrupt vector index for a Direct Memory Access interrupt */
-	SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
-#if defined(__DOXYGEN__) || defined(ID_USB)
-	/** Interrupt vector index for a Universal Serial Bus interrupt */
-	SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
-#endif
-	/** Interrupt vector index for an Event System interrupt */
-	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
-#if defined(__DOXYGEN__)
-	/** Interrupt vector index for a SERCOM peripheral interrupt.
-	 *
-	 *  Each specific device may contain several SERCOM peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
-	 */
-	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
-
-	/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
-	 *
-	 *  Each specific device may contain several TCC peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
-	 */
-	SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
-
-	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
-	 *
-	 *  Each specific device may contain several TC peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_TC3).
-	 */
-	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
-#else
-	_SYSTEM_INTERRUPT_MODULES(SERCOM)
-
-	_SYSTEM_INTERRUPT_MODULES(TCC)
-
-	SYSTEM_INTERRUPT_MODULE_TC3        = TC3_IRQn,
-	SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
-	SYSTEM_INTERRUPT_MODULE_TC5        = TC5_IRQn,
-#  if defined(ID_TC6)
-	SYSTEM_INTERRUPT_MODULE_TC6        = TC6_IRQn,
-#  endif
-#  if defined(ID_TC7)
-	SYSTEM_INTERRUPT_MODULE_TC7        = TC7_IRQn,
-#  endif
-#endif
-
-#if defined(__DOXYGEN__) || defined(ID_ADC)
-	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
-#endif
-
-#if defined(__DOXYGEN__) || defined(ID_AC)
-	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
-#endif
-
-#if defined(__DOXYGEN__) || defined(ID_DAC)
-	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
-#endif
-#if defined(__DOXYGEN__) || defined(ID_PTC)
-	/** Interrupt vector index for a Peripheral Touch Controller peripheral
-	 *  interrupt */
-	SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
-#endif
-#if defined(__DOXYGEN__) || defined(ID_I2S)
-	/** Interrupt vector index for a Inter-IC Sound Interface peripheral
-	 *  interrupt */
-	SYSTEM_INTERRUPT_MODULE_I2S        = I2S_IRQn,
-#endif
-#if defined(__DOXYGEN__) || defined(ID_AC1)
-	/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_AC1        = AC1_IRQn,
-#endif
-};
-
-/** @} */
-
-#endif
+/**
+ * \file
+ *
+ * \brief SAM D21 System Interrupt Driver
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+   and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+#  define _MODULE_IRQn(n, module) \
+		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+   given module type on the selected device. */
+#  define _SYSTEM_INTERRUPT_MODULES(name) \
+		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+#  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
+#  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
+
+#  define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START  0
+
+#  define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS        30
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAM D21 device. Check peripherals configuration in SAM D21 datasheet for
+ * available vector index for specific device.
+ *
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samd21 {
+#else
+enum system_interrupt_vector {
+#endif
+	/** Interrupt vector index for a NMI interrupt */
+	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+	/** Interrupt vector index for a Hard Fault memory access exception */
+	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+	/** Interrupt vector index for a Supervisor Call exception */
+	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+	/** Interrupt vector index for a Pending Supervisor interrupt */
+	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+	/** Interrupt vector index for a System Tick interrupt */
+	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+
+	/** Interrupt vector index for a Power Manager peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
+	/** Interrupt vector index for a System Control peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
+	/** Interrupt vector index for a Watch Dog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+	/** Interrupt vector index for an External Interrupt peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+	/** Interrupt vector index for a Direct Memory Access interrupt */
+	SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
+#if defined(__DOXYGEN__) || defined(ID_USB)
+	/** Interrupt vector index for a Universal Serial Bus interrupt */
+	SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
+#endif
+	/** Interrupt vector index for an Event System interrupt */
+	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+	/** Interrupt vector index for a SERCOM peripheral interrupt.
+	 *
+	 *  Each specific device may contain several SERCOM peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TCC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TC3).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+#else
+	_SYSTEM_INTERRUPT_MODULES(SERCOM)
+
+	_SYSTEM_INTERRUPT_MODULES(TCC)
+
+	SYSTEM_INTERRUPT_MODULE_TC3        = TC3_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC5        = TC5_IRQn,
+#  if defined(ID_TC6)
+	SYSTEM_INTERRUPT_MODULE_TC6        = TC6_IRQn,
+#  endif
+#  if defined(ID_TC7)
+	SYSTEM_INTERRUPT_MODULE_TC7        = TC7_IRQn,
+#  endif
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_ADC)
+	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_AC)
+	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_DAC)
+	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_PTC)
+	/** Interrupt vector index for a Peripheral Touch Controller peripheral
+	 *  interrupt */
+	SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_I2S)
+	/** Interrupt vector index for a Inter-IC Sound Interface peripheral
+	 *  interrupt */
+	SYSTEM_INTERRUPT_MODULE_I2S        = I2S_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_AC1)
+	/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC1        = AC1_IRQn,
+#endif
+};
+
+/** @} */
+
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.c
index 7eeba52..5dfe73d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.c
@@ -1,301 +1,301 @@
-/**
- * \file
- *
- * \brief SAM Pin Multiplexer Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include <pinmux.h>
-
-/**
- * \internal
- * Writes out a given configuration of a Port pin configuration to the
- * hardware module.
- *
- * \note If the pin direction is set as an output, the pull-up/pull-down input
- *       configuration setting is ignored.
- *
- * \param[in] port      Base of the PORT module to configure
- * \param[in] pin_mask  Mask of the port pin to configure
- * \param[in] config    Configuration settings for the pin
- */
-static void _system_pinmux_config(
-		PortGroup *const port,
-		const uint32_t pin_mask,
-		const struct system_pinmux_config *const config)
-{
-	Assert(port);
-	Assert(config);
-
-	/* Track the configuration bits into a temporary variable before writing */
-	uint32_t pin_cfg = 0;
-
-	/* Enabled powersave mode, don't create configuration */
-	if (!config->powersave) {
-		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
-		 * be written later) and store the new MUX mask */
-		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
-			pin_cfg |= PORT_WRCONFIG_PMUXEN;
-			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
-		}
-
-		/* Check if the user has requested that the input buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Enable input buffer flag */
-			pin_cfg |= PORT_WRCONFIG_INEN;
-
-			/* Enable pull-up/pull-down control flag if requested */
-			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
-				pin_cfg |= PORT_WRCONFIG_PULLEN;
-			}
-
-			/* Clear the port DIR bits to disable the output buffer */
-			port->DIRCLR.reg = pin_mask;
-		}
-
-		/* Check if the user has requested that the output buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Cannot use a pull-up if the output driver is enabled,
-			 * if requested the input buffer can only sample the current
-			 * output state */
-			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
-		}
-	} else {
-		port->DIRCLR.reg = pin_mask;
-	}
-
-	/* The Write Configuration register (WRCONFIG) requires the
-	 * pins to to grouped into two 16-bit half-words - split them out here */
-	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
-	uint32_t upper_pin_mask = (pin_mask >> 16);
-
-	/* Configure the lower 16-bits of the port to the desired configuration,
-	 * including the pin peripheral multiplexer just in case it is enabled */
-	port->WRCONFIG.reg
-		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
-
-	/* Configure the upper 16-bits of the port to the desired configuration,
-	 * including the pin peripheral multiplexer just in case it is enabled */
-	port->WRCONFIG.reg
-		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
-			PORT_WRCONFIG_HWSEL;
-
-	if(!config->powersave) {
-		/* Set the pull-up state once the port pins are configured if one was
-		 * requested and it does not violate the valid set of port
-		 * configurations */
-		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
-			/* Set the OUT register bits to enable the pull-up if requested,
-			 * clear to enable pull-down */
-			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
-				port->OUTSET.reg = pin_mask;
-			} else {
-				port->OUTCLR.reg = pin_mask;
-			}
-		}
-
-		/* Check if the user has requested that the output buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Set the port DIR bits to enable the output buffer */
-			port->DIRSET.reg = pin_mask;
-		}
-	}
-}
-
-/**
- * \brief Writes a Port pin configuration to the hardware module.
- *
- * Writes out a given configuration of a Port pin configuration to the hardware
- * module.
- *
- * \note If the pin direction is set as an output, the pull-up/pull-down input
- *       configuration setting is ignored.
- *
- * \param[in] gpio_pin  Index of the GPIO pin to configure
- * \param[in] config    Configuration settings for the pin
- */
-void system_pinmux_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct system_pinmux_config *const config)
-{
-	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask = (1UL << (gpio_pin % 32));
-
-	_system_pinmux_config(port, pin_mask, config);
-}
-
-/**
- * \brief Writes a Port pin group configuration to the hardware module.
- *
- * Writes out a given configuration of a Port pin group configuration to the
- * hardware module.
- *
- * \note If the pin direction is set as an output, the pull-up/pull-down input
- *       configuration setting is ignored.
- *
- * \param[in] port      Base of the PORT module to configure
- * \param[in] mask      Mask of the port pin(s) to configure
- * \param[in] config    Configuration settings for the pin
- */
-void system_pinmux_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct system_pinmux_config *const config)
-{
-	Assert(port);
-
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			_system_pinmux_config(port, (1UL << i), config);
-		}
-	}
-}
-
-/**
- * \brief Configures the input sampling mode for a group of pins.
- *
- * Configures the input sampling mode for a group of pins, to
- * control when the physical I/O pin value is sampled and
- * stored inside the microcontroller.
- *
- * \param[in] port     Base of the PORT module to configure
- * \param[in] mask     Mask of the port pin(s) to configure
- * \param[in] mode     New pin sampling mode to configure
- */
-void system_pinmux_group_set_input_sample_mode(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_sample mode)
-{
-	Assert(port);
-
-	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
-		port->CTRL.reg |= mask;
-	} else {
-		port->CTRL.reg &= ~mask;
-	}
-}
-
-#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
-/**
- * \brief Configures the output slew rate mode for a group of pins.
- *
- * Configures the output slew rate mode for a group of pins, to
- * control the speed at which the physical output pin can react to
- * logical changes of the I/O pin value.
- *
- * \param[in] port     Base of the PORT module to configure
- * \param[in] mask     Mask of the port pin(s) to configure
- * \param[in] mode     New pin slew rate mode to configure
- */
-void system_pinmux_group_set_output_slew_rate(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_slew_rate mode)
-{
-	Assert(port);
-
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
-				port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
-			} else {
-				port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
-			}
-		}
-	}
-}
-#endif
-
-#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
-/**
- * \brief Configures the output driver strength mode for a group of pins.
- *
- * Configures the output drive strength for a group of pins, to
- * control the amount of current the pad is able to sink/source.
- *
- * \param[in] port     Base of the PORT module to configure
- * \param[in] mask     Mask of the port pin(s) to configure
- * \param[in] mode     New output driver strength mode to configure
- */
-void system_pinmux_group_set_output_strength(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_strength mode)
-{
-	Assert(port);
-
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
-				port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
-			} else {
-				port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
-			}
-		}
-	}
-}
-#endif
-
-#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
-/**
- * \brief Configures the output driver mode for a group of pins.
- *
- * Configures the output driver mode for a group of pins, to
- * control the pad behavior.
- *
- * \param[in] port Base of the PORT module to configure
- * \param[in] mask Mask of the port pin(s) to configure
- * \param[in] mode New pad output driver mode to configure
- */
-void system_pinmux_group_set_output_drive(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_drive mode)
-{
-	Assert(port);
-
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
-				port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
-			} else {
-				port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
-			}
-		}
-	}
-}
-#endif
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <pinmux.h>
+
+/**
+ * \internal
+ * Writes out a given configuration of a Port pin configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] pin_mask  Mask of the port pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+static void _system_pinmux_config(
+		PortGroup *const port,
+		const uint32_t pin_mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+	Assert(config);
+
+	/* Track the configuration bits into a temporary variable before writing */
+	uint32_t pin_cfg = 0;
+
+	/* Enabled powersave mode, don't create configuration */
+	if (!config->powersave) {
+		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+		 * be written later) and store the new MUX mask */
+		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+			pin_cfg |= PORT_WRCONFIG_PMUXEN;
+			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+		}
+
+		/* Check if the user has requested that the input buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Enable input buffer flag */
+			pin_cfg |= PORT_WRCONFIG_INEN;
+
+			/* Enable pull-up/pull-down control flag if requested */
+			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+				pin_cfg |= PORT_WRCONFIG_PULLEN;
+			}
+
+			/* Clear the port DIR bits to disable the output buffer */
+			port->DIRCLR.reg = pin_mask;
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Cannot use a pull-up if the output driver is enabled,
+			 * if requested the input buffer can only sample the current
+			 * output state */
+			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+		}
+	} else {
+		port->DIRCLR.reg = pin_mask;
+	}
+
+	/* The Write Configuration register (WRCONFIG) requires the
+	 * pins to to grouped into two 16-bit half-words - split them out here */
+	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+	uint32_t upper_pin_mask = (pin_mask >> 16);
+
+	/* Configure the lower 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+	/* Configure the upper 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+			PORT_WRCONFIG_HWSEL;
+
+	if(!config->powersave) {
+		/* Set the pull-up state once the port pins are configured if one was
+		 * requested and it does not violate the valid set of port
+		 * configurations */
+		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+			/* Set the OUT register bits to enable the pull-up if requested,
+			 * clear to enable pull-down */
+			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+				port->OUTSET.reg = pin_mask;
+			} else {
+				port->OUTCLR.reg = pin_mask;
+			}
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Set the port DIR bits to enable the output buffer */
+			port->DIRSET.reg = pin_mask;
+		}
+	}
+}
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+	_system_pinmux_config(port, pin_mask, config);
+}
+
+/**
+ * \brief Writes a Port pin group configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] mask      Mask of the port pin(s) to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			_system_pinmux_config(port, (1UL << i), config);
+		}
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a group of pins.
+ *
+ * Configures the input sampling mode for a group of pins, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode)
+{
+	Assert(port);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= mask;
+	} else {
+		port->CTRL.reg &= ~mask;
+	}
+}
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Configures the output slew rate mode for a group of pins.
+ *
+ * Configures the output slew rate mode for a group of pins, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin slew rate mode to configure
+ */
+void system_pinmux_group_set_output_slew_rate(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_slew_rate mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Configures the output driver strength mode for a group of pins.
+ *
+ * Configures the output drive strength for a group of pins, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New output driver strength mode to configure
+ */
+void system_pinmux_group_set_output_strength(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_strength mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Configures the output driver mode for a group of pins.
+ *
+ * Configures the output driver mode for a group of pins, to
+ * control the pad behavior.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pad output driver mode to configure
+ */
+void system_pinmux_group_set_output_drive(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_drive mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+				port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
+			}
+		}
+	}
+}
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.h
index 0c70694..49a4739 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/pinmux.h
@@ -1,669 +1,669 @@
-/**
- * \file
- *
- * \brief SAM Pin Multiplexer Driver
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef PINMUX_H_INCLUDED
-#define PINMUX_H_INCLUDED
-
-/**
- * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
- * an interface for the configuration and management of the device's physical
- * I/O Pins, to alter the direction and input/drive characteristics as well as
- * to configure the pin peripheral multiplexer selection.
- *
- * The following peripheral is used by this module:
- *  - PORT (Port I/O Management)
- *
- * The following devices can use this module:
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM L21/L22
- *  - Atmel | SMART SAM DA1
- *  - Atmel | SMART SAM C20/C21
- *  - Atmel | SMART SAM HA1
- *  - Atmel | SMART SAM R30
- *  - Atmel | SMART SAM R34
- *  - Atmel | SMART SAM R35
- *
- * The outline of this documentation is as follows:
- *  - \ref asfdoc_sam0_system_pinmux_prerequisites
- *  - \ref asfdoc_sam0_system_pinmux_module_overview
- *  - \ref asfdoc_sam0_system_pinmux_special_considerations
- *  - \ref asfdoc_sam0_system_pinmux_extra_info
- *  - \ref asfdoc_sam0_system_pinmux_examples
- *  - \ref asfdoc_sam0_system_pinmux_api_overview
- *
- *
- * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
- *
- * The SAM devices contain a number of General Purpose I/O pins, used to
- * interface the user application logic and internal hardware peripherals to
- * an external system. The Pin Multiplexer (PINMUX) driver provides a method
- * of configuring the individual pin peripheral multiplexers to select
- * alternate pin functions.
- *
- * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
- * <table>
- *  <tr>
- *    <th>Driver Feature Macro</th>
- *    <th>Supported devices</th>
- *  </tr>
- *  <tr>
- *    <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
- *    <td>SAM L21, SAM C20/C21, SAM R34/R35</td>
- *  </tr>
- * </table>
- * \note The specific features are only available in the driver when the
- * selected device supports those features.
- *
- * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
- * SAM devices use two naming conventions for the I/O pins in the device; one
- * physical and one logical. Each physical pin on a device package is assigned
- * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
- * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
- * former is used to map physical pins to their physical internal device module
- * counterparts, for simplicity the design of this driver uses the logical GPIO
- * numbers instead.
- *
- * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
- * SAM devices contain a peripheral MUX, which is individually controllable
- * for each I/O pin of the device. The peripheral MUX allows you to select the
- * function of a physical package pin - whether it will be controlled as a user
- * controllable GPIO pin, or whether it will be connected internally to one of
- * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
- * configured in GPIO mode, other peripherals connected to the same pin will be
- * disabled.
- *
- * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
- * There are several special modes that can be selected on one or more I/O pins
- * of the device, which alter the input and output characteristics of the pad.
- *
- * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
- * The Drive Strength configures the strength of the output driver on the
- * pad. Normally, there is a fixed current limit that each I/O pin can safely
- * drive, however some I/O pads offer a higher drive mode which increases this
- * limit for that I/O pin at the expense of an increased power consumption.
- *
- * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
- * The Slew Rate configures the slew rate of the output driver, limiting the
- * rate at which the pad output voltage can change with time.
- *
- * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
- * The Input Sample Mode configures the input sampler buffer of the pad. By
- * default, the input buffer is only sampled "on-demand", i.e. when the user
- * application attempts to read from the input buffer. This mode is the most
- * power efficient, but increases the latency of the input sample by two clock
- * cycles of the port clock. To reduce latency, the input sampler can instead
- * be configured to always sample the input buffer on each port clock cycle, at
- * the expense of an increased power consumption.
- *
- * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
- *
- * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
- * how this module is interconnected within the device:
- *
- * \anchor asfdoc_sam0_system_pinmux_intconnections
- * \dot
- * digraph overview {
- *   node [label="Port Pad" shape=square] pad;
- *
- *   subgraph driver {
- *     node [label="Peripheral MUX" shape=trapezium] pinmux;
- *     node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
- *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
- *   }
- *
- *   pinmux -> gpio;
- *   pad    -> pinmux;
- *   pinmux -> peripherals;
- * }
- * \enddot
- *
- * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
- *
- * The SAM port pin input sampling mode is set in groups of four physical
- * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
- * will configure the sampling mode of the entire sub-group.
- *
- * High Drive Strength output driver mode is not available on all device pins -
- * refer to your device specific datasheet.
- *
- *
- * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
- *  - \ref asfdoc_sam0_system_pinmux_extra_acronyms
- *  - \ref asfdoc_sam0_system_pinmux_extra_dependencies
- *  - \ref asfdoc_sam0_system_pinmux_extra_errata
- *  - \ref asfdoc_sam0_system_pinmux_extra_history
- *
- *
- * \section asfdoc_sam0_system_pinmux_examples Examples
- *
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_system_pinmux_exqsg.
- *
- *
- * \section asfdoc_sam0_system_pinmux_api_overview API Overview
- * @{
- */
-
-#include <compiler.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*@{*/ 
-#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
-/** Output Driver Strength Selection feature support */
-#  define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
-#endif
-/*@}*/
-
-/** Peripheral multiplexer index to select GPIO mode for a pin */
-#define SYSTEM_PINMUX_GPIO    (1 << 7)
-
-/**
- * \brief Port pin direction configuration enum.
- *
- * Enum for the possible pin direction settings of the port pin configuration
- * structure, to indicate the direction the pin should use.
- */
-enum system_pinmux_pin_dir {
-	/** The pin's input buffer should be enabled, so that the pin state can
-	 *  be read */
-	SYSTEM_PINMUX_PIN_DIR_INPUT,
-	/** The pin's output buffer should be enabled, so that the pin state can
-	 *  be set (but not read back) */
-	SYSTEM_PINMUX_PIN_DIR_OUTPUT,
-	/** The pin's output and input buffers should both be enabled, so that the
-	 *  pin state can be set and read back */
-	SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
-};
-
-/**
- * \brief Port pin input pull configuration enum.
- *
- * Enum for the possible pin pull settings of the port pin configuration
- * structure, to indicate the type of logic level pull the pin should use.
- */
-enum system_pinmux_pin_pull {
-	/** No logical pull should be applied to the pin */
-	SYSTEM_PINMUX_PIN_PULL_NONE,
-	/** Pin should be pulled up when idle */
-	SYSTEM_PINMUX_PIN_PULL_UP,
-	/** Pin should be pulled down when idle */
-	SYSTEM_PINMUX_PIN_PULL_DOWN,
-};
-
-/**
- * \brief Port pin digital input sampling mode enum.
- *
- * Enum for the possible input sampling modes for the port pin configuration
- * structure, to indicate the type of sampling a port pin should use.
- */
-enum system_pinmux_pin_sample {
-	/** Pin input buffer should continuously sample the pin state */
-	SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
-	/** Pin input buffer should be enabled when the IN register is read */
-	SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
-};
-
-/**
- * \brief Port pin configuration structure.
- *
- * Configuration structure for a port pin instance. This structure should
- * be initialized by the \ref system_pinmux_get_config_defaults() function
- * before being modified by the user application.
- */
-struct system_pinmux_config {
-	/** MUX index of the peripheral that should control the pin, if peripheral
-	 *  control is desired. For GPIO use, this should be set to
-	 *  \ref SYSTEM_PINMUX_GPIO. */
-	uint8_t mux_position;
-
-	/** Port buffer input/output direction */
-	enum system_pinmux_pin_dir direction;
-
-	/** Logic level pull of the input buffer */
-	enum system_pinmux_pin_pull input_pull;
-
-	/** Enable lowest possible powerstate on the pin
-	 *
-	 *  \note All other configurations will be ignored, the pin will be disabled.
-	 */
-	bool powersave;
-};
-
-/** \name Configuration and Initialization
- * @{
- */
-
-/**
- * \brief Initializes a Port pin configuration structure to defaults.
- *
- * Initializes a given Port pin configuration structure to a set of
- * known default values. This function should be called on all new
- * instances of these configuration structures before being modified by the
- * user application.
- *
- * The default configuration is as follows:
- *  \li Non peripheral (i.e. GPIO) controlled
- *  \li Input mode with internal pull-up enabled
- *
- * \param[out] config  Configuration structure to initialize to default values
- */
-static inline void system_pinmux_get_config_defaults(
-		struct system_pinmux_config *const config)
-{
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->mux_position = SYSTEM_PINMUX_GPIO;
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
-	config->powersave    = false;
-}
-
-void system_pinmux_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct system_pinmux_config *const config);
-
-void system_pinmux_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct system_pinmux_config *const config);
-
-/** @} */
-
-/** \name Special Mode Configuration (Physical Group Orientated)
- *  @{
- */
-
-/**
- * \brief Retrieves the PORT module group instance from a given GPIO pin number.
- *
- * Retrieves the PORT module group instance associated with a given logical
- * GPIO pin number.
- *
- * \param[in] gpio_pin  Index of the GPIO pin to convert
- *
- * \return Base address of the associated PORT module.
- */
-static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
-		const uint8_t gpio_pin)
-{
-	uint8_t port_index  = (gpio_pin / 128);
-	uint8_t group_index = (gpio_pin / 32);
-
-	/* Array of available ports */
-	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
-
-	if (port_index < PORT_INST_NUM) {
-		return &(ports[port_index]->Group[group_index]);
-	} else {
-		Assert(false);
-		return NULL;
-	}
-}
-
-void system_pinmux_group_set_input_sample_mode(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_sample mode);
-
-/** @} */
-
-/** \name Special Mode Configuration (Logical Pin Orientated)
- *  @{
- */
-
-/**
- * \brief Retrieves the currently selected MUX position of a logical pin.
- *
- * Retrieves the selected MUX peripheral on a given logical GPIO pin.
- *
- * \param[in]  gpio_pin  Index of the GPIO pin to configure
- *
- * \return Currently selected peripheral index on the specified pin.
- */
-static inline uint8_t system_pinmux_pin_get_mux_position(
-		const uint8_t gpio_pin)
-{
-	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_index = (gpio_pin % 32);
-
-	if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
-		return SYSTEM_PINMUX_GPIO;
-	}
-
-	uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
-
-	if (pin_index & 1) {
-		return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
-	}
-	else {
-		return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
-	}
-}
-
-/**
- * \brief Configures the input sampling mode for a GPIO pin.
- *
- * Configures the input sampling mode for a GPIO input, to
- * control when the physical I/O pin value is sampled and
- * stored inside the microcontroller.
- *
- * \param[in] gpio_pin Index of the GPIO pin to configure
- * \param[in] mode     New pin sampling mode to configure
- */
-static inline void system_pinmux_pin_set_input_sample_mode(
-		const uint8_t gpio_pin,
-		const enum system_pinmux_pin_sample mode)
-{
-	PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_index = (gpio_pin % 32);
-
-	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
-		port->CTRL.reg |= (1 << pin_index);
-	} else {
-		port->CTRL.reg &= ~(1 << pin_index);
-	}
-}
-
-/** @} */
-
-#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
-/**
- * \brief Port pin drive output strength enum.
- *
- * Enum for the possible output drive strengths for the port pin
- * configuration structure, to indicate the driver strength the pin should
- * use.
- */
-enum system_pinmux_pin_strength {
-  /** Normal output driver strength */
-  SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
-  /** High current output driver strength */
-  SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
-};
-
-/**
- * \brief Configures the output driver strength mode for a GPIO pin.
- *
- * Configures the output drive strength for a GPIO output, to
- * control the amount of current the pad is able to sink/source.
- *
- * \param[in] gpio_pin  Index of the GPIO pin to configure
- * \param[in] mode      New output driver strength mode to configure
- */
-static inline void system_pinmux_pin_set_output_strength(
-    const uint8_t gpio_pin,
-    const enum system_pinmux_pin_strength mode)
-{
-  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-  uint32_t pin_index = (gpio_pin % 32);
-
-  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
-    port->PINCFG[pin_index].reg |=  PORT_PINCFG_DRVSTR;
-  }
- else {
-    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
- }
-}
-
-void system_pinmux_group_set_output_strength(
-    PortGroup *const port,
-    const uint32_t mask,
-    const enum system_pinmux_pin_strength mode);
-#endif
-
-#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
-/**
- * \brief Port pin output slew rate enum.
- *
- * Enum for the possible output drive slew rates for the port pin
- * configuration structure, to indicate the driver slew rate the pin should
- * use.
- */
-enum system_pinmux_pin_slew_rate {
-  /** Normal pin output slew rate */
-  SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
-  /** Enable slew rate limiter on the pin */
-  SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
-};
-
-/**
- * \brief Configures the output slew rate mode for a GPIO pin.
- *
- * Configures the output slew rate mode for a GPIO output, to
- * control the speed at which the physical output pin can react to
- * logical changes of the I/O pin value.
- *
- * \param[in] gpio_pin  Index of the GPIO pin to configure
- * \param[in] mode      New pin slew rate mode to configure
- */
-static inline void system_pinmux_pin_set_output_slew_rate(
-    const uint8_t gpio_pin,
-    const enum system_pinmux_pin_slew_rate mode)
-{
-  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-  uint32_t pin_index = (gpio_pin % 32);
-
-  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
-    port->PINCFG[pin_index].reg |=  PORT_PINCFG_SLEWLIM;
-  }
-  else {
-    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
-  }
-}
-
-void system_pinmux_group_set_output_slew_rate(
-   PortGroup *const port,
-    const uint32_t mask,
-    const enum system_pinmux_pin_slew_rate mode);
-#endif
-
-#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
-/**
- * \brief Port pin output drive mode enum.
- *
- * Enum for the possible output drive modes for the port pin configuration
- * structure, to indicate the output mode the pin should use.
- */
-enum system_pinmux_pin_drive {
-  /** Use totem pole output drive mode */
-  SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
-  /** Use open drain output drive mode */
-  SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
-};
-
-/**
- * \brief Configures the output driver mode for a GPIO pin.
- *
- * Configures the output driver mode for a GPIO output, to
- * control the pad behavior.
- *
- * \param[in] gpio_pin  Index of the GPIO pin to configure
- * \param[in] mode      New pad output driver mode to configure
- */
-static inline void system_pinmux_pin_set_output_drive(
-    const uint8_t gpio_pin,
-    const enum system_pinmux_pin_drive mode)
-{
-  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-  uint32_t pin_index = (gpio_pin % 32);
-
-  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
-    port->PINCFG[pin_index].reg |=  PORT_PINCFG_ODRAIN;
-  }
-  else {
-    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
-  }
-}
-
-void system_pinmux_group_set_output_drive(
-    PortGroup *const port,
-    const uint32_t mask,
-    const enum system_pinmux_pin_drive mode);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-/**
- * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
- *
- * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
- * The table below presents the acronyms used in this module:
- *
- * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>GPIO</td>
- *		<td>General Purpose Input/Output</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
- * </table>
- *
- *
- * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- *  - None
- *
- *
- * \section asfdoc_sam0_system_pinmux_extra_errata Errata
- * There are no errata related to this driver.
- *
- *
- * \section asfdoc_sam0_system_pinmux_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Removed code of open drain, slew limit and drive strength
- *		features</td>
- *	</tr>
- *	<tr>
- *		<td>Fixed broken sampling mode function implementations, which wrote
- *		    corrupt configuration values to the device registers</td>
- *	</tr>
- *	<tr>
- *		<td>Added missing NULL pointer asserts to the PORT driver functions</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
- * </table>
- */
-
-/**
- * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
- *
- * This is a list of the available Quick Start guides (QSGs) and example
- * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
- * examples with step-by-step instructions to configure and use this driver in a
- * selection of use cases. Note that a QSG can be compiled as a standalone
- * application or be added to the user application.
- *
- *  - \subpage asfdoc_sam0_system_pinmux_basic_use_case
- *
- * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
- *
- * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42121F</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42121E</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42121D</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42121C</td>
- *		<td>09/2013</td>
- *		<td>Fixed incorrect documentation for the device pin sampling mode</td>
- *	</tr>
- *	<tr>
- *		<td>42121B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42121A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
- * </table>
- */
-
-#endif
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef PINMUX_H_INCLUDED
+#define PINMUX_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's physical
+ * I/O Pins, to alter the direction and input/drive characteristics as well as
+ * to configure the pin peripheral multiplexer selection.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (Port I/O Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_pinmux_prerequisites
+ *  - \ref asfdoc_sam0_system_pinmux_module_overview
+ *  - \ref asfdoc_sam0_system_pinmux_special_considerations
+ *  - \ref asfdoc_sam0_system_pinmux_extra_info
+ *  - \ref asfdoc_sam0_system_pinmux_examples
+ *  - \ref asfdoc_sam0_system_pinmux_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
+ *
+ * The SAM devices contain a number of General Purpose I/O pins, used to
+ * interface the user application logic and internal hardware peripherals to
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method
+ * of configuring the individual pin peripheral multiplexers to select
+ * alternate pin functions.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
+ *    <td>SAM L21, SAM C20/C21, SAM R34/R35</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
+ * SAM devices contain a peripheral MUX, which is individually controllable
+ * for each I/O pin of the device. The peripheral MUX allows you to select the
+ * function of a physical package pin - whether it will be controlled as a user
+ * controllable GPIO pin, or whether it will be connected internally to one of
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
+ * configured in GPIO mode, other peripherals connected to the same pin will be
+ * disabled.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
+ * There are several special modes that can be selected on one or more I/O pins
+ * of the device, which alter the input and output characteristics of the pad.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
+ * The Drive Strength configures the strength of the output driver on the
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely
+ * drive, however some I/O pads offer a higher drive mode which increases this
+ * limit for that I/O pin at the expense of an increased power consumption.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
+ * The Slew Rate configures the slew rate of the output driver, limiting the
+ * rate at which the pad output voltage can change with time.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
+ * The Input Sample Mode configures the input sampler buffer of the pad. By
+ * default, the input buffer is only sampled "on-demand", i.e. when the user
+ * application attempts to read from the input buffer. This mode is the most
+ * power efficient, but increases the latency of the input sample by two clock
+ * cycles of the port clock. To reduce latency, the input sampler can instead
+ * be configured to always sample the input buffer on each port clock cycle, at
+ * the expense of an increased power consumption.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
+ * how this module is interconnected within the device:
+ *
+ * \anchor asfdoc_sam0_system_pinmux_intconnections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampling mode is set in groups of four physical
+ * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
+ * will configure the sampling mode of the entire sub-group.
+ *
+ * High Drive Strength output driver mode is not available on all device pins -
+ * refer to your device specific datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
+ *  - \ref asfdoc_sam0_system_pinmux_extra_acronyms
+ *  - \ref asfdoc_sam0_system_pinmux_extra_dependencies
+ *  - \ref asfdoc_sam0_system_pinmux_extra_errata
+ *  - \ref asfdoc_sam0_system_pinmux_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_pinmux_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/ 
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || (SAMR34) || (SAMR35) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support */
+#  define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+#endif
+/*@}*/
+
+/** Peripheral multiplexer index to select GPIO mode for a pin */
+#define SYSTEM_PINMUX_GPIO    (1 << 7)
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum system_pinmux_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set (but not read back) */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should both be enabled, so that the
+	 *  pin state can be set and read back */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum system_pinmux_pin_pull {
+	/** No logical pull should be applied to the pin */
+	SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin digital input sampling mode enum.
+ *
+ * Enum for the possible input sampling modes for the port pin configuration
+ * structure, to indicate the type of sampling a port pin should use.
+ */
+enum system_pinmux_pin_sample {
+	/** Pin input buffer should continuously sample the pin state */
+	SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+	/** Pin input buffer should be enabled when the IN register is read */
+	SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should
+ * be initialized by the \ref system_pinmux_get_config_defaults() function
+ * before being modified by the user application.
+ */
+struct system_pinmux_config {
+	/** MUX index of the peripheral that should control the pin, if peripheral
+	 *  control is desired. For GPIO use, this should be set to
+	 *  \ref SYSTEM_PINMUX_GPIO. */
+	uint8_t mux_position;
+
+	/** Port buffer input/output direction */
+	enum system_pinmux_pin_dir direction;
+
+	/** Logic level pull of the input buffer */
+	enum system_pinmux_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin configuration structure to defaults.
+ *
+ * Initializes a given Port pin configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Non peripheral (i.e. GPIO) controlled
+ *  \li Input mode with internal pull-up enabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_pinmux_get_config_defaults(
+		struct system_pinmux_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	config->powersave    = false;
+}
+
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config);
+
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config);
+
+/** @} */
+
+/** \name Special Mode Configuration (Physical Group Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	uint8_t port_index  = (gpio_pin / 128);
+	uint8_t group_index = (gpio_pin / 32);
+
+	/* Array of available ports */
+	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+	if (port_index < PORT_INST_NUM) {
+		return &(ports[port_index]->Group[group_index]);
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode);
+
+/** @} */
+
+/** \name Special Mode Configuration (Logical Pin Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the currently selected MUX position of a logical pin.
+ *
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.
+ *
+ * \param[in]  gpio_pin  Index of the GPIO pin to configure
+ *
+ * \return Currently selected peripheral index on the specified pin.
+ */
+static inline uint8_t system_pinmux_pin_get_mux_position(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
+		return SYSTEM_PINMUX_GPIO;
+	}
+
+	uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+	if (pin_index & 1) {
+		return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	}
+	else {
+		return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a GPIO pin.
+ *
+ * Configures the input sampling mode for a GPIO input, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+static inline void system_pinmux_pin_set_input_sample_mode(
+		const uint8_t gpio_pin,
+		const enum system_pinmux_pin_sample mode)
+{
+	PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= (1 << pin_index);
+	} else {
+		port->CTRL.reg &= ~(1 << pin_index);
+	}
+}
+
+/** @} */
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Port pin drive output strength enum.
+ *
+ * Enum for the possible output drive strengths for the port pin
+ * configuration structure, to indicate the driver strength the pin should
+ * use.
+ */
+enum system_pinmux_pin_strength {
+  /** Normal output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
+  /** High current output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
+};
+
+/**
+ * \brief Configures the output driver strength mode for a GPIO pin.
+ *
+ * Configures the output drive strength for a GPIO output, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New output driver strength mode to configure
+ */
+static inline void system_pinmux_pin_set_output_strength(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_strength mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_DRVSTR;
+  }
+ else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
+ }
+}
+
+void system_pinmux_group_set_output_strength(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_strength mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Port pin output slew rate enum.
+ *
+ * Enum for the possible output drive slew rates for the port pin
+ * configuration structure, to indicate the driver slew rate the pin should
+ * use.
+ */
+enum system_pinmux_pin_slew_rate {
+  /** Normal pin output slew rate */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
+  /** Enable slew rate limiter on the pin */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
+};
+
+/**
+ * \brief Configures the output slew rate mode for a GPIO pin.
+ *
+ * Configures the output slew rate mode for a GPIO output, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pin slew rate mode to configure
+ */
+static inline void system_pinmux_pin_set_output_slew_rate(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_slew_rate mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_SLEWLIM;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
+  }
+}
+
+void system_pinmux_group_set_output_slew_rate(
+   PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_slew_rate mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Port pin output drive mode enum.
+ *
+ * Enum for the possible output drive modes for the port pin configuration
+ * structure, to indicate the output mode the pin should use.
+ */
+enum system_pinmux_pin_drive {
+  /** Use totem pole output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
+  /** Use open drain output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
+};
+
+/**
+ * \brief Configures the output driver mode for a GPIO pin.
+ *
+ * Configures the output driver mode for a GPIO output, to
+ * control the pad behavior.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pad output driver mode to configure
+ */
+static inline void system_pinmux_pin_set_output_drive(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_drive mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_ODRAIN;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
+  }
+}
+
+void system_pinmux_group_set_output_drive(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_drive mode);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed code of open drain, slew limit and drive strength
+ *		features</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Fixed broken sampling mode function implementations, which wrote
+ *		    corrupt configuration values to the device registers</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added missing NULL pointer asserts to the PORT driver functions</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_pinmux_basic_use_case
+ *
+ * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121C</td>
+ *		<td>09/2013</td>
+ *		<td>Fixed incorrect documentation for the device pin sampling mode</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h
index 2d0b417..d17aa47 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h
@@ -1,86 +1,86 @@
-/**
- * \file
- *
- * \brief SAM PINMUX Driver Quick Start
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-/**
- * \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
- *
- * In this use case, the PINMUX module is configured for:
- *  \li One pin in input mode, with pull-up enabled, connected to the GPIO
- *      module
- *  \li Sampling mode of the pin changed to sample on demand
- *
- * This use case sets up the PINMUX to configure a physical I/O pin set as
- * an input with pull-up and changes the sampling mode of the pin to reduce
- * power by only sampling the physical pin state when the user application
- * attempts to read it.
- *
- * \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
- *
- * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
- * There are no special setup requirements for this use-case.
- *
- * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
- * Copy-paste the following setup code to your application:
- * \snippet qs_pinmux_basic.c setup
- *
- * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
- * -# Create a PINMUX module pin configuration struct, which can be filled out
- *    to adjust the configuration of a single port pin.
- *    \snippet qs_pinmux_basic.c pinmux_config
- * -# Initialize the pin configuration struct with the module's default values.
- *    \snippet qs_pinmux_basic.c pinmux_config_defaults
- *    \note This should always be performed before using the configuration
- *          struct to ensure that all values are initialized to known default
- *          settings.
- *
- * -# Adjust the configuration struct to request an input pin with pull-up
- *    connected to the GPIO peripheral.
- *  \snippet qs_pinmux_basic.c pinmux_update_config_values
- * -# Configure GPIO10 with the initialized pin configuration struct, to enable
- *    the input sampler on the pin.
- *    \snippet qs_pinmux_basic.c pinmux_set_config
- *
- * \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
- *
- * \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
- * Copy-paste the following code to your user application:
- * \snippet qs_pinmux_basic.c main
- *
- * \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
-
- * -# Adjust the configuration of the pin to enable on-demand sampling mode.
- *    \snippet qs_pinmux_basic.c pinmux_change_input_sampling
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
+/**
+ * \file
+ *
+ * \brief SAM PINMUX Driver Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
+ *
+ * In this use case, the PINMUX module is configured for:
+ *  \li One pin in input mode, with pull-up enabled, connected to the GPIO
+ *      module
+ *  \li Sampling mode of the pin changed to sample on demand
+ *
+ * This use case sets up the PINMUX to configure a physical I/O pin set as
+ * an input with pull-up and changes the sampling mode of the pin to reduce
+ * power by only sampling the physical pin state when the user application
+ * attempts to read it.
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your application:
+ * \snippet qs_pinmux_basic.c setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
+ * -# Create a PINMUX module pin configuration struct, which can be filled out
+ *    to adjust the configuration of a single port pin.
+ *    \snippet qs_pinmux_basic.c pinmux_config
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_pinmux_basic.c pinmux_config_defaults
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin with pull-up
+ *    connected to the GPIO peripheral.
+ *  \snippet qs_pinmux_basic.c pinmux_update_config_values
+ * -# Configure GPIO10 with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_pinmux_basic.c pinmux_set_config
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_pinmux_basic.c main
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
+
+ * -# Adjust the configuration of the pin to enable on-demand sampling mode.
+ *    \snippet qs_pinmux_basic.c pinmux_change_input_sampling
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h
index 90a5b91..32aacc9 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/power/power_sam_d_r_h/power.h
@@ -1,239 +1,239 @@
-/**
- * \file
- *
- * \brief SAM Power related functionality
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef POWER_H_INCLUDED
-#define POWER_H_INCLUDED
-
-#include <compiler.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* MCU revision number */
-#define _SYSTEM_MCU_REVISION_D 3
-#define _SYSTEM_MCU_REVISION_E 4
-
-/**
- * \addtogroup asfdoc_sam0_system_group
- * @{
- */
-
-/**
- * \brief Voltage references within the device.
- *
- * List of available voltage references (VREF) that may be used within the
- * device.
- */
-enum system_voltage_reference {
-	/** Temperature sensor voltage reference */
-	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
-	/** Bandgap voltage reference */
-	SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
-};
-
-/**
- * \brief Device sleep modes.
- *
- * List of available sleep modes in the device. A table of clocks available in
- * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
- */
-enum system_sleepmode {
-	/** IDLE 0 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_0,
-	/** IDLE 1 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_1,
-	/** IDLE 2 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_2,
-	/** Standby sleep mode */
-	SYSTEM_SLEEPMODE_STANDBY,
-};
-
-
-
-/**
- * \name Voltage References
- * @{
- */
-
-/**
- * \brief Enable the selected voltage reference
- *
- * Enables the selected voltage reference source, making the voltage reference
- * available on a pin as well as an input source to the analog peripherals.
- *
- * \param[in] vref  Voltage reference to enable
- */
-static inline void system_voltage_reference_enable(
-		const enum system_voltage_reference vref)
-{
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
-			break;
-
-		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
-			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
-			break;
-
-		default:
-			Assert(false);
-			return;
-	}
-}
-
-/**
- * \brief Disable the selected voltage reference
- *
- * Disables the selected voltage reference source.
- *
- * \param[in] vref  Voltage reference to disable
- */
-static inline void system_voltage_reference_disable(
-		const enum system_voltage_reference vref)
-{
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
-			break;
-
-		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
-			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
-			break;
-
-		default:
-			Assert(false);
-			return;
-	}
-}
-
-/**
- * @}
- */
-
-
-/**
- * \name Device Sleep Control
- * @{
- */
-
-/**
- * \brief Set the sleep mode of the device
- *
- * Sets the sleep mode of the device; the configured sleep mode will be entered
- * upon the next call of the \ref system_sleep() function.
- *
- * For an overview of which systems are disabled in sleep for the different
- * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
- *
- * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
- *
- * \retval STATUS_OK               Operation completed successfully
- * \retval STATUS_ERR_INVALID_ARG  The requested sleep mode was invalid or not
- *                                 available
- */
-static inline enum status_code system_set_sleepmode(
-	const enum system_sleepmode sleep_mode)
-{
-
-#if (SAMD20 || SAMD21 || SAMR21)
-
-	/* Get MCU revision */
-	uint32_t rev = DSU->DID.reg;
-
-	rev &= DSU_DID_REVISION_Msk;
-	rev = rev >> DSU_DID_REVISION_Pos;
-
-#if (SAMD20)
-	if (rev < _SYSTEM_MCU_REVISION_E) {
-		/* Errata 13140: Make sure that the Flash does not power all the way down
-		 * when in sleep mode. */
-		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
-	}
-#endif
-
-#if (SAMD21 || SAMR21)
-	if (rev < _SYSTEM_MCU_REVISION_D) {
-		/* Errata 13140: Make sure that the Flash does not power all the way down
-		 * when in sleep mode. */
-		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
-	}
-#endif
-
-#endif
-
-	switch (sleep_mode) {
-		case SYSTEM_SLEEPMODE_IDLE_0:
-		case SYSTEM_SLEEPMODE_IDLE_1:
-		case SYSTEM_SLEEPMODE_IDLE_2:
-			SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-			PM->SLEEP.reg = sleep_mode;
-			break;
-
-		case SYSTEM_SLEEPMODE_STANDBY:
-			SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
-			break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
-}
-
-/**
- * \brief Put the system to sleep waiting for interrupt
- *
- * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
- * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
- * instruction to place the device into the sleep mode specified by
- * \ref system_set_sleepmode until woken by an interrupt.
- */
-static inline void system_sleep(void)
-{
-	__DSB();
-	__WFI();
-}
-
-/**
- * @}
- */
-
-/** @} */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* POWER_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Power related functionality
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MCU revision number */
+#define _SYSTEM_MCU_REVISION_D 3
+#define _SYSTEM_MCU_REVISION_E 4
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Voltage references within the device.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+	/** Temperature sensor voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+	/** Bandgap voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
+};
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+	/** IDLE 0 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_0,
+	/** IDLE 1 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_1,
+	/** IDLE 2 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_2,
+	/** Standby sleep mode */
+	SYSTEM_SLEEPMODE_STANDBY,
+};
+
+
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Enable the selected voltage reference
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref  Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+			break;
+
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * \brief Disable the selected voltage reference
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref  Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+			break;
+
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
+ *
+ * \retval STATUS_OK               Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG  The requested sleep mode was invalid or not
+ *                                 available
+ */
+static inline enum status_code system_set_sleepmode(
+	const enum system_sleepmode sleep_mode)
+{
+
+#if (SAMD20 || SAMD21 || SAMR21)
+
+	/* Get MCU revision */
+	uint32_t rev = DSU->DID.reg;
+
+	rev &= DSU_DID_REVISION_Msk;
+	rev = rev >> DSU_DID_REVISION_Pos;
+
+#if (SAMD20)
+	if (rev < _SYSTEM_MCU_REVISION_E) {
+		/* Errata 13140: Make sure that the Flash does not power all the way down
+		 * when in sleep mode. */
+		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+	}
+#endif
+
+#if (SAMD21 || SAMR21)
+	if (rev < _SYSTEM_MCU_REVISION_D) {
+		/* Errata 13140: Make sure that the Flash does not power all the way down
+		 * when in sleep mode. */
+		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+	}
+#endif
+
+#endif
+
+	switch (sleep_mode) {
+		case SYSTEM_SLEEPMODE_IDLE_0:
+		case SYSTEM_SLEEPMODE_IDLE_1:
+		case SYSTEM_SLEEPMODE_IDLE_2:
+			SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+			PM->SLEEP.reg = sleep_mode;
+			break;
+
+		case SYSTEM_SLEEPMODE_STANDBY:
+			SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
+			break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
+ * instruction to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode until woken by an interrupt.
+ */
+static inline void system_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
index d7b21ce..8654829 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
@@ -1,109 +1,109 @@
-/**
- * \file
- *
- * \brief SAM Reset related functionality
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef RESET_H_INCLUDED
-#define RESET_H_INCLUDED
-
-#include <compiler.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup asfdoc_sam0_system_group
- * @{
- */
-
-/**
- * \brief Reset causes of the system.
- *
- * List of possible reset causes of the system.
- */
-enum system_reset_cause {
-	/** The system was last reset by a software reset */
-	SYSTEM_RESET_CAUSE_SOFTWARE       = PM_RCAUSE_SYST,
-	/** The system was last reset by the watchdog timer */
-	SYSTEM_RESET_CAUSE_WDT            = PM_RCAUSE_WDT,
-	/** The system was last reset because the external reset line was pulled low */
-	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
-	/** The system was last reset by the BOD33 */
-	SYSTEM_RESET_CAUSE_BOD33          = PM_RCAUSE_BOD33,
-	/** The system was last reset by the BOD12 */
-	SYSTEM_RESET_CAUSE_BOD12          = PM_RCAUSE_BOD12,
-	/** The system was last reset by the POR (Power on reset) */
-	SYSTEM_RESET_CAUSE_POR            = PM_RCAUSE_POR,
-};
-
-
-/**
- * \name Reset Control
- * @{
- */
-
-/**
- * \brief Reset the MCU.
- *
- * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
- * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
- *
- */
-static inline void system_reset(void)
-{
-	NVIC_SystemReset();
-}
-
-/**
- * \brief Return the reset cause.
- *
- * Retrieves the cause of the last system reset.
- *
- * \return An enum value indicating the cause of the last system reset.
- */
-static inline enum system_reset_cause system_get_reset_cause(void)
-{
-	return (enum system_reset_cause)PM->RCAUSE.reg;
-}
-
-/**
- * @}
- */
-
-/** @} */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* RESET_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM Reset related functionality
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+	/** The system was last reset by a software reset */
+	SYSTEM_RESET_CAUSE_SOFTWARE       = PM_RCAUSE_SYST,
+	/** The system was last reset by the watchdog timer */
+	SYSTEM_RESET_CAUSE_WDT            = PM_RCAUSE_WDT,
+	/** The system was last reset because the external reset line was pulled low */
+	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
+	/** The system was last reset by the BOD33 */
+	SYSTEM_RESET_CAUSE_BOD33          = PM_RCAUSE_BOD33,
+	/** The system was last reset by the BOD12 */
+	SYSTEM_RESET_CAUSE_BOD12          = PM_RCAUSE_BOD12,
+	/** The system was last reset by the POR (Power on reset) */
+	SYSTEM_RESET_CAUSE_POR            = PM_RCAUSE_POR,
+};
+
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
+ * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
+ *
+ */
+static inline void system_reset(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Return the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+	return (enum system_reset_cause)PM->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.c b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.c
index f5f6709..6b17113 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.c
@@ -1,101 +1,101 @@
-/**
- * \file
- *
- * \brief SAM System related functionality
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include <system.h>
-
-/**
- * \internal
- * Dummy initialization function, used as a weak alias target for the various
- * init functions called by \ref system_init().
- */
-void _system_dummy_init(void);
-void _system_dummy_init(void)
-{
-	return;
-}
-
-#if !defined(__DOXYGEN__)
-#  if defined(__GNUC__)
-void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
-void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
-void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
-void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
-void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init")));
-#  elif defined(__ICCARM__)
-void system_clock_init(void);
-void system_board_init(void);
-void _system_events_init(void);
-void _system_extint_init(void);
-void _system_divas_init(void);
-#    pragma weak system_clock_init=_system_dummy_init
-#    pragma weak system_board_init=_system_dummy_init
-#    pragma weak _system_events_init=_system_dummy_init
-#    pragma weak _system_extint_init=_system_dummy_init
-#    pragma weak _system_divas_init=_system_dummy_init
-#  endif
-#endif
-
-/**
- * \brief Initialize system
- *
- * This function will call the various initialization functions within the
- * system namespace. If a given optional system module is not available, the
- * associated call will effectively be a NOP (No Operation).
- *
- * Currently the following initialization functions are supported:
- *  - System clock initialization (via the SYSTEM CLOCK sub-module)
- *  - Board hardware initialization (via the Board module)
- *  - Event system driver initialization (via the EVSYS module)
- *  - External Interrupt driver initialization (via the EXTINT module)
- */
-void system_init(void)
-{
-	/* Configure GCLK and clock sources according to conf_clocks.h */
-	system_clock_init();
-
-	/* Initialize board hardware */
-	system_board_init();
-
-	/* Initialize EVSYS hardware */
-	_system_events_init();
-
-	/* Initialize External hardware */
-	_system_extint_init();
-	
-	/* Initialize DIVAS hardware */
-	_system_divas_init();
-}
-
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <system.h>
+
+/**
+ * \internal
+ * Dummy initialization function, used as a weak alias target for the various
+ * init functions called by \ref system_init().
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+	return;
+}
+
+#if !defined(__DOXYGEN__)
+#  if defined(__GNUC__)
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+#  elif defined(__ICCARM__)
+void system_clock_init(void);
+void system_board_init(void);
+void _system_events_init(void);
+void _system_extint_init(void);
+void _system_divas_init(void);
+#    pragma weak system_clock_init=_system_dummy_init
+#    pragma weak system_board_init=_system_dummy_init
+#    pragma weak _system_events_init=_system_dummy_init
+#    pragma weak _system_extint_init=_system_dummy_init
+#    pragma weak _system_divas_init=_system_dummy_init
+#  endif
+#endif
+
+/**
+ * \brief Initialize system
+ *
+ * This function will call the various initialization functions within the
+ * system namespace. If a given optional system module is not available, the
+ * associated call will effectively be a NOP (No Operation).
+ *
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization (via the SYSTEM CLOCK sub-module)
+ *  - Board hardware initialization (via the Board module)
+ *  - Event system driver initialization (via the EVSYS module)
+ *  - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+	/* Configure GCLK and clock sources according to conf_clocks.h */
+	system_clock_init();
+
+	/* Initialize board hardware */
+	system_board_init();
+
+	/* Initialize EVSYS hardware */
+	_system_events_init();
+
+	/* Initialize External hardware */
+	_system_extint_init();
+	
+	/* Initialize DIVAS hardware */
+	_system_divas_init();
+}
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.h b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.h
index 49a410d..b2c31b9 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/drivers/system/system.h
@@ -1,721 +1,721 @@
-/**
- * \file
- *
- * \brief SAM System related functionality
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef SYSTEM_H_INCLUDED
-#define SYSTEM_H_INCLUDED
-
-#include <compiler.h>
-#include <clock.h>
-#include <gclk.h>
-#include <pinmux.h>
-#include <power.h>
-#include <reset.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver
- *
- * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
- * and management of the device's system relation functionality, necessary for
- * the basic device operation. This is not limited to a single peripheral, but
- * extends across multiple hardware peripherals.
- *
- * The following peripherals are used by this module:
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- *  - PM (Power Manager)
- *  - RSTC (Reset Controller)
- *  - SUPC (Supply Controller)
- * \endif
- * \if DEVICE_SAMC21_SYSTEM_SUPPORT
- *  - PM (Power Manager)
- *  - RSTC (Reset Controller)
- *  - SUPC (Supply Controller)
- * \endif
- * \if DEVICE_SAMD21_SYSTEM_SUPPORT
- *  - SYSCTRL (System Control)
- *  - PM (Power Manager)
- * \endif
- *
- * The following devices can use this module:
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- *  - Atmel | SMART SAM L21
- *  - Atmel | SMART SAM R30
- *  - Atmel | SMART SAM R34
- *  - Atmel | SMART SAM R35
- * \endif
- * \if DEVICE_SAMC21_SYSTEM_SUPPORT
- *  - Atmel | SMART SAM C20/C21
- * \endif
- * \if DEVICE_SAMD21_SYSTEM_SUPPORT
- *  - Atmel | SMART SAM D20/D21
- *  - Atmel | SMART SAM R21
- *  - Atmel | SMART SAM D09/D10/D11
- *  - Atmel | SMART SAM DA1
- * \endif
- *
- * The outline of this documentation is as follows:
- *  - \ref asfdoc_sam0_system_prerequisites
- *  - \ref asfdoc_sam0_system_module_overview
- *  - \ref asfdoc_sam0_system_special_considerations
- *  - \ref asfdoc_sam0_system_extra_info
- *  - \ref asfdoc_sam0_system_examples
- *  - \ref asfdoc_sam0_system_api_overview
- *
- *
- * \section asfdoc_sam0_system_prerequisites Prerequisites
- *
- * There are no prerequisites for this module.
- *
- *
- * \section asfdoc_sam0_system_module_overview Module Overview
- *
- * The System driver provides a collection of interfaces between the user
- * application logic, and the core device functionality (such as clocks, reset
- * cause determination, etc.) that is required for all applications. It contains
- * a number of sub-modules that control one specific aspect of the device:
- *
- * - System Core (this module)
- * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
- * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
- * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
- *
- *
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator
- * The SAM device controls the voltage regulators for the core (VDDCORE) and
- * backup (VDDBU) domains. It sets the voltage regulators according to the sleep
- * modes, the performance level, or the user configuration.
- *
- * In active mode, the voltage regulator can be chosen on the fly between a LDO
- * or a Buck converter. In standby mode, the low power voltage regulator is used
- * to supply VDDCORE.
- *
- * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
- * The SAM device supports connection of a battery backup to the VBAT power pin.
- * It includes functionality that enables automatic power switching between main
- * power and battery backup power. This will ensure power to the backup domain,
- * when the main battery or power source is unavailable.
- * \endif
- *
- * \if DEVICE_SAMC21_SYSTEM_SUPPORT
- * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator
- * The SAM device controls the voltage regulators for the core (VDDCORE). It sets
- * the voltage regulators according to the sleep modes.
- *
- * There are a selectable reference voltage and voltage dependent on the temperature
- * which can be used by analog modules like the ADC.
- * \endif
- *
- * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
- * The various analog modules within the SAM devices (such as AC, ADC, and
- * DAC) require a voltage reference to be configured to act as a reference point
- * for comparisons and conversions.
- *
- * The SAM devices contain multiple references, including an internal
- * temperature sensor and a fixed band-gap voltage source. When enabled, the
- * associated voltage reference can be selected within the desired peripheral
- * where applicable.
- *
- * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
- * In some applications there may be a need to execute a different program
- * flow based on how the device was reset. For example, if the cause of reset
- * was the Watchdog timer (WDT), this might indicate an error in the application,
- * and a form of error handling or error logging might be needed.
- *
- * For this reason, an API is provided to retrieve the cause of the last system
- * reset, so that appropriate action can be taken.
- *
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- * There are three groups of reset sources:
- *   - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset.
- *   - User reset: Resets caused by the application. It covers external reset,
- *             system reset, and watchdog reset.
- *   - Backup reset: Resets caused by a backup mode exit condition.
- *
- * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
- * Performance level allows the user to adjust the regulator output voltage to reduce
- * power consumption. The user can on the fly select the most suitable performance
- * level, depending on the application demands.
- *
- * The SAM device can operate at two different performance levels (PL0 and PL2).
- * When operating at PL0, the voltage applied on the full logic area is reduced
- * by voltage scaling. This voltage scaling technique allows to reduce the active
- * power consumption while decreasing the maximum frequency of the device. When
- * operating at PL2, the voltage regulator supplies the highest voltage, allowing
- * the device to run at higher clock speeds.
- *
- * Performance level transition is possible only when the device is in active
- * mode. After a reset, the device starts at the lowest performance level
- * (lowest power consumption and lowest max. frequency). The application can then
- * switch to another performance level at any time without any stop in the code
- * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
- *
- * \note When scaling down the performance level, the bus frequency should first be
- *  scaled down in order to not exceed the maximum frequency allowed for the
- *  low performance level.
- *  When scaling up the performance level (e.g. from PL0 to PL2), check the performance
- *  level status before increasing the bus frequency. It can be increased only
- *  when the performance level transition is completed.
- *
- * \anchor asfdoc_sam0_system_performance_level_transition_figure
- * \image html performance_level_transition.svg "Performance Level Transition"
- *
- * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
- * Power domain gating allows power saving by reducing the voltage in logic
- * areas in the device to a low-power supply. The feature is available in
- * Standby sleep mode and will reduce the voltage in domains where all peripherals
- * are idle. Internal logic will maintain its content, meaning the corresponding
- * peripherals will not need to be reconfigured when normal operating voltage
- * is returned. Most power domains can be in the following three states:
- *
- * - Active state: The power domain is powered on.
- * - Retention state: The main voltage supply for the power domain is switched off,
- * while maintaining a secondary low-power supply for the sequential cells. The
- * logic context is restored when waking up.
- * - Off state: The power domain is entirely powered off. The logic context is lost.
- *
- * The SAM L21 device  contains three power domains which can be controlled using
- * power domain gating, namely PD0, PD1, and PD2. These power domains can be
- * configured to the following cases:
- * - Default with no sleepwalking peripherals: A power domain is automatically set
- * to retention state in standby sleep mode if no activity require it. The application
- * can force all power domains to remain in active state during standby sleep mode
- * in order to accelerate wakeup time.
- * - Default with sleepwalking peripherals: If one or more peripherals are enabled
- * to perform sleepwalking tasks in standby sleep mode, the corresponding power
- * domain (PDn) remains in active state as well as all inferior power domains (<PDn).
- * - Sleepwalking with dynamic power domain gating: During standby sleep mode, a
- * power domain (PDn) in active can wake up a superior power domain (>PDn) in order
- * to perform a sleepwalking task. The superior power domain is then automatically
- * set to active state. At the end of the sleepwalking task, the device can either
- * be woken up or the superior power domain can return to retention state.
- *
- * Power domains can be linked to each other, it allows a power domain (PDn) to be kept
- * in active state if the inferior power domain (PDn-1) is in active state too.
- *
- * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
- * four cases to consider in standby mode.
- *
- * \anchor asfdoc_sam0_system_power_domain_overview_table
- * <table>
- *  <caption>Sleep Mode versus Power Domain State Overview</caption>
- *  <tr>
- *      <th>Sleep mode</th>
- *      <th>PD0</th>
- *      <th>PD1</th>
- *      <th>PD2</th>
- *      <th>PDTOP</th>
- *      <th>PDBACKUP</th>
- *  </tr>
- *  <tr>
- *      <td>Idle</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>active</td>
- *  </tr>
- *  <tr>
- *      <td>Standby - Case 1</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>active</td>
- *  </tr>
- *  <tr>
- *      <td>Standby - Case 2</td>
- *      <td>active</td>
- *      <td>active</td>
- *      <td>retention</td>
- *      <td>active</td>
- *      <td>active</td>
- *  </tr>
- *  <tr>
- *      <td>Standby - Case 3</td>
- *      <td>active</td>
- *      <td>retention</td>
- *      <td>retention</td>
- *      <td>active</td>
- *      <td>active</td>
- *  </tr>
- *  <tr>
- *      <td>Standby - Case 4</td>
- *      <td>retention</td>
- *      <td>retention</td>
- *      <td>retention</td>
- *      <td>active</td>
- *      <td>active</td>
- *  </tr>
- *  <tr>
- *      <td>Backup</td>
- *      <td>off</td>
- *      <td>off</td>
- *      <td>off</td>
- *      <td>off</td>
- *      <td>active</td>
- *  </tr>
- *  <tr>
- *      <td>Off</td>
- *      <td>off</td>
- *      <td>off</td>
- *      <td>off</td>
- *      <td>off</td>
- *      <td>off</td>
- *  </tr>
- * </table>
- *
- * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
- * By default, in standby sleep mode, RAM is in low power mode (back biased)
- * if its power domain is in retention state.
- * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
- *
- * \anchor asfdoc_sam0_system_power_ram_state_table
- * <table>
- *  <caption>RAM Back-biasing Mode</caption>
- *  <tr>
- *      <th>RAM mode</th>
- *      <th>Description</th>
- *  </tr>
- *  <tr>
- *      <td>Retention Back-biasing mode</td>
- *      <td>RAM is back-biased if its power domain is in retention mode</td>
- *  </tr>
- *  <tr>
- *      <td>Standby Back-biasing mode</td>
- *      <td>RAM is back-biased if the device is in standby mode</td>
- *  </tr>
- *  <tr>
- *      <td>Standby OFF mode</td>
- *      <td>RAM is OFF if the device is in standby mode</td>
- *  </tr>
- *  <tr>
- *      <td>Always OFF mode</td>
- *      <td>RAM is OFF if the device is in RET mode</td>
- *  </tr>
- * </table>
- *
- * \endif
- *
- * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
- * The SAM devices have several sleep modes. The sleep mode controls
- * which clock systems on the device will remain enabled or disabled when the
- * device enters a low power sleep mode.
- * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
- * clock settings of the different sleep modes.
- *
- * \anchor asfdoc_sam0_system_module_sleep_mode_table
- * <table>
- *  <caption>SAM Device Sleep Modes</caption>
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- *  <tr>
- *      <th>Sleep mode</th>
- *      <th>System clock</th>
- *      <th>CPU clock</th>
- *      <th>AHB/AHB clock</th>
- *      <th>GCLK clocks</th>
- *      <th>Oscillators (ONDEMAND  = 0)</th>
- *      <th>Oscillators (ONDEMAND  = 1)</th>
- *      <th>Regulator mode</th>
- *      <th>RAM mode</th>
- *  </tr>
- *  <tr>
- *      <td>Idle</td>
- *      <td>Run</td>
- *      <td>Stop</td>
- *      <td>Run if requested</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run if requested</td>
- *      <td>Normal</td>
- *      <td>Normal</td>
- *  </tr>
- *  <tr>
- *      <td>Standby</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Run if requested</td>
- *      <td>Run if requested</td>
- *      <td>Run if requested or RUNSTDBY  = 1</td>
- *      <td>Run if requested</td>
- *      <td>Low pwer</td>
- *      <td>Low pwer</td>
- *  </tr>
- *  <tr>
- *      <td>Backup</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Backup</td>
- *      <td>Off</td>
- *  </tr>
- *  <tr>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *      <td>Off</td>
- *  </tr>
- * \else
- *  <tr>
- *      <th>Sleep mode</th>
- *      <th>CPU clock</th>
- *      <th>AHB clock</th>
- *      <th>APB clocks</th>
- *      <th>Clock sources</th>
- *      <th>System clock</th>
- *      <th>32KHz</th>
- *      <th>Reg mode</th>
- *      <th>RAM mode</th>
- *  </tr>
- *  <tr>
- *      <td>Idle 0</td>
- *      <td>Stop</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Normal</td>
- *      <td>Normal</td>
- *  </tr>
- *  <tr>
- *      <td>Idle 1</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Normal</td>
- *      <td>Normal</td>
- *  </tr>
- *  <tr>
- *      <td>Idle 2</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Run</td>
- *      <td>Normal</td>
- *      <td>Normal</td>
- *  </tr>
- *  <tr>
- *      <td>Standby</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Stop</td>
- *      <td>Low Power</td>
- *      <td>Source/Drain biasing</td>
- *  </tr>
- * \endif
- * </table>
- *
- * Before entering device sleep, one of the available sleep modes must be set.
- * The device will automatically wake up in response to an interrupt being
- * generated or upon any other sleep mode exit condition.
- *
- * Some peripheral clocks will remain enabled during sleep, depending on their
- * configuration. If desired, the modules can remain clocked during sleep to allow
- * them continue to operate while other parts of the system are powered down
- * to save power.
- *
- *
- * \section asfdoc_sam0_system_special_considerations Special Considerations
- *
- * Most of the functions in this driver have device specific restrictions and
- * caveats; refer to your device datasheet.
- *
- *
- * \section asfdoc_sam0_system_extra_info Extra Information
- *
- * For extra information, see \ref asfdoc_sam0_system_extra. This includes:
- *  - \ref asfdoc_sam0_system_extra_acronyms
- *  - \ref asfdoc_sam0_system_extra_dependencies
- *  - \ref asfdoc_sam0_system_extra_errata
- *  - \ref asfdoc_sam0_system_extra_history
- *
- *
- * \section asfdoc_sam0_system_examples Examples
- *
- * For SYSTEM module related examples, refer to the sub-modules listed in
- * the \ref asfdoc_sam0_system_module_overview "Module Overview".
- *
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- * For a list of examples related to this driver, see
- * \ref asfdoc_sam0_drivers_power_exqsg.
- * \endif
- *
- *
- * \section asfdoc_sam0_system_api_overview API Overview
- * @{
- */
-
-/**
- * \name System Debugger
- * @{
- */
-
-/**
- * \brief Check if debugger is present.
- *
- * Check if debugger is connected to the onboard debug system (DAP).
- *
- * \return A bool identifying if a debugger is present.
- *
- * \retval true  Debugger is connected to the system
- * \retval false Debugger is not connected to the system
- *
- */
-static inline bool system_is_debugger_present(void)
-{
-	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
-}
-
-/**
- * @}
- */
-
-/**
- * \name System Identification
- * @{
- */
-
-/**
- * \brief Retrieve the device identification signature.
- *
- * Retrieves the signature of the current device.
- *
- * \return Device ID signature as a 32-bit integer.
- */
-static inline uint32_t system_get_device_id(void)
-{
-	return DSU->DID.reg;
-}
-
-/**
- * @}
- */
-
-/**
- * \name System Initialization
- * @{
- */
-
-void system_init(void);
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- *
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- * \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver
- *
- * This is a list of the available Quick Start Guides (QSGs) and example
- * applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to
- * configure and use this driver in a selection of
- * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.
- *
- *  - \subpage asfdoc_sam0_power_basic_use_case
- * \endif
- *
- * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
- *
- * \section asfdoc_sam0_system_extra_acronyms Acronyms
- * Below is a table listing the acronyms used in this module, along with their
- * intended meanings.
- *
- * <table>
- *  <tr>
- *      <th>Acronym</th>
- *      <th>Definition</th>
- *  </tr>
- *  <tr>
- *      <td>PM</td>
- *      <td>Power Manager</td>
- *  </tr>
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>SUPC</td>
- *      <td>Supply Controller</td>
- *  </tr>
- *  <tr>
- *      <td>RSTC</td>
- *      <td>Reset Controller</td>
- *  </tr>
- * \endif
- * \if DEVICE_SAMC21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>SUPC</td>
- *      <td>Supply Controller</td>
- *  </tr>
- *  <tr>
- *      <td>RSTC</td>
- *      <td>Reset Controller</td>
- *  </tr>
- * \endif
- * \if DEVICE_SAMD21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>SYSCTRL</td>
- *      <td>System control interface</td>
- *  </tr>
- * \endif
- * </table>
- *
- *
- * \section asfdoc_sam0_system_extra_dependencies Dependencies
- * This driver has the following dependencies:
- *
- *  - None
- *
- *
- * \section asfdoc_sam0_system_extra_errata Errata
- * There are no errata related to this driver.
- *
- *
- * \section asfdoc_sam0_system_extra_history Module History
- * An overview of the module history is presented in the table below, with
- * details on the enhancements and fixes made to the module since its first
- * release. The current version of this corresponds to the newest version in
- * the table.
- *
- * <table>
- *  <tr>
- *      <th>Changelog</th>
- *  </tr>
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>Initial Release</td>
- *  </tr>
- * \endif
- * \if DEVICE_SAMC21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>Initial Release</td>
- *  </tr>
- * \endif
- * \if DEVICE_SAMD21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
- *  </tr>
- *  <tr>
- *      <td>Added new \c system_get_device_id() function to retrieved the device
- *          ID</td>
- *  </tr>
- *  <tr>
- *      <td>Initial Release</td>
- *  </tr>
- * \endif
- * </table>
- *
- * \page asfdoc_sam0_system_document_revision_history Document Revision History
- *
- * <table>
- * <tr>
- *      <th>Doc. Rev.</th>
- *      <th>Date</th>
- *      <th>Comments</th>
- *  </tr>
- * \if DEVICE_SAML21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>42449A</td>
- *      <td>07/2015</td>
- *      <td>Initial document release</td>
- * </tr>
- * \endif
- * \if DEVICE_SAMC21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>42484A</td>
- *      <td>12/2015</td>
- *      <td>Initial document release.</td>
- * </tr>
- * \endif
- * \if DEVICE_SAMD21_SYSTEM_SUPPORT
- *  <tr>
- *      <td>42120E</td>
- *      <td>12/2015</td>
- *      <td>Added support for SAM DA1 and SAM D09</td>
- * </tr>
- *  <tr>
- *      <td>42120D</td>
- *      <td>12/2014</td>
- *      <td>Added support for SAM R21 and SAM D10/D11</td>
- * </tr>
- * <tr>
- *      <td>42120C</td>
- *      <td>01/2014</td>
- *      <td>Added support for SAM D21</td>
- *  </tr>
- *  <tr>
- *      <td>42120B</td>
- *      <td>06/2013</td>
- *      <td>Corrected documentation typos</td>
- *  </tr>
- *  <tr>
- *      <td>42120A</td>
- *      <td>06/2013</td>
- *      <td>Initial document release</td>
- *  </tr>
- * \endif
- * </table>
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_H_INCLUDED */
-
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <power.h>
+#include <reset.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals.
+ *
+ * The following peripherals are used by this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - SYSCTRL (System Control)
+ *  - PM (Power Manager)
+ * \endif
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM L21
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM C20/C21
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_prerequisites
+ *  - \ref asfdoc_sam0_system_module_overview
+ *  - \ref asfdoc_sam0_system_special_considerations
+ *  - \ref asfdoc_sam0_system_extra_info
+ *  - \ref asfdoc_sam0_system_examples
+ *  - \ref asfdoc_sam0_system_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ * - System Core (this module)
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
+ * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
+ *
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE) and
+ * backup (VDDBU) domains. It sets the voltage regulators according to the sleep
+ * modes, the performance level, or the user configuration.
+ *
+ * In active mode, the voltage regulator can be chosen on the fly between a LDO
+ * or a Buck converter. In standby mode, the low power voltage regulator is used
+ * to supply VDDCORE.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
+ * The SAM device supports connection of a battery backup to the VBAT power pin.
+ * It includes functionality that enables automatic power switching between main
+ * power and battery backup power. This will ensure power to the backup domain,
+ * when the main battery or power source is unavailable.
+ * \endif
+ *
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE). It sets
+ * the voltage regulators according to the sleep modes.
+ *
+ * There are a selectable reference voltage and voltage dependent on the temperature
+ * which can be used by analog modules like the ADC.
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
+ * The various analog modules within the SAM devices (such as AC, ADC, and
+ * DAC) require a voltage reference to be configured to act as a reference point
+ * for comparisons and conversions.
+ *
+ * The SAM devices contain multiple references, including an internal
+ * temperature sensor and a fixed band-gap voltage source. When enabled, the
+ * associated voltage reference can be selected within the desired peripheral
+ * where applicable.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
+ * In some applications there may be a need to execute a different program
+ * flow based on how the device was reset. For example, if the cause of reset
+ * was the Watchdog timer (WDT), this might indicate an error in the application,
+ * and a form of error handling or error logging might be needed.
+ *
+ * For this reason, an API is provided to retrieve the cause of the last system
+ * reset, so that appropriate action can be taken.
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * There are three groups of reset sources:
+ *   - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset.
+ *   - User reset: Resets caused by the application. It covers external reset,
+ *             system reset, and watchdog reset.
+ *   - Backup reset: Resets caused by a backup mode exit condition.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
+ * Performance level allows the user to adjust the regulator output voltage to reduce
+ * power consumption. The user can on the fly select the most suitable performance
+ * level, depending on the application demands.
+ *
+ * The SAM device can operate at two different performance levels (PL0 and PL2).
+ * When operating at PL0, the voltage applied on the full logic area is reduced
+ * by voltage scaling. This voltage scaling technique allows to reduce the active
+ * power consumption while decreasing the maximum frequency of the device. When
+ * operating at PL2, the voltage regulator supplies the highest voltage, allowing
+ * the device to run at higher clock speeds.
+ *
+ * Performance level transition is possible only when the device is in active
+ * mode. After a reset, the device starts at the lowest performance level
+ * (lowest power consumption and lowest max. frequency). The application can then
+ * switch to another performance level at any time without any stop in the code
+ * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
+ *
+ * \note When scaling down the performance level, the bus frequency should first be
+ *  scaled down in order to not exceed the maximum frequency allowed for the
+ *  low performance level.
+ *  When scaling up the performance level (e.g. from PL0 to PL2), check the performance
+ *  level status before increasing the bus frequency. It can be increased only
+ *  when the performance level transition is completed.
+ *
+ * \anchor asfdoc_sam0_system_performance_level_transition_figure
+ * \image html performance_level_transition.svg "Performance Level Transition"
+ *
+ * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
+ * Power domain gating allows power saving by reducing the voltage in logic
+ * areas in the device to a low-power supply. The feature is available in
+ * Standby sleep mode and will reduce the voltage in domains where all peripherals
+ * are idle. Internal logic will maintain its content, meaning the corresponding
+ * peripherals will not need to be reconfigured when normal operating voltage
+ * is returned. Most power domains can be in the following three states:
+ *
+ * - Active state: The power domain is powered on.
+ * - Retention state: The main voltage supply for the power domain is switched off,
+ * while maintaining a secondary low-power supply for the sequential cells. The
+ * logic context is restored when waking up.
+ * - Off state: The power domain is entirely powered off. The logic context is lost.
+ *
+ * The SAM L21 device  contains three power domains which can be controlled using
+ * power domain gating, namely PD0, PD1, and PD2. These power domains can be
+ * configured to the following cases:
+ * - Default with no sleepwalking peripherals: A power domain is automatically set
+ * to retention state in standby sleep mode if no activity require it. The application
+ * can force all power domains to remain in active state during standby sleep mode
+ * in order to accelerate wakeup time.
+ * - Default with sleepwalking peripherals: If one or more peripherals are enabled
+ * to perform sleepwalking tasks in standby sleep mode, the corresponding power
+ * domain (PDn) remains in active state as well as all inferior power domains (<PDn).
+ * - Sleepwalking with dynamic power domain gating: During standby sleep mode, a
+ * power domain (PDn) in active can wake up a superior power domain (>PDn) in order
+ * to perform a sleepwalking task. The superior power domain is then automatically
+ * set to active state. At the end of the sleepwalking task, the device can either
+ * be woken up or the superior power domain can return to retention state.
+ *
+ * Power domains can be linked to each other, it allows a power domain (PDn) to be kept
+ * in active state if the inferior power domain (PDn-1) is in active state too.
+ *
+ * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
+ * four cases to consider in standby mode.
+ *
+ * \anchor asfdoc_sam0_system_power_domain_overview_table
+ * <table>
+ *  <caption>Sleep Mode versus Power Domain State Overview</caption>
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>PD0</th>
+ *      <th>PD1</th>
+ *      <th>PD2</th>
+ *      <th>PDTOP</th>
+ *      <th>PDBACKUP</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 1</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 2</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 3</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 4</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
+ * By default, in standby sleep mode, RAM is in low power mode (back biased)
+ * if its power domain is in retention state.
+ * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
+ *
+ * \anchor asfdoc_sam0_system_power_ram_state_table
+ * <table>
+ *  <caption>RAM Back-biasing Mode</caption>
+ *  <tr>
+ *      <th>RAM mode</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Retention Back-biasing mode</td>
+ *      <td>RAM is back-biased if its power domain is in retention mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby Back-biasing mode</td>
+ *      <td>RAM is back-biased if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby OFF mode</td>
+ *      <td>RAM is OFF if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Always OFF mode</td>
+ *      <td>RAM is OFF if the device is in RET mode</td>
+ *  </tr>
+ * </table>
+ *
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
+ * The SAM devices have several sleep modes. The sleep mode controls
+ * which clock systems on the device will remain enabled or disabled when the
+ * device enters a low power sleep mode.
+ * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
+ * clock settings of the different sleep modes.
+ *
+ * \anchor asfdoc_sam0_system_module_sleep_mode_table
+ * <table>
+ *  <caption>SAM Device Sleep Modes</caption>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>System clock</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB/AHB clock</th>
+ *      <th>GCLK clocks</th>
+ *      <th>Oscillators (ONDEMAND  = 0)</th>
+ *      <th>Oscillators (ONDEMAND  = 1)</th>
+ *      <th>Regulator mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>Run</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run if requested</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested or RUNSTDBY  = 1</td>
+ *      <td>Run if requested</td>
+ *      <td>Low pwer</td>
+ *      <td>Low pwer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Backup</td>
+ *      <td>Off</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *  </tr>
+ * \else
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB clock</th>
+ *      <th>APB clocks</th>
+ *      <th>Clock sources</th>
+ *      <th>System clock</th>
+ *      <th>32KHz</th>
+ *      <th>Reg mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 0</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 1</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 2</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Low Power</td>
+ *      <td>Source/Drain biasing</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * Before entering device sleep, one of the available sleep modes must be set.
+ * The device will automatically wake up in response to an interrupt being
+ * generated or upon any other sleep mode exit condition.
+ *
+ * Some peripheral clocks will remain enabled during sleep, depending on their
+ * configuration. If desired, the modules can remain clocked during sleep to allow
+ * them continue to operate while other parts of the system are powered down
+ * to save power.
+ *
+ *
+ * \section asfdoc_sam0_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_extra. This includes:
+ *  - \ref asfdoc_sam0_system_extra_acronyms
+ *  - \ref asfdoc_sam0_system_extra_dependencies
+ *  - \ref asfdoc_sam0_system_extra_errata
+ *  - \ref asfdoc_sam0_system_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_examples Examples
+ *
+ * For SYSTEM module related examples, refer to the sub-modules listed in
+ * the \ref asfdoc_sam0_system_module_overview "Module Overview".
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_power_exqsg.
+ * \endif
+ *
+ *
+ * \section asfdoc_sam0_system_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name System Debugger
+ * @{
+ */
+
+/**
+ * \brief Check if debugger is present.
+ *
+ * Check if debugger is connected to the onboard debug system (DAP).
+ *
+ * \return A bool identifying if a debugger is present.
+ *
+ * \retval true  Debugger is connected to the system
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Identification
+ * @{
+ */
+
+/**
+ * \brief Retrieve the device identification signature.
+ *
+ * Retrieves the signature of the current device.
+ *
+ * \return Device ID signature as a 32-bit integer.
+ */
+static inline uint32_t system_get_device_id(void)
+{
+	return DSU->DID.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Initialization
+ * @{
+ */
+
+void system_init(void);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to
+ * configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_power_basic_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_sam0_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>PM</td>
+ *      <td>Power Manager</td>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>System control interface</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new \c system_get_device_id() function to retrieved the device
+ *          ID</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * \page asfdoc_sam0_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42449A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42484A</td>
+ *      <td>12/2015</td>
+ *      <td>Initial document release.</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42120E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1 and SAM D09</td>
+ * </tr>
+ *  <tr>
+ *      <td>42120D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ * </tr>
+ * <tr>
+ *      <td>42120C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_H_INCLUDED */
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h
index 0697186..0237344 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h
@@ -1,549 +1,549 @@
-/**
- * \file
- *
- * \brief Component description for AC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_AC_COMPONENT_
-#define _SAMD21_AC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR AC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_AC Analog Comparators */
-/*@{*/
-
-#define AC_U2205
-#define REV_AC                      0x112
-
-/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  LPMUX:1;          /*!< bit:      7  Low-Power Mux                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
-#define AC_CTRLA_RESETVALUE         0x00ul       /**< \brief (AC_CTRLA reset_value) Control A */
-
-#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
-#define AC_CTRLA_SWRST              (0x1ul << AC_CTRLA_SWRST_Pos)
-#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
-#define AC_CTRLA_ENABLE             (0x1ul << AC_CTRLA_ENABLE_Pos)
-#define AC_CTRLA_RUNSTDBY_Pos       2            /**< \brief (AC_CTRLA) Run in Standby */
-#define AC_CTRLA_RUNSTDBY_Msk       (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
-#define AC_CTRLA_RUNSTDBY(value)    (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
-#define AC_CTRLA_LPMUX_Pos          7            /**< \brief (AC_CTRLA) Low-Power Mux */
-#define AC_CTRLA_LPMUX              (0x1ul << AC_CTRLA_LPMUX_Pos)
-#define AC_CTRLA_MASK               0x87ul       /**< \brief (AC_CTRLA) MASK Register */
-
-/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
-    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
-#define AC_CTRLB_RESETVALUE         0x00ul       /**< \brief (AC_CTRLB reset_value) Control B */
-
-#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
-#define AC_CTRLB_START0             (1 << AC_CTRLB_START0_Pos)
-#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
-#define AC_CTRLB_START1             (1 << AC_CTRLB_START1_Pos)
-#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
-#define AC_CTRLB_START_Msk          (0x3ul << AC_CTRLB_START_Pos)
-#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
-#define AC_CTRLB_MASK               0x03ul       /**< \brief (AC_CTRLB) MASK Register */
-
-/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
-    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input           */
-    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input           */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input           */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} AC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
-#define AC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (AC_EVCTRL reset_value) Event Control */
-
-#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
-#define AC_EVCTRL_COMPEO0           (1 << AC_EVCTRL_COMPEO0_Pos)
-#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
-#define AC_EVCTRL_COMPEO1           (1 << AC_EVCTRL_COMPEO1_Pos)
-#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
-#define AC_EVCTRL_COMPEO_Msk        (0x3ul << AC_EVCTRL_COMPEO_Pos)
-#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
-#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
-#define AC_EVCTRL_WINEO0            (1 << AC_EVCTRL_WINEO0_Pos)
-#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
-#define AC_EVCTRL_WINEO_Msk         (0x1ul << AC_EVCTRL_WINEO_Pos)
-#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
-#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
-#define AC_EVCTRL_COMPEI0           (1 << AC_EVCTRL_COMPEI0_Pos)
-#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
-#define AC_EVCTRL_COMPEI1           (1 << AC_EVCTRL_COMPEI1_Pos)
-#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input */
-#define AC_EVCTRL_COMPEI_Msk        (0x3ul << AC_EVCTRL_COMPEI_Pos)
-#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
-#define AC_EVCTRL_MASK              0x0313ul     /**< \brief (AC_EVCTRL) MASK Register */
-
-/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
-    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
-#define AC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
-#define AC_INTENCLR_COMP0           (1 << AC_INTENCLR_COMP0_Pos)
-#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
-#define AC_INTENCLR_COMP1           (1 << AC_INTENCLR_COMP1_Pos)
-#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
-#define AC_INTENCLR_COMP_Msk        (0x3ul << AC_INTENCLR_COMP_Pos)
-#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
-#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
-#define AC_INTENCLR_WIN0            (1 << AC_INTENCLR_WIN0_Pos)
-#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
-#define AC_INTENCLR_WIN_Msk         (0x1ul << AC_INTENCLR_WIN_Pos)
-#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
-#define AC_INTENCLR_MASK            0x13ul       /**< \brief (AC_INTENCLR) MASK Register */
-
-/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
-    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
-#define AC_INTENSET_RESETVALUE      0x00ul       /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
-
-#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
-#define AC_INTENSET_COMP0           (1 << AC_INTENSET_COMP0_Pos)
-#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
-#define AC_INTENSET_COMP1           (1 << AC_INTENSET_COMP1_Pos)
-#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
-#define AC_INTENSET_COMP_Msk        (0x3ul << AC_INTENSET_COMP_Pos)
-#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
-#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
-#define AC_INTENSET_WIN0            (1 << AC_INTENSET_WIN0_Pos)
-#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
-#define AC_INTENSET_WIN_Msk         (0x1ul << AC_INTENSET_WIN_Pos)
-#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
-#define AC_INTENSET_MASK            0x13ul       /**< \brief (AC_INTENSET) MASK Register */
-
-/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
-    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
-    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
-    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
-    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
-    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define AC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
-#define AC_INTFLAG_COMP0            (1 << AC_INTFLAG_COMP0_Pos)
-#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
-#define AC_INTFLAG_COMP1            (1 << AC_INTFLAG_COMP1_Pos)
-#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
-#define AC_INTFLAG_COMP_Msk         (0x3ul << AC_INTFLAG_COMP_Pos)
-#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
-#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
-#define AC_INTFLAG_WIN0             (1 << AC_INTFLAG_WIN0_Pos)
-#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
-#define AC_INTFLAG_WIN_Msk          (0x1ul << AC_INTFLAG_WIN_Pos)
-#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
-#define AC_INTFLAG_MASK             0x13ul       /**< \brief (AC_INTFLAG) MASK Register */
-
-/* -------- AC_STATUSA : (AC Offset: 0x08) (R/   8) Status A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
-    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSA_OFFSET           0x08         /**< \brief (AC_STATUSA offset) Status A */
-#define AC_STATUSA_RESETVALUE       0x00ul       /**< \brief (AC_STATUSA reset_value) Status A */
-
-#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
-#define AC_STATUSA_STATE0           (1 << AC_STATUSA_STATE0_Pos)
-#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
-#define AC_STATUSA_STATE1           (1 << AC_STATUSA_STATE1_Pos)
-#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
-#define AC_STATUSA_STATE_Msk        (0x3ul << AC_STATUSA_STATE_Pos)
-#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
-#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
-#define AC_STATUSA_WSTATE0_Msk      (0x3ul << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
-#define   AC_STATUSA_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSA) Signal is above window */
-#define   AC_STATUSA_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSA) Signal is inside window */
-#define   AC_STATUSA_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSA) Signal is below window */
-#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_MASK             0x33ul       /**< \brief (AC_STATUSA) MASK Register */
-
-/* -------- AC_STATUSB : (AC Offset: 0x09) (R/   8) Status B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
-    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
-    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSB_OFFSET           0x09         /**< \brief (AC_STATUSB offset) Status B */
-#define AC_STATUSB_RESETVALUE       0x00ul       /**< \brief (AC_STATUSB reset_value) Status B */
-
-#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
-#define AC_STATUSB_READY0           (1 << AC_STATUSB_READY0_Pos)
-#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
-#define AC_STATUSB_READY1           (1 << AC_STATUSB_READY1_Pos)
-#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
-#define AC_STATUSB_READY_Msk        (0x3ul << AC_STATUSB_READY_Pos)
-#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
-#define AC_STATUSB_SYNCBUSY_Pos     7            /**< \brief (AC_STATUSB) Synchronization Busy */
-#define AC_STATUSB_SYNCBUSY         (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
-#define AC_STATUSB_MASK             0x83ul       /**< \brief (AC_STATUSB) MASK Register */
-
-/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/   8) Status C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
-    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_STATUSC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSC_OFFSET           0x0A         /**< \brief (AC_STATUSC offset) Status C */
-#define AC_STATUSC_RESETVALUE       0x00ul       /**< \brief (AC_STATUSC reset_value) Status C */
-
-#define AC_STATUSC_STATE0_Pos       0            /**< \brief (AC_STATUSC) Comparator 0 Current State */
-#define AC_STATUSC_STATE0           (1 << AC_STATUSC_STATE0_Pos)
-#define AC_STATUSC_STATE1_Pos       1            /**< \brief (AC_STATUSC) Comparator 1 Current State */
-#define AC_STATUSC_STATE1           (1 << AC_STATUSC_STATE1_Pos)
-#define AC_STATUSC_STATE_Pos        0            /**< \brief (AC_STATUSC) Comparator x Current State */
-#define AC_STATUSC_STATE_Msk        (0x3ul << AC_STATUSC_STATE_Pos)
-#define AC_STATUSC_STATE(value)     (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
-#define AC_STATUSC_WSTATE0_Pos      4            /**< \brief (AC_STATUSC) Window 0 Current State */
-#define AC_STATUSC_WSTATE0_Msk      (0x3ul << AC_STATUSC_WSTATE0_Pos)
-#define AC_STATUSC_WSTATE0(value)   (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
-#define   AC_STATUSC_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSC) Signal is above window */
-#define   AC_STATUSC_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSC) Signal is inside window */
-#define   AC_STATUSC_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSC) Signal is below window */
-#define AC_STATUSC_WSTATE0_ABOVE    (AC_STATUSC_WSTATE0_ABOVE_Val  << AC_STATUSC_WSTATE0_Pos)
-#define AC_STATUSC_WSTATE0_INSIDE   (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
-#define AC_STATUSC_WSTATE0_BELOW    (AC_STATUSC_WSTATE0_BELOW_Val  << AC_STATUSC_WSTATE0_Pos)
-#define AC_STATUSC_MASK             0x33ul       /**< \brief (AC_STATUSC) MASK Register */
-
-/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W  8) Window Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
-    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_WINCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_WINCTRL_OFFSET           0x0C         /**< \brief (AC_WINCTRL offset) Window Control */
-#define AC_WINCTRL_RESETVALUE       0x00ul       /**< \brief (AC_WINCTRL reset_value) Window Control */
-
-#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
-#define AC_WINCTRL_WEN0             (0x1ul << AC_WINCTRL_WEN0_Pos)
-#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
-#define AC_WINCTRL_WINTSEL0_Msk     (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
-#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   0x0ul  /**< \brief (AC_WINCTRL) Interrupt on signal above window */
-#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  0x1ul  /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
-#define   AC_WINCTRL_WINTSEL0_BELOW_Val   0x2ul  /**< \brief (AC_WINCTRL) Interrupt on signal below window */
-#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul  /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
-#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_MASK             0x07ul       /**< \brief (AC_WINCTRL) MASK Register */
-
-/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ENABLE:1;         /*!< bit:      0  Enable                             */
-    uint32_t SINGLE:1;         /*!< bit:      1  Single-Shot Mode                   */
-    uint32_t SPEED:2;          /*!< bit:  2.. 3  Speed Selection                    */
-    uint32_t :1;               /*!< bit:      4  Reserved                           */
-    uint32_t INTSEL:2;         /*!< bit:  5.. 6  Interrupt Selection                */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t MUXPOS:2;         /*!< bit: 12..13  Positive Input Mux Selection       */
-    uint32_t :1;               /*!< bit:     14  Reserved                           */
-    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
-    uint32_t OUT:2;            /*!< bit: 16..17  Output                             */
-    uint32_t :1;               /*!< bit:     18  Reserved                           */
-    uint32_t HYST:1;           /*!< bit:     19  Hysteresis Enable                  */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} AC_COMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
-#define AC_COMPCTRL_RESETVALUE      0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
-
-#define AC_COMPCTRL_ENABLE_Pos      0            /**< \brief (AC_COMPCTRL) Enable */
-#define AC_COMPCTRL_ENABLE          (0x1ul << AC_COMPCTRL_ENABLE_Pos)
-#define AC_COMPCTRL_SINGLE_Pos      1            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
-#define AC_COMPCTRL_SINGLE          (0x1ul << AC_COMPCTRL_SINGLE_Pos)
-#define AC_COMPCTRL_SPEED_Pos       2            /**< \brief (AC_COMPCTRL) Speed Selection */
-#define AC_COMPCTRL_SPEED_Msk       (0x3ul << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
-#define   AC_COMPCTRL_SPEED_LOW_Val       0x0ul  /**< \brief (AC_COMPCTRL) Low speed */
-#define   AC_COMPCTRL_SPEED_HIGH_Val      0x1ul  /**< \brief (AC_COMPCTRL) High speed */
-#define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_INTSEL_Pos      5            /**< \brief (AC_COMPCTRL) Interrupt Selection */
-#define AC_COMPCTRL_INTSEL_Msk      (0x3ul << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
-#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   0x0ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
-#define   AC_COMPCTRL_INTSEL_RISING_Val   0x1ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
-#define   AC_COMPCTRL_INTSEL_FALLING_Val  0x2ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
-#define   AC_COMPCTRL_INTSEL_EOC_Val      0x3ul  /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
-#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
-#define AC_COMPCTRL_MUXNEG_Msk      (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
-#define   AC_COMPCTRL_MUXNEG_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define   AC_COMPCTRL_MUXNEG_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define   AC_COMPCTRL_MUXNEG_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define   AC_COMPCTRL_MUXNEG_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define   AC_COMPCTRL_MUXNEG_GND_Val      0x4ul  /**< \brief (AC_COMPCTRL) Ground */
-#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   0x5ul  /**< \brief (AC_COMPCTRL) VDD scaler */
-#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  0x6ul  /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
-#define   AC_COMPCTRL_MUXNEG_DAC_Val      0x7ul  /**< \brief (AC_COMPCTRL) DAC output */
-#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
-#define AC_COMPCTRL_MUXPOS_Msk      (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
-#define   AC_COMPCTRL_MUXPOS_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define   AC_COMPCTRL_MUXPOS_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define   AC_COMPCTRL_MUXPOS_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define   AC_COMPCTRL_MUXPOS_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
-#define AC_COMPCTRL_SWAP            (0x1ul << AC_COMPCTRL_SWAP_Pos)
-#define AC_COMPCTRL_OUT_Pos         16           /**< \brief (AC_COMPCTRL) Output */
-#define AC_COMPCTRL_OUT_Msk         (0x3ul << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
-#define   AC_COMPCTRL_OUT_OFF_Val         0x0ul  /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
-#define   AC_COMPCTRL_OUT_ASYNC_Val       0x1ul  /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
-#define   AC_COMPCTRL_OUT_SYNC_Val        0x2ul  /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_HYST_Pos        19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
-#define AC_COMPCTRL_HYST            (0x1ul << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
-#define AC_COMPCTRL_FLEN_Msk        (0x7ul << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
-#define   AC_COMPCTRL_FLEN_OFF_Val        0x0ul  /**< \brief (AC_COMPCTRL) No filtering */
-#define   AC_COMPCTRL_FLEN_MAJ3_Val       0x1ul  /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
-#define   AC_COMPCTRL_FLEN_MAJ5_Val       0x2ul  /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
-#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_MASK            0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
-
-/* -------- AC_SCALER : (AC Offset: 0x20) (R/W  8) Scaler n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_SCALER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SCALER_OFFSET            0x20         /**< \brief (AC_SCALER offset) Scaler n */
-#define AC_SCALER_RESETVALUE        0x00ul       /**< \brief (AC_SCALER reset_value) Scaler n */
-
-#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
-#define AC_SCALER_VALUE_Msk         (0x3Ful << AC_SCALER_VALUE_Pos)
-#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
-#define AC_SCALER_MASK              0x3Ful       /**< \brief (AC_SCALER) MASK Register */
-
-/** \brief AC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
-  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
-  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
-  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
-  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved1[0x1];
-  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x08 (R/   8) Status A */
-  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x09 (R/   8) Status B */
-  __I  AC_STATUSC_Type           STATUSC;     /**< \brief Offset: 0x0A (R/   8) Status C */
-       RoReg8                    Reserved2[0x1];
-  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0C (R/W  8) Window Control */
-       RoReg8                    Reserved3[0x3];
-  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
-       RoReg8                    Reserved4[0x8];
-  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x20 (R/W  8) Scaler n */
-} Ac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_AC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC                      0x112
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  LPMUX:1;          /*!< bit:      7  Low-Power Mux                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE         0x00ul       /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST              (0x1ul << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE             (0x1ul << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos       2            /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk       (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value)    (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
+#define AC_CTRLA_LPMUX_Pos          7            /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX              (0x1ul << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK               0x87ul       /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
+    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE         0x00ul       /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0             (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1             (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk          (0x3ul << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK               0x03ul       /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
+    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input           */
+    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0           (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1           (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk        (0x3ul << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0            (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk         (0x1ul << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0           (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1           (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk        (0x3ul << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_MASK              0x0313ul     /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0           (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1           (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk        (0x3ul << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0            (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk         (0x1ul << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK            0x13ul       /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      0x00ul       /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0           (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1           (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk        (0x3ul << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0            (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk         (0x1ul << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK            0x13ul       /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
+    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0            (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1            (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk         (0x3ul << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0             (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk          (0x1ul << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK             0x13ul       /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/   8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET           0x08         /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE       0x00ul       /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0           (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1           (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk        (0x3ul << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk      (0x3ul << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK             0x33ul       /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
+    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET           0x09         /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE       0x00ul       /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0           (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1           (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk        (0x3ul << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_SYNCBUSY_Pos     7            /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY         (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK             0x83ul       /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/   8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET           0x0A         /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE       0x00ul       /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos       0            /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0           (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos       1            /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1           (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos        0            /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk        (0x3ul << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value)     (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
+#define AC_STATUSC_WSTATE0_Pos      4            /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk      (0x3ul << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value)   (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
+#define   AC_STATUSC_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSC) Signal is above window */
+#define   AC_STATUSC_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSC) Signal is inside window */
+#define   AC_STATUSC_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE    (AC_STATUSC_WSTATE0_ABOVE_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE   (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW    (AC_STATUSC_WSTATE0_BELOW_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK             0x33ul       /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W  8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
+    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET           0x0C         /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE       0x00ul       /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0             (0x1ul << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk     (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   0x0ul  /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  0x1ul  /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   0x2ul  /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul  /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK             0x07ul       /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  Enable                             */
+    uint32_t SINGLE:1;         /*!< bit:      1  Single-Shot Mode                   */
+    uint32_t SPEED:2;          /*!< bit:  2.. 3  Speed Selection                    */
+    uint32_t :1;               /*!< bit:      4  Reserved                           */
+    uint32_t INTSEL:2;         /*!< bit:  5.. 6  Interrupt Selection                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t MUXPOS:2;         /*!< bit: 12..13  Positive Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     14  Reserved                           */
+    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
+    uint32_t OUT:2;            /*!< bit: 16..17  Output                             */
+    uint32_t :1;               /*!< bit:     18  Reserved                           */
+    uint32_t HYST:1;           /*!< bit:     19  Hysteresis Enable                  */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos      0            /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE          (0x1ul << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos      1            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE          (0x1ul << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos       2            /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk       (0x3ul << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define   AC_COMPCTRL_SPEED_LOW_Val       0x0ul  /**< \brief (AC_COMPCTRL) Low speed */
+#define   AC_COMPCTRL_SPEED_HIGH_Val      0x1ul  /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos      5            /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk      (0x3ul << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   0x0ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   0x1ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  0x2ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      0x3ul  /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk      (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      0x4ul  /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   0x5ul  /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  0x6ul  /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      0x7ul  /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk      (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP            (0x1ul << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos         16           /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk         (0x3ul << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define   AC_COMPCTRL_OUT_OFF_Val         0x0ul  /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       0x1ul  /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        0x2ul  /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos        19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST            (0x1ul << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk        (0x7ul << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define   AC_COMPCTRL_FLEN_OFF_Val        0x0ul  /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       0x1ul  /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       0x2ul  /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK            0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W  8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET            0x20         /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE        0x00ul       /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk         (0x3Ful << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK              0x3Ful       /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
+  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
+  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x08 (R/   8) Status A */
+  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x09 (R/   8) Status B */
+  __I  AC_STATUSC_Type           STATUSC;     /**< \brief Offset: 0x0A (R/   8) Status C */
+       RoReg8                    Reserved2[0x1];
+  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0C (R/W  8) Window Control */
+       RoReg8                    Reserved3[0x3];
+  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+       RoReg8                    Reserved4[0x8];
+  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x20 (R/W  8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h
index bbfcdfc..5243219 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h
@@ -1,689 +1,689 @@
-/**
- * \file
- *
- * \brief Component description for ADC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_ADC_COMPONENT_
-#define _SAMD21_ADC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR ADC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_ADC Analog Digital Converter */
-/*@{*/
-
-#define ADC_U2204
-#define REV_ADC                     0x120
-
-/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
-#define ADC_CTRLA_RESETVALUE        0x00ul       /**< \brief (ADC_CTRLA reset_value) Control A */
-
-#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
-#define ADC_CTRLA_SWRST             (0x1ul << ADC_CTRLA_SWRST_Pos)
-#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
-#define ADC_CTRLA_ENABLE            (0x1ul << ADC_CTRLA_ENABLE_Pos)
-#define ADC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (ADC_CTRLA) Run in Standby */
-#define ADC_CTRLA_RUNSTDBY          (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
-#define ADC_CTRLA_MASK              0x07ul       /**< \brief (ADC_CTRLA) MASK Register */
-
-/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W  8) Reference Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_REFCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_REFCTRL_OFFSET          0x01         /**< \brief (ADC_REFCTRL offset) Reference Control */
-#define ADC_REFCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_REFCTRL reset_value) Reference Control */
-
-#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
-#define ADC_REFCTRL_REFSEL_Msk      (0xFul << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
-#define   ADC_REFCTRL_REFSEL_INT1V_Val    0x0ul  /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
-#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  0x1ul  /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
-#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  0x2ul  /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
-#define   ADC_REFCTRL_REFSEL_AREFA_Val    0x3ul  /**< \brief (ADC_REFCTRL) External reference */
-#define   ADC_REFCTRL_REFSEL_AREFB_Val    0x4ul  /**< \brief (ADC_REFCTRL) External reference */
-#define ADC_REFCTRL_REFSEL_INT1V    (ADC_REFCTRL_REFSEL_INT1V_Val  << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
-#define ADC_REFCTRL_REFCOMP         (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
-#define ADC_REFCTRL_MASK            0x8Ful       /**< \brief (ADC_REFCTRL) MASK Register */
-
-/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W  8) Average Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
-    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_AVGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_AVGCTRL_OFFSET          0x02         /**< \brief (ADC_AVGCTRL offset) Average Control */
-#define ADC_AVGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_AVGCTRL reset_value) Average Control */
-
-#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
-#define ADC_AVGCTRL_SAMPLENUM_Msk   (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
-#define   ADC_AVGCTRL_SAMPLENUM_1_Val     0x0ul  /**< \brief (ADC_AVGCTRL) 1 sample */
-#define   ADC_AVGCTRL_SAMPLENUM_2_Val     0x1ul  /**< \brief (ADC_AVGCTRL) 2 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_4_Val     0x2ul  /**< \brief (ADC_AVGCTRL) 4 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_8_Val     0x3ul  /**< \brief (ADC_AVGCTRL) 8 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_16_Val    0x4ul  /**< \brief (ADC_AVGCTRL) 16 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_32_Val    0x5ul  /**< \brief (ADC_AVGCTRL) 32 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_64_Val    0x6ul  /**< \brief (ADC_AVGCTRL) 64 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_128_Val   0x7ul  /**< \brief (ADC_AVGCTRL) 128 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_256_Val   0x8ul  /**< \brief (ADC_AVGCTRL) 256 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_512_Val   0x9ul  /**< \brief (ADC_AVGCTRL) 512 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  0xAul  /**< \brief (ADC_AVGCTRL) 1024 samples */
-#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
-#define ADC_AVGCTRL_ADJRES_Msk      (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
-#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
-#define ADC_AVGCTRL_MASK            0x7Ful       /**< \brief (ADC_AVGCTRL) MASK Register */
-
-/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W  8) Sampling Time Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_SAMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SAMPCTRL_OFFSET         0x03         /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
-#define ADC_SAMPCTRL_RESETVALUE     0x00ul       /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
-
-#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
-#define ADC_SAMPCTRL_SAMPLEN_Msk    (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
-#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
-#define ADC_SAMPCTRL_MASK           0x3Ful       /**< \brief (ADC_SAMPCTRL) MASK Register */
-
-/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DIFFMODE:1;       /*!< bit:      0  Differential Mode                  */
-    uint16_t LEFTADJ:1;        /*!< bit:      1  Left-Adjusted Result               */
-    uint16_t FREERUN:1;        /*!< bit:      2  Free Running Mode                  */
-    uint16_t CORREN:1;         /*!< bit:      3  Digital Correction Logic Enabled   */
-    uint16_t RESSEL:2;         /*!< bit:  4.. 5  Conversion Result Resolution       */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLB_OFFSET            0x04         /**< \brief (ADC_CTRLB offset) Control B */
-#define ADC_CTRLB_RESETVALUE        0x0000ul     /**< \brief (ADC_CTRLB reset_value) Control B */
-
-#define ADC_CTRLB_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLB) Differential Mode */
-#define ADC_CTRLB_DIFFMODE          (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
-#define ADC_CTRLB_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
-#define ADC_CTRLB_LEFTADJ           (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
-#define ADC_CTRLB_FREERUN_Pos       2            /**< \brief (ADC_CTRLB) Free Running Mode */
-#define ADC_CTRLB_FREERUN           (0x1ul << ADC_CTRLB_FREERUN_Pos)
-#define ADC_CTRLB_CORREN_Pos        3            /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
-#define ADC_CTRLB_CORREN            (0x1ul << ADC_CTRLB_CORREN_Pos)
-#define ADC_CTRLB_RESSEL_Pos        4            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
-#define ADC_CTRLB_RESSEL_Msk        (0x3ul << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
-#define   ADC_CTRLB_RESSEL_12BIT_Val      0x0ul  /**< \brief (ADC_CTRLB) 12-bit result */
-#define   ADC_CTRLB_RESSEL_16BIT_Val      0x1ul  /**< \brief (ADC_CTRLB) For averaging mode output */
-#define   ADC_CTRLB_RESSEL_10BIT_Val      0x2ul  /**< \brief (ADC_CTRLB) 10-bit result */
-#define   ADC_CTRLB_RESSEL_8BIT_Val       0x3ul  /**< \brief (ADC_CTRLB) 8-bit result */
-#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_PRESCALER_Pos     8            /**< \brief (ADC_CTRLB) Prescaler Configuration */
-#define ADC_CTRLB_PRESCALER_Msk     (0x7ul << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER(value)  (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
-#define   ADC_CTRLB_PRESCALER_DIV4_Val    0x0ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
-#define   ADC_CTRLB_PRESCALER_DIV8_Val    0x1ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
-#define   ADC_CTRLB_PRESCALER_DIV16_Val   0x2ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
-#define   ADC_CTRLB_PRESCALER_DIV32_Val   0x3ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
-#define   ADC_CTRLB_PRESCALER_DIV64_Val   0x4ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
-#define   ADC_CTRLB_PRESCALER_DIV128_Val  0x5ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
-#define   ADC_CTRLB_PRESCALER_DIV256_Val  0x6ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
-#define   ADC_CTRLB_PRESCALER_DIV512_Val  0x7ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
-#define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV32   (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV64   (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_PRESCALER_DIV512  (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_MASK              0x073Ful     /**< \brief (ADC_CTRLB) MASK Register */
-
-/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W  8) Window Monitor Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WINMODE:3;        /*!< bit:  0.. 2  Window Monitor Mode                */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_WINCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINCTRL_OFFSET          0x08         /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
-#define ADC_WINCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
-
-#define ADC_WINCTRL_WINMODE_Pos     0            /**< \brief (ADC_WINCTRL) Window Monitor Mode */
-#define ADC_WINCTRL_WINMODE_Msk     (0x7ul << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_WINMODE(value)  (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
-#define   ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul  /**< \brief (ADC_WINCTRL) No window mode (default) */
-#define   ADC_WINCTRL_WINMODE_MODE1_Val   0x1ul  /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
-#define   ADC_WINCTRL_WINMODE_MODE2_Val   0x2ul  /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
-#define   ADC_WINCTRL_WINMODE_MODE3_Val   0x3ul  /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
-#define   ADC_WINCTRL_WINMODE_MODE4_Val   0x4ul  /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
-#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_WINMODE_MODE1   (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_WINMODE_MODE2   (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_WINMODE_MODE3   (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_WINMODE_MODE4   (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_MASK            0x07ul       /**< \brief (ADC_WINCTRL) MASK Register */
-
-/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W  8) Software Trigger -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
-    uint8_t  START:1;          /*!< bit:      1  ADC Start Conversion               */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_SWTRIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SWTRIG_OFFSET           0x0C         /**< \brief (ADC_SWTRIG offset) Software Trigger */
-#define ADC_SWTRIG_RESETVALUE       0x00ul       /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
-
-#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
-#define ADC_SWTRIG_FLUSH            (0x1ul << ADC_SWTRIG_FLUSH_Pos)
-#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
-#define ADC_SWTRIG_START            (0x1ul << ADC_SWTRIG_START_Pos)
-#define ADC_SWTRIG_MASK             0x03ul       /**< \brief (ADC_SWTRIG) MASK Register */
-
-/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
-    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint32_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t INPUTSCAN:4;      /*!< bit: 16..19  Number of Input Channels Included in Scan */
-    uint32_t INPUTOFFSET:4;    /*!< bit: 20..23  Positive Mux Setting Offset        */
-    uint32_t GAIN:4;           /*!< bit: 24..27  Gain Factor Selection              */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ADC_INPUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_INPUTCTRL offset) Input Control */
-#define ADC_INPUTCTRL_RESETVALUE    0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
-
-#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
-#define ADC_INPUTCTRL_MUXPOS_Msk    (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
-#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   0x8ul  /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   0x9ul  /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  0xAul  /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  0xBul  /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  0xCul  /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  0xDul  /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  0xEul  /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  0xFul  /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  0x10ul  /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  0x11ul  /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  0x12ul  /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  0x13ul  /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   0x18ul  /**< \brief (ADC_INPUTCTRL) Temperature Reference */
-#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul  /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
-#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    0x1Cul  /**< \brief (ADC_INPUTCTRL) DAC Output */
-#define ADC_INPUTCTRL_MUXPOS_PIN0   (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN1   (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN2   (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN3   (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN4   (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN5   (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN6   (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN7   (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN8   (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN9   (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN10  (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN11  (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN12  (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN13  (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN14  (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN15  (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN16  (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN17  (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN18  (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PIN19  (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_TEMP   (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
-#define ADC_INPUTCTRL_MUXNEG_Msk    (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
-#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_GND_Val    0x18ul  /**< \brief (ADC_INPUTCTRL) Internal Ground */
-#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  0x19ul  /**< \brief (ADC_INPUTCTRL) I/O Ground */
-#define ADC_INPUTCTRL_MUXNEG_PIN0   (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN1   (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN2   (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN3   (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN4   (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN5   (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN6   (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_PIN7   (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_IOGND  (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_INPUTSCAN_Pos 16           /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
-#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
-#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
-#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20           /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
-#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
-#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
-#define ADC_INPUTCTRL_GAIN_Pos      24           /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
-#define ADC_INPUTCTRL_GAIN_Msk      (0xFul << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_GAIN(value)   (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
-#define   ADC_INPUTCTRL_GAIN_1X_Val       0x0ul  /**< \brief (ADC_INPUTCTRL) 1x */
-#define   ADC_INPUTCTRL_GAIN_2X_Val       0x1ul  /**< \brief (ADC_INPUTCTRL) 2x */
-#define   ADC_INPUTCTRL_GAIN_4X_Val       0x2ul  /**< \brief (ADC_INPUTCTRL) 4x */
-#define   ADC_INPUTCTRL_GAIN_8X_Val       0x3ul  /**< \brief (ADC_INPUTCTRL) 8x */
-#define   ADC_INPUTCTRL_GAIN_16X_Val      0x4ul  /**< \brief (ADC_INPUTCTRL) 16x */
-#define   ADC_INPUTCTRL_GAIN_DIV2_Val     0xFul  /**< \brief (ADC_INPUTCTRL) 1/2x */
-#define ADC_INPUTCTRL_GAIN_1X       (ADC_INPUTCTRL_GAIN_1X_Val     << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_GAIN_2X       (ADC_INPUTCTRL_GAIN_2X_Val     << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_GAIN_4X       (ADC_INPUTCTRL_GAIN_4X_Val     << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_GAIN_8X       (ADC_INPUTCTRL_GAIN_8X_Val     << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_GAIN_16X      (ADC_INPUTCTRL_GAIN_16X_Val    << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_GAIN_DIV2     (ADC_INPUTCTRL_GAIN_DIV2_Val   << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_MASK          0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
-
-/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event In          */
-    uint8_t  SYNCEI:1;         /*!< bit:      1  Synchronization Event In           */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
-    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_EVCTRL_OFFSET           0x14         /**< \brief (ADC_EVCTRL offset) Event Control */
-#define ADC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (ADC_EVCTRL reset_value) Event Control */
-
-#define ADC_EVCTRL_STARTEI_Pos      0            /**< \brief (ADC_EVCTRL) Start Conversion Event In */
-#define ADC_EVCTRL_STARTEI          (0x1ul << ADC_EVCTRL_STARTEI_Pos)
-#define ADC_EVCTRL_SYNCEI_Pos       1            /**< \brief (ADC_EVCTRL) Synchronization Event In */
-#define ADC_EVCTRL_SYNCEI           (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
-#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
-#define ADC_EVCTRL_RESRDYEO         (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
-#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
-#define ADC_EVCTRL_WINMONEO         (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
-#define ADC_EVCTRL_MASK             0x33ul       /**< \brief (ADC_EVCTRL) MASK Register */
-
-/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
-    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
-    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
-    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENCLR_OFFSET         0x16         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
-#define ADC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
-#define ADC_INTENCLR_RESRDY         (0x1ul << ADC_INTENCLR_RESRDY_Pos)
-#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
-#define ADC_INTENCLR_OVERRUN        (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
-#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
-#define ADC_INTENCLR_WINMON         (0x1ul << ADC_INTENCLR_WINMON_Pos)
-#define ADC_INTENCLR_SYNCRDY_Pos    3            /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
-#define ADC_INTENCLR_SYNCRDY        (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
-#define ADC_INTENCLR_MASK           0x0Ful       /**< \brief (ADC_INTENCLR) MASK Register */
-
-/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
-    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
-    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
-    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENSET_OFFSET         0x17         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
-#define ADC_INTENSET_RESETVALUE     0x00ul       /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
-
-#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
-#define ADC_INTENSET_RESRDY         (0x1ul << ADC_INTENSET_RESRDY_Pos)
-#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
-#define ADC_INTENSET_OVERRUN        (0x1ul << ADC_INTENSET_OVERRUN_Pos)
-#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
-#define ADC_INTENSET_WINMON         (0x1ul << ADC_INTENSET_WINMON_Pos)
-#define ADC_INTENSET_SYNCRDY_Pos    3            /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
-#define ADC_INTENSET_SYNCRDY        (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
-#define ADC_INTENSET_MASK           0x0Ful       /**< \brief (ADC_INTENSET) MASK Register */
-
-/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready                       */
-    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun                            */
-    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor                     */
-    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
-    __I uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTFLAG_OFFSET          0x18         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define ADC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready */
-#define ADC_INTFLAG_RESRDY          (0x1ul << ADC_INTFLAG_RESRDY_Pos)
-#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun */
-#define ADC_INTFLAG_OVERRUN         (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
-#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor */
-#define ADC_INTFLAG_WINMON          (0x1ul << ADC_INTFLAG_WINMON_Pos)
-#define ADC_INTFLAG_SYNCRDY_Pos     3            /**< \brief (ADC_INTFLAG) Synchronization Ready */
-#define ADC_INTFLAG_SYNCRDY         (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
-#define ADC_INTFLAG_MASK            0x0Ful       /**< \brief (ADC_INTFLAG) MASK Register */
-
-/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_STATUS_OFFSET           0x19         /**< \brief (ADC_STATUS offset) Status */
-#define ADC_STATUS_RESETVALUE       0x00ul       /**< \brief (ADC_STATUS reset_value) Status */
-
-#define ADC_STATUS_SYNCBUSY_Pos     7            /**< \brief (ADC_STATUS) Synchronization Busy */
-#define ADC_STATUS_SYNCBUSY         (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
-#define ADC_STATUS_MASK             0x80ul       /**< \brief (ADC_STATUS) MASK Register */
-
-/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/  16) Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESULT_OFFSET           0x1A         /**< \brief (ADC_RESULT offset) Result */
-#define ADC_RESULT_RESETVALUE       0x0000ul     /**< \brief (ADC_RESULT reset_value) Result */
-
-#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
-#define ADC_RESULT_RESULT_Msk       (0xFFFFul << ADC_RESULT_RESULT_Pos)
-#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
-#define ADC_RESULT_MASK             0xFFFFul     /**< \brief (ADC_RESULT) MASK Register */
-
-/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_WINLT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINLT_OFFSET            0x1C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
-#define ADC_WINLT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
-
-#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
-#define ADC_WINLT_WINLT_Msk         (0xFFFFul << ADC_WINLT_WINLT_Pos)
-#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
-#define ADC_WINLT_MASK              0xFFFFul     /**< \brief (ADC_WINLT) MASK Register */
-
-/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_WINUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINUT_OFFSET            0x20         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
-#define ADC_WINUT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
-
-#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
-#define ADC_WINUT_WINUT_Msk         (0xFFFFul << ADC_WINUT_WINUT_Pos)
-#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
-#define ADC_WINUT_MASK              0xFFFFul     /**< \brief (ADC_WINUT) MASK Register */
-
-/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_GAINCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_GAINCORR_OFFSET         0x24         /**< \brief (ADC_GAINCORR offset) Gain Correction */
-#define ADC_GAINCORR_RESETVALUE     0x0000ul     /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
-
-#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
-#define ADC_GAINCORR_GAINCORR_Msk   (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
-#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
-#define ADC_GAINCORR_MASK           0x0FFFul     /**< \brief (ADC_GAINCORR) MASK Register */
-
-/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_OFFSETCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_OFFSETCORR_OFFSET       0x26         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
-#define ADC_OFFSETCORR_RESETVALUE   0x0000ul     /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
-
-#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
-#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
-#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
-#define ADC_OFFSETCORR_MASK         0x0FFFul     /**< \brief (ADC_OFFSETCORR) MASK Register */
-
-/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LINEARITY_CAL:8;  /*!< bit:  0.. 7  Linearity Calibration Value        */
-    uint16_t BIAS_CAL:3;       /*!< bit:  8..10  Bias Calibration Value             */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CALIB_OFFSET            0x28         /**< \brief (ADC_CALIB offset) Calibration */
-#define ADC_CALIB_RESETVALUE        0x0000ul     /**< \brief (ADC_CALIB reset_value) Calibration */
-
-#define ADC_CALIB_LINEARITY_CAL_Pos 0            /**< \brief (ADC_CALIB) Linearity Calibration Value */
-#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
-#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
-#define ADC_CALIB_BIAS_CAL_Pos      8            /**< \brief (ADC_CALIB) Bias Calibration Value */
-#define ADC_CALIB_BIAS_CAL_Msk      (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
-#define ADC_CALIB_BIAS_CAL(value)   (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
-#define ADC_CALIB_MASK              0x07FFul     /**< \brief (ADC_CALIB) MASK Register */
-
-/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DBGCTRL_OFFSET          0x2A         /**< \brief (ADC_DBGCTRL offset) Debug Control */
-#define ADC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
-
-#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
-#define ADC_DBGCTRL_DBGRUN          (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
-#define ADC_DBGCTRL_MASK            0x01ul       /**< \brief (ADC_DBGCTRL) MASK Register */
-
-/** \brief ADC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x01 (R/W  8) Reference Control */
-  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x02 (R/W  8) Average Control */
-  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x03 (R/W  8) Sampling Time Control */
-  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W 16) Control B */
-       RoReg8                    Reserved1[0x2];
-  __IO ADC_WINCTRL_Type          WINCTRL;     /**< \brief Offset: 0x08 (R/W  8) Window Monitor Control */
-       RoReg8                    Reserved2[0x3];
-  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x0C (R/W  8) Software Trigger */
-       RoReg8                    Reserved3[0x3];
-  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x10 (R/W 32) Input Control */
-  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x14 (R/W  8) Event Control */
-       RoReg8                    Reserved4[0x1];
-  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x16 (R/W  8) Interrupt Enable Clear */
-  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x17 (R/W  8) Interrupt Enable Set */
-  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) Interrupt Flag Status and Clear */
-  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x19 (R/   8) Status */
-  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x1A (R/  16) Result */
-  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
-       RoReg8                    Reserved5[0x2];
-  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
-       RoReg8                    Reserved6[0x2];
-  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
-  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
-  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x28 (R/W 16) Calibration */
-  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x2A (R/W  8) Debug Control */
-} Adc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_ADC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC                     0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE        0x00ul       /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST             (0x1ul << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE            (0x1ul << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY          (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK              0x07ul       /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W  8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET          0x01         /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk      (0xFul << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define   ADC_REFCTRL_REFSEL_INT1V_Val    0x0ul  /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  0x1ul  /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  0x2ul  /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    0x3ul  /**< \brief (ADC_REFCTRL) External reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    0x4ul  /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V    (ADC_REFCTRL_REFSEL_INT1V_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP         (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            0x8Ful       /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W  8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
+    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET          0x02         /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     0x0ul  /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     0x1ul  /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     0x2ul  /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     0x3ul  /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    0x4ul  /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    0x5ul  /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    0x6ul  /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   0x7ul  /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   0x8ul  /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   0x9ul  /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  0xAul  /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk      (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK            0x7Ful       /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W  8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET         0x03         /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     0x00ul       /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_MASK           0x3Ful       /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DIFFMODE:1;       /*!< bit:      0  Differential Mode                  */
+    uint16_t LEFTADJ:1;        /*!< bit:      1  Left-Adjusted Result               */
+    uint16_t FREERUN:1;        /*!< bit:      2  Free Running Mode                  */
+    uint16_t CORREN:1;         /*!< bit:      3  Digital Correction Logic Enabled   */
+    uint16_t RESSEL:2;         /*!< bit:  4.. 5  Conversion Result Resolution       */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET            0x04         /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE        0x0000ul     /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE          (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ           (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos       2            /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN           (0x1ul << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos        3            /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN            (0x1ul << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos        4            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk        (0x3ul << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define   ADC_CTRLB_RESSEL_12BIT_Val      0x0ul  /**< \brief (ADC_CTRLB) 12-bit result */
+#define   ADC_CTRLB_RESSEL_16BIT_Val      0x1ul  /**< \brief (ADC_CTRLB) For averaging mode output */
+#define   ADC_CTRLB_RESSEL_10BIT_Val      0x2ul  /**< \brief (ADC_CTRLB) 10-bit result */
+#define   ADC_CTRLB_RESSEL_8BIT_Val       0x3ul  /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos     8            /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk     (0x7ul << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value)  (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
+#define   ADC_CTRLB_PRESCALER_DIV4_Val    0x0ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define   ADC_CTRLB_PRESCALER_DIV8_Val    0x1ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define   ADC_CTRLB_PRESCALER_DIV16_Val   0x2ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define   ADC_CTRLB_PRESCALER_DIV32_Val   0x3ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define   ADC_CTRLB_PRESCALER_DIV64_Val   0x4ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define   ADC_CTRLB_PRESCALER_DIV128_Val  0x5ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define   ADC_CTRLB_PRESCALER_DIV256_Val  0x6ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define   ADC_CTRLB_PRESCALER_DIV512_Val  0x7ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32   (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64   (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512  (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK              0x073Ful     /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W  8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WINMODE:3;        /*!< bit:  0.. 2  Window Monitor Mode                */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET          0x08         /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos     0            /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk     (0x7ul << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value)  (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
+#define   ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul  /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define   ADC_WINCTRL_WINMODE_MODE1_Val   0x1ul  /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define   ADC_WINCTRL_WINMODE_MODE2_Val   0x2ul  /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE3_Val   0x3ul  /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE4_Val   0x4ul  /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1   (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2   (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3   (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4   (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK            0x07ul       /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W  8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
+    uint8_t  START:1;          /*!< bit:      1  ADC Start Conversion               */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET           0x0C         /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       0x00ul       /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH            (0x1ul << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START            (0x1ul << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             0x03ul       /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t INPUTSCAN:4;      /*!< bit: 16..19  Number of Input Channels Included in Scan */
+    uint32_t INPUTOFFSET:4;    /*!< bit: 20..23  Positive Mux Setting Offset        */
+    uint32_t GAIN:4;           /*!< bit: 24..27  Gain Factor Selection              */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE    0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk    (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   0x8ul  /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   0x9ul  /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  0xAul  /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  0xBul  /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  0xCul  /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  0xDul  /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  0xEul  /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  0xFul  /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  0x10ul  /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  0x11ul  /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  0x12ul  /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  0x13ul  /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   0x18ul  /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul  /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
+#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    0x1Cul  /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0   (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1   (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2   (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3   (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4   (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5   (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6   (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7   (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8   (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9   (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10  (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11  (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12  (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13  (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14  (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15  (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16  (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17  (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18  (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19  (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP   (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk    (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    0x18ul  /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  0x19ul  /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0   (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1   (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2   (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3   (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4   (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5   (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6   (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7   (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND  (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16           /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20           /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
+#define ADC_INPUTCTRL_GAIN_Pos      24           /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk      (0xFul << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value)   (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
+#define   ADC_INPUTCTRL_GAIN_1X_Val       0x0ul  /**< \brief (ADC_INPUTCTRL) 1x */
+#define   ADC_INPUTCTRL_GAIN_2X_Val       0x1ul  /**< \brief (ADC_INPUTCTRL) 2x */
+#define   ADC_INPUTCTRL_GAIN_4X_Val       0x2ul  /**< \brief (ADC_INPUTCTRL) 4x */
+#define   ADC_INPUTCTRL_GAIN_8X_Val       0x3ul  /**< \brief (ADC_INPUTCTRL) 8x */
+#define   ADC_INPUTCTRL_GAIN_16X_Val      0x4ul  /**< \brief (ADC_INPUTCTRL) 16x */
+#define   ADC_INPUTCTRL_GAIN_DIV2_Val     0xFul  /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X       (ADC_INPUTCTRL_GAIN_1X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X       (ADC_INPUTCTRL_GAIN_2X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X       (ADC_INPUTCTRL_GAIN_4X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X       (ADC_INPUTCTRL_GAIN_8X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X      (ADC_INPUTCTRL_GAIN_16X_Val    << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2     (ADC_INPUTCTRL_GAIN_DIV2_Val   << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK          0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event In          */
+    uint8_t  SYNCEI:1;         /*!< bit:      1  Synchronization Event In           */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
+    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET           0x14         /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos      0            /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI          (0x1ul << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos       1            /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI           (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO         (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO         (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             0x33ul       /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET         0x16         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY         (0x1ul << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN        (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON         (0x1ul << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos    3            /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY        (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK           0x0Ful       /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET         0x17         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     0x00ul       /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY         (0x1ul << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN        (0x1ul << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON         (0x1ul << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos    3            /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY        (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK           0x0Ful       /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready                       */
+    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun                            */
+    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor                     */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    __I uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET          0x18         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY          (0x1ul << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN         (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON          (0x1ul << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos     3            /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY         (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK            0x0Ful       /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET           0x19         /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE       0x00ul       /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos     7            /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY         (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK             0x80ul       /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/  16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET           0x1A         /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE       0x0000ul     /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk       (0xFFFFul << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK             0xFFFFul     /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET            0x1C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk         (0xFFFFul << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK              0xFFFFul     /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET            0x20         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk         (0xFFFFul << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK              0xFFFFul     /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET         0x24         /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     0x0000ul     /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk   (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK           0x0FFFul     /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET       0x26         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   0x0000ul     /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK         0x0FFFul     /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LINEARITY_CAL:8;  /*!< bit:  0.. 7  Linearity Calibration Value        */
+    uint16_t BIAS_CAL:3;       /*!< bit:  8..10  Bias Calibration Value             */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET            0x28         /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE        0x0000ul     /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0            /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
+#define ADC_CALIB_BIAS_CAL_Pos      8            /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk      (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value)   (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
+#define ADC_CALIB_MASK              0x07FFul     /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET          0x2A         /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN          (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            0x01ul       /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x01 (R/W  8) Reference Control */
+  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x02 (R/W  8) Average Control */
+  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x03 (R/W  8) Sampling Time Control */
+  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W 16) Control B */
+       RoReg8                    Reserved1[0x2];
+  __IO ADC_WINCTRL_Type          WINCTRL;     /**< \brief Offset: 0x08 (R/W  8) Window Monitor Control */
+       RoReg8                    Reserved2[0x3];
+  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x0C (R/W  8) Software Trigger */
+       RoReg8                    Reserved3[0x3];
+  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x10 (R/W 32) Input Control */
+  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x14 (R/W  8) Event Control */
+       RoReg8                    Reserved4[0x1];
+  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x16 (R/W  8) Interrupt Enable Clear */
+  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x17 (R/W  8) Interrupt Enable Set */
+  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) Interrupt Flag Status and Clear */
+  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x19 (R/   8) Status */
+  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x1A (R/  16) Result */
+  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+       RoReg8                    Reserved5[0x2];
+  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+       RoReg8                    Reserved6[0x2];
+  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x28 (R/W 16) Calibration */
+  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x2A (R/W  8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h
index a9aff66..343fc7d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h
@@ -1,276 +1,276 @@
-/**
- * \file
- *
- * \brief Component description for DAC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_DAC_COMPONENT_
-#define _SAMD21_DAC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR DAC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_DAC Digital Analog Converter */
-/*@{*/
-
-#define DAC_U2214
-#define REV_DAC                     0x110
-
-/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLA_OFFSET            0x0          /**< \brief (DAC_CTRLA offset) Control A */
-#define DAC_CTRLA_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLA reset_value) Control A */
-
-#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
-#define DAC_CTRLA_SWRST             (0x1ul << DAC_CTRLA_SWRST_Pos)
-#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable */
-#define DAC_CTRLA_ENABLE            (0x1ul << DAC_CTRLA_ENABLE_Pos)
-#define DAC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (DAC_CTRLA) Run in Standby */
-#define DAC_CTRLA_RUNSTDBY          (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
-#define DAC_CTRLA_MASK              0x07ul       /**< \brief (DAC_CTRLA) MASK Register */
-
-/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W  8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EOEN:1;           /*!< bit:      0  External Output Enable             */
-    uint8_t  IOEN:1;           /*!< bit:      1  Internal Output Enable             */
-    uint8_t  LEFTADJ:1;        /*!< bit:      2  Left Adjusted Data                 */
-    uint8_t  VPD:1;            /*!< bit:      3  Voltage Pump Disable               */
-    uint8_t  BDWP:1;           /*!< bit:      4  Bypass DATABUF Write Protection    */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  REFSEL:2;         /*!< bit:  6.. 7  Reference Selection                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLB_OFFSET            0x1          /**< \brief (DAC_CTRLB offset) Control B */
-#define DAC_CTRLB_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLB reset_value) Control B */
-
-#define DAC_CTRLB_EOEN_Pos          0            /**< \brief (DAC_CTRLB) External Output Enable */
-#define DAC_CTRLB_EOEN              (0x1ul << DAC_CTRLB_EOEN_Pos)
-#define DAC_CTRLB_IOEN_Pos          1            /**< \brief (DAC_CTRLB) Internal Output Enable */
-#define DAC_CTRLB_IOEN              (0x1ul << DAC_CTRLB_IOEN_Pos)
-#define DAC_CTRLB_LEFTADJ_Pos       2            /**< \brief (DAC_CTRLB) Left Adjusted Data */
-#define DAC_CTRLB_LEFTADJ           (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
-#define DAC_CTRLB_VPD_Pos           3            /**< \brief (DAC_CTRLB) Voltage Pump Disable */
-#define DAC_CTRLB_VPD               (0x1ul << DAC_CTRLB_VPD_Pos)
-#define DAC_CTRLB_BDWP_Pos          4            /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
-#define DAC_CTRLB_BDWP              (0x1ul << DAC_CTRLB_BDWP_Pos)
-#define DAC_CTRLB_REFSEL_Pos        6            /**< \brief (DAC_CTRLB) Reference Selection */
-#define DAC_CTRLB_REFSEL_Msk        (0x3ul << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
-#define   DAC_CTRLB_REFSEL_INT1V_Val      0x0ul  /**< \brief (DAC_CTRLB) Internal 1.0V reference */
-#define   DAC_CTRLB_REFSEL_AVCC_Val       0x1ul  /**< \brief (DAC_CTRLB) AVCC */
-#define   DAC_CTRLB_REFSEL_VREFP_Val      0x2ul  /**< \brief (DAC_CTRLB) External reference */
-#define DAC_CTRLB_REFSEL_INT1V      (DAC_CTRLB_REFSEL_INT1V_Val    << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_AVCC       (DAC_CTRLB_REFSEL_AVCC_Val     << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VREFP      (DAC_CTRLB_REFSEL_VREFP_Val    << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_MASK              0xDFul       /**< \brief (DAC_CTRLB) MASK Register */
-
-/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event Input       */
-    uint8_t  EMPTYEO:1;        /*!< bit:      1  Data Buffer Empty Event Output     */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_EVCTRL_OFFSET           0x2          /**< \brief (DAC_EVCTRL offset) Event Control */
-#define DAC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (DAC_EVCTRL reset_value) Event Control */
-
-#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
-#define DAC_EVCTRL_STARTEI          (0x1ul << DAC_EVCTRL_STARTEI_Pos)
-#define DAC_EVCTRL_EMPTYEO_Pos      1            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
-#define DAC_EVCTRL_EMPTYEO          (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
-#define DAC_EVCTRL_MASK             0x03ul       /**< \brief (DAC_EVCTRL) MASK Register */
-
-/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
-    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
-    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENCLR_OFFSET         0x4          /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
-#define DAC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN       (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
-#define DAC_INTENCLR_EMPTY_Pos      1            /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY          (0x1ul << DAC_INTENCLR_EMPTY_Pos)
-#define DAC_INTENCLR_SYNCRDY_Pos    2            /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
-#define DAC_INTENCLR_SYNCRDY        (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
-#define DAC_INTENCLR_MASK           0x07ul       /**< \brief (DAC_INTENCLR) MASK Register */
-
-/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
-    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
-    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENSET_OFFSET         0x5          /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
-#define DAC_INTENSET_RESETVALUE     0x00ul       /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
-
-#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN       (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
-#define DAC_INTENSET_EMPTY_Pos      1            /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY          (0x1ul << DAC_INTENSET_EMPTY_Pos)
-#define DAC_INTENSET_SYNCRDY_Pos    2            /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
-#define DAC_INTENSET_SYNCRDY        (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
-#define DAC_INTENSET_MASK           0x07ul       /**< \brief (DAC_INTENSET) MASK Register */
-
-/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun                           */
-    __I uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty                  */
-    __I uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready              */
-    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTFLAG_OFFSET          0x6          /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define DAC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Underrun */
-#define DAC_INTFLAG_UNDERRUN        (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
-#define DAC_INTFLAG_EMPTY_Pos       1            /**< \brief (DAC_INTFLAG) Data Buffer Empty */
-#define DAC_INTFLAG_EMPTY           (0x1ul << DAC_INTFLAG_EMPTY_Pos)
-#define DAC_INTFLAG_SYNCRDY_Pos     2            /**< \brief (DAC_INTFLAG) Synchronization Ready */
-#define DAC_INTFLAG_SYNCRDY         (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
-#define DAC_INTFLAG_MASK            0x07ul       /**< \brief (DAC_INTFLAG) MASK Register */
-
-/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_STATUS_OFFSET           0x7          /**< \brief (DAC_STATUS offset) Status */
-#define DAC_STATUS_RESETVALUE       0x00ul       /**< \brief (DAC_STATUS reset_value) Status */
-
-#define DAC_STATUS_SYNCBUSY_Pos     7            /**< \brief (DAC_STATUS) Synchronization Busy Status */
-#define DAC_STATUS_SYNCBUSY         (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
-#define DAC_STATUS_MASK             0x80ul       /**< \brief (DAC_STATUS) MASK Register */
-
-/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DATA:16;          /*!< bit:  0..15  Data value to be converted         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DAC_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATA_OFFSET             0x8          /**< \brief (DAC_DATA offset) Data */
-#define DAC_DATA_RESETVALUE         0x0000ul     /**< \brief (DAC_DATA reset_value) Data */
-
-#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) Data value to be converted */
-#define DAC_DATA_DATA_Msk           (0xFFFFul << DAC_DATA_DATA_Pos)
-#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
-#define DAC_DATA_MASK               0xFFFFul     /**< \brief (DAC_DATA) MASK Register */
-
-/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DATABUF:16;       /*!< bit:  0..15  Data Buffer                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DAC_DATABUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATABUF_OFFSET          0xC          /**< \brief (DAC_DATABUF offset) Data Buffer */
-#define DAC_DATABUF_RESETVALUE      0x0000ul     /**< \brief (DAC_DATABUF reset_value) Data Buffer */
-
-#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) Data Buffer */
-#define DAC_DATABUF_DATABUF_Msk     (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
-#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
-#define DAC_DATABUF_MASK            0xFFFFul     /**< \brief (DAC_DATABUF) MASK Register */
-
-/** \brief DAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control A */
-  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x1 (R/W  8) Control B */
-  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x2 (R/W  8) Event Control */
-       RoReg8                    Reserved1[0x1];
-  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
-  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
-  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
-  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
-  __IO DAC_DATA_Type             DATA;        /**< \brief Offset: 0x8 (R/W 16) Data */
-       RoReg8                    Reserved2[0x2];
-  __IO DAC_DATABUF_Type          DATABUF;     /**< \brief Offset: 0xC (R/W 16) Data Buffer */
-} Dac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_DAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC                     0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET            0x0          /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST             (0x1ul << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE            (0x1ul << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY          (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK              0x07ul       /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EOEN:1;           /*!< bit:      0  External Output Enable             */
+    uint8_t  IOEN:1;           /*!< bit:      1  Internal Output Enable             */
+    uint8_t  LEFTADJ:1;        /*!< bit:      2  Left Adjusted Data                 */
+    uint8_t  VPD:1;            /*!< bit:      3  Voltage Pump Disable               */
+    uint8_t  BDWP:1;           /*!< bit:      4  Bypass DATABUF Write Protection    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  REFSEL:2;         /*!< bit:  6.. 7  Reference Selection                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET            0x1          /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos          0            /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN              (0x1ul << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos          1            /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN              (0x1ul << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos       2            /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ           (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos           3            /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD               (0x1ul << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos          4            /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP              (0x1ul << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos        6            /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk        (0x3ul << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define   DAC_CTRLB_REFSEL_INT1V_Val      0x0ul  /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define   DAC_CTRLB_REFSEL_AVCC_Val       0x1ul  /**< \brief (DAC_CTRLB) AVCC */
+#define   DAC_CTRLB_REFSEL_VREFP_Val      0x2ul  /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V      (DAC_CTRLB_REFSEL_INT1V_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC       (DAC_CTRLB_REFSEL_AVCC_Val     << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP      (DAC_CTRLB_REFSEL_VREFP_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK              0xDFul       /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event Input       */
+    uint8_t  EMPTYEO:1;        /*!< bit:      1  Data Buffer Empty Event Output     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET           0x2          /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI          (0x1ul << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos      1            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO          (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK             0x03ul       /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET         0x4          /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN       (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos      1            /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY          (0x1ul << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos    2            /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY        (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK           0x07ul       /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET         0x5          /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     0x00ul       /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN       (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos      1            /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY          (0x1ul << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos    2            /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY        (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK           0x07ul       /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun                           */
+    __I uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty                  */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready              */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET          0x6          /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN        (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos       1            /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY           (0x1ul << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos     2            /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY         (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK            0x07ul       /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET           0x7          /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE       0x00ul       /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos     7            /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY         (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK             0x80ul       /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:16;          /*!< bit:  0..15  Data value to be converted         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET             0x8          /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE         0x0000ul     /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk           (0xFFFFul << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK               0xFFFFul     /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATABUF:16;       /*!< bit:  0..15  Data Buffer                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET          0xC          /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE      0x0000ul     /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk     (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK            0xFFFFul     /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control A */
+  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x1 (R/W  8) Control B */
+  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x2 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __IO DAC_DATA_Type             DATA;        /**< \brief Offset: 0x8 (R/W 16) Data */
+       RoReg8                    Reserved2[0x2];
+  __IO DAC_DATABUF_Type          DATABUF;     /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h
index 4a9f8e9..8b8952d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h
@@ -1,1077 +1,1077 @@
-/**
- * \file
- *
- * \brief Component description for DMAC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_DMAC_COMPONENT_
-#define _SAMD21_DMAC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR DMAC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
-/*@{*/
-
-#define DMAC_U2223
-#define REV_DMAC                    0x110
-
-/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
-    uint16_t CRCENABLE:1;      /*!< bit:      2  CRC Enable                         */
-    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
-    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
-    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
-    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
-    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
-#define DMAC_CTRL_RESETVALUE        0x0000ul     /**< \brief (DMAC_CTRL reset_value) Control */
-
-#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
-#define DMAC_CTRL_SWRST             (0x1ul << DMAC_CTRL_SWRST_Pos)
-#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
-#define DMAC_CTRL_DMAENABLE         (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
-#define DMAC_CTRL_CRCENABLE_Pos     2            /**< \brief (DMAC_CTRL) CRC Enable */
-#define DMAC_CTRL_CRCENABLE         (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
-#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
-#define DMAC_CTRL_LVLEN0            (1 << DMAC_CTRL_LVLEN0_Pos)
-#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
-#define DMAC_CTRL_LVLEN1            (1 << DMAC_CTRL_LVLEN1_Pos)
-#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
-#define DMAC_CTRL_LVLEN2            (1 << DMAC_CTRL_LVLEN2_Pos)
-#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
-#define DMAC_CTRL_LVLEN3            (1 << DMAC_CTRL_LVLEN3_Pos)
-#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
-#define DMAC_CTRL_LVLEN_Msk         (0xFul << DMAC_CTRL_LVLEN_Pos)
-#define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
-#define DMAC_CTRL_MASK              0x0F07ul     /**< \brief (DMAC_CTRL) MASK Register */
-
-/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
-    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
-    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_CRCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
-#define DMAC_CRCCTRL_RESETVALUE     0x0000ul     /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
-
-#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
-#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
-#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul  /**< \brief (DMAC_CRCCTRL) Byte bus access */
-#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul  /**< \brief (DMAC_CRCCTRL) Half-word bus access */
-#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul  /**< \brief (DMAC_CRCCTRL) Word bus access */
-#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
-#define DMAC_CRCCTRL_CRCPOLY_Msk    (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
-#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  0x0ul  /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
-#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  0x1ul  /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
-#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
-#define DMAC_CRCCTRL_CRCSRC_Msk     (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
-#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   0x0ul  /**< \brief (DMAC_CRCCTRL) No action */
-#define   DMAC_CRCCTRL_CRCSRC_IO_Val      0x1ul  /**< \brief (DMAC_CRCCTRL) I/O interface */
-#define DMAC_CRCCTRL_CRCSRC_NOACT   (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_MASK           0x3F0Ful     /**< \brief (DMAC_CRCCTRL) MASK Register */
-
-/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_CRCDATAIN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
-#define DMAC_CRCDATAIN_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
-
-#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
-#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
-#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
-#define DMAC_CRCDATAIN_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
-
-/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_CRCCHKSUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
-#define DMAC_CRCCHKSUM_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
-
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
-#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
-#define DMAC_CRCCHKSUM_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
-
-/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
-    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CRCSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
-#define DMAC_CRCSTATUS_RESETVALUE   0x00ul       /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
-
-#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
-#define DMAC_CRCSTATUS_CRCBUSY      (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
-#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
-#define DMAC_CRCSTATUS_CRCZERO      (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
-#define DMAC_CRCSTATUS_MASK         0x03ul       /**< \brief (DMAC_CRCSTATUS) MASK Register */
-
-/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
-#define DMAC_DBGCTRL_RESETVALUE     0x00ul       /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
-
-#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
-#define DMAC_DBGCTRL_DBGRUN         (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
-#define DMAC_DBGCTRL_MASK           0x01ul       /**< \brief (DMAC_DBGCTRL) MASK Register */
-
-/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W  8) QOS Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WRBQOS:2;         /*!< bit:  0.. 1  Write-Back Quality of Service      */
-    uint8_t  FQOS:2;           /*!< bit:  2.. 3  Fetch Quality of Service           */
-    uint8_t  DQOS:2;           /*!< bit:  4.. 5  Data Transfer Quality of Service   */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_QOSCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_QOSCTRL_OFFSET         0x0E         /**< \brief (DMAC_QOSCTRL offset) QOS Control */
-#define DMAC_QOSCTRL_RESETVALUE     0x15ul       /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
-
-#define DMAC_QOSCTRL_WRBQOS_Pos     0            /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
-#define DMAC_QOSCTRL_WRBQOS_Msk     (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
-#define DMAC_QOSCTRL_WRBQOS(value)  (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
-#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
-#define   DMAC_QOSCTRL_WRBQOS_LOW_Val     0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
-#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val  0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
-#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val    0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
-#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
-#define DMAC_QOSCTRL_WRBQOS_LOW     (DMAC_QOSCTRL_WRBQOS_LOW_Val   << DMAC_QOSCTRL_WRBQOS_Pos)
-#define DMAC_QOSCTRL_WRBQOS_MEDIUM  (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
-#define DMAC_QOSCTRL_WRBQOS_HIGH    (DMAC_QOSCTRL_WRBQOS_HIGH_Val  << DMAC_QOSCTRL_WRBQOS_Pos)
-#define DMAC_QOSCTRL_FQOS_Pos       2            /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
-#define DMAC_QOSCTRL_FQOS_Msk       (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
-#define DMAC_QOSCTRL_FQOS(value)    (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
-#define   DMAC_QOSCTRL_FQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
-#define   DMAC_QOSCTRL_FQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
-#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
-#define   DMAC_QOSCTRL_FQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
-#define DMAC_QOSCTRL_FQOS_DISABLE   (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
-#define DMAC_QOSCTRL_FQOS_LOW       (DMAC_QOSCTRL_FQOS_LOW_Val     << DMAC_QOSCTRL_FQOS_Pos)
-#define DMAC_QOSCTRL_FQOS_MEDIUM    (DMAC_QOSCTRL_FQOS_MEDIUM_Val  << DMAC_QOSCTRL_FQOS_Pos)
-#define DMAC_QOSCTRL_FQOS_HIGH      (DMAC_QOSCTRL_FQOS_HIGH_Val    << DMAC_QOSCTRL_FQOS_Pos)
-#define DMAC_QOSCTRL_DQOS_Pos       4            /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
-#define DMAC_QOSCTRL_DQOS_Msk       (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
-#define DMAC_QOSCTRL_DQOS(value)    (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
-#define   DMAC_QOSCTRL_DQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
-#define   DMAC_QOSCTRL_DQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
-#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
-#define   DMAC_QOSCTRL_DQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
-#define DMAC_QOSCTRL_DQOS_DISABLE   (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
-#define DMAC_QOSCTRL_DQOS_LOW       (DMAC_QOSCTRL_DQOS_LOW_Val     << DMAC_QOSCTRL_DQOS_Pos)
-#define DMAC_QOSCTRL_DQOS_MEDIUM    (DMAC_QOSCTRL_DQOS_MEDIUM_Val  << DMAC_QOSCTRL_DQOS_Pos)
-#define DMAC_QOSCTRL_DQOS_HIGH      (DMAC_QOSCTRL_DQOS_HIGH_Val    << DMAC_QOSCTRL_DQOS_Pos)
-#define DMAC_QOSCTRL_MASK           0x3Ful       /**< \brief (DMAC_QOSCTRL) MASK Register */
-
-/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
-    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
-    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
-    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
-    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
-    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
-    uint32_t SWTRIG6:1;        /*!< bit:      6  Channel 6 Software Trigger         */
-    uint32_t SWTRIG7:1;        /*!< bit:      7  Channel 7 Software Trigger         */
-    uint32_t SWTRIG8:1;        /*!< bit:      8  Channel 8 Software Trigger         */
-    uint32_t SWTRIG9:1;        /*!< bit:      9  Channel 9 Software Trigger         */
-    uint32_t SWTRIG10:1;       /*!< bit:     10  Channel 10 Software Trigger        */
-    uint32_t SWTRIG11:1;       /*!< bit:     11  Channel 11 Software Trigger        */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t SWTRIG:12;        /*!< bit:  0..11  Channel x Software Trigger         */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_SWTRIGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
-#define DMAC_SWTRIGCTRL_RESETVALUE  0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
-
-#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG0     (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG1     (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG2     (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG3     (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG4     (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG5     (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6            /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG6     (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7            /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG7     (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8            /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG8     (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9            /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG9     (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10           /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG10    (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG11    (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
-#define DMAC_SWTRIGCTRL_MASK        0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
-
-/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LVLPRI0:4;        /*!< bit:  0.. 3  Level 0 Channel Priority Number    */
-    uint32_t :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
-    uint32_t LVLPRI1:4;        /*!< bit:  8..11  Level 1 Channel Priority Number    */
-    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
-    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
-    uint32_t LVLPRI2:4;        /*!< bit: 16..19  Level 2 Channel Priority Number    */
-    uint32_t :3;               /*!< bit: 20..22  Reserved                           */
-    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
-    uint32_t LVLPRI3:4;        /*!< bit: 24..27  Level 3 Channel Priority Number    */
-    uint32_t :3;               /*!< bit: 28..30  Reserved                           */
-    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_PRICTRL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
-#define DMAC_PRICTRL0_RESETVALUE    0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
-
-#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI0_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
-#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
-#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN0      (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
-#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI1_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
-#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
-#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN1      (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
-#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI2_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
-#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
-#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN2      (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
-#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI3_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
-#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
-#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN3      (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
-#define DMAC_PRICTRL0_MASK          0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
-
-/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ID:4;             /*!< bit:  0.. 3  Channel ID                         */
-    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
-    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
-    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
-    uint16_t :2;               /*!< bit: 11..12  Reserved                           */
-    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
-    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
-    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_INTPEND_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
-#define DMAC_INTPEND_RESETVALUE     0x0000ul     /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
-
-#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
-#define DMAC_INTPEND_ID_Msk         (0xFul << DMAC_INTPEND_ID_Pos)
-#define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
-#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
-#define DMAC_INTPEND_TERR           (0x1ul << DMAC_INTPEND_TERR_Pos)
-#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
-#define DMAC_INTPEND_TCMPL          (0x1ul << DMAC_INTPEND_TCMPL_Pos)
-#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
-#define DMAC_INTPEND_SUSP           (0x1ul << DMAC_INTPEND_SUSP_Pos)
-#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
-#define DMAC_INTPEND_FERR           (0x1ul << DMAC_INTPEND_FERR_Pos)
-#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
-#define DMAC_INTPEND_BUSY           (0x1ul << DMAC_INTPEND_BUSY_Pos)
-#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
-#define DMAC_INTPEND_PEND           (0x1ul << DMAC_INTPEND_PEND_Pos)
-#define DMAC_INTPEND_MASK           0xE70Ful     /**< \brief (DMAC_INTPEND) MASK Register */
-
-/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
-    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
-    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
-    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
-    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
-    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
-    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
-    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
-    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
-    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
-    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
-    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t CHINT:12;         /*!< bit:  0..11  Channel x Pending Interrupt        */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
-#define DMAC_INTSTATUS_RESETVALUE   0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
-
-#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT0       (1 << DMAC_INTSTATUS_CHINT0_Pos)
-#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT1       (1 << DMAC_INTSTATUS_CHINT1_Pos)
-#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT2       (1 << DMAC_INTSTATUS_CHINT2_Pos)
-#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT3       (1 << DMAC_INTSTATUS_CHINT3_Pos)
-#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT4       (1 << DMAC_INTSTATUS_CHINT4_Pos)
-#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT5       (1 << DMAC_INTSTATUS_CHINT5_Pos)
-#define DMAC_INTSTATUS_CHINT6_Pos   6            /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT6       (1 << DMAC_INTSTATUS_CHINT6_Pos)
-#define DMAC_INTSTATUS_CHINT7_Pos   7            /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT7       (1 << DMAC_INTSTATUS_CHINT7_Pos)
-#define DMAC_INTSTATUS_CHINT8_Pos   8            /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT8       (1 << DMAC_INTSTATUS_CHINT8_Pos)
-#define DMAC_INTSTATUS_CHINT9_Pos   9            /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT9       (1 << DMAC_INTSTATUS_CHINT9_Pos)
-#define DMAC_INTSTATUS_CHINT10_Pos  10           /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT10      (1 << DMAC_INTSTATUS_CHINT10_Pos)
-#define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT11      (1 << DMAC_INTSTATUS_CHINT11_Pos)
-#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT_Msk    (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
-#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
-#define DMAC_INTSTATUS_MASK         0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
-
-/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
-    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
-    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
-    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
-    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
-    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
-    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
-    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
-    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
-    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
-    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
-    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t BUSYCH:12;        /*!< bit:  0..11  Busy Channel x                     */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_BUSYCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
-#define DMAC_BUSYCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
-
-#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
-#define DMAC_BUSYCH_BUSYCH0         (1 << DMAC_BUSYCH_BUSYCH0_Pos)
-#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
-#define DMAC_BUSYCH_BUSYCH1         (1 << DMAC_BUSYCH_BUSYCH1_Pos)
-#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
-#define DMAC_BUSYCH_BUSYCH2         (1 << DMAC_BUSYCH_BUSYCH2_Pos)
-#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
-#define DMAC_BUSYCH_BUSYCH3         (1 << DMAC_BUSYCH_BUSYCH3_Pos)
-#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
-#define DMAC_BUSYCH_BUSYCH4         (1 << DMAC_BUSYCH_BUSYCH4_Pos)
-#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
-#define DMAC_BUSYCH_BUSYCH5         (1 << DMAC_BUSYCH_BUSYCH5_Pos)
-#define DMAC_BUSYCH_BUSYCH6_Pos     6            /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
-#define DMAC_BUSYCH_BUSYCH6         (1 << DMAC_BUSYCH_BUSYCH6_Pos)
-#define DMAC_BUSYCH_BUSYCH7_Pos     7            /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
-#define DMAC_BUSYCH_BUSYCH7         (1 << DMAC_BUSYCH_BUSYCH7_Pos)
-#define DMAC_BUSYCH_BUSYCH8_Pos     8            /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
-#define DMAC_BUSYCH_BUSYCH8         (1 << DMAC_BUSYCH_BUSYCH8_Pos)
-#define DMAC_BUSYCH_BUSYCH9_Pos     9            /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
-#define DMAC_BUSYCH_BUSYCH9         (1 << DMAC_BUSYCH_BUSYCH9_Pos)
-#define DMAC_BUSYCH_BUSYCH10_Pos    10           /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
-#define DMAC_BUSYCH_BUSYCH10        (1 << DMAC_BUSYCH_BUSYCH10_Pos)
-#define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
-#define DMAC_BUSYCH_BUSYCH11        (1 << DMAC_BUSYCH_BUSYCH11_Pos)
-#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
-#define DMAC_BUSYCH_BUSYCH_Msk      (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
-#define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
-#define DMAC_BUSYCH_MASK            0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
-
-/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
-    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
-    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
-    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
-    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
-    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
-    uint32_t PENDCH6:1;        /*!< bit:      6  Pending Channel 6                  */
-    uint32_t PENDCH7:1;        /*!< bit:      7  Pending Channel 7                  */
-    uint32_t PENDCH8:1;        /*!< bit:      8  Pending Channel 8                  */
-    uint32_t PENDCH9:1;        /*!< bit:      9  Pending Channel 9                  */
-    uint32_t PENDCH10:1;       /*!< bit:     10  Pending Channel 10                 */
-    uint32_t PENDCH11:1;       /*!< bit:     11  Pending Channel 11                 */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t PENDCH:12;        /*!< bit:  0..11  Pending Channel x                  */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_PENDCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
-#define DMAC_PENDCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
-
-#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
-#define DMAC_PENDCH_PENDCH0         (1 << DMAC_PENDCH_PENDCH0_Pos)
-#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
-#define DMAC_PENDCH_PENDCH1         (1 << DMAC_PENDCH_PENDCH1_Pos)
-#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
-#define DMAC_PENDCH_PENDCH2         (1 << DMAC_PENDCH_PENDCH2_Pos)
-#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
-#define DMAC_PENDCH_PENDCH3         (1 << DMAC_PENDCH_PENDCH3_Pos)
-#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
-#define DMAC_PENDCH_PENDCH4         (1 << DMAC_PENDCH_PENDCH4_Pos)
-#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
-#define DMAC_PENDCH_PENDCH5         (1 << DMAC_PENDCH_PENDCH5_Pos)
-#define DMAC_PENDCH_PENDCH6_Pos     6            /**< \brief (DMAC_PENDCH) Pending Channel 6 */
-#define DMAC_PENDCH_PENDCH6         (1 << DMAC_PENDCH_PENDCH6_Pos)
-#define DMAC_PENDCH_PENDCH7_Pos     7            /**< \brief (DMAC_PENDCH) Pending Channel 7 */
-#define DMAC_PENDCH_PENDCH7         (1 << DMAC_PENDCH_PENDCH7_Pos)
-#define DMAC_PENDCH_PENDCH8_Pos     8            /**< \brief (DMAC_PENDCH) Pending Channel 8 */
-#define DMAC_PENDCH_PENDCH8         (1 << DMAC_PENDCH_PENDCH8_Pos)
-#define DMAC_PENDCH_PENDCH9_Pos     9            /**< \brief (DMAC_PENDCH) Pending Channel 9 */
-#define DMAC_PENDCH_PENDCH9         (1 << DMAC_PENDCH_PENDCH9_Pos)
-#define DMAC_PENDCH_PENDCH10_Pos    10           /**< \brief (DMAC_PENDCH) Pending Channel 10 */
-#define DMAC_PENDCH_PENDCH10        (1 << DMAC_PENDCH_PENDCH10_Pos)
-#define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
-#define DMAC_PENDCH_PENDCH11        (1 << DMAC_PENDCH_PENDCH11_Pos)
-#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
-#define DMAC_PENDCH_PENDCH_Msk      (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
-#define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
-#define DMAC_PENDCH_MASK            0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
-
-/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
-    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
-    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
-    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
-    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
-    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
-    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_ACTIVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
-#define DMAC_ACTIVE_RESETVALUE      0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
-
-#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX0          (1 << DMAC_ACTIVE_LVLEX0_Pos)
-#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX1          (1 << DMAC_ACTIVE_LVLEX1_Pos)
-#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX2          (1 << DMAC_ACTIVE_LVLEX2_Pos)
-#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX3          (1 << DMAC_ACTIVE_LVLEX3_Pos)
-#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX_Msk       (0xFul << DMAC_ACTIVE_LVLEX_Pos)
-#define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
-#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
-#define DMAC_ACTIVE_ID_Msk          (0x1Ful << DMAC_ACTIVE_ID_Pos)
-#define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
-#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
-#define DMAC_ACTIVE_ABUSY           (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
-#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
-#define DMAC_ACTIVE_BTCNT_Msk       (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
-#define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
-#define DMAC_ACTIVE_MASK            0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
-
-/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_BASEADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
-#define DMAC_BASEADDR_RESETVALUE    0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
-
-#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
-#define DMAC_BASEADDR_BASEADDR_Msk  (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
-#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
-#define DMAC_BASEADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
-
-/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_WRBADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
-#define DMAC_WRBADDR_RESETVALUE     0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
-
-#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
-#define DMAC_WRBADDR_WRBADDR_Msk    (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
-#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
-#define DMAC_WRBADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
-
-/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W  8) Channel ID -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ID:4;             /*!< bit:  0.. 3  Channel ID                         */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHID_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHID_OFFSET            0x3F         /**< \brief (DMAC_CHID offset) Channel ID */
-#define DMAC_CHID_RESETVALUE        0x00ul       /**< \brief (DMAC_CHID reset_value) Channel ID */
-
-#define DMAC_CHID_ID_Pos            0            /**< \brief (DMAC_CHID) Channel ID */
-#define DMAC_CHID_ID_Msk            (0xFul << DMAC_CHID_ID_Pos)
-#define DMAC_CHID_ID(value)         (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
-#define DMAC_CHID_MASK              0x0Ful       /**< \brief (DMAC_CHID) MASK Register */
-
-/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W  8) Channel Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Channel Software Reset             */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Channel Enable                     */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
-#define DMAC_CHCTRLA_RESETVALUE     0x00ul       /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
-
-#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
-#define DMAC_CHCTRLA_SWRST          (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
-#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
-#define DMAC_CHCTRLA_ENABLE         (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
-#define DMAC_CHCTRLA_MASK           0x03ul       /**< \brief (DMAC_CHCTRLA) MASK Register */
-
-/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVACT:3;          /*!< bit:  0.. 2  Event Input Action                 */
-    uint32_t EVIE:1;           /*!< bit:      3  Channel Event Input Enable         */
-    uint32_t EVOE:1;           /*!< bit:      4  Channel Event Output Enable        */
-    uint32_t LVL:2;            /*!< bit:  5.. 6  Channel Arbitration Level          */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t TRIGSRC:6;        /*!< bit:  8..13  Peripheral Trigger Source          */
-    uint32_t :8;               /*!< bit: 14..21  Reserved                           */
-    uint32_t TRIGACT:2;        /*!< bit: 22..23  Trigger Action                     */
-    uint32_t CMD:2;            /*!< bit: 24..25  Software Command                   */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_CHCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
-#define DMAC_CHCTRLB_RESETVALUE     0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
-
-#define DMAC_CHCTRLB_EVACT_Pos      0            /**< \brief (DMAC_CHCTRLB) Event Input Action */
-#define DMAC_CHCTRLB_EVACT_Msk      (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT(value)   (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
-#define   DMAC_CHCTRLB_EVACT_NOACT_Val    0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
-#define   DMAC_CHCTRLB_EVACT_TRIG_Val     0x1ul  /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
-#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    0x2ul  /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
-#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   0x3ul  /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
-#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  0x4ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define   DMAC_CHCTRLB_EVACT_RESUME_Val   0x5ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
-#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    0x6ul  /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
-#define DMAC_CHCTRLB_EVACT_NOACT    (DMAC_CHCTRLB_EVACT_NOACT_Val  << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT_TRIG     (DMAC_CHCTRLB_EVACT_TRIG_Val   << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT_CTRIG    (DMAC_CHCTRLB_EVACT_CTRIG_Val  << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT_CBLOCK   (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT_SUSPEND  (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT_RESUME   (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVACT_SSKIP    (DMAC_CHCTRLB_EVACT_SSKIP_Val  << DMAC_CHCTRLB_EVACT_Pos)
-#define DMAC_CHCTRLB_EVIE_Pos       3            /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
-#define DMAC_CHCTRLB_EVIE           (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
-#define DMAC_CHCTRLB_EVOE_Pos       4            /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
-#define DMAC_CHCTRLB_EVOE           (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
-#define DMAC_CHCTRLB_LVL_Pos        5            /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
-#define DMAC_CHCTRLB_LVL_Msk        (0x3ul << DMAC_CHCTRLB_LVL_Pos)
-#define DMAC_CHCTRLB_LVL(value)     (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
-#define   DMAC_CHCTRLB_LVL_LVL0_Val       0x0ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
-#define   DMAC_CHCTRLB_LVL_LVL1_Val       0x1ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
-#define   DMAC_CHCTRLB_LVL_LVL2_Val       0x2ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
-#define   DMAC_CHCTRLB_LVL_LVL3_Val       0x3ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
-#define DMAC_CHCTRLB_LVL_LVL0       (DMAC_CHCTRLB_LVL_LVL0_Val     << DMAC_CHCTRLB_LVL_Pos)
-#define DMAC_CHCTRLB_LVL_LVL1       (DMAC_CHCTRLB_LVL_LVL1_Val     << DMAC_CHCTRLB_LVL_Pos)
-#define DMAC_CHCTRLB_LVL_LVL2       (DMAC_CHCTRLB_LVL_LVL2_Val     << DMAC_CHCTRLB_LVL_Pos)
-#define DMAC_CHCTRLB_LVL_LVL3       (DMAC_CHCTRLB_LVL_LVL3_Val     << DMAC_CHCTRLB_LVL_Pos)
-#define DMAC_CHCTRLB_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
-#define DMAC_CHCTRLB_TRIGSRC_Msk    (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
-#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
-#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul  /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
-#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
-#define DMAC_CHCTRLB_TRIGACT_Pos    22           /**< \brief (DMAC_CHCTRLB) Trigger Action */
-#define DMAC_CHCTRLB_TRIGACT_Msk    (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
-#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
-#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  0x0ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
-#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   0x2ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
-#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
-#define DMAC_CHCTRLB_TRIGACT_BLOCK  (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
-#define DMAC_CHCTRLB_TRIGACT_BEAT   (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
-#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
-#define DMAC_CHCTRLB_CMD_Pos        24           /**< \brief (DMAC_CHCTRLB) Software Command */
-#define DMAC_CHCTRLB_CMD_Msk        (0x3ul << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
-#define   DMAC_CHCTRLB_CMD_NOACT_Val      0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
-#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    0x1ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define   DMAC_CHCTRLB_CMD_RESUME_Val     0x2ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
-#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_MASK           0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
-
-/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) Channel Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
-    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
-    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
-#define DMAC_CHINTENCLR_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
-
-#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
-#define DMAC_CHINTENCLR_TERR        (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
-#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENCLR_TCMPL       (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
-#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENCLR_SUSP        (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
-#define DMAC_CHINTENCLR_MASK        0x07ul       /**< \brief (DMAC_CHINTENCLR) MASK Register */
-
-/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) Channel Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
-    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
-    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
-#define DMAC_CHINTENSET_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
-
-#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
-#define DMAC_CHINTENSET_TERR        (0x1ul << DMAC_CHINTENSET_TERR_Pos)
-#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENSET_TCMPL       (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
-#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENSET_SUSP        (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
-#define DMAC_CHINTENSET_MASK        0x07ul       /**< \brief (DMAC_CHINTENSET) MASK Register */
-
-/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  TERR:1;           /*!< bit:      0  Transfer Error                     */
-    __I uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete                  */
-    __I uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
-    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
-#define DMAC_CHINTFLAG_RESETVALUE   0x00ul       /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
-
-#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Transfer Error */
-#define DMAC_CHINTFLAG_TERR         (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
-#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
-#define DMAC_CHINTFLAG_TCMPL        (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
-#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
-#define DMAC_CHINTFLAG_SUSP         (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
-#define DMAC_CHINTFLAG_MASK         0x07ul       /**< \brief (DMAC_CHINTFLAG) MASK Register */
-
-/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/   8) Channel Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
-    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
-    uint8_t  FERR:1;           /*!< bit:      2  Fetch Error                        */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel Status */
-#define DMAC_CHSTATUS_RESETVALUE    0x00ul       /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
-
-#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
-#define DMAC_CHSTATUS_PEND          (0x1ul << DMAC_CHSTATUS_PEND_Pos)
-#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
-#define DMAC_CHSTATUS_BUSY          (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
-#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Fetch Error */
-#define DMAC_CHSTATUS_FERR          (0x1ul << DMAC_CHSTATUS_FERR_Pos)
-#define DMAC_CHSTATUS_MASK          0x07ul       /**< \brief (DMAC_CHSTATUS) MASK Register */
-
-/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
-    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Event Output Selection             */
-    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
-    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
-    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
-    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
-    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_BTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
-#define DMAC_BTCTRL_RESETVALUE      0x0000ul     /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
-
-#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
-#define DMAC_BTCTRL_VALID           (0x1ul << DMAC_BTCTRL_VALID_Pos)
-#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Event Output Selection */
-#define DMAC_BTCTRL_EVOSEL_Msk      (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
-#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  0x0ul  /**< \brief (DMAC_BTCTRL) Event generation disabled */
-#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
-#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
-#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BEAT     (DMAC_BTCTRL_EVOSEL_BEAT_Val   << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
-#define DMAC_BTCTRL_BLOCKACT_Msk    (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
-#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  0x0ul  /**< \brief (DMAC_BTCTRL) No action */
-#define   DMAC_BTCTRL_BLOCKACT_INT_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
-#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul  /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
-#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   0x3ul  /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
-#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
-#define DMAC_BTCTRL_BEATSIZE_Msk    (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
-#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   0x0ul  /**< \brief (DMAC_BTCTRL) 8-bit access */
-#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  0x1ul  /**< \brief (DMAC_BTCTRL) 16-bit access */
-#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   0x2ul  /**< \brief (DMAC_BTCTRL) 32-bit access */
-#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
-#define DMAC_BTCTRL_SRCINC          (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
-#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
-#define DMAC_BTCTRL_DSTINC          (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
-#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
-#define DMAC_BTCTRL_STEPSEL         (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
-#define   DMAC_BTCTRL_STEPSEL_DST_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
-#define   DMAC_BTCTRL_STEPSEL_SRC_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
-#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
-#define DMAC_BTCTRL_STEPSIZE_Msk    (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
-#define   DMAC_BTCTRL_STEPSIZE_X1_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
-#define   DMAC_BTCTRL_STEPSIZE_X2_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
-#define   DMAC_BTCTRL_STEPSIZE_X4_Val     0x2ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
-#define   DMAC_BTCTRL_STEPSIZE_X8_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
-#define   DMAC_BTCTRL_STEPSIZE_X16_Val    0x4ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
-#define   DMAC_BTCTRL_STEPSIZE_X32_Val    0x5ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
-#define   DMAC_BTCTRL_STEPSIZE_X64_Val    0x6ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
-#define   DMAC_BTCTRL_STEPSIZE_X128_Val   0x7ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
-#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_MASK            0xFF1Ful     /**< \brief (DMAC_BTCTRL) MASK Register */
-
-/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_BTCNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
-
-#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
-#define DMAC_BTCNT_BTCNT_Msk        (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
-#define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
-#define DMAC_BTCNT_MASK             0xFFFFul     /**< \brief (DMAC_BTCNT) MASK Register */
-
-/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_SRCADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
-
-#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
-#define DMAC_SRCADDR_SRCADDR_Msk    (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
-#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
-#define DMAC_SRCADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
-
-/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_DSTADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
-
-#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
-#define DMAC_DSTADDR_DSTADDR_Msk    (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
-#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
-#define DMAC_DSTADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
-
-/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_DESCADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
-
-#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
-#define DMAC_DESCADDR_DESCADDR_Msk  (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
-#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
-#define DMAC_DESCADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
-
-/** \brief DMAC APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
-  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
-  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
-  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
-  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
-  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
-  __IO DMAC_QOSCTRL_Type         QOSCTRL;     /**< \brief Offset: 0x0E (R/W  8) QOS Control */
-       RoReg8                    Reserved1[0x1];
-  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
-  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
-       RoReg8                    Reserved2[0x8];
-  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
-       RoReg8                    Reserved3[0x2];
-  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
-  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
-  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
-  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
-  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
-  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
-       RoReg8                    Reserved4[0x3];
-  __IO DMAC_CHID_Type            CHID;        /**< \brief Offset: 0x3F (R/W  8) Channel ID */
-  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x40 (R/W  8) Channel Control A */
-       RoReg8                    Reserved5[0x3];
-  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
-       RoReg8                    Reserved6[0x4];
-  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x4C (R/W  8) Channel Interrupt Enable Clear */
-  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x4D (R/W  8) Channel Interrupt Enable Set */
-  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x4E (R/W  8) Channel Interrupt Flag Status and Clear */
-  __I  DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x4F (R/   8) Channel Status */
-} Dmac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief DMAC Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
-  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
-  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
-  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
-  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
-} DmacDescriptor
-#ifdef __GNUC__
-  __attribute__ ((aligned (8)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_DMAC_DESCRIPTOR
-
-/*@}*/
-
-#endif /* _SAMD21_DMAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC                    0x110
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
+    uint16_t CRCENABLE:1;      /*!< bit:      2  CRC Enable                         */
+    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
+    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
+    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
+    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE        0x0000ul     /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST             (0x1ul << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE         (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos     2            /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE         (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0            (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1            (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2            (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3            (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk         (0xFul << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK              0x0F07ul     /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
+    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE     0x0000ul     /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul  /**< \brief (DMAC_CRCCTRL) Byte bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul  /**< \brief (DMAC_CRCCTRL) Half-word bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul  /**< \brief (DMAC_CRCCTRL) Word bus access */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk    (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  0x0ul  /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  0x1ul  /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk     (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   0x0ul  /**< \brief (DMAC_CRCCTRL) No action */
+#define   DMAC_CRCCTRL_CRCSRC_IO_Val      0x1ul  /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT   (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK           0x3F0Ful     /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
+    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE   0x00ul       /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY      (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO      (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK         0x03ul       /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE     0x00ul       /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN         (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK           0x01ul       /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W  8) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WRBQOS:2;         /*!< bit:  0.. 1  Write-Back Quality of Service      */
+    uint8_t  FQOS:2;           /*!< bit:  2.. 3  Fetch Quality of Service           */
+    uint8_t  DQOS:2;           /*!< bit:  4.. 5  Data Transfer Quality of Service   */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_QOSCTRL_OFFSET         0x0E         /**< \brief (DMAC_QOSCTRL offset) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE     0x15ul       /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos     0            /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
+#define DMAC_QOSCTRL_WRBQOS_Msk     (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS(value)  (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
+#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_WRBQOS_LOW_Val     0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val  0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val    0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_LOW     (DMAC_QOSCTRL_WRBQOS_LOW_Val   << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM  (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_HIGH    (DMAC_QOSCTRL_WRBQOS_HIGH_Val  << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Pos       2            /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
+#define DMAC_QOSCTRL_FQOS_Msk       (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS(value)    (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
+#define   DMAC_QOSCTRL_FQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_FQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_FQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_FQOS_DISABLE   (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_LOW       (DMAC_QOSCTRL_FQOS_LOW_Val     << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_MEDIUM    (DMAC_QOSCTRL_FQOS_MEDIUM_Val  << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_HIGH      (DMAC_QOSCTRL_FQOS_HIGH_Val    << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Pos       4            /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
+#define DMAC_QOSCTRL_DQOS_Msk       (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS(value)    (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
+#define   DMAC_QOSCTRL_DQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_DQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_DQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_DQOS_DISABLE   (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_LOW       (DMAC_QOSCTRL_DQOS_LOW_Val     << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_MEDIUM    (DMAC_QOSCTRL_DQOS_MEDIUM_Val  << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_HIGH      (DMAC_QOSCTRL_DQOS_HIGH_Val    << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_MASK           0x3Ful       /**< \brief (DMAC_QOSCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
+    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
+    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
+    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
+    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
+    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
+    uint32_t SWTRIG6:1;        /*!< bit:      6  Channel 6 Software Trigger         */
+    uint32_t SWTRIG7:1;        /*!< bit:      7  Channel 7 Software Trigger         */
+    uint32_t SWTRIG8:1;        /*!< bit:      8  Channel 8 Software Trigger         */
+    uint32_t SWTRIG9:1;        /*!< bit:      9  Channel 9 Software Trigger         */
+    uint32_t SWTRIG10:1;       /*!< bit:     10  Channel 10 Software Trigger        */
+    uint32_t SWTRIG11:1;       /*!< bit:     11  Channel 11 Software Trigger        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t SWTRIG:12;        /*!< bit:  0..11  Channel x Software Trigger         */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE  0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0     (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1     (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2     (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3     (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4     (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5     (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6            /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6     (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7            /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7     (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8            /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8     (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9            /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9     (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10           /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10    (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11    (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK        0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLPRI0:4;        /*!< bit:  0.. 3  Level 0 Channel Priority Number    */
+    uint32_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI1:4;        /*!< bit:  8..11  Level 1 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI2:4;        /*!< bit: 16..19  Level 2 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 20..22  Reserved                           */
+    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI3:4;        /*!< bit: 24..27  Level 3 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 28..30  Reserved                           */
+    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE    0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0      (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1      (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2      (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3      (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK          0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
+    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
+    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
+    uint16_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
+    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
+    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE     0x0000ul     /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk         (0xFul << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR           (0x1ul << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL          (0x1ul << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP           (0x1ul << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR           (0x1ul << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY           (0x1ul << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND           (0x1ul << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK           0xE70Ful     /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
+    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
+    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
+    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
+    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
+    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
+    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
+    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
+    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
+    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
+    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
+    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHINT:12;         /*!< bit:  0..11  Channel x Pending Interrupt        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE   0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0       (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1       (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2       (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3       (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4       (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5       (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos   6            /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6       (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos   7            /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7       (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos   8            /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8       (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos   9            /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9       (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos  10           /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10      (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11      (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk    (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK         0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
+    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
+    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
+    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
+    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
+    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
+    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
+    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
+    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
+    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
+    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
+    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t BUSYCH:12;        /*!< bit:  0..11  Busy Channel x                     */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0         (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1         (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2         (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3         (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4         (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5         (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos     6            /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6         (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos     7            /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7         (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos     8            /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8         (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos     9            /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9         (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos    10           /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10        (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11        (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk      (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK            0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
+    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
+    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
+    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
+    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
+    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
+    uint32_t PENDCH6:1;        /*!< bit:      6  Pending Channel 6                  */
+    uint32_t PENDCH7:1;        /*!< bit:      7  Pending Channel 7                  */
+    uint32_t PENDCH8:1;        /*!< bit:      8  Pending Channel 8                  */
+    uint32_t PENDCH9:1;        /*!< bit:      9  Pending Channel 9                  */
+    uint32_t PENDCH10:1;       /*!< bit:     10  Pending Channel 10                 */
+    uint32_t PENDCH11:1;       /*!< bit:     11  Pending Channel 11                 */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PENDCH:12;        /*!< bit:  0..11  Pending Channel x                  */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0         (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1         (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2         (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3         (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4         (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5         (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos     6            /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6         (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos     7            /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7         (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos     8            /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8         (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos     9            /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9         (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos    10           /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10        (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11        (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk      (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK            0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
+    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
+    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
+    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
+    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE      0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0          (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1          (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2          (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3          (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk       (0xFul << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk          (0x1Ful << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY           (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk       (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK            0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE    0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk  (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE     0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk    (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W  8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET            0x3F         /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE        0x00ul       /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos            0            /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk            (0xFul << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value)         (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
+#define DMAC_CHID_MASK              0x0Ful       /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W  8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Channel Software Reset             */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Channel Enable                     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE     0x00ul       /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST          (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE         (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK           0x03ul       /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT:3;          /*!< bit:  0.. 2  Event Input Action                 */
+    uint32_t EVIE:1;           /*!< bit:      3  Channel Event Input Enable         */
+    uint32_t EVOE:1;           /*!< bit:      4  Channel Event Output Enable        */
+    uint32_t LVL:2;            /*!< bit:  5.. 6  Channel Arbitration Level          */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t TRIGSRC:6;        /*!< bit:  8..13  Peripheral Trigger Source          */
+    uint32_t :8;               /*!< bit: 14..21  Reserved                           */
+    uint32_t TRIGACT:2;        /*!< bit: 22..23  Trigger Action                     */
+    uint32_t CMD:2;            /*!< bit: 24..25  Software Command                   */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE     0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos      0            /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk      (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value)   (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
+#define   DMAC_CHCTRLB_EVACT_NOACT_Val    0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_EVACT_TRIG_Val     0x1ul  /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    0x2ul  /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   0x3ul  /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  0x4ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_EVACT_RESUME_Val   0x5ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    0x6ul  /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT    (DMAC_CHCTRLB_EVACT_NOACT_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG     (DMAC_CHCTRLB_EVACT_TRIG_Val   << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG    (DMAC_CHCTRLB_EVACT_CTRIG_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK   (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND  (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME   (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP    (DMAC_CHCTRLB_EVACT_SSKIP_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos       3            /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE           (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos       4            /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE           (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos        5            /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk        (0x3ul << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value)     (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
+#define   DMAC_CHCTRLB_LVL_LVL0_Val       0x0ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define   DMAC_CHCTRLB_LVL_LVL1_Val       0x1ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define   DMAC_CHCTRLB_LVL_LVL2_Val       0x2ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define   DMAC_CHCTRLB_LVL_LVL3_Val       0x3ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0       (DMAC_CHCTRLB_LVL_LVL0_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1       (DMAC_CHCTRLB_LVL_LVL1_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2       (DMAC_CHCTRLB_LVL_LVL2_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3       (DMAC_CHCTRLB_LVL_LVL3_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk    (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
+#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul  /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos    22           /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk    (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
+#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  0x0ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   0x2ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK  (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT   (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos        24           /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk        (0x3ul << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define   DMAC_CHCTRLB_CMD_NOACT_Val      0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    0x1ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_CMD_RESUME_Val     0x2ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK           0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR        (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL       (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP        (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK        0x07ul       /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR        (0x1ul << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL       (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP        (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK        0x07ul       /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TERR:1;           /*!< bit:      0  Transfer Error                     */
+    __I uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete                  */
+    __I uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE   0x00ul       /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Transfer Error */
+#define DMAC_CHINTFLAG_TERR         (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL        (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP         (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK         0x07ul       /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/   8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
+    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
+    uint8_t  FERR:1;           /*!< bit:      2  Fetch Error                        */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE    0x00ul       /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND          (0x1ul << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY          (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Fetch Error */
+#define DMAC_CHSTATUS_FERR          (0x1ul << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK          0x07ul       /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
+    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Event Output Selection             */
+    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
+    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
+    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
+    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
+    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE      0x0000ul     /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID           (0x1ul << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk      (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  0x0ul  /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT     (DMAC_BTCTRL_EVOSEL_BEAT_Val   << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk    (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  0x0ul  /**< \brief (DMAC_BTCTRL) No action */
+#define   DMAC_BTCTRL_BLOCKACT_INT_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
+#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul  /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   0x3ul  /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk    (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   0x0ul  /**< \brief (DMAC_BTCTRL) 8-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  0x1ul  /**< \brief (DMAC_BTCTRL) 16-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   0x2ul  /**< \brief (DMAC_BTCTRL) 32-bit access */
+#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC          (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC          (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL         (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
+#define   DMAC_BTCTRL_STEPSEL_DST_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define   DMAC_BTCTRL_STEPSEL_SRC_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk    (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define   DMAC_BTCTRL_STEPSIZE_X1_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
+#define   DMAC_BTCTRL_STEPSIZE_X2_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
+#define   DMAC_BTCTRL_STEPSIZE_X4_Val     0x2ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
+#define   DMAC_BTCTRL_STEPSIZE_X8_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
+#define   DMAC_BTCTRL_STEPSIZE_X16_Val    0x4ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
+#define   DMAC_BTCTRL_STEPSIZE_X32_Val    0x5ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
+#define   DMAC_BTCTRL_STEPSIZE_X64_Val    0x6ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
+#define   DMAC_BTCTRL_STEPSIZE_X128_Val   0x7ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK            0xFF1Ful     /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk        (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK             0xFFFFul     /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk    (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
+
+#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk    (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk  (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
+  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
+  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
+  __IO DMAC_QOSCTRL_Type         QOSCTRL;     /**< \brief Offset: 0x0E (R/W  8) QOS Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+       RoReg8                    Reserved2[0x8];
+  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+       RoReg8                    Reserved3[0x2];
+  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
+  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
+  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
+  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
+  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+       RoReg8                    Reserved4[0x3];
+  __IO DMAC_CHID_Type            CHID;        /**< \brief Offset: 0x3F (R/W  8) Channel ID */
+  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x40 (R/W  8) Channel Control A */
+       RoReg8                    Reserved5[0x3];
+  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+       RoReg8                    Reserved6[0x4];
+  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x4C (R/W  8) Channel Interrupt Enable Clear */
+  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x4D (R/W  8) Channel Interrupt Enable Set */
+  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x4E (R/W  8) Channel Interrupt Flag Status and Clear */
+  __I  DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x4F (R/   8) Channel Status */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
+  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
+  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+  __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_DMAC_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAMD21_DMAC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h
index fc57afe..beaf8d0 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h
@@ -1,541 +1,541 @@
-/**
- * \file
- *
- * \brief Component description for DSU
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_DSU_COMPONENT_
-#define _SAMD21_DSU_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR DSU */
-/* ========================================================================== */
-/** \addtogroup SAMD21_DSU Device Service Unit */
-/*@{*/
-
-#define DSU_U2209
-#define REV_DSU                     0x203
-
-/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Check     */
-    uint8_t  MBIST:1;          /*!< bit:      3  Memory Built-In Self-Test          */
-    uint8_t  CE:1;             /*!< bit:      4  Chip Erase                         */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DSU_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
-#define DSU_CTRL_RESETVALUE         0x00ul       /**< \brief (DSU_CTRL reset_value) Control */
-
-#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
-#define DSU_CTRL_SWRST              (0x1ul << DSU_CTRL_SWRST_Pos)
-#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
-#define DSU_CTRL_CRC                (0x1ul << DSU_CTRL_CRC_Pos)
-#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
-#define DSU_CTRL_MBIST              (0x1ul << DSU_CTRL_MBIST_Pos)
-#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip Erase */
-#define DSU_CTRL_CE                 (0x1ul << DSU_CTRL_CE_Pos)
-#define DSU_CTRL_MASK               0x1Dul       /**< \brief (DSU_CTRL) MASK Register */
-
-/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
-    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
-    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
-    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
-    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DSU_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
-#define DSU_STATUSA_RESETVALUE      0x00ul       /**< \brief (DSU_STATUSA reset_value) Status A */
-
-#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
-#define DSU_STATUSA_DONE            (0x1ul << DSU_STATUSA_DONE_Pos)
-#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
-#define DSU_STATUSA_CRSTEXT         (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
-#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
-#define DSU_STATUSA_BERR            (0x1ul << DSU_STATUSA_BERR_Pos)
-#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
-#define DSU_STATUSA_FAIL            (0x1ul << DSU_STATUSA_FAIL_Pos)
-#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
-#define DSU_STATUSA_PERR            (0x1ul << DSU_STATUSA_PERR_Pos)
-#define DSU_STATUSA_MASK            0x1Ful       /**< \brief (DSU_STATUSA) MASK Register */
-
-/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
-    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
-    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
-    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
-    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DSU_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
-#define DSU_STATUSB_RESETVALUE      0x10ul       /**< \brief (DSU_STATUSB reset_value) Status B */
-
-#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
-#define DSU_STATUSB_PROT            (0x1ul << DSU_STATUSB_PROT_Pos)
-#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
-#define DSU_STATUSB_DBGPRES         (0x1ul << DSU_STATUSB_DBGPRES_Pos)
-#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
-#define DSU_STATUSB_DCCD0           (1 << DSU_STATUSB_DCCD0_Pos)
-#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
-#define DSU_STATUSB_DCCD1           (1 << DSU_STATUSB_DCCD1_Pos)
-#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
-#define DSU_STATUSB_DCCD_Msk        (0x3ul << DSU_STATUSB_DCCD_Pos)
-#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
-#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
-#define DSU_STATUSB_HPE             (0x1ul << DSU_STATUSB_HPE_Pos)
-#define DSU_STATUSB_MASK            0x1Ful       /**< \brief (DSU_STATUSB) MASK Register */
-
-/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
-#define DSU_ADDR_RESETVALUE         0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
-
-#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
-#define DSU_ADDR_ADDR_Msk           (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
-#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
-#define DSU_ADDR_MASK               0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
-
-/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
-#define DSU_LENGTH_RESETVALUE       0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
-
-#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
-#define DSU_LENGTH_LENGTH_Msk       (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
-#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
-#define DSU_LENGTH_MASK             0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
-
-/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
-#define DSU_DATA_RESETVALUE         0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
-
-#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
-#define DSU_DATA_DATA_Msk           (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
-#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
-#define DSU_DATA_MASK               0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
-
-/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
-#define DSU_DCC_RESETVALUE          0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
-
-#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
-#define DSU_DCC_DATA_Msk            (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
-#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
-#define DSU_DCC_MASK                0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
-
-/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
-    uint32_t REVISION:4;       /*!< bit:  8..11  Revision                           */
-    uint32_t DIE:4;            /*!< bit: 12..15  Die Identification                 */
-    uint32_t SERIES:6;         /*!< bit: 16..21  Product Series                     */
-    uint32_t :1;               /*!< bit:     22  Reserved                           */
-    uint32_t FAMILY:5;         /*!< bit: 23..27  Product Family                     */
-    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DID_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
-
-#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
-#define DSU_DID_DEVSEL_Msk          (0xFFul << DSU_DID_DEVSEL_Pos)
-#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
-#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision */
-#define DSU_DID_REVISION_Msk        (0xFul << DSU_DID_REVISION_Pos)
-#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
-#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Identification */
-#define DSU_DID_DIE_Msk             (0xFul << DSU_DID_DIE_Pos)
-#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
-#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Product Series */
-#define DSU_DID_SERIES_Msk          (0x3Ful << DSU_DID_SERIES_Pos)
-#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
-#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Product Family */
-#define DSU_DID_FAMILY_Msk          (0x1Ful << DSU_DID_FAMILY_Pos)
-#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
-#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
-#define DSU_DID_PROCESSOR_Msk       (0xFul << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
-#define DSU_DID_MASK                0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
-
-/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
-    uint32_t FMT:1;            /*!< bit:      1  Format                             */
-    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
-    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_ENTRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_ENTRY_OFFSET            0x1000       /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
-#define DSU_ENTRY_RESETVALUE        0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
-
-#define DSU_ENTRY_EPRES_Pos         0            /**< \brief (DSU_ENTRY) Entry Present */
-#define DSU_ENTRY_EPRES             (0x1ul << DSU_ENTRY_EPRES_Pos)
-#define DSU_ENTRY_FMT_Pos           1            /**< \brief (DSU_ENTRY) Format */
-#define DSU_ENTRY_FMT               (0x1ul << DSU_ENTRY_FMT_Pos)
-#define DSU_ENTRY_ADDOFF_Pos        12           /**< \brief (DSU_ENTRY) Address Offset */
-#define DSU_ENTRY_ADDOFF_Msk        (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
-#define DSU_ENTRY_ADDOFF(value)     (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
-#define DSU_ENTRY_MASK              0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
-
-/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_END_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
-#define DSU_END_RESETVALUE          0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
-
-#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
-#define DSU_END_END_Msk             (0xFFFFFFFFul << DSU_END_END_Pos)
-#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
-#define DSU_END_MASK                0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
-
-/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MEMTYPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
-#define DSU_MEMTYPE_RESETVALUE      0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
-
-#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
-#define DSU_MEMTYPE_SMEMP           (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
-#define DSU_MEMTYPE_MASK            0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
-
-/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
-    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB Count                          */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID4_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
-#define DSU_PID4_RESETVALUE         0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
-
-#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
-#define DSU_PID4_JEPCC_Msk          (0xFul << DSU_PID4_JEPCC_Pos)
-#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
-#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB Count */
-#define DSU_PID4_FKBC_Msk           (0xFul << DSU_PID4_FKBC_Pos)
-#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
-#define DSU_PID4_MASK               0x000000FFul /**< \brief (DSU_PID4) MASK Register */
-
-/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
-#define DSU_PID0_RESETVALUE         0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
-
-#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
-#define DSU_PID0_PARTNBL_Msk        (0xFFul << DSU_PID0_PARTNBL_Pos)
-#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
-#define DSU_PID0_MASK               0x000000FFul /**< \brief (DSU_PID0) MASK Register */
-
-/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
-    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
-#define DSU_PID1_RESETVALUE         0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
-
-#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
-#define DSU_PID1_PARTNBH_Msk        (0xFul << DSU_PID1_PARTNBH_Pos)
-#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
-#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
-#define DSU_PID1_JEPIDCL_Msk        (0xFul << DSU_PID1_JEPIDCL_Pos)
-#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
-#define DSU_PID1_MASK               0x000000FFul /**< \brief (DSU_PID1) MASK Register */
-
-/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
-    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
-    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
-#define DSU_PID2_RESETVALUE         0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
-
-#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
-#define DSU_PID2_JEPIDCH_Msk        (0x7ul << DSU_PID2_JEPIDCH_Pos)
-#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
-#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
-#define DSU_PID2_JEPU               (0x1ul << DSU_PID2_JEPU_Pos)
-#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
-#define DSU_PID2_REVISION_Msk       (0xFul << DSU_PID2_REVISION_Pos)
-#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
-#define DSU_PID2_MASK               0x000000FFul /**< \brief (DSU_PID2) MASK Register */
-
-/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
-    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
-#define DSU_PID3_RESETVALUE         0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
-
-#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
-#define DSU_PID3_CUSMOD_Msk         (0xFul << DSU_PID3_CUSMOD_Pos)
-#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
-#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
-#define DSU_PID3_REVAND_Msk         (0xFul << DSU_PID3_REVAND_Pos)
-#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
-#define DSU_PID3_MASK               0x000000FFul /**< \brief (DSU_PID3) MASK Register */
-
-/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
-#define DSU_CID0_RESETVALUE         0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
-
-#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
-#define DSU_CID0_PREAMBLEB0_Msk     (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
-#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
-#define DSU_CID0_MASK               0x000000FFul /**< \brief (DSU_CID0) MASK Register */
-
-/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
-    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
-#define DSU_CID1_RESETVALUE         0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
-
-#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
-#define DSU_CID1_PREAMBLE_Msk       (0xFul << DSU_CID1_PREAMBLE_Pos)
-#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
-#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
-#define DSU_CID1_CCLASS_Msk         (0xFul << DSU_CID1_CCLASS_Pos)
-#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
-#define DSU_CID1_MASK               0x000000FFul /**< \brief (DSU_CID1) MASK Register */
-
-/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
-#define DSU_CID2_RESETVALUE         0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
-
-#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
-#define DSU_CID2_PREAMBLEB2_Msk     (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
-#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
-#define DSU_CID2_MASK               0x000000FFul /**< \brief (DSU_CID2) MASK Register */
-
-/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
-#define DSU_CID3_RESETVALUE         0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
-
-#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
-#define DSU_CID3_PREAMBLEB3_Msk     (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
-#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
-#define DSU_CID3_MASK               0x000000FFul /**< \brief (DSU_CID3) MASK Register */
-
-/** \brief DSU hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
-  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
-  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
-       RoReg8                    Reserved1[0x1];
-  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
-  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
-  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
-  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
-  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
-       RoReg8                    Reserved2[0xFE4];
-  __I  DSU_ENTRY_Type            ENTRY[2];    /**< \brief Offset: 0x1000 (R/  32) Coresight ROM Table Entry n */
-  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) Coresight ROM Table End */
-       RoReg8                    Reserved3[0xFC0];
-  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) Coresight ROM Table Memory Type */
-  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
-       RoReg8                    Reserved4[0xC];
-  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
-  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
-  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
-  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
-  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
-  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
-  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
-  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
-} Dsu;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_DSU_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_COMPONENT_
+#define _SAMD21_DSU_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU                     0x203
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Check     */
+    uint8_t  MBIST:1;          /*!< bit:      3  Memory Built-In Self-Test          */
+    uint8_t  CE:1;             /*!< bit:      4  Chip Erase                         */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE         0x00ul       /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST              (0x1ul << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
+#define DSU_CTRL_CRC                (0x1ul << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
+#define DSU_CTRL_MBIST              (0x1ul << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip Erase */
+#define DSU_CTRL_CE                 (0x1ul << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK               0x1Dul       /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
+    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
+    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
+    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
+    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE      0x00ul       /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE            (0x1ul << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT         (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR            (0x1ul << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL            (0x1ul << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR            (0x1ul << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            0x1Ful       /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
+    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
+    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
+    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
+    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE      0x10ul       /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT            (0x1ul << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES         (0x1ul << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0           (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1           (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk        (0x3ul << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE             (0x1ul << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK            0x1Ful       /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE         0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk           (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK               0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE       0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk       (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK             0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE         0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk           (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK               0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk            (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK                0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
+    uint32_t REVISION:4;       /*!< bit:  8..11  Revision                           */
+    uint32_t DIE:4;            /*!< bit: 12..15  Die Identification                 */
+    uint32_t SERIES:6;         /*!< bit: 16..21  Product Series                     */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t FAMILY:5;         /*!< bit: 23..27  Product Family                     */
+    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk          (0xFFul << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision */
+#define DSU_DID_REVISION_Msk        (0xFul << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Identification */
+#define DSU_DID_DIE_Msk             (0xFul << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Product Series */
+#define DSU_DID_SERIES_Msk          (0x3Ful << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Product Family */
+#define DSU_DID_FAMILY_Msk          (0x1Ful << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk       (0xFul << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define DSU_DID_MASK                0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
+    uint32_t FMT:1;            /*!< bit:      1  Format                             */
+    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
+    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET            0x1000       /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE        0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos         0            /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES             (0x1ul << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos           1            /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT               (0x1ul << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos        12           /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk        (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value)     (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
+#define DSU_ENTRY_MASK              0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE          0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk             (0xFFFFFFFFul << DSU_END_END_Pos)
+#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK                0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP           (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
+    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB Count                          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk          (0xFul << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB Count */
+#define DSU_PID4_FKBC_Msk           (0xFul << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK               0x000000FFul /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk        (0xFFul << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK               0x000000FFul /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
+    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk        (0xFul << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk        (0xFul << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK               0x000000FFul /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
+    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
+    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk        (0x7ul << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU               (0x1ul << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk       (0xFul << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK               0x000000FFul /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
+    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk         (0xFul << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk         (0xFul << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK               0x000000FFul /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk     (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK               0x000000FFul /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
+    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk       (0xFul << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk         (0xFul << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK               0x000000FFul /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk     (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK               0x000000FFul /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk     (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK               0x000000FFul /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
+  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
+  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
+       RoReg8                    Reserved1[0x1];
+  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
+  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
+  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
+  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
+       RoReg8                    Reserved2[0xFE4];
+  __I  DSU_ENTRY_Type            ENTRY[2];    /**< \brief Offset: 0x1000 (R/  32) Coresight ROM Table Entry n */
+  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) Coresight ROM Table End */
+       RoReg8                    Reserved3[0xFC0];
+  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) Coresight ROM Table Memory Type */
+  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
+       RoReg8                    Reserved4[0xC];
+  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
+  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
+  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
+  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
+  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
+  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
+  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
+  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DSU_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h
index fe6ab9c..46bbae3 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h
@@ -1,671 +1,671 @@
-/**
- * \file
- *
- * \brief Component description for EIC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_EIC_COMPONENT_
-#define _SAMD21_EIC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR EIC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_EIC External Interrupt Controller */
-/*@{*/
-
-#define EIC_U2217
-#define REV_EIC                     0x101
-
-/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EIC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_CTRL_OFFSET             0x00         /**< \brief (EIC_CTRL offset) Control */
-#define EIC_CTRL_RESETVALUE         0x00ul       /**< \brief (EIC_CTRL reset_value) Control */
-
-#define EIC_CTRL_SWRST_Pos          0            /**< \brief (EIC_CTRL) Software Reset */
-#define EIC_CTRL_SWRST              (0x1ul << EIC_CTRL_SWRST_Pos)
-#define EIC_CTRL_ENABLE_Pos         1            /**< \brief (EIC_CTRL) Enable */
-#define EIC_CTRL_ENABLE             (0x1ul << EIC_CTRL_ENABLE_Pos)
-#define EIC_CTRL_MASK               0x03ul       /**< \brief (EIC_CTRL) MASK Register */
-
-/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EIC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_STATUS_OFFSET           0x01         /**< \brief (EIC_STATUS offset) Status */
-#define EIC_STATUS_RESETVALUE       0x00ul       /**< \brief (EIC_STATUS reset_value) Status */
-
-#define EIC_STATUS_SYNCBUSY_Pos     7            /**< \brief (EIC_STATUS) Synchronization Busy */
-#define EIC_STATUS_SYNCBUSY         (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
-#define EIC_STATUS_MASK             0x80ul       /**< \brief (EIC_STATUS) MASK Register */
-
-/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W  8) Non-Maskable Interrupt Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense       */
-    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EIC_NMICTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_NMICTRL_OFFSET          0x02         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
-#define EIC_NMICTRL_RESETVALUE      0x00ul       /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
-
-#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
-#define EIC_NMICTRL_NMISENSE_Msk    (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
-#define   EIC_NMICTRL_NMISENSE_NONE_Val   0x0ul  /**< \brief (EIC_NMICTRL) No detection */
-#define   EIC_NMICTRL_NMISENSE_RISE_Val   0x1ul  /**< \brief (EIC_NMICTRL) Rising-edge detection */
-#define   EIC_NMICTRL_NMISENSE_FALL_Val   0x2ul  /**< \brief (EIC_NMICTRL) Falling-edge detection */
-#define   EIC_NMICTRL_NMISENSE_BOTH_Val   0x3ul  /**< \brief (EIC_NMICTRL) Both-edges detection */
-#define   EIC_NMICTRL_NMISENSE_HIGH_Val   0x4ul  /**< \brief (EIC_NMICTRL) High-level detection */
-#define   EIC_NMICTRL_NMISENSE_LOW_Val    0x5ul  /**< \brief (EIC_NMICTRL) Low-level detection */
-#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
-#define EIC_NMICTRL_NMIFILTEN       (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
-#define EIC_NMICTRL_MASK            0x0Ful       /**< \brief (EIC_NMICTRL) MASK Register */
-
-/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W  8) Non-Maskable Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EIC_NMIFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_NMIFLAG_OFFSET          0x03         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
-#define EIC_NMIFLAG_RESETVALUE      0x00ul       /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
-
-#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
-#define EIC_NMIFLAG_NMI             (0x1ul << EIC_NMIFLAG_NMI_Pos)
-#define EIC_NMIFLAG_MASK            0x01ul       /**< \brief (EIC_NMIFLAG) MASK Register */
-
-/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINTEO0:1;      /*!< bit:      0  External Interrupt 0 Event Output Enable */
-    uint32_t EXTINTEO1:1;      /*!< bit:      1  External Interrupt 1 Event Output Enable */
-    uint32_t EXTINTEO2:1;      /*!< bit:      2  External Interrupt 2 Event Output Enable */
-    uint32_t EXTINTEO3:1;      /*!< bit:      3  External Interrupt 3 Event Output Enable */
-    uint32_t EXTINTEO4:1;      /*!< bit:      4  External Interrupt 4 Event Output Enable */
-    uint32_t EXTINTEO5:1;      /*!< bit:      5  External Interrupt 5 Event Output Enable */
-    uint32_t EXTINTEO6:1;      /*!< bit:      6  External Interrupt 6 Event Output Enable */
-    uint32_t EXTINTEO7:1;      /*!< bit:      7  External Interrupt 7 Event Output Enable */
-    uint32_t EXTINTEO8:1;      /*!< bit:      8  External Interrupt 8 Event Output Enable */
-    uint32_t EXTINTEO9:1;      /*!< bit:      9  External Interrupt 9 Event Output Enable */
-    uint32_t EXTINTEO10:1;     /*!< bit:     10  External Interrupt 10 Event Output Enable */
-    uint32_t EXTINTEO11:1;     /*!< bit:     11  External Interrupt 11 Event Output Enable */
-    uint32_t EXTINTEO12:1;     /*!< bit:     12  External Interrupt 12 Event Output Enable */
-    uint32_t EXTINTEO13:1;     /*!< bit:     13  External Interrupt 13 Event Output Enable */
-    uint32_t EXTINTEO14:1;     /*!< bit:     14  External Interrupt 14 Event Output Enable */
-    uint32_t EXTINTEO15:1;     /*!< bit:     15  External Interrupt 15 Event Output Enable */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt x Event Output Enable */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_EVCTRL_OFFSET           0x04         /**< \brief (EIC_EVCTRL offset) Event Control */
-#define EIC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
-
-#define EIC_EVCTRL_EXTINTEO0_Pos    0            /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO0        (1 << EIC_EVCTRL_EXTINTEO0_Pos)
-#define EIC_EVCTRL_EXTINTEO1_Pos    1            /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO1        (1 << EIC_EVCTRL_EXTINTEO1_Pos)
-#define EIC_EVCTRL_EXTINTEO2_Pos    2            /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO2        (1 << EIC_EVCTRL_EXTINTEO2_Pos)
-#define EIC_EVCTRL_EXTINTEO3_Pos    3            /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO3        (1 << EIC_EVCTRL_EXTINTEO3_Pos)
-#define EIC_EVCTRL_EXTINTEO4_Pos    4            /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO4        (1 << EIC_EVCTRL_EXTINTEO4_Pos)
-#define EIC_EVCTRL_EXTINTEO5_Pos    5            /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO5        (1 << EIC_EVCTRL_EXTINTEO5_Pos)
-#define EIC_EVCTRL_EXTINTEO6_Pos    6            /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO6        (1 << EIC_EVCTRL_EXTINTEO6_Pos)
-#define EIC_EVCTRL_EXTINTEO7_Pos    7            /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO7        (1 << EIC_EVCTRL_EXTINTEO7_Pos)
-#define EIC_EVCTRL_EXTINTEO8_Pos    8            /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO8        (1 << EIC_EVCTRL_EXTINTEO8_Pos)
-#define EIC_EVCTRL_EXTINTEO9_Pos    9            /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO9        (1 << EIC_EVCTRL_EXTINTEO9_Pos)
-#define EIC_EVCTRL_EXTINTEO10_Pos   10           /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO10       (1 << EIC_EVCTRL_EXTINTEO10_Pos)
-#define EIC_EVCTRL_EXTINTEO11_Pos   11           /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO11       (1 << EIC_EVCTRL_EXTINTEO11_Pos)
-#define EIC_EVCTRL_EXTINTEO12_Pos   12           /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO12       (1 << EIC_EVCTRL_EXTINTEO12_Pos)
-#define EIC_EVCTRL_EXTINTEO13_Pos   13           /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO13       (1 << EIC_EVCTRL_EXTINTEO13_Pos)
-#define EIC_EVCTRL_EXTINTEO14_Pos   14           /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO14       (1 << EIC_EVCTRL_EXTINTEO14_Pos)
-#define EIC_EVCTRL_EXTINTEO15_Pos   15           /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO15       (1 << EIC_EVCTRL_EXTINTEO15_Pos)
-#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO_Msk     (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
-#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
-#define EIC_EVCTRL_MASK             0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
-
-/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
-    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
-    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
-    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
-    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
-    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
-    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
-    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
-    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
-    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
-    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
-    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
-    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
-    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
-    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
-    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTENCLR_OFFSET         0x08         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
-#define EIC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define EIC_INTENCLR_EXTINT0_Pos    0            /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
-#define EIC_INTENCLR_EXTINT0        (1 << EIC_INTENCLR_EXTINT0_Pos)
-#define EIC_INTENCLR_EXTINT1_Pos    1            /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
-#define EIC_INTENCLR_EXTINT1        (1 << EIC_INTENCLR_EXTINT1_Pos)
-#define EIC_INTENCLR_EXTINT2_Pos    2            /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
-#define EIC_INTENCLR_EXTINT2        (1 << EIC_INTENCLR_EXTINT2_Pos)
-#define EIC_INTENCLR_EXTINT3_Pos    3            /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
-#define EIC_INTENCLR_EXTINT3        (1 << EIC_INTENCLR_EXTINT3_Pos)
-#define EIC_INTENCLR_EXTINT4_Pos    4            /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
-#define EIC_INTENCLR_EXTINT4        (1 << EIC_INTENCLR_EXTINT4_Pos)
-#define EIC_INTENCLR_EXTINT5_Pos    5            /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
-#define EIC_INTENCLR_EXTINT5        (1 << EIC_INTENCLR_EXTINT5_Pos)
-#define EIC_INTENCLR_EXTINT6_Pos    6            /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
-#define EIC_INTENCLR_EXTINT6        (1 << EIC_INTENCLR_EXTINT6_Pos)
-#define EIC_INTENCLR_EXTINT7_Pos    7            /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
-#define EIC_INTENCLR_EXTINT7        (1 << EIC_INTENCLR_EXTINT7_Pos)
-#define EIC_INTENCLR_EXTINT8_Pos    8            /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
-#define EIC_INTENCLR_EXTINT8        (1 << EIC_INTENCLR_EXTINT8_Pos)
-#define EIC_INTENCLR_EXTINT9_Pos    9            /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
-#define EIC_INTENCLR_EXTINT9        (1 << EIC_INTENCLR_EXTINT9_Pos)
-#define EIC_INTENCLR_EXTINT10_Pos   10           /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
-#define EIC_INTENCLR_EXTINT10       (1 << EIC_INTENCLR_EXTINT10_Pos)
-#define EIC_INTENCLR_EXTINT11_Pos   11           /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
-#define EIC_INTENCLR_EXTINT11       (1 << EIC_INTENCLR_EXTINT11_Pos)
-#define EIC_INTENCLR_EXTINT12_Pos   12           /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
-#define EIC_INTENCLR_EXTINT12       (1 << EIC_INTENCLR_EXTINT12_Pos)
-#define EIC_INTENCLR_EXTINT13_Pos   13           /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
-#define EIC_INTENCLR_EXTINT13       (1 << EIC_INTENCLR_EXTINT13_Pos)
-#define EIC_INTENCLR_EXTINT14_Pos   14           /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
-#define EIC_INTENCLR_EXTINT14       (1 << EIC_INTENCLR_EXTINT14_Pos)
-#define EIC_INTENCLR_EXTINT15_Pos   15           /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
-#define EIC_INTENCLR_EXTINT15       (1 << EIC_INTENCLR_EXTINT15_Pos)
-#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
-#define EIC_INTENCLR_EXTINT_Msk     (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
-#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
-#define EIC_INTENCLR_MASK           0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
-
-/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
-    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
-    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
-    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
-    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
-    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
-    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
-    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
-    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
-    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
-    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
-    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
-    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
-    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
-    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
-    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTENSET_OFFSET         0x0C         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
-#define EIC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
-
-#define EIC_INTENSET_EXTINT0_Pos    0            /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
-#define EIC_INTENSET_EXTINT0        (1 << EIC_INTENSET_EXTINT0_Pos)
-#define EIC_INTENSET_EXTINT1_Pos    1            /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
-#define EIC_INTENSET_EXTINT1        (1 << EIC_INTENSET_EXTINT1_Pos)
-#define EIC_INTENSET_EXTINT2_Pos    2            /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
-#define EIC_INTENSET_EXTINT2        (1 << EIC_INTENSET_EXTINT2_Pos)
-#define EIC_INTENSET_EXTINT3_Pos    3            /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
-#define EIC_INTENSET_EXTINT3        (1 << EIC_INTENSET_EXTINT3_Pos)
-#define EIC_INTENSET_EXTINT4_Pos    4            /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
-#define EIC_INTENSET_EXTINT4        (1 << EIC_INTENSET_EXTINT4_Pos)
-#define EIC_INTENSET_EXTINT5_Pos    5            /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
-#define EIC_INTENSET_EXTINT5        (1 << EIC_INTENSET_EXTINT5_Pos)
-#define EIC_INTENSET_EXTINT6_Pos    6            /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
-#define EIC_INTENSET_EXTINT6        (1 << EIC_INTENSET_EXTINT6_Pos)
-#define EIC_INTENSET_EXTINT7_Pos    7            /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
-#define EIC_INTENSET_EXTINT7        (1 << EIC_INTENSET_EXTINT7_Pos)
-#define EIC_INTENSET_EXTINT8_Pos    8            /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
-#define EIC_INTENSET_EXTINT8        (1 << EIC_INTENSET_EXTINT8_Pos)
-#define EIC_INTENSET_EXTINT9_Pos    9            /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
-#define EIC_INTENSET_EXTINT9        (1 << EIC_INTENSET_EXTINT9_Pos)
-#define EIC_INTENSET_EXTINT10_Pos   10           /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
-#define EIC_INTENSET_EXTINT10       (1 << EIC_INTENSET_EXTINT10_Pos)
-#define EIC_INTENSET_EXTINT11_Pos   11           /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
-#define EIC_INTENSET_EXTINT11       (1 << EIC_INTENSET_EXTINT11_Pos)
-#define EIC_INTENSET_EXTINT12_Pos   12           /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
-#define EIC_INTENSET_EXTINT12       (1 << EIC_INTENSET_EXTINT12_Pos)
-#define EIC_INTENSET_EXTINT13_Pos   13           /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
-#define EIC_INTENSET_EXTINT13       (1 << EIC_INTENSET_EXTINT13_Pos)
-#define EIC_INTENSET_EXTINT14_Pos   14           /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
-#define EIC_INTENSET_EXTINT14       (1 << EIC_INTENSET_EXTINT14_Pos)
-#define EIC_INTENSET_EXTINT15_Pos   15           /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
-#define EIC_INTENSET_EXTINT15       (1 << EIC_INTENSET_EXTINT15_Pos)
-#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt x Enable */
-#define EIC_INTENSET_EXTINT_Msk     (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
-#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
-#define EIC_INTENSET_MASK           0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
-
-/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0               */
-    __I uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1               */
-    __I uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2               */
-    __I uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3               */
-    __I uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4               */
-    __I uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5               */
-    __I uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6               */
-    __I uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7               */
-    __I uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8               */
-    __I uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9               */
-    __I uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10              */
-    __I uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11              */
-    __I uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12              */
-    __I uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13              */
-    __I uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14              */
-    __I uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15              */
-    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x               */
-    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTFLAG_OFFSET          0x10         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EIC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define EIC_INTFLAG_EXTINT0_Pos     0            /**< \brief (EIC_INTFLAG) External Interrupt 0 */
-#define EIC_INTFLAG_EXTINT0         (1 << EIC_INTFLAG_EXTINT0_Pos)
-#define EIC_INTFLAG_EXTINT1_Pos     1            /**< \brief (EIC_INTFLAG) External Interrupt 1 */
-#define EIC_INTFLAG_EXTINT1         (1 << EIC_INTFLAG_EXTINT1_Pos)
-#define EIC_INTFLAG_EXTINT2_Pos     2            /**< \brief (EIC_INTFLAG) External Interrupt 2 */
-#define EIC_INTFLAG_EXTINT2         (1 << EIC_INTFLAG_EXTINT2_Pos)
-#define EIC_INTFLAG_EXTINT3_Pos     3            /**< \brief (EIC_INTFLAG) External Interrupt 3 */
-#define EIC_INTFLAG_EXTINT3         (1 << EIC_INTFLAG_EXTINT3_Pos)
-#define EIC_INTFLAG_EXTINT4_Pos     4            /**< \brief (EIC_INTFLAG) External Interrupt 4 */
-#define EIC_INTFLAG_EXTINT4         (1 << EIC_INTFLAG_EXTINT4_Pos)
-#define EIC_INTFLAG_EXTINT5_Pos     5            /**< \brief (EIC_INTFLAG) External Interrupt 5 */
-#define EIC_INTFLAG_EXTINT5         (1 << EIC_INTFLAG_EXTINT5_Pos)
-#define EIC_INTFLAG_EXTINT6_Pos     6            /**< \brief (EIC_INTFLAG) External Interrupt 6 */
-#define EIC_INTFLAG_EXTINT6         (1 << EIC_INTFLAG_EXTINT6_Pos)
-#define EIC_INTFLAG_EXTINT7_Pos     7            /**< \brief (EIC_INTFLAG) External Interrupt 7 */
-#define EIC_INTFLAG_EXTINT7         (1 << EIC_INTFLAG_EXTINT7_Pos)
-#define EIC_INTFLAG_EXTINT8_Pos     8            /**< \brief (EIC_INTFLAG) External Interrupt 8 */
-#define EIC_INTFLAG_EXTINT8         (1 << EIC_INTFLAG_EXTINT8_Pos)
-#define EIC_INTFLAG_EXTINT9_Pos     9            /**< \brief (EIC_INTFLAG) External Interrupt 9 */
-#define EIC_INTFLAG_EXTINT9         (1 << EIC_INTFLAG_EXTINT9_Pos)
-#define EIC_INTFLAG_EXTINT10_Pos    10           /**< \brief (EIC_INTFLAG) External Interrupt 10 */
-#define EIC_INTFLAG_EXTINT10        (1 << EIC_INTFLAG_EXTINT10_Pos)
-#define EIC_INTFLAG_EXTINT11_Pos    11           /**< \brief (EIC_INTFLAG) External Interrupt 11 */
-#define EIC_INTFLAG_EXTINT11        (1 << EIC_INTFLAG_EXTINT11_Pos)
-#define EIC_INTFLAG_EXTINT12_Pos    12           /**< \brief (EIC_INTFLAG) External Interrupt 12 */
-#define EIC_INTFLAG_EXTINT12        (1 << EIC_INTFLAG_EXTINT12_Pos)
-#define EIC_INTFLAG_EXTINT13_Pos    13           /**< \brief (EIC_INTFLAG) External Interrupt 13 */
-#define EIC_INTFLAG_EXTINT13        (1 << EIC_INTFLAG_EXTINT13_Pos)
-#define EIC_INTFLAG_EXTINT14_Pos    14           /**< \brief (EIC_INTFLAG) External Interrupt 14 */
-#define EIC_INTFLAG_EXTINT14        (1 << EIC_INTFLAG_EXTINT14_Pos)
-#define EIC_INTFLAG_EXTINT15_Pos    15           /**< \brief (EIC_INTFLAG) External Interrupt 15 */
-#define EIC_INTFLAG_EXTINT15        (1 << EIC_INTFLAG_EXTINT15_Pos)
-#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt x */
-#define EIC_INTFLAG_EXTINT_Msk      (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
-#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
-#define EIC_INTFLAG_MASK            0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
-
-/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAKEUPEN0:1;      /*!< bit:      0  External Interrupt 0 Wake-up Enable */
-    uint32_t WAKEUPEN1:1;      /*!< bit:      1  External Interrupt 1 Wake-up Enable */
-    uint32_t WAKEUPEN2:1;      /*!< bit:      2  External Interrupt 2 Wake-up Enable */
-    uint32_t WAKEUPEN3:1;      /*!< bit:      3  External Interrupt 3 Wake-up Enable */
-    uint32_t WAKEUPEN4:1;      /*!< bit:      4  External Interrupt 4 Wake-up Enable */
-    uint32_t WAKEUPEN5:1;      /*!< bit:      5  External Interrupt 5 Wake-up Enable */
-    uint32_t WAKEUPEN6:1;      /*!< bit:      6  External Interrupt 6 Wake-up Enable */
-    uint32_t WAKEUPEN7:1;      /*!< bit:      7  External Interrupt 7 Wake-up Enable */
-    uint32_t WAKEUPEN8:1;      /*!< bit:      8  External Interrupt 8 Wake-up Enable */
-    uint32_t WAKEUPEN9:1;      /*!< bit:      9  External Interrupt 9 Wake-up Enable */
-    uint32_t WAKEUPEN10:1;     /*!< bit:     10  External Interrupt 10 Wake-up Enable */
-    uint32_t WAKEUPEN11:1;     /*!< bit:     11  External Interrupt 11 Wake-up Enable */
-    uint32_t WAKEUPEN12:1;     /*!< bit:     12  External Interrupt 12 Wake-up Enable */
-    uint32_t WAKEUPEN13:1;     /*!< bit:     13  External Interrupt 13 Wake-up Enable */
-    uint32_t WAKEUPEN14:1;     /*!< bit:     14  External Interrupt 14 Wake-up Enable */
-    uint32_t WAKEUPEN15:1;     /*!< bit:     15  External Interrupt 15 Wake-up Enable */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t WAKEUPEN:16;      /*!< bit:  0..15  External Interrupt x Wake-up Enable */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_WAKEUP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_WAKEUP_OFFSET           0x14         /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
-#define EIC_WAKEUP_RESETVALUE       0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
-
-#define EIC_WAKEUP_WAKEUPEN0_Pos    0            /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN0        (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
-#define EIC_WAKEUP_WAKEUPEN1_Pos    1            /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN1        (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
-#define EIC_WAKEUP_WAKEUPEN2_Pos    2            /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN2        (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
-#define EIC_WAKEUP_WAKEUPEN3_Pos    3            /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN3        (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
-#define EIC_WAKEUP_WAKEUPEN4_Pos    4            /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN4        (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
-#define EIC_WAKEUP_WAKEUPEN5_Pos    5            /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN5        (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
-#define EIC_WAKEUP_WAKEUPEN6_Pos    6            /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN6        (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
-#define EIC_WAKEUP_WAKEUPEN7_Pos    7            /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN7        (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
-#define EIC_WAKEUP_WAKEUPEN8_Pos    8            /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN8        (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
-#define EIC_WAKEUP_WAKEUPEN9_Pos    9            /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN9        (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
-#define EIC_WAKEUP_WAKEUPEN10_Pos   10           /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN10       (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
-#define EIC_WAKEUP_WAKEUPEN11_Pos   11           /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN11       (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
-#define EIC_WAKEUP_WAKEUPEN12_Pos   12           /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN12       (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
-#define EIC_WAKEUP_WAKEUPEN13_Pos   13           /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN13       (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
-#define EIC_WAKEUP_WAKEUPEN14_Pos   14           /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN14       (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
-#define EIC_WAKEUP_WAKEUPEN15_Pos   15           /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN15       (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
-#define EIC_WAKEUP_WAKEUPEN_Pos     0            /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN_Msk     (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
-#define EIC_WAKEUP_WAKEUPEN(value)  (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
-#define EIC_WAKEUP_MASK             0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
-
-/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense 0 Configuration        */
-    uint32_t FILTEN0:1;        /*!< bit:      3  Filter 0 Enable                    */
-    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense 1 Configuration        */
-    uint32_t FILTEN1:1;        /*!< bit:      7  Filter 1 Enable                    */
-    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense 2 Configuration        */
-    uint32_t FILTEN2:1;        /*!< bit:     11  Filter 2 Enable                    */
-    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense 3 Configuration        */
-    uint32_t FILTEN3:1;        /*!< bit:     15  Filter 3 Enable                    */
-    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense 4 Configuration        */
-    uint32_t FILTEN4:1;        /*!< bit:     19  Filter 4 Enable                    */
-    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense 5 Configuration        */
-    uint32_t FILTEN5:1;        /*!< bit:     23  Filter 5 Enable                    */
-    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense 6 Configuration        */
-    uint32_t FILTEN6:1;        /*!< bit:     27  Filter 6 Enable                    */
-    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense 7 Configuration        */
-    uint32_t FILTEN7:1;        /*!< bit:     31  Filter 7 Enable                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_CONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_CONFIG_OFFSET           0x18         /**< \brief (EIC_CONFIG offset) Configuration n */
-#define EIC_CONFIG_RESETVALUE       0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
-
-#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
-#define EIC_CONFIG_SENSE0_Msk       (0x7ul << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
-#define   EIC_CONFIG_SENSE0_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE0_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising-edge detection */
-#define   EIC_CONFIG_SENSE0_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling-edge detection */
-#define   EIC_CONFIG_SENSE0_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both-edges detection */
-#define   EIC_CONFIG_SENSE0_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High-level detection */
-#define   EIC_CONFIG_SENSE0_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low-level detection */
-#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter 0 Enable */
-#define EIC_CONFIG_FILTEN0          (0x1ul << EIC_CONFIG_FILTEN0_Pos)
-#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
-#define EIC_CONFIG_SENSE1_Msk       (0x7ul << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
-#define   EIC_CONFIG_SENSE1_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE1_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE1_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE1_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE1_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE1_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter 1 Enable */
-#define EIC_CONFIG_FILTEN1          (0x1ul << EIC_CONFIG_FILTEN1_Pos)
-#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
-#define EIC_CONFIG_SENSE2_Msk       (0x7ul << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
-#define   EIC_CONFIG_SENSE2_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE2_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE2_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE2_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE2_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE2_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter 2 Enable */
-#define EIC_CONFIG_FILTEN2          (0x1ul << EIC_CONFIG_FILTEN2_Pos)
-#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
-#define EIC_CONFIG_SENSE3_Msk       (0x7ul << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
-#define   EIC_CONFIG_SENSE3_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE3_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE3_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE3_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE3_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE3_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter 3 Enable */
-#define EIC_CONFIG_FILTEN3          (0x1ul << EIC_CONFIG_FILTEN3_Pos)
-#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
-#define EIC_CONFIG_SENSE4_Msk       (0x7ul << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
-#define   EIC_CONFIG_SENSE4_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE4_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE4_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE4_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE4_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE4_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter 4 Enable */
-#define EIC_CONFIG_FILTEN4          (0x1ul << EIC_CONFIG_FILTEN4_Pos)
-#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
-#define EIC_CONFIG_SENSE5_Msk       (0x7ul << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
-#define   EIC_CONFIG_SENSE5_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE5_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE5_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE5_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE5_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE5_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter 5 Enable */
-#define EIC_CONFIG_FILTEN5          (0x1ul << EIC_CONFIG_FILTEN5_Pos)
-#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
-#define EIC_CONFIG_SENSE6_Msk       (0x7ul << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
-#define   EIC_CONFIG_SENSE6_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE6_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE6_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE6_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE6_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE6_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter 6 Enable */
-#define EIC_CONFIG_FILTEN6          (0x1ul << EIC_CONFIG_FILTEN6_Pos)
-#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
-#define EIC_CONFIG_SENSE7_Msk       (0x7ul << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
-#define   EIC_CONFIG_SENSE7_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE7_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE7_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE7_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE7_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE7_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter 7 Enable */
-#define EIC_CONFIG_FILTEN7          (0x1ul << EIC_CONFIG_FILTEN7_Pos)
-#define EIC_CONFIG_MASK             0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
-
-/** \brief EIC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO EIC_CTRL_Type             CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
-  __I  EIC_STATUS_Type           STATUS;      /**< \brief Offset: 0x01 (R/   8) Status */
-  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x02 (R/W  8) Non-Maskable Interrupt Control */
-  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x03 (R/W  8) Non-Maskable Interrupt Flag Status and Clear */
-  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) Event Control */
-  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
-  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
-  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
-  __IO EIC_WAKEUP_Type           WAKEUP;      /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
-  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x18 (R/W 32) Configuration n */
-} Eic;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_EIC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_COMPONENT_
+#define _SAMD21_EIC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC                     0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET             0x00         /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE         0x00ul       /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos          0            /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST              (0x1ul << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos         1            /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE             (0x1ul << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK               0x03ul       /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET           0x01         /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE       0x00ul       /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos     7            /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY         (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK             0x80ul       /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W  8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense       */
+    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET          0x02         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE      0x00ul       /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk    (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   0x0ul  /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   0x1ul  /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   0x2ul  /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   0x3ul  /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   0x4ul  /**< \brief (EIC_NMICTRL) High-level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    0x5ul  /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN       (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK            0x0Ful       /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W  8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET          0x03         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE      0x00ul       /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI             (0x1ul << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            0x01ul       /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINTEO0:1;      /*!< bit:      0  External Interrupt 0 Event Output Enable */
+    uint32_t EXTINTEO1:1;      /*!< bit:      1  External Interrupt 1 Event Output Enable */
+    uint32_t EXTINTEO2:1;      /*!< bit:      2  External Interrupt 2 Event Output Enable */
+    uint32_t EXTINTEO3:1;      /*!< bit:      3  External Interrupt 3 Event Output Enable */
+    uint32_t EXTINTEO4:1;      /*!< bit:      4  External Interrupt 4 Event Output Enable */
+    uint32_t EXTINTEO5:1;      /*!< bit:      5  External Interrupt 5 Event Output Enable */
+    uint32_t EXTINTEO6:1;      /*!< bit:      6  External Interrupt 6 Event Output Enable */
+    uint32_t EXTINTEO7:1;      /*!< bit:      7  External Interrupt 7 Event Output Enable */
+    uint32_t EXTINTEO8:1;      /*!< bit:      8  External Interrupt 8 Event Output Enable */
+    uint32_t EXTINTEO9:1;      /*!< bit:      9  External Interrupt 9 Event Output Enable */
+    uint32_t EXTINTEO10:1;     /*!< bit:     10  External Interrupt 10 Event Output Enable */
+    uint32_t EXTINTEO11:1;     /*!< bit:     11  External Interrupt 11 Event Output Enable */
+    uint32_t EXTINTEO12:1;     /*!< bit:     12  External Interrupt 12 Event Output Enable */
+    uint32_t EXTINTEO13:1;     /*!< bit:     13  External Interrupt 13 Event Output Enable */
+    uint32_t EXTINTEO14:1;     /*!< bit:     14  External Interrupt 14 Event Output Enable */
+    uint32_t EXTINTEO15:1;     /*!< bit:     15  External Interrupt 15 Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt x Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET           0x04         /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos    0            /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0        (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos    1            /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1        (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos    2            /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2        (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos    3            /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3        (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos    4            /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4        (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos    5            /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5        (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos    6            /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6        (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos    7            /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7        (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos    8            /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8        (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos    9            /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9        (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos   10           /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10       (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos   11           /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11       (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos   12           /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12       (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos   13           /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13       (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos   14           /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14       (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos   15           /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15       (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk     (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK             0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET         0x08         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos    0            /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0        (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos    1            /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1        (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos    2            /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2        (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos    3            /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3        (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos    4            /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4        (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos    5            /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5        (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos    6            /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6        (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos    7            /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7        (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos    8            /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8        (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos    9            /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9        (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos   10           /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10       (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos   11           /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11       (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos   12           /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12       (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos   13           /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13       (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos   14           /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14       (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos   15           /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15       (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk     (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK           0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET         0x0C         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos    0            /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0        (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos    1            /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1        (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos    2            /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2        (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos    3            /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3        (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos    4            /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4        (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos    5            /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5        (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos    6            /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6        (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos    7            /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7        (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos    8            /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8        (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos    9            /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9        (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos   10           /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10       (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos   11           /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11       (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos   12           /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12       (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos   13           /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13       (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos   14           /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14       (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos   15           /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15       (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk     (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK           0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0               */
+    __I uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1               */
+    __I uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2               */
+    __I uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3               */
+    __I uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4               */
+    __I uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5               */
+    __I uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6               */
+    __I uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7               */
+    __I uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8               */
+    __I uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9               */
+    __I uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10              */
+    __I uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11              */
+    __I uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12              */
+    __I uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13              */
+    __I uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14              */
+    __I uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15              */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x               */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET          0x10         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos     0            /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0         (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos     1            /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1         (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos     2            /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2         (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos     3            /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3         (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos     4            /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4         (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos     5            /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5         (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos     6            /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6         (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos     7            /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7         (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos     8            /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8         (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos     9            /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9         (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos    10           /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10        (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos    11           /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11        (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos    12           /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12        (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos    13           /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13        (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos    14           /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14        (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos    15           /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15        (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk      (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK            0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAKEUPEN0:1;      /*!< bit:      0  External Interrupt 0 Wake-up Enable */
+    uint32_t WAKEUPEN1:1;      /*!< bit:      1  External Interrupt 1 Wake-up Enable */
+    uint32_t WAKEUPEN2:1;      /*!< bit:      2  External Interrupt 2 Wake-up Enable */
+    uint32_t WAKEUPEN3:1;      /*!< bit:      3  External Interrupt 3 Wake-up Enable */
+    uint32_t WAKEUPEN4:1;      /*!< bit:      4  External Interrupt 4 Wake-up Enable */
+    uint32_t WAKEUPEN5:1;      /*!< bit:      5  External Interrupt 5 Wake-up Enable */
+    uint32_t WAKEUPEN6:1;      /*!< bit:      6  External Interrupt 6 Wake-up Enable */
+    uint32_t WAKEUPEN7:1;      /*!< bit:      7  External Interrupt 7 Wake-up Enable */
+    uint32_t WAKEUPEN8:1;      /*!< bit:      8  External Interrupt 8 Wake-up Enable */
+    uint32_t WAKEUPEN9:1;      /*!< bit:      9  External Interrupt 9 Wake-up Enable */
+    uint32_t WAKEUPEN10:1;     /*!< bit:     10  External Interrupt 10 Wake-up Enable */
+    uint32_t WAKEUPEN11:1;     /*!< bit:     11  External Interrupt 11 Wake-up Enable */
+    uint32_t WAKEUPEN12:1;     /*!< bit:     12  External Interrupt 12 Wake-up Enable */
+    uint32_t WAKEUPEN13:1;     /*!< bit:     13  External Interrupt 13 Wake-up Enable */
+    uint32_t WAKEUPEN14:1;     /*!< bit:     14  External Interrupt 14 Wake-up Enable */
+    uint32_t WAKEUPEN15:1;     /*!< bit:     15  External Interrupt 15 Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t WAKEUPEN:16;      /*!< bit:  0..15  External Interrupt x Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET           0x14         /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE       0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos    0            /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0        (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos    1            /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1        (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos    2            /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2        (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos    3            /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3        (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos    4            /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4        (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos    5            /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5        (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos    6            /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6        (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos    7            /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7        (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos    8            /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8        (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos    9            /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9        (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos   10           /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10       (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos   11           /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11       (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos   12           /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12       (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos   13           /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13       (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos   14           /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14       (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos   15           /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15       (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos     0            /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk     (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value)  (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
+#define EIC_WAKEUP_MASK             0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense 0 Configuration        */
+    uint32_t FILTEN0:1;        /*!< bit:      3  Filter 0 Enable                    */
+    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense 1 Configuration        */
+    uint32_t FILTEN1:1;        /*!< bit:      7  Filter 1 Enable                    */
+    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense 2 Configuration        */
+    uint32_t FILTEN2:1;        /*!< bit:     11  Filter 2 Enable                    */
+    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense 3 Configuration        */
+    uint32_t FILTEN3:1;        /*!< bit:     15  Filter 3 Enable                    */
+    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense 4 Configuration        */
+    uint32_t FILTEN4:1;        /*!< bit:     19  Filter 4 Enable                    */
+    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense 5 Configuration        */
+    uint32_t FILTEN5:1;        /*!< bit:     23  Filter 5 Enable                    */
+    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense 6 Configuration        */
+    uint32_t FILTEN6:1;        /*!< bit:     27  Filter 6 Enable                    */
+    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense 7 Configuration        */
+    uint32_t FILTEN7:1;        /*!< bit:     31  Filter 7 Enable                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET           0x18         /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE       0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk       (0x7ul << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define   EIC_CONFIG_SENSE0_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both-edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High-level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0          (0x1ul << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk       (0x7ul << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define   EIC_CONFIG_SENSE1_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1          (0x1ul << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk       (0x7ul << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define   EIC_CONFIG_SENSE2_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2          (0x1ul << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk       (0x7ul << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define   EIC_CONFIG_SENSE3_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3          (0x1ul << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk       (0x7ul << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define   EIC_CONFIG_SENSE4_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4          (0x1ul << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk       (0x7ul << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define   EIC_CONFIG_SENSE5_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5          (0x1ul << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk       (0x7ul << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define   EIC_CONFIG_SENSE6_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6          (0x1ul << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk       (0x7ul << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define   EIC_CONFIG_SENSE7_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7          (0x1ul << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EIC_CTRL_Type             CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __I  EIC_STATUS_Type           STATUS;      /**< \brief Offset: 0x01 (R/   8) Status */
+  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x02 (R/W  8) Non-Maskable Interrupt Control */
+  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x03 (R/W  8) Non-Maskable Interrupt Flag Status and Clear */
+  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) Event Control */
+  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+  __IO EIC_WAKEUP_Type           WAKEUP;      /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EIC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h
index 15ef9da..1fcde74 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h
@@ -1,594 +1,594 @@
-/**
- * \file
- *
- * \brief Component description for EVSYS
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_EVSYS_COMPONENT_
-#define _SAMD21_EVSYS_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR EVSYS */
-/* ========================================================================== */
-/** \addtogroup SAMD21_EVSYS Event System Interface */
-/*@{*/
-
-#define EVSYS_U2208
-#define REV_EVSYS                   0x101
-
-/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
-    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
-#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
-
-#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
-#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
-#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
-#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
-#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
-
-/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
-    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
-    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_CHANNEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
-#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
-
-#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
-#define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
-#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
-#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
-#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
-#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
-#define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
-#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
-#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
-#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
-#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
-#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
-#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
-#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
-#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
-#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
-
-/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t USER:5;           /*!< bit:  0.. 4  User Multiplexer Selection         */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} EVSYS_USER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
-#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
-
-#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
-#define EVSYS_USER_USER_Msk         (0x1Ful << EVSYS_USER_USER_Pos)
-#define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
-#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
-#define EVSYS_USER_CHANNEL_Msk      (0x1Ful << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
-#define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
-#define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_MASK             0x1F1Ful     /**< \brief (EVSYS_USER) MASK Register */
-
-/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
-    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
-    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
-    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
-    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
-    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
-    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
-    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
-    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
-    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
-    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
-    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
-    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
-    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
-    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
-    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
-    uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
-    uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
-    uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
-    uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
-    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
-    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
-    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
-    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
-    uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
-#define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
-
-#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
-#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
-#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
-#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
-#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
-#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
-#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
-#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
-#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
-#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
-#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
-#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
-#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
-#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
-#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
-#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
-#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
-#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
-#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
-#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
-#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
-#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
-#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
-#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
-#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
-#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
-#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
-#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
-#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
-#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
-#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
-#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
-#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
-#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
-#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
-#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
-#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
-#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
-#define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
-#define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
-#define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
-#define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
-#define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
-#define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
-#define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
-#define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
-#define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
-#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
-#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
-#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
-#define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
-#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
-#define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
-#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
-#define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
-#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
-#define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
-#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
-#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
-#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
-#define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
-
-/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
-    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
-    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
-    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
-    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
-    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
-    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
-    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
-    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
-    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
-    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
-    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
-    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
-    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
-    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
-    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
-    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
-    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
-    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
-    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
-    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
-    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
-    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
-    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
-    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
-#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
-#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
-#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
-#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
-#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
-#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
-#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
-#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
-#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
-#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
-#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
-#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
-#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
-#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
-#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
-#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
-#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
-#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
-#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
-#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
-#define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
-#define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
-#define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
-#define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
-#define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
-#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
-#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
-#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
-#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
-#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
-#define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
-#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
-#define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
-
-/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
-    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
-    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
-    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
-    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
-    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
-    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
-    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
-    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
-    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
-    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
-    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
-    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
-    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
-    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
-    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
-    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
-    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
-    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
-    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
-    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
-    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
-    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
-    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
-    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
-#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
-
-#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
-#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
-#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
-#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
-#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
-#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
-#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
-#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
-#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
-#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
-#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
-#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
-#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
-#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
-#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
-#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
-#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
-#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
-#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
-#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
-#define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
-#define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
-#define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
-#define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
-#define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
-#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
-#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
-#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
-#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
-#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
-#define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
-#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
-#define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
-
-/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
-    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
-    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
-    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
-    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
-    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
-    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
-    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
-    __I uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
-    __I uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
-    __I uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
-    __I uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
-    __I uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
-    __I uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
-    __I uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
-    __I uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
-    __I uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
-    __I uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
-    __I uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
-    __I uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
-    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
-    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
-    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
-    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
-    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
-    __I uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
-    __I uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
-    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    __I uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
-    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
-#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
-#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
-#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
-#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
-#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
-#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
-#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
-#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
-#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
-#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
-#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
-#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
-#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
-#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
-#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
-#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
-#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
-#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
-#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
-#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
-#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
-#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
-#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
-#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
-#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
-#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
-#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
-#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
-#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
-#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
-#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
-#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
-#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
-#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
-#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
-#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
-#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
-#define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
-#define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
-#define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
-#define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
-#define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
-#define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
-#define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
-#define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
-#define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
-#define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
-#define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
-#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
-#define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
-#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
-#define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
-#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
-#define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
-#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
-#define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
-#define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
-#define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
-#define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
-#define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
-
-/** \brief EVSYS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
-       RoReg8                    Reserved1[0x3];
-  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
-  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
-       RoReg8                    Reserved2[0x2];
-  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
-  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
-  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
-  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
-} Evsys;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_EVSYS_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS                   0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
+#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t USER:5;           /*!< bit:  0.. 4  User Multiplexer Selection         */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk         (0x1Ful << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
+#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (0x1Ful << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK             0x1F1Ful     /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
+    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
+    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
+    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
+    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
+    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
+    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
+    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
+    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
+    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
+    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
+    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
+    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
+    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
+    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
+    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
+    uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
+    uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
+    uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
+    uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
+    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
+    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
+    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
+    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
+    uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
+#define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
+#define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
+#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
+#define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
+#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
+#define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
+#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
+#define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
+#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
+#define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
+    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
+    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
+    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
+    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
+    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
+    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
+    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
+    __I uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
+    __I uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
+    __I uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
+    __I uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
+    __I uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
+    __I uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
+    __I uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
+    __I uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
+    __I uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
+    __I uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
+    __I uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
+    __I uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
+    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
+    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
+    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
+    __I uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
+    __I uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
+#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
+#define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
+#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
+#define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
+  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+       RoReg8                    Reserved2[0x2];
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
+  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h
index e21eebb..bd73f09 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys_variant_d.h
@@ -1,594 +1,594 @@
-/**
- * \file
- *
- * \brief Component description for EVSYS
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_EVSYS_COMPONENT_
-#define _SAMD21_EVSYS_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR EVSYS */
-/* ========================================================================== */
-/** \addtogroup SAMD21_EVSYS Event System Interface */
-/*@{*/
-
-#define EVSYS_U2208
-#define REV_EVSYS                   0x101
-
-/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
-    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
-#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
-
-#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
-#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
-#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
-#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
-#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
-
-/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
-    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
-    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_CHANNEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
-#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
-
-#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
-#define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
-#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
-#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
-#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
-#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
-#define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
-#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
-#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
-#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
-#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
-#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
-#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
-#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
-#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
-#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
-
-/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t USER:6;           /*!< bit:  0.. 5  User Multiplexer Selection         */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} EVSYS_USER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
-#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
-
-#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
-#define EVSYS_USER_USER_Msk         (0x3Ful << EVSYS_USER_USER_Pos)
-#define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
-#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
-#define EVSYS_USER_CHANNEL_Msk      (0x3Ful << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
-#define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
-#define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_MASK             0x1F3Ful     /**< \brief (EVSYS_USER) MASK Register */
-
-/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
-    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
-    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
-    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
-    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
-    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
-    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
-    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
-    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
-    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
-    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
-    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
-    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
-    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
-    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
-    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
-    uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
-    uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
-    uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
-    uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
-    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
-    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
-    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
-    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
-    uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
-#define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
-
-#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
-#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
-#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
-#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
-#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
-#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
-#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
-#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
-#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
-#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
-#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
-#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
-#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
-#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
-#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
-#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
-#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
-#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
-#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
-#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
-#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
-#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
-#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
-#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
-#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
-#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
-#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
-#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
-#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
-#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
-#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
-#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
-#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
-#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
-#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
-#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
-#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
-#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
-#define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
-#define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
-#define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
-#define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
-#define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
-#define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
-#define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
-#define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
-#define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
-#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
-#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
-#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
-#define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
-#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
-#define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
-#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
-#define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
-#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
-#define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
-#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
-#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
-#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
-#define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
-
-/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
-    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
-    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
-    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
-    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
-    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
-    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
-    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
-    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
-    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
-    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
-    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
-    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
-    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
-    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
-    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
-    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
-    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
-    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
-    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
-    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
-    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
-    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
-    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
-    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
-#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
-#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
-#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
-#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
-#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
-#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
-#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
-#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
-#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
-#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
-#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
-#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
-#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
-#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
-#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
-#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
-#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
-#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
-#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
-#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
-#define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
-#define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
-#define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
-#define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
-#define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
-#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
-#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
-#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
-#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
-#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
-#define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
-#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
-#define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
-
-/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
-    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
-    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
-    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
-    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
-    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
-    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
-    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
-    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
-    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
-    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
-    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
-    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
-    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
-    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
-    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
-    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
-    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
-    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
-    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
-    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
-    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
-    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
-    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
-    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
-#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
-
-#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
-#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
-#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
-#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
-#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
-#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
-#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
-#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
-#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
-#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
-#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
-#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
-#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
-#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
-#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
-#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
-#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
-#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
-#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
-#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
-#define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
-#define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
-#define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
-#define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
-#define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
-#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
-#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
-#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
-#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
-#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
-#define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
-#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
-#define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
-
-/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
-    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
-    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
-    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
-    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
-    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
-    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
-    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
-    __I uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
-    __I uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
-    __I uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
-    __I uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
-    __I uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
-    __I uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
-    __I uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
-    __I uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
-    __I uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
-    __I uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
-    __I uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
-    __I uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
-    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
-    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
-    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
-    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
-    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
-    __I uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
-    __I uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
-    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    __I uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
-    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
-#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
-#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
-#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
-#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
-#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
-#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
-#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
-#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
-#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
-#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
-#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
-#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
-#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
-#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
-#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
-#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
-#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
-#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
-#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
-#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
-#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
-#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
-#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
-#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
-#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
-#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
-#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
-#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
-#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
-#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
-#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
-#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
-#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
-#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
-#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
-#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
-#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
-#define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
-#define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
-#define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
-#define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
-#define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
-#define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
-#define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
-#define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
-#define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
-#define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
-#define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
-#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
-#define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
-#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
-#define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
-#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
-#define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
-#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
-#define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
-#define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
-#define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
-#define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
-#define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
-
-/** \brief EVSYS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
-       RoReg8                    Reserved1[0x3];
-  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
-  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
-       RoReg8                    Reserved2[0x2];
-  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
-  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
-  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
-  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
-} Evsys;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_EVSYS_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS                   0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
+#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t USER:6;           /*!< bit:  0.. 5  User Multiplexer Selection         */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk         (0x3Ful << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
+#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (0x3Ful << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK             0x1F3Ful     /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
+    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
+    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
+    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
+    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
+    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
+    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
+    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
+    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
+    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
+    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
+    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
+    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
+    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
+    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
+    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
+    uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
+    uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
+    uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
+    uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
+    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
+    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
+    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
+    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
+    uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
+#define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
+#define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
+#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
+#define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
+#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
+#define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
+#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
+#define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
+#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
+#define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
+    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
+    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
+    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
+    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
+    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
+    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
+    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
+    __I uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
+    __I uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
+    __I uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
+    __I uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
+    __I uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
+    __I uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
+    __I uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
+    __I uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
+    __I uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
+    __I uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
+    __I uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
+    __I uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
+    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
+    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
+    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
+    __I uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
+    __I uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
+#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
+#define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
+#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
+#define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
+  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+       RoReg8                    Reserved2[0x2];
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
+  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h
index 1369da5..c05eba5 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h
@@ -1,300 +1,300 @@
-/**
- * \file
- *
- * \brief Component description for GCLK
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_GCLK_COMPONENT_
-#define _SAMD21_GCLK_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR GCLK */
-/* ========================================================================== */
-/** \addtogroup SAMD21_GCLK Generic Clock Generator */
-/*@{*/
-
-#define GCLK_U2102
-#define REV_GCLK                    0x210
-
-/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} GCLK_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_CTRL_OFFSET            0x0          /**< \brief (GCLK_CTRL offset) Control */
-#define GCLK_CTRL_RESETVALUE        0x00ul       /**< \brief (GCLK_CTRL reset_value) Control */
-
-#define GCLK_CTRL_SWRST_Pos         0            /**< \brief (GCLK_CTRL) Software Reset */
-#define GCLK_CTRL_SWRST             (0x1ul << GCLK_CTRL_SWRST_Pos)
-#define GCLK_CTRL_MASK              0x01ul       /**< \brief (GCLK_CTRL) MASK Register */
-
-/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} GCLK_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_STATUS_OFFSET          0x1          /**< \brief (GCLK_STATUS offset) Status */
-#define GCLK_STATUS_RESETVALUE      0x00ul       /**< \brief (GCLK_STATUS reset_value) Status */
-
-#define GCLK_STATUS_SYNCBUSY_Pos    7            /**< \brief (GCLK_STATUS) Synchronization Busy Status */
-#define GCLK_STATUS_SYNCBUSY        (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
-#define GCLK_STATUS_MASK            0x80ul       /**< \brief (GCLK_STATUS) MASK Register */
-
-/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ID:6;             /*!< bit:  0.. 5  Generic Clock Selection ID         */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t GEN:4;            /*!< bit:  8..11  Generic Clock Generator            */
-    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
-    uint16_t CLKEN:1;          /*!< bit:     14  Clock Enable                       */
-    uint16_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} GCLK_CLKCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_CLKCTRL_OFFSET         0x2          /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
-#define GCLK_CLKCTRL_RESETVALUE     0x0000ul     /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
-
-#define GCLK_CLKCTRL_ID_Pos         0            /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
-#define GCLK_CLKCTRL_ID_Msk         (0x3Ful << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID(value)      (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
-#define   GCLK_CLKCTRL_ID_DFLL48_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) DFLL48 */
-#define   GCLK_CLKCTRL_ID_FDPLL_Val       0x1ul  /**< \brief (GCLK_CLKCTRL) FDPLL */
-#define   GCLK_CLKCTRL_ID_FDPLL32K_Val    0x2ul  /**< \brief (GCLK_CLKCTRL) FDPLL32K */
-#define   GCLK_CLKCTRL_ID_WDT_Val         0x3ul  /**< \brief (GCLK_CLKCTRL) WDT */
-#define   GCLK_CLKCTRL_ID_RTC_Val         0x4ul  /**< \brief (GCLK_CLKCTRL) RTC */
-#define   GCLK_CLKCTRL_ID_EIC_Val         0x5ul  /**< \brief (GCLK_CLKCTRL) EIC */
-#define   GCLK_CLKCTRL_ID_USB_Val         0x6ul  /**< \brief (GCLK_CLKCTRL) USB */
-#define   GCLK_CLKCTRL_ID_EVSYS_0_Val     0x7ul  /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
-#define   GCLK_CLKCTRL_ID_EVSYS_1_Val     0x8ul  /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
-#define   GCLK_CLKCTRL_ID_EVSYS_2_Val     0x9ul  /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
-#define   GCLK_CLKCTRL_ID_EVSYS_3_Val     0xAul  /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
-#define   GCLK_CLKCTRL_ID_EVSYS_4_Val     0xBul  /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
-#define   GCLK_CLKCTRL_ID_EVSYS_5_Val     0xCul  /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
-#define   GCLK_CLKCTRL_ID_EVSYS_6_Val     0xDul  /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
-#define   GCLK_CLKCTRL_ID_EVSYS_7_Val     0xEul  /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
-#define   GCLK_CLKCTRL_ID_EVSYS_8_Val     0xFul  /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
-#define   GCLK_CLKCTRL_ID_EVSYS_9_Val     0x10ul  /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
-#define   GCLK_CLKCTRL_ID_EVSYS_10_Val    0x11ul  /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
-#define   GCLK_CLKCTRL_ID_EVSYS_11_Val    0x12ul  /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
-#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul  /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
-#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul  /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul  /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul  /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul  /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul  /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul  /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
-#define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val   0x1Aul  /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
-#define   GCLK_CLKCTRL_ID_TCC2_TC3_Val    0x1Bul  /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
-#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     0x1Cul  /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
-#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     0x1Dul  /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
-#define   GCLK_CLKCTRL_ID_ADC_Val         0x1Eul  /**< \brief (GCLK_CLKCTRL) ADC */
-#define   GCLK_CLKCTRL_ID_AC_DIG_Val      0x1Ful  /**< \brief (GCLK_CLKCTRL) AC_DIG */
-#define   GCLK_CLKCTRL_ID_AC_ANA_Val      0x20ul  /**< \brief (GCLK_CLKCTRL) AC_ANA */
-#define   GCLK_CLKCTRL_ID_DAC_Val         0x21ul  /**< \brief (GCLK_CLKCTRL) DAC */
-#define   GCLK_CLKCTRL_ID_PTC_Val         0x22ul  /**< \brief (GCLK_CLKCTRL) PTC */
-#define   GCLK_CLKCTRL_ID_I2S_0_Val       0x23ul  /**< \brief (GCLK_CLKCTRL) I2S_0 */
-#define   GCLK_CLKCTRL_ID_I2S_1_Val       0x24ul  /**< \brief (GCLK_CLKCTRL) I2S_1 */
-#define GCLK_CLKCTRL_ID_DFLL48      (GCLK_CLKCTRL_ID_DFLL48_Val    << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_FDPLL       (GCLK_CLKCTRL_ID_FDPLL_Val     << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_FDPLL32K    (GCLK_CLKCTRL_ID_FDPLL32K_Val  << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_WDT         (GCLK_CLKCTRL_ID_WDT_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_RTC         (GCLK_CLKCTRL_ID_RTC_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EIC         (GCLK_CLKCTRL_ID_EIC_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_USB         (GCLK_CLKCTRL_ID_USB_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_0     (GCLK_CLKCTRL_ID_EVSYS_0_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_1     (GCLK_CLKCTRL_ID_EVSYS_1_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_2     (GCLK_CLKCTRL_ID_EVSYS_2_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_3     (GCLK_CLKCTRL_ID_EVSYS_3_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_4     (GCLK_CLKCTRL_ID_EVSYS_4_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_5     (GCLK_CLKCTRL_ID_EVSYS_5_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_6     (GCLK_CLKCTRL_ID_EVSYS_6_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_7     (GCLK_CLKCTRL_ID_EVSYS_7_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_8     (GCLK_CLKCTRL_ID_EVSYS_8_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_9     (GCLK_CLKCTRL_ID_EVSYS_9_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_10    (GCLK_CLKCTRL_ID_EVSYS_10_Val  << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_EVSYS_11    (GCLK_CLKCTRL_ID_EVSYS_11_Val  << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_TCC0_TCC1   (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_TCC2_TC3    (GCLK_CLKCTRL_ID_TCC2_TC3_Val  << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_TC4_TC5     (GCLK_CLKCTRL_ID_TC4_TC5_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_TC6_TC7     (GCLK_CLKCTRL_ID_TC6_TC7_Val   << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_ADC         (GCLK_CLKCTRL_ID_ADC_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_AC_DIG      (GCLK_CLKCTRL_ID_AC_DIG_Val    << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_AC_ANA      (GCLK_CLKCTRL_ID_AC_ANA_Val    << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_DAC         (GCLK_CLKCTRL_ID_DAC_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_PTC         (GCLK_CLKCTRL_ID_PTC_Val       << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_I2S_0       (GCLK_CLKCTRL_ID_I2S_0_Val     << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_ID_I2S_1       (GCLK_CLKCTRL_ID_I2S_1_Val     << GCLK_CLKCTRL_ID_Pos)
-#define GCLK_CLKCTRL_GEN_Pos        8            /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
-#define GCLK_CLKCTRL_GEN_Msk        (0xFul << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN(value)     (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
-#define   GCLK_CLKCTRL_GEN_GCLK0_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
-#define   GCLK_CLKCTRL_GEN_GCLK1_Val      0x1ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
-#define   GCLK_CLKCTRL_GEN_GCLK2_Val      0x2ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
-#define   GCLK_CLKCTRL_GEN_GCLK3_Val      0x3ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
-#define   GCLK_CLKCTRL_GEN_GCLK4_Val      0x4ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
-#define   GCLK_CLKCTRL_GEN_GCLK5_Val      0x5ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
-#define   GCLK_CLKCTRL_GEN_GCLK6_Val      0x6ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
-#define   GCLK_CLKCTRL_GEN_GCLK7_Val      0x7ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
-#define GCLK_CLKCTRL_GEN_GCLK0      (GCLK_CLKCTRL_GEN_GCLK0_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK1      (GCLK_CLKCTRL_GEN_GCLK1_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK2      (GCLK_CLKCTRL_GEN_GCLK2_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK3      (GCLK_CLKCTRL_GEN_GCLK3_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK4      (GCLK_CLKCTRL_GEN_GCLK4_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK5      (GCLK_CLKCTRL_GEN_GCLK5_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK6      (GCLK_CLKCTRL_GEN_GCLK6_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_GEN_GCLK7      (GCLK_CLKCTRL_GEN_GCLK7_Val    << GCLK_CLKCTRL_GEN_Pos)
-#define GCLK_CLKCTRL_CLKEN_Pos      14           /**< \brief (GCLK_CLKCTRL) Clock Enable */
-#define GCLK_CLKCTRL_CLKEN          (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
-#define GCLK_CLKCTRL_WRTLOCK_Pos    15           /**< \brief (GCLK_CLKCTRL) Write Lock */
-#define GCLK_CLKCTRL_WRTLOCK        (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
-#define GCLK_CLKCTRL_MASK           0xCF3Ful     /**< \brief (GCLK_CLKCTRL) MASK Register */
-
-/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t SRC:5;            /*!< bit:  8..12  Source Select                      */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t GENEN:1;          /*!< bit:     16  Generic Clock Generator Enable     */
-    uint32_t IDC:1;            /*!< bit:     17  Improve Duty Cycle                 */
-    uint32_t OOV:1;            /*!< bit:     18  Output Off Value                   */
-    uint32_t OE:1;             /*!< bit:     19  Output Enable                      */
-    uint32_t DIVSEL:1;         /*!< bit:     20  Divide Selection                   */
-    uint32_t RUNSTDBY:1;       /*!< bit:     21  Run in Standby                     */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} GCLK_GENCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_GENCTRL_OFFSET         0x4          /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
-#define GCLK_GENCTRL_RESETVALUE     0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
-
-#define GCLK_GENCTRL_ID_Pos         0            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
-#define GCLK_GENCTRL_ID_Msk         (0xFul << GCLK_GENCTRL_ID_Pos)
-#define GCLK_GENCTRL_ID(value)      (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
-#define GCLK_GENCTRL_SRC_Pos        8            /**< \brief (GCLK_GENCTRL) Source Select */
-#define GCLK_GENCTRL_SRC_Msk        (0x1Ful << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
-#define   GCLK_GENCTRL_SRC_XOSC_Val       0x0ul  /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
-#define   GCLK_GENCTRL_SRC_GCLKIN_Val     0x1ul  /**< \brief (GCLK_GENCTRL) Generator input pad */
-#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   0x2ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
-#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  0x3ul  /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
-#define   GCLK_GENCTRL_SRC_OSC32K_Val     0x4ul  /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
-#define   GCLK_GENCTRL_SRC_XOSC32K_Val    0x5ul  /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
-#define   GCLK_GENCTRL_SRC_OSC8M_Val      0x6ul  /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
-#define   GCLK_GENCTRL_SRC_DFLL48M_Val    0x7ul  /**< \brief (GCLK_GENCTRL) DFLL48M output */
-#define   GCLK_GENCTRL_SRC_FDPLL_Val      0x8ul  /**< \brief (GCLK_GENCTRL) FDPLL output */
-#define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_OSC8M      (GCLK_GENCTRL_SRC_OSC8M_Val    << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_FDPLL      (GCLK_GENCTRL_SRC_FDPLL_Val    << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_GENEN_Pos      16           /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
-#define GCLK_GENCTRL_GENEN          (0x1ul << GCLK_GENCTRL_GENEN_Pos)
-#define GCLK_GENCTRL_IDC_Pos        17           /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
-#define GCLK_GENCTRL_IDC            (0x1ul << GCLK_GENCTRL_IDC_Pos)
-#define GCLK_GENCTRL_OOV_Pos        18           /**< \brief (GCLK_GENCTRL) Output Off Value */
-#define GCLK_GENCTRL_OOV            (0x1ul << GCLK_GENCTRL_OOV_Pos)
-#define GCLK_GENCTRL_OE_Pos         19           /**< \brief (GCLK_GENCTRL) Output Enable */
-#define GCLK_GENCTRL_OE             (0x1ul << GCLK_GENCTRL_OE_Pos)
-#define GCLK_GENCTRL_DIVSEL_Pos     20           /**< \brief (GCLK_GENCTRL) Divide Selection */
-#define GCLK_GENCTRL_DIVSEL         (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
-#define GCLK_GENCTRL_RUNSTDBY_Pos   21           /**< \brief (GCLK_GENCTRL) Run in Standby */
-#define GCLK_GENCTRL_RUNSTDBY       (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
-#define GCLK_GENCTRL_MASK           0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
-
-/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t DIV:16;           /*!< bit:  8..23  Division Factor                    */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} GCLK_GENDIV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_GENDIV_OFFSET          0x8          /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
-#define GCLK_GENDIV_RESETVALUE      0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
-
-#define GCLK_GENDIV_ID_Pos          0            /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
-#define GCLK_GENDIV_ID_Msk          (0xFul << GCLK_GENDIV_ID_Pos)
-#define GCLK_GENDIV_ID(value)       (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
-#define GCLK_GENDIV_DIV_Pos         8            /**< \brief (GCLK_GENDIV) Division Factor */
-#define GCLK_GENDIV_DIV_Msk         (0xFFFFul << GCLK_GENDIV_DIV_Pos)
-#define GCLK_GENDIV_DIV(value)      (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
-#define GCLK_GENDIV_MASK            0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
-
-/** \brief GCLK hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO GCLK_CTRL_Type            CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
-  __I  GCLK_STATUS_Type          STATUS;      /**< \brief Offset: 0x1 (R/   8) Status */
-  __IO GCLK_CLKCTRL_Type         CLKCTRL;     /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
-  __IO GCLK_GENCTRL_Type         GENCTRL;     /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
-  __IO GCLK_GENDIV_Type          GENDIV;      /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
-} Gclk;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_GCLK_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_COMPONENT_
+#define _SAMD21_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD21_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK                    0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET            0x0          /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE        0x00ul       /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos         0            /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST             (0x1ul << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK              0x01ul       /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET          0x1          /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE      0x00ul       /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos    7            /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY        (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK            0x80ul       /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:6;             /*!< bit:  0.. 5  Generic Clock Selection ID         */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t GEN:4;            /*!< bit:  8..11  Generic Clock Generator            */
+    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint16_t CLKEN:1;          /*!< bit:     14  Clock Enable                       */
+    uint16_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET         0x2          /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE     0x0000ul     /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos         0            /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk         (0x3Ful << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value)      (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
+#define   GCLK_CLKCTRL_ID_DFLL48_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) DFLL48 */
+#define   GCLK_CLKCTRL_ID_FDPLL_Val       0x1ul  /**< \brief (GCLK_CLKCTRL) FDPLL */
+#define   GCLK_CLKCTRL_ID_FDPLL32K_Val    0x2ul  /**< \brief (GCLK_CLKCTRL) FDPLL32K */
+#define   GCLK_CLKCTRL_ID_WDT_Val         0x3ul  /**< \brief (GCLK_CLKCTRL) WDT */
+#define   GCLK_CLKCTRL_ID_RTC_Val         0x4ul  /**< \brief (GCLK_CLKCTRL) RTC */
+#define   GCLK_CLKCTRL_ID_EIC_Val         0x5ul  /**< \brief (GCLK_CLKCTRL) EIC */
+#define   GCLK_CLKCTRL_ID_USB_Val         0x6ul  /**< \brief (GCLK_CLKCTRL) USB */
+#define   GCLK_CLKCTRL_ID_EVSYS_0_Val     0x7ul  /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
+#define   GCLK_CLKCTRL_ID_EVSYS_1_Val     0x8ul  /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
+#define   GCLK_CLKCTRL_ID_EVSYS_2_Val     0x9ul  /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
+#define   GCLK_CLKCTRL_ID_EVSYS_3_Val     0xAul  /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
+#define   GCLK_CLKCTRL_ID_EVSYS_4_Val     0xBul  /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
+#define   GCLK_CLKCTRL_ID_EVSYS_5_Val     0xCul  /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
+#define   GCLK_CLKCTRL_ID_EVSYS_6_Val     0xDul  /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
+#define   GCLK_CLKCTRL_ID_EVSYS_7_Val     0xEul  /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
+#define   GCLK_CLKCTRL_ID_EVSYS_8_Val     0xFul  /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
+#define   GCLK_CLKCTRL_ID_EVSYS_9_Val     0x10ul  /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
+#define   GCLK_CLKCTRL_ID_EVSYS_10_Val    0x11ul  /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
+#define   GCLK_CLKCTRL_ID_EVSYS_11_Val    0x12ul  /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
+#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul  /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
+#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul  /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul  /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul  /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul  /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul  /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul  /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val   0x1Aul  /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
+#define   GCLK_CLKCTRL_ID_TCC2_TC3_Val    0x1Bul  /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
+#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     0x1Cul  /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
+#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     0x1Dul  /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
+#define   GCLK_CLKCTRL_ID_ADC_Val         0x1Eul  /**< \brief (GCLK_CLKCTRL) ADC */
+#define   GCLK_CLKCTRL_ID_AC_DIG_Val      0x1Ful  /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define   GCLK_CLKCTRL_ID_AC_ANA_Val      0x20ul  /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define   GCLK_CLKCTRL_ID_DAC_Val         0x21ul  /**< \brief (GCLK_CLKCTRL) DAC */
+#define   GCLK_CLKCTRL_ID_PTC_Val         0x22ul  /**< \brief (GCLK_CLKCTRL) PTC */
+#define   GCLK_CLKCTRL_ID_I2S_0_Val       0x23ul  /**< \brief (GCLK_CLKCTRL) I2S_0 */
+#define   GCLK_CLKCTRL_ID_I2S_1_Val       0x24ul  /**< \brief (GCLK_CLKCTRL) I2S_1 */
+#define GCLK_CLKCTRL_ID_DFLL48      (GCLK_CLKCTRL_ID_DFLL48_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL       (GCLK_CLKCTRL_ID_FDPLL_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL32K    (GCLK_CLKCTRL_ID_FDPLL32K_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_WDT         (GCLK_CLKCTRL_ID_WDT_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_RTC         (GCLK_CLKCTRL_ID_RTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EIC         (GCLK_CLKCTRL_ID_EIC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_USB         (GCLK_CLKCTRL_ID_USB_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_0     (GCLK_CLKCTRL_ID_EVSYS_0_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_1     (GCLK_CLKCTRL_ID_EVSYS_1_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_2     (GCLK_CLKCTRL_ID_EVSYS_2_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_3     (GCLK_CLKCTRL_ID_EVSYS_3_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_4     (GCLK_CLKCTRL_ID_EVSYS_4_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_5     (GCLK_CLKCTRL_ID_EVSYS_5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_6     (GCLK_CLKCTRL_ID_EVSYS_6_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_7     (GCLK_CLKCTRL_ID_EVSYS_7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_8     (GCLK_CLKCTRL_ID_EVSYS_8_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_9     (GCLK_CLKCTRL_ID_EVSYS_9_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_10    (GCLK_CLKCTRL_ID_EVSYS_10_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_11    (GCLK_CLKCTRL_ID_EVSYS_11_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC0_TCC1   (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC2_TC3    (GCLK_CLKCTRL_ID_TCC2_TC3_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC4_TC5     (GCLK_CLKCTRL_ID_TC4_TC5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC6_TC7     (GCLK_CLKCTRL_ID_TC6_TC7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_ADC         (GCLK_CLKCTRL_ID_ADC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_DIG      (GCLK_CLKCTRL_ID_AC_DIG_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_ANA      (GCLK_CLKCTRL_ID_AC_ANA_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_DAC         (GCLK_CLKCTRL_ID_DAC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_PTC         (GCLK_CLKCTRL_ID_PTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_0       (GCLK_CLKCTRL_ID_I2S_0_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_1       (GCLK_CLKCTRL_ID_I2S_1_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_GEN_Pos        8            /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk        (0xFul << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value)     (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
+#define   GCLK_CLKCTRL_GEN_GCLK0_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define   GCLK_CLKCTRL_GEN_GCLK1_Val      0x1ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define   GCLK_CLKCTRL_GEN_GCLK2_Val      0x2ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define   GCLK_CLKCTRL_GEN_GCLK3_Val      0x3ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define   GCLK_CLKCTRL_GEN_GCLK4_Val      0x4ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define   GCLK_CLKCTRL_GEN_GCLK5_Val      0x5ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define   GCLK_CLKCTRL_GEN_GCLK6_Val      0x6ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define   GCLK_CLKCTRL_GEN_GCLK7_Val      0x7ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0      (GCLK_CLKCTRL_GEN_GCLK0_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1      (GCLK_CLKCTRL_GEN_GCLK1_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2      (GCLK_CLKCTRL_GEN_GCLK2_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3      (GCLK_CLKCTRL_GEN_GCLK3_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4      (GCLK_CLKCTRL_GEN_GCLK4_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5      (GCLK_CLKCTRL_GEN_GCLK5_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6      (GCLK_CLKCTRL_GEN_GCLK6_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7      (GCLK_CLKCTRL_GEN_GCLK7_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos      14           /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN          (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos    15           /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK        (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK           0xCF3Ful     /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SRC:5;            /*!< bit:  8..12  Source Select                      */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t GENEN:1;          /*!< bit:     16  Generic Clock Generator Enable     */
+    uint32_t IDC:1;            /*!< bit:     17  Improve Duty Cycle                 */
+    uint32_t OOV:1;            /*!< bit:     18  Output Off Value                   */
+    uint32_t OE:1;             /*!< bit:     19  Output Enable                      */
+    uint32_t DIVSEL:1;         /*!< bit:     20  Divide Selection                   */
+    uint32_t RUNSTDBY:1;       /*!< bit:     21  Run in Standby                     */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET         0x4          /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos         0            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk         (0xFul << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value)      (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
+#define GCLK_GENCTRL_SRC_Pos        8            /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk        (0x1Ful << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define   GCLK_GENCTRL_SRC_XOSC_Val       0x0ul  /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     0x1ul  /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   0x2ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  0x3ul  /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC32K_Val     0x4ul  /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    0x5ul  /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC8M_Val      0x6ul  /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val    0x7ul  /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define   GCLK_GENCTRL_SRC_FDPLL_Val      0x8ul  /**< \brief (GCLK_GENCTRL) FDPLL output */
+#define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M      (GCLK_GENCTRL_SRC_OSC8M_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_FDPLL      (GCLK_GENCTRL_SRC_FDPLL_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos      16           /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN          (0x1ul << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos        17           /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC            (0x1ul << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos        18           /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV            (0x1ul << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos         19           /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE             (0x1ul << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos     20           /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL         (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos   21           /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY       (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK           0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t DIV:16;           /*!< bit:  8..23  Division Factor                    */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET          0x8          /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE      0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos          0            /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk          (0xFul << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value)       (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
+#define GCLK_GENDIV_DIV_Pos         8            /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk         (0xFFFFul << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value)      (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
+#define GCLK_GENDIV_MASK            0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GCLK_CTRL_Type            CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __I  GCLK_STATUS_Type          STATUS;      /**< \brief Offset: 0x1 (R/   8) Status */
+  __IO GCLK_CLKCTRL_Type         CLKCTRL;     /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+  __IO GCLK_GENCTRL_Type         GENCTRL;     /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+  __IO GCLK_GENDIV_Type          GENDIV;      /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_GCLK_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h
index 9b38d64..89279a1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/hmatrixb.h
@@ -1,108 +1,108 @@
-/**
- * \file
- *
- * \brief Component description for HMATRIXB
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_HMATRIXB_COMPONENT_
-#define _SAMD21_HMATRIXB_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR HMATRIXB */
-/* ========================================================================== */
-/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
-/*@{*/
-
-#define HMATRIXB_I7638
-#define REV_HMATRIXB                0x212
-
-/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} HMATRIXB_PRAS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
-#define HMATRIXB_PRAS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
-
-#define HMATRIXB_PRAS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
-
-/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} HMATRIXB_PRBS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
-#define HMATRIXB_PRBS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
-
-#define HMATRIXB_PRBS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
-
-/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SFR:32;           /*!< bit:  0..31  Special Function Register          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} HMATRIXB_SFR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_SFR_OFFSET         0x110        /**< \brief (HMATRIXB_SFR offset) Special Function */
-#define HMATRIXB_SFR_RESETVALUE     0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */
-
-#define HMATRIXB_SFR_SFR_Pos        0            /**< \brief (HMATRIXB_SFR) Special Function Register */
-#define HMATRIXB_SFR_SFR_Msk        (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
-#define HMATRIXB_SFR_SFR(value)     (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
-#define HMATRIXB_SFR_MASK           0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
-
-/** \brief HmatrixbPrs hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO HMATRIXB_PRAS_Type        PRAS;        /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
-  __IO HMATRIXB_PRBS_Type        PRBS;        /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
-} HmatrixbPrs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief HMATRIXB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-       RoReg8                    Reserved1[0x80];
-       HmatrixbPrs               Prs[16];     /**< \brief Offset: 0x080 HmatrixbPrs groups */
-       RoReg8                    Reserved2[0x10];
-  __IO HMATRIXB_SFR_Type         SFR[16];     /**< \brief Offset: 0x110 (R/W 32) Special Function */
-} Hmatrixb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_HMATRIXB_COMPONENT_
+#define _SAMD21_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB                0x212
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SFR:32;           /*!< bit:  0..31  Special Function Register          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_SFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_SFR_OFFSET         0x110        /**< \brief (HMATRIXB_SFR offset) Special Function */
+#define HMATRIXB_SFR_RESETVALUE     0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */
+
+#define HMATRIXB_SFR_SFR_Pos        0            /**< \brief (HMATRIXB_SFR) Special Function Register */
+#define HMATRIXB_SFR_SFR_Msk        (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
+#define HMATRIXB_SFR_SFR(value)     (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
+#define HMATRIXB_SFR_MASK           0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO HMATRIXB_PRAS_Type        PRAS;        /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+  __IO HMATRIXB_PRBS_Type        PRBS;        /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       RoReg8                    Reserved1[0x80];
+       HmatrixbPrs               Prs[16];     /**< \brief Offset: 0x080 HmatrixbPrs groups */
+       RoReg8                    Reserved2[0x10];
+  __IO HMATRIXB_SFR_Type         SFR[16];     /**< \brief Offset: 0x110 (R/W 32) Special Function */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h
index 67de29b..6a1eaa1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h
@@ -1,629 +1,629 @@
-/**
- * \file
- *
- * \brief Component description for I2S
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_I2S_COMPONENT_
-#define _SAMD21_I2S_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR I2S */
-/* ========================================================================== */
-/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
-/*@{*/
-
-#define I2S_U2224
-#define REV_I2S                     0x110
-
-/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable                */
-    uint8_t  CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable                */
-    uint8_t  SEREN0:1;         /*!< bit:      4  Serializer 0 Enable                */
-    uint8_t  SEREN1:1;         /*!< bit:      5  Serializer 1 Enable                */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable                */
-    uint8_t  SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable                */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} I2S_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
-#define I2S_CTRLA_RESETVALUE        0x00ul       /**< \brief (I2S_CTRLA reset_value) Control A */
-
-#define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
-#define I2S_CTRLA_SWRST             (0x1ul << I2S_CTRLA_SWRST_Pos)
-#define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
-#define I2S_CTRLA_ENABLE            (0x1ul << I2S_CTRLA_ENABLE_Pos)
-#define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
-#define I2S_CTRLA_CKEN0             (1 << I2S_CTRLA_CKEN0_Pos)
-#define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
-#define I2S_CTRLA_CKEN1             (1 << I2S_CTRLA_CKEN1_Pos)
-#define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
-#define I2S_CTRLA_CKEN_Msk          (0x3ul << I2S_CTRLA_CKEN_Pos)
-#define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
-#define I2S_CTRLA_SEREN0_Pos        4            /**< \brief (I2S_CTRLA) Serializer 0 Enable */
-#define I2S_CTRLA_SEREN0            (1 << I2S_CTRLA_SEREN0_Pos)
-#define I2S_CTRLA_SEREN1_Pos        5            /**< \brief (I2S_CTRLA) Serializer 1 Enable */
-#define I2S_CTRLA_SEREN1            (1 << I2S_CTRLA_SEREN1_Pos)
-#define I2S_CTRLA_SEREN_Pos         4            /**< \brief (I2S_CTRLA) Serializer x Enable */
-#define I2S_CTRLA_SEREN_Msk         (0x3ul << I2S_CTRLA_SEREN_Pos)
-#define I2S_CTRLA_SEREN(value)      (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
-#define I2S_CTRLA_MASK              0x3Ful       /**< \brief (I2S_CTRLA) MASK Register */
-
-/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SLOTSIZE:2;       /*!< bit:  0.. 1  Slot Size                          */
-    uint32_t NBSLOTS:3;        /*!< bit:  2.. 4  Number of Slots in Frame           */
-    uint32_t FSWIDTH:2;        /*!< bit:  5.. 6  Frame Sync Width                   */
-    uint32_t BITDELAY:1;       /*!< bit:      7  Data Delay from Frame Sync         */
-    uint32_t FSSEL:1;          /*!< bit:      8  Frame Sync Select                  */
-    uint32_t :2;               /*!< bit:  9..10  Reserved                           */
-    uint32_t FSINV:1;          /*!< bit:     11  Frame Sync Invert                  */
-    uint32_t SCKSEL:1;         /*!< bit:     12  Serial Clock Select                */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t MCKSEL:1;         /*!< bit:     16  Master Clock Select                */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t MCKEN:1;          /*!< bit:     18  Master Clock Enable                */
-    uint32_t MCKDIV:5;         /*!< bit: 19..23  Master Clock Division Factor       */
-    uint32_t MCKOUTDIV:5;      /*!< bit: 24..28  Master Clock Output Division Factor */
-    uint32_t FSOUTINV:1;       /*!< bit:     29  Frame Sync Output Invert           */
-    uint32_t SCKOUTINV:1;      /*!< bit:     30  Serial Clock Output Invert         */
-    uint32_t MCKOUTINV:1;      /*!< bit:     31  Master Clock Output Invert         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_CLKCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
-#define I2S_CLKCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
-
-#define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
-#define I2S_CLKCTRL_SLOTSIZE_Msk    (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
-#define   I2S_CLKCTRL_SLOTSIZE_8_Val      0x0ul  /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_16_Val     0x1ul  /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_24_Val     0x2ul  /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_32_Val     0x3ul  /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
-#define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
-#define I2S_CLKCTRL_NBSLOTS_Msk     (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
-#define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
-#define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
-#define I2S_CLKCTRL_FSWIDTH_Msk     (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
-#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
-#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    0x1ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
-#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     0x2ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
-#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   0x3ul  /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
-#define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
-#define I2S_CLKCTRL_BITDELAY        (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
-#define   I2S_CLKCTRL_BITDELAY_LJ_Val     0x0ul  /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
-#define   I2S_CLKCTRL_BITDELAY_I2S_Val    0x1ul  /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
-#define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
-#define I2S_CLKCTRL_FSSEL           (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
-#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
-#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     0x1ul  /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
-#define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSINV_Pos       11           /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
-#define I2S_CLKCTRL_FSINV           (0x1ul << I2S_CLKCTRL_FSINV_Pos)
-#define I2S_CLKCTRL_SCKSEL_Pos      12           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
-#define I2S_CLKCTRL_SCKSEL          (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
-#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   0x0ul  /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
-#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
-#define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_MCKSEL_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Select */
-#define I2S_CLKCTRL_MCKSEL          (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
-#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     0x0ul  /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
-#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
-#define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKEN_Pos       18           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
-#define I2S_CLKCTRL_MCKEN           (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
-#define I2S_CLKCTRL_MCKDIV_Pos      19           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
-#define I2S_CLKCTRL_MCKDIV_Msk      (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
-#define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
-#define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
-#define I2S_CLKCTRL_MCKOUTDIV_Msk   (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
-#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
-#define I2S_CLKCTRL_FSOUTINV_Pos    29           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
-#define I2S_CLKCTRL_FSOUTINV        (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
-#define I2S_CLKCTRL_SCKOUTINV_Pos   30           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
-#define I2S_CLKCTRL_SCKOUTINV       (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
-#define I2S_CLKCTRL_MCKOUTINV_Pos   31           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
-#define I2S_CLKCTRL_MCKOUTINV       (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
-#define I2S_CLKCTRL_MASK            0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
-
-/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
-    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
-    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
-    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
-    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
-#define I2S_INTENCLR_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
-#define I2S_INTENCLR_RXRDY0         (1 << I2S_INTENCLR_RXRDY0_Pos)
-#define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
-#define I2S_INTENCLR_RXRDY1         (1 << I2S_INTENCLR_RXRDY1_Pos)
-#define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
-#define I2S_INTENCLR_RXRDY_Msk      (0x3ul << I2S_INTENCLR_RXRDY_Pos)
-#define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
-#define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
-#define I2S_INTENCLR_RXOR0          (1 << I2S_INTENCLR_RXOR0_Pos)
-#define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
-#define I2S_INTENCLR_RXOR1          (1 << I2S_INTENCLR_RXOR1_Pos)
-#define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
-#define I2S_INTENCLR_RXOR_Msk       (0x3ul << I2S_INTENCLR_RXOR_Pos)
-#define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
-#define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
-#define I2S_INTENCLR_TXRDY0         (1 << I2S_INTENCLR_TXRDY0_Pos)
-#define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
-#define I2S_INTENCLR_TXRDY1         (1 << I2S_INTENCLR_TXRDY1_Pos)
-#define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
-#define I2S_INTENCLR_TXRDY_Msk      (0x3ul << I2S_INTENCLR_TXRDY_Pos)
-#define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
-#define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
-#define I2S_INTENCLR_TXUR0          (1 << I2S_INTENCLR_TXUR0_Pos)
-#define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
-#define I2S_INTENCLR_TXUR1          (1 << I2S_INTENCLR_TXUR1_Pos)
-#define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENCLR_TXUR_Msk       (0x3ul << I2S_INTENCLR_TXUR_Pos)
-#define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
-#define I2S_INTENCLR_MASK           0x3333ul     /**< \brief (I2S_INTENCLR) MASK Register */
-
-/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
-    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
-    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
-    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
-    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
-#define I2S_INTENSET_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
-
-#define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
-#define I2S_INTENSET_RXRDY0         (1 << I2S_INTENSET_RXRDY0_Pos)
-#define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
-#define I2S_INTENSET_RXRDY1         (1 << I2S_INTENSET_RXRDY1_Pos)
-#define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
-#define I2S_INTENSET_RXRDY_Msk      (0x3ul << I2S_INTENSET_RXRDY_Pos)
-#define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
-#define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
-#define I2S_INTENSET_RXOR0          (1 << I2S_INTENSET_RXOR0_Pos)
-#define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
-#define I2S_INTENSET_RXOR1          (1 << I2S_INTENSET_RXOR1_Pos)
-#define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
-#define I2S_INTENSET_RXOR_Msk       (0x3ul << I2S_INTENSET_RXOR_Pos)
-#define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
-#define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
-#define I2S_INTENSET_TXRDY0         (1 << I2S_INTENSET_TXRDY0_Pos)
-#define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
-#define I2S_INTENSET_TXRDY1         (1 << I2S_INTENSET_TXRDY1_Pos)
-#define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
-#define I2S_INTENSET_TXRDY_Msk      (0x3ul << I2S_INTENSET_TXRDY_Pos)
-#define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
-#define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
-#define I2S_INTENSET_TXUR0          (1 << I2S_INTENSET_TXUR0_Pos)
-#define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
-#define I2S_INTENSET_TXUR1          (1 << I2S_INTENSET_TXUR1_Pos)
-#define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENSET_TXUR_Msk       (0x3ul << I2S_INTENSET_TXUR_Pos)
-#define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
-#define I2S_INTENSET_MASK           0x3333ul     /**< \brief (I2S_INTENSET) MASK Register */
-
-/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
-    __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
-    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0                  */
-    __I uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1                  */
-    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    __I uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0                   */
-    __I uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1                   */
-    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    __I uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0                */
-    __I uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1                */
-    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x                    */
-    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x                  */
-    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    __I uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x                   */
-    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    __I uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x                */
-    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
-#define I2S_INTFLAG_RESETVALUE      0x0000ul     /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
-#define I2S_INTFLAG_RXRDY0          (1 << I2S_INTFLAG_RXRDY0_Pos)
-#define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
-#define I2S_INTFLAG_RXRDY1          (1 << I2S_INTFLAG_RXRDY1_Pos)
-#define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
-#define I2S_INTFLAG_RXRDY_Msk       (0x3ul << I2S_INTFLAG_RXRDY_Pos)
-#define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
-#define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
-#define I2S_INTFLAG_RXOR0           (1 << I2S_INTFLAG_RXOR0_Pos)
-#define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
-#define I2S_INTFLAG_RXOR1           (1 << I2S_INTFLAG_RXOR1_Pos)
-#define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
-#define I2S_INTFLAG_RXOR_Msk        (0x3ul << I2S_INTFLAG_RXOR_Pos)
-#define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
-#define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
-#define I2S_INTFLAG_TXRDY0          (1 << I2S_INTFLAG_TXRDY0_Pos)
-#define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
-#define I2S_INTFLAG_TXRDY1          (1 << I2S_INTFLAG_TXRDY1_Pos)
-#define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
-#define I2S_INTFLAG_TXRDY_Msk       (0x3ul << I2S_INTFLAG_TXRDY_Pos)
-#define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
-#define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
-#define I2S_INTFLAG_TXUR0           (1 << I2S_INTFLAG_TXUR0_Pos)
-#define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
-#define I2S_INTFLAG_TXUR1           (1 << I2S_INTFLAG_TXUR1_Pos)
-#define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
-#define I2S_INTFLAG_TXUR_Msk        (0x3ul << I2S_INTFLAG_TXUR_Pos)
-#define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
-#define I2S_INTFLAG_MASK            0x3333ul     /**< \brief (I2S_INTFLAG) MASK Register */
-
-/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Status */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Status      */
-    uint16_t CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable Synchronization Status */
-    uint16_t CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable Synchronization Status */
-    uint16_t SEREN0:1;         /*!< bit:      4  Serializer 0 Enable Synchronization Status */
-    uint16_t SEREN1:1;         /*!< bit:      5  Serializer 1 Enable Synchronization Status */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t DATA0:1;          /*!< bit:      8  Data 0 Synchronization Status      */
-    uint16_t DATA1:1;          /*!< bit:      9  Data 1 Synchronization Status      */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable Synchronization Status */
-    uint16_t SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable Synchronization Status */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t DATA:2;           /*!< bit:  8.. 9  Data x Synchronization Status      */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
-#define I2S_SYNCBUSY_RESETVALUE     0x0000ul     /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
-
-#define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
-#define I2S_SYNCBUSY_SWRST          (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
-#define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
-#define I2S_SYNCBUSY_ENABLE         (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
-#define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN0          (1 << I2S_SYNCBUSY_CKEN0_Pos)
-#define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN1          (1 << I2S_SYNCBUSY_CKEN1_Pos)
-#define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN_Msk       (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
-#define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
-#define I2S_SYNCBUSY_SEREN0_Pos     4            /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
-#define I2S_SYNCBUSY_SEREN0         (1 << I2S_SYNCBUSY_SEREN0_Pos)
-#define I2S_SYNCBUSY_SEREN1_Pos     5            /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
-#define I2S_SYNCBUSY_SEREN1         (1 << I2S_SYNCBUSY_SEREN1_Pos)
-#define I2S_SYNCBUSY_SEREN_Pos      4            /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
-#define I2S_SYNCBUSY_SEREN_Msk      (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
-#define I2S_SYNCBUSY_SEREN(value)   (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
-#define I2S_SYNCBUSY_DATA0_Pos      8            /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
-#define I2S_SYNCBUSY_DATA0          (1 << I2S_SYNCBUSY_DATA0_Pos)
-#define I2S_SYNCBUSY_DATA1_Pos      9            /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
-#define I2S_SYNCBUSY_DATA1          (1 << I2S_SYNCBUSY_DATA1_Pos)
-#define I2S_SYNCBUSY_DATA_Pos       8            /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
-#define I2S_SYNCBUSY_DATA_Msk       (0x3ul << I2S_SYNCBUSY_DATA_Pos)
-#define I2S_SYNCBUSY_DATA(value)    (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
-#define I2S_SYNCBUSY_MASK           0x033Ful     /**< \brief (I2S_SYNCBUSY) MASK Register */
-
-/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SERMODE:2;        /*!< bit:  0.. 1  Serializer Mode                    */
-    uint32_t TXDEFAULT:2;      /*!< bit:  2.. 3  Line Default Line when Slot Disabled */
-    uint32_t TXSAME:1;         /*!< bit:      4  Transmit Data when Underrun        */
-    uint32_t CLKSEL:1;         /*!< bit:      5  Clock Unit Selection               */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
-    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
-    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
-    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
-    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
-    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
-    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
-    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
-    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
-    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
-    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
-    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
-    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
-    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
-    uint32_t RXLOOP:1;         /*!< bit:     26  Loop-back Test Mode                */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_SERCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_SERCTRL_OFFSET          0x20         /**< \brief (I2S_SERCTRL offset) Serializer n Control */
-#define I2S_SERCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
-
-#define I2S_SERCTRL_SERMODE_Pos     0            /**< \brief (I2S_SERCTRL) Serializer Mode */
-#define I2S_SERCTRL_SERMODE_Msk     (0x3ul << I2S_SERCTRL_SERMODE_Pos)
-#define I2S_SERCTRL_SERMODE(value)  (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
-#define   I2S_SERCTRL_SERMODE_RX_Val      0x0ul  /**< \brief (I2S_SERCTRL) Receive */
-#define   I2S_SERCTRL_SERMODE_TX_Val      0x1ul  /**< \brief (I2S_SERCTRL) Transmit */
-#define   I2S_SERCTRL_SERMODE_PDM2_Val    0x2ul  /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
-#define I2S_SERCTRL_SERMODE_RX      (I2S_SERCTRL_SERMODE_RX_Val    << I2S_SERCTRL_SERMODE_Pos)
-#define I2S_SERCTRL_SERMODE_TX      (I2S_SERCTRL_SERMODE_TX_Val    << I2S_SERCTRL_SERMODE_Pos)
-#define I2S_SERCTRL_SERMODE_PDM2    (I2S_SERCTRL_SERMODE_PDM2_Val  << I2S_SERCTRL_SERMODE_Pos)
-#define I2S_SERCTRL_TXDEFAULT_Pos   2            /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
-#define I2S_SERCTRL_TXDEFAULT_Msk   (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
-#define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
-#define   I2S_SERCTRL_TXDEFAULT_ZERO_Val  0x0ul  /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
-#define   I2S_SERCTRL_TXDEFAULT_ONE_Val   0x1ul  /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
-#define   I2S_SERCTRL_TXDEFAULT_HIZ_Val   0x3ul  /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
-#define I2S_SERCTRL_TXDEFAULT_ZERO  (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
-#define I2S_SERCTRL_TXDEFAULT_ONE   (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
-#define I2S_SERCTRL_TXDEFAULT_HIZ   (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
-#define I2S_SERCTRL_TXSAME_Pos      4            /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
-#define I2S_SERCTRL_TXSAME          (0x1ul << I2S_SERCTRL_TXSAME_Pos)
-#define   I2S_SERCTRL_TXSAME_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
-#define   I2S_SERCTRL_TXSAME_SAME_Val     0x1ul  /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
-#define I2S_SERCTRL_TXSAME_ZERO     (I2S_SERCTRL_TXSAME_ZERO_Val   << I2S_SERCTRL_TXSAME_Pos)
-#define I2S_SERCTRL_TXSAME_SAME     (I2S_SERCTRL_TXSAME_SAME_Val   << I2S_SERCTRL_TXSAME_Pos)
-#define I2S_SERCTRL_CLKSEL_Pos      5            /**< \brief (I2S_SERCTRL) Clock Unit Selection */
-#define I2S_SERCTRL_CLKSEL          (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
-#define   I2S_SERCTRL_CLKSEL_CLK0_Val     0x0ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
-#define   I2S_SERCTRL_CLKSEL_CLK1_Val     0x1ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
-#define I2S_SERCTRL_CLKSEL_CLK0     (I2S_SERCTRL_CLKSEL_CLK0_Val   << I2S_SERCTRL_CLKSEL_Pos)
-#define I2S_SERCTRL_CLKSEL_CLK1     (I2S_SERCTRL_CLKSEL_CLK1_Val   << I2S_SERCTRL_CLKSEL_Pos)
-#define I2S_SERCTRL_SLOTADJ_Pos     7            /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
-#define I2S_SERCTRL_SLOTADJ         (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
-#define   I2S_SERCTRL_SLOTADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
-#define   I2S_SERCTRL_SLOTADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
-#define I2S_SERCTRL_SLOTADJ_RIGHT   (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
-#define I2S_SERCTRL_SLOTADJ_LEFT    (I2S_SERCTRL_SLOTADJ_LEFT_Val  << I2S_SERCTRL_SLOTADJ_Pos)
-#define I2S_SERCTRL_DATASIZE_Pos    8            /**< \brief (I2S_SERCTRL) Data Word Size */
-#define I2S_SERCTRL_DATASIZE_Msk    (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
-#define   I2S_SERCTRL_DATASIZE_32_Val     0x0ul  /**< \brief (I2S_SERCTRL) 32 bits */
-#define   I2S_SERCTRL_DATASIZE_24_Val     0x1ul  /**< \brief (I2S_SERCTRL) 24 bits */
-#define   I2S_SERCTRL_DATASIZE_20_Val     0x2ul  /**< \brief (I2S_SERCTRL) 20 bits */
-#define   I2S_SERCTRL_DATASIZE_18_Val     0x3ul  /**< \brief (I2S_SERCTRL) 18 bits */
-#define   I2S_SERCTRL_DATASIZE_16_Val     0x4ul  /**< \brief (I2S_SERCTRL) 16 bits */
-#define   I2S_SERCTRL_DATASIZE_16C_Val    0x5ul  /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
-#define   I2S_SERCTRL_DATASIZE_8_Val      0x6ul  /**< \brief (I2S_SERCTRL) 8 bits */
-#define   I2S_SERCTRL_DATASIZE_8C_Val     0x7ul  /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
-#define I2S_SERCTRL_DATASIZE_32     (I2S_SERCTRL_DATASIZE_32_Val   << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_24     (I2S_SERCTRL_DATASIZE_24_Val   << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_20     (I2S_SERCTRL_DATASIZE_20_Val   << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_18     (I2S_SERCTRL_DATASIZE_18_Val   << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_16     (I2S_SERCTRL_DATASIZE_16_Val   << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_16C    (I2S_SERCTRL_DATASIZE_16C_Val  << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_8      (I2S_SERCTRL_DATASIZE_8_Val    << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_DATASIZE_8C     (I2S_SERCTRL_DATASIZE_8C_Val   << I2S_SERCTRL_DATASIZE_Pos)
-#define I2S_SERCTRL_WORDADJ_Pos     12           /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
-#define I2S_SERCTRL_WORDADJ         (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
-#define   I2S_SERCTRL_WORDADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
-#define   I2S_SERCTRL_WORDADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
-#define I2S_SERCTRL_WORDADJ_RIGHT   (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
-#define I2S_SERCTRL_WORDADJ_LEFT    (I2S_SERCTRL_WORDADJ_LEFT_Val  << I2S_SERCTRL_WORDADJ_Pos)
-#define I2S_SERCTRL_EXTEND_Pos      13           /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
-#define I2S_SERCTRL_EXTEND_Msk      (0x3ul << I2S_SERCTRL_EXTEND_Pos)
-#define I2S_SERCTRL_EXTEND(value)   (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
-#define   I2S_SERCTRL_EXTEND_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Extend with zeroes */
-#define   I2S_SERCTRL_EXTEND_ONE_Val      0x1ul  /**< \brief (I2S_SERCTRL) Extend with ones */
-#define   I2S_SERCTRL_EXTEND_MSBIT_Val    0x2ul  /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
-#define   I2S_SERCTRL_EXTEND_LSBIT_Val    0x3ul  /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
-#define I2S_SERCTRL_EXTEND_ZERO     (I2S_SERCTRL_EXTEND_ZERO_Val   << I2S_SERCTRL_EXTEND_Pos)
-#define I2S_SERCTRL_EXTEND_ONE      (I2S_SERCTRL_EXTEND_ONE_Val    << I2S_SERCTRL_EXTEND_Pos)
-#define I2S_SERCTRL_EXTEND_MSBIT    (I2S_SERCTRL_EXTEND_MSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
-#define I2S_SERCTRL_EXTEND_LSBIT    (I2S_SERCTRL_EXTEND_LSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
-#define I2S_SERCTRL_BITREV_Pos      15           /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
-#define I2S_SERCTRL_BITREV          (0x1ul << I2S_SERCTRL_BITREV_Pos)
-#define   I2S_SERCTRL_BITREV_MSBIT_Val    0x0ul  /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
-#define   I2S_SERCTRL_BITREV_LSBIT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
-#define I2S_SERCTRL_BITREV_MSBIT    (I2S_SERCTRL_BITREV_MSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
-#define I2S_SERCTRL_BITREV_LSBIT    (I2S_SERCTRL_BITREV_LSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
-#define I2S_SERCTRL_SLOTDIS0_Pos    16           /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS0        (1 << I2S_SERCTRL_SLOTDIS0_Pos)
-#define I2S_SERCTRL_SLOTDIS1_Pos    17           /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS1        (1 << I2S_SERCTRL_SLOTDIS1_Pos)
-#define I2S_SERCTRL_SLOTDIS2_Pos    18           /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS2        (1 << I2S_SERCTRL_SLOTDIS2_Pos)
-#define I2S_SERCTRL_SLOTDIS3_Pos    19           /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS3        (1 << I2S_SERCTRL_SLOTDIS3_Pos)
-#define I2S_SERCTRL_SLOTDIS4_Pos    20           /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS4        (1 << I2S_SERCTRL_SLOTDIS4_Pos)
-#define I2S_SERCTRL_SLOTDIS5_Pos    21           /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS5        (1 << I2S_SERCTRL_SLOTDIS5_Pos)
-#define I2S_SERCTRL_SLOTDIS6_Pos    22           /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS6        (1 << I2S_SERCTRL_SLOTDIS6_Pos)
-#define I2S_SERCTRL_SLOTDIS7_Pos    23           /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS7        (1 << I2S_SERCTRL_SLOTDIS7_Pos)
-#define I2S_SERCTRL_SLOTDIS_Pos     16           /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS_Msk     (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
-#define I2S_SERCTRL_SLOTDIS(value)  (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
-#define I2S_SERCTRL_MONO_Pos        24           /**< \brief (I2S_SERCTRL) Mono Mode */
-#define I2S_SERCTRL_MONO            (0x1ul << I2S_SERCTRL_MONO_Pos)
-#define   I2S_SERCTRL_MONO_STEREO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Normal mode */
-#define   I2S_SERCTRL_MONO_MONO_Val       0x1ul  /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
-#define I2S_SERCTRL_MONO_STEREO     (I2S_SERCTRL_MONO_STEREO_Val   << I2S_SERCTRL_MONO_Pos)
-#define I2S_SERCTRL_MONO_MONO       (I2S_SERCTRL_MONO_MONO_Val     << I2S_SERCTRL_MONO_Pos)
-#define I2S_SERCTRL_DMA_Pos         25           /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
-#define I2S_SERCTRL_DMA             (0x1ul << I2S_SERCTRL_DMA_Pos)
-#define   I2S_SERCTRL_DMA_SINGLE_Val      0x0ul  /**< \brief (I2S_SERCTRL) Single DMA channel */
-#define   I2S_SERCTRL_DMA_MULTIPLE_Val    0x1ul  /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
-#define I2S_SERCTRL_DMA_SINGLE      (I2S_SERCTRL_DMA_SINGLE_Val    << I2S_SERCTRL_DMA_Pos)
-#define I2S_SERCTRL_DMA_MULTIPLE    (I2S_SERCTRL_DMA_MULTIPLE_Val  << I2S_SERCTRL_DMA_Pos)
-#define I2S_SERCTRL_RXLOOP_Pos      26           /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
-#define I2S_SERCTRL_RXLOOP          (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
-#define I2S_SERCTRL_MASK            0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
-
-/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_DATA_OFFSET             0x30         /**< \brief (I2S_DATA offset) Data n */
-#define I2S_DATA_RESETVALUE         0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
-
-#define I2S_DATA_DATA_Pos           0            /**< \brief (I2S_DATA) Sample Data */
-#define I2S_DATA_DATA_Msk           (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
-#define I2S_DATA_DATA(value)        (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
-#define I2S_DATA_MASK               0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
-
-/** \brief I2S hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO I2S_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x3];
-  __IO I2S_CLKCTRL_Type          CLKCTRL[2];  /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
-  __IO I2S_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x2];
-  __IO I2S_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
-       RoReg8                    Reserved3[0x2];
-  __IO I2S_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x2];
-  __I  I2S_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x18 (R/  16) Synchronization Status */
-       RoReg8                    Reserved5[0x6];
-  __IO I2S_SERCTRL_Type          SERCTRL[2];  /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
-       RoReg8                    Reserved6[0x8];
-  __IO I2S_DATA_Type             DATA[2];     /**< \brief Offset: 0x30 (R/W 32) Data n */
-} I2s;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_I2S_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_COMPONENT_
+#define _SAMD21_I2S_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S                     0x110
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable                */
+    uint8_t  CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable                */
+    uint8_t  SEREN0:1;         /*!< bit:      4  Serializer 0 Enable                */
+    uint8_t  SEREN1:1;         /*!< bit:      5  Serializer 1 Enable                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable                */
+    uint8_t  SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE        0x00ul       /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST             (0x1ul << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE            (0x1ul << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0             (1 << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1             (1 << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk          (0x3ul << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_SEREN0_Pos        4            /**< \brief (I2S_CTRLA) Serializer 0 Enable */
+#define I2S_CTRLA_SEREN0            (1 << I2S_CTRLA_SEREN0_Pos)
+#define I2S_CTRLA_SEREN1_Pos        5            /**< \brief (I2S_CTRLA) Serializer 1 Enable */
+#define I2S_CTRLA_SEREN1            (1 << I2S_CTRLA_SEREN1_Pos)
+#define I2S_CTRLA_SEREN_Pos         4            /**< \brief (I2S_CTRLA) Serializer x Enable */
+#define I2S_CTRLA_SEREN_Msk         (0x3ul << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN(value)      (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
+#define I2S_CTRLA_MASK              0x3Ful       /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SLOTSIZE:2;       /*!< bit:  0.. 1  Slot Size                          */
+    uint32_t NBSLOTS:3;        /*!< bit:  2.. 4  Number of Slots in Frame           */
+    uint32_t FSWIDTH:2;        /*!< bit:  5.. 6  Frame Sync Width                   */
+    uint32_t BITDELAY:1;       /*!< bit:      7  Data Delay from Frame Sync         */
+    uint32_t FSSEL:1;          /*!< bit:      8  Frame Sync Select                  */
+    uint32_t :2;               /*!< bit:  9..10  Reserved                           */
+    uint32_t FSINV:1;          /*!< bit:     11  Frame Sync Invert                  */
+    uint32_t SCKSEL:1;         /*!< bit:     12  Serial Clock Select                */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t MCKSEL:1;         /*!< bit:     16  Master Clock Select                */
+    uint32_t :1;               /*!< bit:     17  Reserved                           */
+    uint32_t MCKEN:1;          /*!< bit:     18  Master Clock Enable                */
+    uint32_t MCKDIV:5;         /*!< bit: 19..23  Master Clock Division Factor       */
+    uint32_t MCKOUTDIV:5;      /*!< bit: 24..28  Master Clock Output Division Factor */
+    uint32_t FSOUTINV:1;       /*!< bit:     29  Frame Sync Output Invert           */
+    uint32_t SCKOUTINV:1;      /*!< bit:     30  Serial Clock Output Invert         */
+    uint32_t MCKOUTINV:1;      /*!< bit:     31  Master Clock Output Invert         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk    (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define   I2S_CLKCTRL_SLOTSIZE_8_Val      0x0ul  /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_16_Val     0x1ul  /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_24_Val     0x2ul  /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_32_Val     0x3ul  /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk     (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk     (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    0x1ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     0x2ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   0x3ul  /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY        (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
+#define   I2S_CLKCTRL_BITDELAY_LJ_Val     0x0ul  /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define   I2S_CLKCTRL_BITDELAY_I2S_Val    0x1ul  /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL           (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
+#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     0x1ul  /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos       11           /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV           (0x1ul << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos      12           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL          (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
+#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   0x0ul  /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL          (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
+#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     0x0ul  /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos       18           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN           (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos      19           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk      (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk   (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_FSOUTINV_Pos    29           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV        (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos   30           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV       (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos   31           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV       (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK            0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0         (1 << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1         (1 << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk      (0x3ul << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0          (1 << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1          (1 << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk       (0x3ul << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0         (1 << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1         (1 << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk      (0x3ul << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0          (1 << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1          (1 << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk       (0x3ul << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK           0x3333ul     /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0         (1 << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1         (1 << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk      (0x3ul << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0          (1 << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1          (1 << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk       (0x3ul << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0         (1 << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1         (1 << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk      (0x3ul << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0          (1 << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1          (1 << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk       (0x3ul << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK           0x3333ul     /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
+    __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0                  */
+    __I uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0                   */
+    __I uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0                */
+    __I uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE      0x0000ul     /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0          (1 << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1          (1 << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk       (0x3ul << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0           (1 << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1           (1 << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk        (0x3ul << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0          (1 << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1          (1 << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk       (0x3ul << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0           (1 << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1           (1 << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk        (0x3ul << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK            0x3333ul     /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Status */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Status      */
+    uint16_t CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable Synchronization Status */
+    uint16_t CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable Synchronization Status */
+    uint16_t SEREN0:1;         /*!< bit:      4  Serializer 0 Enable Synchronization Status */
+    uint16_t SEREN1:1;         /*!< bit:      5  Serializer 1 Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t DATA0:1;          /*!< bit:      8  Data 0 Synchronization Status      */
+    uint16_t DATA1:1;          /*!< bit:      9  Data 1 Synchronization Status      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable Synchronization Status */
+    uint16_t SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t DATA:2;           /*!< bit:  8.. 9  Data x Synchronization Status      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE     0x0000ul     /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST          (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE         (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0          (1 << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1          (1 << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk       (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_SEREN0_Pos     4            /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN0         (1 << I2S_SYNCBUSY_SEREN0_Pos)
+#define I2S_SYNCBUSY_SEREN1_Pos     5            /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN1         (1 << I2S_SYNCBUSY_SEREN1_Pos)
+#define I2S_SYNCBUSY_SEREN_Pos      4            /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN_Msk      (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN(value)   (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
+#define I2S_SYNCBUSY_DATA0_Pos      8            /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
+#define I2S_SYNCBUSY_DATA0          (1 << I2S_SYNCBUSY_DATA0_Pos)
+#define I2S_SYNCBUSY_DATA1_Pos      9            /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
+#define I2S_SYNCBUSY_DATA1          (1 << I2S_SYNCBUSY_DATA1_Pos)
+#define I2S_SYNCBUSY_DATA_Pos       8            /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
+#define I2S_SYNCBUSY_DATA_Msk       (0x3ul << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA(value)    (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
+#define I2S_SYNCBUSY_MASK           0x033Ful     /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERMODE:2;        /*!< bit:  0.. 1  Serializer Mode                    */
+    uint32_t TXDEFAULT:2;      /*!< bit:  2.. 3  Line Default Line when Slot Disabled */
+    uint32_t TXSAME:1;         /*!< bit:      4  Transmit Data when Underrun        */
+    uint32_t CLKSEL:1;         /*!< bit:      5  Clock Unit Selection               */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
+    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
+    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
+    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
+    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
+    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
+    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
+    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
+    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
+    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
+    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
+    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
+    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
+    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
+    uint32_t RXLOOP:1;         /*!< bit:     26  Loop-back Test Mode                */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_SERCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SERCTRL_OFFSET          0x20         /**< \brief (I2S_SERCTRL offset) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+
+#define I2S_SERCTRL_SERMODE_Pos     0            /**< \brief (I2S_SERCTRL) Serializer Mode */
+#define I2S_SERCTRL_SERMODE_Msk     (0x3ul << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE(value)  (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
+#define   I2S_SERCTRL_SERMODE_RX_Val      0x0ul  /**< \brief (I2S_SERCTRL) Receive */
+#define   I2S_SERCTRL_SERMODE_TX_Val      0x1ul  /**< \brief (I2S_SERCTRL) Transmit */
+#define   I2S_SERCTRL_SERMODE_PDM2_Val    0x2ul  /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_SERCTRL_SERMODE_RX      (I2S_SERCTRL_SERMODE_RX_Val    << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_TX      (I2S_SERCTRL_SERMODE_TX_Val    << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_PDM2    (I2S_SERCTRL_SERMODE_PDM2_Val  << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Pos   2            /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_Msk   (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
+#define   I2S_SERCTRL_TXDEFAULT_ZERO_Val  0x0ul  /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define   I2S_SERCTRL_TXDEFAULT_ONE_Val   0x1ul  /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define   I2S_SERCTRL_TXDEFAULT_HIZ_Val   0x3ul  /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define I2S_SERCTRL_TXDEFAULT_ZERO  (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_ONE   (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_HIZ   (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXSAME_Pos      4            /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
+#define I2S_SERCTRL_TXSAME          (0x1ul << I2S_SERCTRL_TXSAME_Pos)
+#define   I2S_SERCTRL_TXSAME_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define   I2S_SERCTRL_TXSAME_SAME_Val     0x1ul  /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_ZERO     (I2S_SERCTRL_TXSAME_ZERO_Val   << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_SAME     (I2S_SERCTRL_TXSAME_SAME_Val   << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_CLKSEL_Pos      5            /**< \brief (I2S_SERCTRL) Clock Unit Selection */
+#define I2S_SERCTRL_CLKSEL          (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
+#define   I2S_SERCTRL_CLKSEL_CLK0_Val     0x0ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define   I2S_SERCTRL_CLKSEL_CLK1_Val     0x1ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL_CLK0     (I2S_SERCTRL_CLKSEL_CLK0_Val   << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK1     (I2S_SERCTRL_CLKSEL_CLK1_Val   << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_SLOTADJ_Pos     7            /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
+#define I2S_SERCTRL_SLOTADJ         (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
+#define   I2S_SERCTRL_SLOTADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define   I2S_SERCTRL_SLOTADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_RIGHT   (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_LEFT    (I2S_SERCTRL_SLOTADJ_LEFT_Val  << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_DATASIZE_Pos    8            /**< \brief (I2S_SERCTRL) Data Word Size */
+#define I2S_SERCTRL_DATASIZE_Msk    (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
+#define   I2S_SERCTRL_DATASIZE_32_Val     0x0ul  /**< \brief (I2S_SERCTRL) 32 bits */
+#define   I2S_SERCTRL_DATASIZE_24_Val     0x1ul  /**< \brief (I2S_SERCTRL) 24 bits */
+#define   I2S_SERCTRL_DATASIZE_20_Val     0x2ul  /**< \brief (I2S_SERCTRL) 20 bits */
+#define   I2S_SERCTRL_DATASIZE_18_Val     0x3ul  /**< \brief (I2S_SERCTRL) 18 bits */
+#define   I2S_SERCTRL_DATASIZE_16_Val     0x4ul  /**< \brief (I2S_SERCTRL) 16 bits */
+#define   I2S_SERCTRL_DATASIZE_16C_Val    0x5ul  /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define   I2S_SERCTRL_DATASIZE_8_Val      0x6ul  /**< \brief (I2S_SERCTRL) 8 bits */
+#define   I2S_SERCTRL_DATASIZE_8C_Val     0x7ul  /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_32     (I2S_SERCTRL_DATASIZE_32_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_24     (I2S_SERCTRL_DATASIZE_24_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_20     (I2S_SERCTRL_DATASIZE_20_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_18     (I2S_SERCTRL_DATASIZE_18_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16     (I2S_SERCTRL_DATASIZE_16_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16C    (I2S_SERCTRL_DATASIZE_16C_Val  << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8      (I2S_SERCTRL_DATASIZE_8_Val    << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8C     (I2S_SERCTRL_DATASIZE_8C_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_WORDADJ_Pos     12           /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
+#define I2S_SERCTRL_WORDADJ         (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
+#define   I2S_SERCTRL_WORDADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define   I2S_SERCTRL_WORDADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ_RIGHT   (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_LEFT    (I2S_SERCTRL_WORDADJ_LEFT_Val  << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_EXTEND_Pos      13           /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
+#define I2S_SERCTRL_EXTEND_Msk      (0x3ul << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND(value)   (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
+#define   I2S_SERCTRL_EXTEND_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define   I2S_SERCTRL_EXTEND_ONE_Val      0x1ul  /**< \brief (I2S_SERCTRL) Extend with ones */
+#define   I2S_SERCTRL_EXTEND_MSBIT_Val    0x2ul  /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define   I2S_SERCTRL_EXTEND_LSBIT_Val    0x3ul  /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define I2S_SERCTRL_EXTEND_ZERO     (I2S_SERCTRL_EXTEND_ZERO_Val   << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_ONE      (I2S_SERCTRL_EXTEND_ONE_Val    << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_MSBIT    (I2S_SERCTRL_EXTEND_MSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_LSBIT    (I2S_SERCTRL_EXTEND_LSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_BITREV_Pos      15           /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
+#define I2S_SERCTRL_BITREV          (0x1ul << I2S_SERCTRL_BITREV_Pos)
+#define   I2S_SERCTRL_BITREV_MSBIT_Val    0x0ul  /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define   I2S_SERCTRL_BITREV_LSBIT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV_MSBIT    (I2S_SERCTRL_BITREV_MSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_LSBIT    (I2S_SERCTRL_BITREV_LSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_SLOTDIS0_Pos    16           /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS0        (1 << I2S_SERCTRL_SLOTDIS0_Pos)
+#define I2S_SERCTRL_SLOTDIS1_Pos    17           /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS1        (1 << I2S_SERCTRL_SLOTDIS1_Pos)
+#define I2S_SERCTRL_SLOTDIS2_Pos    18           /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS2        (1 << I2S_SERCTRL_SLOTDIS2_Pos)
+#define I2S_SERCTRL_SLOTDIS3_Pos    19           /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS3        (1 << I2S_SERCTRL_SLOTDIS3_Pos)
+#define I2S_SERCTRL_SLOTDIS4_Pos    20           /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS4        (1 << I2S_SERCTRL_SLOTDIS4_Pos)
+#define I2S_SERCTRL_SLOTDIS5_Pos    21           /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS5        (1 << I2S_SERCTRL_SLOTDIS5_Pos)
+#define I2S_SERCTRL_SLOTDIS6_Pos    22           /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS6        (1 << I2S_SERCTRL_SLOTDIS6_Pos)
+#define I2S_SERCTRL_SLOTDIS7_Pos    23           /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS7        (1 << I2S_SERCTRL_SLOTDIS7_Pos)
+#define I2S_SERCTRL_SLOTDIS_Pos     16           /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS_Msk     (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS(value)  (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
+#define I2S_SERCTRL_MONO_Pos        24           /**< \brief (I2S_SERCTRL) Mono Mode */
+#define I2S_SERCTRL_MONO            (0x1ul << I2S_SERCTRL_MONO_Pos)
+#define   I2S_SERCTRL_MONO_STEREO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Normal mode */
+#define   I2S_SERCTRL_MONO_MONO_Val       0x1ul  /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO_STEREO     (I2S_SERCTRL_MONO_STEREO_Val   << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_MONO       (I2S_SERCTRL_MONO_MONO_Val     << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_DMA_Pos         25           /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
+#define I2S_SERCTRL_DMA             (0x1ul << I2S_SERCTRL_DMA_Pos)
+#define   I2S_SERCTRL_DMA_SINGLE_Val      0x0ul  /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define   I2S_SERCTRL_DMA_MULTIPLE_Val    0x1ul  /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA_SINGLE      (I2S_SERCTRL_DMA_SINGLE_Val    << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_MULTIPLE    (I2S_SERCTRL_DMA_MULTIPLE_Val  << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_RXLOOP_Pos      26           /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
+#define I2S_SERCTRL_RXLOOP          (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK            0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
+
+/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_DATA_OFFSET             0x30         /**< \brief (I2S_DATA offset) Data n */
+#define I2S_DATA_RESETVALUE         0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
+
+#define I2S_DATA_DATA_Pos           0            /**< \brief (I2S_DATA) Sample Data */
+#define I2S_DATA_DATA_Msk           (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA(value)        (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
+#define I2S_DATA_MASK               0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO I2S_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x3];
+  __IO I2S_CLKCTRL_Type          CLKCTRL[2];  /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+  __IO I2S_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x2];
+  __IO I2S_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x2];
+  __IO I2S_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x2];
+  __I  I2S_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x18 (R/  16) Synchronization Status */
+       RoReg8                    Reserved5[0x6];
+  __IO I2S_SERCTRL_Type          SERCTRL[2];  /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+       RoReg8                    Reserved6[0x8];
+  __IO I2S_DATA_Type             DATA[2];     /**< \brief Offset: 0x30 (R/W 32) Data n */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_I2S_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h
index 52de8c4..c41c7c3 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h
@@ -1,386 +1,386 @@
-/**
- * \file
- *
- * \brief Component description for MTB
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_MTB_COMPONENT_
-#define _SAMD21_MTB_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR MTB */
-/* ========================================================================== */
-/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
-/*@{*/
-
-#define MTB_U2002
-#define REV_MTB                     0x100
-
-/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t WRAP:1;           /*!< bit:      2  Pointer Value Wraps                */
-    uint32_t POINTER:29;       /*!< bit:  3..31  Trace Packet Location Pointer      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_POSITION_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_POSITION_OFFSET         0x000        /**< \brief (MTB_POSITION offset) MTB Position */
-
-#define MTB_POSITION_WRAP_Pos       2            /**< \brief (MTB_POSITION) Pointer Value Wraps */
-#define MTB_POSITION_WRAP           (0x1ul << MTB_POSITION_WRAP_Pos)
-#define MTB_POSITION_POINTER_Pos    3            /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
-#define MTB_POSITION_POINTER_Msk    (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
-#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
-#define MTB_POSITION_MASK           0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
-
-/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MASK:5;           /*!< bit:  0.. 4  Maximum Value of the Trace Buffer in SRAM */
-    uint32_t TSTARTEN:1;       /*!< bit:      5  Trace Start Input Enable           */
-    uint32_t TSTOPEN:1;        /*!< bit:      6  Trace Stop Input Enable            */
-    uint32_t SFRWPRIV:1;       /*!< bit:      7  Special Function Register Write Privilege */
-    uint32_t RAMPRIV:1;        /*!< bit:      8  SRAM Privilege                     */
-    uint32_t HALTREQ:1;        /*!< bit:      9  Halt Request                       */
-    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
-    uint32_t EN:1;             /*!< bit:     31  Main Trace Enable                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_MASTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_MASTER_OFFSET           0x004        /**< \brief (MTB_MASTER offset) MTB Master */
-#define MTB_MASTER_RESETVALUE       0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
-
-#define MTB_MASTER_MASK_Pos         0            /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
-#define MTB_MASTER_MASK_Msk         (0x1Ful << MTB_MASTER_MASK_Pos)
-#define MTB_MASTER_MASK(value)      (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
-#define MTB_MASTER_TSTARTEN_Pos     5            /**< \brief (MTB_MASTER) Trace Start Input Enable */
-#define MTB_MASTER_TSTARTEN         (0x1ul << MTB_MASTER_TSTARTEN_Pos)
-#define MTB_MASTER_TSTOPEN_Pos      6            /**< \brief (MTB_MASTER) Trace Stop Input Enable */
-#define MTB_MASTER_TSTOPEN          (0x1ul << MTB_MASTER_TSTOPEN_Pos)
-#define MTB_MASTER_SFRWPRIV_Pos     7            /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
-#define MTB_MASTER_SFRWPRIV         (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
-#define MTB_MASTER_RAMPRIV_Pos      8            /**< \brief (MTB_MASTER) SRAM Privilege */
-#define MTB_MASTER_RAMPRIV          (0x1ul << MTB_MASTER_RAMPRIV_Pos)
-#define MTB_MASTER_HALTREQ_Pos      9            /**< \brief (MTB_MASTER) Halt Request */
-#define MTB_MASTER_HALTREQ          (0x1ul << MTB_MASTER_HALTREQ_Pos)
-#define MTB_MASTER_EN_Pos           31           /**< \brief (MTB_MASTER) Main Trace Enable */
-#define MTB_MASTER_EN               (0x1ul << MTB_MASTER_EN_Pos)
-#define MTB_MASTER_MASK_            0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
-
-/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t AUTOSTOP:1;       /*!< bit:      0  Auto Stop Tracing                  */
-    uint32_t AUTOHALT:1;       /*!< bit:      1  Auto Halt Request                  */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t WATERMARK:29;     /*!< bit:  3..31  Watermark value                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_FLOW_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_FLOW_OFFSET             0x008        /**< \brief (MTB_FLOW offset) MTB Flow */
-#define MTB_FLOW_RESETVALUE         0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
-
-#define MTB_FLOW_AUTOSTOP_Pos       0            /**< \brief (MTB_FLOW) Auto Stop Tracing */
-#define MTB_FLOW_AUTOSTOP           (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
-#define MTB_FLOW_AUTOHALT_Pos       1            /**< \brief (MTB_FLOW) Auto Halt Request */
-#define MTB_FLOW_AUTOHALT           (0x1ul << MTB_FLOW_AUTOHALT_Pos)
-#define MTB_FLOW_WATERMARK_Pos      3            /**< \brief (MTB_FLOW) Watermark value */
-#define MTB_FLOW_WATERMARK_Msk      (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
-#define MTB_FLOW_WATERMARK(value)   (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
-#define MTB_FLOW_MASK               0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
-
-/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/  32) MTB Base -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_BASE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_BASE_OFFSET             0x00C        /**< \brief (MTB_BASE offset) MTB Base */
-#define MTB_BASE_MASK               0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
-
-/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_ITCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_ITCTRL_OFFSET           0xF00        /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
-#define MTB_ITCTRL_MASK             0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
-
-/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_CLAIMSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_CLAIMSET_OFFSET         0xFA0        /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
-#define MTB_CLAIMSET_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
-
-/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_CLAIMCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_CLAIMCLR_OFFSET         0xFA4        /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
-#define MTB_CLAIMCLR_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
-
-/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_LOCKACCESS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_LOCKACCESS_OFFSET       0xFB0        /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
-#define MTB_LOCKACCESS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
-
-/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/  32) MTB Lock Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_LOCKSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_LOCKSTATUS_OFFSET       0xFB4        /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
-#define MTB_LOCKSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
-
-/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/  32) MTB Authentication Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_AUTHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_AUTHSTATUS_OFFSET       0xFB8        /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
-#define MTB_AUTHSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
-
-/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/  32) MTB Device Architecture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_DEVARCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_DEVARCH_OFFSET          0xFBC        /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
-#define MTB_DEVARCH_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
-
-/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/  32) MTB Device Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_DEVID_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_DEVID_OFFSET            0xFC8        /**< \brief (MTB_DEVID offset) MTB Device Configuration */
-#define MTB_DEVID_MASK              0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
-
-/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/  32) MTB Device Type -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_DEVTYPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_DEVTYPE_OFFSET          0xFCC        /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
-#define MTB_DEVTYPE_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
-
-/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID4_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID4_OFFSET             0xFD0        /**< \brief (MTB_PID4 offset) CoreSight */
-#define MTB_PID4_MASK               0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
-
-/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID5_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID5_OFFSET             0xFD4        /**< \brief (MTB_PID5 offset) CoreSight */
-#define MTB_PID5_MASK               0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
-
-/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID6_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID6_OFFSET             0xFD8        /**< \brief (MTB_PID6 offset) CoreSight */
-#define MTB_PID6_MASK               0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
-
-/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID7_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID7_OFFSET             0xFDC        /**< \brief (MTB_PID7 offset) CoreSight */
-#define MTB_PID7_MASK               0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
-
-/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID0_OFFSET             0xFE0        /**< \brief (MTB_PID0 offset) CoreSight */
-#define MTB_PID0_MASK               0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
-
-/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID1_OFFSET             0xFE4        /**< \brief (MTB_PID1 offset) CoreSight */
-#define MTB_PID1_MASK               0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
-
-/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID2_OFFSET             0xFE8        /**< \brief (MTB_PID2 offset) CoreSight */
-#define MTB_PID2_MASK               0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
-
-/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_PID3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_PID3_OFFSET             0xFEC        /**< \brief (MTB_PID3 offset) CoreSight */
-#define MTB_PID3_MASK               0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
-
-/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_CID0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_CID0_OFFSET             0xFF0        /**< \brief (MTB_CID0 offset) CoreSight */
-#define MTB_CID0_MASK               0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
-
-/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_CID1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_CID1_OFFSET             0xFF4        /**< \brief (MTB_CID1 offset) CoreSight */
-#define MTB_CID1_MASK               0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
-
-/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_CID2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_CID2_OFFSET             0xFF8        /**< \brief (MTB_CID2 offset) CoreSight */
-#define MTB_CID2_MASK               0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
-
-/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/  32) CoreSight -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} MTB_CID3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MTB_CID3_OFFSET             0xFFC        /**< \brief (MTB_CID3 offset) CoreSight */
-#define MTB_CID3_MASK               0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
-
-/** \brief MTB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO MTB_POSITION_Type         POSITION;    /**< \brief Offset: 0x000 (R/W 32) MTB Position */
-  __IO MTB_MASTER_Type           MASTER;      /**< \brief Offset: 0x004 (R/W 32) MTB Master */
-  __IO MTB_FLOW_Type             FLOW;        /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
-  __I  MTB_BASE_Type             BASE;        /**< \brief Offset: 0x00C (R/  32) MTB Base */
-       RoReg8                    Reserved1[0xEF0];
-  __IO MTB_ITCTRL_Type           ITCTRL;      /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
-       RoReg8                    Reserved2[0x9C];
-  __IO MTB_CLAIMSET_Type         CLAIMSET;    /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
-  __IO MTB_CLAIMCLR_Type         CLAIMCLR;    /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
-       RoReg8                    Reserved3[0x8];
-  __IO MTB_LOCKACCESS_Type       LOCKACCESS;  /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
-  __I  MTB_LOCKSTATUS_Type       LOCKSTATUS;  /**< \brief Offset: 0xFB4 (R/  32) MTB Lock Status */
-  __I  MTB_AUTHSTATUS_Type       AUTHSTATUS;  /**< \brief Offset: 0xFB8 (R/  32) MTB Authentication Status */
-  __I  MTB_DEVARCH_Type          DEVARCH;     /**< \brief Offset: 0xFBC (R/  32) MTB Device Architecture */
-       RoReg8                    Reserved4[0x8];
-  __I  MTB_DEVID_Type            DEVID;       /**< \brief Offset: 0xFC8 (R/  32) MTB Device Configuration */
-  __I  MTB_DEVTYPE_Type          DEVTYPE;     /**< \brief Offset: 0xFCC (R/  32) MTB Device Type */
-  __I  MTB_PID4_Type             PID4;        /**< \brief Offset: 0xFD0 (R/  32) CoreSight */
-  __I  MTB_PID5_Type             PID5;        /**< \brief Offset: 0xFD4 (R/  32) CoreSight */
-  __I  MTB_PID6_Type             PID6;        /**< \brief Offset: 0xFD8 (R/  32) CoreSight */
-  __I  MTB_PID7_Type             PID7;        /**< \brief Offset: 0xFDC (R/  32) CoreSight */
-  __I  MTB_PID0_Type             PID0;        /**< \brief Offset: 0xFE0 (R/  32) CoreSight */
-  __I  MTB_PID1_Type             PID1;        /**< \brief Offset: 0xFE4 (R/  32) CoreSight */
-  __I  MTB_PID2_Type             PID2;        /**< \brief Offset: 0xFE8 (R/  32) CoreSight */
-  __I  MTB_PID3_Type             PID3;        /**< \brief Offset: 0xFEC (R/  32) CoreSight */
-  __I  MTB_CID0_Type             CID0;        /**< \brief Offset: 0xFF0 (R/  32) CoreSight */
-  __I  MTB_CID1_Type             CID1;        /**< \brief Offset: 0xFF4 (R/  32) CoreSight */
-  __I  MTB_CID2_Type             CID2;        /**< \brief Offset: 0xFF8 (R/  32) CoreSight */
-  __I  MTB_CID3_Type             CID3;        /**< \brief Offset: 0xFFC (R/  32) CoreSight */
-} Mtb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_MTB_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_COMPONENT_
+#define _SAMD21_MTB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB                     0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t WRAP:1;           /*!< bit:      2  Pointer Value Wraps                */
+    uint32_t POINTER:29;       /*!< bit:  3..31  Trace Packet Location Pointer      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET         0x000        /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos       2            /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP           (0x1ul << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos    3            /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk    (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
+#define MTB_POSITION_MASK           0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MASK:5;           /*!< bit:  0.. 4  Maximum Value of the Trace Buffer in SRAM */
+    uint32_t TSTARTEN:1;       /*!< bit:      5  Trace Start Input Enable           */
+    uint32_t TSTOPEN:1;        /*!< bit:      6  Trace Stop Input Enable            */
+    uint32_t SFRWPRIV:1;       /*!< bit:      7  Special Function Register Write Privilege */
+    uint32_t RAMPRIV:1;        /*!< bit:      8  SRAM Privilege                     */
+    uint32_t HALTREQ:1;        /*!< bit:      9  Halt Request                       */
+    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
+    uint32_t EN:1;             /*!< bit:     31  Main Trace Enable                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET           0x004        /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE       0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos         0            /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk         (0x1Ful << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value)      (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
+#define MTB_MASTER_TSTARTEN_Pos     5            /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN         (0x1ul << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos      6            /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN          (0x1ul << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos     7            /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV         (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos      8            /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV          (0x1ul << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos      9            /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ          (0x1ul << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos           31           /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN               (0x1ul << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_            0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AUTOSTOP:1;       /*!< bit:      0  Auto Stop Tracing                  */
+    uint32_t AUTOHALT:1;       /*!< bit:      1  Auto Halt Request                  */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t WATERMARK:29;     /*!< bit:  3..31  Watermark value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET             0x008        /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE         0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos       0            /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP           (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos       1            /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT           (0x1ul << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos      3            /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk      (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value)   (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
+#define MTB_FLOW_MASK               0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/  32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET             0x00C        /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK               0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET           0xF00        /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK             0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET         0xFA0        /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET         0xFA4        /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET       0xFB0        /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/  32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET       0xFB4        /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/  32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET       0xFB8        /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/  32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET          0xFBC        /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/  32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET            0xFC8        /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK              0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/  32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET          0xFCC        /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET             0xFD0        /**< \brief (MTB_PID4 offset) CoreSight */
+#define MTB_PID4_MASK               0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET             0xFD4        /**< \brief (MTB_PID5 offset) CoreSight */
+#define MTB_PID5_MASK               0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET             0xFD8        /**< \brief (MTB_PID6 offset) CoreSight */
+#define MTB_PID6_MASK               0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET             0xFDC        /**< \brief (MTB_PID7 offset) CoreSight */
+#define MTB_PID7_MASK               0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET             0xFE0        /**< \brief (MTB_PID0 offset) CoreSight */
+#define MTB_PID0_MASK               0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET             0xFE4        /**< \brief (MTB_PID1 offset) CoreSight */
+#define MTB_PID1_MASK               0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET             0xFE8        /**< \brief (MTB_PID2 offset) CoreSight */
+#define MTB_PID2_MASK               0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET             0xFEC        /**< \brief (MTB_PID3 offset) CoreSight */
+#define MTB_PID3_MASK               0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET             0xFF0        /**< \brief (MTB_CID0 offset) CoreSight */
+#define MTB_CID0_MASK               0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET             0xFF4        /**< \brief (MTB_CID1 offset) CoreSight */
+#define MTB_CID1_MASK               0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET             0xFF8        /**< \brief (MTB_CID2 offset) CoreSight */
+#define MTB_CID2_MASK               0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET             0xFFC        /**< \brief (MTB_CID3 offset) CoreSight */
+#define MTB_CID3_MASK               0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO MTB_POSITION_Type         POSITION;    /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+  __IO MTB_MASTER_Type           MASTER;      /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+  __IO MTB_FLOW_Type             FLOW;        /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+  __I  MTB_BASE_Type             BASE;        /**< \brief Offset: 0x00C (R/  32) MTB Base */
+       RoReg8                    Reserved1[0xEF0];
+  __IO MTB_ITCTRL_Type           ITCTRL;      /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+       RoReg8                    Reserved2[0x9C];
+  __IO MTB_CLAIMSET_Type         CLAIMSET;    /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+  __IO MTB_CLAIMCLR_Type         CLAIMCLR;    /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+       RoReg8                    Reserved3[0x8];
+  __IO MTB_LOCKACCESS_Type       LOCKACCESS;  /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+  __I  MTB_LOCKSTATUS_Type       LOCKSTATUS;  /**< \brief Offset: 0xFB4 (R/  32) MTB Lock Status */
+  __I  MTB_AUTHSTATUS_Type       AUTHSTATUS;  /**< \brief Offset: 0xFB8 (R/  32) MTB Authentication Status */
+  __I  MTB_DEVARCH_Type          DEVARCH;     /**< \brief Offset: 0xFBC (R/  32) MTB Device Architecture */
+       RoReg8                    Reserved4[0x8];
+  __I  MTB_DEVID_Type            DEVID;       /**< \brief Offset: 0xFC8 (R/  32) MTB Device Configuration */
+  __I  MTB_DEVTYPE_Type          DEVTYPE;     /**< \brief Offset: 0xFCC (R/  32) MTB Device Type */
+  __I  MTB_PID4_Type             PID4;        /**< \brief Offset: 0xFD0 (R/  32) CoreSight */
+  __I  MTB_PID5_Type             PID5;        /**< \brief Offset: 0xFD4 (R/  32) CoreSight */
+  __I  MTB_PID6_Type             PID6;        /**< \brief Offset: 0xFD8 (R/  32) CoreSight */
+  __I  MTB_PID7_Type             PID7;        /**< \brief Offset: 0xFDC (R/  32) CoreSight */
+  __I  MTB_PID0_Type             PID0;        /**< \brief Offset: 0xFE0 (R/  32) CoreSight */
+  __I  MTB_PID1_Type             PID1;        /**< \brief Offset: 0xFE4 (R/  32) CoreSight */
+  __I  MTB_PID2_Type             PID2;        /**< \brief Offset: 0xFE8 (R/  32) CoreSight */
+  __I  MTB_PID3_Type             PID3;        /**< \brief Offset: 0xFEC (R/  32) CoreSight */
+  __I  MTB_CID0_Type             CID0;        /**< \brief Offset: 0xFF0 (R/  32) CoreSight */
+  __I  MTB_CID1_Type             CID1;        /**< \brief Offset: 0xFF4 (R/  32) CoreSight */
+  __I  MTB_CID2_Type             CID2;        /**< \brief Offset: 0xFF8 (R/  32) CoreSight */
+  __I  MTB_CID3_Type             CID3;        /**< \brief Offset: 0xFFC (R/  32) CoreSight */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_MTB_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
index 37a8ae4..5b77aa3 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
@@ -1,617 +1,617 @@
-/**
- * \file
- *
- * \brief Component description for NVMCTRL
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_NVMCTRL_COMPONENT_
-#define _SAMD21_NVMCTRL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR NVMCTRL */
-/* ========================================================================== */
-/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
-/*@{*/
-
-#define NVMCTRL_U2207
-#define REV_NVMCTRL                 0x202
-
-/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
-#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
-
-#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
-#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
-#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
-#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
-#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
-#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
-#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   0x1Aul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   0x1Cul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
-#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
-#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
-#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
-#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
-#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_RWWEEER   (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_RWWEEWP   (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
-#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
-#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
-#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
-#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
-#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
-
-/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
-    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
-    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
-#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
-
-#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
-#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
-#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
-#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
-#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
-#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
-#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
-#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
-#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
-#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
-#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
-#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
-#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
-#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
-#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
-#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
-#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
-#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
-#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
-
-/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
-    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t RWWEEP:12;        /*!< bit: 20..31  RWW EEPROM Pages                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_PARAM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
-#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
-
-#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
-#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
-#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
-#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
-#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
-#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
-#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
-#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
-#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
-#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
-#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
-#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
-#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
-#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
-#define NVMCTRL_PARAM_RWWEEP_Msk    (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
-#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
-#define NVMCTRL_PARAM_MASK          0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
-
-/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
-    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
-#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
-#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
-#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
-#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
-
-/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
-    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
-#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
-#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
-#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
-#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
-#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
-
-/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
-    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
-#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
-#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
-#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
-#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
-
-/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
-    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
-    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
-    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
-    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
-#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
-
-#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
-#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
-#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
-#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
-#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
-#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
-#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
-#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
-#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
-#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
-#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
-#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
-#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
-
-/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
-#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
-
-#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
-#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
-#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
-#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
-
-/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_LOCK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
-
-#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
-#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
-#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
-#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
-
-/** \brief NVMCTRL APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-       RoReg8                    Reserved1[0x2];
-  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
-  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
-  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x3];
-  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
-       RoReg8                    Reserved3[0x3];
-  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x3];
-  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
-       RoReg8                    Reserved5[0x2];
-  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
-  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
-} Nvmctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_NVMCTRL_AUX3
-
-#define SECTION_NVMCTRL_CAL
-
-#define SECTION_NVMCTRL_LOCKBIT
-
-#define SECTION_NVMCTRL_OTP1
-
-#define SECTION_NVMCTRL_OTP2
-
-#define SECTION_NVMCTRL_OTP4
-
-#define SECTION_NVMCTRL_TEMP_LOG
-
-#define SECTION_NVMCTRL_USER
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
-/* ************************************************************************** */
-/** \addtogroup fuses_api Peripheral Software API */
-/*@{*/
-
-
-#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
-#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
-#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
-#define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
-
-#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
-#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
-#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
-#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
-
-#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
-#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
-#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
-#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
-
-#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
-#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
-#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
-#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
-
-#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
-#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
-#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
-#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
-
-#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
-#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
-#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
-
-#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
-#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
-#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
-
-#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
-#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
-#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
-#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
-
-#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
-#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
-#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
-#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
-
-#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
-#define FUSES_HOT_ADC_VAL_Msk       (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
-#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
-
-#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
-#define FUSES_HOT_INT1V_VAL_Msk     (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
-#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
-
-#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
-#define FUSES_HOT_TEMP_VAL_DEC_Msk  (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
-#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
-
-#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
-#define FUSES_HOT_TEMP_VAL_INT_Msk  (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
-#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
-
-#define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
-#define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
-#define FUSES_OSC32K_CAL_Msk        (0x7Ful << FUSES_OSC32K_CAL_Pos)
-#define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
-
-#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
-#define FUSES_ROOM_ADC_VAL_Msk      (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
-#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
-
-#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
-#define FUSES_ROOM_INT1V_VAL_Msk    (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
-#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
-
-#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
-#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
-#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
-
-#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
-#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
-#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
-
-#define FUSES_SERIAL_NUMBER_0_ADDR  (NVMCTRL_AUX3 + 64)
-#define FUSES_SERIAL_NUMBER_0_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
-#define FUSES_SERIAL_NUMBER_0_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_0_Pos)
-#define FUSES_SERIAL_NUMBER_0(value) (FUSES_SERIAL_NUMBER_0_Msk & ((value) << FUSES_SERIAL_NUMBER_0_Pos))
-
-#define FUSES_SERIAL_NUMBER_1_ADDR  (NVMCTRL_AUX3 + 68)
-#define FUSES_SERIAL_NUMBER_1_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 63:32 */
-#define FUSES_SERIAL_NUMBER_1_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_1_Pos)
-#define FUSES_SERIAL_NUMBER_1(value) (FUSES_SERIAL_NUMBER_1_Msk & ((value) << FUSES_SERIAL_NUMBER_1_Pos))
-
-#define FUSES_SERIAL_NUMBER_2_ADDR  (NVMCTRL_AUX3 + 72)
-#define FUSES_SERIAL_NUMBER_2_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 95:64 */
-#define FUSES_SERIAL_NUMBER_2_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_2_Pos)
-#define FUSES_SERIAL_NUMBER_2(value) (FUSES_SERIAL_NUMBER_2_Msk & ((value) << FUSES_SERIAL_NUMBER_2_Pos))
-
-#define FUSES_SERIAL_NUMBER_3_ADDR  (NVMCTRL_AUX3 + 12)
-#define FUSES_SERIAL_NUMBER_3_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number word 3 */
-#define FUSES_SERIAL_NUMBER_3_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_3_Pos)
-#define FUSES_SERIAL_NUMBER_3(value) (FUSES_SERIAL_NUMBER_3_Msk & ((value) << FUSES_SERIAL_NUMBER_3_Pos))
-
-#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
-#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
-#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
-#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
-
-#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
-#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
-#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
-#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
-
-/* Compatible definition for previous driver (begin 1) */
-#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
-#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
-#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
-#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
-
-#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
-#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
-#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
-#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
-
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
-
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
-#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
-/* Compatible definition for previous driver (end 1) */
-#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
-#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
-#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
-#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
-
-/* Compatible definition for previous driver (begin 2) */
-#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
-#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
-#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
-#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
-
-#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
-#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
-#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
-#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
-
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
-
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
-#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
-
-#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
-#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
-#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
-#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
-
-#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
-#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15           /**< \brief (NVMCTRL_USER) BOD33 Action */
-#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
-#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
-
-#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
-#define SYSCTRL_FUSES_BOD33_EN_Pos  14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
-#define SYSCTRL_FUSES_BOD33_EN_Msk  (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
-
-#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
-#define SYSCTRL_FUSES_BOD33_HYST_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
-#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
-
-#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
-#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
-#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
-#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
-
-#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
-#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
-#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
-#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
-/* Compatible definition for previous driver (end 2) */
-#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
-#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
-#define USB_FUSES_TRANSN_Msk        (0x1Ful << USB_FUSES_TRANSN_Pos)
-#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
-
-#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
-#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
-#define USB_FUSES_TRANSP_Msk        (0x1Ful << USB_FUSES_TRANSP_Pos)
-#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
-
-#define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
-#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
-#define USB_FUSES_TRIM_Msk          (0x7ul << USB_FUSES_TRIM_Pos)
-#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
-
-#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
-#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
-#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
-
-#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
-#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
-#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
-
-#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
-#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
-#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
-#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
-
-#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
-#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
-#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
-#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
-
-#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
-#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
-#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
-
-#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
-#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
-#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
-
-#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
-#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
-#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
-#define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
-
-/*@}*/
-
-#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL                 0x202
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
+#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   0x1Aul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   0x1Cul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEER   (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEWP   (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
+    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
+    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :1;               /*!< bit:     19  Reserved                           */
+    uint32_t RWWEEP:12;        /*!< bit: 20..31  RWW EEPROM Pages                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
+#define NVMCTRL_PARAM_RWWEEP_Msk    (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
+#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
+#define NVMCTRL_PARAM_MASK          0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
+    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
+    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
+#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x3];
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x3];
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x3];
+  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
+       RoReg8                    Reserved5[0x2];
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
+  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_AUX3
+
+#define SECTION_NVMCTRL_CAL
+
+#define SECTION_NVMCTRL_LOCKBIT
+
+#define SECTION_NVMCTRL_OTP1
+
+#define SECTION_NVMCTRL_OTP2
+
+#define SECTION_NVMCTRL_OTP4
+
+#define SECTION_NVMCTRL_TEMP_LOG
+
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
+
+#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
+
+#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
+
+#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk       (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk     (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32K_CAL_Msk        (0x7Ful << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
+
+#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk      (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk    (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define FUSES_SERIAL_NUMBER_0_ADDR  (NVMCTRL_AUX3 + 64)
+#define FUSES_SERIAL_NUMBER_0_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
+#define FUSES_SERIAL_NUMBER_0_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_0_Pos)
+#define FUSES_SERIAL_NUMBER_0(value) (FUSES_SERIAL_NUMBER_0_Msk & ((value) << FUSES_SERIAL_NUMBER_0_Pos))
+
+#define FUSES_SERIAL_NUMBER_1_ADDR  (NVMCTRL_AUX3 + 68)
+#define FUSES_SERIAL_NUMBER_1_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 63:32 */
+#define FUSES_SERIAL_NUMBER_1_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_1_Pos)
+#define FUSES_SERIAL_NUMBER_1(value) (FUSES_SERIAL_NUMBER_1_Msk & ((value) << FUSES_SERIAL_NUMBER_1_Pos))
+
+#define FUSES_SERIAL_NUMBER_2_ADDR  (NVMCTRL_AUX3 + 72)
+#define FUSES_SERIAL_NUMBER_2_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 95:64 */
+#define FUSES_SERIAL_NUMBER_2_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_2_Pos)
+#define FUSES_SERIAL_NUMBER_2(value) (FUSES_SERIAL_NUMBER_2_Msk & ((value) << FUSES_SERIAL_NUMBER_2_Pos))
+
+#define FUSES_SERIAL_NUMBER_3_ADDR  (NVMCTRL_AUX3 + 12)
+#define FUSES_SERIAL_NUMBER_3_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number word 3 */
+#define FUSES_SERIAL_NUMBER_3_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_3_Pos)
+#define FUSES_SERIAL_NUMBER_3(value) (FUSES_SERIAL_NUMBER_3_Msk & ((value) << FUSES_SERIAL_NUMBER_3_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
+
+/* Compatible definition for previous driver (begin 1) */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
+/* Compatible definition for previous driver (end 1) */
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+/* Compatible definition for previous driver (begin 2) */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
+#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
+#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_EN_Pos  14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define SYSCTRL_FUSES_BOD33_EN_Msk  (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
+
+#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define SYSCTRL_FUSES_BOD33_HYST_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
+
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
+#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
+/* Compatible definition for previous driver (end 2) */
+#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk        (0x1Ful << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk        (0x1Ful << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk          (0x7ul << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
+#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h
index ae9ab23..13bd474 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl_variant_d.h
@@ -1,540 +1,540 @@
-/**
- * \file
- *
- * \brief Component description for NVMCTRL
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_NVMCTRL_COMPONENT_
-#define _SAMD21_NVMCTRL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR NVMCTRL */
-/* ========================================================================== */
-/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
-/*@{*/
-
-#define NVMCTRL_U2207
-#define REV_NVMCTRL                 0x220
-
-/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
-#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
-
-#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
-#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
-#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
-#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
-#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
-#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
-#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   0x1Aul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   0x1Cul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
-#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
-#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
-#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
-#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
-#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_RWWEEER   (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_RWWEEWP   (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
-#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
-#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
-#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
-#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
-#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
-#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
-
-/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
-    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
-    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
-#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
-
-#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
-#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
-#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
-#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
-#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
-#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
-#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
-#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
-#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
-#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
-#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
-#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
-#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
-#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
-#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
-#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
-#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
-#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
-#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
-#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
-#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
-#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
-
-/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
-    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t RWWEEP:12;        /*!< bit: 20..31  RWW EEPROM Pages                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_PARAM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
-#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
-
-#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
-#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
-#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
-#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
-#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
-#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
-#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
-#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
-#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
-#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
-#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
-#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
-#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
-#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
-#define NVMCTRL_PARAM_RWWEEP_Msk    (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
-#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
-#define NVMCTRL_PARAM_MASK          0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
-
-/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
-    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
-#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
-#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
-#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
-#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
-
-/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
-    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
-#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
-#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
-#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
-#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
-#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
-
-/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
-    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
-#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
-#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
-#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
-#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
-
-/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
-    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
-    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
-    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
-    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
-#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
-
-#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
-#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
-#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
-#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
-#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
-#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
-#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
-#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
-#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
-#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
-#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
-#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
-#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
-
-/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
-#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
-
-#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
-#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
-#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
-#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
-
-/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_LOCK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
-
-#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
-#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
-#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
-#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
-
-/** \brief NVMCTRL APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-       RoReg8                    Reserved1[0x2];
-  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
-  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
-  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x3];
-  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
-       RoReg8                    Reserved3[0x3];
-  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x3];
-  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
-       RoReg8                    Reserved5[0x2];
-  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
-  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
-} Nvmctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_NVMCTRL_AUX3
-#define SECTION_NVMCTRL_CAL
-#define SECTION_NVMCTRL_LOCKBIT
-#define SECTION_NVMCTRL_OTP1
-#define SECTION_NVMCTRL_OTP2
-#define SECTION_NVMCTRL_OTP4
-#define SECTION_NVMCTRL_TEMP_LOG
-#define SECTION_NVMCTRL_USER
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
-/* ************************************************************************** */
-/** \addtogroup fuses_api Peripheral Software API */
-/*@{*/
-
-
-#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
-#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
-#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
-#define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
-
-#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
-#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
-#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
-#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
-
-#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
-#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
-#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
-#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
-
-#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
-#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
-#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
-#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
-
-#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
-#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
-#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
-#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
-
-#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
-#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
-#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
-
-#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
-#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
-#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
-
-#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
-#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
-#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
-#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
-
-#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
-#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
-#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
-#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
-
-#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
-#define FUSES_HOT_ADC_VAL_Msk       (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
-#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
-
-#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
-#define FUSES_HOT_INT1V_VAL_Msk     (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
-#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
-
-#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
-#define FUSES_HOT_TEMP_VAL_DEC_Msk  (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
-#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
-
-#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
-#define FUSES_HOT_TEMP_VAL_INT_Msk  (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
-#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
-
-#define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
-#define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
-#define FUSES_OSC32K_CAL_Msk        (0x7Ful << FUSES_OSC32K_CAL_Pos)
-#define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
-
-#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
-#define FUSES_ROOM_ADC_VAL_Msk      (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
-#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
-
-#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
-#define FUSES_ROOM_INT1V_VAL_Msk    (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
-#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
-
-#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
-#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
-#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
-
-#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
-#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
-#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
-
-#define FUSES_SERIAL_NUMBER_0_ADDR  (NVMCTRL_AUX3 + 64)
-#define FUSES_SERIAL_NUMBER_0_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
-#define FUSES_SERIAL_NUMBER_0_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_0_Pos)
-#define FUSES_SERIAL_NUMBER_0(value) (FUSES_SERIAL_NUMBER_0_Msk & ((value) << FUSES_SERIAL_NUMBER_0_Pos))
-
-#define FUSES_SERIAL_NUMBER_1_ADDR  (NVMCTRL_AUX3 + 68)
-#define FUSES_SERIAL_NUMBER_1_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 63:32 */
-#define FUSES_SERIAL_NUMBER_1_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_1_Pos)
-#define FUSES_SERIAL_NUMBER_1(value) (FUSES_SERIAL_NUMBER_1_Msk & ((value) << FUSES_SERIAL_NUMBER_1_Pos))
-
-#define FUSES_SERIAL_NUMBER_2_ADDR  (NVMCTRL_AUX3 + 72)
-#define FUSES_SERIAL_NUMBER_2_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 95:64 */
-#define FUSES_SERIAL_NUMBER_2_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_2_Pos)
-#define FUSES_SERIAL_NUMBER_2(value) (FUSES_SERIAL_NUMBER_2_Msk & ((value) << FUSES_SERIAL_NUMBER_2_Pos))
-
-#define FUSES_SERIAL_NUMBER_3_ADDR  (NVMCTRL_AUX3 + 12)
-#define FUSES_SERIAL_NUMBER_3_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number word 3 */
-#define FUSES_SERIAL_NUMBER_3_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_3_Pos)
-#define FUSES_SERIAL_NUMBER_3(value) (FUSES_SERIAL_NUMBER_3_Msk & ((value) << FUSES_SERIAL_NUMBER_3_Pos))
-
-#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
-#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
-#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
-#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
-
-#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
-#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
-#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
-#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
-
-#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
-#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
-#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
-#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
-
-#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
-#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
-#define USB_FUSES_TRANSN_Msk        (0x1Ful << USB_FUSES_TRANSN_Pos)
-#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
-
-#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
-#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
-#define USB_FUSES_TRANSP_Msk        (0x1Ful << USB_FUSES_TRANSP_Pos)
-#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
-
-#define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
-#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
-#define USB_FUSES_TRIM_Msk          (0x7ul << USB_FUSES_TRIM_Pos)
-#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
-
-#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
-#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
-#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
-
-#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
-#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
-#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
-
-#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
-#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
-#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
-#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
-
-#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
-#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
-#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
-#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
-
-#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
-#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
-#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
-
-#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
-#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
-#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
-
-#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
-#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
-#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
-#define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
-
-/*@}*/
-
-#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL                 0x220
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
+#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   0x1Aul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   0x1Cul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEER   (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEWP   (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
+    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
+    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :1;               /*!< bit:     19  Reserved                           */
+    uint32_t RWWEEP:12;        /*!< bit: 20..31  RWW EEPROM Pages                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
+#define NVMCTRL_PARAM_RWWEEP_Msk    (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
+#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
+#define NVMCTRL_PARAM_MASK          0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
+    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
+    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
+#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x3];
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x3];
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x3];
+  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
+       RoReg8                    Reserved5[0x2];
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
+  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_AUX3
+#define SECTION_NVMCTRL_CAL
+#define SECTION_NVMCTRL_LOCKBIT
+#define SECTION_NVMCTRL_OTP1
+#define SECTION_NVMCTRL_OTP2
+#define SECTION_NVMCTRL_OTP4
+#define SECTION_NVMCTRL_TEMP_LOG
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
+
+#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
+
+#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
+
+#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk       (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk     (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32K_CAL_Msk        (0x7Ful << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
+
+#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk      (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk    (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define FUSES_SERIAL_NUMBER_0_ADDR  (NVMCTRL_AUX3 + 64)
+#define FUSES_SERIAL_NUMBER_0_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
+#define FUSES_SERIAL_NUMBER_0_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_0_Pos)
+#define FUSES_SERIAL_NUMBER_0(value) (FUSES_SERIAL_NUMBER_0_Msk & ((value) << FUSES_SERIAL_NUMBER_0_Pos))
+
+#define FUSES_SERIAL_NUMBER_1_ADDR  (NVMCTRL_AUX3 + 68)
+#define FUSES_SERIAL_NUMBER_1_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 63:32 */
+#define FUSES_SERIAL_NUMBER_1_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_1_Pos)
+#define FUSES_SERIAL_NUMBER_1(value) (FUSES_SERIAL_NUMBER_1_Msk & ((value) << FUSES_SERIAL_NUMBER_1_Pos))
+
+#define FUSES_SERIAL_NUMBER_2_ADDR  (NVMCTRL_AUX3 + 72)
+#define FUSES_SERIAL_NUMBER_2_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 95:64 */
+#define FUSES_SERIAL_NUMBER_2_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_2_Pos)
+#define FUSES_SERIAL_NUMBER_2(value) (FUSES_SERIAL_NUMBER_2_Msk & ((value) << FUSES_SERIAL_NUMBER_2_Pos))
+
+#define FUSES_SERIAL_NUMBER_3_ADDR  (NVMCTRL_AUX3 + 12)
+#define FUSES_SERIAL_NUMBER_3_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number word 3 */
+#define FUSES_SERIAL_NUMBER_3_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_3_Pos)
+#define FUSES_SERIAL_NUMBER_3(value) (FUSES_SERIAL_NUMBER_3_Msk & ((value) << FUSES_SERIAL_NUMBER_3_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk        (0x1Ful << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk        (0x1Ful << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk          (0x7ul << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
+#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h
index a4bdf67..b1ffab6 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h
@@ -1,94 +1,94 @@
-/**
- * \file
- *
- * \brief Component description for PAC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PAC_COMPONENT_
-#define _SAMD21_PAC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PAC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_PAC Peripheral Access Controller */
-/*@{*/
-
-#define PAC_U2211
-#define REV_PAC                     0x101
-
-/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Clear             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_WPCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_WPCLR_OFFSET            0x0          /**< \brief (PAC_WPCLR offset) Write Protection Clear */
-#define PAC_WPCLR_RESETVALUE        0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
-
-#define PAC_WPCLR_WP_Pos            1            /**< \brief (PAC_WPCLR) Write Protection Clear */
-#define PAC_WPCLR_WP_Msk            (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
-#define PAC_WPCLR_WP(value)         (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
-#define PAC_WPCLR_MASK              0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
-
-/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Set               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_WPSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_WPSET_OFFSET            0x4          /**< \brief (PAC_WPSET offset) Write Protection Set */
-#define PAC_WPSET_RESETVALUE        0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
-
-#define PAC_WPSET_WP_Pos            1            /**< \brief (PAC_WPSET) Write Protection Set */
-#define PAC_WPSET_WP_Msk            (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
-#define PAC_WPSET_WP(value)         (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
-#define PAC_WPSET_MASK              0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
-
-/** \brief PAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PAC_WPCLR_Type            WPCLR;       /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
-  __IO PAC_WPSET_Type            WPSET;       /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
-} Pac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_PAC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC_COMPONENT_
+#define _SAMD21_PAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC                     0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Clear             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET            0x0          /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE        0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos            1            /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk            (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value)         (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
+#define PAC_WPCLR_MASK              0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Set               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET            0x4          /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE        0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos            1            /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk            (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value)         (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
+#define PAC_WPSET_MASK              0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PAC_WPCLR_Type            WPCLR;       /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+  __IO PAC_WPSET_Type            WPSET;       /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PAC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h
index b9e1f5c..ed8f572 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h
@@ -1,545 +1,545 @@
-/**
- * \file
- *
- * \brief Component description for PM
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PM_COMPONENT_
-#define _SAMD21_PM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PM */
-/* ========================================================================== */
-/** \addtogroup SAMD21_PM Power Manager */
-/*@{*/
-
-#define PM_U2206
-#define REV_PM                      0x212
-
-/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
-#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
-
-#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
-
-/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_SLEEP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
-#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
-
-#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
-#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
-#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
-#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
-#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
-#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
-
-/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W  8) External Reset Controller -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SETDIS:1;         /*!< bit:      0  External Reset Disable             */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_EXTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_EXTCTRL_OFFSET           0x02         /**< \brief (PM_EXTCTRL offset) External Reset Controller */
-#define PM_EXTCTRL_RESETVALUE       0x00ul       /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
-
-#define PM_EXTCTRL_SETDIS_Pos       0            /**< \brief (PM_EXTCTRL) External Reset Disable */
-#define PM_EXTCTRL_SETDIS           (0x1ul << PM_EXTCTRL_SETDIS_Pos)
-#define PM_EXTCTRL_MASK             0x01ul       /**< \brief (PM_EXTCTRL) MASK Register */
-
-/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_CPUSEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
-#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
-
-#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
-#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
-#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
-#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
-#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
-#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
-#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
-#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
-#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
-#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
-#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
-
-/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_APBASEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
-#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
-
-#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
-#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
-#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
-#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
-#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
-#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
-#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
-#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
-#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
-#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
-#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
-
-/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_APBBSEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
-#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
-
-#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
-#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
-#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
-#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
-#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
-#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
-#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
-#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
-#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
-#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
-#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
-
-/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_APBCSEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
-#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
-
-#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
-#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
-#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
-#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
-#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
-#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
-#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
-#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
-#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
-#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
-#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
-
-/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
-    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
-    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
-    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
-    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
-    uint32_t DMAC_:1;          /*!< bit:      5  DMAC AHB Clock Mask                */
-    uint32_t USB_:1;           /*!< bit:      6  USB AHB Clock Mask                 */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_AHBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
-#define PM_AHBMASK_RESETVALUE       0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
-
-#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
-#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
-#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
-#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
-#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
-#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
-#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
-#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
-#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
-#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
-#define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
-#define PM_AHBMASK_DMAC             (0x1ul << PM_AHBMASK_DMAC_Pos)
-#define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
-#define PM_AHBMASK_USB              (0x1ul << PM_AHBMASK_USB_Pos)
-#define PM_AHBMASK_MASK             0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
-
-/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
-    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
-    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
-    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
-    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
-    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
-    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_APBAMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
-#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
-
-#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
-#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
-#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
-#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
-#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
-#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
-#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
-#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
-#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
-#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
-#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
-#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
-#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
-#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
-#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
-
-/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
-    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
-    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
-    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
-    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Clock Enable              */
-    uint32_t USB_:1;           /*!< bit:      5  USB APB Clock Enable               */
-    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_APBBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
-#define PM_APBBMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
-
-#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
-#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
-#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
-#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
-#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
-#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
-#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
-#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
-#define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
-#define PM_APBBMASK_DMAC            (0x1ul << PM_APBBMASK_DMAC_Pos)
-#define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
-#define PM_APBBMASK_USB             (0x1ul << PM_APBBMASK_USB_Pos)
-#define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
-#define PM_APBBMASK_HMATRIX         (0x1ul << PM_APBBMASK_HMATRIX_Pos)
-#define PM_APBBMASK_MASK            0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
-
-/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
-    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
-    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
-    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
-    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
-    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
-    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
-    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
-    uint32_t TCC0_:1;          /*!< bit:      8  TCC0 APB Clock Enable              */
-    uint32_t TCC1_:1;          /*!< bit:      9  TCC1 APB Clock Enable              */
-    uint32_t TCC2_:1;          /*!< bit:     10  TCC2 APB Clock Enable              */
-    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
-    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
-    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
-    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
-    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
-    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
-    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
-    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
-    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
-    uint32_t I2S_:1;           /*!< bit:     20  I2S APB Clock Enable               */
-    uint32_t AC1_:1;           /*!< bit:     21  AC1 APB Clock Enable               */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_APBCMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
-#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
-
-#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
-#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
-#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
-#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
-#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
-#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
-#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
-#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
-#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
-#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
-#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
-#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
-#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
-#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
-#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
-#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
-#define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
-#define PM_APBCMASK_TCC0            (0x1ul << PM_APBCMASK_TCC0_Pos)
-#define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
-#define PM_APBCMASK_TCC1            (0x1ul << PM_APBCMASK_TCC1_Pos)
-#define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
-#define PM_APBCMASK_TCC2            (0x1ul << PM_APBCMASK_TCC2_Pos)
-#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
-#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
-#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
-#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
-#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
-#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
-#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
-#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
-#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
-#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
-#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
-#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
-#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
-#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
-#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
-#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
-#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
-#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
-#define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
-#define PM_APBCMASK_I2S             (0x1ul << PM_APBCMASK_I2S_Pos)
-#define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
-#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
-#define PM_APBCMASK_MASK            0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
-
-/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
-#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
-#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
-#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
-
-/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
-#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
-
-#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
-#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
-#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
-
-/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
-#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
-#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
-
-/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
-    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
-    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
-    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
-    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_RCAUSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
-#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
-
-#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
-#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
-#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
-#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
-#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
-#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
-#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
-#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
-#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
-#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
-#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
-#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
-#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
-
-/** \brief PM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
-  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
-  __IO PM_EXTCTRL_Type           EXTCTRL;     /**< \brief Offset: 0x02 (R/W  8) External Reset Controller */
-       RoReg8                    Reserved1[0x5];
-  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
-  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
-  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
-  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
-       RoReg8                    Reserved2[0x8];
-  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
-  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
-  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
-  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
-       RoReg8                    Reserved3[0x10];
-  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
-  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
-  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
-} Pm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_PM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM                      0x212
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
+#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W  8) External Reset Controller -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SETDIS:1;         /*!< bit:      0  External Reset Disable             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_EXTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_EXTCTRL_OFFSET           0x02         /**< \brief (PM_EXTCTRL offset) External Reset Controller */
+#define PM_EXTCTRL_RESETVALUE       0x00ul       /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
+
+#define PM_EXTCTRL_SETDIS_Pos       0            /**< \brief (PM_EXTCTRL) External Reset Disable */
+#define PM_EXTCTRL_SETDIS           (0x1ul << PM_EXTCTRL_SETDIS_Pos)
+#define PM_EXTCTRL_MASK             0x01ul       /**< \brief (PM_EXTCTRL) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
+#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
+#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
+#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
+#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
+#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
+#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
+#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
+#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
+#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
+#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
+#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
+#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
+#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
+#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
+#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
+#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
+#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
+#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
+#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
+#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
+#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
+#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
+#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
+#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
+#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
+#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
+#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
+#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
+#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
+#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
+#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
+#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
+    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
+    uint32_t DMAC_:1;          /*!< bit:      5  DMAC AHB Clock Mask                */
+    uint32_t USB_:1;           /*!< bit:      6  USB AHB Clock Mask                 */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE       0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC             (0x1ul << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB              (0x1ul << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK             0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
+    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
+    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
+    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Clock Enable              */
+    uint32_t USB_:1;           /*!< bit:      5  USB APB Clock Enable               */
+    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC            (0x1ul << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB             (0x1ul << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
+#define PM_APBBMASK_HMATRIX         (0x1ul << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK            0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
+    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
+    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
+    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
+    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
+    uint32_t TCC0_:1;          /*!< bit:      8  TCC0 APB Clock Enable              */
+    uint32_t TCC1_:1;          /*!< bit:      9  TCC1 APB Clock Enable              */
+    uint32_t TCC2_:1;          /*!< bit:     10  TCC2 APB Clock Enable              */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
+    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
+    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
+    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
+    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
+    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
+    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
+    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
+    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
+    uint32_t I2S_:1;           /*!< bit:     20  I2S APB Clock Enable               */
+    uint32_t AC1_:1;           /*!< bit:     21  AC1 APB Clock Enable               */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0            (0x1ul << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1            (0x1ul << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2            (0x1ul << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S             (0x1ul << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
+#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
+#define PM_APBCMASK_MASK            0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
+    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
+    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
+    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
+    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
+  __IO PM_EXTCTRL_Type           EXTCTRL;     /**< \brief Offset: 0x02 (R/W  8) External Reset Controller */
+       RoReg8                    Reserved1[0x5];
+  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
+  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
+  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
+  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
+       RoReg8                    Reserved2[0x8];
+  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+       RoReg8                    Reserved3[0x10];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm_variant_d.h
index f3b72fc..86fc0d8 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/pm_variant_d.h
@@ -1,549 +1,549 @@
-/**
- * \file
- *
- * \brief Component description for PM
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PM_COMPONENT_
-#define _SAMD21_PM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PM */
-/* ========================================================================== */
-/** \addtogroup SAMD21_PM Power Manager */
-/*@{*/
-
-#define PM_U2206
-#define REV_PM                      0x212
-
-/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
-#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
-
-#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
-
-/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_SLEEP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
-#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
-
-#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
-#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
-#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
-#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
-#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
-#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
-
-/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W  8) External Reset Controller -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SETDIS:1;         /*!< bit:      0  External Reset Disable             */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_EXTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_EXTCTRL_OFFSET           0x02         /**< \brief (PM_EXTCTRL offset) External Reset Controller */
-#define PM_EXTCTRL_RESETVALUE       0x00ul       /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
-
-#define PM_EXTCTRL_SETDIS_Pos       0            /**< \brief (PM_EXTCTRL) External Reset Disable */
-#define PM_EXTCTRL_SETDIS           (0x1ul << PM_EXTCTRL_SETDIS_Pos)
-#define PM_EXTCTRL_MASK             0x01ul       /**< \brief (PM_EXTCTRL) MASK Register */
-
-/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_CPUSEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
-#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
-
-#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
-#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
-#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
-#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
-#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
-#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
-#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
-#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
-#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
-#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
-#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
-
-/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_APBASEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
-#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
-
-#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
-#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
-#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
-#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
-#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
-#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
-#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
-#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
-#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
-#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
-#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
-
-/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_APBBSEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
-#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
-
-#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
-#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
-#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
-#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
-#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
-#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
-#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
-#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
-#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
-#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
-#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
-
-/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_APBCSEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
-#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
-
-#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
-#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
-#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
-#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
-#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
-#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
-#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
-#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
-#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
-#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
-#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
-
-/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
-    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
-    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
-    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
-    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
-    uint32_t DMAC_:1;          /*!< bit:      5  DMAC AHB Clock Mask                */
-    uint32_t USB_:1;           /*!< bit:      6  USB AHB Clock Mask                 */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_AHBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
-#define PM_AHBMASK_RESETVALUE       0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
-
-#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
-#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
-#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
-#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
-#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
-#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
-#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
-#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
-#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
-#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
-#define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
-#define PM_AHBMASK_DMAC             (0x1ul << PM_AHBMASK_DMAC_Pos)
-#define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
-#define PM_AHBMASK_USB              (0x1ul << PM_AHBMASK_USB_Pos)
-#define PM_AHBMASK_MASK             0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
-
-/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
-    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
-    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
-    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
-    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
-    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
-    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_APBAMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
-#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
-
-#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
-#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
-#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
-#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
-#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
-#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
-#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
-#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
-#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
-#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
-#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
-#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
-#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
-#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
-#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
-
-/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
-    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
-    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
-    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
-    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Clock Enable              */
-    uint32_t USB_:1;           /*!< bit:      5  USB APB Clock Enable               */
-    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_APBBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
-#define PM_APBBMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
-
-#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
-#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
-#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
-#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
-#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
-#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
-#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
-#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
-#define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
-#define PM_APBBMASK_DMAC            (0x1ul << PM_APBBMASK_DMAC_Pos)
-#define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
-#define PM_APBBMASK_USB             (0x1ul << PM_APBBMASK_USB_Pos)
-#define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
-#define PM_APBBMASK_HMATRIX         (0x1ul << PM_APBBMASK_HMATRIX_Pos)
-#define PM_APBBMASK_MASK            0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
-
-/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
-    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
-    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
-    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
-    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
-    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
-    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
-    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
-    uint32_t TCC0_:1;          /*!< bit:      8  TCC0 APB Clock Enable              */
-    uint32_t TCC1_:1;          /*!< bit:      9  TCC1 APB Clock Enable              */
-    uint32_t TCC2_:1;          /*!< bit:     10  TCC2 APB Clock Enable              */
-    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
-    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
-    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
-    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
-    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
-    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
-    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
-    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
-    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
-    uint32_t I2S_:1;           /*!< bit:     20  I2S APB Clock Enable               */
-    uint32_t AC1_:1;           /*!< bit:     21  AC1 APB Clock Enable               */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t TCC3_:1;          /*!< bit:     24  TCC3 APB Clock Enable              */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PM_APBCMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
-#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
-
-#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
-#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
-#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
-#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
-#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
-#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
-#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
-#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
-#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
-#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
-#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
-#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
-#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
-#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
-#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
-#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
-#define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
-#define PM_APBCMASK_TCC0            (0x1ul << PM_APBCMASK_TCC0_Pos)
-#define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
-#define PM_APBCMASK_TCC1            (0x1ul << PM_APBCMASK_TCC1_Pos)
-#define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
-#define PM_APBCMASK_TCC2            (0x1ul << PM_APBCMASK_TCC2_Pos)
-#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
-#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
-#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
-#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
-#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
-#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
-#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
-#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
-#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
-#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
-#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
-#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
-#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
-#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
-#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
-#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
-#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
-#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
-#define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
-#define PM_APBCMASK_I2S             (0x1ul << PM_APBCMASK_I2S_Pos)
-#define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
-#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
-#define PM_APBCMASK_TCC3_Pos        24           /**< \brief (PM_APBCMASK) TCC3 APB Clock Enable */
-#define PM_APBCMASK_TCC3            (_U_(0x1) << PM_APBCMASK_TCC3_Pos)
-#define PM_APBCMASK_MASK            0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
-
-/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
-#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
-#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
-#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
-
-/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
-#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
-
-#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
-#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
-#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
-
-/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
-#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
-#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
-
-/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
-    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
-    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
-    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
-    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_RCAUSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
-#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
-
-#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
-#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
-#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
-#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
-#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
-#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
-#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
-#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
-#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
-#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
-#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
-#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
-#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
-
-/** \brief PM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
-  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
-  __IO PM_EXTCTRL_Type           EXTCTRL;     /**< \brief Offset: 0x02 (R/W  8) External Reset Controller */
-       RoReg8                    Reserved1[0x5];
-  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
-  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
-  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
-  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
-       RoReg8                    Reserved2[0x8];
-  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
-  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
-  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
-  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
-       RoReg8                    Reserved3[0x10];
-  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
-  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
-  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
-} Pm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_PM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM                      0x212
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
+#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W  8) External Reset Controller -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SETDIS:1;         /*!< bit:      0  External Reset Disable             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_EXTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_EXTCTRL_OFFSET           0x02         /**< \brief (PM_EXTCTRL offset) External Reset Controller */
+#define PM_EXTCTRL_RESETVALUE       0x00ul       /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
+
+#define PM_EXTCTRL_SETDIS_Pos       0            /**< \brief (PM_EXTCTRL) External Reset Disable */
+#define PM_EXTCTRL_SETDIS           (0x1ul << PM_EXTCTRL_SETDIS_Pos)
+#define PM_EXTCTRL_MASK             0x01ul       /**< \brief (PM_EXTCTRL) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
+#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
+#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
+#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
+#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
+#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
+#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
+#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
+#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
+#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
+#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
+#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
+#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
+#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
+#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
+#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
+#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
+#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
+#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
+#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
+#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
+#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
+#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
+#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
+#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
+#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
+#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
+#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
+#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
+#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
+#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
+#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
+#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
+    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
+    uint32_t DMAC_:1;          /*!< bit:      5  DMAC AHB Clock Mask                */
+    uint32_t USB_:1;           /*!< bit:      6  USB AHB Clock Mask                 */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE       0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC             (0x1ul << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB              (0x1ul << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK             0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
+    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
+    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
+    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Clock Enable              */
+    uint32_t USB_:1;           /*!< bit:      5  USB APB Clock Enable               */
+    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC            (0x1ul << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB             (0x1ul << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
+#define PM_APBBMASK_HMATRIX         (0x1ul << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK            0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
+    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
+    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
+    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
+    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
+    uint32_t TCC0_:1;          /*!< bit:      8  TCC0 APB Clock Enable              */
+    uint32_t TCC1_:1;          /*!< bit:      9  TCC1 APB Clock Enable              */
+    uint32_t TCC2_:1;          /*!< bit:     10  TCC2 APB Clock Enable              */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
+    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
+    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
+    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
+    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
+    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
+    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
+    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
+    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
+    uint32_t I2S_:1;           /*!< bit:     20  I2S APB Clock Enable               */
+    uint32_t AC1_:1;           /*!< bit:     21  AC1 APB Clock Enable               */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t TCC3_:1;          /*!< bit:     24  TCC3 APB Clock Enable              */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0            (0x1ul << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1            (0x1ul << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2            (0x1ul << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S             (0x1ul << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
+#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
+#define PM_APBCMASK_TCC3_Pos        24           /**< \brief (PM_APBCMASK) TCC3 APB Clock Enable */
+#define PM_APBCMASK_TCC3            (_U_(0x1) << PM_APBCMASK_TCC3_Pos)
+#define PM_APBCMASK_MASK            0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
+    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
+    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
+    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
+    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
+  __IO PM_EXTCTRL_Type           EXTCTRL;     /**< \brief Offset: 0x02 (R/W  8) External Reset Controller */
+       RoReg8                    Reserved1[0x5];
+  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
+  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
+  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
+  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
+       RoReg8                    Reserved2[0x8];
+  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+       RoReg8                    Reserved3[0x10];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h
index 61a3e9c..07c0e82 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h
@@ -1,384 +1,384 @@
-/**
- * \file
- *
- * \brief Component description for PORT
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PORT_COMPONENT_
-#define _SAMD21_PORT_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PORT */
-/* ========================================================================== */
-/** \addtogroup SAMD21_PORT Port Module */
-/*@{*/
-
-#define PORT_U2210
-#define REV_PORT                    0x100
-
-/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
-#define PORT_DIR_RESETVALUE         0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
-
-#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
-#define PORT_DIR_DIR_Msk            (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
-#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
-#define PORT_DIR_MASK               0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
-
-/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIRCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
-#define PORT_DIRCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
-
-#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
-#define PORT_DIRCLR_DIRCLR_Msk      (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
-#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
-#define PORT_DIRCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
-
-/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIRSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
-#define PORT_DIRSET_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
-
-#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
-#define PORT_DIRSET_DIRSET_Msk      (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
-#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
-#define PORT_DIRSET_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
-
-/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIRTGL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
-#define PORT_DIRTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
-
-#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
-#define PORT_DIRTGL_DIRTGL_Msk      (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
-#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
-#define PORT_DIRTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
-
-/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUT:32;           /*!< bit:  0..31  Port Data Output Value             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
-#define PORT_OUT_RESETVALUE         0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
-
-#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) Port Data Output Value */
-#define PORT_OUT_OUT_Msk            (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
-#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
-#define PORT_OUT_MASK               0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
-
-/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUTCLR:32;        /*!< bit:  0..31  Port Data Output Value Clear       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUTCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
-#define PORT_OUTCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
-
-#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
-#define PORT_OUTCLR_OUTCLR_Msk      (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
-#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
-#define PORT_OUTCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
-
-/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUTSET:32;        /*!< bit:  0..31  Port Data Output Value Set         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUTSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
-#define PORT_OUTSET_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
-
-#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) Port Data Output Value Set */
-#define PORT_OUTSET_OUTSET_Msk      (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
-#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
-#define PORT_OUTSET_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
-
-/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUTTGL:32;        /*!< bit:  0..31  Port Data Output Value Toggle      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUTTGL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
-#define PORT_OUTTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
-
-#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
-#define PORT_OUTTGL_OUTTGL_Msk      (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
-#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
-#define PORT_OUTTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
-
-/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IN:32;            /*!< bit:  0..31  Port Data Input Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_IN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
-#define PORT_IN_RESETVALUE          0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
-
-#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) Port Data Input Value */
-#define PORT_IN_IN_Msk              (0xFFFFFFFFul << PORT_IN_IN_Pos)
-#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
-#define PORT_IN_MASK                0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
-
-/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
-#define PORT_CTRL_RESETVALUE        0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
-
-#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
-#define PORT_CTRL_SAMPLING_Msk      (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
-#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
-#define PORT_CTRL_MASK              0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
-
-/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
-    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
-    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
-    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
-    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
-    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
-    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
-    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_WRCONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
-#define PORT_WRCONFIG_RESETVALUE    0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
-
-#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
-#define PORT_WRCONFIG_PINMASK_Msk   (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
-#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
-#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
-#define PORT_WRCONFIG_PMUXEN        (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
-#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
-#define PORT_WRCONFIG_INEN          (0x1ul << PORT_WRCONFIG_INEN_Pos)
-#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
-#define PORT_WRCONFIG_PULLEN        (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
-#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
-#define PORT_WRCONFIG_DRVSTR        (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
-#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
-#define PORT_WRCONFIG_PMUX_Msk      (0xFul << PORT_WRCONFIG_PMUX_Pos)
-#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
-#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
-#define PORT_WRCONFIG_WRPMUX        (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
-#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
-#define PORT_WRCONFIG_WRPINCFG      (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
-#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
-#define PORT_WRCONFIG_HWSEL         (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
-#define PORT_WRCONFIG_MASK          0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
-
-/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing Even       */
-    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing Odd        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PORT_PMUX_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
-#define PORT_PMUX_RESETVALUE        0x00ul       /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
-
-#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
-#define PORT_PMUX_PMUXE_Msk         (0xFul << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
-#define   PORT_PMUX_PMUXE_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
-#define   PORT_PMUX_PMUXE_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
-#define   PORT_PMUX_PMUXE_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
-#define   PORT_PMUX_PMUXE_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
-#define   PORT_PMUX_PMUXE_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
-#define   PORT_PMUX_PMUXE_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
-#define   PORT_PMUX_PMUXE_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
-#define   PORT_PMUX_PMUXE_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
-#define PORT_PMUX_PMUXE_A           (PORT_PMUX_PMUXE_A_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_B           (PORT_PMUX_PMUXE_B_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_C           (PORT_PMUX_PMUXE_C_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_D           (PORT_PMUX_PMUXE_D_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_E           (PORT_PMUX_PMUXE_E_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_F           (PORT_PMUX_PMUXE_F_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_G           (PORT_PMUX_PMUXE_G_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE_H           (PORT_PMUX_PMUXE_H_Val         << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
-#define PORT_PMUX_PMUXO_Msk         (0xFul << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
-#define   PORT_PMUX_PMUXO_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
-#define   PORT_PMUX_PMUXO_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
-#define   PORT_PMUX_PMUXO_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
-#define   PORT_PMUX_PMUXO_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
-#define   PORT_PMUX_PMUXO_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
-#define   PORT_PMUX_PMUXO_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
-#define   PORT_PMUX_PMUXO_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
-#define   PORT_PMUX_PMUXO_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
-#define PORT_PMUX_PMUXO_A           (PORT_PMUX_PMUXO_A_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_B           (PORT_PMUX_PMUXO_B_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_C           (PORT_PMUX_PMUXO_C_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_D           (PORT_PMUX_PMUXO_D_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_E           (PORT_PMUX_PMUXO_E_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_F           (PORT_PMUX_PMUXO_F_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_G           (PORT_PMUX_PMUXO_G_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO_H           (PORT_PMUX_PMUXO_H_Val         << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_MASK              0xFFul       /**< \brief (PORT_PMUX) MASK Register */
-
-/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
-    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
-    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
-    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PORT_PINCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration n */
-#define PORT_PINCFG_RESETVALUE      0x00ul       /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
-
-#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
-#define PORT_PINCFG_PMUXEN          (0x1ul << PORT_PINCFG_PMUXEN_Pos)
-#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
-#define PORT_PINCFG_INEN            (0x1ul << PORT_PINCFG_INEN_Pos)
-#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
-#define PORT_PINCFG_PULLEN          (0x1ul << PORT_PINCFG_PULLEN_Pos)
-#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
-#define PORT_PINCFG_DRVSTR          (0x1ul << PORT_PINCFG_DRVSTR_Pos)
-#define PORT_PINCFG_MASK            0x47ul       /**< \brief (PORT_PINCFG) MASK Register */
-
-/** \brief PortGroup hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
-  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
-  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
-  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
-  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
-  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
-  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
-  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
-  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
-  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
-  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
-       RoReg8                    Reserved1[0x4];
-  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
-  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration n */
-       RoReg8                    Reserved2[0x20];
-} PortGroup;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief PORT hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-       PortGroup                 Group[2];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
-} Port;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_PORT_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_COMPONENT_
+#define _SAMD21_PORT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT                    0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE         0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk            (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK               0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk      (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk      (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk      (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUT:32;           /*!< bit:  0..31  Port Data Output Value             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE         0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk            (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK               0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTCLR:32;        /*!< bit:  0..31  Port Data Output Value Clear       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk      (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTSET:32;        /*!< bit:  0..31  Port Data Output Value Set         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk      (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTTGL:32;        /*!< bit:  0..31  Port Data Output Value Toggle      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE      0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk      (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK            0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN:32;            /*!< bit:  0..31  Port Data Input Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE          0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk              (0xFFFFFFFFul << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK                0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE        0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk      (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK              0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
+    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
+    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
+    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
+    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
+    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
+    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
+    uint32_t :1;               /*!< bit:     29  Reserved                           */
+    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
+    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE    0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk   (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN        (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN          (0x1ul << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN        (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR        (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk      (0xFul << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX        (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG      (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL         (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK          0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing Even       */
+    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing Odd        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE        0x00ul       /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk         (0xFul << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define   PORT_PMUX_PMUXE_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXE_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXE_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXE_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXE_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXE_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXE_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXE_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A           (PORT_PMUX_PMUXE_A_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B           (PORT_PMUX_PMUXE_B_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C           (PORT_PMUX_PMUXE_C_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D           (PORT_PMUX_PMUXE_D_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E           (PORT_PMUX_PMUXE_E_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F           (PORT_PMUX_PMUXE_F_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G           (PORT_PMUX_PMUXE_G_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H           (PORT_PMUX_PMUXE_H_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk         (0xFul << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define   PORT_PMUX_PMUXO_A_Val           0x0ul  /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXO_B_Val           0x1ul  /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXO_C_Val           0x2ul  /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXO_D_Val           0x3ul  /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXO_E_Val           0x4ul  /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXO_F_Val           0x5ul  /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXO_G_Val           0x6ul  /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXO_H_Val           0x7ul  /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A           (PORT_PMUX_PMUXO_A_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B           (PORT_PMUX_PMUXO_B_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C           (PORT_PMUX_PMUXO_C_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D           (PORT_PMUX_PMUXO_D_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E           (PORT_PMUX_PMUXO_E_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F           (PORT_PMUX_PMUXO_F_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G           (PORT_PMUX_PMUXO_G_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H           (PORT_PMUX_PMUXO_H_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK              0xFFul       /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
+    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
+    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE      0x00ul       /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN          (0x1ul << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN            (0x1ul << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN          (0x1ul << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR          (0x1ul << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK            0x47ul       /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
+  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
+  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+       RoReg8                    Reserved1[0x4];
+  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
+  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration n */
+       RoReg8                    Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       PortGroup                 Group[2];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PORT_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h
index dd8f8fb..6b25173 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h
@@ -1,1058 +1,1058 @@
-/**
- * \file
- *
- * \brief Component description for RTC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_RTC_COMPONENT_
-#define _SAMD21_RTC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR RTC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_RTC Real-Time Counter */
-/*@{*/
-
-#define RTC_U2202
-#define REV_RTC                     0x101
-
-/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
-    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
-    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
-#define RTC_MODE0_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
-
-#define RTC_MODE0_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE0_CTRL) Software Reset */
-#define RTC_MODE0_CTRL_SWRST        (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
-#define RTC_MODE0_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE0_CTRL) Enable */
-#define RTC_MODE0_CTRL_ENABLE       (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
-#define RTC_MODE0_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE0_CTRL) Operating Mode */
-#define RTC_MODE0_CTRL_MODE_Msk     (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
-#define RTC_MODE0_CTRL_MODE(value)  (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
-#define   RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
-#define   RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
-#define   RTC_MODE0_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
-#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
-#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
-#define RTC_MODE0_CTRL_MODE_CLOCK   (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
-#define RTC_MODE0_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRL) Clear on Match */
-#define RTC_MODE0_CTRL_MATCHCLR     (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRL) Prescaler */
-#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
-#define   RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
-#define   RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
-#define RTC_MODE0_CTRL_MASK         0x0F8Ful     /**< \brief (RTC_MODE0_CTRL) MASK Register */
-
-/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
-    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
-#define RTC_MODE1_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
-
-#define RTC_MODE1_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE1_CTRL) Software Reset */
-#define RTC_MODE1_CTRL_SWRST        (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
-#define RTC_MODE1_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE1_CTRL) Enable */
-#define RTC_MODE1_CTRL_ENABLE       (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
-#define RTC_MODE1_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE1_CTRL) Operating Mode */
-#define RTC_MODE1_CTRL_MODE_Msk     (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
-#define RTC_MODE1_CTRL_MODE(value)  (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
-#define   RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
-#define   RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
-#define   RTC_MODE1_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
-#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
-#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
-#define RTC_MODE1_CTRL_MODE_CLOCK   (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRL) Prescaler */
-#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
-#define   RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
-#define   RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
-#define RTC_MODE1_CTRL_MASK         0x0F0Ful     /**< \brief (RTC_MODE1_CTRL) MASK Register */
-
-/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
-    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
-    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
-    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
-#define RTC_MODE2_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
-
-#define RTC_MODE2_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE2_CTRL) Software Reset */
-#define RTC_MODE2_CTRL_SWRST        (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
-#define RTC_MODE2_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE2_CTRL) Enable */
-#define RTC_MODE2_CTRL_ENABLE       (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
-#define RTC_MODE2_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE2_CTRL) Operating Mode */
-#define RTC_MODE2_CTRL_MODE_Msk     (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
-#define RTC_MODE2_CTRL_MODE(value)  (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
-#define   RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
-#define   RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
-#define   RTC_MODE2_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
-#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
-#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
-#define RTC_MODE2_CTRL_MODE_CLOCK   (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
-#define RTC_MODE2_CTRL_CLKREP_Pos   6            /**< \brief (RTC_MODE2_CTRL) Clock Representation */
-#define RTC_MODE2_CTRL_CLKREP       (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
-#define RTC_MODE2_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRL) Clear on Match */
-#define RTC_MODE2_CTRL_MATCHCLR     (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRL) Prescaler */
-#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
-#define   RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
-#define   RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
-#define RTC_MODE2_CTRL_MASK         0x0FCFul     /**< \brief (RTC_MODE2_CTRL) MASK Register */
-
-/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ADDR:6;           /*!< bit:  0.. 5  Address                            */
-    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
-    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
-    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_READREQ_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_READREQ_OFFSET          0x02         /**< \brief (RTC_READREQ offset) Read Request */
-#define RTC_READREQ_RESETVALUE      0x0010ul     /**< \brief (RTC_READREQ reset_value) Read Request */
-
-#define RTC_READREQ_ADDR_Pos        0            /**< \brief (RTC_READREQ) Address */
-#define RTC_READREQ_ADDR_Msk        (0x3Ful << RTC_READREQ_ADDR_Pos)
-#define RTC_READREQ_ADDR(value)     (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
-#define RTC_READREQ_RCONT_Pos       14           /**< \brief (RTC_READREQ) Read Continuously */
-#define RTC_READREQ_RCONT           (0x1ul << RTC_READREQ_RCONT_Pos)
-#define RTC_READREQ_RREQ_Pos        15           /**< \brief (RTC_READREQ) Read Request */
-#define RTC_READREQ_RREQ            (0x1ul << RTC_READREQ_RREQ_Pos)
-#define RTC_READREQ_MASK            0xC03Ful     /**< \brief (RTC_READREQ) MASK Register */
-
-/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
-    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
-    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
-    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
-    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
-    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
-    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
-    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
-    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
-    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
-    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
-    uint16_t CMPEO:1;          /*!< bit:      8  Compare x Event Output Enable      */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
-#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
-
-#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO0     (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
-#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO1     (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
-#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO2     (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
-#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO3     (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
-#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO4     (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
-#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO5     (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
-#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO6     (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
-#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO7     (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
-#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
-#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
-#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO0     (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO_Msk  (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
-#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE0_EVCTRL_OVFEO      (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
-#define RTC_MODE0_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
-    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
-    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
-    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
-    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
-    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
-    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
-    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
-    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
-    uint16_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
-    uint16_t :5;               /*!< bit: 10..14  Reserved                           */
-    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
-    uint16_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
-#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
-
-#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO0     (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
-#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO1     (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
-#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO2     (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
-#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO3     (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
-#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO4     (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
-#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO5     (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
-#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO6     (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
-#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO7     (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
-#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
-#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
-#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO0     (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO1     (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO_Msk  (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
-#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE1_EVCTRL_OVFEO      (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
-#define RTC_MODE1_EVCTRL_MASK       0x83FFul     /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
-    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
-    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
-    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
-    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
-    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
-    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
-    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
-    uint16_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
-    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
-    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
-    uint16_t ALARMEO:1;        /*!< bit:      8  Alarm x Event Output Enable        */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
-#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
-
-#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO0     (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
-#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO1     (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
-#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO2     (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
-#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO3     (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
-#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO4     (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
-#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO5     (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
-#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO6     (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
-#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO7     (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
-#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
-#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
-#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO0   (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
-#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE2_EVCTRL_OVFEO      (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
-#define RTC_MODE2_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE0 MODE0 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
-    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
-    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE0_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
-#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
-
-#define RTC_MODE0_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP0     (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
-#define RTC_MODE0_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP_Msk  (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
-#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
-#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
-#define RTC_MODE0_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
-#define RTC_MODE0_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE0_INTENCLR_OVF      (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
-#define RTC_MODE0_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE1 MODE1 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
-    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
-    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE1_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
-#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
-
-#define RTC_MODE1_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP0     (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
-#define RTC_MODE1_INTENCLR_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP1     (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
-#define RTC_MODE1_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP_Msk  (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
-#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
-#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
-#define RTC_MODE1_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
-#define RTC_MODE1_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE1_INTENCLR_OVF      (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
-#define RTC_MODE1_INTENCLR_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE2 MODE2 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
-    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
-    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE2_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
-#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
-
-#define RTC_MODE2_INTENCLR_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM0   (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
-#define RTC_MODE2_INTENCLR_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
-#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
-#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
-#define RTC_MODE2_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
-#define RTC_MODE2_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE2_INTENCLR_OVF      (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
-#define RTC_MODE2_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE0 MODE0 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
-    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
-    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE0_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
-#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
-
-#define RTC_MODE0_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP0     (1 << RTC_MODE0_INTENSET_CMP0_Pos)
-#define RTC_MODE0_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP_Msk  (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
-#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
-#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
-#define RTC_MODE0_INTENSET_SYNCRDY  (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
-#define RTC_MODE0_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE0_INTENSET_OVF      (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
-#define RTC_MODE0_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENSET) MASK Register */
-
-/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE1 MODE1 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
-    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
-    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE1_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
-#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
-
-#define RTC_MODE1_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP0     (1 << RTC_MODE1_INTENSET_CMP0_Pos)
-#define RTC_MODE1_INTENSET_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP1     (1 << RTC_MODE1_INTENSET_CMP1_Pos)
-#define RTC_MODE1_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP_Msk  (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
-#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
-#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
-#define RTC_MODE1_INTENSET_SYNCRDY  (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
-#define RTC_MODE1_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE1_INTENSET_OVF      (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
-#define RTC_MODE1_INTENSET_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENSET) MASK Register */
-
-/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE2 MODE2 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
-    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
-    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE2_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
-#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
-
-#define RTC_MODE2_INTENSET_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM0   (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
-#define RTC_MODE2_INTENSET_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
-#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
-#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
-#define RTC_MODE2_INTENSET_SYNCRDY  (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
-#define RTC_MODE2_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE2_INTENSET_OVF      (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
-#define RTC_MODE2_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENSET) MASK Register */
-
-/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
-    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
-    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
-    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  CMP:1;            /*!< bit:      0  Compare x                          */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE0_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
-#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
-
-#define RTC_MODE0_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
-#define RTC_MODE0_INTFLAG_CMP0      (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
-#define RTC_MODE0_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
-#define RTC_MODE0_INTFLAG_CMP_Msk   (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
-#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
-#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
-#define RTC_MODE0_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
-#define RTC_MODE0_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE0_INTFLAG) Overflow */
-#define RTC_MODE0_INTFLAG_OVF       (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
-#define RTC_MODE0_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
-
-/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
-    __I uint8_t  CMP1:1;           /*!< bit:      1  Compare 1                          */
-    __I uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
-    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x                          */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE1_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
-#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
-
-#define RTC_MODE1_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
-#define RTC_MODE1_INTFLAG_CMP0      (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
-#define RTC_MODE1_INTFLAG_CMP1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
-#define RTC_MODE1_INTFLAG_CMP1      (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
-#define RTC_MODE1_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
-#define RTC_MODE1_INTFLAG_CMP_Msk   (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
-#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
-#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
-#define RTC_MODE1_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
-#define RTC_MODE1_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE1_INTFLAG) Overflow */
-#define RTC_MODE1_INTFLAG_OVF       (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
-#define RTC_MODE1_INTFLAG_MASK      0xC3ul       /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
-
-/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0                            */
-    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
-    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
-    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  ALARM:1;          /*!< bit:      0  Alarm x                            */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE2_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
-#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
-
-#define RTC_MODE2_INTFLAG_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
-#define RTC_MODE2_INTFLAG_ALARM0    (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
-#define RTC_MODE2_INTFLAG_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
-#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
-#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
-#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
-#define RTC_MODE2_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
-#define RTC_MODE2_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE2_INTFLAG) Overflow */
-#define RTC_MODE2_INTFLAG_OVF       (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
-#define RTC_MODE2_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
-
-/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W  8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_STATUS_OFFSET           0x0A         /**< \brief (RTC_STATUS offset) Status */
-#define RTC_STATUS_RESETVALUE       0x00ul       /**< \brief (RTC_STATUS reset_value) Status */
-
-#define RTC_STATUS_SYNCBUSY_Pos     7            /**< \brief (RTC_STATUS) Synchronization Busy */
-#define RTC_STATUS_SYNCBUSY         (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
-#define RTC_STATUS_MASK             0x80ul       /**< \brief (RTC_STATUS) MASK Register */
-
-/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_DBGCTRL_OFFSET          0x0B         /**< \brief (RTC_DBGCTRL offset) Debug Control */
-#define RTC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
-
-#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
-#define RTC_DBGCTRL_DBGRUN          (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
-#define RTC_DBGCTRL_MASK            0x01ul       /**< \brief (RTC_DBGCTRL) MASK Register */
-
-/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W  8) Frequency Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
-    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_FREQCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_FREQCORR_OFFSET         0x0C         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
-#define RTC_FREQCORR_RESETVALUE     0x00ul       /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
-
-#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
-#define RTC_FREQCORR_VALUE_Msk      (0x7Ful << RTC_FREQCORR_VALUE_Pos)
-#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
-#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
-#define RTC_FREQCORR_SIGN           (0x1ul << RTC_FREQCORR_SIGN_Pos)
-#define RTC_FREQCORR_MASK           0xFFul       /**< \brief (RTC_FREQCORR) MASK Register */
-
-/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
-#define RTC_MODE0_COUNT_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
-
-#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
-#define RTC_MODE0_COUNT_COUNT_Msk   (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
-#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
-#define RTC_MODE0_COUNT_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
-
-/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
-#define RTC_MODE1_COUNT_RESETVALUE  0x0000ul     /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
-
-#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
-#define RTC_MODE1_COUNT_COUNT_Msk   (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
-#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
-#define RTC_MODE1_COUNT_MASK        0xFFFFul     /**< \brief (RTC_MODE1_COUNT) MASK Register */
-
-/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
-    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
-    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
-    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
-    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
-    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_CLOCK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CLOCK_OFFSET      0x10         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
-#define RTC_MODE2_CLOCK_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
-
-#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
-#define RTC_MODE2_CLOCK_SECOND_Msk  (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
-#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
-#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
-#define RTC_MODE2_CLOCK_MINUTE_Msk  (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
-#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
-#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
-#define RTC_MODE2_CLOCK_HOUR_Msk    (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
-#define   RTC_MODE2_CLOCK_HOUR_AM_Val     0x0ul  /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
-#define   RTC_MODE2_CLOCK_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
-#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
-#define RTC_MODE2_CLOCK_DAY_Msk     (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
-#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
-#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
-#define RTC_MODE2_CLOCK_MONTH_Msk   (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
-#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
-#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
-#define RTC_MODE2_CLOCK_YEAR_Msk    (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
-#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
-#define RTC_MODE2_CLOCK_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
-
-/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_PER_OFFSET        0x14         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
-#define RTC_MODE1_PER_RESETVALUE    0x0000ul     /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
-
-#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
-#define RTC_MODE1_PER_PER_Msk       (0xFFFFul << RTC_MODE1_PER_PER_Pos)
-#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
-#define RTC_MODE1_PER_MASK          0xFFFFul     /**< \brief (RTC_MODE1_PER) MASK Register */
-
-/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_COMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_COMP_OFFSET       0x18         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
-#define RTC_MODE0_COMP_RESETVALUE   0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
-
-#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
-#define RTC_MODE0_COMP_COMP_Msk     (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
-#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
-#define RTC_MODE0_COMP_MASK         0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
-
-/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_COMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_COMP_OFFSET       0x18         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
-#define RTC_MODE1_COMP_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
-
-#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
-#define RTC_MODE1_COMP_COMP_Msk     (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
-#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
-#define RTC_MODE1_COMP_MASK         0xFFFFul     /**< \brief (RTC_MODE1_COMP) MASK Register */
-
-/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
-    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
-    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
-    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
-    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
-    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_ALARM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_ALARM_OFFSET      0x18         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
-#define RTC_MODE2_ALARM_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
-
-#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
-#define RTC_MODE2_ALARM_SECOND_Msk  (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
-#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
-#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
-#define RTC_MODE2_ALARM_MINUTE_Msk  (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
-#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
-#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
-#define RTC_MODE2_ALARM_HOUR_Msk    (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
-#define   RTC_MODE2_ALARM_HOUR_AM_Val     0x0ul  /**< \brief (RTC_MODE2_ALARM) Morning hour */
-#define   RTC_MODE2_ALARM_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
-#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
-#define RTC_MODE2_ALARM_DAY_Msk     (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
-#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
-#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
-#define RTC_MODE2_ALARM_MONTH_Msk   (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
-#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
-#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
-#define RTC_MODE2_ALARM_YEAR_Msk    (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
-#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
-#define RTC_MODE2_ALARM_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
-
-/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE2_MASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_MASK_OFFSET       0x1C         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
-#define RTC_MODE2_MASK_RESETVALUE   0x00ul       /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
-
-#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
-#define RTC_MODE2_MASK_SEL_Msk      (0x7ul << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
-#define   RTC_MODE2_MASK_SEL_OFF_Val      0x0ul  /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
-#define   RTC_MODE2_MASK_SEL_SS_Val       0x1ul  /**< \brief (RTC_MODE2_MASK) Match seconds only */
-#define   RTC_MODE2_MASK_SEL_MMSS_Val     0x2ul  /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
-#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   0x3ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
-#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
-#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
-#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
-#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_MASK         0x07ul       /**< \brief (RTC_MODE2_MASK) MASK Register */
-
-/** \brief RtcMode2Alarm hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
-  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
-       RoReg8                    Reserved1[0x3];
-} RtcMode2Alarm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE0 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 32-bit Counter with Single 32-bit Compare */
-  __IO RTC_MODE0_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
-  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
-  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
-  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE0 Interrupt Enable Clear */
-  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE0 Interrupt Enable Set */
-  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE0 Interrupt Flag Status and Clear */
-       RoReg8                    Reserved1[0x1];
-  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
-  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
-  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
-       RoReg8                    Reserved2[0x3];
-  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
-       RoReg8                    Reserved3[0x4];
-  __IO RTC_MODE0_COMP_Type       COMP[1];     /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
-} RtcMode0;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE1 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 16-bit Counter with Two 16-bit Compares */
-  __IO RTC_MODE1_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
-  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
-  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
-  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE1 Interrupt Enable Clear */
-  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE1 Interrupt Enable Set */
-  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE1 Interrupt Flag Status and Clear */
-       RoReg8                    Reserved1[0x1];
-  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
-  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
-  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
-       RoReg8                    Reserved2[0x3];
-  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
-       RoReg8                    Reserved3[0x2];
-  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
-       RoReg8                    Reserved4[0x2];
-  __IO RTC_MODE1_COMP_Type       COMP[2];     /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
-} RtcMode1;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE2 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* Clock/Calendar with Alarm */
-  __IO RTC_MODE2_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
-  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
-  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
-  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE2 Interrupt Enable Clear */
-  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE2 Interrupt Enable Set */
-  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE2 Interrupt Flag Status and Clear */
-       RoReg8                    Reserved1[0x1];
-  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
-  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
-  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
-       RoReg8                    Reserved2[0x3];
-  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
-       RoReg8                    Reserved3[0x4];
-       RtcMode2Alarm             Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
-} RtcMode2;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
-       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
-       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
-} Rtc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_RTC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_COMPONENT_
+#define _SAMD21_RTC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC                     0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST        (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE       (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk     (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value)  (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
+#define   RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK   (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR     (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK         0x0F8Ful     /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST        (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE       (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk     (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value)  (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
+#define   RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK   (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK         0x0F0Ful     /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST        (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE       (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk     (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value)  (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
+#define   RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_CLOCK_Val   0x2ul  /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK   (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos   6            /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP       (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR     (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul  /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK         0x0FCFul     /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:6;           /*!< bit:  0.. 5  Address                            */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET          0x02         /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE      0x0010ul     /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos        0            /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk        (0x3Ful << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value)     (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
+#define RTC_READREQ_RCONT_Pos       14           /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT           (0x1ul << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos        15           /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ            (0x1ul << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK            0xC03Ful     /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:1;          /*!< bit:      8  Compare x Event Output Enable      */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0     (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1     (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2     (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3     (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4     (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5     (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6     (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7     (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0     (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk  (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO      (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
+    uint16_t :5;               /*!< bit: 10..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0     (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1     (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2     (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3     (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4     (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5     (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6     (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7     (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0     (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1     (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk  (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO      (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK       0x83FFul     /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t ALARMEO:1;        /*!< bit:      8  Alarm x Event Output Enable        */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul     /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0     (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1     (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2     (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3     (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4     (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5     (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6     (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7     (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk  (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0   (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO      (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK       0x81FFul     /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0     (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk  (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF      (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0     (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1     (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk  (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF      (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0   (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY  (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF      (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0     (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk  (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY  (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF      (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0     (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1     (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk  (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY  (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF      (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK     0xC3ul       /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0   (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY  (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF      (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK     0xC1ul       /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  CMP:1;            /*!< bit:      0  Compare x                          */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0      (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk   (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF       (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    __I uint8_t  CMP1:1;           /*!< bit:      1  Compare 1                          */
+    __I uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x                          */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0      (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1      (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk   (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF       (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK      0xC3ul       /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0                            */
+    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  ALARM:1;          /*!< bit:      0  Alarm x                            */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul       /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0    (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY   (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF       (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK      0xC1ul       /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W  8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET           0x0A         /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE       0x00ul       /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos     7            /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY         (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK             0x80ul       /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET          0x0B         /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN          (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK            0x01ul       /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W  8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
+    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET         0x0C         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE     0x00ul       /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk      (0x7Ful << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN           (0x1ul << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK           0xFFul       /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk   (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE  0x0000ul     /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk   (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK        0xFFFFul     /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET      0x10         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk  (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk  (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk    (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define   RTC_MODE2_CLOCK_HOUR_AM_Val     0x0ul  /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
+#define   RTC_MODE2_CLOCK_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk     (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk   (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk    (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET        0x14         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE    0x0000ul     /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk       (0xFFFFul << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK          0xFFFFul     /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET       0x18         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE   0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk     (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK         0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET       0x18         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE   0x0000ul     /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk     (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK         0xFFFFul     /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET      0x18         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE  0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk  (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk  (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk    (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define   RTC_MODE2_ALARM_HOUR_AM_Val     0x0ul  /**< \brief (RTC_MODE2_ALARM) Morning hour */
+#define   RTC_MODE2_ALARM_HOUR_PM_Val     0x10ul  /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
+#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk     (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk   (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk    (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK        0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET       0x1C         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE   0x00ul       /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk      (0x7ul << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define   RTC_MODE2_MASK_SEL_OFF_Val      0x0ul  /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define   RTC_MODE2_MASK_SEL_SS_Val       0x1ul  /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define   RTC_MODE2_MASK_SEL_MMSS_Val     0x2ul  /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   0x3ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul  /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK         0x07ul       /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
+       RoReg8                    Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+  __IO RTC_MODE0_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE0 Interrupt Enable Clear */
+  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE0 Interrupt Enable Set */
+  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE0 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO RTC_MODE0_COMP_Type       COMP[1];     /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+  __IO RTC_MODE1_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE1 Interrupt Enable Clear */
+  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE1 Interrupt Enable Set */
+  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE1 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+       RoReg8                    Reserved3[0x2];
+  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+       RoReg8                    Reserved4[0x2];
+  __IO RTC_MODE1_COMP_Type       COMP[2];     /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+  __IO RTC_MODE2_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE2 Interrupt Enable Clear */
+  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE2 Interrupt Enable Set */
+  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE2 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+       RoReg8                    Reserved3[0x4];
+       RtcMode2Alarm             Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_RTC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h
index ce53438..2efb0b4 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h
@@ -1,1498 +1,1498 @@
-/**
- * \file
- *
- * \brief Component description for SERCOM
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM_COMPONENT_
-#define _SAMD21_SERCOM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR SERCOM */
-/* ========================================================================== */
-/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
-/*@{*/
-
-#define SERCOM_U2201
-#define REV_SERCOM                  0x220
-
-/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
-    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
-    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
-    uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
-    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
-    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
-    uint32_t :1;               /*!< bit:     26  Reserved                           */
-    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
-    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
-    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
-#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
-
-#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
-#define SERCOM_I2CM_CTRLA_SWRST     (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
-#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
-#define SERCOM_I2CM_CTRLA_ENABLE    (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
-#define SERCOM_I2CM_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
-#define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
-#define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
-#define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
-#define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
-#define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
-#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
-#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
-#define SERCOM_I2CM_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
-#define SERCOM_I2CM_CTRLA_PINOUT    (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
-#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
-#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
-#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
-#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22           /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
-#define SERCOM_I2CM_CTRLA_MEXTTOEN  (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
-#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CM_CTRLA_SEXTTOEN  (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
-#define SERCOM_I2CM_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
-#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
-#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
-#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
-#define SERCOM_I2CM_CTRLA_SCLSM     (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
-#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
-#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
-#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
-#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
-#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
-#define SERCOM_I2CM_CTRLA_MASK      0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
-    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
-    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
-    uint32_t :1;               /*!< bit:     22  Reserved                           */
-    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
-    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
-    uint32_t :1;               /*!< bit:     26  Reserved                           */
-    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
-    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
-    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
-#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
-
-#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
-#define SERCOM_I2CS_CTRLA_SWRST     (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
-#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
-#define SERCOM_I2CS_CTRLA_ENABLE    (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
-#define SERCOM_I2CS_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
-#define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
-#define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
-#define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
-#define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
-#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
-#define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
-#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
-#define SERCOM_I2CS_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
-#define SERCOM_I2CS_CTRLA_PINOUT    (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
-#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
-#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
-#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
-#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CS_CTRLA_SEXTTOEN  (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
-#define SERCOM_I2CS_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
-#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
-#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
-#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
-#define SERCOM_I2CS_CTRLA_SCLSM     (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
-#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
-#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
-#define SERCOM_I2CS_CTRLA_MASK      0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
-    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
-    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
-    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
-    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
-    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
-#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
-
-#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
-#define SERCOM_SPI_CTRLA_SWRST      (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
-#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
-#define SERCOM_SPI_CTRLA_ENABLE     (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
-#define SERCOM_SPI_CTRLA_MODE_Msk   (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
-#define   SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
-#define   SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
-#define   SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
-#define   SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
-#define   SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
-#define   SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
-#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
-#define SERCOM_SPI_CTRLA_RUNSTDBY   (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
-#define SERCOM_SPI_CTRLA_IBON       (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
-#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
-#define SERCOM_SPI_CTRLA_DOPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
-#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
-#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
-#define SERCOM_SPI_CTRLA_DIPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
-#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
-#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
-#define SERCOM_SPI_CTRLA_FORM_Msk   (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
-#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
-#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
-#define SERCOM_SPI_CTRLA_CPHA       (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
-#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
-#define SERCOM_SPI_CTRLA_CPOL       (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
-#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
-#define SERCOM_SPI_CTRLA_DORD       (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
-#define SERCOM_SPI_CTRLA_MASK       0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
-
-/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
-    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
-    uint32_t :4;               /*!< bit:  9..12  Reserved                           */
-    uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
-    uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
-    uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
-    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
-    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
-    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
-    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
-#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
-
-#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
-#define SERCOM_USART_CTRLA_SWRST    (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
-#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
-#define SERCOM_USART_CTRLA_ENABLE   (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
-#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
-#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
-#define   SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
-#define   SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
-#define   SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
-#define   SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
-#define   SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
-#define   SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
-#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
-#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
-#define SERCOM_USART_CTRLA_IBON     (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
-#define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
-#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
-#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
-#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
-#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
-#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
-#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
-#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
-#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
-#define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
-#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
-#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
-#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
-#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
-#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
-#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
-#define SERCOM_USART_CTRLA_CMODE    (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
-#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
-#define SERCOM_USART_CTRLA_CPOL     (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
-#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
-#define SERCOM_USART_CTRLA_DORD     (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
-#define SERCOM_USART_CTRLA_MASK     0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
-
-/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
-    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
-    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
-#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
-
-#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
-#define SERCOM_I2CM_CTRLB_SMEN      (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
-#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
-#define SERCOM_I2CM_CTRLB_QCEN      (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
-#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
-#define SERCOM_I2CM_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
-#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
-#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
-#define SERCOM_I2CM_CTRLB_ACKACT    (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
-#define SERCOM_I2CM_CTRLB_MASK      0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
-    uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
-    uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
-    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
-    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
-    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
-    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
-#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
-
-#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
-#define SERCOM_I2CS_CTRLB_SMEN      (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
-#define SERCOM_I2CS_CTRLB_GCMD_Pos  9            /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
-#define SERCOM_I2CS_CTRLB_GCMD      (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
-#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10           /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
-#define SERCOM_I2CS_CTRLB_AACKEN    (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
-#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
-#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
-#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
-#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
-#define SERCOM_I2CS_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
-#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
-#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
-#define SERCOM_I2CS_CTRLB_ACKACT    (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
-#define SERCOM_I2CS_CTRLB_MASK      0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
-    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
-    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
-    uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
-    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
-    uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
-    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
-    uint32_t :1;               /*!< bit:     16  Reserved                           */
-    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
-    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
-#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
-
-#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
-#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
-#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
-#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
-#define SERCOM_SPI_CTRLB_PLOADEN    (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
-#define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
-#define SERCOM_SPI_CTRLB_SSDE       (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
-#define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
-#define SERCOM_SPI_CTRLB_MSSEN      (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
-#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
-#define SERCOM_SPI_CTRLB_AMODE_Msk  (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
-#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
-#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
-#define SERCOM_SPI_CTRLB_RXEN       (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
-#define SERCOM_SPI_CTRLB_MASK       0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
-
-/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
-    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
-    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
-    uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
-    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
-    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
-    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
-    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
-    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
-    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
-#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
-
-#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
-#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
-#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
-#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
-#define SERCOM_USART_CTRLB_SBMODE   (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
-#define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
-#define SERCOM_USART_CTRLB_COLDEN   (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
-#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
-#define SERCOM_USART_CTRLB_SFDE     (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
-#define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
-#define SERCOM_USART_CTRLB_ENC      (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
-#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
-#define SERCOM_USART_CTRLB_PMODE    (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
-#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
-#define SERCOM_USART_CTRLB_TXEN     (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
-#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
-#define SERCOM_USART_CTRLB_RXEN     (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
-#define SERCOM_USART_CTRLB_MASK     0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
-
-/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
-    uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
-    uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
-    uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_BAUD_OFFSET     0x0C         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
-#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
-
-#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
-#define SERCOM_I2CM_BAUD_BAUD_Msk   (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
-#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
-#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
-#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
-#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
-#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
-#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
-#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
-#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
-#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
-#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
-#define SERCOM_I2CM_BAUD_MASK       0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
-
-/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
-#define SERCOM_SPI_BAUD_RESETVALUE  0x00ul       /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
-
-#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
-#define SERCOM_SPI_BAUD_BAUD_Msk    (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
-#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
-#define SERCOM_SPI_BAUD_MASK        0xFFul       /**< \brief (SERCOM_SPI_BAUD) MASK Register */
-
-/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // FRAC mode
-    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
-    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
-  } FRAC;                      /*!< Structure used for FRAC                         */
-  struct { // FRACFP mode
-    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
-    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
-  } FRACFP;                    /*!< Structure used for FRACFP                       */
-  struct { // USARTFP mode
-    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
-  } USARTFP;                   /*!< Structure used for USARTFP                      */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
-#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
-
-#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
-#define SERCOM_USART_BAUD_BAUD_Msk  (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
-#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
-#define SERCOM_USART_BAUD_MASK      0xFFFFul     /**< \brief (SERCOM_USART_BAUD) MASK Register */
-
-// FRAC mode
-#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
-#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
-#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
-#define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
-#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
-#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
-#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
-
-// FRACFP mode
-#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
-#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
-#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
-#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
-#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
-#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
-#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
-
-// USARTFP mode
-#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
-#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
-#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
-#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
-
-/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_RXPL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
-#define SERCOM_USART_RXPL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
-
-#define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
-#define SERCOM_USART_RXPL_RXPL_Msk  (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
-#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
-#define SERCOM_USART_RXPL_MASK      0xFFul       /**< \brief (SERCOM_USART_RXPL) MASK Register */
-
-/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
-    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
-    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
-#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
-
-#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_MB     (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
-#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_SB     (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
-#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_ERROR  (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
-#define SERCOM_I2CM_INTENCLR_MASK   0x83ul       /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
-
-/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
-    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
-    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
-#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
-
-#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_PREC   (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
-#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
-#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_DRDY   (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
-#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_ERROR  (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
-#define SERCOM_I2CS_INTENCLR_MASK   0x87ul       /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
-
-/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
-    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
-#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
-
-#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_DRE     (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
-#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_TXC     (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
-#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_RXC     (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
-#define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_SSL     (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
-#define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_ERROR   (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
-#define SERCOM_SPI_INTENCLR_MASK    0x8Ful       /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
-
-/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
-    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
-    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
-    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
-    uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
-#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
-
-#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
-#define SERCOM_USART_INTENCLR_DRE   (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
-#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
-#define SERCOM_USART_INTENCLR_TXC   (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
-#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXC   (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
-#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXS   (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
-#define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
-#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
-#define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
-#define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
-#define SERCOM_USART_INTENCLR_MASK  0xBFul       /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
-
-/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
-    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
-    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
-#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
-
-#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_MB     (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
-#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_SB     (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
-#define SERCOM_I2CM_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_ERROR  (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
-#define SERCOM_I2CM_INTENSET_MASK   0x83ul       /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
-
-/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
-    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
-    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
-#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
-
-#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_PREC   (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
-#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
-#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_DRDY   (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
-#define SERCOM_I2CS_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_ERROR  (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
-#define SERCOM_I2CS_INTENSET_MASK   0x87ul       /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
-
-/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
-    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
-#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
-
-#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
-#define SERCOM_SPI_INTENSET_DRE     (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
-#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
-#define SERCOM_SPI_INTENSET_TXC     (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
-#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
-#define SERCOM_SPI_INTENSET_RXC     (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
-#define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
-#define SERCOM_SPI_INTENSET_SSL     (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
-#define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_SPI_INTENSET_ERROR   (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
-#define SERCOM_SPI_INTENSET_MASK    0x8Ful       /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
-
-/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
-    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
-    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
-    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
-    uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
-#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
-
-#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
-#define SERCOM_USART_INTENSET_DRE   (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
-#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
-#define SERCOM_USART_INTENSET_TXC   (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
-#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXC   (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
-#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXS   (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
-#define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
-#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
-#define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
-#define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
-#define SERCOM_USART_INTENSET_MASK  0xBFul       /**< \brief (SERCOM_USART_INTENSET) MASK Register */
-
-/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
-    __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
-    __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
-#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
-
-#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
-#define SERCOM_I2CM_INTFLAG_MB      (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
-#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
-#define SERCOM_I2CM_INTFLAG_SB      (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
-#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
-#define SERCOM_I2CM_INTFLAG_ERROR   (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
-#define SERCOM_I2CM_INTFLAG_MASK    0x83ul       /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
-
-/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
-    __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
-    __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
-    __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
-#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
-
-#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
-#define SERCOM_I2CS_INTFLAG_PREC    (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
-#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
-#define SERCOM_I2CS_INTFLAG_AMATCH  (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
-#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
-#define SERCOM_I2CS_INTFLAG_DRDY    (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
-#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
-#define SERCOM_I2CS_INTFLAG_ERROR   (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
-#define SERCOM_I2CS_INTFLAG_MASK    0x87ul       /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
-
-/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
-    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
-    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
-    __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
-    __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
-#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
-
-#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
-#define SERCOM_SPI_INTFLAG_DRE      (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
-#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
-#define SERCOM_SPI_INTFLAG_TXC      (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
-#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
-#define SERCOM_SPI_INTFLAG_RXC      (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
-#define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
-#define SERCOM_SPI_INTFLAG_SSL      (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
-#define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
-#define SERCOM_SPI_INTFLAG_ERROR    (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
-#define SERCOM_SPI_INTFLAG_MASK     0x8Ful       /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
-
-/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
-    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
-    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
-    __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
-    __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
-    __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
-    __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
-#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
-
-#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
-#define SERCOM_USART_INTFLAG_DRE    (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
-#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
-#define SERCOM_USART_INTFLAG_TXC    (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
-#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
-#define SERCOM_USART_INTFLAG_RXC    (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
-#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
-#define SERCOM_USART_INTFLAG_RXS    (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
-#define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
-#define SERCOM_USART_INTFLAG_CTSIC  (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
-#define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
-#define SERCOM_USART_INTFLAG_RXBRK  (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
-#define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
-#define SERCOM_USART_INTFLAG_ERROR  (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
-#define SERCOM_USART_INTFLAG_MASK   0xBFul       /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
-
-/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
-    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
-    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
-    uint16_t :1;               /*!< bit:      3  Reserved                           */
-    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
-    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
-    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
-    uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
-    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
-    uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
-#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
-
-#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
-#define SERCOM_I2CM_STATUS_BUSERR   (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
-#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
-#define SERCOM_I2CM_STATUS_ARBLOST  (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
-#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
-#define SERCOM_I2CM_STATUS_RXNACK   (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
-#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
-#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
-#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
-#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
-#define SERCOM_I2CM_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
-#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
-#define SERCOM_I2CM_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
-#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8            /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
-#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
-#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
-#define SERCOM_I2CM_STATUS_LENERR_Pos 10           /**< \brief (SERCOM_I2CM_STATUS) Length Error */
-#define SERCOM_I2CM_STATUS_LENERR   (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
-#define SERCOM_I2CM_STATUS_MASK     0x07F7ul     /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
-
-/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
-    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
-    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
-    uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
-    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
-    uint16_t :1;               /*!< bit:      5  Reserved                           */
-    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
-    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
-    uint16_t :1;               /*!< bit:      8  Reserved                           */
-    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
-    uint16_t HS:1;             /*!< bit:     10  High Speed                         */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
-#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
-
-#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
-#define SERCOM_I2CS_STATUS_BUSERR   (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
-#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
-#define SERCOM_I2CS_STATUS_COLL     (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
-#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
-#define SERCOM_I2CS_STATUS_RXNACK   (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
-#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
-#define SERCOM_I2CS_STATUS_DIR      (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
-#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
-#define SERCOM_I2CS_STATUS_SR       (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
-#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
-#define SERCOM_I2CS_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
-#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
-#define SERCOM_I2CS_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
-#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
-#define SERCOM_I2CS_STATUS_HS_Pos   10           /**< \brief (SERCOM_I2CS_STATUS) High Speed */
-#define SERCOM_I2CS_STATUS_HS       (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
-#define SERCOM_I2CS_STATUS_MASK     0x06DFul     /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
-
-/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
-    uint16_t :13;              /*!< bit:  3..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
-#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
-
-#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
-#define SERCOM_SPI_STATUS_BUFOVF    (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
-#define SERCOM_SPI_STATUS_MASK      0x0004ul     /**< \brief (SERCOM_SPI_STATUS) MASK Register */
-
-/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
-    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
-    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
-    uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
-    uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
-    uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
-    uint16_t :10;              /*!< bit:  6..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
-#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
-
-#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
-#define SERCOM_USART_STATUS_PERR    (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
-#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
-#define SERCOM_USART_STATUS_FERR    (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
-#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
-#define SERCOM_USART_STATUS_BUFOVF  (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
-#define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
-#define SERCOM_USART_STATUS_CTS     (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
-#define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
-#define SERCOM_USART_STATUS_ISF     (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
-#define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
-#define SERCOM_USART_STATUS_COLL    (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
-#define SERCOM_USART_STATUS_MASK    0x003Ful     /**< \brief (SERCOM_USART_STATUS) MASK Register */
-
-/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CM I2CM Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
-
-#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_SWRST  (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
-#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2            /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_SYSOP  (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
-#define SERCOM_I2CM_SYNCBUSY_MASK   0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CS I2CS Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
-
-#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_SWRST  (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
-#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_I2CS_SYNCBUSY_MASK   0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
-
-#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_SWRST   (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
-#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_ENABLE  (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_CTRLB   (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
-#define SERCOM_SPI_SYNCBUSY_MASK    0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
-
-#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
-#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
-#define SERCOM_USART_SYNCBUSY_MASK  0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
-    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
-    uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
-    uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
-    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
-    uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
-#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
-
-#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address Value */
-#define SERCOM_I2CM_ADDR_ADDR_Msk   (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
-#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
-#define SERCOM_I2CM_ADDR_LENEN_Pos  13           /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
-#define SERCOM_I2CM_ADDR_LENEN      (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
-#define SERCOM_I2CM_ADDR_HS_Pos     14           /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
-#define SERCOM_I2CM_ADDR_HS         (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
-#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
-#define SERCOM_I2CM_ADDR_TENBITEN   (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
-#define SERCOM_I2CM_ADDR_LEN_Pos    16           /**< \brief (SERCOM_I2CM_ADDR) Length */
-#define SERCOM_I2CM_ADDR_LEN_Msk    (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
-#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
-#define SERCOM_I2CM_ADDR_MASK       0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
-
-/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
-    uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
-    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
-    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
-    uint32_t :1;               /*!< bit:     16  Reserved                           */
-    uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
-#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
-
-#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
-#define SERCOM_I2CS_ADDR_GENCEN     (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
-#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address Value */
-#define SERCOM_I2CS_ADDR_ADDR_Msk   (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
-#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
-#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
-#define SERCOM_I2CS_ADDR_TENBITEN   (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
-#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
-#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
-#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
-#define SERCOM_I2CS_ADDR_MASK       0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
-
-/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
-#define SERCOM_SPI_ADDR_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
-
-#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
-#define SERCOM_SPI_ADDR_ADDR_Msk    (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
-#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
-#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
-#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
-#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
-#define SERCOM_SPI_ADDR_MASK        0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
-
-/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CM I2CM Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
-#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
-
-#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data Value */
-#define SERCOM_I2CM_DATA_DATA_Msk   (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
-#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
-#define SERCOM_I2CM_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CM_DATA) MASK Register */
-
-/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CS I2CS Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
-#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
-
-#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data Value */
-#define SERCOM_I2CS_DATA_DATA_Msk   (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
-#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
-#define SERCOM_I2CS_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CS_DATA) MASK Register */
-
-/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
-    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
-#define SERCOM_SPI_DATA_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
-
-#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
-#define SERCOM_SPI_DATA_DATA_Msk    (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
-#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
-#define SERCOM_SPI_DATA_MASK        0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
-
-/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
-#define SERCOM_USART_DATA_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
-
-#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
-#define SERCOM_USART_DATA_DATA_Msk  (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
-#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
-#define SERCOM_USART_DATA_MASK      0x01FFul     /**< \brief (SERCOM_USART_DATA) MASK Register */
-
-/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) I2CM I2CM Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_DBGCTRL_OFFSET  0x30         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
-#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
-
-#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
-#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_I2CM_DBGCTRL_MASK    0x01ul       /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
-
-/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
-#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
-
-#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
-#define SERCOM_SPI_DBGCTRL_DBGSTOP  (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_SPI_DBGCTRL_MASK     0x01ul       /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
-
-/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
-#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
-
-#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
-#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_USART_DBGCTRL_MASK   0x01ul       /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
-
-/** \brief SERCOM_I2CM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* I2C Master Mode */
-  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
-  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
-       RoReg8                    Reserved1[0x4];
-  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
-       RoReg8                    Reserved2[0x4];
-  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
-       RoReg8                    Reserved5[0x1];
-  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
-  __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Synchronization Busy */
-       RoReg8                    Reserved6[0x4];
-  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
-  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CM Data */
-       RoReg8                    Reserved7[0x7];
-  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
-} SercomI2cm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_I2CS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* I2C Slave Mode */
-  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
-  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
-       RoReg8                    Reserved1[0xC];
-  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x1];
-  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
-  __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Synchronization Busy */
-       RoReg8                    Reserved5[0x4];
-  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
-  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CS Data */
-} SercomI2cs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_SPI hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* SPI Mode */
-  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
-  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
-       RoReg8                    Reserved1[0x4];
-  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
-       RoReg8                    Reserved2[0x7];
-  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
-       RoReg8                    Reserved5[0x1];
-  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
-  __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Synchronization Busy */
-       RoReg8                    Reserved6[0x4];
-  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
-  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
-       RoReg8                    Reserved7[0x4];
-  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
-} SercomSpi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_USART hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USART Mode */
-  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
-  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
-       RoReg8                    Reserved1[0x4];
-  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
-  __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
-       RoReg8                    Reserved2[0x5];
-  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
-       RoReg8                    Reserved5[0x1];
-  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
-  __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Synchronization Busy */
-       RoReg8                    Reserved6[0x8];
-  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 16) USART Data */
-       RoReg8                    Reserved7[0x6];
-  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
-} SercomUsart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
-       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
-       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
-       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
-} Sercom;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_SERCOM_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM_COMPONENT_
+#define _SAMD21_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM                  0x220
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST     (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE    (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT    (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22           /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN  (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN  (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM     (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK      0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST     (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE    (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk  (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY  (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT    (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN  (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM     (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK      0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST      (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE     (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk   (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define   SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY   (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON       (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk   (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk   (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA       (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL       (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD       (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK       0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :4;               /*!< bit:  9..12  Reserved                           */
+    uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
+    uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
+    uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST    (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE   (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define   SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul  /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul  /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul  /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON     (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE    (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL     (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD     (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK     0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN      (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN      (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT    (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK      0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
+    uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
+    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN      (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos  9            /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD      (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10           /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN    (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk   (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT    (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK      0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
+    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
+    uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
+    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
+    uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN    (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE       (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN      (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk  (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN       (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK       0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
+    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
+    uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE   (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN   (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE     (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC      (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE    (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN     (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN     (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK     0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+    uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
+    uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
+    uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET     0x0C         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk   (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK       0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE  0x00ul       /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk    (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK        0xFFul       /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // FRAC mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRAC;                      /*!< Structure used for FRAC                         */
+  struct { // FRACFP mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRACFP;                    /*!< Structure used for FRACFP                       */
+  struct { // USARTFP mode
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } USARTFP;                   /*!< Structure used for USARTFP                      */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk  (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK      0xFFFFul     /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk  (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK      0xFFul       /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB     (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB     (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR  (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK   0x83ul       /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC   (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY   (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR  (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK   0x87ul       /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE     (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC     (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC     (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL     (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR   (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK    0x8Ful       /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE   (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC   (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC   (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS   (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK  0xBFul       /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB     (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB     (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR  (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK   0x83ul       /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC   (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY   (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR  (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK   0x87ul       /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE     (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC     (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC     (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL     (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR   (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK    0x8Ful       /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE   (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC   (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC   (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS   (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK  0xBFul       /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
+    __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
+    __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB      (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB      (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR   (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK    0x83ul       /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
+    __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
+    __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
+    __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC    (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH  (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY    (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR   (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK    0x87ul       /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
+    __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE      (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC      (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC      (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL      (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR    (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK     0x8Ful       /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
+    __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
+    __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
+    __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE    (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC    (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC    (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS    (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC  (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK  (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR  (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK   0xBFul       /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR   (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST  (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK   (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8            /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10           /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR   (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK     0x07F7ul     /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
+    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t :1;               /*!< bit:      8  Reserved                           */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t HS:1;             /*!< bit:     10  High Speed                         */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR   (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL     (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK   (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR      (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR       (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT  (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD  (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos   10           /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS       (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_MASK     0x06DFul     /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t :13;              /*!< bit:  3..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF    (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_MASK      0x0004ul     /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
+    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
+    uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
+    uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
+    uint16_t :10;              /*!< bit:  6..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR    (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR    (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF  (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS     (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF     (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL    (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_MASK    0x003Ful     /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CM I2CM Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST  (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2            /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP  (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK   0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CS I2CS Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST  (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK   0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST   (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE  (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB   (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK    0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK  0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
+    uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk   (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos  13           /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN      (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos     14           /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS         (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN   (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos    16           /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk    (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK       0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
+    uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
+    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN     (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk   (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN   (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK       0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk    (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK        0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk   (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk   (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK       0xFFul       /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
+    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE  0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk    (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK        0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE 0x0000ul     /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk  (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK      0x01FFul     /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET  0x30         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK    0x01ul       /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP  (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK     0x01ul       /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul       /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK   0x01ul       /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+       RoReg8                    Reserved2[0x4];
+  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+  __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Synchronization Busy */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CM Data */
+       RoReg8                    Reserved7[0x7];
+  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+       RoReg8                    Reserved1[0xC];
+  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+  __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Synchronization Busy */
+       RoReg8                    Reserved5[0x4];
+  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
+       RoReg8                    Reserved2[0x7];
+  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+  __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Synchronization Busy */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+       RoReg8                    Reserved7[0x4];
+  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+  __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
+       RoReg8                    Reserved2[0x5];
+  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
+  __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Synchronization Busy */
+       RoReg8                    Reserved6[0x8];
+  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 16) USART Data */
+       RoReg8                    Reserved7[0x6];
+  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
+       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
+       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
+       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h
index 18bfe0f..9895541 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h
@@ -1,938 +1,938 @@
-/**
- * \file
- *
- * \brief Component description for SYSCTRL
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SYSCTRL_COMPONENT_
-#define _SAMD21_SYSCTRL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR SYSCTRL */
-/* ========================================================================== */
-/** \addtogroup SAMD21_SYSCTRL System Control */
-/*@{*/
-
-#define SYSCTRL_U2100
-#define REV_SYSCTRL                 0x201
-
-/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
-    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
-    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
-    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
-    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
-    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
-    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
-    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
-    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
-    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
-    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
-    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
-    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
-    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
-    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
-    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
-    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_INTENCLR_OFFSET     0x00         /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_XOSCRDY    (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
-#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
-#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_OSC32KRDY  (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
-#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_OSC8MRDY   (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
-#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_DFLLRDY    (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
-#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
-#define SYSCTRL_INTENCLR_DFLLOOB    (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
-#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
-#define SYSCTRL_INTENCLR_DFLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
-#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
-#define SYSCTRL_INTENCLR_DFLLLCKC   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
-#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
-#define SYSCTRL_INTENCLR_DFLLRCS    (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
-#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_BOD33RDY   (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
-#define SYSCTRL_INTENCLR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
-#define SYSCTRL_INTENCLR_BOD33DET   (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
-#define SYSCTRL_INTENCLR_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
-#define SYSCTRL_INTENCLR_B33SRDY    (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
-#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
-#define SYSCTRL_INTENCLR_DPLLLCKR   (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
-#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
-#define SYSCTRL_INTENCLR_DPLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
-#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
-#define SYSCTRL_INTENCLR_DPLLLTO    (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
-#define SYSCTRL_INTENCLR_MASK       0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
-
-/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
-    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
-    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
-    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
-    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
-    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
-    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
-    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
-    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
-    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
-    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
-    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
-    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
-    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
-    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
-    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
-    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_INTENSET_OFFSET     0x04         /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
-#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define SYSCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_XOSCRDY    (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
-#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
-#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_OSC32KRDY  (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
-#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_OSC8MRDY   (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
-#define SYSCTRL_INTENSET_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_DFLLRDY    (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
-#define SYSCTRL_INTENSET_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
-#define SYSCTRL_INTENSET_DFLLOOB    (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
-#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
-#define SYSCTRL_INTENSET_DFLLLCKF   (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
-#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
-#define SYSCTRL_INTENSET_DFLLLCKC   (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
-#define SYSCTRL_INTENSET_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
-#define SYSCTRL_INTENSET_DFLLRCS    (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
-#define SYSCTRL_INTENSET_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_BOD33RDY   (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
-#define SYSCTRL_INTENSET_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
-#define SYSCTRL_INTENSET_BOD33DET   (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
-#define SYSCTRL_INTENSET_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
-#define SYSCTRL_INTENSET_B33SRDY    (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
-#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
-#define SYSCTRL_INTENSET_DPLLLCKR   (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
-#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
-#define SYSCTRL_INTENSET_DPLLLCKF   (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
-#define SYSCTRL_INTENSET_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
-#define SYSCTRL_INTENSET_DPLLLTO    (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
-#define SYSCTRL_INTENSET_MASK       0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
-
-/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
-    __I uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
-    __I uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
-    __I uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
-    __I uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
-    __I uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
-    __I uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
-    __I uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
-    __I uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
-    __I uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
-    __I uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
-    __I uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
-    __I uint32_t :3;               /*!< bit: 12..14  Reserved                           */
-    __I uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
-    __I uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
-    __I uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
-    __I uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_INTFLAG_OFFSET      0x08         /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define SYSCTRL_INTFLAG_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
-#define SYSCTRL_INTFLAG_XOSCRDY     (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
-#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
-#define SYSCTRL_INTFLAG_XOSC32KRDY  (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
-#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
-#define SYSCTRL_INTFLAG_OSC32KRDY   (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
-#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
-#define SYSCTRL_INTFLAG_OSC8MRDY    (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
-#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
-#define SYSCTRL_INTFLAG_DFLLRDY     (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
-#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
-#define SYSCTRL_INTFLAG_DFLLOOB     (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
-#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
-#define SYSCTRL_INTFLAG_DFLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
-#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
-#define SYSCTRL_INTFLAG_DFLLLCKC    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
-#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
-#define SYSCTRL_INTFLAG_DFLLRCS     (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
-#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
-#define SYSCTRL_INTFLAG_BOD33RDY    (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
-#define SYSCTRL_INTFLAG_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
-#define SYSCTRL_INTFLAG_BOD33DET    (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
-#define SYSCTRL_INTFLAG_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
-#define SYSCTRL_INTFLAG_B33SRDY     (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
-#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
-#define SYSCTRL_INTFLAG_DPLLLCKR    (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
-#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
-#define SYSCTRL_INTFLAG_DPLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
-#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
-#define SYSCTRL_INTFLAG_DPLLLTO     (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
-#define SYSCTRL_INTFLAG_MASK        0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
-
-/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
-    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
-    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
-    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
-    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
-    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
-    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
-    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
-    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
-    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
-    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
-    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
-    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
-    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
-    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
-    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
-    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_PCLKSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_PCLKSR_OFFSET       0x0C         /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
-#define SYSCTRL_PCLKSR_RESETVALUE   0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
-
-#define SYSCTRL_PCLKSR_XOSCRDY_Pos  0            /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
-#define SYSCTRL_PCLKSR_XOSCRDY      (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
-#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
-#define SYSCTRL_PCLKSR_XOSC32KRDY   (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
-#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
-#define SYSCTRL_PCLKSR_OSC32KRDY    (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
-#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
-#define SYSCTRL_PCLKSR_OSC8MRDY     (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
-#define SYSCTRL_PCLKSR_DFLLRDY_Pos  4            /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
-#define SYSCTRL_PCLKSR_DFLLRDY      (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
-#define SYSCTRL_PCLKSR_DFLLOOB_Pos  5            /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
-#define SYSCTRL_PCLKSR_DFLLOOB      (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
-#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
-#define SYSCTRL_PCLKSR_DFLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
-#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
-#define SYSCTRL_PCLKSR_DFLLLCKC     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
-#define SYSCTRL_PCLKSR_DFLLRCS_Pos  8            /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
-#define SYSCTRL_PCLKSR_DFLLRCS      (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
-#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
-#define SYSCTRL_PCLKSR_BOD33RDY     (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
-#define SYSCTRL_PCLKSR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
-#define SYSCTRL_PCLKSR_BOD33DET     (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
-#define SYSCTRL_PCLKSR_B33SRDY_Pos  11           /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
-#define SYSCTRL_PCLKSR_B33SRDY      (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
-#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
-#define SYSCTRL_PCLKSR_DPLLLCKR     (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
-#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
-#define SYSCTRL_PCLKSR_DPLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
-#define SYSCTRL_PCLKSR_DPLLLTO_Pos  17           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
-#define SYSCTRL_PCLKSR_DPLLLTO      (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
-#define SYSCTRL_PCLKSR_MASK         0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
-
-/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :1;               /*!< bit:      0  Reserved                           */
-    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
-    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
-    uint16_t :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint16_t GAIN:3;           /*!< bit:  8..10  Oscillator Gain                    */
-    uint16_t AMPGC:1;          /*!< bit:     11  Automatic Amplitude Gain Control   */
-    uint16_t STARTUP:4;        /*!< bit: 12..15  Start-Up Time                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_XOSC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_XOSC_OFFSET         0x10         /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
-#define SYSCTRL_XOSC_RESETVALUE     0x0080ul     /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
-
-#define SYSCTRL_XOSC_ENABLE_Pos     1            /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
-#define SYSCTRL_XOSC_ENABLE         (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
-#define SYSCTRL_XOSC_XTALEN_Pos     2            /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
-#define SYSCTRL_XOSC_XTALEN         (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
-#define SYSCTRL_XOSC_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_XOSC) Run in Standby */
-#define SYSCTRL_XOSC_RUNSTDBY       (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
-#define SYSCTRL_XOSC_ONDEMAND_Pos   7            /**< \brief (SYSCTRL_XOSC) On Demand Control */
-#define SYSCTRL_XOSC_ONDEMAND       (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
-#define SYSCTRL_XOSC_GAIN_Pos       8            /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
-#define SYSCTRL_XOSC_GAIN_Msk       (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
-#define SYSCTRL_XOSC_GAIN(value)    (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
-#define   SYSCTRL_XOSC_GAIN_0_Val         0x0ul  /**< \brief (SYSCTRL_XOSC) 2MHz */
-#define   SYSCTRL_XOSC_GAIN_1_Val         0x1ul  /**< \brief (SYSCTRL_XOSC) 4MHz */
-#define   SYSCTRL_XOSC_GAIN_2_Val         0x2ul  /**< \brief (SYSCTRL_XOSC) 8MHz */
-#define   SYSCTRL_XOSC_GAIN_3_Val         0x3ul  /**< \brief (SYSCTRL_XOSC) 16MHz */
-#define   SYSCTRL_XOSC_GAIN_4_Val         0x4ul  /**< \brief (SYSCTRL_XOSC) 30MHz */
-#define SYSCTRL_XOSC_GAIN_0         (SYSCTRL_XOSC_GAIN_0_Val       << SYSCTRL_XOSC_GAIN_Pos)
-#define SYSCTRL_XOSC_GAIN_1         (SYSCTRL_XOSC_GAIN_1_Val       << SYSCTRL_XOSC_GAIN_Pos)
-#define SYSCTRL_XOSC_GAIN_2         (SYSCTRL_XOSC_GAIN_2_Val       << SYSCTRL_XOSC_GAIN_Pos)
-#define SYSCTRL_XOSC_GAIN_3         (SYSCTRL_XOSC_GAIN_3_Val       << SYSCTRL_XOSC_GAIN_Pos)
-#define SYSCTRL_XOSC_GAIN_4         (SYSCTRL_XOSC_GAIN_4_Val       << SYSCTRL_XOSC_GAIN_Pos)
-#define SYSCTRL_XOSC_AMPGC_Pos      11           /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
-#define SYSCTRL_XOSC_AMPGC          (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
-#define SYSCTRL_XOSC_STARTUP_Pos    12           /**< \brief (SYSCTRL_XOSC) Start-Up Time */
-#define SYSCTRL_XOSC_STARTUP_Msk    (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
-#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
-#define SYSCTRL_XOSC_MASK           0xFFC6ul     /**< \brief (SYSCTRL_XOSC) MASK Register */
-
-/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :1;               /*!< bit:      0  Reserved                           */
-    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
-    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
-    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
-    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
-    uint16_t AAMPEN:1;         /*!< bit:      5  Automatic Amplitude Control Enable */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint16_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_XOSC32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_XOSC32K_OFFSET      0x14         /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define SYSCTRL_XOSC32K_RESETVALUE  0x0080ul     /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
-
-#define SYSCTRL_XOSC32K_ENABLE_Pos  1            /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
-#define SYSCTRL_XOSC32K_ENABLE      (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
-#define SYSCTRL_XOSC32K_XTALEN_Pos  2            /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
-#define SYSCTRL_XOSC32K_XTALEN      (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
-#define SYSCTRL_XOSC32K_EN32K_Pos   3            /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
-#define SYSCTRL_XOSC32K_EN32K       (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
-#define SYSCTRL_XOSC32K_EN1K_Pos    4            /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
-#define SYSCTRL_XOSC32K_EN1K        (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
-#define SYSCTRL_XOSC32K_AAMPEN_Pos  5            /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
-#define SYSCTRL_XOSC32K_AAMPEN      (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
-#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
-#define SYSCTRL_XOSC32K_RUNSTDBY    (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
-#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
-#define SYSCTRL_XOSC32K_ONDEMAND    (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
-#define SYSCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
-#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
-#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
-#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (SYSCTRL_XOSC32K) Write Lock */
-#define SYSCTRL_XOSC32K_WRTLOCK     (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
-#define SYSCTRL_XOSC32K_MASK        0x17FEul     /**< \brief (SYSCTRL_XOSC32K) MASK Register */
-
-/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
-    uint32_t EN32K:1;          /*!< bit:      2  32kHz Output Enable                */
-    uint32_t EN1K:1;           /*!< bit:      3  1kHz Output Enable                 */
-    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint32_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t CALIB:7;          /*!< bit: 16..22  Oscillator Calibration             */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_OSC32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_OSC32K_OFFSET       0x18         /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
-#define SYSCTRL_OSC32K_RESETVALUE   0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
-
-#define SYSCTRL_OSC32K_ENABLE_Pos   1            /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
-#define SYSCTRL_OSC32K_ENABLE       (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
-#define SYSCTRL_OSC32K_EN32K_Pos    2            /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
-#define SYSCTRL_OSC32K_EN32K        (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
-#define SYSCTRL_OSC32K_EN1K_Pos     3            /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
-#define SYSCTRL_OSC32K_EN1K         (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
-#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_OSC32K) Run in Standby */
-#define SYSCTRL_OSC32K_RUNSTDBY     (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
-#define SYSCTRL_OSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_OSC32K) On Demand Control */
-#define SYSCTRL_OSC32K_ONDEMAND     (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
-#define SYSCTRL_OSC32K_STARTUP_Pos  8            /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
-#define SYSCTRL_OSC32K_STARTUP_Msk  (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
-#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
-#define SYSCTRL_OSC32K_WRTLOCK_Pos  12           /**< \brief (SYSCTRL_OSC32K) Write Lock */
-#define SYSCTRL_OSC32K_WRTLOCK      (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
-#define SYSCTRL_OSC32K_CALIB_Pos    16           /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
-#define SYSCTRL_OSC32K_CALIB_Msk    (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
-#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
-#define SYSCTRL_OSC32K_MASK         0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
-
-/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CALIB:5;          /*!< bit:  0.. 4  Oscillator Calibration             */
-    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint8_t  WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SYSCTRL_OSCULP32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_OSCULP32K_OFFSET    0x1C         /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful       /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-
-#define SYSCTRL_OSCULP32K_CALIB_Pos 0            /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
-#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
-#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
-#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7            /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
-#define SYSCTRL_OSCULP32K_WRTLOCK   (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
-#define SYSCTRL_OSCULP32K_MASK      0x9Ful       /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
-
-/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
-    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint32_t PRESC:2;          /*!< bit:  8.. 9  Oscillator Prescaler               */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t CALIB:12;         /*!< bit: 16..27  Oscillator Calibration             */
-    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
-    uint32_t FRANGE:2;         /*!< bit: 30..31  Oscillator Frequency Range         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_OSC8M_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_OSC8M_OFFSET        0x20         /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
-#define SYSCTRL_OSC8M_RESETVALUE    0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
-
-#define SYSCTRL_OSC8M_ENABLE_Pos    1            /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
-#define SYSCTRL_OSC8M_ENABLE        (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
-#define SYSCTRL_OSC8M_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_OSC8M) Run in Standby */
-#define SYSCTRL_OSC8M_RUNSTDBY      (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
-#define SYSCTRL_OSC8M_ONDEMAND_Pos  7            /**< \brief (SYSCTRL_OSC8M) On Demand Control */
-#define SYSCTRL_OSC8M_ONDEMAND      (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
-#define SYSCTRL_OSC8M_PRESC_Pos     8            /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
-#define SYSCTRL_OSC8M_PRESC_Msk     (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
-#define SYSCTRL_OSC8M_PRESC(value)  (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
-#define   SYSCTRL_OSC8M_PRESC_0_Val       0x0ul  /**< \brief (SYSCTRL_OSC8M) 1 */
-#define   SYSCTRL_OSC8M_PRESC_1_Val       0x1ul  /**< \brief (SYSCTRL_OSC8M) 2 */
-#define   SYSCTRL_OSC8M_PRESC_2_Val       0x2ul  /**< \brief (SYSCTRL_OSC8M) 4 */
-#define   SYSCTRL_OSC8M_PRESC_3_Val       0x3ul  /**< \brief (SYSCTRL_OSC8M) 8 */
-#define SYSCTRL_OSC8M_PRESC_0       (SYSCTRL_OSC8M_PRESC_0_Val     << SYSCTRL_OSC8M_PRESC_Pos)
-#define SYSCTRL_OSC8M_PRESC_1       (SYSCTRL_OSC8M_PRESC_1_Val     << SYSCTRL_OSC8M_PRESC_Pos)
-#define SYSCTRL_OSC8M_PRESC_2       (SYSCTRL_OSC8M_PRESC_2_Val     << SYSCTRL_OSC8M_PRESC_Pos)
-#define SYSCTRL_OSC8M_PRESC_3       (SYSCTRL_OSC8M_PRESC_3_Val     << SYSCTRL_OSC8M_PRESC_Pos)
-#define SYSCTRL_OSC8M_CALIB_Pos     16           /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
-#define SYSCTRL_OSC8M_CALIB_Msk     (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
-#define SYSCTRL_OSC8M_CALIB(value)  (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
-#define SYSCTRL_OSC8M_FRANGE_Pos    30           /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
-#define SYSCTRL_OSC8M_FRANGE_Msk    (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
-#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
-#define   SYSCTRL_OSC8M_FRANGE_0_Val      0x0ul  /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
-#define   SYSCTRL_OSC8M_FRANGE_1_Val      0x1ul  /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
-#define   SYSCTRL_OSC8M_FRANGE_2_Val      0x2ul  /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
-#define   SYSCTRL_OSC8M_FRANGE_3_Val      0x3ul  /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
-#define SYSCTRL_OSC8M_FRANGE_0      (SYSCTRL_OSC8M_FRANGE_0_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
-#define SYSCTRL_OSC8M_FRANGE_1      (SYSCTRL_OSC8M_FRANGE_1_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
-#define SYSCTRL_OSC8M_FRANGE_2      (SYSCTRL_OSC8M_FRANGE_2_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
-#define SYSCTRL_OSC8M_FRANGE_3      (SYSCTRL_OSC8M_FRANGE_3_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
-#define SYSCTRL_OSC8M_MASK          0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
-
-/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :1;               /*!< bit:      0  Reserved                           */
-    uint16_t ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
-    uint16_t MODE:1;           /*!< bit:      2  Operating Mode Selection           */
-    uint16_t STABLE:1;         /*!< bit:      3  Stable DFLL Frequency              */
-    uint16_t LLAW:1;           /*!< bit:      4  Lose Lock After Wake               */
-    uint16_t USBCRM:1;         /*!< bit:      5  USB Clock Recovery Mode            */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint16_t CCDIS:1;          /*!< bit:      8  Chill Cycle Disable                */
-    uint16_t QLDIS:1;          /*!< bit:      9  Quick Lock Disable                 */
-    uint16_t BPLCKC:1;         /*!< bit:     10  Bypass Coarse Lock                 */
-    uint16_t WAITLOCK:1;       /*!< bit:     11  Wait Lock                          */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_DFLLCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DFLLCTRL_OFFSET     0x24         /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
-#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul     /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
-
-#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1            /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
-#define SYSCTRL_DFLLCTRL_ENABLE     (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
-#define SYSCTRL_DFLLCTRL_MODE_Pos   2            /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
-#define SYSCTRL_DFLLCTRL_MODE       (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
-#define SYSCTRL_DFLLCTRL_STABLE_Pos 3            /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
-#define SYSCTRL_DFLLCTRL_STABLE     (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
-#define SYSCTRL_DFLLCTRL_LLAW_Pos   4            /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
-#define SYSCTRL_DFLLCTRL_LLAW       (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
-#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5            /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
-#define SYSCTRL_DFLLCTRL_USBCRM     (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
-#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
-#define SYSCTRL_DFLLCTRL_RUNSTDBY   (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
-#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
-#define SYSCTRL_DFLLCTRL_ONDEMAND   (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
-#define SYSCTRL_DFLLCTRL_CCDIS_Pos  8            /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
-#define SYSCTRL_DFLLCTRL_CCDIS      (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
-#define SYSCTRL_DFLLCTRL_QLDIS_Pos  9            /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
-#define SYSCTRL_DFLLCTRL_QLDIS      (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
-#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10           /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
-#define SYSCTRL_DFLLCTRL_BPLCKC     (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
-#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11           /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
-#define SYSCTRL_DFLLCTRL_WAITLOCK   (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
-#define SYSCTRL_DFLLCTRL_MASK       0x0FFEul     /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
-
-/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FINE:10;          /*!< bit:  0.. 9  Fine Value                         */
-    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
-    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_DFLLVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DFLLVAL_OFFSET      0x28         /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
-#define SYSCTRL_DFLLVAL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
-
-#define SYSCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
-#define SYSCTRL_DFLLVAL_FINE_Msk    (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
-#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
-#define SYSCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
-#define SYSCTRL_DFLLVAL_COARSE_Msk  (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
-#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
-#define SYSCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
-#define SYSCTRL_DFLLVAL_DIFF_Msk    (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
-#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
-#define SYSCTRL_DFLLVAL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
-
-/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
-    uint32_t FSTEP:10;         /*!< bit: 16..25  Fine Maximum Step                  */
-    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_DFLLMUL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DFLLMUL_OFFSET      0x2C         /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
-#define SYSCTRL_DFLLMUL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
-
-#define SYSCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
-#define SYSCTRL_DFLLMUL_MUL_Msk     (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
-#define SYSCTRL_DFLLMUL_MUL(value)  (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
-#define SYSCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
-#define SYSCTRL_DFLLMUL_FSTEP_Msk   (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
-#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
-#define SYSCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
-#define SYSCTRL_DFLLMUL_CSTEP_Msk   (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
-#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
-#define SYSCTRL_DFLLMUL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
-
-/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W  8) DFLL48M Synchronization -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  READREQ:1;        /*!< bit:      7  Read Request                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SYSCTRL_DFLLSYNC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DFLLSYNC_OFFSET     0x30         /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
-#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
-
-#define SYSCTRL_DFLLSYNC_READREQ_Pos 7            /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
-#define SYSCTRL_DFLLSYNC_READREQ    (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
-#define SYSCTRL_DFLLSYNC_MASK       0x80ul       /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
-
-/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t HYST:1;           /*!< bit:      2  Hysteresis                         */
-    uint32_t ACTION:2;         /*!< bit:  3.. 4  BOD33 Action                       */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t MODE:1;           /*!< bit:      8  Operation Mode                     */
-    uint32_t CEN:1;            /*!< bit:      9  Clock Enable                       */
-    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint32_t PSEL:4;           /*!< bit: 12..15  Prescaler Select                   */
-    uint32_t LEVEL:6;          /*!< bit: 16..21  BOD33 Threshold Level              */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_BOD33_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_BOD33_OFFSET        0x34         /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
-#define SYSCTRL_BOD33_RESETVALUE    0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
-
-#define SYSCTRL_BOD33_ENABLE_Pos    1            /**< \brief (SYSCTRL_BOD33) Enable */
-#define SYSCTRL_BOD33_ENABLE        (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
-#define SYSCTRL_BOD33_HYST_Pos      2            /**< \brief (SYSCTRL_BOD33) Hysteresis */
-#define SYSCTRL_BOD33_HYST          (0x1ul << SYSCTRL_BOD33_HYST_Pos)
-#define SYSCTRL_BOD33_ACTION_Pos    3            /**< \brief (SYSCTRL_BOD33) BOD33 Action */
-#define SYSCTRL_BOD33_ACTION_Msk    (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
-#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
-#define   SYSCTRL_BOD33_ACTION_NONE_Val   0x0ul  /**< \brief (SYSCTRL_BOD33) No action */
-#define   SYSCTRL_BOD33_ACTION_RESET_Val  0x1ul  /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
-#define   SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul  /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
-#define SYSCTRL_BOD33_ACTION_NONE   (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
-#define SYSCTRL_BOD33_ACTION_RESET  (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
-#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
-#define SYSCTRL_BOD33_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_BOD33) Run in Standby */
-#define SYSCTRL_BOD33_RUNSTDBY      (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
-#define SYSCTRL_BOD33_MODE_Pos      8            /**< \brief (SYSCTRL_BOD33) Operation Mode */
-#define SYSCTRL_BOD33_MODE          (0x1ul << SYSCTRL_BOD33_MODE_Pos)
-#define SYSCTRL_BOD33_CEN_Pos       9            /**< \brief (SYSCTRL_BOD33) Clock Enable */
-#define SYSCTRL_BOD33_CEN           (0x1ul << SYSCTRL_BOD33_CEN_Pos)
-#define SYSCTRL_BOD33_PSEL_Pos      12           /**< \brief (SYSCTRL_BOD33) Prescaler Select */
-#define SYSCTRL_BOD33_PSEL_Msk      (0xFul << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL(value)   (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
-#define   SYSCTRL_BOD33_PSEL_DIV2_Val     0x0ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
-#define   SYSCTRL_BOD33_PSEL_DIV4_Val     0x1ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
-#define   SYSCTRL_BOD33_PSEL_DIV8_Val     0x2ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
-#define   SYSCTRL_BOD33_PSEL_DIV16_Val    0x3ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
-#define   SYSCTRL_BOD33_PSEL_DIV32_Val    0x4ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
-#define   SYSCTRL_BOD33_PSEL_DIV64_Val    0x5ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
-#define   SYSCTRL_BOD33_PSEL_DIV128_Val   0x6ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
-#define   SYSCTRL_BOD33_PSEL_DIV256_Val   0x7ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
-#define   SYSCTRL_BOD33_PSEL_DIV512_Val   0x8ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
-#define   SYSCTRL_BOD33_PSEL_DIV1K_Val    0x9ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
-#define   SYSCTRL_BOD33_PSEL_DIV2K_Val    0xAul  /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
-#define   SYSCTRL_BOD33_PSEL_DIV4K_Val    0xBul  /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
-#define   SYSCTRL_BOD33_PSEL_DIV8K_Val    0xCul  /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
-#define   SYSCTRL_BOD33_PSEL_DIV16K_Val   0xDul  /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
-#define   SYSCTRL_BOD33_PSEL_DIV32K_Val   0xEul  /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
-#define   SYSCTRL_BOD33_PSEL_DIV64K_Val   0xFul  /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
-#define SYSCTRL_BOD33_PSEL_DIV2     (SYSCTRL_BOD33_PSEL_DIV2_Val   << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV4     (SYSCTRL_BOD33_PSEL_DIV4_Val   << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV8     (SYSCTRL_BOD33_PSEL_DIV8_Val   << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV16    (SYSCTRL_BOD33_PSEL_DIV16_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV32    (SYSCTRL_BOD33_PSEL_DIV32_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV64    (SYSCTRL_BOD33_PSEL_DIV64_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV128   (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV256   (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV512   (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV1K    (SYSCTRL_BOD33_PSEL_DIV1K_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV2K    (SYSCTRL_BOD33_PSEL_DIV2K_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV4K    (SYSCTRL_BOD33_PSEL_DIV4K_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV8K    (SYSCTRL_BOD33_PSEL_DIV8K_Val  << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV16K   (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV32K   (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_PSEL_DIV64K   (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
-#define SYSCTRL_BOD33_LEVEL_Pos     16           /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
-#define SYSCTRL_BOD33_LEVEL_Msk     (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
-#define SYSCTRL_BOD33_LEVEL(value)  (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
-#define SYSCTRL_BOD33_MASK          0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
-
-/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t :6;               /*!< bit:  7..12  Reserved                           */
-    uint16_t FORCELDO:1;       /*!< bit:     13  Force LDO Voltage Regulator        */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_VREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_VREG_OFFSET         0x3C         /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
-#define SYSCTRL_VREG_RESETVALUE     0x0000ul     /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
-
-#define SYSCTRL_VREG_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_VREG) Run in Standby */
-#define SYSCTRL_VREG_RUNSTDBY       (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
-#define SYSCTRL_VREG_FORCELDO_Pos   13           /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
-#define SYSCTRL_VREG_FORCELDO       (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
-#define SYSCTRL_VREG_MASK           0x2040ul     /**< \brief (SYSCTRL_VREG) MASK Register */
-
-/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Enable          */
-    uint32_t BGOUTEN:1;        /*!< bit:      2  Bandgap Output Enable              */
-    uint32_t :13;              /*!< bit:  3..15  Reserved                           */
-    uint32_t CALIB:11;         /*!< bit: 16..26  Bandgap Voltage Generator Calibration */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_VREF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_VREF_OFFSET         0x40         /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
-#define SYSCTRL_VREF_RESETVALUE     0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
-
-#define SYSCTRL_VREF_TSEN_Pos       1            /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
-#define SYSCTRL_VREF_TSEN           (0x1ul << SYSCTRL_VREF_TSEN_Pos)
-#define SYSCTRL_VREF_BGOUTEN_Pos    2            /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
-#define SYSCTRL_VREF_BGOUTEN        (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
-#define SYSCTRL_VREF_CALIB_Pos      16           /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
-#define SYSCTRL_VREF_CALIB_Msk      (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
-#define SYSCTRL_VREF_CALIB(value)   (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
-#define SYSCTRL_VREF_MASK           0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
-
-/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W  8) DPLL Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable                        */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Clock Activation         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SYSCTRL_DPLLCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DPLLCTRLA_OFFSET    0x44         /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
-#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul       /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
-
-#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
-#define SYSCTRL_DPLLCTRLA_ENABLE    (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
-#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
-#define SYSCTRL_DPLLCTRLA_RUNSTDBY  (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
-#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
-#define SYSCTRL_DPLLCTRLA_ONDEMAND  (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
-#define SYSCTRL_DPLLCTRLA_MASK      0xC2ul       /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
-
-/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LDR:12;           /*!< bit:  0..11  Loop Divider Ratio                 */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t LDRFRAC:4;        /*!< bit: 16..19  Loop Divider Ratio Fractional Part */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_DPLLRATIO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DPLLRATIO_OFFSET    0x48         /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
-#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
-
-#define SYSCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
-#define SYSCTRL_DPLLRATIO_LDR_Msk   (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
-#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
-#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
-#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
-#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
-#define SYSCTRL_DPLLRATIO_MASK      0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
-
-/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FILTER:2;         /*!< bit:  0.. 1  Proportional Integral Filter Selection */
-    uint32_t LPEN:1;           /*!< bit:      2  Low-Power Enable                   */
-    uint32_t WUF:1;            /*!< bit:      3  Wake Up Fast                       */
-    uint32_t REFCLK:2;         /*!< bit:  4.. 5  Reference Clock Selection          */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t LBYPASS:1;        /*!< bit:     12  Lock Bypass                        */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SYSCTRL_DPLLCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DPLLCTRLB_OFFSET    0x4C         /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
-#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
-
-#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
-#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
-#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
-#define   SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
-#define   SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul  /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
-#define   SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul  /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
-#define   SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul  /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
-#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
-#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
-#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
-#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
-#define SYSCTRL_DPLLCTRLB_LPEN_Pos  2            /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
-#define SYSCTRL_DPLLCTRLB_LPEN      (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
-#define SYSCTRL_DPLLCTRLB_WUF_Pos   3            /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
-#define SYSCTRL_DPLLCTRLB_WUF       (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
-#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4            /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
-#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
-#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
-#define   SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
-#define   SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul  /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
-#define   SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul  /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
-#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
-#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
-#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
-#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
-#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
-#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
-#define   SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
-#define   SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
-#define   SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
-#define   SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
-#define   SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
-#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
-#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
-#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
-#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
-#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
-#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12           /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
-#define SYSCTRL_DPLLCTRLB_LBYPASS   (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
-#define SYSCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
-#define SYSCTRL_DPLLCTRLB_DIV_Msk   (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
-#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
-#define SYSCTRL_DPLLCTRLB_MASK      0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
-
-/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/   8) DPLL Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
-    uint8_t  CLKRDY:1;         /*!< bit:      1  Output Clock Ready                 */
-    uint8_t  ENABLE:1;         /*!< bit:      2  DPLL Enable                        */
-    uint8_t  DIV:1;            /*!< bit:      3  Divider Enable                     */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SYSCTRL_DPLLSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SYSCTRL_DPLLSTATUS_OFFSET   0x50         /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
-#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
-
-#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
-#define SYSCTRL_DPLLSTATUS_LOCK     (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
-#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
-#define SYSCTRL_DPLLSTATUS_CLKRDY   (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
-#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
-#define SYSCTRL_DPLLSTATUS_ENABLE   (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
-#define SYSCTRL_DPLLSTATUS_DIV_Pos  3            /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
-#define SYSCTRL_DPLLSTATUS_DIV      (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
-#define SYSCTRL_DPLLSTATUS_MASK     0x0Ful       /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
-
-/** \brief SYSCTRL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO SYSCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
-  __IO SYSCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
-  __IO SYSCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
-  __I  SYSCTRL_PCLKSR_Type       PCLKSR;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
-  __IO SYSCTRL_XOSC_Type         XOSC;        /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
-       RoReg8                    Reserved1[0x2];
-  __IO SYSCTRL_XOSC32K_Type      XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
-       RoReg8                    Reserved2[0x2];
-  __IO SYSCTRL_OSC32K_Type       OSC32K;      /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
-  __IO SYSCTRL_OSCULP32K_Type    OSCULP32K;   /**< \brief Offset: 0x1C (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-       RoReg8                    Reserved3[0x3];
-  __IO SYSCTRL_OSC8M_Type        OSC8M;       /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
-  __IO SYSCTRL_DFLLCTRL_Type     DFLLCTRL;    /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
-       RoReg8                    Reserved4[0x2];
-  __IO SYSCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
-  __IO SYSCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
-  __IO SYSCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x30 (R/W  8) DFLL48M Synchronization */
-       RoReg8                    Reserved5[0x3];
-  __IO SYSCTRL_BOD33_Type        BOD33;       /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
-       RoReg8                    Reserved6[0x4];
-  __IO SYSCTRL_VREG_Type         VREG;        /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
-       RoReg8                    Reserved7[0x2];
-  __IO SYSCTRL_VREF_Type         VREF;        /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
-  __IO SYSCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x44 (R/W  8) DPLL Control A */
-       RoReg8                    Reserved8[0x3];
-  __IO SYSCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
-  __IO SYSCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
-  __I  SYSCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x50 (R/   8) DPLL Status */
-} Sysctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_COMPONENT_
+#define _SAMD21_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL                 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET     0x00         /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSCRDY    (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC32KRDY  (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC8MRDY   (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRDY    (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLOOB    (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKC   (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRCS    (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33RDY   (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33DET   (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_B33SRDY    (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKR   (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKF   (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLTO    (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
+#define SYSCTRL_INTENCLR_MASK       0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET     0x04         /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSCRDY    (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC32KRDY  (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC8MRDY   (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRDY    (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLOOB    (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKF   (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKC   (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRCS    (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33RDY   (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33DET   (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_B33SRDY    (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKR   (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKF   (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLTO    (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
+#define SYSCTRL_INTENSET_MASK       0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    __I uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    __I uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    __I uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    __I uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    __I uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    __I uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    __I uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    __I uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    __I uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    __I uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    __I uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    __I uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    __I uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
+    __I uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
+    __I uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
+    __I uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET      0x08         /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY     (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY  (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY   (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY    (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY     (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB     (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC    (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS     (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY    (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET    (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY     (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
+#define SYSCTRL_INTFLAG_DPLLLCKR    (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
+#define SYSCTRL_INTFLAG_DPLLLCKF    (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
+#define SYSCTRL_INTFLAG_DPLLLTO     (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
+#define SYSCTRL_INTFLAG_MASK        0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET       0x0C         /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE   0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos  0            /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY      (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY   (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY    (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY     (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos  4            /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY      (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos  5            /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB      (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC     (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos  8            /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS      (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY     (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET     (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos  11           /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY      (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
+#define SYSCTRL_PCLKSR_DPLLLCKR     (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
+#define SYSCTRL_PCLKSR_DPLLLCKF     (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DPLLLTO_Pos  17           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
+#define SYSCTRL_PCLKSR_DPLLLTO      (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
+#define SYSCTRL_PCLKSR_MASK         0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t GAIN:3;           /*!< bit:  8..10  Oscillator Gain                    */
+    uint16_t AMPGC:1;          /*!< bit:     11  Automatic Amplitude Gain Control   */
+    uint16_t STARTUP:4;        /*!< bit: 12..15  Start-Up Time                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET         0x10         /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define SYSCTRL_XOSC_RESETVALUE     0x0080ul     /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos     1            /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
+#define SYSCTRL_XOSC_ENABLE         (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos     2            /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN         (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_XOSC) Run in Standby */
+#define SYSCTRL_XOSC_RUNSTDBY       (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos   7            /**< \brief (SYSCTRL_XOSC) On Demand Control */
+#define SYSCTRL_XOSC_ONDEMAND       (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos       8            /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
+#define SYSCTRL_XOSC_GAIN_Msk       (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value)    (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
+#define   SYSCTRL_XOSC_GAIN_0_Val         0x0ul  /**< \brief (SYSCTRL_XOSC) 2MHz */
+#define   SYSCTRL_XOSC_GAIN_1_Val         0x1ul  /**< \brief (SYSCTRL_XOSC) 4MHz */
+#define   SYSCTRL_XOSC_GAIN_2_Val         0x2ul  /**< \brief (SYSCTRL_XOSC) 8MHz */
+#define   SYSCTRL_XOSC_GAIN_3_Val         0x3ul  /**< \brief (SYSCTRL_XOSC) 16MHz */
+#define   SYSCTRL_XOSC_GAIN_4_Val         0x4ul  /**< \brief (SYSCTRL_XOSC) 30MHz */
+#define SYSCTRL_XOSC_GAIN_0         (SYSCTRL_XOSC_GAIN_0_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_1         (SYSCTRL_XOSC_GAIN_1_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_2         (SYSCTRL_XOSC_GAIN_2_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_3         (SYSCTRL_XOSC_GAIN_3_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_4         (SYSCTRL_XOSC_GAIN_4_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_AMPGC_Pos      11           /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC          (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos    12           /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk    (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
+#define SYSCTRL_XOSC_MASK           0xFFC6ul     /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
+    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
+    uint16_t AAMPEN:1;         /*!< bit:      5  Automatic Amplitude Control Enable */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET      0x14         /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define SYSCTRL_XOSC32K_RESETVALUE  0x0080ul     /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos  1            /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
+#define SYSCTRL_XOSC32K_ENABLE      (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos  2            /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN      (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos   3            /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K       (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos    4            /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K        (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos  5            /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN      (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY    (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
+#define SYSCTRL_XOSC32K_ONDEMAND    (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK     (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK        0x17FEul     /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t EN32K:1;          /*!< bit:      2  32kHz Output Enable                */
+    uint32_t EN1K:1;           /*!< bit:      3  1kHz Output Enable                 */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t CALIB:7;          /*!< bit: 16..22  Oscillator Calibration             */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET       0x18         /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define SYSCTRL_OSC32K_RESETVALUE   0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos   1            /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
+#define SYSCTRL_OSC32K_ENABLE       (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos    2            /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K        (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos     3            /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K         (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_OSC32K) Run in Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY     (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_OSC32K) On Demand Control */
+#define SYSCTRL_OSC32K_ONDEMAND     (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos  8            /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk  (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos  12           /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK      (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos    16           /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
+#define SYSCTRL_OSC32K_CALIB_Msk    (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
+#define SYSCTRL_OSC32K_MASK         0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CALIB:5;          /*!< bit:  0.. 4  Oscillator Calibration             */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET    0x1C         /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful       /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0            /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7            /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK   (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK      0x9Ful       /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t PRESC:2;          /*!< bit:  8.. 9  Oscillator Prescaler               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CALIB:12;         /*!< bit: 16..27  Oscillator Calibration             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t FRANGE:2;         /*!< bit: 30..31  Oscillator Frequency Range         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET        0x20         /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
+#define SYSCTRL_OSC8M_RESETVALUE    0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos    1            /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
+#define SYSCTRL_OSC8M_ENABLE        (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_OSC8M) Run in Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY      (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos  7            /**< \brief (SYSCTRL_OSC8M) On Demand Control */
+#define SYSCTRL_OSC8M_ONDEMAND      (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos     8            /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
+#define SYSCTRL_OSC8M_PRESC_Msk     (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value)  (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
+#define   SYSCTRL_OSC8M_PRESC_0_Val       0x0ul  /**< \brief (SYSCTRL_OSC8M) 1 */
+#define   SYSCTRL_OSC8M_PRESC_1_Val       0x1ul  /**< \brief (SYSCTRL_OSC8M) 2 */
+#define   SYSCTRL_OSC8M_PRESC_2_Val       0x2ul  /**< \brief (SYSCTRL_OSC8M) 4 */
+#define   SYSCTRL_OSC8M_PRESC_3_Val       0x3ul  /**< \brief (SYSCTRL_OSC8M) 8 */
+#define SYSCTRL_OSC8M_PRESC_0       (SYSCTRL_OSC8M_PRESC_0_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_1       (SYSCTRL_OSC8M_PRESC_1_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_2       (SYSCTRL_OSC8M_PRESC_2_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_3       (SYSCTRL_OSC8M_PRESC_3_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_CALIB_Pos     16           /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
+#define SYSCTRL_OSC8M_CALIB_Msk     (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value)  (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
+#define SYSCTRL_OSC8M_FRANGE_Pos    30           /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk    (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
+#define   SYSCTRL_OSC8M_FRANGE_0_Val      0x0ul  /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
+#define   SYSCTRL_OSC8M_FRANGE_1_Val      0x1ul  /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
+#define   SYSCTRL_OSC8M_FRANGE_2_Val      0x2ul  /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
+#define   SYSCTRL_OSC8M_FRANGE_3_Val      0x3ul  /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
+#define SYSCTRL_OSC8M_FRANGE_0      (SYSCTRL_OSC8M_FRANGE_0_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_1      (SYSCTRL_OSC8M_FRANGE_1_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_2      (SYSCTRL_OSC8M_FRANGE_2_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_3      (SYSCTRL_OSC8M_FRANGE_3_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_MASK          0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
+    uint16_t MODE:1;           /*!< bit:      2  Operating Mode Selection           */
+    uint16_t STABLE:1;         /*!< bit:      3  Stable DFLL Frequency              */
+    uint16_t LLAW:1;           /*!< bit:      4  Lose Lock After Wake               */
+    uint16_t USBCRM:1;         /*!< bit:      5  USB Clock Recovery Mode            */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t CCDIS:1;          /*!< bit:      8  Chill Cycle Disable                */
+    uint16_t QLDIS:1;          /*!< bit:      9  Quick Lock Disable                 */
+    uint16_t BPLCKC:1;         /*!< bit:     10  Bypass Coarse Lock                 */
+    uint16_t WAITLOCK:1;       /*!< bit:     11  Wait Lock                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET     0x24         /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul     /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1            /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE     (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos   2            /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE       (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3            /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE     (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos   4            /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW       (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5            /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define SYSCTRL_DFLLCTRL_USBCRM     (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY   (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
+#define SYSCTRL_DFLLCTRL_ONDEMAND   (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos  8            /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS      (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos  9            /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS      (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10           /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define SYSCTRL_DFLLCTRL_BPLCKC     (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
+#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11           /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
+#define SYSCTRL_DFLLCTRL_WAITLOCK   (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define SYSCTRL_DFLLCTRL_MASK       0x0FFEul     /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FINE:10;          /*!< bit:  0.. 9  Fine Value                         */
+    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
+    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET      0x28         /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk    (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
+#define SYSCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk  (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
+#define SYSCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk    (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
+#define SYSCTRL_DFLLVAL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
+    uint32_t FSTEP:10;         /*!< bit: 16..25  Fine Maximum Step                  */
+    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET      0x2C         /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE  0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
+#define SYSCTRL_DFLLMUL_MUL_Msk     (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value)  (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk   (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk   (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
+#define SYSCTRL_DFLLMUL_MASK        0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W  8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  READREQ:1;        /*!< bit:      7  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET     0x30         /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7            /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
+#define SYSCTRL_DFLLSYNC_READREQ    (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK       0x80ul       /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t HYST:1;           /*!< bit:      2  Hysteresis                         */
+    uint32_t ACTION:2;         /*!< bit:  3.. 4  BOD33 Action                       */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MODE:1;           /*!< bit:      8  Operation Mode                     */
+    uint32_t CEN:1;            /*!< bit:      9  Clock Enable                       */
+    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint32_t PSEL:4;           /*!< bit: 12..15  Prescaler Select                   */
+    uint32_t LEVEL:6;          /*!< bit: 16..21  BOD33 Threshold Level              */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET        0x34         /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE    0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos    1            /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE        (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos      2            /**< \brief (SYSCTRL_BOD33) Hysteresis */
+#define SYSCTRL_BOD33_HYST          (0x1ul << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos    3            /**< \brief (SYSCTRL_BOD33) BOD33 Action */
+#define SYSCTRL_BOD33_ACTION_Msk    (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
+#define   SYSCTRL_BOD33_ACTION_NONE_Val   0x0ul  /**< \brief (SYSCTRL_BOD33) No action */
+#define   SYSCTRL_BOD33_ACTION_RESET_Val  0x1ul  /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
+#define   SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul  /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
+#define SYSCTRL_BOD33_ACTION_NONE   (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_RESET  (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_BOD33) Run in Standby */
+#define SYSCTRL_BOD33_RUNSTDBY      (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos      8            /**< \brief (SYSCTRL_BOD33) Operation Mode */
+#define SYSCTRL_BOD33_MODE          (0x1ul << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos       9            /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN           (0x1ul << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos      12           /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk      (0xFul << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value)   (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
+#define   SYSCTRL_BOD33_PSEL_DIV2_Val     0x0ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
+#define   SYSCTRL_BOD33_PSEL_DIV4_Val     0x1ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
+#define   SYSCTRL_BOD33_PSEL_DIV8_Val     0x2ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
+#define   SYSCTRL_BOD33_PSEL_DIV16_Val    0x3ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
+#define   SYSCTRL_BOD33_PSEL_DIV32_Val    0x4ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
+#define   SYSCTRL_BOD33_PSEL_DIV64_Val    0x5ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
+#define   SYSCTRL_BOD33_PSEL_DIV128_Val   0x6ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
+#define   SYSCTRL_BOD33_PSEL_DIV256_Val   0x7ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
+#define   SYSCTRL_BOD33_PSEL_DIV512_Val   0x8ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
+#define   SYSCTRL_BOD33_PSEL_DIV1K_Val    0x9ul  /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
+#define   SYSCTRL_BOD33_PSEL_DIV2K_Val    0xAul  /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
+#define   SYSCTRL_BOD33_PSEL_DIV4K_Val    0xBul  /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
+#define   SYSCTRL_BOD33_PSEL_DIV8K_Val    0xCul  /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
+#define   SYSCTRL_BOD33_PSEL_DIV16K_Val   0xDul  /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
+#define   SYSCTRL_BOD33_PSEL_DIV32K_Val   0xEul  /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
+#define   SYSCTRL_BOD33_PSEL_DIV64K_Val   0xFul  /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
+#define SYSCTRL_BOD33_PSEL_DIV2     (SYSCTRL_BOD33_PSEL_DIV2_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4     (SYSCTRL_BOD33_PSEL_DIV4_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8     (SYSCTRL_BOD33_PSEL_DIV8_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16    (SYSCTRL_BOD33_PSEL_DIV16_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32    (SYSCTRL_BOD33_PSEL_DIV32_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64    (SYSCTRL_BOD33_PSEL_DIV64_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV128   (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV256   (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV512   (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV1K    (SYSCTRL_BOD33_PSEL_DIV1K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV2K    (SYSCTRL_BOD33_PSEL_DIV2K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4K    (SYSCTRL_BOD33_PSEL_DIV4K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8K    (SYSCTRL_BOD33_PSEL_DIV8K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16K   (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32K   (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64K   (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_LEVEL_Pos     16           /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk     (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value)  (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
+#define SYSCTRL_BOD33_MASK          0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t :6;               /*!< bit:  7..12  Reserved                           */
+    uint16_t FORCELDO:1;       /*!< bit:     13  Force LDO Voltage Regulator        */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET         0x3C         /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
+#define SYSCTRL_VREG_RESETVALUE     0x0000ul     /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_VREG) Run in Standby */
+#define SYSCTRL_VREG_RUNSTDBY       (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos   13           /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO       (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK           0x2040ul     /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Enable          */
+    uint32_t BGOUTEN:1;        /*!< bit:      2  Bandgap Output Enable              */
+    uint32_t :13;              /*!< bit:  3..15  Reserved                           */
+    uint32_t CALIB:11;         /*!< bit: 16..26  Bandgap Voltage Generator Calibration */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET         0x40         /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
+#define SYSCTRL_VREF_RESETVALUE     0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
+
+#define SYSCTRL_VREF_TSEN_Pos       1            /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
+#define SYSCTRL_VREF_TSEN           (0x1ul << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos    2            /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN        (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos      16           /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
+#define SYSCTRL_VREF_CALIB_Msk      (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value)   (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
+#define SYSCTRL_VREF_MASK           0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W  8) DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable                        */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Clock Activation         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLA_OFFSET    0x44         /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
+#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul       /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
+#define SYSCTRL_DPLLCTRLA_ENABLE    (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY  (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
+#define SYSCTRL_DPLLCTRLA_ONDEMAND  (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define SYSCTRL_DPLLCTRLA_MASK      0xC2ul       /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LDR:12;           /*!< bit:  0..11  Loop Divider Ratio                 */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t LDRFRAC:4;        /*!< bit: 16..19  Loop Divider Ratio Fractional Part */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLRATIO_OFFSET    0x48         /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define SYSCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
+#define SYSCTRL_DPLLRATIO_LDR_Msk   (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
+#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define SYSCTRL_DPLLRATIO_MASK      0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FILTER:2;         /*!< bit:  0.. 1  Proportional Integral Filter Selection */
+    uint32_t LPEN:1;           /*!< bit:      2  Low-Power Enable                   */
+    uint32_t WUF:1;            /*!< bit:      3  Wake Up Fast                       */
+    uint32_t REFCLK:2;         /*!< bit:  4.. 5  Reference Clock Selection          */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t LBYPASS:1;        /*!< bit:     12  Lock Bypass                        */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLB_OFFSET    0x4C         /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
+#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
+#define   SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
+#define   SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul  /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
+#define   SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul  /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
+#define   SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul  /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_LPEN_Pos  2            /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
+#define SYSCTRL_DPLLCTRLB_LPEN      (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
+#define SYSCTRL_DPLLCTRLB_WUF_Pos   3            /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
+#define SYSCTRL_DPLLCTRLB_WUF       (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4            /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
+#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
+#define   SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
+#define   SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul  /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
+#define   SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul  /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
+#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
+#define   SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul  /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
+#define   SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul  /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12           /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
+#define SYSCTRL_DPLLCTRLB_LBYPASS   (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
+#define SYSCTRL_DPLLCTRLB_DIV_Msk   (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
+#define SYSCTRL_DPLLCTRLB_MASK      0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/   8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
+    uint8_t  CLKRDY:1;         /*!< bit:      1  Output Clock Ready                 */
+    uint8_t  ENABLE:1;         /*!< bit:      2  DPLL Enable                        */
+    uint8_t  DIV:1;            /*!< bit:      3  Divider Enable                     */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLSTATUS_OFFSET   0x50         /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
+#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul       /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
+#define SYSCTRL_DPLLSTATUS_LOCK     (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
+#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
+#define SYSCTRL_DPLLSTATUS_CLKRDY   (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
+#define SYSCTRL_DPLLSTATUS_ENABLE   (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
+#define SYSCTRL_DPLLSTATUS_DIV_Pos  3            /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
+#define SYSCTRL_DPLLSTATUS_DIV      (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
+#define SYSCTRL_DPLLSTATUS_MASK     0x0Ful       /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO SYSCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO SYSCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO SYSCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  SYSCTRL_PCLKSR_Type       PCLKSR;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO SYSCTRL_XOSC_Type         XOSC;        /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+       RoReg8                    Reserved1[0x2];
+  __IO SYSCTRL_XOSC32K_Type      XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+       RoReg8                    Reserved2[0x2];
+  __IO SYSCTRL_OSC32K_Type       OSC32K;      /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+  __IO SYSCTRL_OSCULP32K_Type    OSCULP32K;   /**< \brief Offset: 0x1C (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+       RoReg8                    Reserved3[0x3];
+  __IO SYSCTRL_OSC8M_Type        OSC8M;       /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+  __IO SYSCTRL_DFLLCTRL_Type     DFLLCTRL;    /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+       RoReg8                    Reserved4[0x2];
+  __IO SYSCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+  __IO SYSCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+  __IO SYSCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x30 (R/W  8) DFLL48M Synchronization */
+       RoReg8                    Reserved5[0x3];
+  __IO SYSCTRL_BOD33_Type        BOD33;       /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+       RoReg8                    Reserved6[0x4];
+  __IO SYSCTRL_VREG_Type         VREG;        /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+       RoReg8                    Reserved7[0x2];
+  __IO SYSCTRL_VREF_Type         VREF;        /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+  __IO SYSCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x44 (R/W  8) DPLL Control A */
+       RoReg8                    Reserved8[0x3];
+  __IO SYSCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+  __IO SYSCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+  __I  SYSCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x50 (R/   8) DPLL Status */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h
index 76962c7..5ac5ef3 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h
@@ -1,674 +1,674 @@
-/**
- * \file
- *
- * \brief Component description for TC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TC_COMPONENT_
-#define _SAMD21_TC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_TC Basic Timer Counter */
-/*@{*/
-
-#define TC_U2212
-#define REV_TC                      0x131
-
-/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  TC Mode                            */
-    uint16_t :1;               /*!< bit:      4  Reserved                           */
-    uint16_t WAVEGEN:2;        /*!< bit:  5.. 6  Waveform Generation Operation      */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
-    uint16_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
-    uint16_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
-#define TC_CTRLA_RESETVALUE         0x0000ul     /**< \brief (TC_CTRLA reset_value) Control A */
-
-#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
-#define TC_CTRLA_SWRST              (0x1ul << TC_CTRLA_SWRST_Pos)
-#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
-#define TC_CTRLA_ENABLE             (0x1ul << TC_CTRLA_ENABLE_Pos)
-#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) TC Mode */
-#define TC_CTRLA_MODE_Msk           (0x3ul << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE(value)        (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
-#define   TC_CTRLA_MODE_COUNT16_Val       0x0ul  /**< \brief (TC_CTRLA) Counter in 16-bit mode */
-#define   TC_CTRLA_MODE_COUNT8_Val        0x1ul  /**< \brief (TC_CTRLA) Counter in 8-bit mode */
-#define   TC_CTRLA_MODE_COUNT32_Val       0x2ul  /**< \brief (TC_CTRLA) Counter in 32-bit mode */
-#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_WAVEGEN_Pos        5            /**< \brief (TC_CTRLA) Waveform Generation Operation */
-#define TC_CTRLA_WAVEGEN_Msk        (0x3ul << TC_CTRLA_WAVEGEN_Pos)
-#define TC_CTRLA_WAVEGEN(value)     (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
-#define   TC_CTRLA_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TC_CTRLA)  */
-#define   TC_CTRLA_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TC_CTRLA)  */
-#define   TC_CTRLA_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TC_CTRLA)  */
-#define   TC_CTRLA_WAVEGEN_MPWM_Val       0x3ul  /**< \brief (TC_CTRLA)  */
-#define TC_CTRLA_WAVEGEN_NFRQ       (TC_CTRLA_WAVEGEN_NFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
-#define TC_CTRLA_WAVEGEN_MFRQ       (TC_CTRLA_WAVEGEN_MFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
-#define TC_CTRLA_WAVEGEN_NPWM       (TC_CTRLA_WAVEGEN_NPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
-#define TC_CTRLA_WAVEGEN_MPWM       (TC_CTRLA_WAVEGEN_MPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
-#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
-#define TC_CTRLA_PRESCALER_Msk      (0x7ul << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER(value)   (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
-#define   TC_CTRLA_PRESCALER_DIV1_Val     0x0ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
-#define   TC_CTRLA_PRESCALER_DIV2_Val     0x1ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
-#define   TC_CTRLA_PRESCALER_DIV4_Val     0x2ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
-#define   TC_CTRLA_PRESCALER_DIV8_Val     0x3ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
-#define   TC_CTRLA_PRESCALER_DIV16_Val    0x4ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
-#define   TC_CTRLA_PRESCALER_DIV64_Val    0x5ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
-#define   TC_CTRLA_PRESCALER_DIV256_Val   0x6ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
-#define   TC_CTRLA_PRESCALER_DIV1024_Val  0x7ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
-#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_RUNSTDBY_Pos       11           /**< \brief (TC_CTRLA) Run in Standby */
-#define TC_CTRLA_RUNSTDBY           (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
-#define TC_CTRLA_PRESCSYNC_Pos      12           /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
-#define TC_CTRLA_PRESCSYNC_Msk      (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC(value)   (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
-#define   TC_CTRLA_PRESCSYNC_GCLK_Val     0x0ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
-#define   TC_CTRLA_PRESCSYNC_PRESC_Val    0x1ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
-#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   0x2ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
-#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_MASK               0x3F6Ful     /**< \brief (TC_CTRLA) MASK Register */
-
-/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ADDR:5;           /*!< bit:  0.. 4  Address                            */
-    uint16_t :9;               /*!< bit:  5..13  Reserved                           */
-    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
-    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_READREQ_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_READREQ_OFFSET           0x02         /**< \brief (TC_READREQ offset) Read Request */
-#define TC_READREQ_RESETVALUE       0x0000ul     /**< \brief (TC_READREQ reset_value) Read Request */
-
-#define TC_READREQ_ADDR_Pos         0            /**< \brief (TC_READREQ) Address */
-#define TC_READREQ_ADDR_Msk         (0x1Ful << TC_READREQ_ADDR_Pos)
-#define TC_READREQ_ADDR(value)      (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
-#define TC_READREQ_RCONT_Pos        14           /**< \brief (TC_READREQ) Read Continuously */
-#define TC_READREQ_RCONT            (0x1ul << TC_READREQ_RCONT_Pos)
-#define TC_READREQ_RREQ_Pos         15           /**< \brief (TC_READREQ) Read Request */
-#define TC_READREQ_RREQ             (0x1ul << TC_READREQ_RREQ_Pos)
-#define TC_READREQ_MASK             0xC01Ful     /**< \brief (TC_READREQ) MASK Register */
-
-/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
-#define TC_CTRLBCLR_RESETVALUE      0x02ul       /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
-
-#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
-#define TC_CTRLBCLR_DIR             (0x1ul << TC_CTRLBCLR_DIR_Pos)
-#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot */
-#define TC_CTRLBCLR_ONESHOT         (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
-#define TC_CTRLBCLR_CMD_Pos         6            /**< \brief (TC_CTRLBCLR) Command */
-#define TC_CTRLBCLR_CMD_Msk         (0x3ul << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD(value)      (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
-#define   TC_CTRLBCLR_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBCLR) No action */
-#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
-#define   TC_CTRLBCLR_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBCLR) Force a stop */
-#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_MASK            0xC5ul       /**< \brief (TC_CTRLBCLR) MASK Register */
-
-/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
-#define TC_CTRLBSET_RESETVALUE      0x00ul       /**< \brief (TC_CTRLBSET reset_value) Control B Set */
-
-#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
-#define TC_CTRLBSET_DIR             (0x1ul << TC_CTRLBSET_DIR_Pos)
-#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-Shot */
-#define TC_CTRLBSET_ONESHOT         (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
-#define TC_CTRLBSET_CMD_Pos         6            /**< \brief (TC_CTRLBSET) Command */
-#define TC_CTRLBSET_CMD_Msk         (0x3ul << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD(value)      (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
-#define   TC_CTRLBSET_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBSET) No action */
-#define   TC_CTRLBSET_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
-#define   TC_CTRLBSET_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBSET) Force a stop */
-#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_MASK            0xC5ul       /**< \brief (TC_CTRLBSET) MASK Register */
-
-/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W  8) Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform 0 Invert Enable    */
-    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform 1 Invert Enable    */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  CPTEN0:1;         /*!< bit:      4  Capture Channel 0 Enable           */
-    uint8_t  CPTEN1:1;         /*!< bit:      5  Capture Channel 1 Enable           */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform x Invert Enable    */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  CPTEN:2;          /*!< bit:  4.. 5  Capture Channel x Enable           */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLC_OFFSET             0x06         /**< \brief (TC_CTRLC offset) Control C */
-#define TC_CTRLC_RESETVALUE         0x00ul       /**< \brief (TC_CTRLC reset_value) Control C */
-
-#define TC_CTRLC_INVEN0_Pos         0            /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
-#define TC_CTRLC_INVEN0             (1 << TC_CTRLC_INVEN0_Pos)
-#define TC_CTRLC_INVEN1_Pos         1            /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
-#define TC_CTRLC_INVEN1             (1 << TC_CTRLC_INVEN1_Pos)
-#define TC_CTRLC_INVEN_Pos          0            /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
-#define TC_CTRLC_INVEN_Msk          (0x3ul << TC_CTRLC_INVEN_Pos)
-#define TC_CTRLC_INVEN(value)       (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
-#define TC_CTRLC_CPTEN0_Pos         4            /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
-#define TC_CTRLC_CPTEN0             (1 << TC_CTRLC_CPTEN0_Pos)
-#define TC_CTRLC_CPTEN1_Pos         5            /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
-#define TC_CTRLC_CPTEN1             (1 << TC_CTRLC_CPTEN1_Pos)
-#define TC_CTRLC_CPTEN_Pos          4            /**< \brief (TC_CTRLC) Capture Channel x Enable */
-#define TC_CTRLC_CPTEN_Msk          (0x3ul << TC_CTRLC_CPTEN_Pos)
-#define TC_CTRLC_CPTEN(value)       (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
-#define TC_CTRLC_MASK               0x33ul       /**< \brief (TC_CTRLC) MASK Register */
-
-/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_DBGCTRL_OFFSET           0x08         /**< \brief (TC_DBGCTRL offset) Debug Control */
-#define TC_DBGCTRL_RESETVALUE       0x00ul       /**< \brief (TC_DBGCTRL reset_value) Debug Control */
-
-#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Debug Run Mode */
-#define TC_DBGCTRL_DBGRUN           (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
-#define TC_DBGCTRL_MASK             0x01ul       /**< \brief (TC_DBGCTRL) MASK Register */
-
-/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
-    uint16_t :1;               /*!< bit:      3  Reserved                           */
-    uint16_t TCINV:1;          /*!< bit:      4  TC Inverted Event Input            */
-    uint16_t TCEI:1;           /*!< bit:      5  TC Event Input                     */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Event Output Enable */
-    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
-    uint16_t MCEO0:1;          /*!< bit:     12  Match or Capture Channel 0 Event Output Enable */
-    uint16_t MCEO1:1;          /*!< bit:     13  Match or Capture Channel 1 Event Output Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint16_t MCEO:2;           /*!< bit: 12..13  Match or Capture Channel x Event Output Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_EVCTRL_OFFSET            0x0A         /**< \brief (TC_EVCTRL offset) Event Control */
-#define TC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (TC_EVCTRL reset_value) Event Control */
-
-#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
-#define TC_EVCTRL_EVACT_Msk         (0x7ul << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT(value)      (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
-#define   TC_EVCTRL_EVACT_OFF_Val         0x0ul  /**< \brief (TC_EVCTRL) Event action disabled */
-#define   TC_EVCTRL_EVACT_RETRIGGER_Val   0x1ul  /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
-#define   TC_EVCTRL_EVACT_COUNT_Val       0x2ul  /**< \brief (TC_EVCTRL) Count on event */
-#define   TC_EVCTRL_EVACT_START_Val       0x3ul  /**< \brief (TC_EVCTRL) Start TC on event */
-#define   TC_EVCTRL_EVACT_PPW_Val         0x5ul  /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
-#define   TC_EVCTRL_EVACT_PWP_Val         0x6ul  /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
-#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Inverted Event Input */
-#define TC_EVCTRL_TCINV             (0x1ul << TC_EVCTRL_TCINV_Pos)
-#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Input */
-#define TC_EVCTRL_TCEI              (0x1ul << TC_EVCTRL_TCEI_Pos)
-#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
-#define TC_EVCTRL_OVFEO             (0x1ul << TC_EVCTRL_OVFEO_Pos)
-#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
-#define TC_EVCTRL_MCEO0             (1 << TC_EVCTRL_MCEO0_Pos)
-#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
-#define TC_EVCTRL_MCEO1             (1 << TC_EVCTRL_MCEO1_Pos)
-#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
-#define TC_EVCTRL_MCEO_Msk          (0x3ul << TC_EVCTRL_MCEO_Pos)
-#define TC_EVCTRL_MCEO(value)       (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
-#define TC_EVCTRL_MASK              0x3137ul     /**< \brief (TC_EVCTRL) MASK Register */
-
-/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  :1;               /*!< bit:      2  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
-    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
-    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTENCLR_OFFSET          0x0C         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
-#define TC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
-#define TC_INTENCLR_OVF             (0x1ul << TC_INTENCLR_OVF_Pos)
-#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) Error Interrupt Enable */
-#define TC_INTENCLR_ERR             (0x1ul << TC_INTENCLR_ERR_Pos)
-#define TC_INTENCLR_SYNCRDY_Pos     3            /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
-#define TC_INTENCLR_SYNCRDY         (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
-#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
-#define TC_INTENCLR_MC0             (1 << TC_INTENCLR_MC0_Pos)
-#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
-#define TC_INTENCLR_MC1             (1 << TC_INTENCLR_MC1_Pos)
-#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
-#define TC_INTENCLR_MC_Msk          (0x3ul << TC_INTENCLR_MC_Pos)
-#define TC_INTENCLR_MC(value)       (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
-#define TC_INTENCLR_MASK            0x3Bul       /**< \brief (TC_INTENCLR) MASK Register */
-
-/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  :1;               /*!< bit:      2  Reserved                           */
-    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
-    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
-    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTENSET_OFFSET          0x0D         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
-#define TC_INTENSET_RESETVALUE      0x00ul       /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
-#define TC_INTENSET_OVF             (0x1ul << TC_INTENSET_OVF_Pos)
-#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) Error Interrupt Enable */
-#define TC_INTENSET_ERR             (0x1ul << TC_INTENSET_ERR_Pos)
-#define TC_INTENSET_SYNCRDY_Pos     3            /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
-#define TC_INTENSET_SYNCRDY         (0x1ul << TC_INTENSET_SYNCRDY_Pos)
-#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
-#define TC_INTENSET_MC0             (1 << TC_INTENSET_MC0_Pos)
-#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
-#define TC_INTENSET_MC1             (1 << TC_INTENSET_MC1_Pos)
-#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
-#define TC_INTENSET_MC_Msk          (0x3ul << TC_INTENSET_MC_Pos)
-#define TC_INTENSET_MC(value)       (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
-#define TC_INTENSET_MASK            0x3Bul       /**< \brief (TC_INTENSET) MASK Register */
-
-/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  OVF:1;            /*!< bit:      0  Overflow                           */
-    __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
-    __I uint8_t  :1;               /*!< bit:      2  Reserved                           */
-    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
-    __I uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0         */
-    __I uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1         */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    __I uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x         */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTFLAG_OFFSET           0x0E         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) Overflow */
-#define TC_INTFLAG_OVF              (0x1ul << TC_INTFLAG_OVF_Pos)
-#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) Error */
-#define TC_INTFLAG_ERR              (0x1ul << TC_INTFLAG_ERR_Pos)
-#define TC_INTFLAG_SYNCRDY_Pos      3            /**< \brief (TC_INTFLAG) Synchronization Ready */
-#define TC_INTFLAG_SYNCRDY          (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
-#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
-#define TC_INTFLAG_MC0              (1 << TC_INTFLAG_MC0_Pos)
-#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
-#define TC_INTFLAG_MC1              (1 << TC_INTFLAG_MC1_Pos)
-#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) Match or Capture Channel x */
-#define TC_INTFLAG_MC_Msk           (0x3ul << TC_INTFLAG_MC_Pos)
-#define TC_INTFLAG_MC(value)        (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
-#define TC_INTFLAG_MASK             0x3Bul       /**< \brief (TC_INTFLAG) MASK Register */
-
-/* -------- TC_STATUS : (TC Offset: 0x0F) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :3;               /*!< bit:  0.. 2  Reserved                           */
-    uint8_t  STOP:1;           /*!< bit:      3  Stop                               */
-    uint8_t  SLAVE:1;          /*!< bit:      4  Slave                              */
-    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_STATUS_OFFSET            0x0F         /**< \brief (TC_STATUS offset) Status */
-#define TC_STATUS_RESETVALUE        0x08ul       /**< \brief (TC_STATUS reset_value) Status */
-
-#define TC_STATUS_STOP_Pos          3            /**< \brief (TC_STATUS) Stop */
-#define TC_STATUS_STOP              (0x1ul << TC_STATUS_STOP_Pos)
-#define TC_STATUS_SLAVE_Pos         4            /**< \brief (TC_STATUS) Slave */
-#define TC_STATUS_SLAVE             (0x1ul << TC_STATUS_SLAVE_Pos)
-#define TC_STATUS_SYNCBUSY_Pos      7            /**< \brief (TC_STATUS) Synchronization Busy */
-#define TC_STATUS_SYNCBUSY          (0x1ul << TC_STATUS_SYNCBUSY_Pos)
-#define TC_STATUS_MASK              0x98ul       /**< \brief (TC_STATUS) MASK Register */
-
-/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COUNT:16;         /*!< bit:  0..15  Count Value                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_COUNT16_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
-#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul     /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
-
-#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Count Value */
-#define TC_COUNT16_COUNT_COUNT_Msk  (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
-#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
-#define TC_COUNT16_COUNT_MASK       0xFFFFul     /**< \brief (TC_COUNT16_COUNT) MASK Register */
-
-/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:32;         /*!< bit:  0..31  Count Value                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_COUNT32_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
-#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
-
-#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Count Value */
-#define TC_COUNT32_COUNT_COUNT_Msk  (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
-#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
-#define TC_COUNT32_COUNT_MASK       0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
-
-/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W  8) COUNT8 COUNT8 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_COUNT_OFFSET      0x10         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
-#define TC_COUNT8_COUNT_RESETVALUE  0x00ul       /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
-
-#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
-#define TC_COUNT8_COUNT_COUNT_Msk   (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
-#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
-#define TC_COUNT8_COUNT_MASK        0xFFul       /**< \brief (TC_COUNT8_COUNT) MASK Register */
-
-/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Period Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_PER_OFFSET        0x14         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
-#define TC_COUNT8_PER_RESETVALUE    0xFFul       /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
-
-#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
-#define TC_COUNT8_PER_PER_Msk       (0xFFul << TC_COUNT8_PER_PER_Pos)
-#define TC_COUNT8_PER_PER(value)    (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
-#define TC_COUNT8_PER_MASK          0xFFul       /**< \brief (TC_COUNT8_PER) MASK Register */
-
-/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CC:16;            /*!< bit:  0..15  Compare/Capture Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_COUNT16_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_CC_OFFSET        0x18         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
-#define TC_COUNT16_CC_RESETVALUE    0x0000ul     /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
-
-#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
-#define TC_COUNT16_CC_CC_Msk        (0xFFFFul << TC_COUNT16_CC_CC_Pos)
-#define TC_COUNT16_CC_CC(value)     (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
-#define TC_COUNT16_CC_MASK          0xFFFFul     /**< \brief (TC_COUNT16_CC) MASK Register */
-
-/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CC:32;            /*!< bit:  0..31  Compare/Capture Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_COUNT32_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_CC_OFFSET        0x18         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
-#define TC_COUNT32_CC_RESETVALUE    0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
-
-#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
-#define TC_COUNT32_CC_CC_Msk        (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
-#define TC_COUNT32_CC_CC(value)     (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
-#define TC_COUNT32_CC_MASK          0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
-
-/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W  8) COUNT8 COUNT8 Compare/Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CC:8;             /*!< bit:  0.. 7  Compare/Capture Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_CC_OFFSET         0x18         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
-#define TC_COUNT8_CC_RESETVALUE     0x00ul       /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
-
-#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
-#define TC_COUNT8_CC_CC_Msk         (0xFFul << TC_COUNT8_CC_CC_Pos)
-#define TC_COUNT8_CC_CC(value)      (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
-#define TC_COUNT8_CC_MASK           0xFFul       /**< \brief (TC_COUNT8_CC) MASK Register */
-
-/** \brief TC_COUNT8 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 8-bit Counter Mode */
-  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
-  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
-       RoReg8                    Reserved1[0x1];
-  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
-       RoReg8                    Reserved2[0x1];
-  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
-  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
-  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
-  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
-  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
-  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W  8) COUNT8 Counter Value */
-       RoReg8                    Reserved3[0x3];
-  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W  8) COUNT8 Period Value */
-       RoReg8                    Reserved4[0x3];
-  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x18 (R/W  8) COUNT8 Compare/Capture */
-} TcCount8;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TC_COUNT16 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 16-bit Counter Mode */
-  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
-  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
-       RoReg8                    Reserved1[0x1];
-  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
-       RoReg8                    Reserved2[0x1];
-  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
-  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
-  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
-  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
-  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
-  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
-       RoReg8                    Reserved3[0x6];
-  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
-} TcCount16;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TC_COUNT32 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 32-bit Counter Mode */
-  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
-  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
-       RoReg8                    Reserved1[0x1];
-  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
-       RoReg8                    Reserved2[0x1];
-  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
-  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
-  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
-  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
-  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
-  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
-       RoReg8                    Reserved3[0x4];
-  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
-} TcCount32;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
-       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
-       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
-} Tc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_TC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC_COMPONENT_
+#define _SAMD21_TC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC                      0x131
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  TC Mode                            */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t WAVEGEN:2;        /*!< bit:  5.. 6  Waveform Generation Operation      */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint16_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint16_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE         0x0000ul     /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST              (0x1ul << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE             (0x1ul << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk           (0x3ul << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value)        (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define   TC_CTRLA_MODE_COUNT16_Val       0x0ul  /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define   TC_CTRLA_MODE_COUNT8_Val        0x1ul  /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define   TC_CTRLA_MODE_COUNT32_Val       0x2ul  /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos        5            /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk        (0x3ul << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value)     (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
+#define   TC_CTRLA_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MPWM_Val       0x3ul  /**< \brief (TC_CTRLA)  */
+#define TC_CTRLA_WAVEGEN_NFRQ       (TC_CTRLA_WAVEGEN_NFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ       (TC_CTRLA_WAVEGEN_MFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM       (TC_CTRLA_WAVEGEN_NPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM       (TC_CTRLA_WAVEGEN_MPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk      (0x7ul << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value)   (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define   TC_CTRLA_PRESCALER_DIV1_Val     0x0ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define   TC_CTRLA_PRESCALER_DIV2_Val     0x1ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define   TC_CTRLA_PRESCALER_DIV4_Val     0x2ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define   TC_CTRLA_PRESCALER_DIV8_Val     0x3ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define   TC_CTRLA_PRESCALER_DIV16_Val    0x4ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define   TC_CTRLA_PRESCALER_DIV64_Val    0x5ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define   TC_CTRLA_PRESCALER_DIV256_Val   0x6ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define   TC_CTRLA_PRESCALER_DIV1024_Val  0x7ul  /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos       11           /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY           (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos      12           /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk      (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value)   (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define   TC_CTRLA_PRESCSYNC_GCLK_Val     0x0ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define   TC_CTRLA_PRESCSYNC_PRESC_Val    0x1ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   0x2ul  /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK               0x3F6Ful     /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:5;           /*!< bit:  0.. 4  Address                            */
+    uint16_t :9;               /*!< bit:  5..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET           0x02         /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE       0x0000ul     /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos         0            /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk         (0x1Ful << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value)      (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
+#define TC_READREQ_RCONT_Pos        14           /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT            (0x1ul << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos         15           /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ             (0x1ul << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK             0xC01Ful     /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE      0x02ul       /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR             (0x1ul << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT         (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos         6            /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk         (0x3ul << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value)      (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define   TC_CTRLBCLR_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBCLR) No action */
+#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define   TC_CTRLBCLR_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK            0xC5ul       /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE      0x00ul       /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR             (0x1ul << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-Shot */
+#define TC_CTRLBSET_ONESHOT         (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos         6            /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk         (0x3ul << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value)      (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define   TC_CTRLBSET_CMD_NONE_Val        0x0ul  /**< \brief (TC_CTRLBSET) No action */
+#define   TC_CTRLBSET_CMD_RETRIGGER_Val   0x1ul  /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define   TC_CTRLBSET_CMD_STOP_Val        0x2ul  /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK            0xC5ul       /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W  8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform 0 Invert Enable    */
+    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform 1 Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN0:1;         /*!< bit:      4  Capture Channel 0 Enable           */
+    uint8_t  CPTEN1:1;         /*!< bit:      5  Capture Channel 1 Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform x Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN:2;          /*!< bit:  4.. 5  Capture Channel x Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET             0x06         /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE         0x00ul       /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos         0            /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0             (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos         1            /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1             (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos          0            /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk          (0x3ul << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value)       (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
+#define TC_CTRLC_CPTEN0_Pos         4            /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0             (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos         5            /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1             (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos          4            /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk          (0x3ul << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value)       (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
+#define TC_CTRLC_MASK               0x33ul       /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET           0x08         /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE       0x00ul       /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN           (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK             0x01ul       /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t TCINV:1;          /*!< bit:      4  TC Inverted Event Input            */
+    uint16_t TCEI:1;           /*!< bit:      5  TC Event Input                     */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Event Output Enable */
+    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
+    uint16_t MCEO0:1;          /*!< bit:     12  Match or Capture Channel 0 Event Output Enable */
+    uint16_t MCEO1:1;          /*!< bit:     13  Match or Capture Channel 1 Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t MCEO:2;           /*!< bit: 12..13  Match or Capture Channel x Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET            0x0A         /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk         (0x7ul << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value)      (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define   TC_EVCTRL_EVACT_OFF_Val         0x0ul  /**< \brief (TC_EVCTRL) Event action disabled */
+#define   TC_EVCTRL_EVACT_RETRIGGER_Val   0x1ul  /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define   TC_EVCTRL_EVACT_COUNT_Val       0x2ul  /**< \brief (TC_EVCTRL) Count on event */
+#define   TC_EVCTRL_EVACT_START_Val       0x3ul  /**< \brief (TC_EVCTRL) Start TC on event */
+#define   TC_EVCTRL_EVACT_PPW_Val         0x5ul  /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
+#define   TC_EVCTRL_EVACT_PWP_Val         0x6ul  /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV             (0x1ul << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI              (0x1ul << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO             (0x1ul << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0             (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1             (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk          (0x3ul << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value)       (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK              0x3137ul     /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET          0x0C         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF             (0x1ul << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR             (0x1ul << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos     3            /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY         (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0             (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1             (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk          (0x3ul << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value)       (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK            0x3Bul       /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET          0x0D         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE      0x00ul       /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF             (0x1ul << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR             (0x1ul << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos     3            /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY         (0x1ul << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0             (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1             (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk          (0x3ul << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value)       (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK            0x3Bul       /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
+    __I uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    __I uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0         */
+    __I uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1         */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    __I uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x         */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET           0x0E         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF              (0x1ul << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR              (0x1ul << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos      3            /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY          (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0              (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1              (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk           (0x3ul << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value)        (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK             0x3Bul       /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :3;               /*!< bit:  0.. 2  Reserved                           */
+    uint8_t  STOP:1;           /*!< bit:      3  Stop                               */
+    uint8_t  SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET            0x0F         /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE        0x08ul       /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos          3            /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP              (0x1ul << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos         4            /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE             (0x1ul << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos      7            /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY          (0x1ul << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK              0x98ul       /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Count Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul     /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Count Value */
+#define TC_COUNT16_COUNT_COUNT_Msk  (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK       0xFFFFul     /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Count Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Count Value */
+#define TC_COUNT32_COUNT_COUNT_Msk  (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK       0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W  8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET      0x10         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE  0x00ul       /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk   (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK        0xFFul       /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET        0x14         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE    0xFFul       /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk       (0xFFul << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value)    (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK          0xFFul       /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CC:16;            /*!< bit:  0..15  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET        0x18         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE    0x0000ul     /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk        (0xFFFFul << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value)     (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK          0xFFFFul     /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CC:32;            /*!< bit:  0..31  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET        0x18         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE    0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk        (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value)     (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK          0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W  8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CC:8;             /*!< bit:  0.. 7  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET         0x18         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE     0x00ul       /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk         (0xFFul << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value)      (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK           0xFFul       /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W  8) COUNT8 Counter Value */
+       RoReg8                    Reserved3[0x3];
+  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W  8) COUNT8 Period Value */
+       RoReg8                    Reserved4[0x3];
+  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x18 (R/W  8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+       RoReg8                    Reserved3[0x6];
+  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
+       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
+       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h
index ec77656..db81c32 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h
@@ -1,1828 +1,1828 @@
-/**
- * \file
- *
- * \brief Component description for TCC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC_COMPONENT_
-#define _SAMD21_TCC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TCC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_TCC Timer Counter Control */
-/*@{*/
-
-#define TCC_U2213
-#define REV_TCC                     0x122
-
-/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
-    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
-    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
-    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
-    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
-    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
-    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
-    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
-    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
-    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
-#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
-
-#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
-#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
-#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
-#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
-#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
-#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
-#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
-#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
-#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
-#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
-#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
-#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
-#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
-#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
-#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
-#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
-#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
-#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
-#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
-#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
-#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
-#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
-#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
-#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
-#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
-#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
-#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
-#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
-#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
-#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
-#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
-#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
-#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
-#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
-#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
-#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
-#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
-#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
-#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
-
-/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
-#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
-
-#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
-#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
-#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
-#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
-#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
-#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
-#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
-#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
-#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
-#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
-#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
-#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
-#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
-#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
-#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
-#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
-
-/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
-#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
-
-#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
-#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
-#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
-#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
-#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
-#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
-#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
-#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
-#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
-#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
-#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
-#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
-#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
-#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
-#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
-#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
-
-/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
-    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
-    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
-    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
-    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
-    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
-    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
-    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
-    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
-    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
-    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
-    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
-    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
-    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
-    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
-    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
-    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
-    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
-    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
-#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
-#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
-#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
-#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
-#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
-#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
-#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
-#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
-#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
-#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
-#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
-#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
-#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
-#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
-#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
-#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
-#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
-#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
-#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
-#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
-#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
-#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
-#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
-#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
-#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
-#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
-#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
-#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
-#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
-#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
-#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
-#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
-#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
-#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
-#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
-#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
-#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
-#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
-#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
-#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
-#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
-#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
-#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
-#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
-#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
-
-/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
-#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
-
-#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
-#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
-#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
-#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
-#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
-#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
-#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
-#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
-#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
-#define   TCC_FCTRLA_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
-#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
-#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
-#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
-#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
-#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
-#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
-#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
-#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
-#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
-#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
-#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
-#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
-#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
-#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
-#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
-#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
-#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
-#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
-#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
-#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
-#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
-#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
-#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
-#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
-#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
-#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
-#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
-#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
-#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
-
-/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
-#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
-
-#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
-#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
-#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
-#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
-#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
-#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
-#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
-#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
-#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
-#define   TCC_FCTRLB_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
-#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
-#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
-#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
-#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
-#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
-#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
-#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
-#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
-#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
-#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
-#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
-#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
-#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
-#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
-#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
-#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
-#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
-#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
-#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
-#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
-#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
-#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
-#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
-#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
-#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
-#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
-#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
-#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
-#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
-
-/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
-    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
-    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
-    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
-    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
-    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WEXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
-#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
-
-#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
-#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
-#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
-#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
-#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
-#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
-#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
-#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
-#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
-#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
-#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
-#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
-#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
-#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
-#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
-#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
-#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
-#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
-#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
-#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
-#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
-
-/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
-    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
-    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
-    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
-    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
-    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
-    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
-    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
-    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
-    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
-    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
-    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
-    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
-    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
-    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
-    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
-    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
-    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
-    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
-    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
-    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
-    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
-    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
-    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
-    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
-    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
-    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
-    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
-#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
-
-#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
-#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
-#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
-#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
-#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
-#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
-#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
-#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
-#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
-#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
-#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
-#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
-#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
-#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
-#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
-#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
-#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
-#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
-#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
-#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
-#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
-#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
-#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
-#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
-#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
-#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
-#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
-#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
-#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
-#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
-#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
-#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
-#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
-#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
-#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
-#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
-#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
-#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
-#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
-#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
-#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
-#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
-#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
-#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
-#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
-#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
-#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
-#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
-#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
-#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
-#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
-#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
-#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
-#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
-#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
-#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
-#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
-#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
-#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
-#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
-#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
-#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
-
-/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
-#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
-
-#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
-#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
-#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
-#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
-#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
-
-/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
-    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
-    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
-    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
-    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
-    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
-    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
-    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
-    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
-    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
-    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
-    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
-    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
-    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
-    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
-    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
-    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
-    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
-#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
-
-#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
-#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
-#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
-#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
-#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
-#define   TCC_EVCTRL_EVACT0_STAMP_Val     0x6ul  /**< \brief (TCC_EVCTRL) Stamp capture */
-#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
-#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
-#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
-#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
-#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
-#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
-#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
-#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
-#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
-#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
-#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
-#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
-#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
-#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
-#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
-#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
-#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
-#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
-#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
-#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
-#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
-#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
-#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
-#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
-#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
-#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
-#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
-#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
-#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
-#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
-#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
-#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
-#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
-#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
-#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
-#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
-#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
-#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
-#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
-#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
-#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
-#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
-#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
-#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
-#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
-#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
-#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
-#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
-#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
-#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
-#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
-#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
-#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
-#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
-#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
-
-/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
-#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
-#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
-#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
-#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
-#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
-#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
-#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
-#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
-#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENCLR_UFS            (0x1ul << TCC_INTENCLR_UFS_Pos)
-#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
-#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
-#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
-#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
-#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
-#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
-#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
-#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
-#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
-#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
-#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
-#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
-
-/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
-#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
-#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
-#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
-#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
-#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
-#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
-#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
-#define TCC_INTENSET_ERR            (0x1ul << TCC_INTENSET_ERR_Pos)
-#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENSET_UFS            (0x1ul << TCC_INTENSET_UFS_Pos)
-#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
-#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
-#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
-#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
-#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
-#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
-#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
-#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
-#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
-#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
-#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
-#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
-
-/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
-    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
-    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
-    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
-    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
-    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
-    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
-    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
-    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
-    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
-    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
-    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
-    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
-    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
-    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
-    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
-#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
-#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
-#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
-#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
-#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
-#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
-#define TCC_INTFLAG_ERR             (0x1ul << TCC_INTFLAG_ERR_Pos)
-#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
-#define TCC_INTFLAG_UFS             (0x1ul << TCC_INTFLAG_UFS_Pos)
-#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
-#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
-#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
-#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
-#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
-#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
-#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
-#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
-#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
-#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
-#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
-#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
-#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
-#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
-#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
-#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
-#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
-#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
-#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
-#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
-#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
-#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
-
-/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
-    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
-    uint32_t UFS:1;            /*!< bit:      2  Non-Recoverable Update Fault State */
-    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
-    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
-    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
-    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
-    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
-    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
-    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
-    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
-    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
-    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
-    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
-    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
-    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
-    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
-    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
-    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
-#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
-
-#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
-#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
-#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
-#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
-#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
-#define TCC_STATUS_UFS              (0x1ul << TCC_STATUS_UFS_Pos)
-#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
-#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
-#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
-#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
-#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
-#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
-#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
-#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
-#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
-#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
-#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
-#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
-#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
-#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
-#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
-#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
-#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
-#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
-#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
-#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
-#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
-#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
-#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
-#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
-#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
-#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
-#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
-#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
-#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
-#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
-#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
-#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
-#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
-#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
-#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
-#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
-#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
-#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
-#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
-#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
-#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
-#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
-#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
-#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
-#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
-#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
-#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
-#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
-#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
-
-/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
-#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
-
-// DITH4 mode
-#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
-#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
-#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
-#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
-#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
-#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
-#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
-#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
-#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
-#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
-
-#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
-#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
-#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
-#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
-
-/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
-    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
-    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
-    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
-    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
-    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
-    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
-    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
-    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
-    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
-    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
-    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
-    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
-    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
-    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
-    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
-    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
-#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
-
-#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
-#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
-#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
-#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
-#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
-#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
-#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
-#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
-#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
-#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
-#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
-#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
-#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
-#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
-#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
-#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
-#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
-#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
-#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
-#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
-#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
-#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
-#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
-#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
-#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
-#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
-#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
-#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
-#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
-#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
-#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
-#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
-#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
-#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
-#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
-#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
-#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
-#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
-#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
-
-/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
-    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
-    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
-    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
-    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
-    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
-    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
-    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
-    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
-    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
-    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
-#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
-
-#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
-#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
-#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
-#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
-#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
-#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
-#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
-#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
-#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
-#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2C_Val        0x3ul  /**< \brief (TCC_WAVE) Critical RAMP2 operation */
-#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
-#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
-#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
-#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
-#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
-#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
-#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
-#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
-#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
-#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
-#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
-#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
-#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
-#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
-#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
-#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
-#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
-#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
-#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
-#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
-#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
-#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
-#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
-#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
-#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
-#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
-#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
-#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
-#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
-#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
-#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
-#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
-#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
-#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
-#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
-#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
-
-/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
-#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
-
-// DITH4 mode
-#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
-#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
-#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
-#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
-#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
-#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
-#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
-#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
-#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
-#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
-#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
-#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
-#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
-#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
-#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
-#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
-#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
-#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
-#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
-
-#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
-#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
-#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
-#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
-
-/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
-#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
-
-// DITH4 mode
-#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
-#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
-#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
-#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
-#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
-#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
-#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
-#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
-#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
-#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
-#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
-#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
-#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
-#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
-#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
-#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
-#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
-#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
-#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
-
-#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
-#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
-#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
-#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
-
-/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
-    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
-    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
-    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
-    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
-    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
-    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
-    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
-    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
-    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
-    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
-    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
-    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
-    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
-    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
-    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
-    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATTB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
-#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
-
-#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
-#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
-#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
-#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
-#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
-#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
-#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
-#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
-#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
-#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
-#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
-#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
-#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
-#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
-#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
-#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
-#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
-#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
-#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
-#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
-#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
-#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
-#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
-#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
-#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
-#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
-#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
-#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
-#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
-#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
-#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
-#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
-#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
-#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
-#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
-#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
-#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
-#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
-#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
-
-/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
-    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
-    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
-    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
-    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
-    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
-    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
-    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
-    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
-    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
-    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVEB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
-#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
-
-#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
-#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
-#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
-#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
-#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
-#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
-#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
-#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
-#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2C_Val      0x3ul  /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
-#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2C      (TCC_WAVEB_RAMPB_RAMP2C_Val    << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
-#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
-#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
-#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
-#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
-#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
-#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
-#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
-#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
-#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
-#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
-#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
-#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
-#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
-#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
-#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
-#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
-#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
-#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
-#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
-#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
-#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
-#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
-#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
-#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
-#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
-#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
-#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
-#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
-#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
-#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
-#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
-#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
-#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
-#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
-#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
-
-/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PERB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
-#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
-
-// DITH4 mode
-#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
-#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
-#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
-#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
-#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
-#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
-#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
-#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
-#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
-#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
-#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
-#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
-#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
-#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
-#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
-#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
-
-#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
-#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
-#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
-#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
-
-/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CCB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
-#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
-
-// DITH4 mode
-#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
-#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
-#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
-#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
-#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
-#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
-#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
-#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
-#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
-#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
-#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
-#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
-#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
-
-#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
-#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
-#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
-
-/** \brief TCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-       RoReg8                    Reserved1[0x2];
-  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
-  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
-  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
-  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
-  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
-       RoReg8                    Reserved2[0x2];
-  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
-       RoReg8                    Reserved3[0x1];
-  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
-  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
-  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
-  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
-  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
-  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
-  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
-       RoReg8                    Reserved4[0x2];
-  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
-  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
-  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
-       RoReg8                    Reserved5[0x10];
-  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
-       RoReg8                    Reserved6[0x2];
-  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
-  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
-  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
-} Tcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_TCC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x122
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
+    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
+    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
+    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
+    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
+    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
+    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
+    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
+    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
+#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
+#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define   TCC_EVCTRL_EVACT0_STAMP_Val     0x6ul  /**< \brief (TCC_EVCTRL) Stamp capture */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS            (0x1ul << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (0x1ul << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS            (0x1ul << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (0x1ul << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS             (0x1ul << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t UFS:1;            /*!< bit:      2  Non-Recoverable Update Fault State */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
+    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
+#define TCC_STATUS_UFS              (0x1ul << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2C_Val        0x3ul  /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
+    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
+    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
+    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
+    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
+    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
+    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
+    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
+    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
+    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
+    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
+#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
+#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
+#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2C_Val      0x3ul  /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2C      (TCC_WAVEB_RAMPB_RAMP2C_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x10];
+  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x2];
+  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
index ec77656..db81c32 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
@@ -1,1828 +1,1828 @@
-/**
- * \file
- *
- * \brief Component description for TCC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC_COMPONENT_
-#define _SAMD21_TCC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TCC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_TCC Timer Counter Control */
-/*@{*/
-
-#define TCC_U2213
-#define REV_TCC                     0x122
-
-/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
-    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
-    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
-    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
-    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
-    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
-    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
-    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
-    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
-    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
-#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
-
-#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
-#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
-#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
-#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
-#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
-#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
-#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
-#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
-#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
-#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
-#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
-#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
-#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
-#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
-#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
-#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
-#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
-#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
-#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
-#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
-#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
-#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
-#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
-#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
-#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
-#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
-#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
-#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
-#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
-#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
-#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
-#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
-#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
-#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
-#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
-#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
-#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
-#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
-#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
-
-/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
-#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
-
-#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
-#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
-#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
-#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
-#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
-#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
-#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
-#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
-#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
-#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
-#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
-#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
-#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
-#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
-#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
-#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
-
-/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
-#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
-
-#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
-#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
-#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
-#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
-#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
-#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
-#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
-#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
-#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
-#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
-#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
-#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
-#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
-#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
-#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
-#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
-
-/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
-    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
-    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
-    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
-    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
-    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
-    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
-    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
-    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
-    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
-    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
-    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
-    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
-    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
-    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
-    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
-    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
-    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
-    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
-#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
-#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
-#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
-#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
-#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
-#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
-#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
-#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
-#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
-#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
-#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
-#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
-#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
-#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
-#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
-#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
-#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
-#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
-#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
-#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
-#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
-#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
-#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
-#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
-#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
-#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
-#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
-#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
-#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
-#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
-#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
-#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
-#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
-#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
-#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
-#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
-#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
-#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
-#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
-#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
-#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
-#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
-#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
-#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
-#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
-
-/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
-#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
-
-#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
-#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
-#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
-#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
-#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
-#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
-#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
-#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
-#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
-#define   TCC_FCTRLA_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
-#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
-#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
-#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
-#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
-#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
-#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
-#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
-#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
-#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
-#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
-#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
-#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
-#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
-#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
-#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
-#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
-#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
-#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
-#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
-#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
-#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
-#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
-#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
-#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
-#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
-#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
-#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
-#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
-#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
-
-/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
-#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
-
-#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
-#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
-#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
-#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
-#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
-#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
-#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
-#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
-#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
-#define   TCC_FCTRLB_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
-#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
-#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
-#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
-#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
-#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
-#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
-#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
-#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
-#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
-#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
-#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
-#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
-#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
-#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
-#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
-#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
-#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
-#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
-#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
-#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
-#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
-#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
-#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
-#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
-#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
-#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
-#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
-#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
-#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
-
-/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
-    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
-    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
-    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
-    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
-    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WEXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
-#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
-
-#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
-#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
-#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
-#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
-#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
-#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
-#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
-#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
-#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
-#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
-#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
-#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
-#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
-#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
-#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
-#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
-#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
-#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
-#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
-#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
-#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
-
-/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
-    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
-    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
-    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
-    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
-    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
-    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
-    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
-    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
-    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
-    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
-    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
-    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
-    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
-    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
-    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
-    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
-    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
-    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
-    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
-    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
-    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
-    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
-    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
-    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
-    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
-    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
-    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
-#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
-
-#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
-#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
-#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
-#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
-#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
-#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
-#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
-#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
-#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
-#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
-#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
-#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
-#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
-#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
-#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
-#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
-#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
-#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
-#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
-#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
-#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
-#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
-#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
-#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
-#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
-#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
-#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
-#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
-#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
-#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
-#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
-#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
-#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
-#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
-#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
-#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
-#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
-#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
-#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
-#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
-#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
-#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
-#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
-#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
-#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
-#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
-#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
-#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
-#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
-#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
-#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
-#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
-#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
-#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
-#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
-#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
-#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
-#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
-#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
-#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
-#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
-#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
-
-/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
-#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
-
-#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
-#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
-#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
-#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
-#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
-
-/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
-    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
-    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
-    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
-    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
-    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
-    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
-    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
-    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
-    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
-    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
-    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
-    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
-    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
-    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
-    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
-    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
-    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
-#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
-
-#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
-#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
-#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
-#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
-#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
-#define   TCC_EVCTRL_EVACT0_STAMP_Val     0x6ul  /**< \brief (TCC_EVCTRL) Stamp capture */
-#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
-#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
-#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
-#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
-#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
-#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
-#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
-#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
-#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
-#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
-#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
-#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
-#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
-#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
-#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
-#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
-#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
-#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
-#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
-#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
-#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
-#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
-#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
-#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
-#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
-#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
-#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
-#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
-#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
-#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
-#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
-#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
-#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
-#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
-#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
-#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
-#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
-#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
-#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
-#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
-#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
-#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
-#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
-#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
-#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
-#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
-#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
-#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
-#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
-#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
-#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
-#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
-#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
-#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
-#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
-
-/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
-#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
-#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
-#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
-#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
-#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
-#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
-#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
-#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
-#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENCLR_UFS            (0x1ul << TCC_INTENCLR_UFS_Pos)
-#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
-#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
-#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
-#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
-#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
-#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
-#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
-#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
-#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
-#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
-#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
-#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
-
-/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
-#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
-#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
-#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
-#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
-#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
-#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
-#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
-#define TCC_INTENSET_ERR            (0x1ul << TCC_INTENSET_ERR_Pos)
-#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENSET_UFS            (0x1ul << TCC_INTENSET_UFS_Pos)
-#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
-#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
-#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
-#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
-#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
-#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
-#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
-#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
-#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
-#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
-#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
-#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
-
-/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
-    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
-    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
-    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
-    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
-    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
-    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
-    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
-    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
-    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
-    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
-    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
-    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
-    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
-    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
-    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
-#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
-#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
-#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
-#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
-#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
-#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
-#define TCC_INTFLAG_ERR             (0x1ul << TCC_INTFLAG_ERR_Pos)
-#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
-#define TCC_INTFLAG_UFS             (0x1ul << TCC_INTFLAG_UFS_Pos)
-#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
-#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
-#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
-#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
-#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
-#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
-#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
-#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
-#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
-#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
-#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
-#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
-#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
-#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
-#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
-#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
-#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
-#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
-#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
-#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
-#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
-#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
-
-/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
-    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
-    uint32_t UFS:1;            /*!< bit:      2  Non-Recoverable Update Fault State */
-    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
-    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
-    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
-    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
-    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
-    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
-    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
-    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
-    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
-    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
-    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
-    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
-    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
-    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
-    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
-    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
-#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
-
-#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
-#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
-#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
-#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
-#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
-#define TCC_STATUS_UFS              (0x1ul << TCC_STATUS_UFS_Pos)
-#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
-#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
-#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
-#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
-#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
-#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
-#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
-#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
-#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
-#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
-#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
-#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
-#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
-#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
-#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
-#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
-#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
-#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
-#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
-#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
-#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
-#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
-#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
-#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
-#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
-#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
-#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
-#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
-#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
-#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
-#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
-#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
-#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
-#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
-#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
-#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
-#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
-#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
-#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
-#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
-#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
-#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
-#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
-#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
-#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
-#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
-#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
-#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
-#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
-
-/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
-#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
-
-// DITH4 mode
-#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
-#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
-#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
-#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
-#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
-#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
-#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
-#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
-#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
-#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
-
-#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
-#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
-#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
-#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
-
-/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
-    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
-    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
-    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
-    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
-    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
-    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
-    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
-    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
-    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
-    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
-    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
-    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
-    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
-    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
-    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
-    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
-#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
-
-#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
-#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
-#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
-#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
-#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
-#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
-#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
-#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
-#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
-#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
-#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
-#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
-#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
-#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
-#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
-#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
-#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
-#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
-#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
-#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
-#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
-#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
-#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
-#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
-#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
-#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
-#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
-#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
-#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
-#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
-#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
-#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
-#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
-#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
-#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
-#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
-#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
-#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
-#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
-
-/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
-    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
-    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
-    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
-    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
-    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
-    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
-    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
-    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
-    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
-    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
-#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
-
-#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
-#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
-#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
-#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
-#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
-#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
-#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
-#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
-#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
-#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2C_Val        0x3ul  /**< \brief (TCC_WAVE) Critical RAMP2 operation */
-#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
-#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
-#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
-#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
-#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
-#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
-#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
-#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
-#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
-#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
-#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
-#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
-#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
-#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
-#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
-#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
-#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
-#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
-#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
-#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
-#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
-#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
-#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
-#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
-#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
-#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
-#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
-#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
-#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
-#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
-#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
-#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
-#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
-#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
-#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
-#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
-
-/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
-#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
-
-// DITH4 mode
-#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
-#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
-#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
-#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
-#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
-#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
-#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
-#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
-#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
-#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
-#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
-#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
-#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
-#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
-#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
-#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
-#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
-#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
-#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
-
-#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
-#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
-#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
-#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
-
-/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
-#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
-
-// DITH4 mode
-#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
-#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
-#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
-#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
-#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
-#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
-#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
-#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
-#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
-#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
-#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
-#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
-#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
-#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
-#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
-#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
-#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
-#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
-#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
-
-#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
-#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
-#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
-#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
-
-/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
-    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
-    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
-    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
-    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
-    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
-    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
-    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
-    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
-    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
-    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
-    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
-    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
-    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
-    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
-    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
-    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATTB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
-#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
-
-#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
-#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
-#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
-#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
-#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
-#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
-#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
-#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
-#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
-#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
-#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
-#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
-#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
-#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
-#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
-#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
-#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
-#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
-#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
-#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
-#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
-#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
-#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
-#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
-#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
-#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
-#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
-#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
-#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
-#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
-#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
-#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
-#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
-#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
-#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
-#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
-#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
-#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
-#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
-
-/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
-    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
-    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
-    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
-    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
-    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
-    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
-    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
-    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
-    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
-    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVEB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
-#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
-
-#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
-#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
-#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
-#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
-#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
-#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
-#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
-#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
-#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2C_Val      0x3ul  /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
-#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2C      (TCC_WAVEB_RAMPB_RAMP2C_Val    << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
-#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
-#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
-#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
-#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
-#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
-#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
-#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
-#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
-#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
-#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
-#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
-#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
-#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
-#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
-#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
-#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
-#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
-#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
-#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
-#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
-#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
-#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
-#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
-#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
-#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
-#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
-#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
-#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
-#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
-#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
-#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
-#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
-#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
-#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
-#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
-
-/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PERB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
-#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
-
-// DITH4 mode
-#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
-#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
-#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
-#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
-#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
-#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
-#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
-#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
-#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
-#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
-#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
-#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
-#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
-#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
-#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
-#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
-
-#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
-#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
-#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
-#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
-
-/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CCB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
-#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
-
-// DITH4 mode
-#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
-#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
-#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
-#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
-#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
-#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
-#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
-#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
-#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
-#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
-#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
-#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
-#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
-
-#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
-#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
-#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
-
-/** \brief TCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-       RoReg8                    Reserved1[0x2];
-  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
-  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
-  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
-  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
-  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
-       RoReg8                    Reserved2[0x2];
-  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
-       RoReg8                    Reserved3[0x1];
-  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
-  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
-  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
-  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
-  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
-  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
-  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
-       RoReg8                    Reserved4[0x2];
-  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
-  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
-  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
-       RoReg8                    Reserved5[0x10];
-  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
-       RoReg8                    Reserved6[0x2];
-  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
-  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
-  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
-} Tcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_TCC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x122
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
+    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
+    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
+    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
+    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
+    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
+    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
+    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
+    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
+#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_START_Val      0x0ul  /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
+#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul  /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define   TCC_EVCTRL_EVACT0_STAMP_Val     0x6ul  /**< \brief (TCC_EVCTRL) Stamp capture */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS            (0x1ul << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (0x1ul << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS            (0x1ul << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (0x1ul << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS             (0x1ul << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t UFS:1;            /*!< bit:      2  Non-Recoverable Update Fault State */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
+    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
+#define TCC_STATUS_UFS              (0x1ul << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2C_Val        0x3ul  /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
+    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
+    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
+    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
+    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
+    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
+    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
+    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
+    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
+    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
+    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
+#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
+#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
+#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2C_Val      0x3ul  /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2C      (TCC_WAVEB_RAMPB_RAMP2C_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x10];
+  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x2];
+  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h
index b5efb00..2dab0ba 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc_variant_d.h
@@ -1,1816 +1,1816 @@
-/**
- * \file
- *
- * \brief Component description for TCC
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC_COMPONENT_
-#define _SAMD21_TCC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TCC */
-/* ========================================================================== */
-/** \addtogroup SAMD21_TCC Timer Counter Control */
-/*@{*/
-
-#define TCC_U2213
-#define REV_TCC                     0x122
-
-/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
-    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
-    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
-    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
-    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
-    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
-    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
-    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
-    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
-    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
-#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
-
-#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
-#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
-#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
-#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
-#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
-#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
-#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
-#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
-#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
-#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
-#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
-#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
-#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
-#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
-#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
-#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
-#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
-#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
-#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
-#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
-#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
-#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
-#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
-#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
-#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
-#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
-#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
-#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
-#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
-#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
-#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
-#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
-#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
-#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
-#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
-#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
-#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
-#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
-#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
-
-/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
-#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
-
-#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
-#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
-#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
-#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
-#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
-#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
-#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
-#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
-#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
-#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
-#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
-#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
-#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
-#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
-#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
-#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
-
-/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
-#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
-
-#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
-#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
-#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
-#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
-#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
-#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
-#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
-#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
-#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
-#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
-#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
-#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
-#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
-#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
-#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
-#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
-
-/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
-    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
-    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
-    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
-    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
-    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
-    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
-    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
-    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
-    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
-    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
-    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
-    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
-    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
-    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
-    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
-    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
-    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
-    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
-#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
-#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
-#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
-#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
-#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
-#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
-#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
-#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
-#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
-#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
-#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
-#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
-#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
-#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
-#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
-#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
-#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
-#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
-#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
-#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
-#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
-#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
-#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
-#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
-#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
-#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
-#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
-#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
-#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
-#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
-#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
-#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
-#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
-#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
-#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
-#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
-#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
-#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
-#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
-#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
-#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
-#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
-#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
-#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
-#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
-
-/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
-#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
-
-#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
-#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
-#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
-#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
-#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
-#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
-#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
-#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
-#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
-#define   TCC_FCTRLA_BLANK_NONE_Val      0x0ul  /**< \brief (TCC_FCTRLA) No blanking applied */
-#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLA_BLANK_NONE      (TCC_FCTRLA_BLANK_NONE_Val    << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
-#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
-#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
-#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
-#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
-#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
-#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
-#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
-#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
-#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
-#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
-#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
-#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
-#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
-#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
-#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
-#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
-#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
-#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
-#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
-#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
-#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
-
-#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
-#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
-#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
-#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
-#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
-#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
-#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
-
-/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
-#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
-
-#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
-#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
-#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
-#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
-#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
-#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
-#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
-#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
-#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
-#define   TCC_FCTRLB_BLANK_NONE_Val      0x0ul  /**< \brief (TCC_FCTRLB) No blanking applied */
-#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLB_BLANK_NONE      (TCC_FCTRLB_BLANK_NONE_Val    << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
-#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
-#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
-#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
-#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
-#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
-#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
-#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
-#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
-#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
-#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
-#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
-#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
-#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
-#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
-#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
-#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
-#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
-#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
-#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
-#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
-#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
-
-#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
-
-#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
-#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
-#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
-#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
-#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
-#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
-#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
-
-/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
-    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
-    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
-    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
-    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
-    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WEXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
-#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
-
-#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
-#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
-#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
-#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
-#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
-#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
-#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
-#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
-#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
-#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
-#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
-#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
-#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
-#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
-#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
-#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
-#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
-#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
-#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
-#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
-#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
-
-/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
-    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
-    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
-    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
-    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
-    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
-    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
-    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
-    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
-    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
-    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
-    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
-    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
-    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
-    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
-    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
-    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
-    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
-    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
-    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
-    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
-    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
-    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
-    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
-    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
-    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
-    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
-    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
-#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
-
-#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
-#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
-#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
-#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
-#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
-#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
-#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
-#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
-#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
-#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
-#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
-#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
-#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
-#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
-#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
-#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
-#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
-#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
-#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
-#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
-#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
-#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
-#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
-#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
-#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
-#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
-#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
-#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
-#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
-#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
-#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
-#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
-#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
-#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
-#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
-#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
-#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
-#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
-#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
-#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
-#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
-#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
-#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
-#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
-#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
-#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
-#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
-#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
-#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
-#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
-#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
-#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
-#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
-#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
-#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
-#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
-#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
-#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
-#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
-#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
-#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
-#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
-
-/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
-#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
-
-#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
-#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
-#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
-#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
-#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
-
-/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
-    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
-    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
-    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
-    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
-    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
-    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
-    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
-    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
-    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
-    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
-    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
-    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
-    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
-    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
-    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
-    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
-    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
-#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
-
-#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
-#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
-#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
-#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
-#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
-
-#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
-
-#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
-#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
-#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
-#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
-#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
-#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
-#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
-#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
-#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
-#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
-#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
-#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
-#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
-#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
-#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
-#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
-#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
-#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
-#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
-#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
-#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
-#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
-#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
-#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
-#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
-#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
-#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
-#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
-#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
-#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
-#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
-#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
-#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
-#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
-#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
-#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
-#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
-#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
-#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
-#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
-#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
-#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
-#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
-#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
-#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
-#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
-#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
-#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
-#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
-#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
-#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
-#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
-#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
-#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
-#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
-
-/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :7;               /*!< bit:  4..10  Reserved                           */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
-#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
-#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
-#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
-#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
-#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
-#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
-#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
-#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
-#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
-#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
-#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
-#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
-#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
-#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
-#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
-#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
-#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
-#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
-#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
-#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
-
-/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :7;               /*!< bit:  4..10  Reserved                           */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
-#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
-#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
-#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
-#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
-#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
-#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
-#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
-#define TCC_INTENSET_ERR            (0x1ul  << TCC_INTENSET_ERR_Pos)
-#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
-#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
-#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
-#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
-#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
-#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
-#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
-#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
-#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
-#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
-#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
-#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
-
-/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
-    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
-    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
-    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
-    __I uint32_t :7;               /*!< bit:  4..10  Reserved                           */
-    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
-    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
-    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
-    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
-    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
-    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
-    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
-    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
-    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
-    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
-    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
-#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
-#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
-#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
-#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
-#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
-#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
-#define TCC_INTFLAG_ERR             (0x1ul  << TCC_INTFLAG_ERR_Pos)
-#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
-#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
-#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
-#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
-#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
-#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
-#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
-#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
-#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
-#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
-#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
-#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
-#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
-#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
-#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
-#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
-#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
-#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
-#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
-#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
-#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
-#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
-
-/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
-    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
-    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
-    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
-    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
-    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
-    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
-    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
-    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
-    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
-    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
-    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
-    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
-    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
-    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
-    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
-    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
-#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
-
-#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
-#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
-#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
-#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
-#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
-#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
-#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
-#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
-#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
-#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
-#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
-#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
-#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
-#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
-#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
-#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
-#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
-#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
-#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
-#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
-#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
-#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
-#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
-#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
-#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
-#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
-#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
-#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
-#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
-#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
-#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
-#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
-#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
-#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
-#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
-#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
-#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
-#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
-#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
-#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
-#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
-#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
-#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
-#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
-#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
-#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
-#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
-#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
-#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
-#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
-#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
-#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
-#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
-
-/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
-#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
-
-// DITH4 mode
-#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
-#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
-#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
-#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
-#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
-#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
-#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
-#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
-#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
-#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
-
-#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
-#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
-#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
-#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
-
-/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
-    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
-    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
-    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
-    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
-    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
-    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
-    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
-    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
-    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
-    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
-    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
-    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
-    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
-    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
-    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
-    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
-#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
-
-#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
-#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
-#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
-#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
-#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
-#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
-#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
-#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
-#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
-#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
-#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
-#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
-#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
-#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
-#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
-#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
-#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
-#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
-#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
-#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
-#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
-#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
-#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
-#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
-#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
-#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
-#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
-#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
-#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
-#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
-#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
-#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
-#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
-#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
-#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
-#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
-#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
-#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
-#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
-
-/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
-    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
-    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
-    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
-    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
-    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
-    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
-    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
-    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
-    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
-    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
-#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
-
-#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
-#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
-#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
-#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
-#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
-#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
-#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
-#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
-#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
-#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
-
-#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
-#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
-#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
-#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
-#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
-#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
-#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
-#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
-#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
-#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
-#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
-#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
-#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
-#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
-#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
-#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
-#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
-#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
-#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
-#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
-#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
-#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
-#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
-#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
-#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
-#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
-#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
-#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
-#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
-#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
-#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
-#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
-#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
-#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
-#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
-#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
-
-/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
-#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
-
-// DITH4 mode
-#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
-#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
-#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
-#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
-#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
-#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
-#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
-#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
-#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
-#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
-#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
-#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
-#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
-#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
-#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
-#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
-#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
-#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
-#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
-
-#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
-#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
-#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
-#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
-
-/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
-#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
-
-// DITH4 mode
-#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
-#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
-#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
-#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
-#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
-#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
-#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
-#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
-#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
-#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
-#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
-#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
-#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
-#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
-#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
-#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
-#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
-#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
-#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
-
-#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
-#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
-#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
-#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
-
-/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
-    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
-    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
-    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
-    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
-    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
-    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
-    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
-    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
-    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
-    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
-    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
-    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
-    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
-    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
-    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
-    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATTB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
-#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
-
-#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
-#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
-#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
-#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
-#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
-#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
-#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
-#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
-#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
-#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
-#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
-#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
-#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
-#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
-#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
-#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
-#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
-#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
-#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
-#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
-#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
-#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
-#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
-#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
-#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
-#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
-#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
-#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
-#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
-#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
-#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
-#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
-#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
-#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
-#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
-#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
-#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
-#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
-#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
-
-/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
-    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
-    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
-    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
-    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
-    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
-    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
-    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
-    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
-    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
-    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVEB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
-#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
-
-#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
-#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
-#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
-#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
-#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
-#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
-#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
-#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
-#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
-#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
-#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
-
-#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
-#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
-
-#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
-#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
-#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
-#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
-#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
-#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
-#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
-#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
-#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
-#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
-#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
-#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
-#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
-#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
-#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
-#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
-#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
-#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
-#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
-#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
-#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
-#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
-#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
-#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
-#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
-#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
-#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
-#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
-#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
-#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
-#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
-#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
-#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
-#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
-#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
-#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
-
-/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PERB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
-#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
-
-// DITH4 mode
-#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
-#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
-#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
-#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
-#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
-#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
-#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
-#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
-#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
-#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
-#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
-#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
-#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
-#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
-#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
-#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
-#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
-
-#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
-#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
-#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
-#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
-
-/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CCB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
-#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
-
-// DITH4 mode
-#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
-#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
-#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
-#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
-#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
-#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
-#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
-#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
-#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
-#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
-#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
-#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
-#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
-#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
-
-#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
-#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
-#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
-#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
-
-/** \brief TCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-       RoReg8                    Reserved1[0x2];
-  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
-  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
-  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
-  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
-  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
-       RoReg8                    Reserved2[0x2];
-  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
-       RoReg8                    Reserved3[0x1];
-  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
-  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
-  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
-  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
-  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
-  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
-  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
-       RoReg8                    Reserved4[0x2];
-  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
-  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
-  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
-       RoReg8                    Reserved5[0x10];
-  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
-       RoReg8                    Reserved6[0x2];
-  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
-  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
-  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
-} Tcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_TCC_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x122
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   0x0ul  /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  0x1ul  /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  0x2ul  /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  0x3ul  /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    0x0ul  /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    0x1ul  /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    0x2ul  /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    0x3ul  /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   0x4ul  /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   0x5ul  /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  0x6ul  /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul  /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    0x0ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   0x1ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  0x2ul  /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           0xFFul       /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     0x00ul       /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul  /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     0x1ul  /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   0x2ul  /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    0x3ul  /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       0x0ul  /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  0x1ul  /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       0x2ul  /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     0x3ul  /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   0x4ul  /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           0xFFul       /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
+    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
+    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
+    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
+    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
+    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
+    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
+    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
+    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER            (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB          (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB          (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB           (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk        (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK           0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_NONE_Val      0x0ul  /**< \brief (TCC_FCTRLA) No blanking applied */
+#define   TCC_FCTRLA_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_NONE      (TCC_FCTRLA_BLANK_NONE_Val    << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      0x0ul  /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       0x1ul  /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       0x2ul  /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     0x3ul  /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_NONE_Val      0x0ul  /**< \brief (TCC_FCTRLB) No blanking applied */
+#define   TCC_FCTRLB_BLANK_RISE_Val       0x1ul  /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       0x2ul  /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       0x3ul  /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_NONE      (TCC_FCTRLB_BLANK_NONE_Val    << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     0x0ul  /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          0x1ul  /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          0x2ul  /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          0x3ul  /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        0x0ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        0x1ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        0x2ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        0x3ul  /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  0x0ul  /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     0x1ul  /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  0x2ul  /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  0x3ul  /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   0x4ul  /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   0x5ul  /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   0x6ul  /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            0x05ul       /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   0x2ul  /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     0x3ul  /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     0x5ul  /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       0x0ul  /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul  /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       0x2ul  /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      0x3ul  /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       0x4ul  /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       0x5ul  /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       0x6ul  /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     0x7ul  /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     0x0ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       0x1ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   0x2ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  0x3ul  /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :7;               /*!< bit:  4..10  Reserved                           */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :7;               /*!< bit:  4..10  Reserved                           */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (0x1ul  << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :7;               /*!< bit:  4..10  Reserved                           */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (0x1ul  << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
+    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV           (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV           (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV            (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk         (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         0x0000ul     /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               0xFFFFul     /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       0x0ul  /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       0x1ul  /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       0x2ul  /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   0x5ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     0x6ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      0x7ul  /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         0x0ul  /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        0x1ul  /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         0x2ul  /**< \brief (TCC_WAVE) RAMP2 operation */
+
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE        0x0000ul     /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk          (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk          (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK              0xFFFFul     /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
+    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
+    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
+    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
+    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
+    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
+    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
+    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
+    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
+    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
+    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE        0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk      (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     0x0ul  /**< \brief (TCC_WAVEB) Normal frequency */
+#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     0x1ul  /**< \brief (TCC_WAVEB) Match frequency */
+#define   TCC_WAVEB_WAVEGENB_NPWM_Val     0x2ul  /**< \brief (TCC_WAVEB) Normal PWM */
+#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul  /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   0x6ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    0x7ul  /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk         (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define   TCC_WAVEB_RAMPB_RAMP1_Val       0x0ul  /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2A_Val      0x1ul  /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2_Val       0x2ul  /**< \brief (TCC_WAVEB) RAMP2 operation */
+
+#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
+
+#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB          (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk       (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk          (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk         (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK              0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk     (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk     (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk     (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk           (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK               0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk       (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk       (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk       (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk             (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK                0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x10];
+  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x2];
+  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h
index 6713630..4a879e4 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h
@@ -1,1795 +1,1795 @@
-/**
- * \file
- *
- * \brief Component description for USB
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_USB_COMPONENT_
-#define _SAMD21_USB_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR USB */
-/* ========================================================================== */
-/** \addtogroup SAMD21_USB Universal Serial Bus */
-/*@{*/
-
-#define USB_U2222
-#define REV_USB                     0x103
-
-/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby Mode                */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  MODE:1;           /*!< bit:      7  Operating Mode                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_CTRLA_OFFSET            0x000        /**< \brief (USB_CTRLA offset) Control A */
-#define USB_CTRLA_RESETVALUE        0x00ul       /**< \brief (USB_CTRLA reset_value) Control A */
-
-#define USB_CTRLA_SWRST_Pos         0            /**< \brief (USB_CTRLA) Software Reset */
-#define USB_CTRLA_SWRST             (0x1ul << USB_CTRLA_SWRST_Pos)
-#define USB_CTRLA_ENABLE_Pos        1            /**< \brief (USB_CTRLA) Enable */
-#define USB_CTRLA_ENABLE            (0x1ul << USB_CTRLA_ENABLE_Pos)
-#define USB_CTRLA_RUNSTDBY_Pos      2            /**< \brief (USB_CTRLA) Run in Standby Mode */
-#define USB_CTRLA_RUNSTDBY          (0x1ul << USB_CTRLA_RUNSTDBY_Pos)
-#define USB_CTRLA_MODE_Pos          7            /**< \brief (USB_CTRLA) Operating Mode */
-#define USB_CTRLA_MODE              (0x1ul << USB_CTRLA_MODE_Pos)
-#define   USB_CTRLA_MODE_DEVICE_Val       0x0ul  /**< \brief (USB_CTRLA) Device Mode */
-#define   USB_CTRLA_MODE_HOST_Val         0x1ul  /**< \brief (USB_CTRLA) Host Mode */
-#define USB_CTRLA_MODE_DEVICE       (USB_CTRLA_MODE_DEVICE_Val     << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MODE_HOST         (USB_CTRLA_MODE_HOST_Val       << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MASK              0x87ul       /**< \brief (USB_CTRLA) MASK Register */
-
-/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/   8) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_SYNCBUSY_OFFSET         0x002        /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
-#define USB_SYNCBUSY_RESETVALUE     0x00ul       /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
-
-#define USB_SYNCBUSY_SWRST_Pos      0            /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
-#define USB_SYNCBUSY_SWRST          (0x1ul << USB_SYNCBUSY_SWRST_Pos)
-#define USB_SYNCBUSY_ENABLE_Pos     1            /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
-#define USB_SYNCBUSY_ENABLE         (0x1ul << USB_SYNCBUSY_ENABLE_Pos)
-#define USB_SYNCBUSY_MASK           0x03ul       /**< \brief (USB_SYNCBUSY) MASK Register */
-
-/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W  8) USB Quality Of Service -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CQOS:2;           /*!< bit:  0.. 1  Configuration Quality of Service   */
-    uint8_t  DQOS:2;           /*!< bit:  2.. 3  Data Quality of Service            */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_QOSCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_QOSCTRL_OFFSET          0x003        /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
-#define USB_QOSCTRL_RESETVALUE      0x05ul       /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
-
-#define USB_QOSCTRL_CQOS_Pos        0            /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
-#define USB_QOSCTRL_CQOS_Msk        (0x3ul << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_CQOS(value)     (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
-#define   USB_QOSCTRL_CQOS_DISABLE_Val    0x0ul  /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
-#define   USB_QOSCTRL_CQOS_LOW_Val        0x1ul  /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
-#define   USB_QOSCTRL_CQOS_MEDIUM_Val     0x2ul  /**< \brief (USB_QOSCTRL) Sensitive Latency */
-#define   USB_QOSCTRL_CQOS_HIGH_Val       0x3ul  /**< \brief (USB_QOSCTRL) Critical Latency */
-#define USB_QOSCTRL_CQOS_DISABLE    (USB_QOSCTRL_CQOS_DISABLE_Val  << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_CQOS_LOW        (USB_QOSCTRL_CQOS_LOW_Val      << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_CQOS_MEDIUM     (USB_QOSCTRL_CQOS_MEDIUM_Val   << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_CQOS_HIGH       (USB_QOSCTRL_CQOS_HIGH_Val     << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_DQOS_Pos        2            /**< \brief (USB_QOSCTRL) Data Quality of Service */
-#define USB_QOSCTRL_DQOS_Msk        (0x3ul << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_DQOS(value)     (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
-#define   USB_QOSCTRL_DQOS_DISABLE_Val    0x0ul  /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
-#define   USB_QOSCTRL_DQOS_LOW_Val        0x1ul  /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
-#define   USB_QOSCTRL_DQOS_MEDIUM_Val     0x2ul  /**< \brief (USB_QOSCTRL) Sensitive Latency */
-#define   USB_QOSCTRL_DQOS_HIGH_Val       0x3ul  /**< \brief (USB_QOSCTRL) Critical Latency */
-#define USB_QOSCTRL_DQOS_DISABLE    (USB_QOSCTRL_DQOS_DISABLE_Val  << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_DQOS_LOW        (USB_QOSCTRL_DQOS_LOW_Val      << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_DQOS_MEDIUM     (USB_QOSCTRL_DQOS_MEDIUM_Val   << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_DQOS_HIGH       (USB_QOSCTRL_DQOS_HIGH_Val     << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_MASK            0x0Ful       /**< \brief (USB_QOSCTRL) MASK Register */
-
-/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DETACH:1;         /*!< bit:      0  Detach                             */
-    uint16_t UPRSM:1;          /*!< bit:      1  Upstream Resume                    */
-    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration                */
-    uint16_t NREPLY:1;         /*!< bit:      4  No Reply                           */
-    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
-    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
-    uint16_t TSTPCKT:1;        /*!< bit:      7  Test packet mode                   */
-    uint16_t OPMODE2:1;        /*!< bit:      8  Specific Operational Mode          */
-    uint16_t GNAK:1;           /*!< bit:      9  Global NAK                         */
-    uint16_t LPMHDSK:2;        /*!< bit: 10..11  Link Power Management Handshake    */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_CTRLB_OFFSET     0x008        /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
-#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul     /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
-
-#define USB_DEVICE_CTRLB_DETACH_Pos 0            /**< \brief (USB_DEVICE_CTRLB) Detach */
-#define USB_DEVICE_CTRLB_DETACH     (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos)
-#define USB_DEVICE_CTRLB_UPRSM_Pos  1            /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
-#define USB_DEVICE_CTRLB_UPRSM      (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_Pos 2            /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
-#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
-#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul  /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
-#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul  /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
-#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul  /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
-#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul  /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
-#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_NREPLY_Pos 4            /**< \brief (USB_DEVICE_CTRLB) No Reply */
-#define USB_DEVICE_CTRLB_NREPLY     (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos)
-#define USB_DEVICE_CTRLB_TSTJ_Pos   5            /**< \brief (USB_DEVICE_CTRLB) Test mode J */
-#define USB_DEVICE_CTRLB_TSTJ       (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos)
-#define USB_DEVICE_CTRLB_TSTK_Pos   6            /**< \brief (USB_DEVICE_CTRLB) Test mode K */
-#define USB_DEVICE_CTRLB_TSTK       (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos)
-#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7            /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
-#define USB_DEVICE_CTRLB_TSTPCKT    (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos)
-#define USB_DEVICE_CTRLB_OPMODE2_Pos 8            /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
-#define USB_DEVICE_CTRLB_OPMODE2    (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos)
-#define USB_DEVICE_CTRLB_GNAK_Pos   9            /**< \brief (USB_DEVICE_CTRLB) Global NAK */
-#define USB_DEVICE_CTRLB_GNAK       (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10           /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
-#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
-#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul  /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
-#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul  /**< \brief (USB_DEVICE_CTRLB) ACK */
-#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul  /**< \brief (USB_DEVICE_CTRLB) NYET */
-#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul  /**< \brief (USB_DEVICE_CTRLB) STALL */
-#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_MASK       0x0FFFul     /**< \brief (USB_DEVICE_CTRLB) MASK Register */
-
-/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :1;               /*!< bit:      0  Reserved                           */
-    uint16_t RESUME:1;         /*!< bit:      1  Send USB Resume                    */
-    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration for Host       */
-    uint16_t :1;               /*!< bit:      4  Reserved                           */
-    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
-    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t SOFE:1;           /*!< bit:      8  Start of Frame Generation Enable   */
-    uint16_t BUSRESET:1;       /*!< bit:      9  Send USB Reset                     */
-    uint16_t VBUSOK:1;         /*!< bit:     10  VBUS is OK                         */
-    uint16_t L1RESUME:1;       /*!< bit:     11  Send L1 Resume                     */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_CTRLB_OFFSET       0x008        /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
-#define USB_HOST_CTRLB_RESETVALUE   0x0000ul     /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
-
-#define USB_HOST_CTRLB_RESUME_Pos   1            /**< \brief (USB_HOST_CTRLB) Send USB Resume */
-#define USB_HOST_CTRLB_RESUME       (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
-#define USB_HOST_CTRLB_SPDCONF_Pos  2            /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
-#define USB_HOST_CTRLB_SPDCONF_Msk  (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
-#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul  /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
-#define   USB_HOST_CTRLB_SPDCONF_FS_Val   0x3ul  /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
-#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_SPDCONF_FS   (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_TSTJ_Pos     5            /**< \brief (USB_HOST_CTRLB) Test mode J */
-#define USB_HOST_CTRLB_TSTJ         (0x1ul << USB_HOST_CTRLB_TSTJ_Pos)
-#define USB_HOST_CTRLB_TSTK_Pos     6            /**< \brief (USB_HOST_CTRLB) Test mode K */
-#define USB_HOST_CTRLB_TSTK         (0x1ul << USB_HOST_CTRLB_TSTK_Pos)
-#define USB_HOST_CTRLB_SOFE_Pos     8            /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
-#define USB_HOST_CTRLB_SOFE         (0x1ul << USB_HOST_CTRLB_SOFE_Pos)
-#define USB_HOST_CTRLB_BUSRESET_Pos 9            /**< \brief (USB_HOST_CTRLB) Send USB Reset */
-#define USB_HOST_CTRLB_BUSRESET     (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos)
-#define USB_HOST_CTRLB_VBUSOK_Pos   10           /**< \brief (USB_HOST_CTRLB) VBUS is OK */
-#define USB_HOST_CTRLB_VBUSOK       (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos)
-#define USB_HOST_CTRLB_L1RESUME_Pos 11           /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
-#define USB_HOST_CTRLB_L1RESUME     (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos)
-#define USB_HOST_CTRLB_MASK         0x0F6Eul     /**< \brief (USB_HOST_CTRLB) MASK Register */
-
-/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE Device Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DADD:7;           /*!< bit:  0.. 6  Device Address                     */
-    uint8_t  ADDEN:1;          /*!< bit:      7  Device Address Enable              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_DADD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_DADD_OFFSET      0x00A        /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
-#define USB_DEVICE_DADD_RESETVALUE  0x00ul       /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
-
-#define USB_DEVICE_DADD_DADD_Pos    0            /**< \brief (USB_DEVICE_DADD) Device Address */
-#define USB_DEVICE_DADD_DADD_Msk    (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
-#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
-#define USB_DEVICE_DADD_ADDEN_Pos   7            /**< \brief (USB_DEVICE_DADD) Device Address Enable */
-#define USB_DEVICE_DADD_ADDEN       (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
-#define USB_DEVICE_DADD_MASK        0xFFul       /**< \brief (USB_DEVICE_DADD) MASK Register */
-
-/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W  8) HOST HOST Host Start Of Frame Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLENC:4;          /*!< bit:  0.. 3  Frame Length Control               */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  FLENCE:1;         /*!< bit:      7  Frame Length Control Enable        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_HSOFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_HSOFC_OFFSET       0x00A        /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
-#define USB_HOST_HSOFC_RESETVALUE   0x00ul       /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
-
-#define USB_HOST_HSOFC_FLENC_Pos    0            /**< \brief (USB_HOST_HSOFC) Frame Length Control */
-#define USB_HOST_HSOFC_FLENC_Msk    (0xFul << USB_HOST_HSOFC_FLENC_Pos)
-#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
-#define USB_HOST_HSOFC_FLENCE_Pos   7            /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
-#define USB_HOST_HSOFC_FLENCE       (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
-#define USB_HOST_HSOFC_MASK         0x8Ful       /**< \brief (USB_HOST_HSOFC) MASK Register */
-
-/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/   8) DEVICE DEVICE Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
-    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_STATUS_OFFSET    0x00C        /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
-#define USB_DEVICE_STATUS_RESETVALUE 0x40ul       /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
-
-#define USB_DEVICE_STATUS_SPEED_Pos 2            /**< \brief (USB_DEVICE_STATUS) Speed Status */
-#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
-#define   USB_DEVICE_STATUS_SPEED_FS_Val  0x0ul  /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
-#define   USB_DEVICE_STATUS_SPEED_HS_Val  0x1ul  /**< \brief (USB_DEVICE_STATUS) High-speed mode */
-#define   USB_DEVICE_STATUS_SPEED_LS_Val  0x2ul  /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
-#define USB_DEVICE_STATUS_SPEED_FS  (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED_HS  (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED_LS  (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_Pos 6            /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
-#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
-#define   USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul  /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
-#define   USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul  /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
-#define   USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul  /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
-#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_MASK      0xCCul       /**< \brief (USB_DEVICE_STATUS) MASK Register */
-
-/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W  8) HOST HOST Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
-    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_OFFSET      0x00C        /**< \brief (USB_HOST_STATUS offset) HOST Status */
-#define USB_HOST_STATUS_RESETVALUE  0x00ul       /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
-
-#define USB_HOST_STATUS_SPEED_Pos   2            /**< \brief (USB_HOST_STATUS) Speed Status */
-#define USB_HOST_STATUS_SPEED_Msk   (0x3ul << USB_HOST_STATUS_SPEED_Pos)
-#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
-#define USB_HOST_STATUS_LINESTATE_Pos 6            /**< \brief (USB_HOST_STATUS) USB Line State Status */
-#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
-#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
-#define USB_HOST_STATUS_MASK        0xCCul       /**< \brief (USB_HOST_STATUS) MASK Register */
-
-/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/   8) Finite State Machine Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FSMSTATE:7;       /*!< bit:  0.. 6  Fine State Machine Status          */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_FSMSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_FSMSTATUS_OFFSET        0x00D        /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
-#define USB_FSMSTATUS_RESETVALUE    0x01ul       /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
-
-#define USB_FSMSTATUS_FSMSTATE_Pos  0            /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
-#define USB_FSMSTATUS_FSMSTATE_Msk  (0x7Ful << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
-#define   USB_FSMSTATUS_FSMSTATE_OFF_Val  0x1ul  /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
-#define   USB_FSMSTATUS_FSMSTATE_ON_Val   0x2ul  /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
-#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul  /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
-#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul  /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
-#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul  /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
-#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul  /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
-#define   USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul  /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
-#define USB_FSMSTATUS_FSMSTATE_OFF  (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_ON   (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_MASK          0x7Ful       /**< \brief (USB_FSMSTATUS) MASK Register */
-
-/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/  16) DEVICE DEVICE Device Frame Number -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
-    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
-    uint16_t :1;               /*!< bit:     14  Reserved                           */
-    uint16_t FNCERR:1;         /*!< bit:     15  Frame Number CRC Error             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_FNUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_FNUM_OFFSET      0x010        /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
-#define USB_DEVICE_FNUM_RESETVALUE  0x0000ul     /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
-
-#define USB_DEVICE_FNUM_MFNUM_Pos   0            /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
-#define USB_DEVICE_FNUM_MFNUM_Msk   (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
-#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
-#define USB_DEVICE_FNUM_FNUM_Pos    3            /**< \brief (USB_DEVICE_FNUM) Frame Number */
-#define USB_DEVICE_FNUM_FNUM_Msk    (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
-#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
-#define USB_DEVICE_FNUM_FNCERR_Pos  15           /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
-#define USB_DEVICE_FNUM_FNCERR      (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
-#define USB_DEVICE_FNUM_MASK        0xBFFFul     /**< \brief (USB_DEVICE_FNUM) MASK Register */
-
-/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
-    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_FNUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_FNUM_OFFSET        0x010        /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
-#define USB_HOST_FNUM_RESETVALUE    0x0000ul     /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
-
-#define USB_HOST_FNUM_MFNUM_Pos     0            /**< \brief (USB_HOST_FNUM) Micro Frame Number */
-#define USB_HOST_FNUM_MFNUM_Msk     (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
-#define USB_HOST_FNUM_MFNUM(value)  (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
-#define USB_HOST_FNUM_FNUM_Pos      3            /**< \brief (USB_HOST_FNUM) Frame Number */
-#define USB_HOST_FNUM_FNUM_Msk      (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
-#define USB_HOST_FNUM_FNUM(value)   (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
-#define USB_HOST_FNUM_MASK          0x3FFFul     /**< \brief (USB_HOST_FNUM) MASK Register */
-
-/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/   8) HOST HOST Host Frame Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLENHIGH:8;       /*!< bit:  0.. 7  Frame Length                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_FLENHIGH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_FLENHIGH_OFFSET    0x012        /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
-#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul       /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
-
-#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0            /**< \brief (USB_HOST_FLENHIGH) Frame Length */
-#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
-#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
-#define USB_HOST_FLENHIGH_MASK      0xFFul       /**< \brief (USB_HOST_FLENHIGH) MASK Register */
-
-/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
-    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
-    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
-    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
-    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
-    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
-    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTENCLR_OFFSET  0x014        /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
-#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
-
-#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
-#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos)
-#define USB_DEVICE_INTENCLR_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
-#define USB_DEVICE_INTENCLR_MSOF    (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos)
-#define USB_DEVICE_INTENCLR_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
-#define USB_DEVICE_INTENCLR_SOF     (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos)
-#define USB_DEVICE_INTENCLR_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
-#define USB_DEVICE_INTENCLR_EORST   (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos)
-#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
-#define USB_DEVICE_INTENCLR_WAKEUP  (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos)
-#define USB_DEVICE_INTENCLR_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
-#define USB_DEVICE_INTENCLR_EORSM   (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos)
-#define USB_DEVICE_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
-#define USB_DEVICE_INTENCLR_UPRSM   (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos)
-#define USB_DEVICE_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
-#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos)
-#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
-#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos)
-#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
-#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
-#define USB_DEVICE_INTENCLR_MASK    0x03FFul     /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
-
-/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Disable */
-    uint16_t RST:1;            /*!< bit:      3  BUS Reset Interrupt Disable        */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Disable          */
-    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to Device Interrupt Disable */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from Device Interrupt Disable */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Disable       */
-    uint16_t DCONN:1;          /*!< bit:      8  Device Connection Interrupt Disable */
-    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Disable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTENCLR_OFFSET    0x014        /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
-#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
-
-#define USB_HOST_INTENCLR_HSOF_Pos  2            /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
-#define USB_HOST_INTENCLR_HSOF      (0x1ul << USB_HOST_INTENCLR_HSOF_Pos)
-#define USB_HOST_INTENCLR_RST_Pos   3            /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
-#define USB_HOST_INTENCLR_RST       (0x1ul << USB_HOST_INTENCLR_RST_Pos)
-#define USB_HOST_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
-#define USB_HOST_INTENCLR_WAKEUP    (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos)
-#define USB_HOST_INTENCLR_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
-#define USB_HOST_INTENCLR_DNRSM     (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos)
-#define USB_HOST_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
-#define USB_HOST_INTENCLR_UPRSM     (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos)
-#define USB_HOST_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
-#define USB_HOST_INTENCLR_RAMACER   (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos)
-#define USB_HOST_INTENCLR_DCONN_Pos 8            /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
-#define USB_HOST_INTENCLR_DCONN     (0x1ul << USB_HOST_INTENCLR_DCONN_Pos)
-#define USB_HOST_INTENCLR_DDISC_Pos 9            /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
-#define USB_HOST_INTENCLR_DDISC     (0x1ul << USB_HOST_INTENCLR_DDISC_Pos)
-#define USB_HOST_INTENCLR_MASK      0x03FCul     /**< \brief (USB_HOST_INTENCLR) MASK Register */
-
-/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
-    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
-    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
-    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
-    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
-    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
-    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTENSET_OFFSET  0x018        /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
-#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
-
-#define USB_DEVICE_INTENSET_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
-#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos)
-#define USB_DEVICE_INTENSET_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
-#define USB_DEVICE_INTENSET_MSOF    (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos)
-#define USB_DEVICE_INTENSET_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
-#define USB_DEVICE_INTENSET_SOF     (0x1ul << USB_DEVICE_INTENSET_SOF_Pos)
-#define USB_DEVICE_INTENSET_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
-#define USB_DEVICE_INTENSET_EORST   (0x1ul << USB_DEVICE_INTENSET_EORST_Pos)
-#define USB_DEVICE_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
-#define USB_DEVICE_INTENSET_WAKEUP  (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos)
-#define USB_DEVICE_INTENSET_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
-#define USB_DEVICE_INTENSET_EORSM   (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos)
-#define USB_DEVICE_INTENSET_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
-#define USB_DEVICE_INTENSET_UPRSM   (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos)
-#define USB_DEVICE_INTENSET_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
-#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos)
-#define USB_DEVICE_INTENSET_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
-#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos)
-#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
-#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos)
-#define USB_DEVICE_INTENSET_MASK    0x03FFul     /**< \brief (USB_DEVICE_INTENSET) MASK Register */
-
-/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Enable */
-    uint16_t RST:1;            /*!< bit:      3  Bus Reset Interrupt Enable         */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
-    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to the Device Interrupt Enable */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume fromthe device Interrupt Enable */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
-    uint16_t DCONN:1;          /*!< bit:      8  Link Power Management Interrupt Enable */
-    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Enable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTENSET_OFFSET    0x018        /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
-#define USB_HOST_INTENSET_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
-
-#define USB_HOST_INTENSET_HSOF_Pos  2            /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
-#define USB_HOST_INTENSET_HSOF      (0x1ul << USB_HOST_INTENSET_HSOF_Pos)
-#define USB_HOST_INTENSET_RST_Pos   3            /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
-#define USB_HOST_INTENSET_RST       (0x1ul << USB_HOST_INTENSET_RST_Pos)
-#define USB_HOST_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
-#define USB_HOST_INTENSET_WAKEUP    (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos)
-#define USB_HOST_INTENSET_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
-#define USB_HOST_INTENSET_DNRSM     (0x1ul << USB_HOST_INTENSET_DNRSM_Pos)
-#define USB_HOST_INTENSET_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
-#define USB_HOST_INTENSET_UPRSM     (0x1ul << USB_HOST_INTENSET_UPRSM_Pos)
-#define USB_HOST_INTENSET_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
-#define USB_HOST_INTENSET_RAMACER   (0x1ul << USB_HOST_INTENSET_RAMACER_Pos)
-#define USB_HOST_INTENSET_DCONN_Pos 8            /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
-#define USB_HOST_INTENSET_DCONN     (0x1ul << USB_HOST_INTENSET_DCONN_Pos)
-#define USB_HOST_INTENSET_DDISC_Pos 9            /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
-#define USB_HOST_INTENSET_DDISC     (0x1ul << USB_HOST_INTENSET_DDISC_Pos)
-#define USB_HOST_INTENSET_MASK      0x03FCul     /**< \brief (USB_HOST_INTENSET) MASK Register */
-
-/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
-    __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
-    __I uint16_t SOF:1;            /*!< bit:      2  Start Of Frame                     */
-    __I uint16_t EORST:1;          /*!< bit:      3  End of Reset                       */
-    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
-    __I uint16_t EORSM:1;          /*!< bit:      5  End Of Resume                      */
-    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume                    */
-    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
-    __I uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet      */
-    __I uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend      */
-    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTFLAG_OFFSET   0x01C        /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
-#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
-
-#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTFLAG) Suspend */
-#define USB_DEVICE_INTFLAG_SUSPEND  (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos)
-#define USB_DEVICE_INTFLAG_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
-#define USB_DEVICE_INTFLAG_MSOF     (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos)
-#define USB_DEVICE_INTFLAG_SOF_Pos  2            /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
-#define USB_DEVICE_INTFLAG_SOF      (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos)
-#define USB_DEVICE_INTFLAG_EORST_Pos 3            /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
-#define USB_DEVICE_INTFLAG_EORST    (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos)
-#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
-#define USB_DEVICE_INTFLAG_WAKEUP   (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos)
-#define USB_DEVICE_INTFLAG_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
-#define USB_DEVICE_INTFLAG_EORSM    (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos)
-#define USB_DEVICE_INTFLAG_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
-#define USB_DEVICE_INTFLAG_UPRSM    (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos)
-#define USB_DEVICE_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
-#define USB_DEVICE_INTFLAG_RAMACER  (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos)
-#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
-#define USB_DEVICE_INTFLAG_LPMNYET  (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos)
-#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
-#define USB_DEVICE_INTFLAG_LPMSUSP  (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
-#define USB_DEVICE_INTFLAG_MASK     0x03FFul     /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
-
-/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
-    __I uint16_t RST:1;            /*!< bit:      3  Bus Reset                          */
-    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
-    __I uint16_t DNRSM:1;          /*!< bit:      5  Downstream                         */
-    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from the Device    */
-    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
-    __I uint16_t DCONN:1;          /*!< bit:      8  Device Connection                  */
-    __I uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection               */
-    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTFLAG_OFFSET     0x01C        /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
-#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
-
-#define USB_HOST_INTFLAG_HSOF_Pos   2            /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
-#define USB_HOST_INTFLAG_HSOF       (0x1ul << USB_HOST_INTFLAG_HSOF_Pos)
-#define USB_HOST_INTFLAG_RST_Pos    3            /**< \brief (USB_HOST_INTFLAG) Bus Reset */
-#define USB_HOST_INTFLAG_RST        (0x1ul << USB_HOST_INTFLAG_RST_Pos)
-#define USB_HOST_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTFLAG) Wake Up */
-#define USB_HOST_INTFLAG_WAKEUP     (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos)
-#define USB_HOST_INTFLAG_DNRSM_Pos  5            /**< \brief (USB_HOST_INTFLAG) Downstream */
-#define USB_HOST_INTFLAG_DNRSM      (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos)
-#define USB_HOST_INTFLAG_UPRSM_Pos  6            /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
-#define USB_HOST_INTFLAG_UPRSM      (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos)
-#define USB_HOST_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_HOST_INTFLAG) Ram Access */
-#define USB_HOST_INTFLAG_RAMACER    (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos)
-#define USB_HOST_INTFLAG_DCONN_Pos  8            /**< \brief (USB_HOST_INTFLAG) Device Connection */
-#define USB_HOST_INTFLAG_DCONN      (0x1ul << USB_HOST_INTFLAG_DCONN_Pos)
-#define USB_HOST_INTFLAG_DDISC_Pos  9            /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
-#define USB_HOST_INTFLAG_DDISC      (0x1ul << USB_HOST_INTFLAG_DDISC_Pos)
-#define USB_HOST_INTFLAG_MASK       0x03FCul     /**< \brief (USB_HOST_INTFLAG) MASK Register */
-
-/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/  16) DEVICE DEVICE End Point Interrupt Summary -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EPINT0:1;         /*!< bit:      0  End Point 0 Interrupt              */
-    uint16_t EPINT1:1;         /*!< bit:      1  End Point 1 Interrupt              */
-    uint16_t EPINT2:1;         /*!< bit:      2  End Point 2 Interrupt              */
-    uint16_t EPINT3:1;         /*!< bit:      3  End Point 3 Interrupt              */
-    uint16_t EPINT4:1;         /*!< bit:      4  End Point 4 Interrupt              */
-    uint16_t EPINT5:1;         /*!< bit:      5  End Point 5 Interrupt              */
-    uint16_t EPINT6:1;         /*!< bit:      6  End Point 6 Interrupt              */
-    uint16_t EPINT7:1;         /*!< bit:      7  End Point 7 Interrupt              */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t EPINT:8;          /*!< bit:  0.. 7  End Point x Interrupt              */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_EPINTSMRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTSMRY_OFFSET 0x020        /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
-#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
-
-#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
-#define USB_DEVICE_EPINTSMRY_MASK   0x00FFul     /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
-
-/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/  16) HOST HOST Pipe Interrupt Summary -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EPINT0:1;         /*!< bit:      0  Pipe 0 Interrupt                   */
-    uint16_t EPINT1:1;         /*!< bit:      1  Pipe 1 Interrupt                   */
-    uint16_t EPINT2:1;         /*!< bit:      2  Pipe 2 Interrupt                   */
-    uint16_t EPINT3:1;         /*!< bit:      3  Pipe 3 Interrupt                   */
-    uint16_t EPINT4:1;         /*!< bit:      4  Pipe 4 Interrupt                   */
-    uint16_t EPINT5:1;         /*!< bit:      5  Pipe 5 Interrupt                   */
-    uint16_t EPINT6:1;         /*!< bit:      6  Pipe 6 Interrupt                   */
-    uint16_t EPINT7:1;         /*!< bit:      7  Pipe 7 Interrupt                   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t EPINT:8;          /*!< bit:  0.. 7  Pipe x Interrupt                   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_PINTSMRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTSMRY_OFFSET    0x020        /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
-#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
-
-#define USB_HOST_PINTSMRY_EPINT0_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT0    (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
-#define USB_HOST_PINTSMRY_EPINT1_Pos 1            /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT1    (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
-#define USB_HOST_PINTSMRY_EPINT2_Pos 2            /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT2    (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
-#define USB_HOST_PINTSMRY_EPINT3_Pos 3            /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT3    (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
-#define USB_HOST_PINTSMRY_EPINT4_Pos 4            /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT4    (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
-#define USB_HOST_PINTSMRY_EPINT5_Pos 5            /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT5    (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
-#define USB_HOST_PINTSMRY_EPINT6_Pos 6            /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT6    (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
-#define USB_HOST_PINTSMRY_EPINT7_Pos 7            /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT7    (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
-#define USB_HOST_PINTSMRY_EPINT_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
-#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
-#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
-#define USB_HOST_PINTSMRY_MASK      0x00FFul     /**< \brief (USB_HOST_PINTSMRY) MASK Register */
-
-/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DESCADD:32;       /*!< bit:  0..31  Descriptor Address Value           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_DESCADD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DESCADD_OFFSET          0x024        /**< \brief (USB_DESCADD offset) Descriptor Address */
-#define USB_DESCADD_RESETVALUE      0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */
-
-#define USB_DESCADD_DESCADD_Pos     0            /**< \brief (USB_DESCADD) Descriptor Address Value */
-#define USB_DESCADD_DESCADD_Msk     (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
-#define USB_DESCADD_DESCADD(value)  (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
-#define USB_DESCADD_MASK            0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
-
-/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t TRANSP:5;         /*!< bit:  0.. 4  USB Pad Transp calibration         */
-    uint16_t :1;               /*!< bit:      5  Reserved                           */
-    uint16_t TRANSN:5;         /*!< bit:  6..10  USB Pad Transn calibration         */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t TRIM:3;           /*!< bit: 12..14  USB Pad Trim calibration           */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_PADCAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_PADCAL_OFFSET           0x028        /**< \brief (USB_PADCAL offset) USB PAD Calibration */
-#define USB_PADCAL_RESETVALUE       0x0000ul     /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
-
-#define USB_PADCAL_TRANSP_Pos       0            /**< \brief (USB_PADCAL) USB Pad Transp calibration */
-#define USB_PADCAL_TRANSP_Msk       (0x1Ful << USB_PADCAL_TRANSP_Pos)
-#define USB_PADCAL_TRANSP(value)    (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
-#define USB_PADCAL_TRANSN_Pos       6            /**< \brief (USB_PADCAL) USB Pad Transn calibration */
-#define USB_PADCAL_TRANSN_Msk       (0x1Ful << USB_PADCAL_TRANSN_Pos)
-#define USB_PADCAL_TRANSN(value)    (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
-#define USB_PADCAL_TRIM_Pos         12           /**< \brief (USB_PADCAL) USB Pad Trim calibration */
-#define USB_PADCAL_TRIM_Msk         (0x7ul << USB_PADCAL_TRIM_Pos)
-#define USB_PADCAL_TRIM(value)      (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
-#define USB_PADCAL_MASK             0x77DFul     /**< \brief (USB_PADCAL) MASK Register */
-
-/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EPTYPE0:3;        /*!< bit:  0.. 2  End Point Type0                    */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  EPTYPE1:3;        /*!< bit:  4.. 6  End Point Type1                    */
-    uint8_t  NYETDIS:1;        /*!< bit:      7  NYET Token Disable                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPCFG_OFFSET     0x100        /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
-#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
-
-#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0            /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
-#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
-#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
-#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4            /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
-#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
-#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
-#define USB_DEVICE_EPCFG_NYETDIS_Pos 7            /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
-#define USB_DEVICE_EPCFG_NYETDIS    (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
-#define USB_DEVICE_EPCFG_MASK       0xF7ul       /**< \brief (USB_DEVICE_EPCFG) MASK Register */
-
-/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W  8) HOST HOST_PIPE End Point Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PTOKEN:2;         /*!< bit:  0.. 1  Pipe Token                         */
-    uint8_t  BK:1;             /*!< bit:      2  Pipe Bank                          */
-    uint8_t  PTYPE:3;          /*!< bit:  3.. 5  Pipe Type                          */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PCFG_OFFSET        0x100        /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
-#define USB_HOST_PCFG_RESETVALUE    0x00ul       /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
-
-#define USB_HOST_PCFG_PTOKEN_Pos    0            /**< \brief (USB_HOST_PCFG) Pipe Token */
-#define USB_HOST_PCFG_PTOKEN_Msk    (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
-#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
-#define USB_HOST_PCFG_BK_Pos        2            /**< \brief (USB_HOST_PCFG) Pipe Bank */
-#define USB_HOST_PCFG_BK            (0x1ul << USB_HOST_PCFG_BK_Pos)
-#define USB_HOST_PCFG_PTYPE_Pos     3            /**< \brief (USB_HOST_PCFG) Pipe Type */
-#define USB_HOST_PCFG_PTYPE_Msk     (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
-#define USB_HOST_PCFG_PTYPE(value)  (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
-#define USB_HOST_PCFG_MASK          0x3Ful       /**< \brief (USB_HOST_PCFG) MASK Register */
-
-/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W  8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BITINTERVAL:8;    /*!< bit:  0.. 7  Bit Interval                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_BINTERVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_BINTERVAL_OFFSET   0x103        /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
-#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul       /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
-
-#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0            /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
-#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
-#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
-#define USB_HOST_BINTERVAL_MASK     0xFFul       /**< \brief (USB_HOST_BINTERVAL) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Clear              */
-    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Clear               */
-    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank Clear                  */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Clear              */
-    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Clear              */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Clear              */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPSTATUSCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104        /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
-#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
-
-#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
-#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
-#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
-#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
-#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
-#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul       /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
-
-/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W  8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle clear                  */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank clear                  */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Clear                  */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PSTATUSCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUSCLR_OFFSET  0x104        /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
-#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
-
-#define USB_HOST_PSTATUSCLR_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
-#define USB_HOST_PSTATUSCLR_DTGL    (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos)
-#define USB_HOST_PSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
-#define USB_HOST_PSTATUSCLR_CURBK   (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos)
-#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
-#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
-#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
-#define USB_HOST_PSTATUSCLR_BK0RDY  (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
-#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
-#define USB_HOST_PSTATUSCLR_BK1RDY  (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
-#define USB_HOST_PSTATUSCLR_MASK    0xD5ul       /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Set                */
-    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Set                 */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Set                */
-    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Set                */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Set                */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPSTATUSSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105        /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
-#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
-
-#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
-#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
-#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
-#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
-#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
-#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul       /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
-
-/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W  8) HOST HOST_PIPE End Point Pipe Status Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle Set                    */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Set                    */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PSTATUSSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUSSET_OFFSET  0x105        /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
-#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
-
-#define USB_HOST_PSTATUSSET_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
-#define USB_HOST_PSTATUSSET_DTGL    (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos)
-#define USB_HOST_PSTATUSSET_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
-#define USB_HOST_PSTATUSSET_CURBK   (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos)
-#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
-#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos)
-#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
-#define USB_HOST_PSTATUSSET_BK0RDY  (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos)
-#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
-#define USB_HOST_PSTATUSSET_BK1RDY  (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos)
-#define USB_HOST_PSTATUSSET_MASK    0xD5ul       /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/   8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle Out                    */
-    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle In                     */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request                    */
-    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request                    */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request                    */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUS_OFFSET  0x106        /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
-#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
-
-#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
-#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
-#define USB_DEVICE_EPSTATUS_DTGLIN  (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUS_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
-#define USB_DEVICE_EPSTATUS_CURBK   (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
-#define USB_DEVICE_EPSTATUS_BK0RDY  (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
-#define USB_DEVICE_EPSTATUS_BK1RDY  (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUS_MASK    0xF7ul       /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
-
-/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/   8) HOST HOST_PIPE End Point Pipe Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle                        */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze                        */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUS_OFFSET     0x106        /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
-#define USB_HOST_PSTATUS_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
-
-#define USB_HOST_PSTATUS_DTGL_Pos   0            /**< \brief (USB_HOST_PSTATUS) Data Toggle */
-#define USB_HOST_PSTATUS_DTGL       (0x1ul << USB_HOST_PSTATUS_DTGL_Pos)
-#define USB_HOST_PSTATUS_CURBK_Pos  2            /**< \brief (USB_HOST_PSTATUS) Current Bank */
-#define USB_HOST_PSTATUS_CURBK      (0x1ul << USB_HOST_PSTATUS_CURBK_Pos)
-#define USB_HOST_PSTATUS_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
-#define USB_HOST_PSTATUS_PFREEZE    (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos)
-#define USB_HOST_PSTATUS_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
-#define USB_HOST_PSTATUS_BK0RDY     (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos)
-#define USB_HOST_PSTATUS_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
-#define USB_HOST_PSTATUS_BK1RDY     (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos)
-#define USB_HOST_PSTATUS_MASK       0xD5ul       /**< \brief (USB_HOST_PSTATUS) MASK Register */
-
-/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
-    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
-    __I uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0                       */
-    __I uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1                       */
-    __I uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup                     */
-    __I uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out                     */
-    __I uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out                     */
-    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x                */
-    __I uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x                       */
-    __I uint8_t  :1;               /*!< bit:      4  Reserved                           */
-    __I uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out                     */
-    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTFLAG_OFFSET 0x107        /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
-#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
-
-#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
-#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
-#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
-#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
-#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
-#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
-#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
-#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
-#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
-#define USB_DEVICE_EPINTFLAG_RXSTP  (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
-#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
-#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
-#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
-#define USB_DEVICE_EPINTFLAG_MASK   0x7Ful       /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
-
-/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
-    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
-    __I uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Flag          */
-    __I uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Flag          */
-    __I uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Flag     */
-    __I uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Flag               */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Flag */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTFLAG_OFFSET    0x107        /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
-#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
-
-#define USB_HOST_PINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT0    (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
-#define USB_HOST_PINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT1    (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
-#define USB_HOST_PINTFLAG_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
-#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
-#define USB_HOST_PINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRFAIL    (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
-#define USB_HOST_PINTFLAG_PERR_Pos  3            /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
-#define USB_HOST_PINTFLAG_PERR      (0x1ul << USB_HOST_PINTFLAG_PERR_Pos)
-#define USB_HOST_PINTFLAG_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag */
-#define USB_HOST_PINTFLAG_TXSTP     (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos)
-#define USB_HOST_PINTFLAG_STALL_Pos 5            /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
-#define USB_HOST_PINTFLAG_STALL     (0x1ul << USB_HOST_PINTFLAG_STALL_Pos)
-#define USB_HOST_PINTFLAG_MASK      0x3Ful       /**< \brief (USB_HOST_PINTFLAG) MASK Register */
-
-/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Disable */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Disable */
-    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Disable     */
-    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Disable     */
-    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Disable   */
-    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/Out Interrupt Disable   */
-    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/Out Interrupt Disable   */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Disable */
-    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Disable     */
-    uint8_t  :1;               /*!< bit:      4  Reserved                           */
-    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/Out Interrupt Disable   */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTENCLR_OFFSET 0x108        /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-
-#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
-#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
-#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
-#define USB_DEVICE_EPINTENCLR_MASK  0x7Ful       /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
-
-/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Disable        */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Disable        */
-    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Disable       */
-    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Disable       */
-    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Disable  */
-    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Disable            */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Disable        */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTENCLR_OFFSET   0x108        /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
-#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
-
-#define USB_HOST_PINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
-#define USB_HOST_PINTENCLR_TRCPT0   (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
-#define USB_HOST_PINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
-#define USB_HOST_PINTENCLR_TRCPT1   (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
-#define USB_HOST_PINTENCLR_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
-#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
-#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
-#define USB_HOST_PINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
-#define USB_HOST_PINTENCLR_TRFAIL   (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
-#define USB_HOST_PINTENCLR_PERR_Pos 3            /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
-#define USB_HOST_PINTENCLR_PERR     (0x1ul << USB_HOST_PINTENCLR_PERR_Pos)
-#define USB_HOST_PINTENCLR_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENCLR) Transmit  Setup Interrupt Disable */
-#define USB_HOST_PINTENCLR_TXSTP    (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos)
-#define USB_HOST_PINTENCLR_STALL_Pos 5            /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */
-#define USB_HOST_PINTENCLR_STALL    (0x1ul << USB_HOST_PINTENCLR_STALL_Pos)
-#define USB_HOST_PINTENCLR_MASK     0x3Ful       /**< \brief (USB_HOST_PINTENCLR) MASK Register */
-
-/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
-    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Enable      */
-    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Enable      */
-    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Enable    */
-    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out Interrupt enable    */
-    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out Interrupt enable    */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
-    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Enable      */
-    uint8_t  :1;               /*!< bit:      4  Reserved                           */
-    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out Interrupt enable    */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTENSET_OFFSET 0x109        /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-
-#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
-#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
-#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
-#define USB_DEVICE_EPINTENSET_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
-#define USB_DEVICE_EPINTENSET_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
-#define USB_DEVICE_EPINTENSET_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
-#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
-#define USB_DEVICE_EPINTENSET_MASK  0x7Ful       /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
-
-/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
-    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Enable        */
-    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Enable        */
-    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Enable   */
-    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Enable             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTENSET_OFFSET   0x109        /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
-#define USB_HOST_PINTENSET_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
-
-#define USB_HOST_PINTENSET_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT0   (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
-#define USB_HOST_PINTENSET_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT1   (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
-#define USB_HOST_PINTENSET_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
-#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
-#define USB_HOST_PINTENSET_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
-#define USB_HOST_PINTENSET_TRFAIL   (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
-#define USB_HOST_PINTENSET_PERR_Pos 3            /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
-#define USB_HOST_PINTENSET_PERR     (0x1ul << USB_HOST_PINTENSET_PERR_Pos)
-#define USB_HOST_PINTENSET_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable */
-#define USB_HOST_PINTENSET_TXSTP    (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos)
-#define USB_HOST_PINTENSET_STALL_Pos 5            /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
-#define USB_HOST_PINTENSET_STALL    (0x1ul << USB_HOST_PINTENSET_STALL_Pos)
-#define USB_HOST_PINTENSET_MASK     0x3Ful       /**< \brief (USB_HOST_PINTENSET) MASK Register */
-
-/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_ADDR_OFFSET      0x000        /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
-
-#define USB_DEVICE_ADDR_ADDR_Pos    0            /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
-#define USB_DEVICE_ADDR_ADDR_Msk    (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
-#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
-#define USB_DEVICE_ADDR_MASK        0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
-
-/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_HOST_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_ADDR_OFFSET        0x000        /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
-
-#define USB_HOST_ADDR_ADDR_Pos      0            /**< \brief (USB_HOST_ADDR) Adress of data buffer */
-#define USB_HOST_ADDR_ADDR_Msk      (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
-#define USB_HOST_ADDR_ADDR(value)   (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
-#define USB_HOST_ADDR_MASK          0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
-
-/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
-    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
-    uint32_t SIZE:3;           /*!< bit: 28..30  Enpoint size                       */
-    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_PCKSIZE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_PCKSIZE_OFFSET   0x004        /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
-
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
-#define USB_DEVICE_PCKSIZE_SIZE_Pos 28           /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
-#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
-#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
-#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
-#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
-#define USB_DEVICE_PCKSIZE_MASK     0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
-
-/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
-    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
-    uint32_t SIZE:3;           /*!< bit: 28..30  Pipe size                          */
-    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_HOST_PCKSIZE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PCKSIZE_OFFSET     0x004        /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
-
-#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_HOST_PCKSIZE) Byte Count */
-#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
-#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
-#define USB_HOST_PCKSIZE_SIZE_Pos   28           /**< \brief (USB_HOST_PCKSIZE) Pipe size */
-#define USB_HOST_PCKSIZE_SIZE_Msk   (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
-#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
-#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
-#define USB_HOST_PCKSIZE_AUTO_ZLP   (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
-#define USB_HOST_PCKSIZE_MASK       0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
-
-/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
-    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_EXTREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EXTREG_OFFSET    0x008        /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
-
-#define USB_DEVICE_EXTREG_SUBPID_Pos 0            /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
-#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
-#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
-#define USB_DEVICE_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
-#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
-#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
-#define USB_DEVICE_EXTREG_MASK      0x7FFFul     /**< \brief (USB_DEVICE_EXTREG) MASK Register */
-
-/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
-    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_EXTREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_EXTREG_OFFSET      0x008        /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
-
-#define USB_HOST_EXTREG_SUBPID_Pos  0            /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
-#define USB_HOST_EXTREG_SUBPID_Msk  (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
-#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
-#define USB_HOST_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
-#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
-#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
-#define USB_HOST_EXTREG_MASK        0x7FFFul     /**< \brief (USB_HOST_EXTREG) MASK Register */
-
-/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
-    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_STATUS_BK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_STATUS_BK_OFFSET 0x00A        /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
-
-#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
-#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos)
-#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
-#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
-#define USB_DEVICE_STATUS_BK_MASK   0x03ul       /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
-
-/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W  8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
-    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_STATUS_BK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_BK_OFFSET   0x00A        /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
-
-#define USB_HOST_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
-#define USB_HOST_STATUS_BK_CRCERR   (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos)
-#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
-#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
-#define USB_HOST_STATUS_BK_MASK     0x03ul       /**< \brief (USB_HOST_STATUS_BK) MASK Register */
-
-/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PDADDR:7;         /*!< bit:  0.. 6  Pipe Device Adress                 */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t PEPNUM:4;         /*!< bit:  8..11  Pipe Endpoint Number               */
-    uint16_t PERMAX:4;         /*!< bit: 12..15  Pipe Error Max Number              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_CTRL_PIPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_CTRL_PIPE_OFFSET   0x00C        /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
-#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
-
-#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
-#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
-#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
-#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
-#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
-#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
-#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12           /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
-#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
-#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
-#define USB_HOST_CTRL_PIPE_MASK     0xFF7Ful     /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
-
-/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DTGLER:1;         /*!< bit:      0  Data Toggle Error                  */
-    uint16_t DAPIDER:1;        /*!< bit:      1  Data PID Error                     */
-    uint16_t PIDER:1;          /*!< bit:      2  PID Error                          */
-    uint16_t TOUTER:1;         /*!< bit:      3  Time Out Error                     */
-    uint16_t CRC16ER:1;        /*!< bit:      4  CRC16 Error                        */
-    uint16_t ERCNT:3;          /*!< bit:  5.. 7  Pipe Error Count                   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_STATUS_PIPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_PIPE_OFFSET 0x00E        /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
-
-#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0            /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
-#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos)
-#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1            /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
-#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
-#define USB_HOST_STATUS_PIPE_PIDER_Pos 2            /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
-#define USB_HOST_STATUS_PIPE_PIDER  (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos)
-#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3            /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
-#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos)
-#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4            /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
-#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
-#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5            /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
-#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
-#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
-#define USB_HOST_STATUS_PIPE_MASK   0x00FFul     /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
-
-/** \brief UsbDeviceDescBank SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_DEVICE_ADDR_Type      ADDR;        /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
-  __IO USB_DEVICE_PCKSIZE_Type   PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
-  __IO USB_DEVICE_EXTREG_Type    EXTREG;      /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
-  __IO USB_DEVICE_STATUS_BK_Type STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
-       RoReg8                    Reserved1[0x5];
-} UsbDeviceDescBank;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbHostDescBank SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_HOST_ADDR_Type        ADDR;        /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
-  __IO USB_HOST_PCKSIZE_Type     PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
-  __IO USB_HOST_EXTREG_Type      EXTREG;      /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
-  __IO USB_HOST_STATUS_BK_Type   STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
-       RoReg8                    Reserved1[0x1];
-  __IO USB_HOST_CTRL_PIPE_Type   CTRL_PIPE;   /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
-  __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
-} UsbHostDescBank;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbDeviceEndpoint hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_DEVICE_EPCFG_Type     EPCFG;       /**< \brief Offset: 0x000 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
-       RoReg8                    Reserved1[0x3];
-  __O  USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
-  __O  USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
-  __I  USB_DEVICE_EPSTATUS_Type  EPSTATUS;    /**< \brief Offset: 0x006 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
-  __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG;   /**< \brief Offset: 0x007 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
-  __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR;  /**< \brief Offset: 0x008 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-  __IO USB_DEVICE_EPINTENSET_Type EPINTENSET;  /**< \brief Offset: 0x009 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-       RoReg8                    Reserved2[0x16];
-} UsbDeviceEndpoint;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbHostPipe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_HOST_PCFG_Type        PCFG;        /**< \brief Offset: 0x000 (R/W  8) HOST_PIPE End Point Configuration */
-       RoReg8                    Reserved1[0x2];
-  __IO USB_HOST_BINTERVAL_Type   BINTERVAL;   /**< \brief Offset: 0x003 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
-  __O  USB_HOST_PSTATUSCLR_Type  PSTATUSCLR;  /**< \brief Offset: 0x004 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
-  __O  USB_HOST_PSTATUSSET_Type  PSTATUSSET;  /**< \brief Offset: 0x005 ( /W  8) HOST_PIPE End Point Pipe Status Set */
-  __I  USB_HOST_PSTATUS_Type     PSTATUS;     /**< \brief Offset: 0x006 (R/   8) HOST_PIPE End Point Pipe Status */
-  __IO USB_HOST_PINTFLAG_Type    PINTFLAG;    /**< \brief Offset: 0x007 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
-  __IO USB_HOST_PINTENCLR_Type   PINTENCLR;   /**< \brief Offset: 0x008 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
-  __IO USB_HOST_PINTENSET_Type   PINTENSET;   /**< \brief Offset: 0x009 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
-       RoReg8                    Reserved2[0x16];
-} UsbHostPipe;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_DEVICE APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Device */
-  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x1];
-  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
-  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
-       RoReg8                    Reserved2[0x4];
-  __IO USB_DEVICE_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
-  __IO USB_DEVICE_DADD_Type      DADD;        /**< \brief Offset: 0x00A (R/W  8) DEVICE Device Address */
-       RoReg8                    Reserved3[0x1];
-  __I  USB_DEVICE_STATUS_Type    STATUS;      /**< \brief Offset: 0x00C (R/   8) DEVICE Status */
-  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
-       RoReg8                    Reserved4[0x2];
-  __I  USB_DEVICE_FNUM_Type      FNUM;        /**< \brief Offset: 0x010 (R/  16) DEVICE Device Frame Number */
-       RoReg8                    Reserved5[0x2];
-  __IO USB_DEVICE_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
-       RoReg8                    Reserved6[0x2];
-  __IO USB_DEVICE_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
-       RoReg8                    Reserved7[0x2];
-  __IO USB_DEVICE_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
-       RoReg8                    Reserved8[0x2];
-  __I  USB_DEVICE_EPINTSMRY_Type EPINTSMRY;   /**< \brief Offset: 0x020 (R/  16) DEVICE End Point Interrupt Summary */
-       RoReg8                    Reserved9[0x2];
-  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
-  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
-       RoReg8                    Reserved10[0xD6];
-       UsbDeviceEndpoint         DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
-} UsbDevice;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_HOST hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Host */
-  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x1];
-  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
-  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
-       RoReg8                    Reserved2[0x4];
-  __IO USB_HOST_CTRLB_Type       CTRLB;       /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
-  __IO USB_HOST_HSOFC_Type       HSOFC;       /**< \brief Offset: 0x00A (R/W  8) HOST Host Start Of Frame Control */
-       RoReg8                    Reserved3[0x1];
-  __IO USB_HOST_STATUS_Type      STATUS;      /**< \brief Offset: 0x00C (R/W  8) HOST Status */
-  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
-       RoReg8                    Reserved4[0x2];
-  __IO USB_HOST_FNUM_Type        FNUM;        /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
-  __I  USB_HOST_FLENHIGH_Type    FLENHIGH;    /**< \brief Offset: 0x012 (R/   8) HOST Host Frame Length */
-       RoReg8                    Reserved5[0x1];
-  __IO USB_HOST_INTENCLR_Type    INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
-       RoReg8                    Reserved6[0x2];
-  __IO USB_HOST_INTENSET_Type    INTENSET;    /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
-       RoReg8                    Reserved7[0x2];
-  __IO USB_HOST_INTFLAG_Type     INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
-       RoReg8                    Reserved8[0x2];
-  __I  USB_HOST_PINTSMRY_Type    PINTSMRY;    /**< \brief Offset: 0x020 (R/  16) HOST Pipe Interrupt Summary */
-       RoReg8                    Reserved9[0x2];
-  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
-  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
-       RoReg8                    Reserved10[0xD6];
-       UsbHostPipe               HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
-} UsbHost;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_DEVICE Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Device */
-       UsbDeviceDescBank         DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
-} UsbDeviceDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_HOST Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Host */
-       UsbHostDescBank           HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
-} UsbHostDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_USB_DESCRIPTOR
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       UsbDevice                 DEVICE;      /**< \brief Offset: 0x000 USB is Device */
-       UsbHost                   HOST;        /**< \brief Offset: 0x000 USB is Host */
-} Usb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_USB_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_COMPONENT_
+#define _SAMD21_USB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB                     0x103
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby Mode                */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  MODE:1;           /*!< bit:      7  Operating Mode                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET            0x000        /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE        0x00ul       /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos         0            /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST             (0x1ul << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos        1            /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE            (0x1ul << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos      2            /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY          (0x1ul << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos          7            /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE              (0x1ul << USB_CTRLA_MODE_Pos)
+#define   USB_CTRLA_MODE_DEVICE_Val       0x0ul  /**< \brief (USB_CTRLA) Device Mode */
+#define   USB_CTRLA_MODE_HOST_Val         0x1ul  /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE       (USB_CTRLA_MODE_DEVICE_Val     << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST         (USB_CTRLA_MODE_HOST_Val       << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK              0x87ul       /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/   8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET         0x002        /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE     0x00ul       /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos      0            /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST          (0x1ul << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos     1            /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE         (0x1ul << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK           0x03ul       /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W  8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CQOS:2;           /*!< bit:  0.. 1  Configuration Quality of Service   */
+    uint8_t  DQOS:2;           /*!< bit:  2.. 3  Data Quality of Service            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET          0x003        /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE      0x05ul       /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos        0            /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk        (0x3ul << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value)     (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define   USB_QOSCTRL_CQOS_DISABLE_Val    0x0ul  /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define   USB_QOSCTRL_CQOS_LOW_Val        0x1ul  /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define   USB_QOSCTRL_CQOS_MEDIUM_Val     0x2ul  /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define   USB_QOSCTRL_CQOS_HIGH_Val       0x3ul  /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_CQOS_DISABLE    (USB_QOSCTRL_CQOS_DISABLE_Val  << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_LOW        (USB_QOSCTRL_CQOS_LOW_Val      << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_MEDIUM     (USB_QOSCTRL_CQOS_MEDIUM_Val   << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_HIGH       (USB_QOSCTRL_CQOS_HIGH_Val     << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_DQOS_Pos        2            /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk        (0x3ul << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value)     (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define   USB_QOSCTRL_DQOS_DISABLE_Val    0x0ul  /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define   USB_QOSCTRL_DQOS_LOW_Val        0x1ul  /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define   USB_QOSCTRL_DQOS_MEDIUM_Val     0x2ul  /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define   USB_QOSCTRL_DQOS_HIGH_Val       0x3ul  /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_DQOS_DISABLE    (USB_QOSCTRL_DQOS_DISABLE_Val  << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_LOW        (USB_QOSCTRL_DQOS_LOW_Val      << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_MEDIUM     (USB_QOSCTRL_DQOS_MEDIUM_Val   << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_HIGH       (USB_QOSCTRL_DQOS_HIGH_Val     << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_MASK            0x0Ful       /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DETACH:1;         /*!< bit:      0  Detach                             */
+    uint16_t UPRSM:1;          /*!< bit:      1  Upstream Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration                */
+    uint16_t NREPLY:1;         /*!< bit:      4  No Reply                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t TSTPCKT:1;        /*!< bit:      7  Test packet mode                   */
+    uint16_t OPMODE2:1;        /*!< bit:      8  Specific Operational Mode          */
+    uint16_t GNAK:1;           /*!< bit:      9  Global NAK                         */
+    uint16_t LPMHDSK:2;        /*!< bit: 10..11  Link Power Management Handshake    */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET     0x008        /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul     /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0            /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH     (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos  1            /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM      (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2            /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul  /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul  /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul  /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul  /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4            /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY     (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos   5            /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ       (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos   6            /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK       (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7            /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT    (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8            /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2    (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos   9            /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK       (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10           /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul  /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul  /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul  /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul  /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK       0x0FFFul     /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t RESUME:1;         /*!< bit:      1  Send USB Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration for Host       */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t SOFE:1;           /*!< bit:      8  Start of Frame Generation Enable   */
+    uint16_t BUSRESET:1;       /*!< bit:      9  Send USB Reset                     */
+    uint16_t VBUSOK:1;         /*!< bit:     10  VBUS is OK                         */
+    uint16_t L1RESUME:1;       /*!< bit:     11  Send L1 Resume                     */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET       0x008        /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE   0x0000ul     /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos   1            /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME       (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos  2            /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk  (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul  /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define   USB_HOST_CTRLB_SPDCONF_FS_Val   0x3ul  /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS   (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos     5            /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ         (0x1ul << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos     6            /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK         (0x1ul << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos     8            /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE         (0x1ul << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9            /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET     (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos   10           /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK       (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11           /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME     (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK         0x0F6Eul     /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DADD:7;           /*!< bit:  0.. 6  Device Address                     */
+    uint8_t  ADDEN:1;          /*!< bit:      7  Device Address Enable              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET      0x00A        /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE  0x00ul       /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos    0            /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk    (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos   7            /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN       (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK        0xFFul       /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W  8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENC:4;          /*!< bit:  0.. 3  Frame Length Control               */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  FLENCE:1;         /*!< bit:      7  Frame Length Control Enable        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET       0x00A        /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE   0x00ul       /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos    0            /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk    (0xFul << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos   7            /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE       (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK         0x8Ful       /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/   8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET    0x00C        /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE 0x40ul       /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2            /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define   USB_DEVICE_STATUS_SPEED_FS_Val  0x0ul  /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_HS_Val  0x1ul  /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_LS_Val  0x2ul  /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS  (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS  (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS  (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6            /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define   USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul  /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define   USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul  /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define   USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul  /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK      0xCCul       /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W  8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET      0x00C        /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE  0x00ul       /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos   2            /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk   (0x3ul << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6            /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK        0xCCul       /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/   8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FSMSTATE:7;       /*!< bit:  0.. 6  Fine State Machine Status          */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET        0x00D        /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE    0x01ul       /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos  0            /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk  (0x7Ful << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define   USB_FSMSTATUS_FSMSTATE_OFF_Val  0x1ul  /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define   USB_FSMSTATUS_FSMSTATE_ON_Val   0x2ul  /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul  /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul  /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul  /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul  /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul  /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF  (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON   (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK          0x7Ful       /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/  16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :1;               /*!< bit:     14  Reserved                           */
+    uint16_t FNCERR:1;         /*!< bit:     15  Frame Number CRC Error             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET      0x010        /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE  0x0000ul     /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos   0            /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk   (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos    3            /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk    (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos  15           /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR      (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK        0xBFFFul     /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET        0x010        /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE    0x0000ul     /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos     0            /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk     (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value)  (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos      3            /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk      (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value)   (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK          0x3FFFul     /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/   8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENHIGH:8;       /*!< bit:  0.. 7  Frame Length                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET    0x012        /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul       /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0            /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK      0xFFul       /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET  0x014        /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF    (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF     (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST   (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP  (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM   (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM   (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK    0x03FFul     /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Disable */
+    uint16_t RST:1;            /*!< bit:      3  BUS Reset Interrupt Disable        */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Disable          */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to Device Interrupt Disable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from Device Interrupt Disable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Disable       */
+    uint16_t DCONN:1;          /*!< bit:      8  Device Connection Interrupt Disable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Disable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET    0x014        /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos  2            /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF      (0x1ul << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos   3            /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST       (0x1ul << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP    (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM     (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM     (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER   (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8            /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN     (0x1ul << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9            /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC     (0x1ul << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK      0x03FCul     /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET  0x018        /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF    (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF     (0x1ul << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST   (0x1ul << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP  (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM   (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM   (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK    0x03FFul     /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Enable */
+    uint16_t RST:1;            /*!< bit:      3  Bus Reset Interrupt Enable         */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to the Device Interrupt Enable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume fromthe device Interrupt Enable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t DCONN:1;          /*!< bit:      8  Link Power Management Interrupt Enable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET    0x018        /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos  2            /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF      (0x1ul << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos   3            /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST       (0x1ul << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP    (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM     (0x1ul << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM     (0x1ul << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER   (0x1ul << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8            /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN     (0x1ul << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9            /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC     (0x1ul << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK      0x03FCul     /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
+    __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
+    __I uint16_t SOF:1;            /*!< bit:      2  Start Of Frame                     */
+    __I uint16_t EORST:1;          /*!< bit:      3  End of Reset                       */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t EORSM:1;          /*!< bit:      5  End Of Resume                      */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume                    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet      */
+    __I uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend      */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET   0x01C        /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND  (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF     (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos  2            /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF      (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3            /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST    (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP   (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM    (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM    (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER  (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET  (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP  (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK     0x03FFul     /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
+    __I uint16_t RST:1;            /*!< bit:      3  Bus Reset                          */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t DNRSM:1;          /*!< bit:      5  Downstream                         */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from the Device    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t DCONN:1;          /*!< bit:      8  Device Connection                  */
+    __I uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection               */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET     0x01C        /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos   2            /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF       (0x1ul << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos    3            /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST        (0x1ul << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP     (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos  5            /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM      (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos  6            /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM      (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER    (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos  8            /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN      (0x1ul << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos  9            /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC      (0x1ul << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK       0x03FCul     /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/  16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  End Point 0 Interrupt              */
+    uint16_t EPINT1:1;         /*!< bit:      1  End Point 1 Interrupt              */
+    uint16_t EPINT2:1;         /*!< bit:      2  End Point 2 Interrupt              */
+    uint16_t EPINT3:1;         /*!< bit:      3  End Point 3 Interrupt              */
+    uint16_t EPINT4:1;         /*!< bit:      4  End Point 4 Interrupt              */
+    uint16_t EPINT5:1;         /*!< bit:      5  End Point 5 Interrupt              */
+    uint16_t EPINT6:1;         /*!< bit:      6  End Point 6 Interrupt              */
+    uint16_t EPINT7:1;         /*!< bit:      7  End Point 7 Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  End Point x Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020        /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul     /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK   0x00FFul     /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/  16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  Pipe 0 Interrupt                   */
+    uint16_t EPINT1:1;         /*!< bit:      1  Pipe 1 Interrupt                   */
+    uint16_t EPINT2:1;         /*!< bit:      2  Pipe 2 Interrupt                   */
+    uint16_t EPINT3:1;         /*!< bit:      3  Pipe 3 Interrupt                   */
+    uint16_t EPINT4:1;         /*!< bit:      4  Pipe 4 Interrupt                   */
+    uint16_t EPINT5:1;         /*!< bit:      5  Pipe 5 Interrupt                   */
+    uint16_t EPINT6:1;         /*!< bit:      6  Pipe 6 Interrupt                   */
+    uint16_t EPINT7:1;         /*!< bit:      7  Pipe 7 Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  Pipe x Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET    0x020        /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0    (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1            /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1    (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2            /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2    (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3            /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3    (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4            /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4    (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5            /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5    (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6            /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6    (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7            /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7    (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK      0x00FFul     /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADD:32;       /*!< bit:  0..31  Descriptor Address Value           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET          0x024        /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE      0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos     0            /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk     (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value)  (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK            0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t TRANSP:5;         /*!< bit:  0.. 4  USB Pad Transp calibration         */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t TRANSN:5;         /*!< bit:  6..10  USB Pad Transn calibration         */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t TRIM:3;           /*!< bit: 12..14  USB Pad Trim calibration           */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET           0x028        /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE       0x0000ul     /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos       0            /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk       (0x1Ful << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value)    (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos       6            /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk       (0x1Ful << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value)    (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos         12           /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk         (0x7ul << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value)      (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK             0x77DFul     /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EPTYPE0:3;        /*!< bit:  0.. 2  End Point Type0                    */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EPTYPE1:3;        /*!< bit:  4.. 6  End Point Type1                    */
+    uint8_t  NYETDIS:1;        /*!< bit:      7  NYET Token Disable                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET     0x100        /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0            /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4            /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7            /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS    (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK       0xF7ul       /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W  8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PTOKEN:2;         /*!< bit:  0.. 1  Pipe Token                         */
+    uint8_t  BK:1;             /*!< bit:      2  Pipe Bank                          */
+    uint8_t  PTYPE:3;          /*!< bit:  3.. 5  Pipe Type                          */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET        0x100        /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE    0x00ul       /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos    0            /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk    (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos        2            /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK            (0x1ul << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos     3            /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk     (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value)  (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK          0x3Ful       /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W  8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BITINTERVAL:8;    /*!< bit:  0.. 7  Bit Interval                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET   0x103        /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul       /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0            /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK     0xFFul       /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Clear              */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Clear               */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank Clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Clear              */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Clear              */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Clear              */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104        /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul       /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W  8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle clear                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Clear                  */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET  0x104        /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL    (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK   (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY  (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY  (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK    0xD5ul       /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Set                */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Set                 */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Set                */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Set                */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Set                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105        /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul       /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W  8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle Set                    */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Set                    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET  0x105        /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL    (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK   (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY  (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY  (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK    0xD5ul       /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/   8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle Out                    */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle In                     */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request                    */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request                    */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request                    */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET  0x106        /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN  (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK   (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY  (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY  (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK    0xF7ul       /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/   8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle                        */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze                        */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET     0x106        /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos   0            /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL       (0x1ul << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos  2            /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK      (0x1ul << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE    (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY     (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY     (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK       0xD5ul       /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
+    __I uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0                       */
+    __I uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1                       */
+    __I uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup                     */
+    __I uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out                     */
+    __I uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x                */
+    __I uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x                       */
+    __I uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    __I uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107        /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP  (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK   0x7Ful       /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
+    __I uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Flag          */
+    __I uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Flag          */
+    __I uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Flag     */
+    __I uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Flag               */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Flag */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET    0x107        /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0    (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1    (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL    (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos  3            /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR      (0x1ul << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP     (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5            /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL     (0x1ul << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK      0x3Ful       /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Disable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Disable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Disable     */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Disable     */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Disable   */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/Out Interrupt Disable   */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Disable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Disable     */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108        /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK  0x7Ful       /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Disable        */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Disable        */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Disable       */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Disable       */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Disable  */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Disable            */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Disable        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET   0x108        /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0   (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1   (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL   (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3            /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR     (0x1ul << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENCLR) Transmit  Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP    (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5            /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */
+#define USB_HOST_PINTENCLR_STALL    (0x1ul << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK     0x3Ful       /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Enable      */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Enable      */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Enable    */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out Interrupt enable    */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Enable      */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109        /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul       /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK  0x7Ful       /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Enable        */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Enable        */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Enable   */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Enable             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET   0x109        /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE 0x00ul       /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0   (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1   (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL   (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3            /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR     (0x1ul << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP    (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5            /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL    (0x1ul << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK     0x3Ful       /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET      0x000        /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos    0            /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk    (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK        0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET        0x000        /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos      0            /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk      (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value)   (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK          0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Enpoint size                       */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET   0x004        /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28           /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK     0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Pipe size                          */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET     0x004        /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos   28           /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk   (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP   (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK       0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET    0x008        /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0            /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK      0x7FFFul     /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET      0x008        /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos  0            /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk  (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK        0x7FFFul     /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A        /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK   0x03ul       /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W  8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET   0x00A        /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR   (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK     0x03ul       /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PDADDR:7;         /*!< bit:  0.. 6  Pipe Device Adress                 */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PEPNUM:4;         /*!< bit:  8..11  Pipe Endpoint Number               */
+    uint16_t PERMAX:4;         /*!< bit: 12..15  Pipe Error Max Number              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET   0x00C        /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul     /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12           /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK     0xFF7Ful     /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DTGLER:1;         /*!< bit:      0  Data Toggle Error                  */
+    uint16_t DAPIDER:1;        /*!< bit:      1  Data PID Error                     */
+    uint16_t PIDER:1;          /*!< bit:      2  PID Error                          */
+    uint16_t TOUTER:1;         /*!< bit:      3  Time Out Error                     */
+    uint16_t CRC16ER:1;        /*!< bit:      4  CRC16 Error                        */
+    uint16_t ERCNT:3;          /*!< bit:  5.. 7  Pipe Error Count                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E        /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0            /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1            /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2            /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER  (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3            /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4            /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5            /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK   0x00FFul     /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_ADDR_Type      ADDR;        /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+  __IO USB_DEVICE_PCKSIZE_Type   PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+  __IO USB_DEVICE_EXTREG_Type    EXTREG;      /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+  __IO USB_DEVICE_STATUS_BK_Type STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+       RoReg8                    Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_ADDR_Type        ADDR;        /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+  __IO USB_HOST_PCKSIZE_Type     PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+  __IO USB_HOST_EXTREG_Type      EXTREG;      /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+  __IO USB_HOST_STATUS_BK_Type   STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
+       RoReg8                    Reserved1[0x1];
+  __IO USB_HOST_CTRL_PIPE_Type   CTRL_PIPE;   /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+  __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_EPCFG_Type     EPCFG;       /**< \brief Offset: 0x000 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
+       RoReg8                    Reserved1[0x3];
+  __O  USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+  __O  USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
+  __I  USB_DEVICE_EPSTATUS_Type  EPSTATUS;    /**< \brief Offset: 0x006 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
+  __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG;   /**< \brief Offset: 0x007 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
+  __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR;  /**< \brief Offset: 0x008 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+  __IO USB_DEVICE_EPINTENSET_Type EPINTENSET;  /**< \brief Offset: 0x009 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+       RoReg8                    Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_PCFG_Type        PCFG;        /**< \brief Offset: 0x000 (R/W  8) HOST_PIPE End Point Configuration */
+       RoReg8                    Reserved1[0x2];
+  __IO USB_HOST_BINTERVAL_Type   BINTERVAL;   /**< \brief Offset: 0x003 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
+  __O  USB_HOST_PSTATUSCLR_Type  PSTATUSCLR;  /**< \brief Offset: 0x004 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
+  __O  USB_HOST_PSTATUSSET_Type  PSTATUSSET;  /**< \brief Offset: 0x005 ( /W  8) HOST_PIPE End Point Pipe Status Set */
+  __I  USB_HOST_PSTATUS_Type     PSTATUS;     /**< \brief Offset: 0x006 (R/   8) HOST_PIPE End Point Pipe Status */
+  __IO USB_HOST_PINTFLAG_Type    PINTFLAG;    /**< \brief Offset: 0x007 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
+  __IO USB_HOST_PINTENCLR_Type   PINTENCLR;   /**< \brief Offset: 0x008 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
+  __IO USB_HOST_PINTENSET_Type   PINTENSET;   /**< \brief Offset: 0x009 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
+       RoReg8                    Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_DEVICE_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+  __IO USB_DEVICE_DADD_Type      DADD;        /**< \brief Offset: 0x00A (R/W  8) DEVICE Device Address */
+       RoReg8                    Reserved3[0x1];
+  __I  USB_DEVICE_STATUS_Type    STATUS;      /**< \brief Offset: 0x00C (R/   8) DEVICE Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __I  USB_DEVICE_FNUM_Type      FNUM;        /**< \brief Offset: 0x010 (R/  16) DEVICE Device Frame Number */
+       RoReg8                    Reserved5[0x2];
+  __IO USB_DEVICE_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_DEVICE_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_DEVICE_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_DEVICE_EPINTSMRY_Type EPINTSMRY;   /**< \brief Offset: 0x020 (R/  16) DEVICE End Point Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbDeviceEndpoint         DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_HOST_CTRLB_Type       CTRLB;       /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+  __IO USB_HOST_HSOFC_Type       HSOFC;       /**< \brief Offset: 0x00A (R/W  8) HOST Host Start Of Frame Control */
+       RoReg8                    Reserved3[0x1];
+  __IO USB_HOST_STATUS_Type      STATUS;      /**< \brief Offset: 0x00C (R/W  8) HOST Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __IO USB_HOST_FNUM_Type        FNUM;        /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+  __I  USB_HOST_FLENHIGH_Type    FLENHIGH;    /**< \brief Offset: 0x012 (R/   8) HOST Host Frame Length */
+       RoReg8                    Reserved5[0x1];
+  __IO USB_HOST_INTENCLR_Type    INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_HOST_INTENSET_Type    INTENSET;    /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_HOST_INTFLAG_Type     INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_HOST_PINTSMRY_Type    PINTSMRY;    /**< \brief Offset: 0x020 (R/  16) HOST Pipe Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbHostPipe               HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+       UsbDeviceDescBank         DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+       UsbHostDescBank           HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       UsbDevice                 DEVICE;      /**< \brief Offset: 0x000 USB is Device */
+       UsbHost                   HOST;        /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_USB_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h
index b0e1209..553e82d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h
@@ -1,293 +1,293 @@
-/**
- * \file
- *
- * \brief Component description for WDT
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_WDT_COMPONENT_
-#define _SAMD21_WDT_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR WDT */
-/* ========================================================================== */
-/** \addtogroup SAMD21_WDT Watchdog Timer */
-/*@{*/
-
-#define WDT_U2203
-#define REV_WDT                     0x200
-
-/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CTRL_OFFSET             0x0          /**< \brief (WDT_CTRL offset) Control */
-#define WDT_CTRL_RESETVALUE         0x00ul       /**< \brief (WDT_CTRL reset_value) Control */
-
-#define WDT_CTRL_ENABLE_Pos         1            /**< \brief (WDT_CTRL) Enable */
-#define WDT_CTRL_ENABLE             (0x1ul << WDT_CTRL_ENABLE_Pos)
-#define WDT_CTRL_WEN_Pos            2            /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
-#define WDT_CTRL_WEN                (0x1ul << WDT_CTRL_WEN_Pos)
-#define WDT_CTRL_ALWAYSON_Pos       7            /**< \brief (WDT_CTRL) Always-On */
-#define WDT_CTRL_ALWAYSON           (0x1ul << WDT_CTRL_ALWAYSON_Pos)
-#define WDT_CTRL_MASK               0x86ul       /**< \brief (WDT_CTRL) MASK Register */
-
-/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
-    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_CONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
-#define WDT_CONFIG_RESETVALUE       0xBBul       /**< \brief (WDT_CONFIG reset_value) Configuration */
-
-#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
-#define WDT_CONFIG_PER_Msk          (0xFul << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER(value)       (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
-#define   WDT_CONFIG_PER_8_Val            0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
-#define   WDT_CONFIG_PER_16_Val           0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
-#define   WDT_CONFIG_PER_32_Val           0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
-#define   WDT_CONFIG_PER_64_Val           0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
-#define   WDT_CONFIG_PER_128_Val          0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
-#define   WDT_CONFIG_PER_256_Val          0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
-#define   WDT_CONFIG_PER_512_Val          0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
-#define   WDT_CONFIG_PER_1K_Val           0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
-#define   WDT_CONFIG_PER_2K_Val           0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
-#define   WDT_CONFIG_PER_4K_Val           0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
-#define   WDT_CONFIG_PER_8K_Val           0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
-#define   WDT_CONFIG_PER_16K_Val          0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
-#define WDT_CONFIG_PER_8            (WDT_CONFIG_PER_8_Val          << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_16           (WDT_CONFIG_PER_16_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_32           (WDT_CONFIG_PER_32_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_64           (WDT_CONFIG_PER_64_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_128          (WDT_CONFIG_PER_128_Val        << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_256          (WDT_CONFIG_PER_256_Val        << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_512          (WDT_CONFIG_PER_512_Val        << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_1K           (WDT_CONFIG_PER_1K_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_2K           (WDT_CONFIG_PER_2K_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_4K           (WDT_CONFIG_PER_4K_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_8K           (WDT_CONFIG_PER_8K_Val         << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_16K          (WDT_CONFIG_PER_16K_Val        << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
-#define WDT_CONFIG_WINDOW_Msk       (0xFul << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW(value)    (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
-#define   WDT_CONFIG_WINDOW_8_Val         0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
-#define   WDT_CONFIG_WINDOW_16_Val        0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
-#define   WDT_CONFIG_WINDOW_32_Val        0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
-#define   WDT_CONFIG_WINDOW_64_Val        0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
-#define   WDT_CONFIG_WINDOW_128_Val       0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
-#define   WDT_CONFIG_WINDOW_256_Val       0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
-#define   WDT_CONFIG_WINDOW_512_Val       0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
-#define   WDT_CONFIG_WINDOW_1K_Val        0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
-#define   WDT_CONFIG_WINDOW_2K_Val        0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
-#define   WDT_CONFIG_WINDOW_4K_Val        0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
-#define   WDT_CONFIG_WINDOW_8K_Val        0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
-#define   WDT_CONFIG_WINDOW_16K_Val       0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
-#define WDT_CONFIG_WINDOW_8         (WDT_CONFIG_WINDOW_8_Val       << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_16        (WDT_CONFIG_WINDOW_16_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_32        (WDT_CONFIG_WINDOW_32_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_64        (WDT_CONFIG_WINDOW_64_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_128       (WDT_CONFIG_WINDOW_128_Val     << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_256       (WDT_CONFIG_WINDOW_256_Val     << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_512       (WDT_CONFIG_WINDOW_512_Val     << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_1K        (WDT_CONFIG_WINDOW_1K_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_2K        (WDT_CONFIG_WINDOW_2K_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_4K        (WDT_CONFIG_WINDOW_4K_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_8K        (WDT_CONFIG_WINDOW_8K_Val      << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_16K       (WDT_CONFIG_WINDOW_16K_Val     << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_MASK             0xFFul       /**< \brief (WDT_CONFIG) MASK Register */
-
-/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_EWCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
-#define WDT_EWCTRL_RESETVALUE       0x0Bul       /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
-
-#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
-#define WDT_EWCTRL_EWOFFSET_Msk     (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET(value)  (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
-#define   WDT_EWCTRL_EWOFFSET_8_Val       0x0ul  /**< \brief (WDT_EWCTRL) 8 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_16_Val      0x1ul  /**< \brief (WDT_EWCTRL) 16 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_32_Val      0x2ul  /**< \brief (WDT_EWCTRL) 32 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_64_Val      0x3ul  /**< \brief (WDT_EWCTRL) 64 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_128_Val     0x4ul  /**< \brief (WDT_EWCTRL) 128 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_256_Val     0x5ul  /**< \brief (WDT_EWCTRL) 256 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_512_Val     0x6ul  /**< \brief (WDT_EWCTRL) 512 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_1K_Val      0x7ul  /**< \brief (WDT_EWCTRL) 1024 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_2K_Val      0x8ul  /**< \brief (WDT_EWCTRL) 2048 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_4K_Val      0x9ul  /**< \brief (WDT_EWCTRL) 4096 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_8K_Val      0xAul  /**< \brief (WDT_EWCTRL) 8192 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_16K_Val     0xBul  /**< \brief (WDT_EWCTRL) 16384 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_8       (WDT_EWCTRL_EWOFFSET_8_Val     << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_16      (WDT_EWCTRL_EWOFFSET_16_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_32      (WDT_EWCTRL_EWOFFSET_32_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_64      (WDT_EWCTRL_EWOFFSET_64_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_128     (WDT_EWCTRL_EWOFFSET_128_Val   << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_256     (WDT_EWCTRL_EWOFFSET_256_Val   << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_512     (WDT_EWCTRL_EWOFFSET_512_Val   << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_1K      (WDT_EWCTRL_EWOFFSET_1K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_2K      (WDT_EWCTRL_EWOFFSET_2K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_4K      (WDT_EWCTRL_EWOFFSET_4K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_8K      (WDT_EWCTRL_EWOFFSET_8K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_16K     (WDT_EWCTRL_EWOFFSET_16K_Val   << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_MASK             0x0Ful       /**< \brief (WDT_EWCTRL) MASK Register */
-
-/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
-#define WDT_INTENCLR_RESETVALUE     0x00ul       /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
-#define WDT_INTENCLR_EW             (0x1ul << WDT_INTENCLR_EW_Pos)
-#define WDT_INTENCLR_MASK           0x01ul       /**< \brief (WDT_INTENCLR) MASK Register */
-
-/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
-#define WDT_INTENSET_RESETVALUE     0x00ul       /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
-
-#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
-#define WDT_INTENSET_EW             (0x1ul << WDT_INTENSET_EW_Pos)
-#define WDT_INTENSET_MASK           0x01ul       /**< \brief (WDT_INTENSET) MASK Register */
-
-/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
-#define WDT_INTFLAG_RESETVALUE      0x00ul       /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
-#define WDT_INTFLAG_EW              (0x1ul << WDT_INTFLAG_EW_Pos)
-#define WDT_INTFLAG_MASK            0x01ul       /**< \brief (WDT_INTFLAG) MASK Register */
-
-/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_STATUS_OFFSET           0x7          /**< \brief (WDT_STATUS offset) Status */
-#define WDT_STATUS_RESETVALUE       0x00ul       /**< \brief (WDT_STATUS reset_value) Status */
-
-#define WDT_STATUS_SYNCBUSY_Pos     7            /**< \brief (WDT_STATUS) Synchronization Busy */
-#define WDT_STATUS_SYNCBUSY         (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
-#define WDT_STATUS_MASK             0x80ul       /**< \brief (WDT_STATUS) MASK Register */
-
-/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W  8) Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_CLEAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CLEAR_OFFSET            0x8          /**< \brief (WDT_CLEAR offset) Clear */
-#define WDT_CLEAR_RESETVALUE        0x00ul       /**< \brief (WDT_CLEAR reset_value) Clear */
-
-#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
-#define WDT_CLEAR_CLEAR_Msk         (0xFFul << WDT_CLEAR_CLEAR_Pos)
-#define WDT_CLEAR_CLEAR(value)      (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
-#define   WDT_CLEAR_CLEAR_KEY_Val         0xA5ul  /**< \brief (WDT_CLEAR) Clear Key */
-#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
-#define WDT_CLEAR_MASK              0xFFul       /**< \brief (WDT_CLEAR) MASK Register */
-
-/** \brief WDT hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO WDT_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
-  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
-  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
-       RoReg8                    Reserved1[0x1];
-  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
-  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
-  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
-  __I  WDT_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
-  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0x8 ( /W  8) Clear */
-} Wdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD21_WDT_COMPONENT_ */
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_COMPONENT_
+#define _SAMD21_WDT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT                     0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET             0x0          /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE         0x00ul       /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos         1            /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE             (0x1ul << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos            2            /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN                (0x1ul << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos       7            /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON           (0x1ul << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK               0x86ul       /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
+    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE       0xBBul       /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk          (0xFul << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value)       (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define   WDT_CONFIG_PER_8_Val            0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_PER_16_Val           0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_PER_32_Val           0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_PER_64_Val           0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_PER_128_Val          0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_PER_256_Val          0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_PER_512_Val          0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_PER_1K_Val           0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_PER_2K_Val           0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_PER_4K_Val           0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_PER_8K_Val           0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_PER_16K_Val          0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_8            (WDT_CONFIG_PER_8_Val          << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16           (WDT_CONFIG_PER_16_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_32           (WDT_CONFIG_PER_32_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_64           (WDT_CONFIG_PER_64_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_128          (WDT_CONFIG_PER_128_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_256          (WDT_CONFIG_PER_256_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_512          (WDT_CONFIG_PER_512_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1K           (WDT_CONFIG_PER_1K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2K           (WDT_CONFIG_PER_2K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4K           (WDT_CONFIG_PER_4K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8K           (WDT_CONFIG_PER_8K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16K          (WDT_CONFIG_PER_16K_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk       (0xFul << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value)    (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define   WDT_CONFIG_WINDOW_8_Val         0x0ul  /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_WINDOW_16_Val        0x1ul  /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_WINDOW_32_Val        0x2ul  /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_WINDOW_64_Val        0x3ul  /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_WINDOW_128_Val       0x4ul  /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_WINDOW_256_Val       0x5ul  /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_WINDOW_512_Val       0x6ul  /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_WINDOW_1K_Val        0x7ul  /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_WINDOW_2K_Val        0x8ul  /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_WINDOW_4K_Val        0x9ul  /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_WINDOW_8K_Val        0xAul  /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_WINDOW_16K_Val       0xBul  /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_8         (WDT_CONFIG_WINDOW_8_Val       << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16        (WDT_CONFIG_WINDOW_16_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_32        (WDT_CONFIG_WINDOW_32_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_64        (WDT_CONFIG_WINDOW_64_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_128       (WDT_CONFIG_WINDOW_128_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_256       (WDT_CONFIG_WINDOW_256_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_512       (WDT_CONFIG_WINDOW_512_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1K        (WDT_CONFIG_WINDOW_1K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2K        (WDT_CONFIG_WINDOW_2K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4K        (WDT_CONFIG_WINDOW_4K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8K        (WDT_CONFIG_WINDOW_8K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16K       (WDT_CONFIG_WINDOW_16K_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK             0xFFul       /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE       0x0Bul       /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk     (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value)  (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define   WDT_EWCTRL_EWOFFSET_8_Val       0x0ul  /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16_Val      0x1ul  /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_32_Val      0x2ul  /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_64_Val      0x3ul  /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_128_Val     0x4ul  /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_256_Val     0x5ul  /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_512_Val     0x6ul  /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_1K_Val      0x7ul  /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_2K_Val      0x8ul  /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_4K_Val      0x9ul  /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_8K_Val      0xAul  /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16K_Val     0xBul  /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8       (WDT_EWCTRL_EWOFFSET_8_Val     << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16      (WDT_EWCTRL_EWOFFSET_16_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_32      (WDT_EWCTRL_EWOFFSET_32_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_64      (WDT_EWCTRL_EWOFFSET_64_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_128     (WDT_EWCTRL_EWOFFSET_128_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_256     (WDT_EWCTRL_EWOFFSET_256_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_512     (WDT_EWCTRL_EWOFFSET_512_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1K      (WDT_EWCTRL_EWOFFSET_1K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2K      (WDT_EWCTRL_EWOFFSET_2K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4K      (WDT_EWCTRL_EWOFFSET_4K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8K      (WDT_EWCTRL_EWOFFSET_8K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16K     (WDT_EWCTRL_EWOFFSET_16K_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK             0x0Ful       /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE     0x00ul       /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW             (0x1ul << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK           0x01ul       /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE     0x00ul       /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW             (0x1ul << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK           0x01ul       /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE      0x00ul       /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW              (0x1ul << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK            0x01ul       /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET           0x7          /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE       0x00ul       /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos     7            /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY         (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK             0x80ul       /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W  8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET            0x8          /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE        0x00ul       /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk         (0xFFul << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value)      (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define   WDT_CLEAR_CLEAR_KEY_Val         0xA5ul  /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK              0xFFul       /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO WDT_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
+  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
+       RoReg8                    Reserved1[0x1];
+  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  WDT_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0x8 ( /W  8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_WDT_COMPONENT_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h
index cc504f6..d26c7d5 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h
@@ -1,77 +1,77 @@
-/**
- * \file
- *
- * \brief Instance description for AC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_AC_INSTANCE_
-#define _SAMD21_AC_INSTANCE_
-
-/* ========== Register definition for AC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_AC_CTRLA               (0x42004400U) /**< \brief (AC) Control A */
-#define REG_AC_CTRLB               (0x42004401U) /**< \brief (AC) Control B */
-#define REG_AC_EVCTRL              (0x42004402U) /**< \brief (AC) Event Control */
-#define REG_AC_INTENCLR            (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
-#define REG_AC_INTENSET            (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
-#define REG_AC_INTFLAG             (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
-#define REG_AC_STATUSA             (0x42004408U) /**< \brief (AC) Status A */
-#define REG_AC_STATUSB             (0x42004409U) /**< \brief (AC) Status B */
-#define REG_AC_STATUSC             (0x4200440AU) /**< \brief (AC) Status C */
-#define REG_AC_WINCTRL             (0x4200440CU) /**< \brief (AC) Window Control */
-#define REG_AC_COMPCTRL0           (0x42004410U) /**< \brief (AC) Comparator Control 0 */
-#define REG_AC_COMPCTRL1           (0x42004414U) /**< \brief (AC) Comparator Control 1 */
-#define REG_AC_SCALER0             (0x42004420U) /**< \brief (AC) Scaler 0 */
-#define REG_AC_SCALER1             (0x42004421U) /**< \brief (AC) Scaler 1 */
-#else
-#define REG_AC_CTRLA               (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
-#define REG_AC_CTRLB               (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
-#define REG_AC_EVCTRL              (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
-#define REG_AC_INTENCLR            (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
-#define REG_AC_INTENSET            (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
-#define REG_AC_INTFLAG             (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
-#define REG_AC_STATUSA             (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
-#define REG_AC_STATUSB             (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
-#define REG_AC_STATUSC             (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
-#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
-#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
-#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
-#define REG_AC_SCALER0             (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
-#define REG_AC_SCALER1             (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for AC peripheral ========== */
-#define AC_CMP_NUM                  2        // Number of comparators
-#define AC_GCLK_ID_ANA              32       // Index of Generic Clock for analog
-#define AC_GCLK_ID_DIG              31       // Index of Generic Clock for digital
-#define AC_NUM_CMP                  2       
-#define AC_PAIRS                    1        // Number of pairs of comparators
-
-#endif /* _SAMD21_AC_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_INSTANCE_
+#define _SAMD21_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA               (0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (0x42004421U) /**< \brief (AC) Scaler 1 */
+#else
+#define REG_AC_CTRLA               (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_CMP_NUM                  2        // Number of comparators
+#define AC_GCLK_ID_ANA              32       // Index of Generic Clock for analog
+#define AC_GCLK_ID_DIG              31       // Index of Generic Clock for digital
+#define AC_NUM_CMP                  2       
+#define AC_PAIRS                    1        // Number of pairs of comparators
+
+#endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac1.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac1.h
index fcaa93c..c91c6ed 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac1.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac1.h
@@ -1,77 +1,77 @@
-/**
- * \file
- *
- * \brief Instance description for AC1
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_AC1_INSTANCE_
-#define _SAMD21_AC1_INSTANCE_
-
-/* ========== Register definition for AC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_AC1_CTRLA              (0x42005400U) /**< \brief (AC1) Control A */
-#define REG_AC1_CTRLB              (0x42005401U) /**< \brief (AC1) Control B */
-#define REG_AC1_EVCTRL             (0x42005402U) /**< \brief (AC1) Event Control */
-#define REG_AC1_INTENCLR           (0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
-#define REG_AC1_INTENSET           (0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
-#define REG_AC1_INTFLAG            (0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
-#define REG_AC1_STATUSA            (0x42005408U) /**< \brief (AC1) Status A */
-#define REG_AC1_STATUSB            (0x42005409U) /**< \brief (AC1) Status B */
-#define REG_AC1_STATUSC            (0x4200540AU) /**< \brief (AC1) Status C */
-#define REG_AC1_WINCTRL            (0x4200540CU) /**< \brief (AC1) Window Control */
-#define REG_AC1_COMPCTRL0          (0x42005410U) /**< \brief (AC1) Comparator Control 0 */
-#define REG_AC1_COMPCTRL1          (0x42005414U) /**< \brief (AC1) Comparator Control 1 */
-#define REG_AC1_SCALER0            (0x42005420U) /**< \brief (AC1) Scaler 0 */
-#define REG_AC1_SCALER1            (0x42005421U) /**< \brief (AC1) Scaler 1 */
-#else
-#define REG_AC1_CTRLA              (*(RwReg8 *)0x42005400U) /**< \brief (AC1) Control A */
-#define REG_AC1_CTRLB              (*(WoReg8 *)0x42005401U) /**< \brief (AC1) Control B */
-#define REG_AC1_EVCTRL             (*(RwReg16*)0x42005402U) /**< \brief (AC1) Event Control */
-#define REG_AC1_INTENCLR           (*(RwReg8 *)0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
-#define REG_AC1_INTENSET           (*(RwReg8 *)0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
-#define REG_AC1_INTFLAG            (*(RwReg8 *)0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
-#define REG_AC1_STATUSA            (*(RoReg8 *)0x42005408U) /**< \brief (AC1) Status A */
-#define REG_AC1_STATUSB            (*(RoReg8 *)0x42005409U) /**< \brief (AC1) Status B */
-#define REG_AC1_STATUSC            (*(RoReg8 *)0x4200540AU) /**< \brief (AC1) Status C */
-#define REG_AC1_WINCTRL            (*(RwReg8 *)0x4200540CU) /**< \brief (AC1) Window Control */
-#define REG_AC1_COMPCTRL0          (*(RwReg  *)0x42005410U) /**< \brief (AC1) Comparator Control 0 */
-#define REG_AC1_COMPCTRL1          (*(RwReg  *)0x42005414U) /**< \brief (AC1) Comparator Control 1 */
-#define REG_AC1_SCALER0            (*(RwReg8 *)0x42005420U) /**< \brief (AC1) Scaler 0 */
-#define REG_AC1_SCALER1            (*(RwReg8 *)0x42005421U) /**< \brief (AC1) Scaler 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for AC1 peripheral ========== */
-#define AC1_CMP_NUM                 2        // Number of comparators
-#define AC1_GCLK_ID_ANA             32       // Index of Generic Clock for analog
-#define AC1_GCLK_ID_DIG             31       // Index of Generic Clock for digital
-#define AC1_NUM_CMP                 2       
-#define AC1_PAIRS                   1        // Number of pairs of comparators
-
-#endif /* _SAMD21_AC1_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for AC1
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC1_INSTANCE_
+#define _SAMD21_AC1_INSTANCE_
+
+/* ========== Register definition for AC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC1_CTRLA              (0x42005400U) /**< \brief (AC1) Control A */
+#define REG_AC1_CTRLB              (0x42005401U) /**< \brief (AC1) Control B */
+#define REG_AC1_EVCTRL             (0x42005402U) /**< \brief (AC1) Event Control */
+#define REG_AC1_INTENCLR           (0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
+#define REG_AC1_INTENSET           (0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
+#define REG_AC1_INTFLAG            (0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
+#define REG_AC1_STATUSA            (0x42005408U) /**< \brief (AC1) Status A */
+#define REG_AC1_STATUSB            (0x42005409U) /**< \brief (AC1) Status B */
+#define REG_AC1_STATUSC            (0x4200540AU) /**< \brief (AC1) Status C */
+#define REG_AC1_WINCTRL            (0x4200540CU) /**< \brief (AC1) Window Control */
+#define REG_AC1_COMPCTRL0          (0x42005410U) /**< \brief (AC1) Comparator Control 0 */
+#define REG_AC1_COMPCTRL1          (0x42005414U) /**< \brief (AC1) Comparator Control 1 */
+#define REG_AC1_SCALER0            (0x42005420U) /**< \brief (AC1) Scaler 0 */
+#define REG_AC1_SCALER1            (0x42005421U) /**< \brief (AC1) Scaler 1 */
+#else
+#define REG_AC1_CTRLA              (*(RwReg8 *)0x42005400U) /**< \brief (AC1) Control A */
+#define REG_AC1_CTRLB              (*(WoReg8 *)0x42005401U) /**< \brief (AC1) Control B */
+#define REG_AC1_EVCTRL             (*(RwReg16*)0x42005402U) /**< \brief (AC1) Event Control */
+#define REG_AC1_INTENCLR           (*(RwReg8 *)0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
+#define REG_AC1_INTENSET           (*(RwReg8 *)0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
+#define REG_AC1_INTFLAG            (*(RwReg8 *)0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
+#define REG_AC1_STATUSA            (*(RoReg8 *)0x42005408U) /**< \brief (AC1) Status A */
+#define REG_AC1_STATUSB            (*(RoReg8 *)0x42005409U) /**< \brief (AC1) Status B */
+#define REG_AC1_STATUSC            (*(RoReg8 *)0x4200540AU) /**< \brief (AC1) Status C */
+#define REG_AC1_WINCTRL            (*(RwReg8 *)0x4200540CU) /**< \brief (AC1) Window Control */
+#define REG_AC1_COMPCTRL0          (*(RwReg  *)0x42005410U) /**< \brief (AC1) Comparator Control 0 */
+#define REG_AC1_COMPCTRL1          (*(RwReg  *)0x42005414U) /**< \brief (AC1) Comparator Control 1 */
+#define REG_AC1_SCALER0            (*(RwReg8 *)0x42005420U) /**< \brief (AC1) Scaler 0 */
+#define REG_AC1_SCALER1            (*(RwReg8 *)0x42005421U) /**< \brief (AC1) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC1 peripheral ========== */
+#define AC1_CMP_NUM                 2        // Number of comparators
+#define AC1_GCLK_ID_ANA             32       // Index of Generic Clock for analog
+#define AC1_GCLK_ID_DIG             31       // Index of Generic Clock for digital
+#define AC1_NUM_CMP                 2       
+#define AC1_PAIRS                   1        // Number of pairs of comparators
+
+#endif /* _SAMD21_AC1_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h
index 18cef20..681bc60 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h
@@ -1,89 +1,89 @@
-/**
- * \file
- *
- * \brief Instance description for ADC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_ADC_INSTANCE_
-#define _SAMD21_ADC_INSTANCE_
-
-/* ========== Register definition for ADC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_ADC_CTRLA              (0x42004000U) /**< \brief (ADC) Control A */
-#define REG_ADC_REFCTRL            (0x42004001U) /**< \brief (ADC) Reference Control */
-#define REG_ADC_AVGCTRL            (0x42004002U) /**< \brief (ADC) Average Control */
-#define REG_ADC_SAMPCTRL           (0x42004003U) /**< \brief (ADC) Sampling Time Control */
-#define REG_ADC_CTRLB              (0x42004004U) /**< \brief (ADC) Control B */
-#define REG_ADC_WINCTRL            (0x42004008U) /**< \brief (ADC) Window Monitor Control */
-#define REG_ADC_SWTRIG             (0x4200400CU) /**< \brief (ADC) Software Trigger */
-#define REG_ADC_INPUTCTRL          (0x42004010U) /**< \brief (ADC) Input Control */
-#define REG_ADC_EVCTRL             (0x42004014U) /**< \brief (ADC) Event Control */
-#define REG_ADC_INTENCLR           (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
-#define REG_ADC_INTENSET           (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
-#define REG_ADC_INTFLAG            (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
-#define REG_ADC_STATUS             (0x42004019U) /**< \brief (ADC) Status */
-#define REG_ADC_RESULT             (0x4200401AU) /**< \brief (ADC) Result */
-#define REG_ADC_WINLT              (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
-#define REG_ADC_WINUT              (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
-#define REG_ADC_GAINCORR           (0x42004024U) /**< \brief (ADC) Gain Correction */
-#define REG_ADC_OFFSETCORR         (0x42004026U) /**< \brief (ADC) Offset Correction */
-#define REG_ADC_CALIB              (0x42004028U) /**< \brief (ADC) Calibration */
-#define REG_ADC_DBGCTRL            (0x4200402AU) /**< \brief (ADC) Debug Control */
-#else
-#define REG_ADC_CTRLA              (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
-#define REG_ADC_REFCTRL            (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
-#define REG_ADC_AVGCTRL            (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
-#define REG_ADC_SAMPCTRL           (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
-#define REG_ADC_CTRLB              (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
-#define REG_ADC_WINCTRL            (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
-#define REG_ADC_SWTRIG             (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
-#define REG_ADC_INPUTCTRL          (*(RwReg  *)0x42004010U) /**< \brief (ADC) Input Control */
-#define REG_ADC_EVCTRL             (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
-#define REG_ADC_INTENCLR           (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
-#define REG_ADC_INTENSET           (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
-#define REG_ADC_INTFLAG            (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
-#define REG_ADC_STATUS             (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
-#define REG_ADC_RESULT             (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
-#define REG_ADC_WINLT              (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
-#define REG_ADC_WINUT              (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
-#define REG_ADC_GAINCORR           (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
-#define REG_ADC_OFFSETCORR         (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
-#define REG_ADC_CALIB              (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
-#define REG_ADC_DBGCTRL            (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for ADC peripheral ========== */
-#define ADC_DMAC_ID_RESRDY          39       // Index of DMA RESRDY trigger
-#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
-#define ADC_GCLK_ID                 30       // Index of Generic Clock
-#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
-#define ADC_RESULT_MSB              15       // Size of Result
-
-#endif /* _SAMD21_ADC_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_INSTANCE_
+#define _SAMD21_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA              (0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL             (0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (0x4200402AU) /**< \brief (ADC) Debug Control */
+#else
+#define REG_ADC_CTRLA              (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (*(RwReg  *)0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL             (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_DMAC_ID_RESRDY          39       // Index of DMA RESRDY trigger
+#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
+#define ADC_GCLK_ID                 30       // Index of Generic Clock
+#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
+#define ADC_RESULT_MSB              15       // Size of Result
+
+#endif /* _SAMD21_ADC_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h
index 5d8b3d5..2558322 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h
@@ -1,64 +1,64 @@
-/**
- * \file
- *
- * \brief Instance description for DAC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_DAC_INSTANCE_
-#define _SAMD21_DAC_INSTANCE_
-
-/* ========== Register definition for DAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_DAC_CTRLA              (0x42004800U) /**< \brief (DAC) Control A */
-#define REG_DAC_CTRLB              (0x42004801U) /**< \brief (DAC) Control B */
-#define REG_DAC_EVCTRL             (0x42004802U) /**< \brief (DAC) Event Control */
-#define REG_DAC_INTENCLR           (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
-#define REG_DAC_INTENSET           (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
-#define REG_DAC_INTFLAG            (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
-#define REG_DAC_STATUS             (0x42004807U) /**< \brief (DAC) Status */
-#define REG_DAC_DATA               (0x42004808U) /**< \brief (DAC) Data */
-#define REG_DAC_DATABUF            (0x4200480CU) /**< \brief (DAC) Data Buffer */
-#else
-#define REG_DAC_CTRLA              (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
-#define REG_DAC_CTRLB              (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
-#define REG_DAC_EVCTRL             (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
-#define REG_DAC_INTENCLR           (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
-#define REG_DAC_INTENSET           (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
-#define REG_DAC_INTFLAG            (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
-#define REG_DAC_STATUS             (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
-#define REG_DAC_DATA               (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
-#define REG_DAC_DATABUF            (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for DAC peripheral ========== */
-#define DAC_DMAC_ID_EMPTY           40       // Index of DMAC EMPTY trigger
-#define DAC_GCLK_ID                 33       // Index of Generic Clock
-
-#endif /* _SAMD21_DAC_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_INSTANCE_
+#define _SAMD21_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA              (0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (0x4200480CU) /**< \brief (DAC) Data Buffer */
+#else
+#define REG_DAC_CTRLA              (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_DMAC_ID_EMPTY           40       // Index of DMAC EMPTY trigger
+#define DAC_GCLK_ID                 33       // Index of Generic Clock
+
+#endif /* _SAMD21_DAC_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h
index d25c7fc..d57099e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h
@@ -1,99 +1,99 @@
-/**
- * \file
- *
- * \brief Instance description for DMAC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_DMAC_INSTANCE_
-#define _SAMD21_DMAC_INSTANCE_
-
-/* ========== Register definition for DMAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_DMAC_CTRL              (0x41004800U) /**< \brief (DMAC) Control */
-#define REG_DMAC_CRCCTRL           (0x41004802U) /**< \brief (DMAC) CRC Control */
-#define REG_DMAC_CRCDATAIN         (0x41004804U) /**< \brief (DMAC) CRC Data Input */
-#define REG_DMAC_CRCCHKSUM         (0x41004808U) /**< \brief (DMAC) CRC Checksum */
-#define REG_DMAC_CRCSTATUS         (0x4100480CU) /**< \brief (DMAC) CRC Status */
-#define REG_DMAC_DBGCTRL           (0x4100480DU) /**< \brief (DMAC) Debug Control */
-#define REG_DMAC_QOSCTRL           (0x4100480EU) /**< \brief (DMAC) QOS Control */
-#define REG_DMAC_SWTRIGCTRL        (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
-#define REG_DMAC_PRICTRL0          (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
-#define REG_DMAC_INTPEND           (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
-#define REG_DMAC_INTSTATUS         (0x41004824U) /**< \brief (DMAC) Interrupt Status */
-#define REG_DMAC_BUSYCH            (0x41004828U) /**< \brief (DMAC) Busy Channels */
-#define REG_DMAC_PENDCH            (0x4100482CU) /**< \brief (DMAC) Pending Channels */
-#define REG_DMAC_ACTIVE            (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
-#define REG_DMAC_BASEADDR          (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
-#define REG_DMAC_WRBADDR           (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
-#define REG_DMAC_CHID              (0x4100483FU) /**< \brief (DMAC) Channel ID */
-#define REG_DMAC_CHCTRLA           (0x41004840U) /**< \brief (DMAC) Channel Control A */
-#define REG_DMAC_CHCTRLB           (0x41004844U) /**< \brief (DMAC) Channel Control B */
-#define REG_DMAC_CHINTENCLR        (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET        (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG         (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS          (0x4100484FU) /**< \brief (DMAC) Channel Status */
-#else
-#define REG_DMAC_CTRL              (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
-#define REG_DMAC_CRCCTRL           (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
-#define REG_DMAC_CRCDATAIN         (*(RwReg  *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
-#define REG_DMAC_CRCCHKSUM         (*(RwReg  *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
-#define REG_DMAC_CRCSTATUS         (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
-#define REG_DMAC_DBGCTRL           (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
-#define REG_DMAC_QOSCTRL           (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
-#define REG_DMAC_SWTRIGCTRL        (*(RwReg  *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
-#define REG_DMAC_PRICTRL0          (*(RwReg  *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
-#define REG_DMAC_INTPEND           (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
-#define REG_DMAC_INTSTATUS         (*(RoReg  *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
-#define REG_DMAC_BUSYCH            (*(RoReg  *)0x41004828U) /**< \brief (DMAC) Busy Channels */
-#define REG_DMAC_PENDCH            (*(RoReg  *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
-#define REG_DMAC_ACTIVE            (*(RoReg  *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
-#define REG_DMAC_BASEADDR          (*(RwReg  *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
-#define REG_DMAC_WRBADDR           (*(RwReg  *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
-#define REG_DMAC_CHID              (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
-#define REG_DMAC_CHCTRLA           (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
-#define REG_DMAC_CHCTRLB           (*(RwReg  *)0x41004844U) /**< \brief (DMAC) Channel Control B */
-#define REG_DMAC_CHINTENCLR        (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET        (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG         (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS          (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for DMAC peripheral ========== */
-#define DMAC_CH_BITS                4        // Number of bits to select channel
-#define DMAC_CH_NUM                 12       // Number of channels
-#define DMAC_CLK_AHB_ID             5        // AHB clock index
-#define DMAC_EVIN_NUM               4        // Number of input events
-#define DMAC_EVOUT_NUM              4        // Number of output events
-#define DMAC_LVL_BITS               2        // Number of bit to select level priority
-#define DMAC_LVL_NUM                4        // Enable priority level number
-#define DMAC_TRIG_BITS              6        // Number of bits to select trigger source
-#define DMAC_TRIG_NUM               45       // Number of peripheral triggers
-
-#endif /* _SAMD21_DMAC_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_INSTANCE_
+#define _SAMD21_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL              (0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL           (0x4100480EU) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL        (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID              (0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA           (0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB           (0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR        (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET        (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG         (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS          (0x4100484FU) /**< \brief (DMAC) Channel Status */
+#else
+#define REG_DMAC_CTRL              (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (*(RwReg  *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (*(RwReg  *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL           (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL        (*(RwReg  *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (*(RwReg  *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (*(RoReg  *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (*(RoReg  *)0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (*(RoReg  *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (*(RoReg  *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (*(RwReg  *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (*(RwReg  *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID              (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA           (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB           (*(RwReg  *)0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR        (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET        (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG         (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS          (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_CH_BITS                4        // Number of bits to select channel
+#define DMAC_CH_NUM                 12       // Number of channels
+#define DMAC_CLK_AHB_ID             5        // AHB clock index
+#define DMAC_EVIN_NUM               4        // Number of input events
+#define DMAC_EVOUT_NUM              4        // Number of output events
+#define DMAC_LVL_BITS               2        // Number of bit to select level priority
+#define DMAC_LVL_NUM                4        // Enable priority level number
+#define DMAC_TRIG_BITS              6        // Number of bits to select trigger source
+#define DMAC_TRIG_NUM               45       // Number of peripheral triggers
+
+#endif /* _SAMD21_DMAC_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h
index 08cdc17..4fbb6e8 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h
@@ -1,89 +1,89 @@
-/**
- * \file
- *
- * \brief Instance description for DSU
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_DSU_INSTANCE_
-#define _SAMD21_DSU_INSTANCE_
-
-/* ========== Register definition for DSU peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_DSU_CTRL               (0x41002000U) /**< \brief (DSU) Control */
-#define REG_DSU_STATUSA            (0x41002001U) /**< \brief (DSU) Status A */
-#define REG_DSU_STATUSB            (0x41002002U) /**< \brief (DSU) Status B */
-#define REG_DSU_ADDR               (0x41002004U) /**< \brief (DSU) Address */
-#define REG_DSU_LENGTH             (0x41002008U) /**< \brief (DSU) Length */
-#define REG_DSU_DATA               (0x4100200CU) /**< \brief (DSU) Data */
-#define REG_DSU_DCC0               (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
-#define REG_DSU_DCC1               (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
-#define REG_DSU_DID                (0x41002018U) /**< \brief (DSU) Device Identification */
-#define REG_DSU_ENTRY0             (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
-#define REG_DSU_ENTRY1             (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
-#define REG_DSU_END                (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
-#define REG_DSU_MEMTYPE            (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
-#define REG_DSU_PID4               (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
-#define REG_DSU_PID0               (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
-#define REG_DSU_PID1               (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
-#define REG_DSU_PID2               (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
-#define REG_DSU_PID3               (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
-#define REG_DSU_CID0               (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
-#define REG_DSU_CID1               (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
-#define REG_DSU_CID2               (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
-#define REG_DSU_CID3               (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
-#else
-#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
-#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
-#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
-#define REG_DSU_ADDR               (*(RwReg  *)0x41002004U) /**< \brief (DSU) Address */
-#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008U) /**< \brief (DSU) Length */
-#define REG_DSU_DATA               (*(RwReg  *)0x4100200CU) /**< \brief (DSU) Data */
-#define REG_DSU_DCC0               (*(RwReg  *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
-#define REG_DSU_DCC1               (*(RwReg  *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
-#define REG_DSU_DID                (*(RoReg  *)0x41002018U) /**< \brief (DSU) Device Identification */
-#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
-#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
-#define REG_DSU_END                (*(RoReg  *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
-#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
-#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
-#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
-#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
-#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
-#define REG_DSU_PID3               (*(RoReg  *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
-#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
-#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
-#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
-#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for DSU peripheral ========== */
-#define DSU_CLK_HSB_ID              3        // Index of AHB clock in PM.AHBMASK register
-
-#endif /* _SAMD21_DSU_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_INSTANCE_
+#define _SAMD21_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL               (0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0             (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0               (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (*(RwReg  *)0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (*(RwReg  *)0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (*(RwReg  *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (*(RwReg  *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (*(RoReg  *)0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (*(RoReg  *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (*(RoReg  *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_HSB_ID              3        // Index of AHB clock in PM.AHBMASK register
+
+#endif /* _SAMD21_DSU_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h
index 13f86c8..291d0df 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h
@@ -1,68 +1,68 @@
-/**
- * \file
- *
- * \brief Instance description for EIC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_EIC_INSTANCE_
-#define _SAMD21_EIC_INSTANCE_
-
-/* ========== Register definition for EIC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_EIC_CTRL               (0x40001800U) /**< \brief (EIC) Control */
-#define REG_EIC_STATUS             (0x40001801U) /**< \brief (EIC) Status */
-#define REG_EIC_NMICTRL            (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
-#define REG_EIC_NMIFLAG            (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
-#define REG_EIC_EVCTRL             (0x40001804U) /**< \brief (EIC) Event Control */
-#define REG_EIC_INTENCLR           (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
-#define REG_EIC_INTENSET           (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
-#define REG_EIC_INTFLAG            (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
-#define REG_EIC_WAKEUP             (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
-#define REG_EIC_CONFIG0            (0x40001818U) /**< \brief (EIC) Configuration 0 */
-#define REG_EIC_CONFIG1            (0x4000181CU) /**< \brief (EIC) Configuration 1 */
-#else
-#define REG_EIC_CTRL               (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
-#define REG_EIC_STATUS             (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
-#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
-#define REG_EIC_NMIFLAG            (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
-#define REG_EIC_EVCTRL             (*(RwReg  *)0x40001804U) /**< \brief (EIC) Event Control */
-#define REG_EIC_INTENCLR           (*(RwReg  *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
-#define REG_EIC_INTENSET           (*(RwReg  *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
-#define REG_EIC_INTFLAG            (*(RwReg  *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
-#define REG_EIC_WAKEUP             (*(RwReg  *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
-#define REG_EIC_CONFIG0            (*(RwReg  *)0x40001818U) /**< \brief (EIC) Configuration 0 */
-#define REG_EIC_CONFIG1            (*(RwReg  *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for EIC peripheral ========== */
-#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
-#define EIC_GCLK_ID                 5        // Index of Generic Clock
-
-#endif /* _SAMD21_EIC_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_INSTANCE_
+#define _SAMD21_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRL               (0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRL               (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (*(RwReg  *)0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (*(RwReg  *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (*(RwReg  *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (*(RwReg  *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (*(RwReg  *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (*(RwReg  *)0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (*(RwReg  *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
+#define EIC_GCLK_ID                 5        // Index of Generic Clock
+
+#endif /* _SAMD21_EIC_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h
index 273311e..be3414a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h
@@ -1,192 +1,192 @@
-/**
- * \file
- *
- * \brief Instance description for EVSYS
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_EVSYS_INSTANCE_
-#define _SAMD21_EVSYS_INSTANCE_
-
-/* ========== Register definition for EVSYS peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_EVSYS_CTRL             (0x42000400U) /**< \brief (EVSYS) Control */
-#define REG_EVSYS_CHANNEL          (0x42000404U) /**< \brief (EVSYS) Channel */
-#define REG_EVSYS_USER             (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
-#define REG_EVSYS_CHSTATUS         (0x4200040CU) /**< \brief (EVSYS) Channel Status */
-#define REG_EVSYS_INTENCLR         (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
-#define REG_EVSYS_INTENSET         (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
-#define REG_EVSYS_INTFLAG          (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
-#else
-#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
-#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404U) /**< \brief (EVSYS) Channel */
-#define REG_EVSYS_USER             (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
-#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
-#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
-#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
-#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for EVSYS peripheral ========== */
-#define EVSYS_CHANNELS              12       // Number of Channels
-#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
-#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
-#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
-#define EVSYS_GCLK_ID_0             7
-#define EVSYS_GCLK_ID_1             8
-#define EVSYS_GCLK_ID_2             9
-#define EVSYS_GCLK_ID_3             10
-#define EVSYS_GCLK_ID_4             11
-#define EVSYS_GCLK_ID_5             12
-#define EVSYS_GCLK_ID_6             13
-#define EVSYS_GCLK_ID_7             14
-#define EVSYS_GCLK_ID_8             15
-#define EVSYS_GCLK_ID_9             16
-#define EVSYS_GCLK_ID_10            17
-#define EVSYS_GCLK_ID_11            18
-#define EVSYS_GCLK_ID_LSB           7
-#define EVSYS_GCLK_ID_MSB           18
-#define EVSYS_GCLK_ID_SIZE          12
-#define EVSYS_GENERATORS            76       // Total Number of Event Generators
-#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
-#define EVSYS_USERS                 31       // Total Number of Event Users
-#define EVSYS_USERS_BITS            5        // Number of bits to select Event User
-
-// GENERATORS
-#define EVSYS_ID_GEN_RTC_CMP_0      1
-#define EVSYS_ID_GEN_RTC_CMP_1      2
-#define EVSYS_ID_GEN_RTC_OVF        3
-#define EVSYS_ID_GEN_RTC_PER_0      4
-#define EVSYS_ID_GEN_RTC_PER_1      5
-#define EVSYS_ID_GEN_RTC_PER_2      6
-#define EVSYS_ID_GEN_RTC_PER_3      7
-#define EVSYS_ID_GEN_RTC_PER_4      8
-#define EVSYS_ID_GEN_RTC_PER_5      9
-#define EVSYS_ID_GEN_RTC_PER_6      10
-#define EVSYS_ID_GEN_RTC_PER_7      11
-#define EVSYS_ID_GEN_EIC_EXTINT_0   12
-#define EVSYS_ID_GEN_EIC_EXTINT_1   13
-#define EVSYS_ID_GEN_EIC_EXTINT_2   14
-#define EVSYS_ID_GEN_EIC_EXTINT_3   15
-#define EVSYS_ID_GEN_EIC_EXTINT_4   16
-#define EVSYS_ID_GEN_EIC_EXTINT_5   17
-#define EVSYS_ID_GEN_EIC_EXTINT_6   18
-#define EVSYS_ID_GEN_EIC_EXTINT_7   19
-#define EVSYS_ID_GEN_EIC_EXTINT_8   20
-#define EVSYS_ID_GEN_EIC_EXTINT_9   21
-#define EVSYS_ID_GEN_EIC_EXTINT_10  22
-#define EVSYS_ID_GEN_EIC_EXTINT_11  23
-#define EVSYS_ID_GEN_EIC_EXTINT_12  24
-#define EVSYS_ID_GEN_EIC_EXTINT_13  25
-#define EVSYS_ID_GEN_EIC_EXTINT_14  26
-#define EVSYS_ID_GEN_EIC_EXTINT_15  27
-#define EVSYS_ID_GEN_EIC_EXTINT_16  28
-#define EVSYS_ID_GEN_EIC_EXTINT_17  29
-#define EVSYS_ID_GEN_DMAC_CH_0      30
-#define EVSYS_ID_GEN_DMAC_CH_1      31
-#define EVSYS_ID_GEN_DMAC_CH_2      32
-#define EVSYS_ID_GEN_DMAC_CH_3      33
-#define EVSYS_ID_GEN_TCC0_OVF       34
-#define EVSYS_ID_GEN_TCC0_TRG       35
-#define EVSYS_ID_GEN_TCC0_CNT       36
-#define EVSYS_ID_GEN_TCC0_MCX_0     37
-#define EVSYS_ID_GEN_TCC0_MCX_1     38
-#define EVSYS_ID_GEN_TCC0_MCX_2     39
-#define EVSYS_ID_GEN_TCC0_MCX_3     40
-#define EVSYS_ID_GEN_TCC1_OVF       41
-#define EVSYS_ID_GEN_TCC1_TRG       42
-#define EVSYS_ID_GEN_TCC1_CNT       43
-#define EVSYS_ID_GEN_TCC1_MCX_0     44
-#define EVSYS_ID_GEN_TCC1_MCX_1     45
-#define EVSYS_ID_GEN_TCC2_OVF       46
-#define EVSYS_ID_GEN_TCC2_TRG       47
-#define EVSYS_ID_GEN_TCC2_CNT       48
-#define EVSYS_ID_GEN_TCC2_MCX_0     49
-#define EVSYS_ID_GEN_TCC2_MCX_1     50
-#define EVSYS_ID_GEN_TC3_OVF        51
-#define EVSYS_ID_GEN_TC3_MCX_0      52
-#define EVSYS_ID_GEN_TC3_MCX_1      53
-#define EVSYS_ID_GEN_TC4_OVF        54
-#define EVSYS_ID_GEN_TC4_MCX_0      55
-#define EVSYS_ID_GEN_TC4_MCX_1      56
-#define EVSYS_ID_GEN_TC5_OVF        57
-#define EVSYS_ID_GEN_TC5_MCX_0      58
-#define EVSYS_ID_GEN_TC5_MCX_1      59
-#define EVSYS_ID_GEN_TC6_OVF        60
-#define EVSYS_ID_GEN_TC6_MCX_0      61
-#define EVSYS_ID_GEN_TC6_MCX_1      62
-#define EVSYS_ID_GEN_TC7_OVF        63
-#define EVSYS_ID_GEN_TC7_MCX_0      64
-#define EVSYS_ID_GEN_TC7_MCX_1      65
-#define EVSYS_ID_GEN_ADC_RESRDY     66
-#define EVSYS_ID_GEN_ADC_WINMON     67
-#define EVSYS_ID_GEN_AC_COMP_0      68
-#define EVSYS_ID_GEN_AC_COMP_1      69
-#define EVSYS_ID_GEN_AC_WIN_0       70
-#define EVSYS_ID_GEN_DAC_EMPTY      71
-#define EVSYS_ID_GEN_PTC_EOC        72
-#define EVSYS_ID_GEN_PTC_WCOMP      73
-#define EVSYS_ID_GEN_AC1_COMP_0     74
-#define EVSYS_ID_GEN_AC1_COMP_1     75
-#define EVSYS_ID_GEN_AC1_WIN_0      76
-
-// USERS
-#define EVSYS_ID_USER_DMAC_CH_0     0
-#define EVSYS_ID_USER_DMAC_CH_1     1
-#define EVSYS_ID_USER_DMAC_CH_2     2
-#define EVSYS_ID_USER_DMAC_CH_3     3
-#define EVSYS_ID_USER_TCC0_EV_0     4
-#define EVSYS_ID_USER_TCC0_EV_1     5
-#define EVSYS_ID_USER_TCC0_MC_0     6
-#define EVSYS_ID_USER_TCC0_MC_1     7
-#define EVSYS_ID_USER_TCC0_MC_2     8
-#define EVSYS_ID_USER_TCC0_MC_3     9
-#define EVSYS_ID_USER_TCC1_EV_0     10
-#define EVSYS_ID_USER_TCC1_EV_1     11
-#define EVSYS_ID_USER_TCC1_MC_0     12
-#define EVSYS_ID_USER_TCC1_MC_1     13
-#define EVSYS_ID_USER_TCC2_EV_0     14
-#define EVSYS_ID_USER_TCC2_EV_1     15
-#define EVSYS_ID_USER_TCC2_MC_0     16
-#define EVSYS_ID_USER_TCC2_MC_1     17
-#define EVSYS_ID_USER_TC3_EVU       18
-#define EVSYS_ID_USER_TC4_EVU       19
-#define EVSYS_ID_USER_TC5_EVU       20
-#define EVSYS_ID_USER_TC6_EVU       21
-#define EVSYS_ID_USER_TC7_EVU       22
-#define EVSYS_ID_USER_ADC_START     23
-#define EVSYS_ID_USER_ADC_SYNC      24
-#define EVSYS_ID_USER_AC_SOC_0      25
-#define EVSYS_ID_USER_AC_SOC_1      26
-#define EVSYS_ID_USER_DAC_START     27
-#define EVSYS_ID_USER_PTC_STCONV    28
-#define EVSYS_ID_USER_AC1_SOC_0     29
-#define EVSYS_ID_USER_AC1_SOC_1     30
-
-#endif /* _SAMD21_EVSYS_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_INSTANCE_
+#define _SAMD21_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL             (0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS              12       // Number of Channels
+#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
+#define EVSYS_GCLK_ID_0             7
+#define EVSYS_GCLK_ID_1             8
+#define EVSYS_GCLK_ID_2             9
+#define EVSYS_GCLK_ID_3             10
+#define EVSYS_GCLK_ID_4             11
+#define EVSYS_GCLK_ID_5             12
+#define EVSYS_GCLK_ID_6             13
+#define EVSYS_GCLK_ID_7             14
+#define EVSYS_GCLK_ID_8             15
+#define EVSYS_GCLK_ID_9             16
+#define EVSYS_GCLK_ID_10            17
+#define EVSYS_GCLK_ID_11            18
+#define EVSYS_GCLK_ID_LSB           7
+#define EVSYS_GCLK_ID_MSB           18
+#define EVSYS_GCLK_ID_SIZE          12
+#define EVSYS_GENERATORS            76       // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
+#define EVSYS_USERS                 31       // Total Number of Event Users
+#define EVSYS_USERS_BITS            5        // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0      1
+#define EVSYS_ID_GEN_RTC_CMP_1      2
+#define EVSYS_ID_GEN_RTC_OVF        3
+#define EVSYS_ID_GEN_RTC_PER_0      4
+#define EVSYS_ID_GEN_RTC_PER_1      5
+#define EVSYS_ID_GEN_RTC_PER_2      6
+#define EVSYS_ID_GEN_RTC_PER_3      7
+#define EVSYS_ID_GEN_RTC_PER_4      8
+#define EVSYS_ID_GEN_RTC_PER_5      9
+#define EVSYS_ID_GEN_RTC_PER_6      10
+#define EVSYS_ID_GEN_RTC_PER_7      11
+#define EVSYS_ID_GEN_EIC_EXTINT_0   12
+#define EVSYS_ID_GEN_EIC_EXTINT_1   13
+#define EVSYS_ID_GEN_EIC_EXTINT_2   14
+#define EVSYS_ID_GEN_EIC_EXTINT_3   15
+#define EVSYS_ID_GEN_EIC_EXTINT_4   16
+#define EVSYS_ID_GEN_EIC_EXTINT_5   17
+#define EVSYS_ID_GEN_EIC_EXTINT_6   18
+#define EVSYS_ID_GEN_EIC_EXTINT_7   19
+#define EVSYS_ID_GEN_EIC_EXTINT_8   20
+#define EVSYS_ID_GEN_EIC_EXTINT_9   21
+#define EVSYS_ID_GEN_EIC_EXTINT_10  22
+#define EVSYS_ID_GEN_EIC_EXTINT_11  23
+#define EVSYS_ID_GEN_EIC_EXTINT_12  24
+#define EVSYS_ID_GEN_EIC_EXTINT_13  25
+#define EVSYS_ID_GEN_EIC_EXTINT_14  26
+#define EVSYS_ID_GEN_EIC_EXTINT_15  27
+#define EVSYS_ID_GEN_EIC_EXTINT_16  28
+#define EVSYS_ID_GEN_EIC_EXTINT_17  29
+#define EVSYS_ID_GEN_DMAC_CH_0      30
+#define EVSYS_ID_GEN_DMAC_CH_1      31
+#define EVSYS_ID_GEN_DMAC_CH_2      32
+#define EVSYS_ID_GEN_DMAC_CH_3      33
+#define EVSYS_ID_GEN_TCC0_OVF       34
+#define EVSYS_ID_GEN_TCC0_TRG       35
+#define EVSYS_ID_GEN_TCC0_CNT       36
+#define EVSYS_ID_GEN_TCC0_MCX_0     37
+#define EVSYS_ID_GEN_TCC0_MCX_1     38
+#define EVSYS_ID_GEN_TCC0_MCX_2     39
+#define EVSYS_ID_GEN_TCC0_MCX_3     40
+#define EVSYS_ID_GEN_TCC1_OVF       41
+#define EVSYS_ID_GEN_TCC1_TRG       42
+#define EVSYS_ID_GEN_TCC1_CNT       43
+#define EVSYS_ID_GEN_TCC1_MCX_0     44
+#define EVSYS_ID_GEN_TCC1_MCX_1     45
+#define EVSYS_ID_GEN_TCC2_OVF       46
+#define EVSYS_ID_GEN_TCC2_TRG       47
+#define EVSYS_ID_GEN_TCC2_CNT       48
+#define EVSYS_ID_GEN_TCC2_MCX_0     49
+#define EVSYS_ID_GEN_TCC2_MCX_1     50
+#define EVSYS_ID_GEN_TC3_OVF        51
+#define EVSYS_ID_GEN_TC3_MCX_0      52
+#define EVSYS_ID_GEN_TC3_MCX_1      53
+#define EVSYS_ID_GEN_TC4_OVF        54
+#define EVSYS_ID_GEN_TC4_MCX_0      55
+#define EVSYS_ID_GEN_TC4_MCX_1      56
+#define EVSYS_ID_GEN_TC5_OVF        57
+#define EVSYS_ID_GEN_TC5_MCX_0      58
+#define EVSYS_ID_GEN_TC5_MCX_1      59
+#define EVSYS_ID_GEN_TC6_OVF        60
+#define EVSYS_ID_GEN_TC6_MCX_0      61
+#define EVSYS_ID_GEN_TC6_MCX_1      62
+#define EVSYS_ID_GEN_TC7_OVF        63
+#define EVSYS_ID_GEN_TC7_MCX_0      64
+#define EVSYS_ID_GEN_TC7_MCX_1      65
+#define EVSYS_ID_GEN_ADC_RESRDY     66
+#define EVSYS_ID_GEN_ADC_WINMON     67
+#define EVSYS_ID_GEN_AC_COMP_0      68
+#define EVSYS_ID_GEN_AC_COMP_1      69
+#define EVSYS_ID_GEN_AC_WIN_0       70
+#define EVSYS_ID_GEN_DAC_EMPTY      71
+#define EVSYS_ID_GEN_PTC_EOC        72
+#define EVSYS_ID_GEN_PTC_WCOMP      73
+#define EVSYS_ID_GEN_AC1_COMP_0     74
+#define EVSYS_ID_GEN_AC1_COMP_1     75
+#define EVSYS_ID_GEN_AC1_WIN_0      76
+
+// USERS
+#define EVSYS_ID_USER_DMAC_CH_0     0
+#define EVSYS_ID_USER_DMAC_CH_1     1
+#define EVSYS_ID_USER_DMAC_CH_2     2
+#define EVSYS_ID_USER_DMAC_CH_3     3
+#define EVSYS_ID_USER_TCC0_EV_0     4
+#define EVSYS_ID_USER_TCC0_EV_1     5
+#define EVSYS_ID_USER_TCC0_MC_0     6
+#define EVSYS_ID_USER_TCC0_MC_1     7
+#define EVSYS_ID_USER_TCC0_MC_2     8
+#define EVSYS_ID_USER_TCC0_MC_3     9
+#define EVSYS_ID_USER_TCC1_EV_0     10
+#define EVSYS_ID_USER_TCC1_EV_1     11
+#define EVSYS_ID_USER_TCC1_MC_0     12
+#define EVSYS_ID_USER_TCC1_MC_1     13
+#define EVSYS_ID_USER_TCC2_EV_0     14
+#define EVSYS_ID_USER_TCC2_EV_1     15
+#define EVSYS_ID_USER_TCC2_MC_0     16
+#define EVSYS_ID_USER_TCC2_MC_1     17
+#define EVSYS_ID_USER_TC3_EVU       18
+#define EVSYS_ID_USER_TC4_EVU       19
+#define EVSYS_ID_USER_TC5_EVU       20
+#define EVSYS_ID_USER_TC6_EVU       21
+#define EVSYS_ID_USER_TC7_EVU       22
+#define EVSYS_ID_USER_ADC_START     23
+#define EVSYS_ID_USER_ADC_SYNC      24
+#define EVSYS_ID_USER_AC_SOC_0      25
+#define EVSYS_ID_USER_AC_SOC_1      26
+#define EVSYS_ID_USER_DAC_START     27
+#define EVSYS_ID_USER_PTC_STCONV    28
+#define EVSYS_ID_USER_AC1_SOC_0     29
+#define EVSYS_ID_USER_AC1_SOC_1     30
+
+#endif /* _SAMD21_EVSYS_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h
index 39d5767..0188cee 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys_variant_d.h
@@ -1,202 +1,202 @@
-/**
- * \file
- *
- * \brief Instance description for EVSYS
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_EVSYS_INSTANCE_
-#define _SAMD21_EVSYS_INSTANCE_
-
-/* ========== Register definition for EVSYS peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_EVSYS_CTRL             (0x42000400U) /**< \brief (EVSYS) Control */
-#define REG_EVSYS_CHANNEL          (0x42000404U) /**< \brief (EVSYS) Channel */
-#define REG_EVSYS_USER             (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
-#define REG_EVSYS_CHSTATUS         (0x4200040CU) /**< \brief (EVSYS) Channel Status */
-#define REG_EVSYS_INTENCLR         (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
-#define REG_EVSYS_INTENSET         (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
-#define REG_EVSYS_INTFLAG          (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
-#else
-#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
-#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404U) /**< \brief (EVSYS) Channel */
-#define REG_EVSYS_USER             (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
-#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
-#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
-#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
-#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for EVSYS peripheral ========== */
-#define EVSYS_CHANNELS              12       // Number of Channels
-#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
-#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
-#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
-#define EVSYS_GCLK_ID_0             7
-#define EVSYS_GCLK_ID_1             8
-#define EVSYS_GCLK_ID_2             9
-#define EVSYS_GCLK_ID_3             10
-#define EVSYS_GCLK_ID_4             11
-#define EVSYS_GCLK_ID_5             12
-#define EVSYS_GCLK_ID_6             13
-#define EVSYS_GCLK_ID_7             14
-#define EVSYS_GCLK_ID_8             15
-#define EVSYS_GCLK_ID_9             16
-#define EVSYS_GCLK_ID_10            17
-#define EVSYS_GCLK_ID_11            18
-#define EVSYS_GCLK_ID_LSB           7
-#define EVSYS_GCLK_ID_MSB           18
-#define EVSYS_GCLK_ID_SIZE          12
-#define EVSYS_GENERATORS            83       // Total Number of Event Generators
-#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
-#define EVSYS_USERS                 37       // Total Number of Event Users
-#define EVSYS_USERS_BITS            6        // Number of bits to select Event User
-
-// GENERATORS
-#define EVSYS_ID_GEN_RTC_CMP_0      1
-#define EVSYS_ID_GEN_RTC_CMP_1      2
-#define EVSYS_ID_GEN_RTC_OVF        3
-#define EVSYS_ID_GEN_RTC_PER_0      4
-#define EVSYS_ID_GEN_RTC_PER_1      5
-#define EVSYS_ID_GEN_RTC_PER_2      6
-#define EVSYS_ID_GEN_RTC_PER_3      7
-#define EVSYS_ID_GEN_RTC_PER_4      8
-#define EVSYS_ID_GEN_RTC_PER_5      9
-#define EVSYS_ID_GEN_RTC_PER_6      10
-#define EVSYS_ID_GEN_RTC_PER_7      11
-#define EVSYS_ID_GEN_EIC_EXTINT_0   12
-#define EVSYS_ID_GEN_EIC_EXTINT_1   13
-#define EVSYS_ID_GEN_EIC_EXTINT_2   14
-#define EVSYS_ID_GEN_EIC_EXTINT_3   15
-#define EVSYS_ID_GEN_EIC_EXTINT_4   16
-#define EVSYS_ID_GEN_EIC_EXTINT_5   17
-#define EVSYS_ID_GEN_EIC_EXTINT_6   18
-#define EVSYS_ID_GEN_EIC_EXTINT_7   19
-#define EVSYS_ID_GEN_EIC_EXTINT_8   20
-#define EVSYS_ID_GEN_EIC_EXTINT_9   21
-#define EVSYS_ID_GEN_EIC_EXTINT_10  22
-#define EVSYS_ID_GEN_EIC_EXTINT_11  23
-#define EVSYS_ID_GEN_EIC_EXTINT_12  24
-#define EVSYS_ID_GEN_EIC_EXTINT_13  25
-#define EVSYS_ID_GEN_EIC_EXTINT_14  26
-#define EVSYS_ID_GEN_EIC_EXTINT_15  27
-#define EVSYS_ID_GEN_EIC_EXTINT_16  28
-#define EVSYS_ID_GEN_EIC_EXTINT_17  29
-#define EVSYS_ID_GEN_DMAC_CH_0      30
-#define EVSYS_ID_GEN_DMAC_CH_1      31
-#define EVSYS_ID_GEN_DMAC_CH_2      32
-#define EVSYS_ID_GEN_DMAC_CH_3      33
-#define EVSYS_ID_GEN_TCC0_OVF       34
-#define EVSYS_ID_GEN_TCC0_TRG       35
-#define EVSYS_ID_GEN_TCC0_CNT       36
-#define EVSYS_ID_GEN_TCC0_MCX_0     37
-#define EVSYS_ID_GEN_TCC0_MCX_1     38
-#define EVSYS_ID_GEN_TCC0_MCX_2     39
-#define EVSYS_ID_GEN_TCC0_MCX_3     40
-#define EVSYS_ID_GEN_TCC1_OVF       41
-#define EVSYS_ID_GEN_TCC1_TRG       42
-#define EVSYS_ID_GEN_TCC1_CNT       43
-#define EVSYS_ID_GEN_TCC1_MCX_0     44
-#define EVSYS_ID_GEN_TCC1_MCX_1     45
-#define EVSYS_ID_GEN_TCC2_OVF       46
-#define EVSYS_ID_GEN_TCC2_TRG       47
-#define EVSYS_ID_GEN_TCC2_CNT       48
-#define EVSYS_ID_GEN_TCC2_MCX_0     49
-#define EVSYS_ID_GEN_TCC2_MCX_1     50
-#define EVSYS_ID_GEN_TC3_OVF        51
-#define EVSYS_ID_GEN_TC3_MCX_0      52
-#define EVSYS_ID_GEN_TC3_MCX_1      53
-#define EVSYS_ID_GEN_TC4_OVF        54
-#define EVSYS_ID_GEN_TC4_MCX_0      55
-#define EVSYS_ID_GEN_TC4_MCX_1      56
-#define EVSYS_ID_GEN_TC5_OVF        57
-#define EVSYS_ID_GEN_TC5_MCX_0      58
-#define EVSYS_ID_GEN_TC5_MCX_1      59
-#define EVSYS_ID_GEN_TC6_OVF        60
-#define EVSYS_ID_GEN_TC6_MCX_0      61
-#define EVSYS_ID_GEN_TC6_MCX_1      62
-#define EVSYS_ID_GEN_TC7_OVF        63
-#define EVSYS_ID_GEN_TC7_MCX_0      64
-#define EVSYS_ID_GEN_TC7_MCX_1      65
-#define EVSYS_ID_GEN_ADC_RESRDY     66
-#define EVSYS_ID_GEN_ADC_WINMON     67
-#define EVSYS_ID_GEN_AC_COMP_0      68
-#define EVSYS_ID_GEN_AC_COMP_1      69
-#define EVSYS_ID_GEN_AC_WIN_0       70
-#define EVSYS_ID_GEN_DAC_EMPTY      71
-#define EVSYS_ID_GEN_AC1_COMP_0     74
-#define EVSYS_ID_GEN_AC1_COMP_1     75
-#define EVSYS_ID_GEN_AC1_WIN_0      76
-#define EVSYS_ID_GEN_TCC3_OVF       77
-#define EVSYS_ID_GEN_TCC3_TRG       78
-#define EVSYS_ID_GEN_TCC3_CNT       79
-#define EVSYS_ID_GEN_TCC3_MCX_0     80
-#define EVSYS_ID_GEN_TCC3_MCX_1     81
-#define EVSYS_ID_GEN_TCC3_MCX_2     82
-#define EVSYS_ID_GEN_TCC3_MCX_3     83
-
-// USERS
-#define EVSYS_ID_USER_DMAC_CH_0     0
-#define EVSYS_ID_USER_DMAC_CH_1     1
-#define EVSYS_ID_USER_DMAC_CH_2     2
-#define EVSYS_ID_USER_DMAC_CH_3     3
-#define EVSYS_ID_USER_TCC0_EV_0     4
-#define EVSYS_ID_USER_TCC0_EV_1     5
-#define EVSYS_ID_USER_TCC0_MC_0     6
-#define EVSYS_ID_USER_TCC0_MC_1     7
-#define EVSYS_ID_USER_TCC0_MC_2     8
-#define EVSYS_ID_USER_TCC0_MC_3     9
-#define EVSYS_ID_USER_TCC1_EV_0     10
-#define EVSYS_ID_USER_TCC1_EV_1     11
-#define EVSYS_ID_USER_TCC1_MC_0     12
-#define EVSYS_ID_USER_TCC1_MC_1     13
-#define EVSYS_ID_USER_TCC2_EV_0     14
-#define EVSYS_ID_USER_TCC2_EV_1     15
-#define EVSYS_ID_USER_TCC2_MC_0     16
-#define EVSYS_ID_USER_TCC2_MC_1     17
-#define EVSYS_ID_USER_TC3_EVU       18
-#define EVSYS_ID_USER_TC4_EVU       19
-#define EVSYS_ID_USER_TC5_EVU       20
-#define EVSYS_ID_USER_TC6_EVU       21
-#define EVSYS_ID_USER_TC7_EVU       22
-#define EVSYS_ID_USER_ADC_START     23
-#define EVSYS_ID_USER_ADC_SYNC      24
-#define EVSYS_ID_USER_AC_SOC_0      25
-#define EVSYS_ID_USER_AC_SOC_1      26
-#define EVSYS_ID_USER_DAC_START     27
-#define EVSYS_ID_USER_AC1_SOC_0     29
-#define EVSYS_ID_USER_AC1_SOC_1     30
-#define EVSYS_ID_USER_TCC3_EV_0     31
-#define EVSYS_ID_USER_TCC3_EV_1     32
-#define EVSYS_ID_USER_TCC3_MC_0     33
-#define EVSYS_ID_USER_TCC3_MC_1     34
-#define EVSYS_ID_USER_TCC3_MC_2     35
-#define EVSYS_ID_USER_TCC3_MC_3     36
-
-#endif /* _SAMD21_EVSYS_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_INSTANCE_
+#define _SAMD21_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL             (0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS              12       // Number of Channels
+#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
+#define EVSYS_GCLK_ID_0             7
+#define EVSYS_GCLK_ID_1             8
+#define EVSYS_GCLK_ID_2             9
+#define EVSYS_GCLK_ID_3             10
+#define EVSYS_GCLK_ID_4             11
+#define EVSYS_GCLK_ID_5             12
+#define EVSYS_GCLK_ID_6             13
+#define EVSYS_GCLK_ID_7             14
+#define EVSYS_GCLK_ID_8             15
+#define EVSYS_GCLK_ID_9             16
+#define EVSYS_GCLK_ID_10            17
+#define EVSYS_GCLK_ID_11            18
+#define EVSYS_GCLK_ID_LSB           7
+#define EVSYS_GCLK_ID_MSB           18
+#define EVSYS_GCLK_ID_SIZE          12
+#define EVSYS_GENERATORS            83       // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
+#define EVSYS_USERS                 37       // Total Number of Event Users
+#define EVSYS_USERS_BITS            6        // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0      1
+#define EVSYS_ID_GEN_RTC_CMP_1      2
+#define EVSYS_ID_GEN_RTC_OVF        3
+#define EVSYS_ID_GEN_RTC_PER_0      4
+#define EVSYS_ID_GEN_RTC_PER_1      5
+#define EVSYS_ID_GEN_RTC_PER_2      6
+#define EVSYS_ID_GEN_RTC_PER_3      7
+#define EVSYS_ID_GEN_RTC_PER_4      8
+#define EVSYS_ID_GEN_RTC_PER_5      9
+#define EVSYS_ID_GEN_RTC_PER_6      10
+#define EVSYS_ID_GEN_RTC_PER_7      11
+#define EVSYS_ID_GEN_EIC_EXTINT_0   12
+#define EVSYS_ID_GEN_EIC_EXTINT_1   13
+#define EVSYS_ID_GEN_EIC_EXTINT_2   14
+#define EVSYS_ID_GEN_EIC_EXTINT_3   15
+#define EVSYS_ID_GEN_EIC_EXTINT_4   16
+#define EVSYS_ID_GEN_EIC_EXTINT_5   17
+#define EVSYS_ID_GEN_EIC_EXTINT_6   18
+#define EVSYS_ID_GEN_EIC_EXTINT_7   19
+#define EVSYS_ID_GEN_EIC_EXTINT_8   20
+#define EVSYS_ID_GEN_EIC_EXTINT_9   21
+#define EVSYS_ID_GEN_EIC_EXTINT_10  22
+#define EVSYS_ID_GEN_EIC_EXTINT_11  23
+#define EVSYS_ID_GEN_EIC_EXTINT_12  24
+#define EVSYS_ID_GEN_EIC_EXTINT_13  25
+#define EVSYS_ID_GEN_EIC_EXTINT_14  26
+#define EVSYS_ID_GEN_EIC_EXTINT_15  27
+#define EVSYS_ID_GEN_EIC_EXTINT_16  28
+#define EVSYS_ID_GEN_EIC_EXTINT_17  29
+#define EVSYS_ID_GEN_DMAC_CH_0      30
+#define EVSYS_ID_GEN_DMAC_CH_1      31
+#define EVSYS_ID_GEN_DMAC_CH_2      32
+#define EVSYS_ID_GEN_DMAC_CH_3      33
+#define EVSYS_ID_GEN_TCC0_OVF       34
+#define EVSYS_ID_GEN_TCC0_TRG       35
+#define EVSYS_ID_GEN_TCC0_CNT       36
+#define EVSYS_ID_GEN_TCC0_MCX_0     37
+#define EVSYS_ID_GEN_TCC0_MCX_1     38
+#define EVSYS_ID_GEN_TCC0_MCX_2     39
+#define EVSYS_ID_GEN_TCC0_MCX_3     40
+#define EVSYS_ID_GEN_TCC1_OVF       41
+#define EVSYS_ID_GEN_TCC1_TRG       42
+#define EVSYS_ID_GEN_TCC1_CNT       43
+#define EVSYS_ID_GEN_TCC1_MCX_0     44
+#define EVSYS_ID_GEN_TCC1_MCX_1     45
+#define EVSYS_ID_GEN_TCC2_OVF       46
+#define EVSYS_ID_GEN_TCC2_TRG       47
+#define EVSYS_ID_GEN_TCC2_CNT       48
+#define EVSYS_ID_GEN_TCC2_MCX_0     49
+#define EVSYS_ID_GEN_TCC2_MCX_1     50
+#define EVSYS_ID_GEN_TC3_OVF        51
+#define EVSYS_ID_GEN_TC3_MCX_0      52
+#define EVSYS_ID_GEN_TC3_MCX_1      53
+#define EVSYS_ID_GEN_TC4_OVF        54
+#define EVSYS_ID_GEN_TC4_MCX_0      55
+#define EVSYS_ID_GEN_TC4_MCX_1      56
+#define EVSYS_ID_GEN_TC5_OVF        57
+#define EVSYS_ID_GEN_TC5_MCX_0      58
+#define EVSYS_ID_GEN_TC5_MCX_1      59
+#define EVSYS_ID_GEN_TC6_OVF        60
+#define EVSYS_ID_GEN_TC6_MCX_0      61
+#define EVSYS_ID_GEN_TC6_MCX_1      62
+#define EVSYS_ID_GEN_TC7_OVF        63
+#define EVSYS_ID_GEN_TC7_MCX_0      64
+#define EVSYS_ID_GEN_TC7_MCX_1      65
+#define EVSYS_ID_GEN_ADC_RESRDY     66
+#define EVSYS_ID_GEN_ADC_WINMON     67
+#define EVSYS_ID_GEN_AC_COMP_0      68
+#define EVSYS_ID_GEN_AC_COMP_1      69
+#define EVSYS_ID_GEN_AC_WIN_0       70
+#define EVSYS_ID_GEN_DAC_EMPTY      71
+#define EVSYS_ID_GEN_AC1_COMP_0     74
+#define EVSYS_ID_GEN_AC1_COMP_1     75
+#define EVSYS_ID_GEN_AC1_WIN_0      76
+#define EVSYS_ID_GEN_TCC3_OVF       77
+#define EVSYS_ID_GEN_TCC3_TRG       78
+#define EVSYS_ID_GEN_TCC3_CNT       79
+#define EVSYS_ID_GEN_TCC3_MCX_0     80
+#define EVSYS_ID_GEN_TCC3_MCX_1     81
+#define EVSYS_ID_GEN_TCC3_MCX_2     82
+#define EVSYS_ID_GEN_TCC3_MCX_3     83
+
+// USERS
+#define EVSYS_ID_USER_DMAC_CH_0     0
+#define EVSYS_ID_USER_DMAC_CH_1     1
+#define EVSYS_ID_USER_DMAC_CH_2     2
+#define EVSYS_ID_USER_DMAC_CH_3     3
+#define EVSYS_ID_USER_TCC0_EV_0     4
+#define EVSYS_ID_USER_TCC0_EV_1     5
+#define EVSYS_ID_USER_TCC0_MC_0     6
+#define EVSYS_ID_USER_TCC0_MC_1     7
+#define EVSYS_ID_USER_TCC0_MC_2     8
+#define EVSYS_ID_USER_TCC0_MC_3     9
+#define EVSYS_ID_USER_TCC1_EV_0     10
+#define EVSYS_ID_USER_TCC1_EV_1     11
+#define EVSYS_ID_USER_TCC1_MC_0     12
+#define EVSYS_ID_USER_TCC1_MC_1     13
+#define EVSYS_ID_USER_TCC2_EV_0     14
+#define EVSYS_ID_USER_TCC2_EV_1     15
+#define EVSYS_ID_USER_TCC2_MC_0     16
+#define EVSYS_ID_USER_TCC2_MC_1     17
+#define EVSYS_ID_USER_TC3_EVU       18
+#define EVSYS_ID_USER_TC4_EVU       19
+#define EVSYS_ID_USER_TC5_EVU       20
+#define EVSYS_ID_USER_TC6_EVU       21
+#define EVSYS_ID_USER_TC7_EVU       22
+#define EVSYS_ID_USER_ADC_START     23
+#define EVSYS_ID_USER_ADC_SYNC      24
+#define EVSYS_ID_USER_AC_SOC_0      25
+#define EVSYS_ID_USER_AC_SOC_1      26
+#define EVSYS_ID_USER_DAC_START     27
+#define EVSYS_ID_USER_AC1_SOC_0     29
+#define EVSYS_ID_USER_AC1_SOC_1     30
+#define EVSYS_ID_USER_TCC3_EV_0     31
+#define EVSYS_ID_USER_TCC3_EV_1     32
+#define EVSYS_ID_USER_TCC3_MC_0     33
+#define EVSYS_ID_USER_TCC3_MC_1     34
+#define EVSYS_ID_USER_TCC3_MC_2     35
+#define EVSYS_ID_USER_TCC3_MC_3     36
+
+#endif /* _SAMD21_EVSYS_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h
index 448f551..979b502 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h
@@ -1,69 +1,69 @@
-/**
- * \file
- *
- * \brief Instance description for GCLK
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_GCLK_INSTANCE_
-#define _SAMD21_GCLK_INSTANCE_
-
-/* ========== Register definition for GCLK peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_GCLK_CTRL              (0x40000C00U) /**< \brief (GCLK) Control */
-#define REG_GCLK_STATUS            (0x40000C01U) /**< \brief (GCLK) Status */
-#define REG_GCLK_CLKCTRL           (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
-#define REG_GCLK_GENCTRL           (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
-#define REG_GCLK_GENDIV            (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
-#else
-#define REG_GCLK_CTRL              (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
-#define REG_GCLK_STATUS            (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
-#define REG_GCLK_CLKCTRL           (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
-#define REG_GCLK_GENCTRL           (*(RwReg  *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
-#define REG_GCLK_GENDIV            (*(RwReg  *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENDIV_BITS            16      
-#define GCLK_GEN_NUM                9        // Number of Generic Clock Generators
-#define GCLK_GEN_NUM_MSB            8        // Number of Generic Clock Generators - 1
-#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
-#define GCLK_NUM                    37       // Number of Generic Clock Users
-#define GCLK_SOURCE_DFLL48M         7        // DFLL48M output
-#define GCLK_SOURCE_FDPLL           8        // FDPLL output
-#define GCLK_SOURCE_GCLKGEN1        2        // Generic clock generator 1 output
-#define GCLK_SOURCE_GCLKIN          1        // Generator input pad
-#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
-#define GCLK_SOURCE_OSCULP32K       3        // OSCULP32K oscillator output
-#define GCLK_SOURCE_OSC8M           6        // OSC8M oscillator output
-#define GCLK_SOURCE_OSC32K          4        // OSC32K oscillator outpur
-#define GCLK_SOURCE_XOSC            0        // XOSC oscillator output
-#define GCLK_SOURCE_XOSC32K         5        // XOSC32K oscillator output
-
-#endif /* _SAMD21_GCLK_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_INSTANCE_
+#define _SAMD21_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRL              (0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#else
+#define REG_GCLK_CTRL              (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (*(RwReg  *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (*(RwReg  *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS            16      
+#define GCLK_GEN_NUM                9        // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB            8        // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
+#define GCLK_NUM                    37       // Number of Generic Clock Users
+#define GCLK_SOURCE_DFLL48M         7        // DFLL48M output
+#define GCLK_SOURCE_FDPLL           8        // FDPLL output
+#define GCLK_SOURCE_GCLKGEN1        2        // Generic clock generator 1 output
+#define GCLK_SOURCE_GCLKIN          1        // Generator input pad
+#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
+#define GCLK_SOURCE_OSCULP32K       3        // OSCULP32K oscillator output
+#define GCLK_SOURCE_OSC8M           6        // OSC8M oscillator output
+#define GCLK_SOURCE_OSC32K          4        // OSC32K oscillator outpur
+#define GCLK_SOURCE_XOSC            0        // XOSC oscillator output
+#define GCLK_SOURCE_XOSC32K         5        // XOSC32K oscillator output
+
+#endif /* _SAMD21_GCLK_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h
index 391b43e..f38d25b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h
@@ -1,84 +1,84 @@
-/**
- * \file
- *
- * \brief Instance description for I2S
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_I2S_INSTANCE_
-#define _SAMD21_I2S_INSTANCE_
-
-/* ========== Register definition for I2S peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_I2S_CTRLA              (0x42005000U) /**< \brief (I2S) Control A */
-#define REG_I2S_CLKCTRL0           (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
-#define REG_I2S_CLKCTRL1           (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
-#define REG_I2S_INTENCLR           (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
-#define REG_I2S_INTENSET           (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
-#define REG_I2S_INTFLAG            (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
-#define REG_I2S_SYNCBUSY           (0x42005018U) /**< \brief (I2S) Synchronization Status */
-#define REG_I2S_SERCTRL0           (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
-#define REG_I2S_SERCTRL1           (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
-#define REG_I2S_DATA0              (0x42005030U) /**< \brief (I2S) Data 0 */
-#define REG_I2S_DATA1              (0x42005034U) /**< \brief (I2S) Data 1 */
-#else
-#define REG_I2S_CTRLA              (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
-#define REG_I2S_CLKCTRL0           (*(RwReg  *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
-#define REG_I2S_CLKCTRL1           (*(RwReg  *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
-#define REG_I2S_INTENCLR           (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
-#define REG_I2S_INTENSET           (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
-#define REG_I2S_INTFLAG            (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
-#define REG_I2S_SYNCBUSY           (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
-#define REG_I2S_SERCTRL0           (*(RwReg  *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
-#define REG_I2S_SERCTRL1           (*(RwReg  *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
-#define REG_I2S_DATA0              (*(RwReg  *)0x42005030U) /**< \brief (I2S) Data 0 */
-#define REG_I2S_DATA1              (*(RwReg  *)0x42005034U) /**< \brief (I2S) Data 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for I2S peripheral ========== */
-#define I2S_CLK_NUM                 2        // Number of clock units
-#define I2S_DMAC_ID_RX_0            41
-#define I2S_DMAC_ID_RX_1            42
-#define I2S_DMAC_ID_RX_LSB          41
-#define I2S_DMAC_ID_RX_MSB          42
-#define I2S_DMAC_ID_RX_SIZE         2
-#define I2S_DMAC_ID_TX_0            43
-#define I2S_DMAC_ID_TX_1            44
-#define I2S_DMAC_ID_TX_LSB          43
-#define I2S_DMAC_ID_TX_MSB          44
-#define I2S_DMAC_ID_TX_SIZE         2
-#define I2S_GCLK_ID_0               35
-#define I2S_GCLK_ID_1               36
-#define I2S_GCLK_ID_LSB             35
-#define I2S_GCLK_ID_MSB             36
-#define I2S_GCLK_ID_SIZE            2
-#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
-#define I2S_SER_NUM                 2        // Number of serializers
-
-#endif /* _SAMD21_I2S_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_INSTANCE_
+#define _SAMD21_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA              (0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0           (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1           (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0              (0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1              (0x42005034U) /**< \brief (I2S) Data 1 */
+#else
+#define REG_I2S_CTRLA              (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (*(RwReg  *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (*(RwReg  *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0           (*(RwReg  *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1           (*(RwReg  *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0              (*(RwReg  *)0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1              (*(RwReg  *)0x42005034U) /**< \brief (I2S) Data 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM                 2        // Number of clock units
+#define I2S_DMAC_ID_RX_0            41
+#define I2S_DMAC_ID_RX_1            42
+#define I2S_DMAC_ID_RX_LSB          41
+#define I2S_DMAC_ID_RX_MSB          42
+#define I2S_DMAC_ID_RX_SIZE         2
+#define I2S_DMAC_ID_TX_0            43
+#define I2S_DMAC_ID_TX_1            44
+#define I2S_DMAC_ID_TX_LSB          43
+#define I2S_DMAC_ID_TX_MSB          44
+#define I2S_DMAC_ID_TX_SIZE         2
+#define I2S_GCLK_ID_0               35
+#define I2S_GCLK_ID_1               36
+#define I2S_GCLK_ID_LSB             35
+#define I2S_GCLK_ID_MSB             36
+#define I2S_GCLK_ID_SIZE            2
+#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
+#define I2S_SER_NUM                 2        // Number of serializers
+
+#endif /* _SAMD21_I2S_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h
index f86562f..3c2794a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h
@@ -1,93 +1,93 @@
-/**
- * \file
- *
- * \brief Instance description for MTB
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_MTB_INSTANCE_
-#define _SAMD21_MTB_INSTANCE_
-
-/* ========== Register definition for MTB peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_MTB_POSITION           (0x41006000U) /**< \brief (MTB) MTB Position */
-#define REG_MTB_MASTER             (0x41006004U) /**< \brief (MTB) MTB Master */
-#define REG_MTB_FLOW               (0x41006008U) /**< \brief (MTB) MTB Flow */
-#define REG_MTB_BASE               (0x4100600CU) /**< \brief (MTB) MTB Base */
-#define REG_MTB_ITCTRL             (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
-#define REG_MTB_CLAIMSET           (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
-#define REG_MTB_CLAIMCLR           (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
-#define REG_MTB_LOCKACCESS         (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
-#define REG_MTB_LOCKSTATUS         (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
-#define REG_MTB_AUTHSTATUS         (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
-#define REG_MTB_DEVARCH            (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
-#define REG_MTB_DEVID              (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
-#define REG_MTB_DEVTYPE            (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
-#define REG_MTB_PID4               (0x41006FD0U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID5               (0x41006FD4U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID6               (0x41006FD8U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID7               (0x41006FDCU) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID0               (0x41006FE0U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID1               (0x41006FE4U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID2               (0x41006FE8U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID3               (0x41006FECU) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID0               (0x41006FF0U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID1               (0x41006FF4U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID2               (0x41006FF8U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID3               (0x41006FFCU) /**< \brief (MTB) CoreSight */
-#else
-#define REG_MTB_POSITION           (*(RwReg  *)0x41006000U) /**< \brief (MTB) MTB Position */
-#define REG_MTB_MASTER             (*(RwReg  *)0x41006004U) /**< \brief (MTB) MTB Master */
-#define REG_MTB_FLOW               (*(RwReg  *)0x41006008U) /**< \brief (MTB) MTB Flow */
-#define REG_MTB_BASE               (*(RoReg  *)0x4100600CU) /**< \brief (MTB) MTB Base */
-#define REG_MTB_ITCTRL             (*(RwReg  *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
-#define REG_MTB_CLAIMSET           (*(RwReg  *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
-#define REG_MTB_CLAIMCLR           (*(RwReg  *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
-#define REG_MTB_LOCKACCESS         (*(RwReg  *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
-#define REG_MTB_LOCKSTATUS         (*(RoReg  *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
-#define REG_MTB_AUTHSTATUS         (*(RoReg  *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
-#define REG_MTB_DEVARCH            (*(RoReg  *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
-#define REG_MTB_DEVID              (*(RoReg  *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
-#define REG_MTB_DEVTYPE            (*(RoReg  *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
-#define REG_MTB_PID4               (*(RoReg  *)0x41006FD0U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID5               (*(RoReg  *)0x41006FD4U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID6               (*(RoReg  *)0x41006FD8U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID7               (*(RoReg  *)0x41006FDCU) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID0               (*(RoReg  *)0x41006FE0U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID1               (*(RoReg  *)0x41006FE4U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID2               (*(RoReg  *)0x41006FE8U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_PID3               (*(RoReg  *)0x41006FECU) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID0               (*(RoReg  *)0x41006FF0U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID1               (*(RoReg  *)0x41006FF4U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID2               (*(RoReg  *)0x41006FF8U) /**< \brief (MTB) CoreSight */
-#define REG_MTB_CID3               (*(RoReg  *)0x41006FFCU) /**< \brief (MTB) CoreSight */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-
-#endif /* _SAMD21_MTB_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for MTB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_INSTANCE_
+#define _SAMD21_MTB_INSTANCE_
+
+/* ========== Register definition for MTB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MTB_POSITION           (0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER             (0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW               (0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE               (0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL             (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET           (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR           (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS         (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS         (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS         (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH            (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID              (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE            (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4               (0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5               (0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6               (0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7               (0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0               (0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1               (0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2               (0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3               (0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0               (0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1               (0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2               (0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3               (0x41006FFCU) /**< \brief (MTB) CoreSight */
+#else
+#define REG_MTB_POSITION           (*(RwReg  *)0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER             (*(RwReg  *)0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW               (*(RwReg  *)0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE               (*(RoReg  *)0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL             (*(RwReg  *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET           (*(RwReg  *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR           (*(RwReg  *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS         (*(RwReg  *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS         (*(RoReg  *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS         (*(RoReg  *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH            (*(RoReg  *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID              (*(RoReg  *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE            (*(RoReg  *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4               (*(RoReg  *)0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5               (*(RoReg  *)0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6               (*(RoReg  *)0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7               (*(RoReg  *)0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0               (*(RoReg  *)0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1               (*(RoReg  *)0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2               (*(RoReg  *)0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3               (*(RoReg  *)0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0               (*(RoReg  *)0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1               (*(RoReg  *)0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2               (*(RoReg  *)0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3               (*(RoReg  *)0x41006FFCU) /**< \brief (MTB) CoreSight */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAMD21_MTB_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
index 87dcd45..00fedcb 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
@@ -1,82 +1,82 @@
-/**
- * \file
- *
- * \brief Instance description for NVMCTRL
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_NVMCTRL_INSTANCE_
-#define _SAMD21_NVMCTRL_INSTANCE_
-
-/* ========== Register definition for NVMCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_NVMCTRL_CTRLA          (0x41004000U) /**< \brief (NVMCTRL) Control A */
-#define REG_NVMCTRL_CTRLB          (0x41004004U) /**< \brief (NVMCTRL) Control B */
-#define REG_NVMCTRL_PARAM          (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
-#define REG_NVMCTRL_INTENCLR       (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
-#define REG_NVMCTRL_INTENSET       (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
-#define REG_NVMCTRL_INTFLAG        (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
-#define REG_NVMCTRL_STATUS         (0x41004018U) /**< \brief (NVMCTRL) Status */
-#define REG_NVMCTRL_ADDR           (0x4100401CU) /**< \brief (NVMCTRL) Address */
-#define REG_NVMCTRL_LOCK           (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
-#else
-#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
-#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004U) /**< \brief (NVMCTRL) Control B */
-#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
-#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
-#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
-#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
-#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
-#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CU) /**< \brief (NVMCTRL) Address */
-#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for NVMCTRL peripheral ========== */
-#define NVMCTRL_AUX0_ADDRESS        0x00804000
-#define NVMCTRL_AUX1_ADDRESS        0x00806000
-#define NVMCTRL_AUX2_ADDRESS        0x00808000
-#define NVMCTRL_AUX3_ADDRESS        0x0080A000
-#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
-#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE          65536   
-#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
-#define NVMCTRL_PAGE_HW             32      
-#define NVMCTRL_PAGE_SIZE           64      
-#define NVMCTRL_PAGE_W              16      
-#define NVMCTRL_PMSB                3       
-#define NVMCTRL_PSZ_BITS            6       
-#define NVMCTRL_ROW_PAGES           4       
-#define NVMCTRL_ROW_SIZE            256     
-#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
-#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
-#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
-#define NVMCTRL_RWWEE_PAGES         32       // Page size
-#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 // Start address of the RWW EEPROM area
-
-#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_INSTANCE_
+#define _SAMD21_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA          (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS        0x00804000
+#define NVMCTRL_AUX1_ADDRESS        0x00806000
+#define NVMCTRL_AUX2_ADDRESS        0x00808000
+#define NVMCTRL_AUX3_ADDRESS        0x0080A000
+#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE          65536   
+#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
+#define NVMCTRL_PAGE_HW             32      
+#define NVMCTRL_PAGE_SIZE           64      
+#define NVMCTRL_PAGE_W              16      
+#define NVMCTRL_PMSB                3       
+#define NVMCTRL_PSZ_BITS            6       
+#define NVMCTRL_ROW_PAGES           4       
+#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+#define NVMCTRL_RWWEE_PAGES         32       // Page size
+#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 // Start address of the RWW EEPROM area
+
+#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h
index 6528b54..8bcd8fd 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl_variant_d.h
@@ -1,82 +1,82 @@
-/**
- * \file
- *
- * \brief Instance description for NVMCTRL
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_NVMCTRL_INSTANCE_
-#define _SAMD21_NVMCTRL_INSTANCE_
-
-/* ========== Register definition for NVMCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_NVMCTRL_CTRLA          (0x41004000U) /**< \brief (NVMCTRL) Control A */
-#define REG_NVMCTRL_CTRLB          (0x41004004U) /**< \brief (NVMCTRL) Control B */
-#define REG_NVMCTRL_PARAM          (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
-#define REG_NVMCTRL_INTENCLR       (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
-#define REG_NVMCTRL_INTENSET       (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
-#define REG_NVMCTRL_INTFLAG        (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
-#define REG_NVMCTRL_STATUS         (0x41004018U) /**< \brief (NVMCTRL) Status */
-#define REG_NVMCTRL_ADDR           (0x4100401CU) /**< \brief (NVMCTRL) Address */
-#define REG_NVMCTRL_LOCK           (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
-#else
-#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
-#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004U) /**< \brief (NVMCTRL) Control B */
-#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
-#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
-#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
-#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
-#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
-#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CU) /**< \brief (NVMCTRL) Address */
-#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for NVMCTRL peripheral ========== */
-#define NVMCTRL_AUX0_ADDRESS        0x00804000
-#define NVMCTRL_AUX1_ADDRESS        0x00806000
-#define NVMCTRL_AUX2_ADDRESS        0x00808000
-#define NVMCTRL_AUX3_ADDRESS        0x0080A000
-#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
-#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE          131072  
-#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
-#define NVMCTRL_PAGE_HW             32      
-#define NVMCTRL_PAGE_SIZE           64      
-#define NVMCTRL_PAGE_W              16      
-#define NVMCTRL_PMSB                3       
-#define NVMCTRL_PSZ_BITS            6       
-#define NVMCTRL_ROW_PAGES           4       
-#define NVMCTRL_ROW_SIZE            256     
-#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
-#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
-#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
-#define NVMCTRL_RWWEE_PAGES         64       // Page size
-#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 // Start address of the RWW EEPROM area
-
-#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_INSTANCE_
+#define _SAMD21_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA          (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS        0x00804000
+#define NVMCTRL_AUX1_ADDRESS        0x00806000
+#define NVMCTRL_AUX2_ADDRESS        0x00808000
+#define NVMCTRL_AUX3_ADDRESS        0x0080A000
+#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE          131072  
+#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
+#define NVMCTRL_PAGE_HW             32      
+#define NVMCTRL_PAGE_SIZE           64      
+#define NVMCTRL_PAGE_W              16      
+#define NVMCTRL_PMSB                3       
+#define NVMCTRL_PSZ_BITS            6       
+#define NVMCTRL_ROW_PAGES           4       
+#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+#define NVMCTRL_RWWEE_PAGES         64       // Page size
+#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 // Start address of the RWW EEPROM area
+
+#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h
index d9f0cfa..02dcbe4 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h
@@ -1,49 +1,49 @@
-/**
- * \file
- *
- * \brief Instance description for PAC0
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PAC0_INSTANCE_
-#define _SAMD21_PAC0_INSTANCE_
-
-/* ========== Register definition for PAC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PAC0_WPCLR             (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
-#define REG_PAC0_WPSET             (0x40000004U) /**< \brief (PAC0) Write Protection Set */
-#else
-#define REG_PAC0_WPCLR             (*(RwReg  *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
-#define REG_PAC0_WPSET             (*(RwReg  *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PAC0 peripheral ========== */
-#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
-
-#endif /* _SAMD21_PAC0_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for PAC0
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC0_INSTANCE_
+#define _SAMD21_PAC0_INSTANCE_
+
+/* ========== Register definition for PAC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC0_WPCLR             (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#else
+#define REG_PAC0_WPCLR             (*(RwReg  *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (*(RwReg  *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC0 peripheral ========== */
+#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC0_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h
index 81fe797..072764d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h
@@ -1,49 +1,49 @@
-/**
- * \file
- *
- * \brief Instance description for PAC1
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PAC1_INSTANCE_
-#define _SAMD21_PAC1_INSTANCE_
-
-/* ========== Register definition for PAC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PAC1_WPCLR             (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
-#define REG_PAC1_WPSET             (0x41000004U) /**< \brief (PAC1) Write Protection Set */
-#else
-#define REG_PAC1_WPCLR             (*(RwReg  *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
-#define REG_PAC1_WPSET             (*(RwReg  *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PAC1 peripheral ========== */
-#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
-
-#endif /* _SAMD21_PAC1_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for PAC1
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC1_INSTANCE_
+#define _SAMD21_PAC1_INSTANCE_
+
+/* ========== Register definition for PAC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC1_WPCLR             (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#else
+#define REG_PAC1_WPCLR             (*(RwReg  *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (*(RwReg  *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC1 peripheral ========== */
+#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC1_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h
index 632c380..6652909 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h
@@ -1,49 +1,49 @@
-/**
- * \file
- *
- * \brief Instance description for PAC2
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PAC2_INSTANCE_
-#define _SAMD21_PAC2_INSTANCE_
-
-/* ========== Register definition for PAC2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PAC2_WPCLR             (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
-#define REG_PAC2_WPSET             (0x42000004U) /**< \brief (PAC2) Write Protection Set */
-#else
-#define REG_PAC2_WPCLR             (*(RwReg  *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
-#define REG_PAC2_WPSET             (*(RwReg  *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PAC2 peripheral ========== */
-#define PAC2_WPROT_DEFAULT_VAL      0x00800000 // PAC protection mask at reset
-
-#endif /* _SAMD21_PAC2_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for PAC2
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC2_INSTANCE_
+#define _SAMD21_PAC2_INSTANCE_
+
+/* ========== Register definition for PAC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC2_WPCLR             (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#else
+#define REG_PAC2_WPCLR             (*(RwReg  *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (*(RwReg  *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC2 peripheral ========== */
+#define PAC2_WPROT_DEFAULT_VAL      0x00800000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC2_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h
index 0dceb53..760455b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h
@@ -1,79 +1,79 @@
-/**
- * \file
- *
- * \brief Instance description for PM
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PM_INSTANCE_
-#define _SAMD21_PM_INSTANCE_
-
-/* ========== Register definition for PM peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PM_CTRL                (0x40000400U) /**< \brief (PM) Control */
-#define REG_PM_SLEEP               (0x40000401U) /**< \brief (PM) Sleep Mode */
-#define REG_PM_EXTCTRL             (0x40000402U) /**< \brief (PM) External Reset Controller */
-#define REG_PM_CPUSEL              (0x40000408U) /**< \brief (PM) CPU Clock Select */
-#define REG_PM_APBASEL             (0x40000409U) /**< \brief (PM) APBA Clock Select */
-#define REG_PM_APBBSEL             (0x4000040AU) /**< \brief (PM) APBB Clock Select */
-#define REG_PM_APBCSEL             (0x4000040BU) /**< \brief (PM) APBC Clock Select */
-#define REG_PM_AHBMASK             (0x40000414U) /**< \brief (PM) AHB Mask */
-#define REG_PM_APBAMASK            (0x40000418U) /**< \brief (PM) APBA Mask */
-#define REG_PM_APBBMASK            (0x4000041CU) /**< \brief (PM) APBB Mask */
-#define REG_PM_APBCMASK            (0x40000420U) /**< \brief (PM) APBC Mask */
-#define REG_PM_INTENCLR            (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
-#define REG_PM_INTENSET            (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
-#define REG_PM_INTFLAG             (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
-#define REG_PM_RCAUSE              (0x40000438U) /**< \brief (PM) Reset Cause */
-#else
-#define REG_PM_CTRL                (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
-#define REG_PM_SLEEP               (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
-#define REG_PM_EXTCTRL             (*(RwReg8 *)0x40000402U) /**< \brief (PM) External Reset Controller */
-#define REG_PM_CPUSEL              (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
-#define REG_PM_APBASEL             (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
-#define REG_PM_APBBSEL             (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
-#define REG_PM_APBCSEL             (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
-#define REG_PM_AHBMASK             (*(RwReg  *)0x40000414U) /**< \brief (PM) AHB Mask */
-#define REG_PM_APBAMASK            (*(RwReg  *)0x40000418U) /**< \brief (PM) APBA Mask */
-#define REG_PM_APBBMASK            (*(RwReg  *)0x4000041CU) /**< \brief (PM) APBB Mask */
-#define REG_PM_APBCMASK            (*(RwReg  *)0x40000420U) /**< \brief (PM) APBC Mask */
-#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
-#define REG_PM_INTENSET            (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
-#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
-#define REG_PM_RCAUSE              (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PM peripheral ========== */
-#define PM_CTRL_MCSEL_DFLL48M       3       
-#define PM_CTRL_MCSEL_GCLK          0       
-#define PM_CTRL_MCSEL_OSC8M         1       
-#define PM_CTRL_MCSEL_XOSC          2       
-#define PM_PM_CLK_APB_NUM           2       
-
-#endif /* _SAMD21_PM_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_INSTANCE_
+#define _SAMD21_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRL                (0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_EXTCTRL             (0x40000402U) /**< \brief (PM) External Reset Controller */
+#define REG_PM_CPUSEL              (0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (0x40000438U) /**< \brief (PM) Reset Cause */
+#else
+#define REG_PM_CTRL                (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_EXTCTRL             (*(RwReg8 *)0x40000402U) /**< \brief (PM) External Reset Controller */
+#define REG_PM_CPUSEL              (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (*(RwReg  *)0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (*(RwReg  *)0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (*(RwReg  *)0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (*(RwReg  *)0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_CTRL_MCSEL_DFLL48M       3       
+#define PM_CTRL_MCSEL_GCLK          0       
+#define PM_CTRL_MCSEL_OSC8M         1       
+#define PM_CTRL_MCSEL_XOSC          2       
+#define PM_PM_CLK_APB_NUM           2       
+
+#endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h
index cb61fc8..a867a00 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h
@@ -1,126 +1,126 @@
-/**
- * \file
- *
- * \brief Instance description for PORT
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PORT_INSTANCE_
-#define _SAMD21_PORT_INSTANCE_
-
-/* ========== Register definition for PORT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
-#define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
-#define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
-#define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
-#define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
-#define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
-#define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
-#define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
-#define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
-#define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
-#define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
-#define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
-#define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
-#define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
-#define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
-#define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
-#define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
-#define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
-#define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
-#define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
-#define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
-#define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
-#define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
-#define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
-#define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
-#define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
-#else
-#define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
-#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
-#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
-#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
-#define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
-#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
-#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
-#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
-#define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
-#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
-#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
-#define REG_PORT_PMUX0             (*(RwReg  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
-#define REG_PORT_PINCFG0           (*(RwReg  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
-#define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
-#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
-#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
-#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
-#define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
-#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
-#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
-#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
-#define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
-#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
-#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
-#define REG_PORT_PMUX1             (*(RwReg  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
-#define REG_PORT_PINCFG1           (*(RwReg  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PORT peripheral ========== */
-#define PORT_BITS                   64       // Number of PORT pins
-#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
-#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
-#define PORT_DRVSTR                 1        // DRVSTR supported
-#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
-#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
-#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
-#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
-#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
-#define PORT_ODRAIN                 0        // ODRAIN supported
-#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
-#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
-#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
-#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
-#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
-#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
-#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
-#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
-#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
-#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
-#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
-#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
-#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
-#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
-#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
-#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
-#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
-#define PORT_SLEWLIM                0        // SLEWLIM supported
-#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
-#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
-
-#endif /* _SAMD21_PORT_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (*(RwReg  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (*(RwReg  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (*(RwReg  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (*(RwReg  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS                   64       // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR                 1        // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN                 0        // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM                0        // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port_variant_d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port_variant_d.h
index 216a8f3..a7ed9f6 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port_variant_d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/port_variant_d.h
@@ -1,126 +1,126 @@
-/**
- * \file
- *
- * \brief Instance description for PORT
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_PORT_INSTANCE_
-#define _SAMD21_PORT_INSTANCE_
-
-/* ========== Register definition for PORT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
-#define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
-#define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
-#define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
-#define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
-#define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
-#define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
-#define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
-#define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
-#define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
-#define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
-#define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
-#define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
-#define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
-#define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
-#define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
-#define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
-#define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
-#define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
-#define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
-#define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
-#define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
-#define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
-#define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
-#define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
-#define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
-#else
-#define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
-#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
-#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
-#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
-#define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
-#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
-#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
-#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
-#define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
-#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
-#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
-#define REG_PORT_PMUX0             (*(RwReg8  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
-#define REG_PORT_PINCFG0           (*(RwReg8  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
-#define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
-#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
-#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
-#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
-#define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
-#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
-#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
-#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
-#define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
-#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
-#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
-#define REG_PORT_PMUX1             (*(RwReg8  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
-#define REG_PORT_PINCFG1           (*(RwReg8  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PORT peripheral ========== */
-#define PORT_BITS                   64       // Number of PORT pins
-#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
-#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
-#define PORT_DRVSTR                 1        // DRVSTR supported
-#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
-#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
-#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
-#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
-#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
-#define PORT_ODRAIN                 0        // ODRAIN supported
-#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
-#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
-#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
-#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
-#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
-#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
-#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
-#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
-#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
-#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
-#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
-#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
-#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
-#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
-#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
-#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
-#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
-#define PORT_SLEWLIM                0        // SLEWLIM supported
-#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
-#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
-
-#endif /* _SAMD21_PORT_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (*(RwReg8  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (*(RwReg8  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (*(RwReg8  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (*(RwReg8  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS                   64       // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR                 1        // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN                 0        // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM                0        // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h
index b360d0d..2ec6caf 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h
@@ -1,107 +1,107 @@
-/**
- * \file
- *
- * \brief Instance description for RTC
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_RTC_INSTANCE_
-#define _SAMD21_RTC_INSTANCE_
-
-/* ========== Register definition for RTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_RTC_READREQ            (0x40001402U) /**< \brief (RTC) Read Request */
-#define REG_RTC_STATUS             (0x4000140AU) /**< \brief (RTC) Status */
-#define REG_RTC_DBGCTRL            (0x4000140BU) /**< \brief (RTC) Debug Control */
-#define REG_RTC_FREQCORR           (0x4000140CU) /**< \brief (RTC) Frequency Correction */
-#define REG_RTC_MODE0_CTRL         (0x40001400U) /**< \brief (RTC) MODE0 Control */
-#define REG_RTC_MODE0_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
-#define REG_RTC_MODE0_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
-#define REG_RTC_MODE0_INTENSET     (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
-#define REG_RTC_MODE0_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE0_COUNT        (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
-#define REG_RTC_MODE0_COMP0        (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
-#define REG_RTC_MODE1_CTRL         (0x40001400U) /**< \brief (RTC) MODE1 Control */
-#define REG_RTC_MODE1_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
-#define REG_RTC_MODE1_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
-#define REG_RTC_MODE1_INTENSET     (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
-#define REG_RTC_MODE1_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE1_COUNT        (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
-#define REG_RTC_MODE1_PER          (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
-#define REG_RTC_MODE1_COMP0        (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
-#define REG_RTC_MODE1_COMP1        (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
-#define REG_RTC_MODE2_CTRL         (0x40001400U) /**< \brief (RTC) MODE2 Control */
-#define REG_RTC_MODE2_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
-#define REG_RTC_MODE2_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
-#define REG_RTC_MODE2_INTENSET     (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
-#define REG_RTC_MODE2_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE2_CLOCK        (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
-#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
-#define REG_RTC_MODE2_ALARM_MASK0  (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
-#else
-#define REG_RTC_READREQ            (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
-#define REG_RTC_STATUS             (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
-#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
-#define REG_RTC_FREQCORR           (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
-#define REG_RTC_MODE0_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
-#define REG_RTC_MODE0_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
-#define REG_RTC_MODE0_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
-#define REG_RTC_MODE0_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
-#define REG_RTC_MODE0_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
-#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
-#define REG_RTC_MODE1_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
-#define REG_RTC_MODE1_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
-#define REG_RTC_MODE1_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
-#define REG_RTC_MODE1_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
-#define REG_RTC_MODE1_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
-#define REG_RTC_MODE1_PER          (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
-#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
-#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
-#define REG_RTC_MODE2_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
-#define REG_RTC_MODE2_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
-#define REG_RTC_MODE2_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
-#define REG_RTC_MODE2_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
-#define REG_RTC_MODE2_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
-#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
-#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg  *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for RTC peripheral ========== */
-#define RTC_ALARM_NUM               1        // Number of Alarms
-#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
-#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
-#define RTC_GCLK_ID                 4        // Index of Generic Clock
-#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
-#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
-#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
-
-#endif /* _SAMD21_RTC_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_INSTANCE_
+#define _SAMD21_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_READREQ            (0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_READREQ            (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg  *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM               1        // Number of Alarms
+#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
+#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
+#define RTC_GCLK_ID                 4        // Index of Generic Clock
+#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
+#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
+#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
+
+#endif /* _SAMD21_RTC_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
index 808f41b..b5f9cab 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
@@ -1,155 +1,155 @@
-/**
- * \file
- *
- * \brief Instance description for SBMATRIX
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SBMATRIX_INSTANCE_
-#define _SAMD21_SBMATRIX_INSTANCE_
-
-/* ========== Register definition for SBMATRIX peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SBMATRIX_PRAS0         (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
-#define REG_SBMATRIX_PRBS0         (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
-#define REG_SBMATRIX_PRAS1         (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
-#define REG_SBMATRIX_PRBS1         (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
-#define REG_SBMATRIX_PRAS2         (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
-#define REG_SBMATRIX_PRBS2         (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
-#define REG_SBMATRIX_PRAS3         (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
-#define REG_SBMATRIX_PRBS3         (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
-#define REG_SBMATRIX_PRAS4         (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
-#define REG_SBMATRIX_PRBS4         (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
-#define REG_SBMATRIX_PRAS5         (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
-#define REG_SBMATRIX_PRBS5         (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
-#define REG_SBMATRIX_PRAS6         (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
-#define REG_SBMATRIX_PRBS6         (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
-#define REG_SBMATRIX_PRAS7         (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
-#define REG_SBMATRIX_PRBS7         (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
-#define REG_SBMATRIX_PRAS8         (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
-#define REG_SBMATRIX_PRBS8         (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
-#define REG_SBMATRIX_PRAS9         (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
-#define REG_SBMATRIX_PRBS9         (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
-#define REG_SBMATRIX_PRAS10        (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
-#define REG_SBMATRIX_PRBS10        (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
-#define REG_SBMATRIX_PRAS11        (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
-#define REG_SBMATRIX_PRBS11        (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
-#define REG_SBMATRIX_PRAS12        (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
-#define REG_SBMATRIX_PRBS12        (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
-#define REG_SBMATRIX_PRAS13        (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
-#define REG_SBMATRIX_PRBS13        (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
-#define REG_SBMATRIX_PRAS14        (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
-#define REG_SBMATRIX_PRBS14        (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
-#define REG_SBMATRIX_PRAS15        (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
-#define REG_SBMATRIX_PRBS15        (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
-#define REG_SBMATRIX_SFR0          (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
-#define REG_SBMATRIX_SFR1          (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
-#define REG_SBMATRIX_SFR2          (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
-#define REG_SBMATRIX_SFR3          (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
-#define REG_SBMATRIX_SFR4          (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
-#define REG_SBMATRIX_SFR5          (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
-#define REG_SBMATRIX_SFR6          (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
-#define REG_SBMATRIX_SFR7          (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
-#define REG_SBMATRIX_SFR8          (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
-#define REG_SBMATRIX_SFR9          (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
-#define REG_SBMATRIX_SFR10         (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
-#define REG_SBMATRIX_SFR11         (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
-#define REG_SBMATRIX_SFR12         (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
-#define REG_SBMATRIX_SFR13         (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
-#define REG_SBMATRIX_SFR14         (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
-#define REG_SBMATRIX_SFR15         (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
-#else
-#define REG_SBMATRIX_PRAS0         (*(RwReg  *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
-#define REG_SBMATRIX_PRBS0         (*(RwReg  *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
-#define REG_SBMATRIX_PRAS1         (*(RwReg  *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
-#define REG_SBMATRIX_PRBS1         (*(RwReg  *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
-#define REG_SBMATRIX_PRAS2         (*(RwReg  *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
-#define REG_SBMATRIX_PRBS2         (*(RwReg  *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
-#define REG_SBMATRIX_PRAS3         (*(RwReg  *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
-#define REG_SBMATRIX_PRBS3         (*(RwReg  *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
-#define REG_SBMATRIX_PRAS4         (*(RwReg  *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
-#define REG_SBMATRIX_PRBS4         (*(RwReg  *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
-#define REG_SBMATRIX_PRAS5         (*(RwReg  *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
-#define REG_SBMATRIX_PRBS5         (*(RwReg  *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
-#define REG_SBMATRIX_PRAS6         (*(RwReg  *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
-#define REG_SBMATRIX_PRBS6         (*(RwReg  *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
-#define REG_SBMATRIX_PRAS7         (*(RwReg  *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
-#define REG_SBMATRIX_PRBS7         (*(RwReg  *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
-#define REG_SBMATRIX_PRAS8         (*(RwReg  *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
-#define REG_SBMATRIX_PRBS8         (*(RwReg  *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
-#define REG_SBMATRIX_PRAS9         (*(RwReg  *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
-#define REG_SBMATRIX_PRBS9         (*(RwReg  *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
-#define REG_SBMATRIX_PRAS10        (*(RwReg  *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
-#define REG_SBMATRIX_PRBS10        (*(RwReg  *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
-#define REG_SBMATRIX_PRAS11        (*(RwReg  *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
-#define REG_SBMATRIX_PRBS11        (*(RwReg  *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
-#define REG_SBMATRIX_PRAS12        (*(RwReg  *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
-#define REG_SBMATRIX_PRBS12        (*(RwReg  *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
-#define REG_SBMATRIX_PRAS13        (*(RwReg  *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
-#define REG_SBMATRIX_PRBS13        (*(RwReg  *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
-#define REG_SBMATRIX_PRAS14        (*(RwReg  *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
-#define REG_SBMATRIX_PRBS14        (*(RwReg  *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
-#define REG_SBMATRIX_PRAS15        (*(RwReg  *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
-#define REG_SBMATRIX_PRBS15        (*(RwReg  *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
-#define REG_SBMATRIX_SFR0          (*(RwReg  *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
-#define REG_SBMATRIX_SFR1          (*(RwReg  *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
-#define REG_SBMATRIX_SFR2          (*(RwReg  *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
-#define REG_SBMATRIX_SFR3          (*(RwReg  *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
-#define REG_SBMATRIX_SFR4          (*(RwReg  *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
-#define REG_SBMATRIX_SFR5          (*(RwReg  *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
-#define REG_SBMATRIX_SFR6          (*(RwReg  *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
-#define REG_SBMATRIX_SFR7          (*(RwReg  *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
-#define REG_SBMATRIX_SFR8          (*(RwReg  *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
-#define REG_SBMATRIX_SFR9          (*(RwReg  *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
-#define REG_SBMATRIX_SFR10         (*(RwReg  *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
-#define REG_SBMATRIX_SFR11         (*(RwReg  *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
-#define REG_SBMATRIX_SFR12         (*(RwReg  *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
-#define REG_SBMATRIX_SFR13         (*(RwReg  *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
-#define REG_SBMATRIX_SFR14         (*(RwReg  *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
-#define REG_SBMATRIX_SFR15         (*(RwReg  *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SBMATRIX peripheral ========== */
-#define SBMATRIX_DEFINED                    
-/* ========== Instance parameters for SBMATRIX ========== */
-#define SBMATRIX_SLAVE_FLASH        0
-#define SBMATRIX_SLAVE_HPB0         1
-#define SBMATRIX_SLAVE_HPB1         2
-#define SBMATRIX_SLAVE_HPB2         3
-#define SBMATRIX_SLAVE_HMCRAMC0     4
-#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
-#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
-#define SBMATRIX_SLAVE_NUM          7
-
-#define SBMATRIX_MASTER_CM0PLUS     0
-#define SBMATRIX_MASTER_DSU         1
-#define SBMATRIX_MASTER_DMAC        2
-#define SBMATRIX_MASTER_NUM         3
-
-#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SBMATRIX
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SBMATRIX_INSTANCE_
+#define _SAMD21_SBMATRIX_INSTANCE_
+
+/* ========== Register definition for SBMATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SBMATRIX_PRAS0         (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0         (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1         (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1         (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2         (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2         (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3         (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3         (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4         (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4         (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5         (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5         (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6         (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6         (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7         (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7         (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8         (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8         (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9         (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9         (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10        (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10        (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11        (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11        (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12        (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12        (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13        (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13        (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14        (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14        (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15        (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15        (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0          (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1          (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2          (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3          (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4          (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5          (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6          (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7          (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8          (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9          (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10         (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11         (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12         (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13         (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14         (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15         (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
+#else
+#define REG_SBMATRIX_PRAS0         (*(RwReg  *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0         (*(RwReg  *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1         (*(RwReg  *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1         (*(RwReg  *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2         (*(RwReg  *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2         (*(RwReg  *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3         (*(RwReg  *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3         (*(RwReg  *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4         (*(RwReg  *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4         (*(RwReg  *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5         (*(RwReg  *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5         (*(RwReg  *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6         (*(RwReg  *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6         (*(RwReg  *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7         (*(RwReg  *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7         (*(RwReg  *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8         (*(RwReg  *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8         (*(RwReg  *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9         (*(RwReg  *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9         (*(RwReg  *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10        (*(RwReg  *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10        (*(RwReg  *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11        (*(RwReg  *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11        (*(RwReg  *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12        (*(RwReg  *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12        (*(RwReg  *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13        (*(RwReg  *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13        (*(RwReg  *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14        (*(RwReg  *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14        (*(RwReg  *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15        (*(RwReg  *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15        (*(RwReg  *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0          (*(RwReg  *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1          (*(RwReg  *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2          (*(RwReg  *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3          (*(RwReg  *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4          (*(RwReg  *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5          (*(RwReg  *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6          (*(RwReg  *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7          (*(RwReg  *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8          (*(RwReg  *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9          (*(RwReg  *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10         (*(RwReg  *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11         (*(RwReg  *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12         (*(RwReg  *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13         (*(RwReg  *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14         (*(RwReg  *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15         (*(RwReg  *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SBMATRIX peripheral ========== */
+#define SBMATRIX_DEFINED                    
+/* ========== Instance parameters for SBMATRIX ========== */
+#define SBMATRIX_SLAVE_FLASH        0
+#define SBMATRIX_SLAVE_HPB0         1
+#define SBMATRIX_SLAVE_HPB1         2
+#define SBMATRIX_SLAVE_HPB2         3
+#define SBMATRIX_SLAVE_HMCRAMC0     4
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
+#define SBMATRIX_SLAVE_NUM          7
+
+#define SBMATRIX_MASTER_CM0PLUS     0
+#define SBMATRIX_MASTER_DSU         1
+#define SBMATRIX_MASTER_DMAC        2
+#define SBMATRIX_MASTER_NUM         3
+
+#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h
index 67366f8..4b98f3e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h
@@ -1,133 +1,133 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM0
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM0_INSTANCE_
-#define _SAMD21_SERCOM0_INSTANCE_
-
-/* ========== Register definition for SERCOM0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM0_I2CM_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
-#define REG_SERCOM0_I2CM_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
-#define REG_SERCOM0_I2CM_BAUD      (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
-#define REG_SERCOM0_I2CM_INTENCLR  (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
-#define REG_SERCOM0_I2CM_INTENSET  (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
-#define REG_SERCOM0_I2CM_INTFLAG   (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CM_STATUS    (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
-#define REG_SERCOM0_I2CM_SYNCBUSY  (0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
-#define REG_SERCOM0_I2CM_ADDR      (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
-#define REG_SERCOM0_I2CM_DATA      (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
-#define REG_SERCOM0_I2CM_DBGCTRL   (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
-#define REG_SERCOM0_I2CS_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
-#define REG_SERCOM0_I2CS_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
-#define REG_SERCOM0_I2CS_INTENCLR  (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
-#define REG_SERCOM0_I2CS_INTENSET  (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
-#define REG_SERCOM0_I2CS_INTFLAG   (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CS_STATUS    (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
-#define REG_SERCOM0_I2CS_SYNCBUSY  (0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
-#define REG_SERCOM0_I2CS_ADDR      (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
-#define REG_SERCOM0_I2CS_DATA      (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
-#define REG_SERCOM0_SPI_CTRLA      (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
-#define REG_SERCOM0_SPI_CTRLB      (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
-#define REG_SERCOM0_SPI_BAUD       (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
-#define REG_SERCOM0_SPI_INTENCLR   (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
-#define REG_SERCOM0_SPI_INTENSET   (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
-#define REG_SERCOM0_SPI_INTFLAG    (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM0_SPI_STATUS     (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
-#define REG_SERCOM0_SPI_SYNCBUSY   (0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
-#define REG_SERCOM0_SPI_ADDR       (0x42000824U) /**< \brief (SERCOM0) SPI Address */
-#define REG_SERCOM0_SPI_DATA       (0x42000828U) /**< \brief (SERCOM0) SPI Data */
-#define REG_SERCOM0_SPI_DBGCTRL    (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
-#define REG_SERCOM0_USART_CTRLA    (0x42000800U) /**< \brief (SERCOM0) USART Control A */
-#define REG_SERCOM0_USART_CTRLB    (0x42000804U) /**< \brief (SERCOM0) USART Control B */
-#define REG_SERCOM0_USART_BAUD     (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
-#define REG_SERCOM0_USART_RXPL     (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
-#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
-#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
-#define REG_SERCOM0_USART_INTFLAG  (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM0_USART_STATUS   (0x4200081AU) /**< \brief (SERCOM0) USART Status */
-#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
-#define REG_SERCOM0_USART_DATA     (0x42000828U) /**< \brief (SERCOM0) USART Data */
-#define REG_SERCOM0_USART_DBGCTRL  (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
-#else
-#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
-#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
-#define REG_SERCOM0_I2CM_BAUD      (*(RwReg  *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
-#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
-#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
-#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
-#define REG_SERCOM0_I2CM_SYNCBUSY  (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
-#define REG_SERCOM0_I2CM_ADDR      (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
-#define REG_SERCOM0_I2CM_DATA      (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
-#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
-#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
-#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
-#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
-#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
-#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
-#define REG_SERCOM0_I2CS_SYNCBUSY  (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
-#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
-#define REG_SERCOM0_I2CS_DATA      (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
-#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
-#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
-#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
-#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
-#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
-#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
-#define REG_SERCOM0_SPI_SYNCBUSY   (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
-#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
-#define REG_SERCOM0_SPI_DATA       (*(RwReg  *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
-#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
-#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
-#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
-#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
-#define REG_SERCOM0_USART_RXPL     (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
-#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
-#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
-#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
-#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
-#define REG_SERCOM0_USART_DATA     (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
-#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM0 peripheral ========== */
-#define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
-#define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
-#define SERCOM0_GCLK_ID_CORE        20       // Index of Generic Clock for Core
-#define SERCOM0_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM0_INT_MSB             6       
-
-#endif /* _SAMD21_SERCOM0_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM0_INSTANCE_
+#define _SAMD21_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD      (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR      (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_ADDR      (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD       (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_ADDR       (0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD     (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_DATA     (0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD      (*(RwReg  *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR      (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (*(RwReg  *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg  *)0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_DATA     (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
+#define SERCOM0_GCLK_ID_CORE        20       // Index of Generic Clock for Core
+#define SERCOM0_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM0_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h
index 239f33c..57abfb6 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h
@@ -1,133 +1,133 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM1
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM1_INSTANCE_
-#define _SAMD21_SERCOM1_INSTANCE_
-
-/* ========== Register definition for SERCOM1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM1_I2CM_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
-#define REG_SERCOM1_I2CM_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
-#define REG_SERCOM1_I2CM_BAUD      (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
-#define REG_SERCOM1_I2CM_INTENCLR  (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
-#define REG_SERCOM1_I2CM_INTENSET  (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
-#define REG_SERCOM1_I2CM_INTFLAG   (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CM_STATUS    (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
-#define REG_SERCOM1_I2CM_SYNCBUSY  (0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
-#define REG_SERCOM1_I2CM_ADDR      (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
-#define REG_SERCOM1_I2CM_DATA      (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
-#define REG_SERCOM1_I2CM_DBGCTRL   (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
-#define REG_SERCOM1_I2CS_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
-#define REG_SERCOM1_I2CS_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
-#define REG_SERCOM1_I2CS_INTENCLR  (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
-#define REG_SERCOM1_I2CS_INTENSET  (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
-#define REG_SERCOM1_I2CS_INTFLAG   (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CS_STATUS    (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
-#define REG_SERCOM1_I2CS_SYNCBUSY  (0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
-#define REG_SERCOM1_I2CS_ADDR      (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
-#define REG_SERCOM1_I2CS_DATA      (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
-#define REG_SERCOM1_SPI_CTRLA      (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
-#define REG_SERCOM1_SPI_CTRLB      (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
-#define REG_SERCOM1_SPI_BAUD       (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
-#define REG_SERCOM1_SPI_INTENCLR   (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
-#define REG_SERCOM1_SPI_INTENSET   (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
-#define REG_SERCOM1_SPI_INTFLAG    (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM1_SPI_STATUS     (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
-#define REG_SERCOM1_SPI_SYNCBUSY   (0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
-#define REG_SERCOM1_SPI_ADDR       (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
-#define REG_SERCOM1_SPI_DATA       (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
-#define REG_SERCOM1_SPI_DBGCTRL    (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
-#define REG_SERCOM1_USART_CTRLA    (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
-#define REG_SERCOM1_USART_CTRLB    (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
-#define REG_SERCOM1_USART_BAUD     (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
-#define REG_SERCOM1_USART_RXPL     (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
-#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
-#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
-#define REG_SERCOM1_USART_INTFLAG  (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM1_USART_STATUS   (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
-#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
-#define REG_SERCOM1_USART_DATA     (0x42000C28U) /**< \brief (SERCOM1) USART Data */
-#define REG_SERCOM1_USART_DBGCTRL  (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
-#else
-#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
-#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
-#define REG_SERCOM1_I2CM_BAUD      (*(RwReg  *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
-#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
-#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
-#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
-#define REG_SERCOM1_I2CM_SYNCBUSY  (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
-#define REG_SERCOM1_I2CM_ADDR      (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
-#define REG_SERCOM1_I2CM_DATA      (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
-#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
-#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
-#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
-#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
-#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
-#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
-#define REG_SERCOM1_I2CS_SYNCBUSY  (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
-#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
-#define REG_SERCOM1_I2CS_DATA      (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
-#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
-#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
-#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
-#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
-#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
-#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
-#define REG_SERCOM1_SPI_SYNCBUSY   (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
-#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
-#define REG_SERCOM1_SPI_DATA       (*(RwReg  *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
-#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
-#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
-#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
-#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
-#define REG_SERCOM1_USART_RXPL     (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
-#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
-#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
-#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
-#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
-#define REG_SERCOM1_USART_DATA     (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
-#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM1 peripheral ========== */
-#define SERCOM1_DMAC_ID_RX          3        // Index of DMA RX trigger
-#define SERCOM1_DMAC_ID_TX          4        // Index of DMA TX trigger
-#define SERCOM1_GCLK_ID_CORE        21       // Index of Generic Clock for Core
-#define SERCOM1_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM1_INT_MSB             6       
-
-#endif /* _SAMD21_SERCOM1_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM1_INSTANCE_
+#define _SAMD21_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD      (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR      (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_ADDR      (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD       (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_ADDR       (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD     (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_DATA     (0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD      (*(RwReg  *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR      (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (*(RwReg  *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg  *)0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_DATA     (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_DMAC_ID_RX          3        // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX          4        // Index of DMA TX trigger
+#define SERCOM1_GCLK_ID_CORE        21       // Index of Generic Clock for Core
+#define SERCOM1_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM1_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h
index 2ca05c2..061f81f 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h
@@ -1,133 +1,133 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM2
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM2_INSTANCE_
-#define _SAMD21_SERCOM2_INSTANCE_
-
-/* ========== Register definition for SERCOM2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM2_I2CM_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
-#define REG_SERCOM2_I2CM_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
-#define REG_SERCOM2_I2CM_BAUD      (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
-#define REG_SERCOM2_I2CM_INTENCLR  (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
-#define REG_SERCOM2_I2CM_INTENSET  (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
-#define REG_SERCOM2_I2CM_INTFLAG   (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CM_STATUS    (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
-#define REG_SERCOM2_I2CM_SYNCBUSY  (0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
-#define REG_SERCOM2_I2CM_ADDR      (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
-#define REG_SERCOM2_I2CM_DATA      (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
-#define REG_SERCOM2_I2CM_DBGCTRL   (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
-#define REG_SERCOM2_I2CS_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
-#define REG_SERCOM2_I2CS_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
-#define REG_SERCOM2_I2CS_INTENCLR  (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
-#define REG_SERCOM2_I2CS_INTENSET  (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
-#define REG_SERCOM2_I2CS_INTFLAG   (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CS_STATUS    (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
-#define REG_SERCOM2_I2CS_SYNCBUSY  (0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
-#define REG_SERCOM2_I2CS_ADDR      (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
-#define REG_SERCOM2_I2CS_DATA      (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
-#define REG_SERCOM2_SPI_CTRLA      (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
-#define REG_SERCOM2_SPI_CTRLB      (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
-#define REG_SERCOM2_SPI_BAUD       (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
-#define REG_SERCOM2_SPI_INTENCLR   (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
-#define REG_SERCOM2_SPI_INTENSET   (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
-#define REG_SERCOM2_SPI_INTFLAG    (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM2_SPI_STATUS     (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
-#define REG_SERCOM2_SPI_SYNCBUSY   (0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
-#define REG_SERCOM2_SPI_ADDR       (0x42001024U) /**< \brief (SERCOM2) SPI Address */
-#define REG_SERCOM2_SPI_DATA       (0x42001028U) /**< \brief (SERCOM2) SPI Data */
-#define REG_SERCOM2_SPI_DBGCTRL    (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
-#define REG_SERCOM2_USART_CTRLA    (0x42001000U) /**< \brief (SERCOM2) USART Control A */
-#define REG_SERCOM2_USART_CTRLB    (0x42001004U) /**< \brief (SERCOM2) USART Control B */
-#define REG_SERCOM2_USART_BAUD     (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
-#define REG_SERCOM2_USART_RXPL     (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
-#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
-#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
-#define REG_SERCOM2_USART_INTFLAG  (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM2_USART_STATUS   (0x4200101AU) /**< \brief (SERCOM2) USART Status */
-#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
-#define REG_SERCOM2_USART_DATA     (0x42001028U) /**< \brief (SERCOM2) USART Data */
-#define REG_SERCOM2_USART_DBGCTRL  (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
-#else
-#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
-#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
-#define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
-#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
-#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
-#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
-#define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
-#define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
-#define REG_SERCOM2_I2CM_DATA      (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
-#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
-#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
-#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
-#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
-#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
-#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
-#define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
-#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
-#define REG_SERCOM2_I2CS_DATA      (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
-#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
-#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
-#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
-#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
-#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
-#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
-#define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
-#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
-#define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
-#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
-#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
-#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
-#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
-#define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
-#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
-#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
-#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
-#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
-#define REG_SERCOM2_USART_DATA     (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
-#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM2 peripheral ========== */
-#define SERCOM2_DMAC_ID_RX          5        // Index of DMA RX trigger
-#define SERCOM2_DMAC_ID_TX          6        // Index of DMA TX trigger
-#define SERCOM2_GCLK_ID_CORE        22       // Index of Generic Clock for Core
-#define SERCOM2_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM2_INT_MSB             6       
-
-#endif /* _SAMD21_SERCOM2_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM2_INSTANCE_
+#define _SAMD21_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD      (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR      (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_ADDR      (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD       (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_ADDR       (0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD     (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_DATA     (0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_DATA     (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_DMAC_ID_RX          5        // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX          6        // Index of DMA TX trigger
+#define SERCOM2_GCLK_ID_CORE        22       // Index of Generic Clock for Core
+#define SERCOM2_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM2_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h
index a9ae269..bcf586c 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h
@@ -1,133 +1,133 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM3
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM3_INSTANCE_
-#define _SAMD21_SERCOM3_INSTANCE_
-
-/* ========== Register definition for SERCOM3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM3_I2CM_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
-#define REG_SERCOM3_I2CM_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
-#define REG_SERCOM3_I2CM_BAUD      (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
-#define REG_SERCOM3_I2CM_INTENCLR  (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
-#define REG_SERCOM3_I2CM_INTENSET  (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
-#define REG_SERCOM3_I2CM_INTFLAG   (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CM_STATUS    (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
-#define REG_SERCOM3_I2CM_SYNCBUSY  (0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
-#define REG_SERCOM3_I2CM_ADDR      (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
-#define REG_SERCOM3_I2CM_DATA      (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
-#define REG_SERCOM3_I2CM_DBGCTRL   (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
-#define REG_SERCOM3_I2CS_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
-#define REG_SERCOM3_I2CS_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
-#define REG_SERCOM3_I2CS_INTENCLR  (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
-#define REG_SERCOM3_I2CS_INTENSET  (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
-#define REG_SERCOM3_I2CS_INTFLAG   (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CS_STATUS    (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
-#define REG_SERCOM3_I2CS_SYNCBUSY  (0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
-#define REG_SERCOM3_I2CS_ADDR      (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
-#define REG_SERCOM3_I2CS_DATA      (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
-#define REG_SERCOM3_SPI_CTRLA      (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
-#define REG_SERCOM3_SPI_CTRLB      (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
-#define REG_SERCOM3_SPI_BAUD       (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
-#define REG_SERCOM3_SPI_INTENCLR   (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
-#define REG_SERCOM3_SPI_INTENSET   (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
-#define REG_SERCOM3_SPI_INTFLAG    (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM3_SPI_STATUS     (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
-#define REG_SERCOM3_SPI_SYNCBUSY   (0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
-#define REG_SERCOM3_SPI_ADDR       (0x42001424U) /**< \brief (SERCOM3) SPI Address */
-#define REG_SERCOM3_SPI_DATA       (0x42001428U) /**< \brief (SERCOM3) SPI Data */
-#define REG_SERCOM3_SPI_DBGCTRL    (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
-#define REG_SERCOM3_USART_CTRLA    (0x42001400U) /**< \brief (SERCOM3) USART Control A */
-#define REG_SERCOM3_USART_CTRLB    (0x42001404U) /**< \brief (SERCOM3) USART Control B */
-#define REG_SERCOM3_USART_BAUD     (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
-#define REG_SERCOM3_USART_RXPL     (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
-#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
-#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
-#define REG_SERCOM3_USART_INTFLAG  (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM3_USART_STATUS   (0x4200141AU) /**< \brief (SERCOM3) USART Status */
-#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
-#define REG_SERCOM3_USART_DATA     (0x42001428U) /**< \brief (SERCOM3) USART Data */
-#define REG_SERCOM3_USART_DBGCTRL  (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
-#else
-#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
-#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
-#define REG_SERCOM3_I2CM_BAUD      (*(RwReg  *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
-#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
-#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
-#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
-#define REG_SERCOM3_I2CM_SYNCBUSY  (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
-#define REG_SERCOM3_I2CM_ADDR      (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
-#define REG_SERCOM3_I2CM_DATA      (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
-#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
-#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
-#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
-#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
-#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
-#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
-#define REG_SERCOM3_I2CS_SYNCBUSY  (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
-#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
-#define REG_SERCOM3_I2CS_DATA      (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
-#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
-#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
-#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
-#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
-#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
-#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
-#define REG_SERCOM3_SPI_SYNCBUSY   (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
-#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
-#define REG_SERCOM3_SPI_DATA       (*(RwReg  *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
-#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
-#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
-#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
-#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
-#define REG_SERCOM3_USART_RXPL     (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
-#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
-#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
-#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
-#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
-#define REG_SERCOM3_USART_DATA     (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
-#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM3 peripheral ========== */
-#define SERCOM3_DMAC_ID_RX          7        // Index of DMA RX trigger
-#define SERCOM3_DMAC_ID_TX          8        // Index of DMA TX trigger
-#define SERCOM3_GCLK_ID_CORE        23       // Index of Generic Clock for Core
-#define SERCOM3_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM3_INT_MSB             6       
-
-#endif /* _SAMD21_SERCOM3_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM3_INSTANCE_
+#define _SAMD21_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD      (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR      (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_ADDR      (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD       (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_ADDR       (0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD     (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_DATA     (0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD      (*(RwReg  *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR      (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (*(RwReg  *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg  *)0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_DATA     (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_DMAC_ID_RX          7        // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX          8        // Index of DMA TX trigger
+#define SERCOM3_GCLK_ID_CORE        23       // Index of Generic Clock for Core
+#define SERCOM3_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM3_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h
index 053fb43..5e4474a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h
@@ -1,133 +1,133 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM4
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM4_INSTANCE_
-#define _SAMD21_SERCOM4_INSTANCE_
-
-/* ========== Register definition for SERCOM4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM4_I2CM_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
-#define REG_SERCOM4_I2CM_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
-#define REG_SERCOM4_I2CM_BAUD      (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
-#define REG_SERCOM4_I2CM_INTENCLR  (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
-#define REG_SERCOM4_I2CM_INTENSET  (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
-#define REG_SERCOM4_I2CM_INTFLAG   (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CM_STATUS    (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
-#define REG_SERCOM4_I2CM_SYNCBUSY  (0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
-#define REG_SERCOM4_I2CM_ADDR      (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
-#define REG_SERCOM4_I2CM_DATA      (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
-#define REG_SERCOM4_I2CM_DBGCTRL   (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
-#define REG_SERCOM4_I2CS_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
-#define REG_SERCOM4_I2CS_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
-#define REG_SERCOM4_I2CS_INTENCLR  (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
-#define REG_SERCOM4_I2CS_INTENSET  (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
-#define REG_SERCOM4_I2CS_INTFLAG   (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CS_STATUS    (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
-#define REG_SERCOM4_I2CS_SYNCBUSY  (0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
-#define REG_SERCOM4_I2CS_ADDR      (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
-#define REG_SERCOM4_I2CS_DATA      (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
-#define REG_SERCOM4_SPI_CTRLA      (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
-#define REG_SERCOM4_SPI_CTRLB      (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
-#define REG_SERCOM4_SPI_BAUD       (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
-#define REG_SERCOM4_SPI_INTENCLR   (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
-#define REG_SERCOM4_SPI_INTENSET   (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
-#define REG_SERCOM4_SPI_INTFLAG    (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM4_SPI_STATUS     (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
-#define REG_SERCOM4_SPI_SYNCBUSY   (0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
-#define REG_SERCOM4_SPI_ADDR       (0x42001824U) /**< \brief (SERCOM4) SPI Address */
-#define REG_SERCOM4_SPI_DATA       (0x42001828U) /**< \brief (SERCOM4) SPI Data */
-#define REG_SERCOM4_SPI_DBGCTRL    (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
-#define REG_SERCOM4_USART_CTRLA    (0x42001800U) /**< \brief (SERCOM4) USART Control A */
-#define REG_SERCOM4_USART_CTRLB    (0x42001804U) /**< \brief (SERCOM4) USART Control B */
-#define REG_SERCOM4_USART_BAUD     (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
-#define REG_SERCOM4_USART_RXPL     (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
-#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
-#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
-#define REG_SERCOM4_USART_INTFLAG  (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM4_USART_STATUS   (0x4200181AU) /**< \brief (SERCOM4) USART Status */
-#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
-#define REG_SERCOM4_USART_DATA     (0x42001828U) /**< \brief (SERCOM4) USART Data */
-#define REG_SERCOM4_USART_DBGCTRL  (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
-#else
-#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
-#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
-#define REG_SERCOM4_I2CM_BAUD      (*(RwReg  *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
-#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
-#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
-#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
-#define REG_SERCOM4_I2CM_SYNCBUSY  (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
-#define REG_SERCOM4_I2CM_ADDR      (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
-#define REG_SERCOM4_I2CM_DATA      (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
-#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
-#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
-#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
-#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
-#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
-#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
-#define REG_SERCOM4_I2CS_SYNCBUSY  (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
-#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
-#define REG_SERCOM4_I2CS_DATA      (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
-#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
-#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
-#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
-#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
-#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
-#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
-#define REG_SERCOM4_SPI_SYNCBUSY   (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
-#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
-#define REG_SERCOM4_SPI_DATA       (*(RwReg  *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
-#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
-#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
-#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
-#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
-#define REG_SERCOM4_USART_RXPL     (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
-#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
-#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
-#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
-#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
-#define REG_SERCOM4_USART_DATA     (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
-#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM4 peripheral ========== */
-#define SERCOM4_DMAC_ID_RX          9        // Index of DMA RX trigger
-#define SERCOM4_DMAC_ID_TX          10       // Index of DMA TX trigger
-#define SERCOM4_GCLK_ID_CORE        24       // Index of Generic Clock for Core
-#define SERCOM4_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM4_INT_MSB             6       
-
-#endif /* _SAMD21_SERCOM4_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM4_INSTANCE_
+#define _SAMD21_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD      (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR      (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_ADDR      (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD       (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_ADDR       (0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD     (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_DATA     (0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD      (*(RwReg  *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR      (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (*(RwReg  *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg  *)0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_DATA     (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_DMAC_ID_RX          9        // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX          10       // Index of DMA TX trigger
+#define SERCOM4_GCLK_ID_CORE        24       // Index of Generic Clock for Core
+#define SERCOM4_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM4_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h
index 1ecc982..0da3c74 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h
@@ -1,133 +1,133 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM5
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SERCOM5_INSTANCE_
-#define _SAMD21_SERCOM5_INSTANCE_
-
-/* ========== Register definition for SERCOM5 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM5_I2CM_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
-#define REG_SERCOM5_I2CM_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
-#define REG_SERCOM5_I2CM_BAUD      (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
-#define REG_SERCOM5_I2CM_INTENCLR  (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
-#define REG_SERCOM5_I2CM_INTENSET  (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
-#define REG_SERCOM5_I2CM_INTFLAG   (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CM_STATUS    (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
-#define REG_SERCOM5_I2CM_SYNCBUSY  (0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
-#define REG_SERCOM5_I2CM_ADDR      (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
-#define REG_SERCOM5_I2CM_DATA      (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
-#define REG_SERCOM5_I2CM_DBGCTRL   (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
-#define REG_SERCOM5_I2CS_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
-#define REG_SERCOM5_I2CS_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
-#define REG_SERCOM5_I2CS_INTENCLR  (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
-#define REG_SERCOM5_I2CS_INTENSET  (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
-#define REG_SERCOM5_I2CS_INTFLAG   (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CS_STATUS    (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
-#define REG_SERCOM5_I2CS_SYNCBUSY  (0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
-#define REG_SERCOM5_I2CS_ADDR      (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
-#define REG_SERCOM5_I2CS_DATA      (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
-#define REG_SERCOM5_SPI_CTRLA      (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
-#define REG_SERCOM5_SPI_CTRLB      (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
-#define REG_SERCOM5_SPI_BAUD       (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
-#define REG_SERCOM5_SPI_INTENCLR   (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
-#define REG_SERCOM5_SPI_INTENSET   (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
-#define REG_SERCOM5_SPI_INTFLAG    (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM5_SPI_STATUS     (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
-#define REG_SERCOM5_SPI_SYNCBUSY   (0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
-#define REG_SERCOM5_SPI_ADDR       (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
-#define REG_SERCOM5_SPI_DATA       (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
-#define REG_SERCOM5_SPI_DBGCTRL    (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
-#define REG_SERCOM5_USART_CTRLA    (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
-#define REG_SERCOM5_USART_CTRLB    (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
-#define REG_SERCOM5_USART_BAUD     (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
-#define REG_SERCOM5_USART_RXPL     (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
-#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
-#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
-#define REG_SERCOM5_USART_INTFLAG  (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM5_USART_STATUS   (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
-#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
-#define REG_SERCOM5_USART_DATA     (0x42001C28U) /**< \brief (SERCOM5) USART Data */
-#define REG_SERCOM5_USART_DBGCTRL  (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
-#else
-#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
-#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
-#define REG_SERCOM5_I2CM_BAUD      (*(RwReg  *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
-#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
-#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
-#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
-#define REG_SERCOM5_I2CM_SYNCBUSY  (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
-#define REG_SERCOM5_I2CM_ADDR      (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
-#define REG_SERCOM5_I2CM_DATA      (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
-#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
-#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
-#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
-#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
-#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
-#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
-#define REG_SERCOM5_I2CS_SYNCBUSY  (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
-#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
-#define REG_SERCOM5_I2CS_DATA      (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
-#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
-#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
-#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
-#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
-#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
-#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
-#define REG_SERCOM5_SPI_SYNCBUSY   (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
-#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
-#define REG_SERCOM5_SPI_DATA       (*(RwReg  *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
-#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
-#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
-#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
-#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
-#define REG_SERCOM5_USART_RXPL     (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
-#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
-#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
-#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
-#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
-#define REG_SERCOM5_USART_DATA     (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
-#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM5 peripheral ========== */
-#define SERCOM5_DMAC_ID_RX          11       // Index of DMA RX trigger
-#define SERCOM5_DMAC_ID_TX          12       // Index of DMA TX trigger
-#define SERCOM5_GCLK_ID_CORE        25       // Index of Generic Clock for Core
-#define SERCOM5_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM5_INT_MSB             6       
-
-#endif /* _SAMD21_SERCOM5_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM5_INSTANCE_
+#define _SAMD21_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD      (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR      (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_ADDR      (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD       (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_ADDR       (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD     (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_DATA     (0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD      (*(RwReg  *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR      (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (*(RwReg  *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg  *)0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_DATA     (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_DMAC_ID_RX          11       // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX          12       // Index of DMA TX trigger
+#define SERCOM5_GCLK_ID_CORE        25       // Index of Generic Clock for Core
+#define SERCOM5_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM5_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
index c56d1c5..0876a20 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
@@ -1,111 +1,111 @@
-/**
- * \file
- *
- * \brief Instance description for SYSCTRL
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_SYSCTRL_INSTANCE_
-#define _SAMD21_SYSCTRL_INSTANCE_
-
-/* ========== Register definition for SYSCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SYSCTRL_INTENCLR       (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
-#define REG_SYSCTRL_INTENSET       (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
-#define REG_SYSCTRL_INTFLAG        (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
-#define REG_SYSCTRL_PCLKSR         (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
-#define REG_SYSCTRL_XOSC           (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
-#define REG_SYSCTRL_XOSC32K        (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define REG_SYSCTRL_OSC32K         (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
-#define REG_SYSCTRL_OSCULP32K      (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define REG_SYSCTRL_OSC8M          (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
-#define REG_SYSCTRL_DFLLCTRL       (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
-#define REG_SYSCTRL_DFLLVAL        (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
-#define REG_SYSCTRL_DFLLMUL        (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
-#define REG_SYSCTRL_DFLLSYNC       (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
-#define REG_SYSCTRL_BOD33          (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
-#define REG_SYSCTRL_VREG           (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
-#define REG_SYSCTRL_VREF           (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
-#define REG_SYSCTRL_DPLLCTRLA      (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
-#define REG_SYSCTRL_DPLLRATIO      (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
-#define REG_SYSCTRL_DPLLCTRLB      (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
-#define REG_SYSCTRL_DPLLSTATUS     (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
-#else
-#define REG_SYSCTRL_INTENCLR       (*(RwReg  *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
-#define REG_SYSCTRL_INTENSET       (*(RwReg  *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
-#define REG_SYSCTRL_INTFLAG        (*(RwReg  *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
-#define REG_SYSCTRL_PCLKSR         (*(RoReg  *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
-#define REG_SYSCTRL_XOSC           (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
-#define REG_SYSCTRL_XOSC32K        (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define REG_SYSCTRL_OSC32K         (*(RwReg  *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
-#define REG_SYSCTRL_OSCULP32K      (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define REG_SYSCTRL_OSC8M          (*(RwReg  *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
-#define REG_SYSCTRL_DFLLCTRL       (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
-#define REG_SYSCTRL_DFLLVAL        (*(RwReg  *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
-#define REG_SYSCTRL_DFLLMUL        (*(RwReg  *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
-#define REG_SYSCTRL_DFLLSYNC       (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
-#define REG_SYSCTRL_BOD33          (*(RwReg  *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
-#define REG_SYSCTRL_VREG           (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
-#define REG_SYSCTRL_VREF           (*(RwReg  *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
-#define REG_SYSCTRL_DPLLCTRLA      (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
-#define REG_SYSCTRL_DPLLRATIO      (*(RwReg  *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
-#define REG_SYSCTRL_DPLLCTRLB      (*(RwReg  *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
-#define REG_SYSCTRL_DPLLSTATUS     (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SYSCTRL peripheral ========== */
-#define SYSCTRL_BGAP_CALIB_MSB      11      
-#define SYSCTRL_BOD33_CALIB_MSB     5       
-#define SYSCTRL_DFLL48M_COARSE_MSB  5       
-#define SYSCTRL_DFLL48M_FINE_MSB    9       
-#define SYSCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
-#define SYSCTRL_GCLK_ID_FDPLL       1        // Index of Generic Clock for DPLL
-#define SYSCTRL_GCLK_ID_FDPLL32K    2        // Index of Generic Clock for DPLL 32K
-#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6       
-#define SYSCTRL_POR33_ENTEST_MSB    1       
-#define SYSCTRL_SYSTEM_CLOCK        1000000  // Initial system clock frequency
-#define SYSCTRL_ULPVREF_DIVLEV_MSB  3       
-#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1       
-#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2       
-#define SYSCTRL_VREF_CONTROL_MSB    48      
-#define SYSCTRL_VREF_STATUS_MSB     7       
-#define SYSCTRL_VREG_LEVEL_MSB      2       
-#define SYSCTRL_BOD12_VERSION       0x112   
-#define SYSCTRL_BOD33_VERSION       0x112   
-#define SYSCTRL_DFLL48M_VERSION     0x301   
-#define SYSCTRL_FDPLL_VERSION       0x111   
-#define SYSCTRL_OSCULP32K_VERSION   0x111   
-#define SYSCTRL_OSC8M_VERSION       0x120   
-#define SYSCTRL_OSC32K_VERSION      0x112   
-#define SYSCTRL_VREF_VERSION        0x201   
-#define SYSCTRL_VREG_VERSION        0x201   
-#define SYSCTRL_XOSC_VERSION        0x114   
-#define SYSCTRL_XOSC32K_VERSION     0x113   
-
-#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for SYSCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_INSTANCE_
+#define _SAMD21_SYSCTRL_INSTANCE_
+
+/* ========== Register definition for SYSCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SYSCTRL_INTENCLR       (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K        (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K         (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K      (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M          (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL       (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL        (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL        (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33          (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF           (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA      (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO      (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB      (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS     (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#else
+#define REG_SYSCTRL_INTENCLR       (*(RwReg  *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (*(RwReg  *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (*(RwReg  *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (*(RoReg  *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K        (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K         (*(RwReg  *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K      (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M          (*(RwReg  *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL       (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL        (*(RwReg  *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL        (*(RwReg  *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33          (*(RwReg  *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF           (*(RwReg  *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA      (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO      (*(RwReg  *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB      (*(RwReg  *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS     (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SYSCTRL peripheral ========== */
+#define SYSCTRL_BGAP_CALIB_MSB      11      
+#define SYSCTRL_BOD33_CALIB_MSB     5       
+#define SYSCTRL_DFLL48M_COARSE_MSB  5       
+#define SYSCTRL_DFLL48M_FINE_MSB    9       
+#define SYSCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
+#define SYSCTRL_GCLK_ID_FDPLL       1        // Index of Generic Clock for DPLL
+#define SYSCTRL_GCLK_ID_FDPLL32K    2        // Index of Generic Clock for DPLL 32K
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6       
+#define SYSCTRL_POR33_ENTEST_MSB    1       
+#define SYSCTRL_SYSTEM_CLOCK        1000000  // Initial system clock frequency
+#define SYSCTRL_ULPVREF_DIVLEV_MSB  3       
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1       
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2       
+#define SYSCTRL_VREF_CONTROL_MSB    48      
+#define SYSCTRL_VREF_STATUS_MSB     7       
+#define SYSCTRL_VREG_LEVEL_MSB      2       
+#define SYSCTRL_BOD12_VERSION       0x112   
+#define SYSCTRL_BOD33_VERSION       0x112   
+#define SYSCTRL_DFLL48M_VERSION     0x301   
+#define SYSCTRL_FDPLL_VERSION       0x111   
+#define SYSCTRL_OSCULP32K_VERSION   0x111   
+#define SYSCTRL_OSC8M_VERSION       0x120   
+#define SYSCTRL_OSC32K_VERSION      0x112   
+#define SYSCTRL_VREF_VERSION        0x201   
+#define SYSCTRL_VREG_VERSION        0x201   
+#define SYSCTRL_XOSC_VERSION        0x114   
+#define SYSCTRL_XOSC32K_VERSION     0x113   
+
+#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h
index 78d066e..37ab554 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h
@@ -1,101 +1,101 @@
-/**
- * \file
- *
- * \brief Instance description for TC3
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TC3_INSTANCE_
-#define _SAMD21_TC3_INSTANCE_
-
-/* ========== Register definition for TC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC3_CTRLA              (0x42002C00U) /**< \brief (TC3) Control A */
-#define REG_TC3_READREQ            (0x42002C02U) /**< \brief (TC3) Read Request */
-#define REG_TC3_CTRLBCLR           (0x42002C04U) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET           (0x42002C05U) /**< \brief (TC3) Control B Set */
-#define REG_TC3_CTRLC              (0x42002C06U) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL            (0x42002C08U) /**< \brief (TC3) Debug Control */
-#define REG_TC3_EVCTRL             (0x42002C0AU) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR           (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET           (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG            (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS             (0x42002C0FU) /**< \brief (TC3) Status */
-#define REG_TC3_COUNT16_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
-#define REG_TC3_COUNT16_CC0        (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
-#define REG_TC3_COUNT16_CC1        (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
-#define REG_TC3_COUNT32_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
-#define REG_TC3_COUNT32_CC0        (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
-#define REG_TC3_COUNT32_CC1        (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
-#define REG_TC3_COUNT8_COUNT       (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
-#define REG_TC3_COUNT8_PER         (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
-#define REG_TC3_COUNT8_CC0         (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
-#define REG_TC3_COUNT8_CC1         (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC3_CTRLA              (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
-#define REG_TC3_READREQ            (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
-#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
-#define REG_TC3_CTRLC              (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
-#define REG_TC3_EVCTRL             (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR           (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET           (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG            (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS             (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
-#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
-#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
-#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
-#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
-#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
-#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
-#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
-#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
-#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
-#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC3 peripheral ========== */
-#define TC3_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC3_CC16_NUM                2        // Number of 16-bit Counters
-#define TC3_CC32_NUM                2        // Number of 32-bit Counters
-#define TC3_DITHERING_EXT           0        // Dithering feature implemented
-#define TC3_DMAC_ID_MC_0            25
-#define TC3_DMAC_ID_MC_1            26
-#define TC3_DMAC_ID_MC_LSB          25
-#define TC3_DMAC_ID_MC_MSB          26
-#define TC3_DMAC_ID_MC_SIZE         2
-#define TC3_DMAC_ID_OVF             24       // Indexes of DMA Overflow trigger
-#define TC3_GCLK_ID                 27       // Index of Generic Clock
-#define TC3_MASTER                  0       
-#define TC3_OW_NUM                  2        // Number of Output Waveforms
-#define TC3_PERIOD_EXT              0        // Period feature implemented
-#define TC3_SHADOW_EXT              0        // Shadow feature implemented
-
-#endif /* _SAMD21_TC3_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC3_INSTANCE_
+#define _SAMD21_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA              (0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC3_CTRLA              (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC3_CC16_NUM                2        // Number of 16-bit Counters
+#define TC3_CC32_NUM                2        // Number of 32-bit Counters
+#define TC3_DITHERING_EXT           0        // Dithering feature implemented
+#define TC3_DMAC_ID_MC_0            25
+#define TC3_DMAC_ID_MC_1            26
+#define TC3_DMAC_ID_MC_LSB          25
+#define TC3_DMAC_ID_MC_MSB          26
+#define TC3_DMAC_ID_MC_SIZE         2
+#define TC3_DMAC_ID_OVF             24       // Indexes of DMA Overflow trigger
+#define TC3_GCLK_ID                 27       // Index of Generic Clock
+#define TC3_MASTER                  0       
+#define TC3_OW_NUM                  2        // Number of Output Waveforms
+#define TC3_PERIOD_EXT              0        // Period feature implemented
+#define TC3_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC3_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h
index d53e394..b2d2802 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h
@@ -1,101 +1,101 @@
-/**
- * \file
- *
- * \brief Instance description for TC4
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TC4_INSTANCE_
-#define _SAMD21_TC4_INSTANCE_
-
-/* ========== Register definition for TC4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC4_CTRLA              (0x42003000U) /**< \brief (TC4) Control A */
-#define REG_TC4_READREQ            (0x42003002U) /**< \brief (TC4) Read Request */
-#define REG_TC4_CTRLBCLR           (0x42003004U) /**< \brief (TC4) Control B Clear */
-#define REG_TC4_CTRLBSET           (0x42003005U) /**< \brief (TC4) Control B Set */
-#define REG_TC4_CTRLC              (0x42003006U) /**< \brief (TC4) Control C */
-#define REG_TC4_DBGCTRL            (0x42003008U) /**< \brief (TC4) Debug Control */
-#define REG_TC4_EVCTRL             (0x4200300AU) /**< \brief (TC4) Event Control */
-#define REG_TC4_INTENCLR           (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
-#define REG_TC4_INTENSET           (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
-#define REG_TC4_INTFLAG            (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
-#define REG_TC4_STATUS             (0x4200300FU) /**< \brief (TC4) Status */
-#define REG_TC4_COUNT16_COUNT      (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
-#define REG_TC4_COUNT16_CC0        (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
-#define REG_TC4_COUNT16_CC1        (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
-#define REG_TC4_COUNT32_COUNT      (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
-#define REG_TC4_COUNT32_CC0        (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
-#define REG_TC4_COUNT32_CC1        (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
-#define REG_TC4_COUNT8_COUNT       (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
-#define REG_TC4_COUNT8_PER         (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
-#define REG_TC4_COUNT8_CC0         (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
-#define REG_TC4_COUNT8_CC1         (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC4_CTRLA              (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
-#define REG_TC4_READREQ            (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
-#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
-#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
-#define REG_TC4_CTRLC              (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
-#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
-#define REG_TC4_EVCTRL             (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
-#define REG_TC4_INTENCLR           (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
-#define REG_TC4_INTENSET           (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
-#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
-#define REG_TC4_STATUS             (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
-#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
-#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
-#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
-#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
-#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
-#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
-#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
-#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
-#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
-#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC4 peripheral ========== */
-#define TC4_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC4_CC16_NUM                2        // Number of 16-bit Counters
-#define TC4_CC32_NUM                2        // Number of 32-bit Counters
-#define TC4_DITHERING_EXT           0        // Dithering feature implemented
-#define TC4_DMAC_ID_MC_0            28
-#define TC4_DMAC_ID_MC_1            29
-#define TC4_DMAC_ID_MC_LSB          28
-#define TC4_DMAC_ID_MC_MSB          29
-#define TC4_DMAC_ID_MC_SIZE         2
-#define TC4_DMAC_ID_OVF             27       // Indexes of DMA Overflow trigger
-#define TC4_GCLK_ID                 28       // Index of Generic Clock
-#define TC4_MASTER                  1       
-#define TC4_OW_NUM                  2        // Number of Output Waveforms
-#define TC4_PERIOD_EXT              0        // Period feature implemented
-#define TC4_SHADOW_EXT              0        // Shadow feature implemented
-
-#endif /* _SAMD21_TC4_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC4_INSTANCE_
+#define _SAMD21_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA              (0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC4_CTRLA              (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC4_CC16_NUM                2        // Number of 16-bit Counters
+#define TC4_CC32_NUM                2        // Number of 32-bit Counters
+#define TC4_DITHERING_EXT           0        // Dithering feature implemented
+#define TC4_DMAC_ID_MC_0            28
+#define TC4_DMAC_ID_MC_1            29
+#define TC4_DMAC_ID_MC_LSB          28
+#define TC4_DMAC_ID_MC_MSB          29
+#define TC4_DMAC_ID_MC_SIZE         2
+#define TC4_DMAC_ID_OVF             27       // Indexes of DMA Overflow trigger
+#define TC4_GCLK_ID                 28       // Index of Generic Clock
+#define TC4_MASTER                  1       
+#define TC4_OW_NUM                  2        // Number of Output Waveforms
+#define TC4_PERIOD_EXT              0        // Period feature implemented
+#define TC4_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC4_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h
index 3acc4ff..c62ed69 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h
@@ -1,101 +1,101 @@
-/**
- * \file
- *
- * \brief Instance description for TC5
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TC5_INSTANCE_
-#define _SAMD21_TC5_INSTANCE_
-
-/* ========== Register definition for TC5 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC5_CTRLA              (0x42003400U) /**< \brief (TC5) Control A */
-#define REG_TC5_READREQ            (0x42003402U) /**< \brief (TC5) Read Request */
-#define REG_TC5_CTRLBCLR           (0x42003404U) /**< \brief (TC5) Control B Clear */
-#define REG_TC5_CTRLBSET           (0x42003405U) /**< \brief (TC5) Control B Set */
-#define REG_TC5_CTRLC              (0x42003406U) /**< \brief (TC5) Control C */
-#define REG_TC5_DBGCTRL            (0x42003408U) /**< \brief (TC5) Debug Control */
-#define REG_TC5_EVCTRL             (0x4200340AU) /**< \brief (TC5) Event Control */
-#define REG_TC5_INTENCLR           (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
-#define REG_TC5_INTENSET           (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
-#define REG_TC5_INTFLAG            (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
-#define REG_TC5_STATUS             (0x4200340FU) /**< \brief (TC5) Status */
-#define REG_TC5_COUNT16_COUNT      (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
-#define REG_TC5_COUNT16_CC0        (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
-#define REG_TC5_COUNT16_CC1        (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
-#define REG_TC5_COUNT32_COUNT      (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
-#define REG_TC5_COUNT32_CC0        (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
-#define REG_TC5_COUNT32_CC1        (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
-#define REG_TC5_COUNT8_COUNT       (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
-#define REG_TC5_COUNT8_PER         (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
-#define REG_TC5_COUNT8_CC0         (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
-#define REG_TC5_COUNT8_CC1         (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC5_CTRLA              (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
-#define REG_TC5_READREQ            (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
-#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
-#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
-#define REG_TC5_CTRLC              (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
-#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
-#define REG_TC5_EVCTRL             (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
-#define REG_TC5_INTENCLR           (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
-#define REG_TC5_INTENSET           (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
-#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
-#define REG_TC5_STATUS             (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
-#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
-#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
-#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
-#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
-#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
-#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
-#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
-#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
-#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
-#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC5 peripheral ========== */
-#define TC5_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC5_CC16_NUM                2        // Number of 16-bit Counters
-#define TC5_CC32_NUM                2        // Number of 32-bit Counters
-#define TC5_DITHERING_EXT           0        // Dithering feature implemented
-#define TC5_DMAC_ID_MC_0            31
-#define TC5_DMAC_ID_MC_1            32
-#define TC5_DMAC_ID_MC_LSB          31
-#define TC5_DMAC_ID_MC_MSB          32
-#define TC5_DMAC_ID_MC_SIZE         2
-#define TC5_DMAC_ID_OVF             30       // Indexes of DMA Overflow trigger
-#define TC5_GCLK_ID                 28       // Index of Generic Clock
-#define TC5_MASTER                  0       
-#define TC5_OW_NUM                  2        // Number of Output Waveforms
-#define TC5_PERIOD_EXT              0        // Period feature implemented
-#define TC5_SHADOW_EXT              0        // Shadow feature implemented
-
-#endif /* _SAMD21_TC5_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC5_INSTANCE_
+#define _SAMD21_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA              (0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC5_CTRLA              (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC5_CC16_NUM                2        // Number of 16-bit Counters
+#define TC5_CC32_NUM                2        // Number of 32-bit Counters
+#define TC5_DITHERING_EXT           0        // Dithering feature implemented
+#define TC5_DMAC_ID_MC_0            31
+#define TC5_DMAC_ID_MC_1            32
+#define TC5_DMAC_ID_MC_LSB          31
+#define TC5_DMAC_ID_MC_MSB          32
+#define TC5_DMAC_ID_MC_SIZE         2
+#define TC5_DMAC_ID_OVF             30       // Indexes of DMA Overflow trigger
+#define TC5_GCLK_ID                 28       // Index of Generic Clock
+#define TC5_MASTER                  0       
+#define TC5_OW_NUM                  2        // Number of Output Waveforms
+#define TC5_PERIOD_EXT              0        // Period feature implemented
+#define TC5_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC5_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h
index 715253d..5d5efd1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h
@@ -1,101 +1,101 @@
-/**
- * \file
- *
- * \brief Instance description for TC6
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TC6_INSTANCE_
-#define _SAMD21_TC6_INSTANCE_
-
-/* ========== Register definition for TC6 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC6_CTRLA              (0x42003800U) /**< \brief (TC6) Control A */
-#define REG_TC6_READREQ            (0x42003802U) /**< \brief (TC6) Read Request */
-#define REG_TC6_CTRLBCLR           (0x42003804U) /**< \brief (TC6) Control B Clear */
-#define REG_TC6_CTRLBSET           (0x42003805U) /**< \brief (TC6) Control B Set */
-#define REG_TC6_CTRLC              (0x42003806U) /**< \brief (TC6) Control C */
-#define REG_TC6_DBGCTRL            (0x42003808U) /**< \brief (TC6) Debug Control */
-#define REG_TC6_EVCTRL             (0x4200380AU) /**< \brief (TC6) Event Control */
-#define REG_TC6_INTENCLR           (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
-#define REG_TC6_INTENSET           (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
-#define REG_TC6_INTFLAG            (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
-#define REG_TC6_STATUS             (0x4200380FU) /**< \brief (TC6) Status */
-#define REG_TC6_COUNT16_COUNT      (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
-#define REG_TC6_COUNT16_CC0        (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
-#define REG_TC6_COUNT16_CC1        (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
-#define REG_TC6_COUNT32_COUNT      (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
-#define REG_TC6_COUNT32_CC0        (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
-#define REG_TC6_COUNT32_CC1        (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
-#define REG_TC6_COUNT8_COUNT       (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
-#define REG_TC6_COUNT8_PER         (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
-#define REG_TC6_COUNT8_CC0         (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
-#define REG_TC6_COUNT8_CC1         (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC6_CTRLA              (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
-#define REG_TC6_READREQ            (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
-#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
-#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
-#define REG_TC6_CTRLC              (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
-#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
-#define REG_TC6_EVCTRL             (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
-#define REG_TC6_INTENCLR           (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
-#define REG_TC6_INTENSET           (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
-#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
-#define REG_TC6_STATUS             (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
-#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
-#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
-#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
-#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
-#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
-#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
-#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
-#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
-#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
-#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC6 peripheral ========== */
-#define TC6_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC6_CC16_NUM                2        // Number of 16-bit Counters
-#define TC6_CC32_NUM                2        // Number of 32-bit Counters
-#define TC6_DITHERING_EXT           0        // Dithering feature implemented
-#define TC6_DMAC_ID_MC_0            34
-#define TC6_DMAC_ID_MC_1            35
-#define TC6_DMAC_ID_MC_LSB          34
-#define TC6_DMAC_ID_MC_MSB          35
-#define TC6_DMAC_ID_MC_SIZE         2
-#define TC6_DMAC_ID_OVF             33       // Indexes of DMA Overflow trigger
-#define TC6_GCLK_ID                 29       // Index of Generic Clock
-#define TC6_MASTER                  1       
-#define TC6_OW_NUM                  2        // Number of Output Waveforms
-#define TC6_PERIOD_EXT              0        // Period feature implemented
-#define TC6_SHADOW_EXT              0        // Shadow feature implemented
-
-#endif /* _SAMD21_TC6_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC6_INSTANCE_
+#define _SAMD21_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA              (0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC6_CTRLA              (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC6_CC16_NUM                2        // Number of 16-bit Counters
+#define TC6_CC32_NUM                2        // Number of 32-bit Counters
+#define TC6_DITHERING_EXT           0        // Dithering feature implemented
+#define TC6_DMAC_ID_MC_0            34
+#define TC6_DMAC_ID_MC_1            35
+#define TC6_DMAC_ID_MC_LSB          34
+#define TC6_DMAC_ID_MC_MSB          35
+#define TC6_DMAC_ID_MC_SIZE         2
+#define TC6_DMAC_ID_OVF             33       // Indexes of DMA Overflow trigger
+#define TC6_GCLK_ID                 29       // Index of Generic Clock
+#define TC6_MASTER                  1       
+#define TC6_OW_NUM                  2        // Number of Output Waveforms
+#define TC6_PERIOD_EXT              0        // Period feature implemented
+#define TC6_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC6_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h
index 458949c..2b0056b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h
@@ -1,101 +1,101 @@
-/**
- * \file
- *
- * \brief Instance description for TC7
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TC7_INSTANCE_
-#define _SAMD21_TC7_INSTANCE_
-
-/* ========== Register definition for TC7 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC7_CTRLA              (0x42003C00U) /**< \brief (TC7) Control A */
-#define REG_TC7_READREQ            (0x42003C02U) /**< \brief (TC7) Read Request */
-#define REG_TC7_CTRLBCLR           (0x42003C04U) /**< \brief (TC7) Control B Clear */
-#define REG_TC7_CTRLBSET           (0x42003C05U) /**< \brief (TC7) Control B Set */
-#define REG_TC7_CTRLC              (0x42003C06U) /**< \brief (TC7) Control C */
-#define REG_TC7_DBGCTRL            (0x42003C08U) /**< \brief (TC7) Debug Control */
-#define REG_TC7_EVCTRL             (0x42003C0AU) /**< \brief (TC7) Event Control */
-#define REG_TC7_INTENCLR           (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
-#define REG_TC7_INTENSET           (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
-#define REG_TC7_INTFLAG            (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
-#define REG_TC7_STATUS             (0x42003C0FU) /**< \brief (TC7) Status */
-#define REG_TC7_COUNT16_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
-#define REG_TC7_COUNT16_CC0        (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
-#define REG_TC7_COUNT16_CC1        (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
-#define REG_TC7_COUNT32_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
-#define REG_TC7_COUNT32_CC0        (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
-#define REG_TC7_COUNT32_CC1        (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
-#define REG_TC7_COUNT8_COUNT       (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
-#define REG_TC7_COUNT8_PER         (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
-#define REG_TC7_COUNT8_CC0         (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
-#define REG_TC7_COUNT8_CC1         (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC7_CTRLA              (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
-#define REG_TC7_READREQ            (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
-#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
-#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
-#define REG_TC7_CTRLC              (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
-#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
-#define REG_TC7_EVCTRL             (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
-#define REG_TC7_INTENCLR           (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
-#define REG_TC7_INTENSET           (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
-#define REG_TC7_INTFLAG            (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
-#define REG_TC7_STATUS             (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
-#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
-#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
-#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
-#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
-#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
-#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
-#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
-#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
-#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
-#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC7 peripheral ========== */
-#define TC7_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC7_CC16_NUM                2        // Number of 16-bit Counters
-#define TC7_CC32_NUM                2        // Number of 32-bit Counters
-#define TC7_DITHERING_EXT           0        // Dithering feature implemented
-#define TC7_DMAC_ID_MC_0            37
-#define TC7_DMAC_ID_MC_1            38
-#define TC7_DMAC_ID_MC_LSB          37
-#define TC7_DMAC_ID_MC_MSB          38
-#define TC7_DMAC_ID_MC_SIZE         2
-#define TC7_DMAC_ID_OVF             36       // Indexes of DMA Overflow trigger
-#define TC7_GCLK_ID                 29       // Index of Generic Clock
-#define TC7_MASTER                  0       
-#define TC7_OW_NUM                  2        // Number of Output Waveforms
-#define TC7_PERIOD_EXT              0        // Period feature implemented
-#define TC7_SHADOW_EXT              0        // Shadow feature implemented
-
-#endif /* _SAMD21_TC7_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC7_INSTANCE_
+#define _SAMD21_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA              (0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC7_CTRLA              (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC7_CC16_NUM                2        // Number of 16-bit Counters
+#define TC7_CC32_NUM                2        // Number of 32-bit Counters
+#define TC7_DITHERING_EXT           0        // Dithering feature implemented
+#define TC7_DMAC_ID_MC_0            37
+#define TC7_DMAC_ID_MC_1            38
+#define TC7_DMAC_ID_MC_LSB          37
+#define TC7_DMAC_ID_MC_MSB          38
+#define TC7_DMAC_ID_MC_SIZE         2
+#define TC7_DMAC_ID_OVF             36       // Indexes of DMA Overflow trigger
+#define TC7_GCLK_ID                 29       // Index of Generic Clock
+#define TC7_MASTER                  0       
+#define TC7_OW_NUM                  2        // Number of Output Waveforms
+#define TC7_PERIOD_EXT              0        // Period feature implemented
+#define TC7_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC7_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h
index e9b339a..75dc641 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h
@@ -1,122 +1,122 @@
-/**
- * \file
- *
- * \brief Instance description for TCC0
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC0_INSTANCE_
-#define _SAMD21_TCC0_INSTANCE_
-
-/* ========== Register definition for TCC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC0_CTRLA             (0x42002000U) /**< \brief (TCC0) Control A */
-#define REG_TCC0_CTRLBCLR          (0x42002004U) /**< \brief (TCC0) Control B Clear */
-#define REG_TCC0_CTRLBSET          (0x42002005U) /**< \brief (TCC0) Control B Set */
-#define REG_TCC0_SYNCBUSY          (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
-#define REG_TCC0_FCTRLA            (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
-#define REG_TCC0_FCTRLB            (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
-#define REG_TCC0_WEXCTRL           (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
-#define REG_TCC0_DRVCTRL           (0x42002018U) /**< \brief (TCC0) Driver Control */
-#define REG_TCC0_DBGCTRL           (0x4200201EU) /**< \brief (TCC0) Debug Control */
-#define REG_TCC0_EVCTRL            (0x42002020U) /**< \brief (TCC0) Event Control */
-#define REG_TCC0_INTENCLR          (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
-#define REG_TCC0_INTENSET          (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
-#define REG_TCC0_INTFLAG           (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
-#define REG_TCC0_STATUS            (0x42002030U) /**< \brief (TCC0) Status */
-#define REG_TCC0_COUNT             (0x42002034U) /**< \brief (TCC0) Count */
-#define REG_TCC0_PATT              (0x42002038U) /**< \brief (TCC0) Pattern */
-#define REG_TCC0_WAVE              (0x4200203CU) /**< \brief (TCC0) Waveform Control */
-#define REG_TCC0_PER               (0x42002040U) /**< \brief (TCC0) Period */
-#define REG_TCC0_CC0               (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
-#define REG_TCC0_CC1               (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
-#define REG_TCC0_CC2               (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
-#define REG_TCC0_CC3               (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
-#define REG_TCC0_PATTB             (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
-#define REG_TCC0_WAVEB             (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
-#define REG_TCC0_PERB              (0x4200206CU) /**< \brief (TCC0) Period Buffer */
-#define REG_TCC0_CCB0              (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
-#define REG_TCC0_CCB1              (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
-#define REG_TCC0_CCB2              (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
-#define REG_TCC0_CCB3              (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
-#else
-#define REG_TCC0_CTRLA             (*(RwReg  *)0x42002000U) /**< \brief (TCC0) Control A */
-#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
-#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
-#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
-#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
-#define REG_TCC0_FCTRLB            (*(RwReg  *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
-#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
-#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x42002018U) /**< \brief (TCC0) Driver Control */
-#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
-#define REG_TCC0_EVCTRL            (*(RwReg  *)0x42002020U) /**< \brief (TCC0) Event Control */
-#define REG_TCC0_INTENCLR          (*(RwReg  *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
-#define REG_TCC0_INTENSET          (*(RwReg  *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
-#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
-#define REG_TCC0_STATUS            (*(RwReg  *)0x42002030U) /**< \brief (TCC0) Status */
-#define REG_TCC0_COUNT             (*(RwReg  *)0x42002034U) /**< \brief (TCC0) Count */
-#define REG_TCC0_PATT              (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
-#define REG_TCC0_WAVE              (*(RwReg  *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
-#define REG_TCC0_PER               (*(RwReg  *)0x42002040U) /**< \brief (TCC0) Period */
-#define REG_TCC0_CC0               (*(RwReg  *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
-#define REG_TCC0_CC1               (*(RwReg  *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
-#define REG_TCC0_CC2               (*(RwReg  *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
-#define REG_TCC0_CC3               (*(RwReg  *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
-#define REG_TCC0_PATTB             (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
-#define REG_TCC0_WAVEB             (*(RwReg  *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
-#define REG_TCC0_PERB              (*(RwReg  *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
-#define REG_TCC0_CCB0              (*(RwReg  *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
-#define REG_TCC0_CCB1              (*(RwReg  *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
-#define REG_TCC0_CCB2              (*(RwReg  *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
-#define REG_TCC0_CCB3              (*(RwReg  *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC0 peripheral ========== */
-#define TCC0_CC_NUM                 4        // Number of Compare/Capture units
-#define TCC0_DITHERING              1        // Dithering feature implemented
-#define TCC0_DMAC_ID_MC_0           14
-#define TCC0_DMAC_ID_MC_1           15
-#define TCC0_DMAC_ID_MC_2           16
-#define TCC0_DMAC_ID_MC_3           17
-#define TCC0_DMAC_ID_MC_LSB         14
-#define TCC0_DMAC_ID_MC_MSB         17
-#define TCC0_DMAC_ID_MC_SIZE        4
-#define TCC0_DMAC_ID_OVF            13       // DMA overflow/underflow/retrigger trigger
-#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
-#define TCC0_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
-#define TCC0_GCLK_ID                26       // Index of Generic Clock
-#define TCC0_MASTER                 0       
-#define TCC0_OTMX                   1        // Output Matrix feature implemented
-#define TCC0_OW_NUM                 8        // Number of Output Waveforms
-#define TCC0_PG                     1        // Pattern Generation feature implemented
-#define TCC0_SIZE                   24      
-#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
-#define TCC0_TYPE                   1        // TCC type 0 : NA, 1 : Master, 2 : Slave
-
-#endif /* _SAMD21_TCC0_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC0_INSTANCE_
+#define _SAMD21_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA             (0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (0x42002018U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB             (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB             (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB              (0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0              (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1              (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2              (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3              (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC0_CTRLA             (*(RwReg  *)0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (*(RwReg  *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x42002018U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (*(RwReg  *)0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (*(RwReg  *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (*(RwReg  *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (*(RwReg  *)0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (*(RwReg  *)0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (*(RwReg  *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (*(RwReg  *)0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (*(RwReg  *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (*(RwReg  *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (*(RwReg  *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (*(RwReg  *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB             (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB             (*(RwReg  *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB              (*(RwReg  *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0              (*(RwReg  *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1              (*(RwReg  *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2              (*(RwReg  *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3              (*(RwReg  *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM                 4        // Number of Compare/Capture units
+#define TCC0_DITHERING              1        // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0           14
+#define TCC0_DMAC_ID_MC_1           15
+#define TCC0_DMAC_ID_MC_2           16
+#define TCC0_DMAC_ID_MC_3           17
+#define TCC0_DMAC_ID_MC_LSB         14
+#define TCC0_DMAC_ID_MC_MSB         17
+#define TCC0_DMAC_ID_MC_SIZE        4
+#define TCC0_DMAC_ID_OVF            13       // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
+#define TCC0_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
+#define TCC0_GCLK_ID                26       // Index of Generic Clock
+#define TCC0_MASTER                 0       
+#define TCC0_OTMX                   1        // Output Matrix feature implemented
+#define TCC0_OW_NUM                 8        // Number of Output Waveforms
+#define TCC0_PG                     1        // Pattern Generation feature implemented
+#define TCC0_SIZE                   24      
+#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
+#define TCC0_TYPE                   1        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC0_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h
index b483666..42a72e3 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h
@@ -1,110 +1,110 @@
-/**
- * \file
- *
- * \brief Instance description for TCC1
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC1_INSTANCE_
-#define _SAMD21_TCC1_INSTANCE_
-
-/* ========== Register definition for TCC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC1_CTRLA             (0x42002400U) /**< \brief (TCC1) Control A */
-#define REG_TCC1_CTRLBCLR          (0x42002404U) /**< \brief (TCC1) Control B Clear */
-#define REG_TCC1_CTRLBSET          (0x42002405U) /**< \brief (TCC1) Control B Set */
-#define REG_TCC1_SYNCBUSY          (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
-#define REG_TCC1_FCTRLA            (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
-#define REG_TCC1_FCTRLB            (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
-#define REG_TCC1_DRVCTRL           (0x42002418U) /**< \brief (TCC1) Driver Control */
-#define REG_TCC1_DBGCTRL           (0x4200241EU) /**< \brief (TCC1) Debug Control */
-#define REG_TCC1_EVCTRL            (0x42002420U) /**< \brief (TCC1) Event Control */
-#define REG_TCC1_INTENCLR          (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
-#define REG_TCC1_INTENSET          (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
-#define REG_TCC1_INTFLAG           (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
-#define REG_TCC1_STATUS            (0x42002430U) /**< \brief (TCC1) Status */
-#define REG_TCC1_COUNT             (0x42002434U) /**< \brief (TCC1) Count */
-#define REG_TCC1_PATT              (0x42002438U) /**< \brief (TCC1) Pattern */
-#define REG_TCC1_WAVE              (0x4200243CU) /**< \brief (TCC1) Waveform Control */
-#define REG_TCC1_PER               (0x42002440U) /**< \brief (TCC1) Period */
-#define REG_TCC1_CC0               (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
-#define REG_TCC1_CC1               (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
-#define REG_TCC1_PATTB             (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
-#define REG_TCC1_WAVEB             (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
-#define REG_TCC1_PERB              (0x4200246CU) /**< \brief (TCC1) Period Buffer */
-#define REG_TCC1_CCB0              (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
-#define REG_TCC1_CCB1              (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
-#else
-#define REG_TCC1_CTRLA             (*(RwReg  *)0x42002400U) /**< \brief (TCC1) Control A */
-#define REG_TCC1_CTRLBCLR          (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
-#define REG_TCC1_CTRLBSET          (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
-#define REG_TCC1_SYNCBUSY          (*(RoReg  *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
-#define REG_TCC1_FCTRLA            (*(RwReg  *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
-#define REG_TCC1_FCTRLB            (*(RwReg  *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
-#define REG_TCC1_DRVCTRL           (*(RwReg  *)0x42002418U) /**< \brief (TCC1) Driver Control */
-#define REG_TCC1_DBGCTRL           (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
-#define REG_TCC1_EVCTRL            (*(RwReg  *)0x42002420U) /**< \brief (TCC1) Event Control */
-#define REG_TCC1_INTENCLR          (*(RwReg  *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
-#define REG_TCC1_INTENSET          (*(RwReg  *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
-#define REG_TCC1_INTFLAG           (*(RwReg  *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
-#define REG_TCC1_STATUS            (*(RwReg  *)0x42002430U) /**< \brief (TCC1) Status */
-#define REG_TCC1_COUNT             (*(RwReg  *)0x42002434U) /**< \brief (TCC1) Count */
-#define REG_TCC1_PATT              (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
-#define REG_TCC1_WAVE              (*(RwReg  *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
-#define REG_TCC1_PER               (*(RwReg  *)0x42002440U) /**< \brief (TCC1) Period */
-#define REG_TCC1_CC0               (*(RwReg  *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
-#define REG_TCC1_CC1               (*(RwReg  *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
-#define REG_TCC1_PATTB             (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
-#define REG_TCC1_WAVEB             (*(RwReg  *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
-#define REG_TCC1_PERB              (*(RwReg  *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
-#define REG_TCC1_CCB0              (*(RwReg  *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
-#define REG_TCC1_CCB1              (*(RwReg  *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC1 peripheral ========== */
-#define TCC1_CC_NUM                 2        // Number of Compare/Capture units
-#define TCC1_DITHERING              1        // Dithering feature implemented
-#define TCC1_DMAC_ID_MC_0           19
-#define TCC1_DMAC_ID_MC_1           20
-#define TCC1_DMAC_ID_MC_LSB         19
-#define TCC1_DMAC_ID_MC_MSB         20
-#define TCC1_DMAC_ID_MC_SIZE        2
-#define TCC1_DMAC_ID_OVF            18       // DMA overflow/underflow/retrigger trigger
-#define TCC1_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC1_EXT                    24       // Coding of implemented extended features
-#define TCC1_GCLK_ID                26       // Index of Generic Clock
-#define TCC1_MASTER                 1       
-#define TCC1_OTMX                   0        // Output Matrix feature implemented
-#define TCC1_OW_NUM                 4        // Number of Output Waveforms
-#define TCC1_PG                     1        // Pattern Generation feature implemented
-#define TCC1_SIZE                   24      
-#define TCC1_SWAP                   0        // DTI outputs swap feature implemented
-#define TCC1_TYPE                   2        // TCC type 0 : NA, 1 : Master, 2 : Slave
-
-#endif /* _SAMD21_TCC1_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC1_INSTANCE_
+#define _SAMD21_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA             (0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL           (0x42002418U) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB             (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB             (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB              (0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0              (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1              (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC1_CTRLA             (*(RwReg  *)0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (*(RoReg  *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (*(RwReg  *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (*(RwReg  *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL           (*(RwReg  *)0x42002418U) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (*(RwReg  *)0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (*(RwReg  *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (*(RwReg  *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (*(RwReg  *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (*(RwReg  *)0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (*(RwReg  *)0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (*(RwReg  *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (*(RwReg  *)0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (*(RwReg  *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (*(RwReg  *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB             (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB             (*(RwReg  *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB              (*(RwReg  *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0              (*(RwReg  *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1              (*(RwReg  *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC1_DITHERING              1        // Dithering feature implemented
+#define TCC1_DMAC_ID_MC_0           19
+#define TCC1_DMAC_ID_MC_1           20
+#define TCC1_DMAC_ID_MC_LSB         19
+#define TCC1_DMAC_ID_MC_MSB         20
+#define TCC1_DMAC_ID_MC_SIZE        2
+#define TCC1_DMAC_ID_OVF            18       // DMA overflow/underflow/retrigger trigger
+#define TCC1_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC1_EXT                    24       // Coding of implemented extended features
+#define TCC1_GCLK_ID                26       // Index of Generic Clock
+#define TCC1_MASTER                 1       
+#define TCC1_OTMX                   0        // Output Matrix feature implemented
+#define TCC1_OW_NUM                 4        // Number of Output Waveforms
+#define TCC1_PG                     1        // Pattern Generation feature implemented
+#define TCC1_SIZE                   24      
+#define TCC1_SWAP                   0        // DTI outputs swap feature implemented
+#define TCC1_TYPE                   2        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC1_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h
index f5e484c..43b7049 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h
@@ -1,106 +1,106 @@
-/**
- * \file
- *
- * \brief Instance description for TCC2
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC2_INSTANCE_
-#define _SAMD21_TCC2_INSTANCE_
-
-/* ========== Register definition for TCC2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC2_CTRLA             (0x42002800U) /**< \brief (TCC2) Control A */
-#define REG_TCC2_CTRLBCLR          (0x42002804U) /**< \brief (TCC2) Control B Clear */
-#define REG_TCC2_CTRLBSET          (0x42002805U) /**< \brief (TCC2) Control B Set */
-#define REG_TCC2_SYNCBUSY          (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
-#define REG_TCC2_FCTRLA            (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
-#define REG_TCC2_FCTRLB            (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
-#define REG_TCC2_DRVCTRL           (0x42002818U) /**< \brief (TCC2) Driver Control */
-#define REG_TCC2_DBGCTRL           (0x4200281EU) /**< \brief (TCC2) Debug Control */
-#define REG_TCC2_EVCTRL            (0x42002820U) /**< \brief (TCC2) Event Control */
-#define REG_TCC2_INTENCLR          (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
-#define REG_TCC2_INTENSET          (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
-#define REG_TCC2_INTFLAG           (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
-#define REG_TCC2_STATUS            (0x42002830U) /**< \brief (TCC2) Status */
-#define REG_TCC2_COUNT             (0x42002834U) /**< \brief (TCC2) Count */
-#define REG_TCC2_WAVE              (0x4200283CU) /**< \brief (TCC2) Waveform Control */
-#define REG_TCC2_PER               (0x42002840U) /**< \brief (TCC2) Period */
-#define REG_TCC2_CC0               (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
-#define REG_TCC2_CC1               (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
-#define REG_TCC2_WAVEB             (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
-#define REG_TCC2_PERB              (0x4200286CU) /**< \brief (TCC2) Period Buffer */
-#define REG_TCC2_CCB0              (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
-#define REG_TCC2_CCB1              (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
-#else
-#define REG_TCC2_CTRLA             (*(RwReg  *)0x42002800U) /**< \brief (TCC2) Control A */
-#define REG_TCC2_CTRLBCLR          (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
-#define REG_TCC2_CTRLBSET          (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
-#define REG_TCC2_SYNCBUSY          (*(RoReg  *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
-#define REG_TCC2_FCTRLA            (*(RwReg  *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
-#define REG_TCC2_FCTRLB            (*(RwReg  *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
-#define REG_TCC2_DRVCTRL           (*(RwReg  *)0x42002818U) /**< \brief (TCC2) Driver Control */
-#define REG_TCC2_DBGCTRL           (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
-#define REG_TCC2_EVCTRL            (*(RwReg  *)0x42002820U) /**< \brief (TCC2) Event Control */
-#define REG_TCC2_INTENCLR          (*(RwReg  *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
-#define REG_TCC2_INTENSET          (*(RwReg  *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
-#define REG_TCC2_INTFLAG           (*(RwReg  *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
-#define REG_TCC2_STATUS            (*(RwReg  *)0x42002830U) /**< \brief (TCC2) Status */
-#define REG_TCC2_COUNT             (*(RwReg  *)0x42002834U) /**< \brief (TCC2) Count */
-#define REG_TCC2_WAVE              (*(RwReg  *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
-#define REG_TCC2_PER               (*(RwReg  *)0x42002840U) /**< \brief (TCC2) Period */
-#define REG_TCC2_CC0               (*(RwReg  *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
-#define REG_TCC2_CC1               (*(RwReg  *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
-#define REG_TCC2_WAVEB             (*(RwReg  *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
-#define REG_TCC2_PERB              (*(RwReg  *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
-#define REG_TCC2_CCB0              (*(RwReg  *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
-#define REG_TCC2_CCB1              (*(RwReg  *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC2 peripheral ========== */
-#define TCC2_CC_NUM                 2        // Number of Compare/Capture units
-#define TCC2_DITHERING              0        // Dithering feature implemented
-#define TCC2_DMAC_ID_MC_0           22
-#define TCC2_DMAC_ID_MC_1           23
-#define TCC2_DMAC_ID_MC_LSB         22
-#define TCC2_DMAC_ID_MC_MSB         23
-#define TCC2_DMAC_ID_MC_SIZE        2
-#define TCC2_DMAC_ID_OVF            21       // DMA overflow/underflow/retrigger trigger
-#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC2_EXT                    0        // Coding of implemented extended features
-#define TCC2_GCLK_ID                27       // Index of Generic Clock
-#define TCC2_MASTER                 0       
-#define TCC2_OTMX                   0        // Output Matrix feature implemented
-#define TCC2_OW_NUM                 2        // Number of Output Waveforms
-#define TCC2_PG                     0        // Pattern Generation feature implemented
-#define TCC2_SIZE                   16      
-#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
-#define TCC2_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
-
-#endif /* _SAMD21_TCC2_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC2_INSTANCE_
+#define _SAMD21_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA             (0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL           (0x42002818U) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB             (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB              (0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0              (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1              (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC2_CTRLA             (*(RwReg  *)0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (*(RoReg  *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (*(RwReg  *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (*(RwReg  *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL           (*(RwReg  *)0x42002818U) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (*(RwReg  *)0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (*(RwReg  *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (*(RwReg  *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (*(RwReg  *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (*(RwReg  *)0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (*(RwReg  *)0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (*(RwReg  *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (*(RwReg  *)0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (*(RwReg  *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (*(RwReg  *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB             (*(RwReg  *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB              (*(RwReg  *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0              (*(RwReg  *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1              (*(RwReg  *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC2_DITHERING              0        // Dithering feature implemented
+#define TCC2_DMAC_ID_MC_0           22
+#define TCC2_DMAC_ID_MC_1           23
+#define TCC2_DMAC_ID_MC_LSB         22
+#define TCC2_DMAC_ID_MC_MSB         23
+#define TCC2_DMAC_ID_MC_SIZE        2
+#define TCC2_DMAC_ID_OVF            21       // DMA overflow/underflow/retrigger trigger
+#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC2_EXT                    0        // Coding of implemented extended features
+#define TCC2_GCLK_ID                27       // Index of Generic Clock
+#define TCC2_MASTER                 0       
+#define TCC2_OTMX                   0        // Output Matrix feature implemented
+#define TCC2_OW_NUM                 2        // Number of Output Waveforms
+#define TCC2_PG                     0        // Pattern Generation feature implemented
+#define TCC2_SIZE                   16      
+#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
+#define TCC2_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC2_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc3.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc3.h
index 7ea1d54..808dd78 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc3.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc3.h
@@ -1,122 +1,122 @@
-/**
- * \file
- *
- * \brief Instance description for TCC3
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_TCC3_INSTANCE_
-#define _SAMD21_TCC3_INSTANCE_
-
-/* ========== Register definition for TCC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC3_CTRLA             (0x42006000) /**< \brief (TCC3) Control A */
-#define REG_TCC3_CTRLBCLR          (0x42006004) /**< \brief (TCC3) Control B Clear */
-#define REG_TCC3_CTRLBSET          (0x42006005) /**< \brief (TCC3) Control B Set */
-#define REG_TCC3_SYNCBUSY          (0x42006008) /**< \brief (TCC3) Synchronization Busy */
-#define REG_TCC3_FCTRLA            (0x4200600C) /**< \brief (TCC3) Recoverable Fault A Configuration */
-#define REG_TCC3_FCTRLB            (0x42006010) /**< \brief (TCC3) Recoverable Fault B Configuration */
-#define REG_TCC3_WEXCTRL           (0x42006014) /**< \brief (TCC3) Waveform Extension Configuration */
-#define REG_TCC3_DRVCTRL           (0x42006018) /**< \brief (TCC3) Driver Control */
-#define REG_TCC3_DBGCTRL           (0x4200601E) /**< \brief (TCC3) Debug Control */
-#define REG_TCC3_EVCTRL            (0x42006020) /**< \brief (TCC3) Event Control */
-#define REG_TCC3_INTENCLR          (0x42006024) /**< \brief (TCC3) Interrupt Enable Clear */
-#define REG_TCC3_INTENSET          (0x42006028) /**< \brief (TCC3) Interrupt Enable Set */
-#define REG_TCC3_INTFLAG           (0x4200602C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
-#define REG_TCC3_STATUS            (0x42006030) /**< \brief (TCC3) Status */
-#define REG_TCC3_COUNT             (0x42006034) /**< \brief (TCC3) Count */
-#define REG_TCC3_PATT              (0x42006038) /**< \brief (TCC3) Pattern */
-#define REG_TCC3_WAVE              (0x4200603C) /**< \brief (TCC3) Waveform Control */
-#define REG_TCC3_PER               (0x42006040) /**< \brief (TCC3) Period */
-#define REG_TCC3_CC0               (0x42006044) /**< \brief (TCC3) Compare and Capture 0 */
-#define REG_TCC3_CC1               (0x42006048) /**< \brief (TCC3) Compare and Capture 1 */
-#define REG_TCC3_CC2               (0x4200604C) /**< \brief (TCC3) Compare and Capture 2 */
-#define REG_TCC3_CC3               (0x42006050) /**< \brief (TCC3) Compare and Capture 3 */
-#define REG_TCC3_PATTB             (0x42006064) /**< \brief (TCC3) Pattern Buffer */
-#define REG_TCC3_WAVEB             (0x42006068) /**< \brief (TCC3) Waveform Control Buffer */
-#define REG_TCC3_PERB              (0x4200606C) /**< \brief (TCC3) Period Buffer */
-#define REG_TCC3_CCB0              (0x42006070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
-#define REG_TCC3_CCB1              (0x42006074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
-#define REG_TCC3_CCB2              (0x42006078) /**< \brief (TCC3) Compare and Capture Buffer 2 */
-#define REG_TCC3_CCB3              (0x4200607C) /**< \brief (TCC3) Compare and Capture Buffer 3 */
-#else
-#define REG_TCC3_CTRLA             (*(RwReg  *)0x42006000UL) /**< \brief (TCC3) Control A */
-#define REG_TCC3_CTRLBCLR          (*(RwReg8 *)0x42006004UL) /**< \brief (TCC3) Control B Clear */
-#define REG_TCC3_CTRLBSET          (*(RwReg8 *)0x42006005UL) /**< \brief (TCC3) Control B Set */
-#define REG_TCC3_SYNCBUSY          (*(RoReg  *)0x42006008UL) /**< \brief (TCC3) Synchronization Busy */
-#define REG_TCC3_FCTRLA            (*(RwReg  *)0x4200600CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
-#define REG_TCC3_FCTRLB            (*(RwReg  *)0x42006010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
-#define REG_TCC3_WEXCTRL           (*(RwReg  *)0x42006014UL) /**< \brief (TCC3) Waveform Extension Configuration */
-#define REG_TCC3_DRVCTRL           (*(RwReg  *)0x42006018UL) /**< \brief (TCC3) Driver Control */
-#define REG_TCC3_DBGCTRL           (*(RwReg8 *)0x4200601EUL) /**< \brief (TCC3) Debug Control */
-#define REG_TCC3_EVCTRL            (*(RwReg  *)0x42006020UL) /**< \brief (TCC3) Event Control */
-#define REG_TCC3_INTENCLR          (*(RwReg  *)0x42006024UL) /**< \brief (TCC3) Interrupt Enable Clear */
-#define REG_TCC3_INTENSET          (*(RwReg  *)0x42006028UL) /**< \brief (TCC3) Interrupt Enable Set */
-#define REG_TCC3_INTFLAG           (*(RwReg  *)0x4200602CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
-#define REG_TCC3_STATUS            (*(RwReg  *)0x42006030UL) /**< \brief (TCC3) Status */
-#define REG_TCC3_COUNT             (*(RwReg  *)0x42006034UL) /**< \brief (TCC3) Count */
-#define REG_TCC3_PATT              (*(RwReg16*)0x42006038UL) /**< \brief (TCC3) Pattern */
-#define REG_TCC3_WAVE              (*(RwReg  *)0x4200603CUL) /**< \brief (TCC3) Waveform Control */
-#define REG_TCC3_PER               (*(RwReg  *)0x42006040UL) /**< \brief (TCC3) Period */
-#define REG_TCC3_CC0               (*(RwReg  *)0x42006044UL) /**< \brief (TCC3) Compare and Capture 0 */
-#define REG_TCC3_CC1               (*(RwReg  *)0x42006048UL) /**< \brief (TCC3) Compare and Capture 1 */
-#define REG_TCC3_CC2               (*(RwReg  *)0x4200604CUL) /**< \brief (TCC3) Compare and Capture 2 */
-#define REG_TCC3_CC3               (*(RwReg  *)0x42006050UL) /**< \brief (TCC3) Compare and Capture 3 */
-#define REG_TCC3_PATTB             (*(RwReg16*)0x42006064UL) /**< \brief (TCC3) Pattern Buffer */
-#define REG_TCC3_WAVEB             (*(RwReg  *)0x42006068UL) /**< \brief (TCC3) Waveform Control Buffer */
-#define REG_TCC3_PERB              (*(RwReg  *)0x4200606CUL) /**< \brief (TCC3) Period Buffer */
-#define REG_TCC3_CCB0              (*(RwReg  *)0x42006070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
-#define REG_TCC3_CCB1              (*(RwReg  *)0x42006074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
-#define REG_TCC3_CCB2              (*(RwReg  *)0x42006078UL) /**< \brief (TCC3) Compare and Capture Buffer 2 */
-#define REG_TCC3_CCB3              (*(RwReg  *)0x4200607CUL) /**< \brief (TCC3) Compare and Capture Buffer 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC3 peripheral ========== */
-#define TCC3_CC_NUM                 4        // Number of Compare/Capture units
-#define TCC3_DITHERING              1        // Dithering feature implemented
-#define TCC3_DMAC_ID_MC_0           46
-#define TCC3_DMAC_ID_MC_1           47
-#define TCC3_DMAC_ID_MC_2           48
-#define TCC3_DMAC_ID_MC_3           49
-#define TCC3_DMAC_ID_MC_LSB         46
-#define TCC3_DMAC_ID_MC_MSB         49
-#define TCC3_DMAC_ID_MC_SIZE        4
-#define TCC3_DMAC_ID_OVF            45       // DMA overflow/underflow/retrigger trigger
-#define TCC3_DTI                    1        // Dead-Time-Insertion feature implemented
-#define TCC3_EXT                    31       // Coding of implemented extended features
-#define TCC3_GCLK_ID                37       // Index of Generic Clock
-#define TCC3_MASTER                 0       
-#define TCC3_OTMX                   1        // Output Matrix feature implemented
-#define TCC3_OW_NUM                 8        // Number of Output Waveforms
-#define TCC3_PG                     1        // Pattern Generation feature implemented
-#define TCC3_SIZE                   24      
-#define TCC3_SWAP                   1        // DTI outputs swap feature implemented
-#define TCC3_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
-
-#endif /* _SAMD21_TCC3_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for TCC3
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC3_INSTANCE_
+#define _SAMD21_TCC3_INSTANCE_
+
+/* ========== Register definition for TCC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC3_CTRLA             (0x42006000) /**< \brief (TCC3) Control A */
+#define REG_TCC3_CTRLBCLR          (0x42006004) /**< \brief (TCC3) Control B Clear */
+#define REG_TCC3_CTRLBSET          (0x42006005) /**< \brief (TCC3) Control B Set */
+#define REG_TCC3_SYNCBUSY          (0x42006008) /**< \brief (TCC3) Synchronization Busy */
+#define REG_TCC3_FCTRLA            (0x4200600C) /**< \brief (TCC3) Recoverable Fault A Configuration */
+#define REG_TCC3_FCTRLB            (0x42006010) /**< \brief (TCC3) Recoverable Fault B Configuration */
+#define REG_TCC3_WEXCTRL           (0x42006014) /**< \brief (TCC3) Waveform Extension Configuration */
+#define REG_TCC3_DRVCTRL           (0x42006018) /**< \brief (TCC3) Driver Control */
+#define REG_TCC3_DBGCTRL           (0x4200601E) /**< \brief (TCC3) Debug Control */
+#define REG_TCC3_EVCTRL            (0x42006020) /**< \brief (TCC3) Event Control */
+#define REG_TCC3_INTENCLR          (0x42006024) /**< \brief (TCC3) Interrupt Enable Clear */
+#define REG_TCC3_INTENSET          (0x42006028) /**< \brief (TCC3) Interrupt Enable Set */
+#define REG_TCC3_INTFLAG           (0x4200602C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
+#define REG_TCC3_STATUS            (0x42006030) /**< \brief (TCC3) Status */
+#define REG_TCC3_COUNT             (0x42006034) /**< \brief (TCC3) Count */
+#define REG_TCC3_PATT              (0x42006038) /**< \brief (TCC3) Pattern */
+#define REG_TCC3_WAVE              (0x4200603C) /**< \brief (TCC3) Waveform Control */
+#define REG_TCC3_PER               (0x42006040) /**< \brief (TCC3) Period */
+#define REG_TCC3_CC0               (0x42006044) /**< \brief (TCC3) Compare and Capture 0 */
+#define REG_TCC3_CC1               (0x42006048) /**< \brief (TCC3) Compare and Capture 1 */
+#define REG_TCC3_CC2               (0x4200604C) /**< \brief (TCC3) Compare and Capture 2 */
+#define REG_TCC3_CC3               (0x42006050) /**< \brief (TCC3) Compare and Capture 3 */
+#define REG_TCC3_PATTB             (0x42006064) /**< \brief (TCC3) Pattern Buffer */
+#define REG_TCC3_WAVEB             (0x42006068) /**< \brief (TCC3) Waveform Control Buffer */
+#define REG_TCC3_PERB              (0x4200606C) /**< \brief (TCC3) Period Buffer */
+#define REG_TCC3_CCB0              (0x42006070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
+#define REG_TCC3_CCB1              (0x42006074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
+#define REG_TCC3_CCB2              (0x42006078) /**< \brief (TCC3) Compare and Capture Buffer 2 */
+#define REG_TCC3_CCB3              (0x4200607C) /**< \brief (TCC3) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC3_CTRLA             (*(RwReg  *)0x42006000UL) /**< \brief (TCC3) Control A */
+#define REG_TCC3_CTRLBCLR          (*(RwReg8 *)0x42006004UL) /**< \brief (TCC3) Control B Clear */
+#define REG_TCC3_CTRLBSET          (*(RwReg8 *)0x42006005UL) /**< \brief (TCC3) Control B Set */
+#define REG_TCC3_SYNCBUSY          (*(RoReg  *)0x42006008UL) /**< \brief (TCC3) Synchronization Busy */
+#define REG_TCC3_FCTRLA            (*(RwReg  *)0x4200600CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
+#define REG_TCC3_FCTRLB            (*(RwReg  *)0x42006010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
+#define REG_TCC3_WEXCTRL           (*(RwReg  *)0x42006014UL) /**< \brief (TCC3) Waveform Extension Configuration */
+#define REG_TCC3_DRVCTRL           (*(RwReg  *)0x42006018UL) /**< \brief (TCC3) Driver Control */
+#define REG_TCC3_DBGCTRL           (*(RwReg8 *)0x4200601EUL) /**< \brief (TCC3) Debug Control */
+#define REG_TCC3_EVCTRL            (*(RwReg  *)0x42006020UL) /**< \brief (TCC3) Event Control */
+#define REG_TCC3_INTENCLR          (*(RwReg  *)0x42006024UL) /**< \brief (TCC3) Interrupt Enable Clear */
+#define REG_TCC3_INTENSET          (*(RwReg  *)0x42006028UL) /**< \brief (TCC3) Interrupt Enable Set */
+#define REG_TCC3_INTFLAG           (*(RwReg  *)0x4200602CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
+#define REG_TCC3_STATUS            (*(RwReg  *)0x42006030UL) /**< \brief (TCC3) Status */
+#define REG_TCC3_COUNT             (*(RwReg  *)0x42006034UL) /**< \brief (TCC3) Count */
+#define REG_TCC3_PATT              (*(RwReg16*)0x42006038UL) /**< \brief (TCC3) Pattern */
+#define REG_TCC3_WAVE              (*(RwReg  *)0x4200603CUL) /**< \brief (TCC3) Waveform Control */
+#define REG_TCC3_PER               (*(RwReg  *)0x42006040UL) /**< \brief (TCC3) Period */
+#define REG_TCC3_CC0               (*(RwReg  *)0x42006044UL) /**< \brief (TCC3) Compare and Capture 0 */
+#define REG_TCC3_CC1               (*(RwReg  *)0x42006048UL) /**< \brief (TCC3) Compare and Capture 1 */
+#define REG_TCC3_CC2               (*(RwReg  *)0x4200604CUL) /**< \brief (TCC3) Compare and Capture 2 */
+#define REG_TCC3_CC3               (*(RwReg  *)0x42006050UL) /**< \brief (TCC3) Compare and Capture 3 */
+#define REG_TCC3_PATTB             (*(RwReg16*)0x42006064UL) /**< \brief (TCC3) Pattern Buffer */
+#define REG_TCC3_WAVEB             (*(RwReg  *)0x42006068UL) /**< \brief (TCC3) Waveform Control Buffer */
+#define REG_TCC3_PERB              (*(RwReg  *)0x4200606CUL) /**< \brief (TCC3) Period Buffer */
+#define REG_TCC3_CCB0              (*(RwReg  *)0x42006070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
+#define REG_TCC3_CCB1              (*(RwReg  *)0x42006074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
+#define REG_TCC3_CCB2              (*(RwReg  *)0x42006078UL) /**< \brief (TCC3) Compare and Capture Buffer 2 */
+#define REG_TCC3_CCB3              (*(RwReg  *)0x4200607CUL) /**< \brief (TCC3) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC3 peripheral ========== */
+#define TCC3_CC_NUM                 4        // Number of Compare/Capture units
+#define TCC3_DITHERING              1        // Dithering feature implemented
+#define TCC3_DMAC_ID_MC_0           46
+#define TCC3_DMAC_ID_MC_1           47
+#define TCC3_DMAC_ID_MC_2           48
+#define TCC3_DMAC_ID_MC_3           49
+#define TCC3_DMAC_ID_MC_LSB         46
+#define TCC3_DMAC_ID_MC_MSB         49
+#define TCC3_DMAC_ID_MC_SIZE        4
+#define TCC3_DMAC_ID_OVF            45       // DMA overflow/underflow/retrigger trigger
+#define TCC3_DTI                    1        // Dead-Time-Insertion feature implemented
+#define TCC3_EXT                    31       // Coding of implemented extended features
+#define TCC3_GCLK_ID                37       // Index of Generic Clock
+#define TCC3_MASTER                 0       
+#define TCC3_OTMX                   1        // Output Matrix feature implemented
+#define TCC3_OW_NUM                 8        // Number of Output Waveforms
+#define TCC3_PG                     1        // Pattern Generation feature implemented
+#define TCC3_SIZE                   24      
+#define TCC3_SWAP                   1        // DTI outputs swap feature implemented
+#define TCC3_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC3_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h
index 9912f5a..b86d3bb 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h
@@ -1,334 +1,334 @@
-/**
- * \file
- *
- * \brief Instance description for USB
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_USB_INSTANCE_
-#define _SAMD21_USB_INSTANCE_
-
-/* ========== Register definition for USB peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_USB_CTRLA              (0x41005000U) /**< \brief (USB) Control A */
-#define REG_USB_SYNCBUSY           (0x41005002U) /**< \brief (USB) Synchronization Busy */
-#define REG_USB_QOSCTRL            (0x41005003U) /**< \brief (USB) USB Quality Of Service */
-#define REG_USB_FSMSTATUS          (0x4100500DU) /**< \brief (USB) Finite State Machine Status */
-#define REG_USB_DESCADD            (0x41005024U) /**< \brief (USB) Descriptor Address */
-#define REG_USB_PADCAL             (0x41005028U) /**< \brief (USB) USB PAD Calibration */
-#define REG_USB_DEVICE_CTRLB       (0x41005008U) /**< \brief (USB) DEVICE Control B */
-#define REG_USB_DEVICE_DADD        (0x4100500AU) /**< \brief (USB) DEVICE Device Address */
-#define REG_USB_DEVICE_STATUS      (0x4100500CU) /**< \brief (USB) DEVICE Status */
-#define REG_USB_DEVICE_FNUM        (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
-#define REG_USB_DEVICE_INTENCLR    (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
-#define REG_USB_DEVICE_INTENSET    (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
-#define REG_USB_DEVICE_INTFLAG     (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
-#define REG_USB_DEVICE_EPINTSMRY   (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
-#define REG_USB_HOST_CTRLB         (0x41005008U) /**< \brief (USB) HOST Control B */
-#define REG_USB_HOST_HSOFC         (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
-#define REG_USB_HOST_STATUS        (0x4100500CU) /**< \brief (USB) HOST Status */
-#define REG_USB_HOST_FNUM          (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
-#define REG_USB_HOST_FLENHIGH      (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
-#define REG_USB_HOST_INTENCLR      (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
-#define REG_USB_HOST_INTENSET      (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
-#define REG_USB_HOST_INTFLAG       (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
-#define REG_USB_HOST_PINTSMRY      (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
-#define REG_USB_HOST_PIPE_PCFG0    (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
-#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
-#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
-#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
-#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
-#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
-#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
-#define REG_USB_HOST_PIPE_PCFG1    (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
-#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
-#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
-#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
-#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
-#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
-#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
-#define REG_USB_HOST_PIPE_PCFG2    (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
-#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
-#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
-#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
-#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
-#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
-#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
-#define REG_USB_HOST_PIPE_PCFG3    (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
-#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
-#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
-#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
-#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
-#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
-#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
-#define REG_USB_HOST_PIPE_PCFG4    (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
-#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
-#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
-#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
-#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
-#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
-#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
-#define REG_USB_HOST_PIPE_PCFG5    (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
-#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
-#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
-#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
-#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
-#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
-#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
-#define REG_USB_HOST_PIPE_PCFG6    (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
-#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
-#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
-#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
-#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
-#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
-#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
-#define REG_USB_HOST_PIPE_PCFG7    (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
-#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
-#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
-#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
-#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
-#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
-#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
-#else
-#define REG_USB_CTRLA              (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
-#define REG_USB_SYNCBUSY           (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
-#define REG_USB_QOSCTRL            (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */
-#define REG_USB_FSMSTATUS          (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */
-#define REG_USB_DESCADD            (*(RwReg  *)0x41005024U) /**< \brief (USB) Descriptor Address */
-#define REG_USB_PADCAL             (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */
-#define REG_USB_DEVICE_CTRLB       (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */
-#define REG_USB_DEVICE_DADD        (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */
-#define REG_USB_DEVICE_STATUS      (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */
-#define REG_USB_DEVICE_FNUM        (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
-#define REG_USB_DEVICE_INTENCLR    (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
-#define REG_USB_DEVICE_INTENSET    (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
-#define REG_USB_DEVICE_INTFLAG     (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
-#define REG_USB_DEVICE_EPINTSMRY   (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
-#define REG_USB_HOST_CTRLB         (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
-#define REG_USB_HOST_HSOFC         (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
-#define REG_USB_HOST_STATUS        (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
-#define REG_USB_HOST_FNUM          (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
-#define REG_USB_HOST_FLENHIGH      (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
-#define REG_USB_HOST_INTENCLR      (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
-#define REG_USB_HOST_INTENSET      (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
-#define REG_USB_HOST_INTFLAG       (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
-#define REG_USB_HOST_PINTSMRY      (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
-#define REG_USB_HOST_PIPE_PCFG0    (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
-#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
-#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
-#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
-#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
-#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
-#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
-#define REG_USB_HOST_PIPE_PCFG1    (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
-#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
-#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
-#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
-#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
-#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
-#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
-#define REG_USB_HOST_PIPE_PCFG2    (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
-#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
-#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
-#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
-#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
-#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
-#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
-#define REG_USB_HOST_PIPE_PCFG3    (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
-#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
-#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
-#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
-#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
-#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
-#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
-#define REG_USB_HOST_PIPE_PCFG4    (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
-#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
-#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
-#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
-#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
-#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
-#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
-#define REG_USB_HOST_PIPE_PCFG5    (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
-#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
-#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
-#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
-#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
-#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
-#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
-#define REG_USB_HOST_PIPE_PCFG6    (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
-#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
-#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
-#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
-#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
-#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
-#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
-#define REG_USB_HOST_PIPE_PCFG7    (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
-#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
-#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
-#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
-#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
-#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
-#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for USB peripheral ========== */
-#define USB_EPT_NBR                 8        // Number of USB end points (obsolete)
-#define USB_EPT_NUM                 8        // Number of USB end points
-#define USB_GCLK_ID                 6        // Index of Generic Clock
-#define USB_PIPE_NUM                8        // Number of USB pipes
-
-#endif /* _SAMD21_USB_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_INSTANCE_
+#define _SAMD21_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA              (0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (0x41005003U) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA              (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (*(RwReg  *)0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_EPT_NBR                 8        // Number of USB end points (obsolete)
+#define USB_EPT_NUM                 8        // Number of USB end points
+#define USB_GCLK_ID                 6        // Index of Generic Clock
+#define USB_PIPE_NUM                8        // Number of USB pipes
+
+#endif /* _SAMD21_USB_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h
index ce1ca65..c796b5b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h
@@ -1,61 +1,61 @@
-/**
- * \file
- *
- * \brief Instance description for WDT
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21_WDT_INSTANCE_
-#define _SAMD21_WDT_INSTANCE_
-
-/* ========== Register definition for WDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_WDT_CTRL               (0x40001000U) /**< \brief (WDT) Control */
-#define REG_WDT_CONFIG             (0x40001001U) /**< \brief (WDT) Configuration */
-#define REG_WDT_EWCTRL             (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
-#define REG_WDT_INTENCLR           (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
-#define REG_WDT_INTENSET           (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
-#define REG_WDT_INTFLAG            (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
-#define REG_WDT_STATUS             (0x40001007U) /**< \brief (WDT) Status */
-#define REG_WDT_CLEAR              (0x40001008U) /**< \brief (WDT) Clear */
-#else
-#define REG_WDT_CTRL               (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */
-#define REG_WDT_CONFIG             (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */
-#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
-#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
-#define REG_WDT_INTENSET           (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
-#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
-#define REG_WDT_STATUS             (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */
-#define REG_WDT_CLEAR              (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for WDT peripheral ========== */
-#define WDT_GCLK_ID                 3        // Index of Generic Clock
-
-#endif /* _SAMD21_WDT_INSTANCE_ */
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_INSTANCE_
+#define _SAMD21_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRL               (0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (0x40001008U) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRL               (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for WDT peripheral ========== */
+#define WDT_GCLK_ID                 3        // Index of Generic Clock
+
+#endif /* _SAMD21_WDT_INSTANCE_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
index fe3f095..19fc170 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
@@ -1,634 +1,634 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E15A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21E15A_PIO_
-#define _SAMD21E15A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E15A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21E15A_PIO_
+#define _SAMD21E15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E15A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h
index 3fdf86c..0015ada 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h
@@ -1,631 +1,631 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E15B
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15B_PIO_
-#define _SAMD21E15B_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E15B_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15B
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15B_PIO_
+#define _SAMD21E15B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E15B_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h
index 3097e76..ffcaac1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h
@@ -1,631 +1,631 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E15BU
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15BU_PIO_
-#define _SAMD21E15BU_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E15BU_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15BU
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15BU_PIO_
+#define _SAMD21E15BU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E15BU_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h
index 4754473..1471713 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h
@@ -1,610 +1,610 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E15L
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15L_PIO_
-#define _SAMD21E15L_PIO_
-
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for AC1 peripheral ========== */
-#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
-#define MUX_PB04B_AC1_AIN0                 1L
-#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
-#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
-#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
-#define MUX_PB05B_AC1_AIN1                 1L
-#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
-#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
-#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
-#define MUX_PB02B_AC1_AIN2                 1L
-#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
-#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
-#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
-#define MUX_PB03B_AC1_AIN3                 1L
-#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
-#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
-#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
-#define MUX_PA24H_AC1_CMP0                 7L
-#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
-#define PORT_PA24H_AC1_CMP0        (1ul << 24)
-#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
-#define MUX_PA25H_AC1_CMP1                 7L
-#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
-#define PORT_PA25H_AC1_CMP1        (1ul << 25)
-
-#endif /* _SAMD21E15L_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15L
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15L_PIO_
+#define _SAMD21E15L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21E15L_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
index 6798cf3..03c659e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
@@ -1,634 +1,634 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E16A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21E16A_PIO_
-#define _SAMD21E16A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E16A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21E16A_PIO_
+#define _SAMD21E16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E16A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h
index a892941..2bc74fd 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h
@@ -1,631 +1,631 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E16B
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16B_PIO_
-#define _SAMD21E16B_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E16B_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16B
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16B_PIO_
+#define _SAMD21E16B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E16B_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h
index a85c292..5c0d8bf 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h
@@ -1,631 +1,631 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E16BU
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16BU_PIO_
-#define _SAMD21E16BU_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E16BU_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16BU
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16BU_PIO_
+#define _SAMD21E16BU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E16BU_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h
index c766825..1f18b96 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h
@@ -1,610 +1,610 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E16L
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16L_PIO_
-#define _SAMD21E16L_PIO_
-
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for AC1 peripheral ========== */
-#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
-#define MUX_PB04B_AC1_AIN0                 1L
-#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
-#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
-#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
-#define MUX_PB05B_AC1_AIN1                 1L
-#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
-#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
-#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
-#define MUX_PB02B_AC1_AIN2                 1L
-#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
-#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
-#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
-#define MUX_PB03B_AC1_AIN3                 1L
-#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
-#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
-#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
-#define MUX_PA24H_AC1_CMP0                 7L
-#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
-#define PORT_PA24H_AC1_CMP0        (1ul << 24)
-#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
-#define MUX_PA25H_AC1_CMP1                 7L
-#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
-#define PORT_PA25H_AC1_CMP1        (1ul << 25)
-
-#endif /* _SAMD21E16L_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16L
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16L_PIO_
+#define _SAMD21E16L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21E16L_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
index f84b2f2..82f4c3a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
@@ -1,634 +1,634 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E17A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21E17A_PIO_
-#define _SAMD21E17A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E17A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21E17A_PIO_
+#define _SAMD21E17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E17A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17d.h
index e0c91a8..0cb9e3b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17d.h
@@ -1,700 +1,700 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E17D
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21E17D_PIO_
-#define _SAMD21E17D_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA28A_EIC_EXTINT_NUM           8L  /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM           9L  /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1     	   (1ul <<  8)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
-#define MUX_PA02F_TCC3_WO0                 5L
-#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
-#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
-#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
-#define MUX_PA03F_TCC3_WO1                 5L
-#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
-#define PORT_PA03F_TCC3_WO1    (1ul<<  3)
-#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
-#define MUX_PA04F_TCC3_WO2                 5L
-#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
-#define PORT_PA04F_TCC3_WO2    (1ul<<  4)
-#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
-#define MUX_PA05F_TCC3_WO3                 5L
-#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
-#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
-#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
-#define MUX_PA06F_TCC3_WO4                 5L
-#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
-#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
-#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
-#define MUX_PA30F_TCC3_WO4                 5L
-#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
-#define PORT_PA30F_TCC3_WO4    (1ul << 30)
-#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
-#define MUX_PA07F_TCC3_WO5                 5L
-#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
-#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
-#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
-#define MUX_PA31F_TCC3_WO5                 5L
-#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
-#define PORT_PA31F_TCC3_WO5    (1ul << 31)
-#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
-#define MUX_PA27F_TCC3_WO6                 5L
-#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
-#define PORT_PA27F_TCC3_WO6    (1ul << 27)
-#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
-#define MUX_PA28F_TCC3_WO7                 5L
-#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
-#define PORT_PA28F_TCC3_WO7    (1ul << 28)
-
-#endif /* _SAMD21E17D_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17D
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21E17D_PIO_
+#define _SAMD21E17D_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM           8L  /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM           9L  /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     	   (1ul <<  8)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
+#define MUX_PA02F_TCC3_WO0                 5L
+#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
+#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
+#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
+#define MUX_PA03F_TCC3_WO1                 5L
+#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
+#define PORT_PA03F_TCC3_WO1    (1ul<<  3)
+#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
+#define MUX_PA04F_TCC3_WO2                 5L
+#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
+#define PORT_PA04F_TCC3_WO2    (1ul<<  4)
+#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
+#define MUX_PA05F_TCC3_WO3                 5L
+#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
+#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
+#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
+#define MUX_PA06F_TCC3_WO4                 5L
+#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
+#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
+#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
+#define MUX_PA30F_TCC3_WO4                 5L
+#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
+#define PORT_PA30F_TCC3_WO4    (1ul << 30)
+#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
+#define MUX_PA07F_TCC3_WO5                 5L
+#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
+#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
+#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
+#define MUX_PA31F_TCC3_WO5                 5L
+#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
+#define PORT_PA31F_TCC3_WO5    (1ul << 31)
+#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
+#define MUX_PA27F_TCC3_WO6                 5L
+#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
+#define PORT_PA27F_TCC3_WO6    (1ul << 27)
+#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
+#define MUX_PA28F_TCC3_WO7                 5L
+#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
+#define PORT_PA28F_TCC3_WO7    (1ul << 28)
+
+#endif /* _SAMD21E17D_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17du.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17du.h
index 9de0bc7..66f0572 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17du.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17du.h
@@ -1,700 +1,700 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E17DU
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21E17DU_PIO_
-#define _SAMD21E17DU_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA28A_EIC_EXTINT_NUM           8L  /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM           9L  /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1     	   (1ul <<  8)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
-#define MUX_PA02F_TCC3_WO0                 5L
-#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
-#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
-#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
-#define MUX_PA03F_TCC3_WO1                 5L
-#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
-#define PORT_PA03F_TCC3_WO1    (1ul<<  3)
-#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
-#define MUX_PA04F_TCC3_WO2                 5L
-#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
-#define PORT_PA04F_TCC3_WO2    (1ul<<  4)
-#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
-#define MUX_PA05F_TCC3_WO3                 5L
-#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
-#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
-#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
-#define MUX_PA06F_TCC3_WO4                 5L
-#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
-#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
-#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
-#define MUX_PA30F_TCC3_WO4                 5L
-#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
-#define PORT_PA30F_TCC3_WO4    (1ul << 30)
-#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
-#define MUX_PA07F_TCC3_WO5                 5L
-#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
-#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
-#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
-#define MUX_PA31F_TCC3_WO5                 5L
-#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
-#define PORT_PA31F_TCC3_WO5    (1ul << 31)
-#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
-#define MUX_PA27F_TCC3_WO6                 5L
-#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
-#define PORT_PA27F_TCC3_WO6    (1ul << 27)
-#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
-#define MUX_PA28F_TCC3_WO7                 5L
-#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
-#define PORT_PA28F_TCC3_WO7    (1ul << 28)
-
-#endif /* _SAMD21E17DU_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17DU
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21E17DU_PIO_
+#define _SAMD21E17DU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM           8L  /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM           9L  /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     	   (1ul <<  8)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
+#define MUX_PA02F_TCC3_WO0                 5L
+#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
+#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
+#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
+#define MUX_PA03F_TCC3_WO1                 5L
+#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
+#define PORT_PA03F_TCC3_WO1    (1ul<<  3)
+#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
+#define MUX_PA04F_TCC3_WO2                 5L
+#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
+#define PORT_PA04F_TCC3_WO2    (1ul<<  4)
+#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
+#define MUX_PA05F_TCC3_WO3                 5L
+#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
+#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
+#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
+#define MUX_PA06F_TCC3_WO4                 5L
+#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
+#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
+#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
+#define MUX_PA30F_TCC3_WO4                 5L
+#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
+#define PORT_PA30F_TCC3_WO4    (1ul << 30)
+#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
+#define MUX_PA07F_TCC3_WO5                 5L
+#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
+#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
+#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
+#define MUX_PA31F_TCC3_WO5                 5L
+#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
+#define PORT_PA31F_TCC3_WO5    (1ul << 31)
+#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
+#define MUX_PA27F_TCC3_WO6                 5L
+#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
+#define PORT_PA27F_TCC3_WO6    (1ul << 27)
+#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
+#define MUX_PA28F_TCC3_WO7                 5L
+#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
+#define PORT_PA28F_TCC3_WO7    (1ul << 28)
+
+#endif /* _SAMD21E17DU_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17l.h
index c8185d9..c2e0d3e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17l.h
@@ -1,676 +1,676 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E17L
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E17L_PIO_
-#define _SAMD21E17L_PIO_
-
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PB03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PB04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PB05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM           9L  /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for AC1 peripheral ========== */
-#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
-#define MUX_PB04B_AC1_AIN0                 1L
-#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
-#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
-#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
-#define MUX_PB05B_AC1_AIN1                 1L
-#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
-#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
-#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
-#define MUX_PB02B_AC1_AIN2                 1L
-#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
-#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
-#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
-#define MUX_PB03B_AC1_AIN3                 1L
-#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
-#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
-#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
-#define MUX_PA24H_AC1_CMP0                 7L
-#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
-#define PORT_PA24H_AC1_CMP0        (1ul << 24)
-#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
-#define MUX_PA25H_AC1_CMP1                 7L
-#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
-#define PORT_PA25H_AC1_CMP1    	   (1ul << 25)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
-#define MUX_PA02F_TCC3_WO0                 5L
-#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
-#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
-#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
-#define MUX_PA03F_TCC3_WO1                 5L
-#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
-#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
-#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
-#define MUX_PA04F_TCC3_WO2                 5L
-#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
-#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
-#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
-#define MUX_PB02F_TCC3_WO2                 5L
-#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
-#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
-#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
-#define MUX_PA05F_TCC3_WO3                 5L
-#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
-#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
-#define PIN_PB03F_TCC3_WO3                35L /**< \brief TCC3 signal: WO3 on PB03 mux F */
-#define MUX_PB03F_TCC3_WO3                 5L
-#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
-#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
-#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
-#define MUX_PA06F_TCC3_WO4                 5L
-#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
-#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
-#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
-#define MUX_PA30F_TCC3_WO4                 5L
-#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
-#define PORT_PA30F_TCC3_WO4    (1ul << 30)
-#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
-#define MUX_PA07F_TCC3_WO5                 5L
-#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
-#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
-#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
-#define MUX_PA31F_TCC3_WO5                 5L
-#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
-#define PORT_PA31F_TCC3_WO5    (1ul << 31)
-
-#endif /* _SAMD21E17L_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17L
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17L_PIO_
+#define _SAMD21E17L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM           9L  /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1    	   (1ul << 25)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
+#define MUX_PA02F_TCC3_WO0                 5L
+#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
+#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
+#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
+#define MUX_PA03F_TCC3_WO1                 5L
+#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
+#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
+#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
+#define MUX_PA04F_TCC3_WO2                 5L
+#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
+#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
+#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC3_WO2                 5L
+#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
+#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
+#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
+#define MUX_PA05F_TCC3_WO3                 5L
+#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
+#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
+#define PIN_PB03F_TCC3_WO3                35L /**< \brief TCC3 signal: WO3 on PB03 mux F */
+#define MUX_PB03F_TCC3_WO3                 5L
+#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
+#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
+#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
+#define MUX_PA06F_TCC3_WO4                 5L
+#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
+#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
+#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
+#define MUX_PA30F_TCC3_WO4                 5L
+#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
+#define PORT_PA30F_TCC3_WO4    (1ul << 30)
+#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
+#define MUX_PA07F_TCC3_WO5                 5L
+#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
+#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
+#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
+#define MUX_PA31F_TCC3_WO5                 5L
+#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
+#define PORT_PA31F_TCC3_WO5    (1ul << 31)
+
+#endif /* _SAMD21E17L_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
index 61f15d5..56f2ae2 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
@@ -1,634 +1,634 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21E18A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21E18A_PIO_
-#define _SAMD21E18A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21E18A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E18A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21E18A_PIO_
+#define _SAMD21E18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21E18A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
index 1c51f21..e397639 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
@@ -1,908 +1,908 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G15A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G15A_PIO_
-#define _SAMD21G15A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G15A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G15A_PIO_
+#define _SAMD21G15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G15A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h
index df61e19..59639c1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h
@@ -1,905 +1,905 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G15B
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G15B_PIO_
-#define _SAMD21G15B_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G15B_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15B
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15B_PIO_
+#define _SAMD21G15B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G15B_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h
index cf3d776..24edb09 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h
@@ -1,894 +1,894 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G15L
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G15L_PIO_
-#define _SAMD21G15L_PIO_
-
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for AC1 peripheral ========== */
-#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
-#define MUX_PB04B_AC1_AIN0                 1L
-#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
-#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
-#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
-#define MUX_PB05B_AC1_AIN1                 1L
-#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
-#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
-#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
-#define MUX_PB02B_AC1_AIN2                 1L
-#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
-#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
-#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
-#define MUX_PB03B_AC1_AIN3                 1L
-#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
-#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
-#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
-#define MUX_PA24H_AC1_CMP0                 7L
-#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
-#define PORT_PA24H_AC1_CMP0        (1ul << 24)
-#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
-#define MUX_PA25H_AC1_CMP1                 7L
-#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
-#define PORT_PA25H_AC1_CMP1        (1ul << 25)
-
-#endif /* _SAMD21G15L_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15L
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15L_PIO_
+#define _SAMD21G15L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21G15L_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
index 398234c..6759665 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
@@ -1,908 +1,908 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G16A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G16A_PIO_
-#define _SAMD21G16A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G16A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G16A_PIO_
+#define _SAMD21G16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G16A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h
index ed463a8..13f07b6 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h
@@ -1,905 +1,905 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G16B
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G16B_PIO_
-#define _SAMD21G16B_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G16B_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16B
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16B_PIO_
+#define _SAMD21G16B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G16B_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h
index 41c64ba..e88fb8b 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h
@@ -1,894 +1,894 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G16L
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G16L_PIO_
-#define _SAMD21G16L_PIO_
-
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for AC1 peripheral ========== */
-#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
-#define MUX_PB04B_AC1_AIN0                 1L
-#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
-#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
-#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
-#define MUX_PB05B_AC1_AIN1                 1L
-#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
-#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
-#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
-#define MUX_PB02B_AC1_AIN2                 1L
-#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
-#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
-#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
-#define MUX_PB03B_AC1_AIN3                 1L
-#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
-#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
-#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
-#define MUX_PA24H_AC1_CMP0                 7L
-#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
-#define PORT_PA24H_AC1_CMP0        (1ul << 24)
-#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
-#define MUX_PA25H_AC1_CMP1                 7L
-#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
-#define PORT_PA25H_AC1_CMP1        (1ul << 25)
-
-#endif /* _SAMD21G16L_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16L
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16L_PIO_
+#define _SAMD21G16L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+
+#endif /* _SAMD21G16L_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
index 4284e10..5d5d38e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
@@ -1,908 +1,908 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G17A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G17A_PIO_
-#define _SAMD21G17A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G17A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G17A_PIO_
+#define _SAMD21G17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G17A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h
index 8807b13..076fef0 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h
@@ -1,856 +1,856 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G17AU
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
- /*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G17AU_PIO_
-#define _SAMD21G17AU_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G17AU_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17AU
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G17AU_PIO_
+#define _SAMD21G17AU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G17AU_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17d.h
index 5355bcc..c8cf444 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17d.h
@@ -1,1010 +1,1010 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G17D
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G17D_PIO_
-#define _SAMD21G17D_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PB03A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA20A_EIC_EXTINT_NUM           4L /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA21A_EIC_EXTINT_NUM           5L /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA28A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PB08A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PB10A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PB11A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA12A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
-#define MUX_PA02F_TCC3_WO0                 5L
-#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
-#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
-#define PIN_PB22F_TCC3_WO0                54L /**< \brief TCC3 signal: WO0 on PB22 mux F */
-#define MUX_PB22F_TCC3_WO0                 5L
-#define PINMUX_PB22F_TCC3_WO0      ((PIN_PB22F_TCC3_WO0 << 16) | MUX_PB22F_TCC3_WO0)
-#define PORT_PB22F_TCC3_WO0    (1ul << 22)
-#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
-#define MUX_PA03F_TCC3_WO1                 5L
-#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
-#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
-#define PIN_PB23F_TCC3_WO1                55L /**< \brief TCC3 signal: WO1 on PB23 mux F */
-#define MUX_PB23F_TCC3_WO1                 5L
-#define PINMUX_PB23F_TCC3_WO1      ((PIN_PB23F_TCC3_WO1 << 16) | MUX_PB23F_TCC3_WO1)
-#define PORT_PB23F_TCC3_WO1    (1ul << 23)
-#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
-#define MUX_PA04F_TCC3_WO2                 5L
-#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
-#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
-#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
-#define MUX_PB02F_TCC3_WO2                 5L
-#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
-#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
-#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
-#define MUX_PA05F_TCC3_WO3                 5L
-#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
-#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
-#define PIN_PB03F_TCC3_WO3                35L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
-#define MUX_PB03F_TCC3_WO3                 5L
-#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
-#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
-#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
-#define MUX_PA06F_TCC3_WO4                 5L
-#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
-#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
-#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
-#define MUX_PA30F_TCC3_WO4                 5L
-#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
-#define PORT_PA30F_TCC3_WO4    (1ul << 30)
-#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
-#define MUX_PA07F_TCC3_WO5                 5L
-#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
-#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
-#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
-#define MUX_PA31F_TCC3_WO5                 5L
-#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
-#define PORT_PA31F_TCC3_WO5    (1ul << 31)
-#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
-#define MUX_PA27F_TCC3_WO6                 5L
-#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
-#define PORT_PA27F_TCC3_WO6    (1ul << 27)
-#define PIN_PB08F_TCC3_WO6                40L /**< \brief TCC3 signal: WO6 on PB08 mux F */
-#define MUX_PB08F_TCC3_WO6                 5L
-#define PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
-#define PORT_PB08F_TCC3_WO6    (1ul <<  8)
-#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
-#define MUX_PA28F_TCC3_WO7                 5L
-#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
-#define PORT_PA28F_TCC3_WO7    (1ul << 28)
-#define PIN_PB09F_TCC3_WO7                41L /**< \brief TCC3 signal: WO7 on PB09 mux F */
-#define MUX_PB09F_TCC3_WO7                 5L
-#define PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
-#define PORT_PB09F_TCC3_WO7    (1ul <<  9)
-
-#endif /* _SAMD21G17D_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17D
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G17D_PIO_
+#define _SAMD21G17D_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM           4L /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM           5L /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
+#define MUX_PA02F_TCC3_WO0                 5L
+#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
+#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
+#define PIN_PB22F_TCC3_WO0                54L /**< \brief TCC3 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TCC3_WO0                 5L
+#define PINMUX_PB22F_TCC3_WO0      ((PIN_PB22F_TCC3_WO0 << 16) | MUX_PB22F_TCC3_WO0)
+#define PORT_PB22F_TCC3_WO0    (1ul << 22)
+#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
+#define MUX_PA03F_TCC3_WO1                 5L
+#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
+#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
+#define PIN_PB23F_TCC3_WO1                55L /**< \brief TCC3 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TCC3_WO1                 5L
+#define PINMUX_PB23F_TCC3_WO1      ((PIN_PB23F_TCC3_WO1 << 16) | MUX_PB23F_TCC3_WO1)
+#define PORT_PB23F_TCC3_WO1    (1ul << 23)
+#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
+#define MUX_PA04F_TCC3_WO2                 5L
+#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
+#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
+#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC3_WO2                 5L
+#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
+#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
+#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
+#define MUX_PA05F_TCC3_WO3                 5L
+#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
+#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
+#define PIN_PB03F_TCC3_WO3                35L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
+#define MUX_PB03F_TCC3_WO3                 5L
+#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
+#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
+#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
+#define MUX_PA06F_TCC3_WO4                 5L
+#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
+#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
+#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
+#define MUX_PA30F_TCC3_WO4                 5L
+#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
+#define PORT_PA30F_TCC3_WO4    (1ul << 30)
+#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
+#define MUX_PA07F_TCC3_WO5                 5L
+#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
+#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
+#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
+#define MUX_PA31F_TCC3_WO5                 5L
+#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
+#define PORT_PA31F_TCC3_WO5    (1ul << 31)
+#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
+#define MUX_PA27F_TCC3_WO6                 5L
+#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
+#define PORT_PA27F_TCC3_WO6    (1ul << 27)
+#define PIN_PB08F_TCC3_WO6                40L /**< \brief TCC3 signal: WO6 on PB08 mux F */
+#define MUX_PB08F_TCC3_WO6                 5L
+#define PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
+#define PORT_PB08F_TCC3_WO6    (1ul <<  8)
+#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
+#define MUX_PA28F_TCC3_WO7                 5L
+#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
+#define PORT_PA28F_TCC3_WO7    (1ul << 28)
+#define PIN_PB09F_TCC3_WO7                41L /**< \brief TCC3 signal: WO7 on PB09 mux F */
+#define MUX_PB09F_TCC3_WO7                 5L
+#define PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
+#define PORT_PB09F_TCC3_WO7    (1ul <<  9)
+
+#endif /* _SAMD21G17D_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17l.h
index b395916..457a75d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17l.h
@@ -1,988 +1,988 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G17L
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G17L_PIO_
-#define _SAMD21G17L_PIO_
-
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PB03A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA20A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PB04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA21A_EIC_EXTINT_NUM           5L /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PB05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA28A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PB08A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PB10A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PB11A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA12A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for AC1 peripheral ========== */
-#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
-#define MUX_PB04B_AC1_AIN0                 1L
-#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
-#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
-#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
-#define MUX_PB05B_AC1_AIN1                 1L
-#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
-#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
-#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
-#define MUX_PB02B_AC1_AIN2                 1L
-#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
-#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
-#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
-#define MUX_PB03B_AC1_AIN3                 1L
-#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
-#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
-#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
-#define MUX_PA24H_AC1_CMP0                 7L
-#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
-#define PORT_PA24H_AC1_CMP0        (1ul << 24)
-#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
-#define MUX_PA25H_AC1_CMP1                 7L
-#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
-#define PORT_PA25H_AC1_CMP1        (1ul << 25)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
-#define MUX_PA02F_TCC3_WO0                 5L
-#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
-#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
-#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
-#define MUX_PA03F_TCC3_WO1                 5L
-#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
-#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
-#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
-#define MUX_PA04F_TCC3_WO2                 5L
-#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
-#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
-#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
-#define MUX_PB02F_TCC3_WO2                 5L
-#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
-#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
-#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
-#define MUX_PA05F_TCC3_WO3                 5L
-#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
-#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
-#define PIN_PB03F_TCC3_WO3                35L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
-#define MUX_PB03F_TCC3_WO3                 5L
-#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
-#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
-#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
-#define MUX_PA06F_TCC3_WO4                 5L
-#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
-#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
-#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
-#define MUX_PA30F_TCC3_WO4                 5L
-#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
-#define PORT_PA30F_TCC3_WO4    (1ul << 30)
-#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
-#define MUX_PA07F_TCC3_WO5                 5L
-#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
-#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
-#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
-#define MUX_PA31F_TCC3_WO5                 5L
-#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
-#define PORT_PA31F_TCC3_WO5    (1ul << 31)
-#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
-#define MUX_PA27F_TCC3_WO6                 5L
-#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
-#define PORT_PA27F_TCC3_WO6    (1ul << 27)
-#define PIN_PB08F_TCC3_WO6                40L /**< \brief TCC3 signal: WO6 on PB08 mux F */
-#define MUX_PB08F_TCC3_WO6                 5L
-#define PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
-#define PORT_PB08F_TCC3_WO6    (1ul <<  8)
-#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
-#define MUX_PA28F_TCC3_WO7                 5L
-#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
-#define PORT_PA28F_TCC3_WO7    (1ul << 28)
-#define PIN_PB09F_TCC3_WO7                41L /**< \brief TCC3 signal: WO7 on PB09 mux F */
-#define MUX_PB09F_TCC3_WO7                 5L
-#define PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
-#define PORT_PB09F_TCC3_WO7    (1ul <<  9)
-
-#endif /* _SAMD21G17L_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17L
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17L_PIO_
+#define _SAMD21G17L_PIO_
+
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM           5L /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for AC1 peripheral ========== */
+#define PIN_PB04B_AC1_AIN0                36L  /**< \brief AC1 signal: AIN0 on PB04 mux B */
+#define MUX_PB04B_AC1_AIN0                 1L
+#define PINMUX_PB04B_AC1_AIN0      ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
+#define PORT_PB04B_AC1_AIN0        (1ul <<  4)
+#define PIN_PB05B_AC1_AIN1                37L  /**< \brief AC1 signal: AIN1 on PB05 mux B */
+#define MUX_PB05B_AC1_AIN1                 1L
+#define PINMUX_PB05B_AC1_AIN1      ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
+#define PORT_PB05B_AC1_AIN1        (1ul <<  5)
+#define PIN_PB02B_AC1_AIN2                34L  /**< \brief AC1 signal: AIN2 on PB02 mux B */
+#define MUX_PB02B_AC1_AIN2                 1L
+#define PINMUX_PB02B_AC1_AIN2      ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
+#define PORT_PB02B_AC1_AIN2        (1ul <<  2)
+#define PIN_PB03B_AC1_AIN3                35L  /**< \brief AC1 signal: AIN3 on PB03 mux B */
+#define MUX_PB03B_AC1_AIN3                 1L
+#define PINMUX_PB03B_AC1_AIN3      ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
+#define PORT_PB03B_AC1_AIN3        (1ul <<  3)
+#define PIN_PA24H_AC1_CMP0                24L  /**< \brief AC1 signal: CMP0 on PA24 mux H */
+#define MUX_PA24H_AC1_CMP0                 7L
+#define PINMUX_PA24H_AC1_CMP0      ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
+#define PORT_PA24H_AC1_CMP0        (1ul << 24)
+#define PIN_PA25H_AC1_CMP1                25L  /**< \brief AC1 signal: CMP1 on PA25 mux H */
+#define MUX_PA25H_AC1_CMP1                 7L
+#define PINMUX_PA25H_AC1_CMP1      ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
+#define PORT_PA25H_AC1_CMP1        (1ul << 25)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
+#define MUX_PA02F_TCC3_WO0                 5L
+#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
+#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
+#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
+#define MUX_PA03F_TCC3_WO1                 5L
+#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
+#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
+#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
+#define MUX_PA04F_TCC3_WO2                 5L
+#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
+#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
+#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC3_WO2                 5L
+#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
+#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
+#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
+#define MUX_PA05F_TCC3_WO3                 5L
+#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
+#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
+#define PIN_PB03F_TCC3_WO3                35L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
+#define MUX_PB03F_TCC3_WO3                 5L
+#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
+#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
+#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
+#define MUX_PA06F_TCC3_WO4                 5L
+#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
+#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
+#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
+#define MUX_PA30F_TCC3_WO4                 5L
+#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
+#define PORT_PA30F_TCC3_WO4    (1ul << 30)
+#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
+#define MUX_PA07F_TCC3_WO5                 5L
+#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
+#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
+#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
+#define MUX_PA31F_TCC3_WO5                 5L
+#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
+#define PORT_PA31F_TCC3_WO5    (1ul << 31)
+#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
+#define MUX_PA27F_TCC3_WO6                 5L
+#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
+#define PORT_PA27F_TCC3_WO6    (1ul << 27)
+#define PIN_PB08F_TCC3_WO6                40L /**< \brief TCC3 signal: WO6 on PB08 mux F */
+#define MUX_PB08F_TCC3_WO6                 5L
+#define PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
+#define PORT_PB08F_TCC3_WO6    (1ul <<  8)
+#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
+#define MUX_PA28F_TCC3_WO7                 5L
+#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
+#define PORT_PA28F_TCC3_WO7    (1ul << 28)
+#define PIN_PB09F_TCC3_WO7                41L /**< \brief TCC3 signal: WO7 on PB09 mux F */
+#define MUX_PB09F_TCC3_WO7                 5L
+#define PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
+#define PORT_PB09F_TCC3_WO7    (1ul <<  9)
+
+#endif /* _SAMD21G17L_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
index ed5727c..8705ce8 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
@@ -1,908 +1,908 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G18A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G18A_PIO_
-#define _SAMD21G18A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G18A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G18A_PIO_
+#define _SAMD21G18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G18A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h
index d2692f2..43a25b4 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h
@@ -1,856 +1,856 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21G18AU
- *
- * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
- /*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21G18AU_PIO_
-#define _SAMD21G18AU_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-
-#endif /* _SAMD21G18AU_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18AU
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+ /*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21G18AU_PIO_
+#define _SAMD21G18AU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+
+#endif /* _SAMD21G18AU_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
index c067dac..4a0b538 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
@@ -1,1182 +1,1182 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J15A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21J15A_PIO_
-#define _SAMD21J15A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1         (1ul << 16)
-
-#endif /* _SAMD21J15A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21J15A_PIO_
+#define _SAMD21J15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J15A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h
index 40e56d3..4934229 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h
@@ -1,1179 +1,1179 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J15B
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J15B_PIO_
-#define _SAMD21J15B_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1         (1ul << 16)
-
-#endif /* _SAMD21J15B_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15B
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15B_PIO_
+#define _SAMD21J15B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J15B_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
index 8a31bdf..c3b4316 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
@@ -1,1182 +1,1182 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J16A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21J16A_PIO_
-#define _SAMD21J16A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1         (1ul << 16)
-
-#endif /* _SAMD21J16A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21J16A_PIO_
+#define _SAMD21J16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J16A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h
index ce6cbf8..da1af8d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h
@@ -1,1179 +1,1179 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J16B
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J16B_PIO_
-#define _SAMD21J16B_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1         (1ul << 16)
-
-#endif /* _SAMD21J16B_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16B
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16B_PIO_
+#define _SAMD21J16B_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J16B_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
index 6ce8855..8c6c4f9 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
@@ -1,1182 +1,1182 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J17A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21J17A_PIO_
-#define _SAMD21J17A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1         (1ul << 16)
-
-#endif /* _SAMD21J17A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J17A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21J17A_PIO_
+#define _SAMD21J17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J17A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17d.h
index 51393ef..f77c1b6 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17d.h
@@ -1,1297 +1,1297 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J17D
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21J17D_PIO_
-#define _SAMD21J17D_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB17A_EIC_EXTINT_NUM           1L /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PB03A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PA20A_EIC_EXTINT_NUM           4L /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PB04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PA21A_EIC_EXTINT_NUM           5L /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PB05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB07A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PA28A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PB08A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PB10A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PB11A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA12A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PB12A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PB30A_EIC_EXTINT_NUM          14L /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1     	   (1ul << 16)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
-#define MUX_PA02F_TCC3_WO0                 5L
-#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
-#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
-#define PIN_PB22F_TCC3_WO0                54L /**< \brief TCC3 signal: WO0 on PB22 mux F */
-#define MUX_PB22F_TCC3_WO0                 5L
-#define PINMUX_PB22F_TCC3_WO0      ((PIN_PB22F_TCC3_WO0 << 16) | MUX_PB22F_TCC3_WO0)
-#define PORT_PB22F_TCC3_WO0    (1ul << 22)
-#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
-#define MUX_PA03F_TCC3_WO1                 5L
-#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
-#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
-#define PIN_PB23F_TCC3_WO1                55L /**< \brief TCC3 signal: WO1 on PB23 mux F */
-#define MUX_PB23F_TCC3_WO1                 5L
-#define PINMUX_PB23F_TCC3_WO1      ((PIN_PB23F_TCC3_WO1 << 16) | MUX_PB23F_TCC3_WO1)
-#define PORT_PB23F_TCC3_WO1    (1ul << 23)
-#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
-#define MUX_PA04F_TCC3_WO2                 5L
-#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
-#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
-#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
-#define MUX_PB02F_TCC3_WO2                 5L
-#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
-#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
-#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
-#define MUX_PA05F_TCC3_WO3                 5L
-#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
-#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
-#define PIN_PB03F_TCC3_WO3                35L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
-#define MUX_PB03F_TCC3_WO3                 5L
-#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
-#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
-#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
-#define MUX_PA06F_TCC3_WO4                 5L
-#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
-#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
-#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
-#define MUX_PA30F_TCC3_WO4                 5L
-#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
-#define PORT_PA30F_TCC3_WO4    (1ul << 30)
-#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
-#define MUX_PA07F_TCC3_WO5                 5L
-#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
-#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
-#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
-#define MUX_PA31F_TCC3_WO5                 5L
-#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
-#define PORT_PA31F_TCC3_WO5    (1ul << 31)
-#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
-#define MUX_PA27F_TCC3_WO6                 5L
-#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
-#define PORT_PA27F_TCC3_WO6    (1ul << 27)
-#define PIN_PB08F_TCC3_WO6                40L /**< \brief TCC3 signal: WO6 on PB08 mux F */
-#define MUX_PB08F_TCC3_WO6                 5L
-#define PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
-#define PORT_PB08F_TCC3_WO6    (1ul <<  8)
-#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
-#define MUX_PA28F_TCC3_WO7                 5L
-#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
-#define PORT_PA28F_TCC3_WO7    (1ul << 28)
-#define PIN_PB09F_TCC3_WO7                41L /**< \brief TCC3 signal: WO7 on PB09 mux F */
-#define MUX_PB09F_TCC3_WO7                 5L
-#define PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
-#define PORT_PB09F_TCC3_WO7    (1ul <<  9)
-
-#endif /* _SAMD21J17D_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J17D
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21J17D_PIO_
+#define _SAMD21J17D_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM           0L  /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM           1L /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM           1L  /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM           2L  /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM           2L /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM           3L  /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM           3L /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM           4L /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM           4L  /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM           5L /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM           5L  /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM           6L  /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM           6L /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM           7L  /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM           7L /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM           8L /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM           9L /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM          10L  /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM          10L /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM          11L  /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM          11L /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM          12L /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM          12L  /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM          13L  /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM          13L /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM          14L /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM          14L  /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM          15L  /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1     	   (1ul << 16)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PA02F_TCC3_WO0                 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
+#define MUX_PA02F_TCC3_WO0                 5L
+#define PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
+#define PORT_PA02F_TCC3_WO0    (1ul <<  2)
+#define PIN_PB22F_TCC3_WO0                54L /**< \brief TCC3 signal: WO0 on PB22 mux F */
+#define MUX_PB22F_TCC3_WO0                 5L
+#define PINMUX_PB22F_TCC3_WO0      ((PIN_PB22F_TCC3_WO0 << 16) | MUX_PB22F_TCC3_WO0)
+#define PORT_PB22F_TCC3_WO0    (1ul << 22)
+#define PIN_PA03F_TCC3_WO1                 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
+#define MUX_PA03F_TCC3_WO1                 5L
+#define PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
+#define PORT_PA03F_TCC3_WO1    (1ul <<  3)
+#define PIN_PB23F_TCC3_WO1                55L /**< \brief TCC3 signal: WO1 on PB23 mux F */
+#define MUX_PB23F_TCC3_WO1                 5L
+#define PINMUX_PB23F_TCC3_WO1      ((PIN_PB23F_TCC3_WO1 << 16) | MUX_PB23F_TCC3_WO1)
+#define PORT_PB23F_TCC3_WO1    (1ul << 23)
+#define PIN_PA04F_TCC3_WO2                 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
+#define MUX_PA04F_TCC3_WO2                 5L
+#define PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
+#define PORT_PA04F_TCC3_WO2    (1ul <<  4)
+#define PIN_PB02F_TCC3_WO2                34L /**< \brief TCC3 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC3_WO2                 5L
+#define PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
+#define PORT_PB02F_TCC3_WO2    (1ul <<  2)
+#define PIN_PA05F_TCC3_WO3                 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
+#define MUX_PA05F_TCC3_WO3                 5L
+#define PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
+#define PORT_PA05F_TCC3_WO3    (1ul <<  5)
+#define PIN_PB03F_TCC3_WO3                35L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
+#define MUX_PB03F_TCC3_WO3                 5L
+#define PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
+#define PORT_PB03F_TCC3_WO3    (1ul <<  3)
+#define PIN_PA06F_TCC3_WO4                 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
+#define MUX_PA06F_TCC3_WO4                 5L
+#define PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
+#define PORT_PA06F_TCC3_WO4    (1ul <<  6)
+#define PIN_PA30F_TCC3_WO4                30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
+#define MUX_PA30F_TCC3_WO4                 5L
+#define PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
+#define PORT_PA30F_TCC3_WO4    (1ul << 30)
+#define PIN_PA07F_TCC3_WO5                 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
+#define MUX_PA07F_TCC3_WO5                 5L
+#define PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
+#define PORT_PA07F_TCC3_WO5    (1ul <<  7)
+#define PIN_PA31F_TCC3_WO5                31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
+#define MUX_PA31F_TCC3_WO5                 5L
+#define PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
+#define PORT_PA31F_TCC3_WO5    (1ul << 31)
+#define PIN_PA27F_TCC3_WO6                27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
+#define MUX_PA27F_TCC3_WO6                 5L
+#define PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
+#define PORT_PA27F_TCC3_WO6    (1ul << 27)
+#define PIN_PB08F_TCC3_WO6                40L /**< \brief TCC3 signal: WO6 on PB08 mux F */
+#define MUX_PB08F_TCC3_WO6                 5L
+#define PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
+#define PORT_PB08F_TCC3_WO6    (1ul <<  8)
+#define PIN_PA28F_TCC3_WO7                28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
+#define MUX_PA28F_TCC3_WO7                 5L
+#define PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
+#define PORT_PA28F_TCC3_WO7    (1ul << 28)
+#define PIN_PB09F_TCC3_WO7                41L /**< \brief TCC3 signal: WO7 on PB09 mux F */
+#define MUX_PB09F_TCC3_WO7                 5L
+#define PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
+#define PORT_PB09F_TCC3_WO7    (1ul <<  9)
+
+#endif /* _SAMD21J17D_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
index b1ac18f..0c65211 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
@@ -1,1182 +1,1182 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD21J18A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21J18A_PIO_
-#define _SAMD21J18A_PIO_
-
-#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
-#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
-#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
-#define MUX_PB14H_GCLK_IO0                 7L
-#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
-#define PORT_PB14H_GCLK_IO0        (1ul << 14)
-#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
-#define MUX_PB22H_GCLK_IO0                 7L
-#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
-#define PORT_PB22H_GCLK_IO0        (1ul << 22)
-#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
-#define MUX_PA14H_GCLK_IO0                 7L
-#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
-#define PORT_PA14H_GCLK_IO0        (1ul << 14)
-#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
-#define MUX_PA27H_GCLK_IO0                 7L
-#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
-#define PORT_PA27H_GCLK_IO0        (1ul << 27)
-#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
-#define MUX_PA28H_GCLK_IO0                 7L
-#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
-#define PORT_PA28H_GCLK_IO0        (1ul << 28)
-#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
-#define MUX_PA30H_GCLK_IO0                 7L
-#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
-#define PORT_PA30H_GCLK_IO0        (1ul << 30)
-#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
-#define MUX_PB15H_GCLK_IO1                 7L
-#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
-#define PORT_PB15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
-#define MUX_PB23H_GCLK_IO1                 7L
-#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
-#define PORT_PB23H_GCLK_IO1        (1ul << 23)
-#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
-#define MUX_PA15H_GCLK_IO1                 7L
-#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
-#define PORT_PA15H_GCLK_IO1        (1ul << 15)
-#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
-#define MUX_PB16H_GCLK_IO2                 7L
-#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
-#define PORT_PB16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
-#define MUX_PA16H_GCLK_IO2                 7L
-#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
-#define PORT_PA16H_GCLK_IO2        (1ul << 16)
-#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
-#define MUX_PA17H_GCLK_IO3                 7L
-#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
-#define PORT_PA17H_GCLK_IO3        (1ul << 17)
-#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
-#define MUX_PB17H_GCLK_IO3                 7L
-#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
-#define PORT_PB17H_GCLK_IO3        (1ul << 17)
-#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
-#define MUX_PA10H_GCLK_IO4                 7L
-#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
-#define PORT_PA10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
-#define MUX_PA20H_GCLK_IO4                 7L
-#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
-#define PORT_PA20H_GCLK_IO4        (1ul << 20)
-#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
-#define MUX_PB10H_GCLK_IO4                 7L
-#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
-#define PORT_PB10H_GCLK_IO4        (1ul << 10)
-#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
-#define MUX_PA11H_GCLK_IO5                 7L
-#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
-#define PORT_PA11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
-#define MUX_PA21H_GCLK_IO5                 7L
-#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
-#define PORT_PA21H_GCLK_IO5        (1ul << 21)
-#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
-#define MUX_PB11H_GCLK_IO5                 7L
-#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
-#define PORT_PB11H_GCLK_IO5        (1ul << 11)
-#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
-#define MUX_PA22H_GCLK_IO6                 7L
-#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
-#define PORT_PA22H_GCLK_IO6        (1ul << 22)
-#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
-#define MUX_PB12H_GCLK_IO6                 7L
-#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
-#define PORT_PB12H_GCLK_IO6        (1ul << 12)
-#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
-#define MUX_PA23H_GCLK_IO7                 7L
-#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
-#define PORT_PA23H_GCLK_IO7        (1ul << 23)
-#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
-#define MUX_PB13H_GCLK_IO7                 7L
-#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
-#define PORT_PB13H_GCLK_IO7        (1ul << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0              0L
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0              0L
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0              0L
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
-#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0              0L
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
-#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1              0L
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1              0L
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1              0L
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
-#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1              0L
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
-#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2              0L
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
-#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2              0L
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2              0L
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
-#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3              0L
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3              0L
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
-#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3              0L
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
-#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4              0L
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4              0L
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
-#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4              0L
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
-#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5              0L
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5              0L
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
-#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5              0L
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
-#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6              0L
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6              0L
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6              0L
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
-#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6              0L
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
-#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7              0L
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7              0L
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7              0L
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
-#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7              0L
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
-#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
-#define MUX_PA28A_EIC_EXTINT8              0L
-#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
-#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
-#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8              0L
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
-#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9              0L
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9              0L
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
-#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10             0L
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT10             0L
-#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
-#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
-#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10             0L
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
-#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11             0L
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT11             0L
-#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
-#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
-#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11             0L
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
-#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12             0L
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT12             0L
-#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
-#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
-#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12             0L
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
-#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13             0L
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT13             0L
-#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
-#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
-#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13             0L
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
-#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14             0L
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14             0L
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
-#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14             0L
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
-#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15             0L
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT15             0L
-#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
-#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
-#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15             0L
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
-#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15             0L
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
-#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI                  0L
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI         (1ul <<  8)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
-#define MUX_PA24G_USB_DM                   6L
-#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
-#define PORT_PA24G_USB_DM          (1ul << 24)
-#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
-#define MUX_PA25G_USB_DP                   6L
-#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
-#define PORT_PA25G_USB_DP          (1ul << 25)
-#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
-#define MUX_PA23G_USB_SOF_1KHZ             6L
-#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
-#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0             3L
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
-#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0             2L
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
-#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1             3L
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
-#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1             2L
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
-#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2             3L
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
-#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2             2L
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
-#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3             3L
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
-#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3             2L
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0             2L
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
-#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0             3L
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
-#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1             2L
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
-#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1             3L
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
-#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2             3L
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
-#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2             2L
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
-#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3             3L
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
-#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3             2L
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD0             3L
-#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
-#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
-#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0             2L
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
-#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD1             3L
-#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
-#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
-#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1             2L
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
-#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2             3L
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
-#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2             2L
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
-#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3             3L
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
-#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3             2L
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD0             3L
-#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
-#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
-#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0             2L
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
-#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD1             3L
-#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
-#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
-#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1             2L
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
-#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2             3L
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
-#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2             3L
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
-#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2             2L
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
-#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3             3L
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
-#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3             3L
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
-#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3             2L
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD0             3L
-#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
-#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0             3L
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
-#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0             2L
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
-#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD1             3L
-#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
-#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1             3L
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
-#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1             2L
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
-#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2             3L
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2             3L
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
-#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2             2L
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
-#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3             3L
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
-#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3             3L
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
-#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3             2L
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0             2L
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
-#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD0             3L
-#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
-#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
-#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0             3L
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
-#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD0             3L
-#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
-#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
-#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1             2L
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
-#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD1             3L
-#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
-#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
-#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1             3L
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
-#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD1             3L
-#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
-#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
-#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2             3L
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
-#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2             3L
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
-#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2             3L
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
-#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2             2L
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
-#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3             3L
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
-#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3             3L
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
-#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3             3L
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
-#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3             2L
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TCC0_WO0                 4L
-#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
-#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
-#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TCC0_WO0                 4L
-#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
-#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
-#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TCC0_WO0                 4L
-#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
-#define PORT_PB30E_TCC0_WO0        (1ul << 30)
-#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TCC0_WO1                 4L
-#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
-#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
-#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TCC0_WO1                 4L
-#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
-#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
-#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TCC0_WO1                 4L
-#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
-#define PORT_PB31E_TCC0_WO1        (1ul << 31)
-#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2                 5L
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2        (1ul << 10)
-#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC0_WO2                 5L
-#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
-#define PORT_PA18F_TCC0_WO2        (1ul << 18)
-#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3                 5L
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3        (1ul << 11)
-#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC0_WO3                 5L
-#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
-#define PORT_PA19F_TCC0_WO3        (1ul << 19)
-#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
-#define MUX_PA14F_TCC0_WO4                 5L
-#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
-#define PORT_PA14F_TCC0_WO4        (1ul << 14)
-#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
-#define MUX_PA22F_TCC0_WO4                 5L
-#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
-#define PORT_PA22F_TCC0_WO4        (1ul << 22)
-#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4                 5L
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4        (1ul << 10)
-#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
-#define MUX_PB16F_TCC0_WO4                 5L
-#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
-#define PORT_PB16F_TCC0_WO4        (1ul << 16)
-#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
-#define MUX_PA15F_TCC0_WO5                 5L
-#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
-#define PORT_PA15F_TCC0_WO5        (1ul << 15)
-#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
-#define MUX_PA23F_TCC0_WO5                 5L
-#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
-#define PORT_PA23F_TCC0_WO5        (1ul << 23)
-#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5                 5L
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5        (1ul << 11)
-#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
-#define MUX_PB17F_TCC0_WO5                 5L
-#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
-#define PORT_PB17F_TCC0_WO5        (1ul << 17)
-#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6                 5L
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
-#define MUX_PA20F_TCC0_WO6                 5L
-#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
-#define PORT_PA20F_TCC0_WO6        (1ul << 20)
-#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
-#define MUX_PB12F_TCC0_WO6                 5L
-#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
-#define PORT_PB12F_TCC0_WO6        (1ul << 12)
-#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
-#define MUX_PA16F_TCC0_WO6                 5L
-#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
-#define PORT_PA16F_TCC0_WO6        (1ul << 16)
-#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7                 5L
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
-#define MUX_PA21F_TCC0_WO7                 5L
-#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
-#define PORT_PA21F_TCC0_WO7        (1ul << 21)
-#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
-#define MUX_PB13F_TCC0_WO7                 5L
-#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
-#define PORT_PB13F_TCC0_WO7        (1ul << 13)
-#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
-#define MUX_PA17F_TCC0_WO7                 5L
-#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
-#define PORT_PA17F_TCC0_WO7        (1ul << 17)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TCC1_WO0                 4L
-#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
-#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
-#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TCC1_WO0                 4L
-#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
-#define PORT_PA10E_TCC1_WO0        (1ul << 10)
-#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
-#define MUX_PA30E_TCC1_WO0                 4L
-#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
-#define PORT_PA30E_TCC1_WO0        (1ul << 30)
-#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TCC1_WO1                 4L
-#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
-#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
-#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TCC1_WO1                 4L
-#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
-#define PORT_PA11E_TCC1_WO1        (1ul << 11)
-#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
-#define MUX_PA31E_TCC1_WO1                 4L
-#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
-#define PORT_PA31E_TCC1_WO1        (1ul << 31)
-#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
-#define MUX_PA08F_TCC1_WO2                 5L
-#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
-#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
-#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC1_WO2                 5L
-#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
-#define PORT_PA24F_TCC1_WO2        (1ul << 24)
-#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
-#define MUX_PB30F_TCC1_WO2                 5L
-#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
-#define PORT_PB30F_TCC1_WO2        (1ul << 30)
-#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
-#define MUX_PA09F_TCC1_WO3                 5L
-#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
-#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
-#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
-#define MUX_PA25F_TCC1_WO3                 5L
-#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
-#define PORT_PA25F_TCC1_WO3        (1ul << 25)
-#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
-#define MUX_PB31F_TCC1_WO3                 5L
-#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
-#define PORT_PB31F_TCC1_WO3        (1ul << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TCC2_WO0                 4L
-#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
-#define PORT_PA12E_TCC2_WO0        (1ul << 12)
-#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TCC2_WO0                 4L
-#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
-#define PORT_PA16E_TCC2_WO0        (1ul << 16)
-#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TCC2_WO0                 4L
-#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
-#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
-#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TCC2_WO1                 4L
-#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
-#define PORT_PA13E_TCC2_WO1        (1ul << 13)
-#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TCC2_WO1                 4L
-#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
-#define PORT_PA17E_TCC2_WO1        (1ul << 17)
-#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TCC2_WO1                 4L
-#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
-#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0                  4L
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0         (1ul << 18)
-#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0                  4L
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0         (1ul << 14)
-#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1                  4L
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1         (1ul << 19)
-#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1                  4L
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1         (1ul << 15)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0                  4L
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0         (1ul << 22)
-#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0                  4L
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0         (1ul <<  8)
-#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0                  4L
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0         (1ul << 12)
-#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1                  4L
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1         (1ul << 23)
-#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1                  4L
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1         (1ul <<  9)
-#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1                  4L
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1         (1ul << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0                  4L
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0         (1ul << 24)
-#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0                  4L
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0         (1ul << 10)
-#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0                  4L
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0         (1ul << 14)
-#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1                  4L
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1         (1ul << 25)
-#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1                  4L
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1         (1ul << 11)
-#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1                  4L
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1         (1ul << 15)
-/* ========== PORT definition for TC6 peripheral ========== */
-#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
-#define MUX_PB02E_TC6_WO0                  4L
-#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
-#define PORT_PB02E_TC6_WO0         (1ul <<  2)
-#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
-#define MUX_PB16E_TC6_WO0                  4L
-#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
-#define PORT_PB16E_TC6_WO0         (1ul << 16)
-#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
-#define MUX_PB03E_TC6_WO1                  4L
-#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
-#define PORT_PB03E_TC6_WO1         (1ul <<  3)
-#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
-#define MUX_PB17E_TC6_WO1                  4L
-#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
-#define PORT_PB17E_TC6_WO1         (1ul << 17)
-/* ========== PORT definition for TC7 peripheral ========== */
-#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
-#define MUX_PA20E_TC7_WO0                  4L
-#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
-#define PORT_PA20E_TC7_WO0         (1ul << 20)
-#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
-#define MUX_PB00E_TC7_WO0                  4L
-#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
-#define PORT_PB00E_TC7_WO0         (1ul <<  0)
-#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
-#define MUX_PB22E_TC7_WO0                  4L
-#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
-#define PORT_PB22E_TC7_WO0         (1ul << 22)
-#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
-#define MUX_PA21E_TC7_WO1                  4L
-#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
-#define PORT_PA21E_TC7_WO1         (1ul << 21)
-#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
-#define MUX_PB01E_TC7_WO1                  4L
-#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
-#define PORT_PB01E_TC7_WO1         (1ul <<  1)
-#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
-#define MUX_PB23E_TC7_WO1                  4L
-#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
-#define PORT_PB23E_TC7_WO1         (1ul << 23)
-/* ========== PORT definition for ADC peripheral ========== */
-#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC_AIN0                 1L
-#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
-#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
-#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC_AIN1                 1L
-#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
-#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
-#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC_AIN2                 1L
-#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
-#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
-#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC_AIN3                 1L
-#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
-#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
-#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC_AIN4                 1L
-#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
-#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
-#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC_AIN5                 1L
-#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
-#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
-#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC_AIN6                 1L
-#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
-#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
-#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC_AIN7                 1L
-#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
-#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
-#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
-#define MUX_PB00B_ADC_AIN8                 1L
-#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
-#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
-#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
-#define MUX_PB01B_ADC_AIN9                 1L
-#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
-#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
-#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
-#define MUX_PB02B_ADC_AIN10                1L
-#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
-#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
-#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
-#define MUX_PB03B_ADC_AIN11                1L
-#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
-#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
-#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
-#define MUX_PB04B_ADC_AIN12                1L
-#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
-#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
-#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
-#define MUX_PB05B_ADC_AIN13                1L
-#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
-#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
-#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
-#define MUX_PB06B_ADC_AIN14                1L
-#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
-#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
-#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
-#define MUX_PB07B_ADC_AIN15                1L
-#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
-#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
-#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
-#define MUX_PA08B_ADC_AIN16                1L
-#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
-#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
-#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
-#define MUX_PA09B_ADC_AIN17                1L
-#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
-#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
-#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
-#define MUX_PA10B_ADC_AIN18                1L
-#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
-#define PORT_PA10B_ADC_AIN18       (1ul << 10)
-#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
-#define MUX_PA11B_ADC_AIN19                1L
-#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
-#define PORT_PA11B_ADC_AIN19       (1ul << 11)
-#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
-#define MUX_PA04B_ADC_VREFP                1L
-#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
-#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0                  1L
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0         (1ul <<  4)
-#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1                  1L
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1         (1ul <<  5)
-#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2                  1L
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2         (1ul <<  6)
-#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3                  1L
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3         (1ul <<  7)
-#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
-#define MUX_PA12H_AC_CMP0                  7L
-#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
-#define PORT_PA12H_AC_CMP0         (1ul << 12)
-#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
-#define MUX_PA18H_AC_CMP0                  7L
-#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
-#define PORT_PA18H_AC_CMP0         (1ul << 18)
-#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
-#define MUX_PA13H_AC_CMP1                  7L
-#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
-#define PORT_PA13H_AC_CMP1         (1ul << 13)
-#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
-#define MUX_PA19H_AC_CMP1                  7L
-#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
-#define PORT_PA19H_AC_CMP1         (1ul << 19)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT                 1L
-#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
-#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
-#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
-#define MUX_PA03B_DAC_VREFP                1L
-#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
-#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
-#define MUX_PA11G_I2S_FS0                  6L
-#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
-#define PORT_PA11G_I2S_FS0         (1ul << 11)
-#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
-#define MUX_PA21G_I2S_FS0                  6L
-#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
-#define PORT_PA21G_I2S_FS0         (1ul << 21)
-#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
-#define MUX_PB12G_I2S_FS1                  6L
-#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
-#define PORT_PB12G_I2S_FS1         (1ul << 12)
-#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
-#define MUX_PA09G_I2S_MCK0                 6L
-#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
-#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
-#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
-#define MUX_PB17G_I2S_MCK0                 6L
-#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
-#define PORT_PB17G_I2S_MCK0        (1ul << 17)
-#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
-#define MUX_PB10G_I2S_MCK1                 6L
-#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
-#define PORT_PB10G_I2S_MCK1        (1ul << 10)
-#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
-#define MUX_PA10G_I2S_SCK0                 6L
-#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
-#define PORT_PA10G_I2S_SCK0        (1ul << 10)
-#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
-#define MUX_PA20G_I2S_SCK0                 6L
-#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
-#define PORT_PA20G_I2S_SCK0        (1ul << 20)
-#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
-#define MUX_PB11G_I2S_SCK1                 6L
-#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
-#define PORT_PB11G_I2S_SCK1        (1ul << 11)
-#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
-#define MUX_PA07G_I2S_SD0                  6L
-#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
-#define PORT_PA07G_I2S_SD0         (1ul <<  7)
-#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
-#define MUX_PA19G_I2S_SD0                  6L
-#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
-#define PORT_PA19G_I2S_SD0         (1ul << 19)
-#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
-#define MUX_PA08G_I2S_SD1                  6L
-#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
-#define PORT_PA08G_I2S_SD1         (1ul <<  8)
-#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
-#define MUX_PB16G_I2S_SD1                  6L
-#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
-#define PORT_PB16G_I2S_SD1         (1ul << 16)
-
-#endif /* _SAMD21J18A_PIO_ */
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J18A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21J18A_PIO_
+#define _SAMD21J18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00                 (1ul <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01                 (1ul <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02                 (1ul <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03                 (1ul <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04                 (1ul <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05                 (1ul <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06                 (1ul <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07                 (1ul <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08                 (1ul <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09                 (1ul <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10                 (1ul << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11                 (1ul << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12                 (1ul << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13                 (1ul << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14                 (1ul << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15                 (1ul << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16                 (1ul << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17                 (1ul << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18                 (1ul << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19                 (1ul << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20                 (1ul << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21                 (1ul << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22                 (1ul << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23                 (1ul << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24                 (1ul << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25                 (1ul << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27                 (1ul << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28                 (1ul << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30                 (1ul << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31                 (1ul << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00                 (1ul <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01                 (1ul <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02                 (1ul <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03                 (1ul <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04                 (1ul <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05                 (1ul <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06                 (1ul <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07                 (1ul <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08                 (1ul <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09                 (1ul <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10                 (1ul << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11                 (1ul << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12                 (1ul << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13                 (1ul << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14                 (1ul << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15                 (1ul << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16                 (1ul << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17                 (1ul << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22                 (1ul << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23                 (1ul << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30                 (1ul << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31                 (1ul << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0                46L  /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0                 7L
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0        (1ul << 14)
+#define PIN_PB22H_GCLK_IO0                54L  /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0                 7L
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0        (1ul << 22)
+#define PIN_PA14H_GCLK_IO0                14L  /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0                 7L
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0        (1ul << 14)
+#define PIN_PA27H_GCLK_IO0                27L  /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0                 7L
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0        (1ul << 27)
+#define PIN_PA28H_GCLK_IO0                28L  /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0                 7L
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0        (1ul << 28)
+#define PIN_PA30H_GCLK_IO0                30L  /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0                 7L
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0        (1ul << 30)
+#define PIN_PB15H_GCLK_IO1                47L  /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1                 7L
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB23H_GCLK_IO1                55L  /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1                 7L
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1        (1ul << 23)
+#define PIN_PA15H_GCLK_IO1                15L  /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1                 7L
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1        (1ul << 15)
+#define PIN_PB16H_GCLK_IO2                48L  /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2                 7L
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA16H_GCLK_IO2                16L  /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2                 7L
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2        (1ul << 16)
+#define PIN_PA17H_GCLK_IO3                17L  /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3                 7L
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3        (1ul << 17)
+#define PIN_PB17H_GCLK_IO3                49L  /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3                 7L
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3        (1ul << 17)
+#define PIN_PA10H_GCLK_IO4                10L  /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4                 7L
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA20H_GCLK_IO4                20L  /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4                 7L
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4        (1ul << 20)
+#define PIN_PB10H_GCLK_IO4                42L  /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4                 7L
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4        (1ul << 10)
+#define PIN_PA11H_GCLK_IO5                11L  /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5                 7L
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA21H_GCLK_IO5                21L  /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5                 7L
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5        (1ul << 21)
+#define PIN_PB11H_GCLK_IO5                43L  /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5                 7L
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5        (1ul << 11)
+#define PIN_PA22H_GCLK_IO6                22L  /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6                 7L
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6        (1ul << 22)
+#define PIN_PB12H_GCLK_IO6                44L  /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6                 7L
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6        (1ul << 12)
+#define PIN_PA23H_GCLK_IO7                23L  /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7                 7L
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7        (1ul << 23)
+#define PIN_PB13H_GCLK_IO7                45L  /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7                 7L
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7        (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0             16L  /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0              0L
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0             32L  /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0              0L
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PB16A_EIC_EXTINT0             48L  /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0              0L
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0     (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0              0L  /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0              0L
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0     (1ul <<  0)
+#define PIN_PA17A_EIC_EXTINT1             17L  /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1              0L
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1             33L  /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1              0L
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PB17A_EIC_EXTINT1             49L  /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1              0L
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1     (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1              1L  /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1              0L
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1     (1ul <<  1)
+#define PIN_PA18A_EIC_EXTINT2             18L  /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2              0L
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2     (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2              2L  /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2              0L
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PB02A_EIC_EXTINT2             34L  /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2              0L
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2     (1ul <<  2)
+#define PIN_PA03A_EIC_EXTINT3              3L  /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3              0L
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA19A_EIC_EXTINT3             19L  /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3              0L
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3     (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3             35L  /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3              0L
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3     (1ul <<  3)
+#define PIN_PA04A_EIC_EXTINT4              4L  /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4              0L
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA20A_EIC_EXTINT4             20L  /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4              0L
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4     (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4             36L  /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4              0L
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4     (1ul <<  4)
+#define PIN_PA05A_EIC_EXTINT5              5L  /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5              0L
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA21A_EIC_EXTINT5             21L  /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5              0L
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5     (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5             37L  /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5              0L
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5     (1ul <<  5)
+#define PIN_PA06A_EIC_EXTINT6              6L  /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6              0L
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PA22A_EIC_EXTINT6             22L  /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6              0L
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6             38L  /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6              0L
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6     (1ul <<  6)
+#define PIN_PB22A_EIC_EXTINT6             54L  /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6              0L
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6     (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7              7L  /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7              0L
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PA23A_EIC_EXTINT7             23L  /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7              0L
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7             39L  /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7              0L
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7     (1ul <<  7)
+#define PIN_PB23A_EIC_EXTINT7             55L  /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7              0L
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7     (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8             28L  /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8              0L
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8     (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8             40L  /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8              0L
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8     (1ul <<  8)
+#define PIN_PA09A_EIC_EXTINT9              9L  /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9              0L
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PB09A_EIC_EXTINT9             41L  /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9              0L
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9     (1ul <<  9)
+#define PIN_PA10A_EIC_EXTINT10            10L  /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10             0L
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10            30L  /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10             0L
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10    (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10            42L  /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10             0L
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10    (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11            11L  /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11             0L
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11            31L  /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11             0L
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11    (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11            43L  /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11             0L
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11    (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12            12L  /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12             0L
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12            24L  /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12             0L
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12    (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12            44L  /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12             0L
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12    (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13            13L  /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13             0L
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13            25L  /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13             0L
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13    (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13            45L  /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13             0L
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13    (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14            46L  /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14             0L
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14            62L  /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14             0L
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14    (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14            14L  /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14             0L
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14    (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15            15L  /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15             0L
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15            27L  /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15             0L
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15    (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15            47L  /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15             0L
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15    (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15            63L  /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15             0L
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15    (1ul << 31)
+#define PIN_PA08A_EIC_NMI                  8L  /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI                  0L
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI         (1ul <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM                  24L  /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                   6L
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM          (1ul << 24)
+#define PIN_PA25G_USB_DP                  25L  /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                   6L
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP          (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ            23L  /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ             6L
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ    (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0             4L  /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0             3L
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0    (1ul <<  4)
+#define PIN_PA08C_SERCOM0_PAD0             8L  /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0             2L
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0    (1ul <<  8)
+#define PIN_PA05D_SERCOM0_PAD1             5L  /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1             3L
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1    (1ul <<  5)
+#define PIN_PA09C_SERCOM0_PAD1             9L  /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1             2L
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1    (1ul <<  9)
+#define PIN_PA06D_SERCOM0_PAD2             6L  /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2             3L
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2    (1ul <<  6)
+#define PIN_PA10C_SERCOM0_PAD2            10L  /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2             2L
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2    (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3             7L  /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3             3L
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3    (1ul <<  7)
+#define PIN_PA11C_SERCOM0_PAD3            11L  /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3             2L
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3    (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0            16L  /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0             2L
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0    (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0             0L  /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0             3L
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0    (1ul <<  0)
+#define PIN_PA17C_SERCOM1_PAD1            17L  /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1             2L
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1    (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1             1L  /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1             3L
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1    (1ul <<  1)
+#define PIN_PA30D_SERCOM1_PAD2            30L  /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2             3L
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2    (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2            18L  /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2             2L
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2    (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3            31L  /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3             3L
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3    (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3            19L  /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3             2L
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3    (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0             8L  /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0             3L
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0    (1ul <<  8)
+#define PIN_PA12C_SERCOM2_PAD0            12L  /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0             2L
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0    (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1             9L  /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1             3L
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1    (1ul <<  9)
+#define PIN_PA13C_SERCOM2_PAD1            13L  /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1             2L
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1    (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2            10L  /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2             3L
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2    (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2            14L  /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2             2L
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2    (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3            11L  /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3             3L
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3    (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3            15L  /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3             2L
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0            16L  /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0             3L
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0    (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0            22L  /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0             2L
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0    (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1            17L  /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1             3L
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1    (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1            23L  /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1             2L
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1    (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2            18L  /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2             3L
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2    (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2            20L  /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2             3L
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2    (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2            24L  /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2             2L
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2    (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3            19L  /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3             3L
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3    (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3            21L  /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3             3L
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3    (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3            25L  /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3             2L
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3    (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0            12L  /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0             3L
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0            40L  /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0             3L
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0    (1ul <<  8)
+#define PIN_PB12C_SERCOM4_PAD0            44L  /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0             2L
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0    (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1            13L  /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1             3L
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1            41L  /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1             3L
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1    (1ul <<  9)
+#define PIN_PB13C_SERCOM4_PAD1            45L  /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1             2L
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1    (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2            14L  /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2             3L
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2            42L  /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2             3L
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2    (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2            46L  /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2             2L
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2    (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3            15L  /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3             3L
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3    (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3            43L  /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3             3L
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3    (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3            47L  /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3             2L
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3    (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0            48L  /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0             2L
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0    (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0            22L  /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0             3L
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0    (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0            34L  /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0             3L
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0    (1ul <<  2)
+#define PIN_PB30D_SERCOM5_PAD0            62L  /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0             3L
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0    (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1            49L  /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1             2L
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1    (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1            23L  /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1             3L
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1    (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1            35L  /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1             3L
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1    (1ul <<  3)
+#define PIN_PB31D_SERCOM5_PAD1            63L  /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1             3L
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1    (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2            24L  /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2             3L
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2    (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2            32L  /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2             3L
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2    (1ul <<  0)
+#define PIN_PB22D_SERCOM5_PAD2            54L  /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2             3L
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2    (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2            20L  /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2             2L
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2    (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3            25L  /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3             3L
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3    (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3            33L  /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3             3L
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3    (1ul <<  1)
+#define PIN_PB23D_SERCOM5_PAD3            55L  /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3             3L
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3    (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3            21L  /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3             2L
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3    (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0                 4L  /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0                 4L
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0        (1ul <<  4)
+#define PIN_PA08E_TCC0_WO0                 8L  /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0                 4L
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0        (1ul <<  8)
+#define PIN_PB30E_TCC0_WO0                62L  /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0                 4L
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0        (1ul << 30)
+#define PIN_PA05E_TCC0_WO1                 5L  /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1                 4L
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1        (1ul <<  5)
+#define PIN_PA09E_TCC0_WO1                 9L  /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1                 4L
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1        (1ul <<  9)
+#define PIN_PB31E_TCC0_WO1                63L  /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1                 4L
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1        (1ul << 31)
+#define PIN_PA10F_TCC0_WO2                10L  /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2                 5L
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2        (1ul << 10)
+#define PIN_PA18F_TCC0_WO2                18L  /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2                 5L
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2        (1ul << 18)
+#define PIN_PA11F_TCC0_WO3                11L  /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3                 5L
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3        (1ul << 11)
+#define PIN_PA19F_TCC0_WO3                19L  /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3                 5L
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3        (1ul << 19)
+#define PIN_PA14F_TCC0_WO4                14L  /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4                 5L
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4        (1ul << 14)
+#define PIN_PA22F_TCC0_WO4                22L  /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4                 5L
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4        (1ul << 22)
+#define PIN_PB10F_TCC0_WO4                42L  /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4                 5L
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4        (1ul << 10)
+#define PIN_PB16F_TCC0_WO4                48L  /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4                 5L
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4        (1ul << 16)
+#define PIN_PA15F_TCC0_WO5                15L  /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5                 5L
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5        (1ul << 15)
+#define PIN_PA23F_TCC0_WO5                23L  /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5                 5L
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5        (1ul << 23)
+#define PIN_PB11F_TCC0_WO5                43L  /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5                 5L
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5        (1ul << 11)
+#define PIN_PB17F_TCC0_WO5                49L  /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5                 5L
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5        (1ul << 17)
+#define PIN_PA12F_TCC0_WO6                12L  /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6                 5L
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA20F_TCC0_WO6                20L  /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6                 5L
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6        (1ul << 20)
+#define PIN_PB12F_TCC0_WO6                44L  /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6                 5L
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6        (1ul << 12)
+#define PIN_PA16F_TCC0_WO6                16L  /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6                 5L
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6        (1ul << 16)
+#define PIN_PA13F_TCC0_WO7                13L  /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7                 5L
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA21F_TCC0_WO7                21L  /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7                 5L
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7        (1ul << 21)
+#define PIN_PB13F_TCC0_WO7                45L  /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7                 5L
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7        (1ul << 13)
+#define PIN_PA17F_TCC0_WO7                17L  /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7                 5L
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7        (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0                 6L  /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0                 4L
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0        (1ul <<  6)
+#define PIN_PA10E_TCC1_WO0                10L  /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0                 4L
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0        (1ul << 10)
+#define PIN_PA30E_TCC1_WO0                30L  /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0                 4L
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0        (1ul << 30)
+#define PIN_PA07E_TCC1_WO1                 7L  /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1                 4L
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1        (1ul <<  7)
+#define PIN_PA11E_TCC1_WO1                11L  /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1                 4L
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1        (1ul << 11)
+#define PIN_PA31E_TCC1_WO1                31L  /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1                 4L
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1        (1ul << 31)
+#define PIN_PA08F_TCC1_WO2                 8L  /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2                 5L
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2        (1ul <<  8)
+#define PIN_PA24F_TCC1_WO2                24L  /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2                 5L
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2        (1ul << 24)
+#define PIN_PB30F_TCC1_WO2                62L  /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2                 5L
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2        (1ul << 30)
+#define PIN_PA09F_TCC1_WO3                 9L  /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3                 5L
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3        (1ul <<  9)
+#define PIN_PA25F_TCC1_WO3                25L  /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3                 5L
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3        (1ul << 25)
+#define PIN_PB31F_TCC1_WO3                63L  /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3                 5L
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3        (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0                12L  /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0                 4L
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0        (1ul << 12)
+#define PIN_PA16E_TCC2_WO0                16L  /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0                 4L
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0        (1ul << 16)
+#define PIN_PA00E_TCC2_WO0                 0L  /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0                 4L
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0        (1ul <<  0)
+#define PIN_PA13E_TCC2_WO1                13L  /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1                 4L
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1        (1ul << 13)
+#define PIN_PA17E_TCC2_WO1                17L  /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1                 4L
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1        (1ul << 17)
+#define PIN_PA01E_TCC2_WO1                 1L  /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1                 4L
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1        (1ul <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0                 18L  /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0                  4L
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0         (1ul << 18)
+#define PIN_PA14E_TC3_WO0                 14L  /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0                  4L
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0         (1ul << 14)
+#define PIN_PA19E_TC3_WO1                 19L  /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1                  4L
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1         (1ul << 19)
+#define PIN_PA15E_TC3_WO1                 15L  /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1                  4L
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1         (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0                 22L  /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0                  4L
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0         (1ul << 22)
+#define PIN_PB08E_TC4_WO0                 40L  /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0                  4L
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0         (1ul <<  8)
+#define PIN_PB12E_TC4_WO0                 44L  /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0                  4L
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0         (1ul << 12)
+#define PIN_PA23E_TC4_WO1                 23L  /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1                  4L
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1         (1ul << 23)
+#define PIN_PB09E_TC4_WO1                 41L  /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1                  4L
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1         (1ul <<  9)
+#define PIN_PB13E_TC4_WO1                 45L  /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1                  4L
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1         (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0                 24L  /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0                  4L
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0         (1ul << 24)
+#define PIN_PB10E_TC5_WO0                 42L  /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0                  4L
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0         (1ul << 10)
+#define PIN_PB14E_TC5_WO0                 46L  /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0                  4L
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0         (1ul << 14)
+#define PIN_PA25E_TC5_WO1                 25L  /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1                  4L
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1         (1ul << 25)
+#define PIN_PB11E_TC5_WO1                 43L  /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1                  4L
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1         (1ul << 11)
+#define PIN_PB15E_TC5_WO1                 47L  /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1                  4L
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1         (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0                 34L  /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0                  4L
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0         (1ul <<  2)
+#define PIN_PB16E_TC6_WO0                 48L  /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0                  4L
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0         (1ul << 16)
+#define PIN_PB03E_TC6_WO1                 35L  /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1                  4L
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1         (1ul <<  3)
+#define PIN_PB17E_TC6_WO1                 49L  /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1                  4L
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1         (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0                 20L  /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0                  4L
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0         (1ul << 20)
+#define PIN_PB00E_TC7_WO0                 32L  /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0                  4L
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0         (1ul <<  0)
+#define PIN_PB22E_TC7_WO0                 54L  /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0                  4L
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0         (1ul << 22)
+#define PIN_PA21E_TC7_WO1                 21L  /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1                  4L
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1         (1ul << 21)
+#define PIN_PB01E_TC7_WO1                 33L  /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1                  4L
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1         (1ul <<  1)
+#define PIN_PB23E_TC7_WO1                 55L  /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1                  4L
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1         (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0                 2L  /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0                 1L
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0        (1ul <<  2)
+#define PIN_PA03B_ADC_AIN1                 3L  /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1                 1L
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1        (1ul <<  3)
+#define PIN_PB08B_ADC_AIN2                40L  /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2                 1L
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2        (1ul <<  8)
+#define PIN_PB09B_ADC_AIN3                41L  /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3                 1L
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3        (1ul <<  9)
+#define PIN_PA04B_ADC_AIN4                 4L  /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4                 1L
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4        (1ul <<  4)
+#define PIN_PA05B_ADC_AIN5                 5L  /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5                 1L
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5        (1ul <<  5)
+#define PIN_PA06B_ADC_AIN6                 6L  /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6                 1L
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6        (1ul <<  6)
+#define PIN_PA07B_ADC_AIN7                 7L  /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7                 1L
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7        (1ul <<  7)
+#define PIN_PB00B_ADC_AIN8                32L  /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8                 1L
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8        (1ul <<  0)
+#define PIN_PB01B_ADC_AIN9                33L  /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9                 1L
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9        (1ul <<  1)
+#define PIN_PB02B_ADC_AIN10               34L  /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10                1L
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10       (1ul <<  2)
+#define PIN_PB03B_ADC_AIN11               35L  /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11                1L
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11       (1ul <<  3)
+#define PIN_PB04B_ADC_AIN12               36L  /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12                1L
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12       (1ul <<  4)
+#define PIN_PB05B_ADC_AIN13               37L  /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13                1L
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13       (1ul <<  5)
+#define PIN_PB06B_ADC_AIN14               38L  /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14                1L
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14       (1ul <<  6)
+#define PIN_PB07B_ADC_AIN15               39L  /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15                1L
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15       (1ul <<  7)
+#define PIN_PA08B_ADC_AIN16                8L  /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16                1L
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16       (1ul <<  8)
+#define PIN_PA09B_ADC_AIN17                9L  /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17                1L
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17       (1ul <<  9)
+#define PIN_PA10B_ADC_AIN18               10L  /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18                1L
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18       (1ul << 10)
+#define PIN_PA11B_ADC_AIN19               11L  /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19                1L
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19       (1ul << 11)
+#define PIN_PA04B_ADC_VREFP                4L  /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP                1L
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP       (1ul <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0                  4L  /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0                  1L
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0         (1ul <<  4)
+#define PIN_PA05B_AC_AIN1                  5L  /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1                  1L
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1         (1ul <<  5)
+#define PIN_PA06B_AC_AIN2                  6L  /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2                  1L
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2         (1ul <<  6)
+#define PIN_PA07B_AC_AIN3                  7L  /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3                  1L
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3         (1ul <<  7)
+#define PIN_PA12H_AC_CMP0                 12L  /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0                  7L
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0         (1ul << 12)
+#define PIN_PA18H_AC_CMP0                 18L  /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0                  7L
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0         (1ul << 18)
+#define PIN_PA13H_AC_CMP1                 13L  /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1                  7L
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1         (1ul << 13)
+#define PIN_PA19H_AC_CMP1                 19L  /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1                  7L
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1         (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT                 2L  /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT                 1L
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT        (1ul <<  2)
+#define PIN_PA03B_DAC_VREFP                3L  /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP                1L
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP       (1ul <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0                 11L  /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0                  6L
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0         (1ul << 11)
+#define PIN_PA21G_I2S_FS0                 21L  /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0                  6L
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0         (1ul << 21)
+#define PIN_PB12G_I2S_FS1                 44L  /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1                  6L
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1         (1ul << 12)
+#define PIN_PA09G_I2S_MCK0                 9L  /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0                 6L
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0        (1ul <<  9)
+#define PIN_PB17G_I2S_MCK0                49L  /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0                 6L
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0        (1ul << 17)
+#define PIN_PB10G_I2S_MCK1                42L  /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1                 6L
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1        (1ul << 10)
+#define PIN_PA10G_I2S_SCK0                10L  /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0                 6L
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0        (1ul << 10)
+#define PIN_PA20G_I2S_SCK0                20L  /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0                 6L
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0        (1ul << 20)
+#define PIN_PB11G_I2S_SCK1                43L  /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1                 6L
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1        (1ul << 11)
+#define PIN_PA07G_I2S_SD0                  7L  /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0                  6L
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0         (1ul <<  7)
+#define PIN_PA19G_I2S_SD0                 19L  /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0                  6L
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0         (1ul << 19)
+#define PIN_PA08G_I2S_SD1                  8L  /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1                  6L
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1         (1ul <<  8)
+#define PIN_PB16G_I2S_SD1                 48L  /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1                  6L
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1         (1ul << 16)
+
+#endif /* _SAMD21J18A_PIO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h
index c9905b7..8a1121d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h
@@ -1,113 +1,113 @@
-/**
- * \file
- *
- * \brief Top header file for SAMD21
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAMD21_
-#define _SAMD21_
-
-/**
- * \defgroup SAMD21_definitions SAMD21 Device Definitions
- * \brief SAMD21 CMSIS Definitions.
- */
-
-#if   defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
-  #include "samd21e15a.h"
-#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
-  #include "samd21e16a.h"
-#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
-  #include "samd21e17a.h"
-#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
-  #include "samd21e18a.h"
-#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
-  #include "samd21g15a.h"
-#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
-  #include "samd21g16a.h"
-#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
-  #include "samd21g17a.h"
-#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
-  #include "samd21g17au.h"
-#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
-  #include "samd21g18a.h"
-#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
-  #include "samd21g18au.h"
-#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
-  #include "samd21j15a.h"
-#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
-  #include "samd21j16a.h"
-#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
-  #include "samd21j17a.h"
-#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
-  #include "samd21j18a.h"
-#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__)
-  #include "samd21e15b.h"
-#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__)
-  #include "samd21e15bu.h"
-#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__)
-  #include "samd21e15l.h"
-#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__)
-  #include "samd21e16b.h"
-#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__)
-  #include "samd21e16bu.h"
-#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__)
-  #include "samd21e16l.h"
-#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__)
-  #include "samd21g15b.h"
-#elif defined(__SAMD21G15L__) || defined(__ATSAMD21G15L__)
-  #include "samd21g15l.h"
-#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__)
-  #include "samd21g16b.h"
-#elif defined(__SAMD21G16L__) || defined(__ATSAMD21G16L__)
-  #include "samd21g16l.h"
-#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__)
-  #include "samd21j15b.h"
-#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__)
-  #include "samd21j16b.h"
-#elif defined(__SAMD21E17D__) || defined(__ATSAMD21E17D__)
-  #include "samd21e17d.h"
-#elif defined(__SAMD21E17DU__) || defined(__ATSAMD21E17DU__)
-  #include "samd21e17du.h"
-#elif defined(__SAMD21E17L__) || defined(__ATSAMD21E17L__)
-  #include "samd21e17l.h"
-#elif defined(__SAMD21G17D__) || defined(__ATSAMD21G17D__)
-  #include "samd21g17d.h"
-#elif defined(__SAMD21G17L__) || defined(__ATSAMD21G17L__)
-  #include "samd21g17l.h"
-#elif defined(__SAMD21J17D__) || defined(__ATSAMD21J17D__)
-  #include "samd21j17d.h"
-#else
-  #error Library does not support the specified device.
-#endif
-
-#endif /* _SAMD21_ */
+/**
+ * \file
+ *
+ * \brief Top header file for SAMD21
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAMD21_
+#define _SAMD21_
+
+/**
+ * \defgroup SAMD21_definitions SAMD21 Device Definitions
+ * \brief SAMD21 CMSIS Definitions.
+ */
+
+#if   defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
+  #include "samd21e15a.h"
+#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
+  #include "samd21e16a.h"
+#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
+  #include "samd21e17a.h"
+#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
+  #include "samd21e18a.h"
+#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
+  #include "samd21g15a.h"
+#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
+  #include "samd21g16a.h"
+#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
+  #include "samd21g17a.h"
+#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
+  #include "samd21g17au.h"
+#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
+  #include "samd21g18a.h"
+#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
+  #include "samd21g18au.h"
+#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
+  #include "samd21j15a.h"
+#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
+  #include "samd21j16a.h"
+#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
+  #include "samd21j17a.h"
+#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
+  #include "samd21j18a.h"
+#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__)
+  #include "samd21e15b.h"
+#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__)
+  #include "samd21e15bu.h"
+#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__)
+  #include "samd21e15l.h"
+#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__)
+  #include "samd21e16b.h"
+#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__)
+  #include "samd21e16bu.h"
+#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__)
+  #include "samd21e16l.h"
+#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__)
+  #include "samd21g15b.h"
+#elif defined(__SAMD21G15L__) || defined(__ATSAMD21G15L__)
+  #include "samd21g15l.h"
+#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__)
+  #include "samd21g16b.h"
+#elif defined(__SAMD21G16L__) || defined(__ATSAMD21G16L__)
+  #include "samd21g16l.h"
+#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__)
+  #include "samd21j15b.h"
+#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__)
+  #include "samd21j16b.h"
+#elif defined(__SAMD21E17D__) || defined(__ATSAMD21E17D__)
+  #include "samd21e17d.h"
+#elif defined(__SAMD21E17DU__) || defined(__ATSAMD21E17DU__)
+  #include "samd21e17du.h"
+#elif defined(__SAMD21E17L__) || defined(__ATSAMD21E17L__)
+  #include "samd21e17l.h"
+#elif defined(__SAMD21G17D__) || defined(__ATSAMD21G17D__)
+  #include "samd21g17d.h"
+#elif defined(__SAMD21G17L__) || defined(__ATSAMD21G17L__)
+  #include "samd21g17l.h"
+#elif defined(__SAMD21J17D__) || defined(__ATSAMD21J17D__)
+  #include "samd21j17d.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAMD21_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h
index 2448e72..a2b99a1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h
@@ -1,547 +1,547 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E15A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15A_
-#define _SAMD21E15A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
- * This file defines all structures and symbols for SAMD21E15A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E15A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E15A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E15A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E15A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E15A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E15A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E15A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E15A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e15a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001000DUL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E15A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E15A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_
+#define _SAMD21E15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
+ * This file defines all structures and symbols for SAMD21E15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000DUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15b.h
index ebab4f3..4a1f200 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15b.h
@@ -1,551 +1,551 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E15B
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15B_
-#define _SAMD21E15B_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E15B_definitions SAMD21E15B definitions
- * This file defines all structures and symbols for SAMD21E15B:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15B_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E15B-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E15B Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15B System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E15B Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E15B Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E15B External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E15B Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E15B Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E15B Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E15B Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15B_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15B_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15B_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15B_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15B_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e15b.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011427UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
-#define PORT_GROUPS           1
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E15B */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E15B_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15B
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15B_
+#define _SAMD21E15B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15B_definitions SAMD21E15B definitions
+ * This file defines all structures and symbols for SAMD21E15B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011427UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15B_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15bu.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15bu.h
index fca4bbc..0349e17 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15bu.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15bu.h
@@ -1,551 +1,551 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E15BU
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15BU_
-#define _SAMD21E15BU_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E15BU_definitions SAMD21E15BU definitions
- * This file defines all structures and symbols for SAMD21E15BU:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15BU_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E15BU-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E15BU Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15BU System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E15BU Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E15BU Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E15BU External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E15BU Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E15BU Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E15BU Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15BU_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15BU_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15BU_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15BU_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15BU_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e15bu.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011456UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
-#define PORT_GROUPS           1
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E15BU */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E15BU_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15BU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15BU_
+#define _SAMD21E15BU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15BU_definitions SAMD21E15BU definitions
+ * This file defines all structures and symbols for SAMD21E15BU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15BU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15BU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15BU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15BU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15BU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15BU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15BU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15BU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15BU Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15BU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15bu.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011456UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15BU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15BU_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15l.h
index 8346456..f49e0b8 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15l.h
@@ -1,530 +1,530 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E15L
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E15L_
-#define _SAMD21E15L_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E15L_definitions SAMD21E15L definitions
- * This file defines all structures and symbols for SAMD21E15L:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15L_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E15L-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E15L Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15L System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E15L Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E15L Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E15L External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E15L Direct Memory Access Controller (DMAC) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E15L Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E15L Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
-  AC1_IRQn                 = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pvReserved7;
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pvReserved26;
-  void* pvReserved27;
-  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void AC1_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15L_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_lighting.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15L_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/ac1.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15L_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
-
-#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15L_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E15L_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e15l.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001143FUL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              0
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E15L */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E15L_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15L
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15L_
+#define _SAMD21E15L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15L_definitions SAMD21E15L definitions
+ * This file defines all structures and symbols for SAMD21E15L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001143FUL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15L_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h
index 042dde0..5da96f2 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h
@@ -1,547 +1,547 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E16A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16A_
-#define _SAMD21E16A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
- * This file defines all structures and symbols for SAMD21E16A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E16A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E16A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E16A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E16A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E16A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E16A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E16A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E16A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e16a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001000CUL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E16A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E16A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_
+#define _SAMD21E16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
+ * This file defines all structures and symbols for SAMD21E16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000CUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16b.h
index e5c7031..913fa27 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16b.h
@@ -1,551 +1,551 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E16B
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16B_
-#define _SAMD21E16B_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E16B_definitions SAMD21E16B definitions
- * This file defines all structures and symbols for SAMD21E16B:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16B_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E16B-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E16B Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16B System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E16B Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E16B Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E16B External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E16B Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E16B Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E16B Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E16B Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16B_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16B_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16B_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16B_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16B_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e16b.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011426UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
-#define PORT_GROUPS           1
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E16B */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E16B_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16B
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16B_
+#define _SAMD21E16B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16B_definitions SAMD21E16B definitions
+ * This file defines all structures and symbols for SAMD21E16B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011426UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16B_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16bu.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16bu.h
index a539c9c..6bce239 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16bu.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16bu.h
@@ -1,551 +1,551 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E16BU
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16BU_
-#define _SAMD21E16BU_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E16BU_definitions SAMD21E16BU definitions
- * This file defines all structures and symbols for SAMD21E16BU:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16BU_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E16BU-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E16BU Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16BU System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E16BU Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E16BU Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E16BU External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E16BU Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E16BU Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E16BU Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16BU_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16BU_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16BU_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16BU_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16BU_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e16bu.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011455UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
-#define PORT_GROUPS           1
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E16BU */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E16BU_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16BU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16BU_
+#define _SAMD21E16BU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16BU_definitions SAMD21E16BU definitions
+ * This file defines all structures and symbols for SAMD21E16BU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16BU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16BU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16BU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16BU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16BU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16BU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16BU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16BU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16BU Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16BU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16bu.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011455UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16BU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16BU_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16l.h
index 57f4978..7511e66 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16l.h
@@ -1,530 +1,530 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E16L
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E16L_
-#define _SAMD21E16L_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E16L_definitions SAMD21E16L definitions
- * This file defines all structures and symbols for SAMD21E16L:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16L_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E16L-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E16L Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16L System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E16L Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E16L Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E16L External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E16L Direct Memory Access Controller (DMAC) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E16L Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E16L Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
-  AC1_IRQn                 = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pvReserved7;
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pvReserved26;
-  void* pvReserved27;
-  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void AC1_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16L_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_lighting.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16L_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/ac1.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16L_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
-
-#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16L_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E16L_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e16l.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001143EUL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              0
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E16L */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E16L_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16L
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16L_
+#define _SAMD21E16L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16L_definitions SAMD21E16L definitions
+ * This file defines all structures and symbols for SAMD21E16L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001143EUL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16L_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h
index 1d9db3d..356a579 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h
@@ -1,547 +1,547 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E17A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E17A_
-#define _SAMD21E17A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
- * This file defines all structures and symbols for SAMD21E17A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E17A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E17A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E17A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E17A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E17A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E17A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E17A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E17A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e17a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x20000UL /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001000BUL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E17A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E17A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_
+#define _SAMD21E17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
+ * This file defines all structures and symbols for SAMD21E17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000BUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17d.h
index 3dcd735..16c6cb8 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17d.h
@@ -1,574 +1,574 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E17D
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E17D_
-#define _SAMD21E17D_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E17D_definitions SAMD21E17D definitions
- * This file defines all structures and symbols for SAMD21E17D:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17D_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E17D-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E17D Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17D System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E17D Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E17D Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E17D External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17D Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E17D Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E17D Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E17D Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17D Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17D Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17D Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17D Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E17D Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E17D Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E17D Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E17D Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E17D Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E17D Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E17D Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E17D Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E17D Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E17D Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E17D Inter-IC Sound Interface (I2S) */
-  TCC3_IRQn                = 29, /**< 29 SAMD21E17D Timer Counter Control 3 (TCC3) */
-
-  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-void TCC3_Handler                ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17D_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys_variant_d.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl_variant_d.h"
-#include "component/pac.h"
-#include "component/pm_variant_d.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_variant_d.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17D_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys_variant_d.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl_variant_d.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port_variant_d.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17D_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
-
-#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17D_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
-#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
-#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
-#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
-#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
-
-#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17D_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e17d.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x10012694)
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
-#define PORT_GROUPS           1
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E17D */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E17D_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17D
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17D_
+#define _SAMD21E17D_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17D_definitions SAMD21E17D definitions
+ * This file defines all structures and symbols for SAMD21E17D:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17D_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E17D-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E17D Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17D System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E17D Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E17D Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E17D External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17D Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E17D Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E17D Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E17D Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17D Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17D Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17D Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17D Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E17D Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E17D Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E17D Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E17D Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E17D Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E17D Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E17D Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E17D Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E17D Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E17D Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E17D Inter-IC Sound Interface (I2S) */
+  TCC3_IRQn                = 29, /**< 29 SAMD21E17D Timer Counter Control 3 (TCC3) */
+
+  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+void TCC3_Handler                ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17D_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys_variant_d.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl_variant_d.h"
+#include "component/pac.h"
+#include "component/pm_variant_d.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_variant_d.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17D_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys_variant_d.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl_variant_d.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port_variant_d.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17D_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
+
+#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17D_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17D_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17d.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x10012694)
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E17D */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17D_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17du.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17du.h
index 419b57b..364e3ae 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17du.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17du.h
@@ -1,574 +1,574 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E17DU
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E17DU_
-#define _SAMD21E17DU_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E17DU_definitions SAMD21E17DU definitions
- * This file defines all structures and symbols for SAMD21E17DU:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17DU_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E17DU-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E17DU Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17DU System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E17DU Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E17DU Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E17DU External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17DU Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E17DU Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E17DU Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E17DU Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17DU Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17DU Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17DU Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17DU Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E17DU Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E17DU Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E17DU Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E17DU Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E17DU Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E17DU Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E17DU Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E17DU Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E17DU Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E17DU Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E17DU Inter-IC Sound Interface (I2S) */
-  TCC3_IRQn                = 29, /**< 29 SAMD21E17DU Timer Counter Control 3 (TCC3) */
-
-  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-void TCC3_Handler                ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17DU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17DU_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys_variant_d.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl_variant_d.h"
-#include "component/pac.h"
-#include "component/pm_variant_d.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_variant_d.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17DU_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys_variant_d.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl_variant_d.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port_variant_d.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17DU_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
-
-#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17DU_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
-#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
-#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
-#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
-#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
-
-#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17DU_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e17du.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x10012695)
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
-#define PORT_GROUPS           1
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E17DU */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E17DU_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17DU
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17DU_
+#define _SAMD21E17DU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17DU_definitions SAMD21E17DU definitions
+ * This file defines all structures and symbols for SAMD21E17DU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17DU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E17DU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E17DU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17DU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E17DU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E17DU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E17DU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17DU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E17DU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E17DU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E17DU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17DU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17DU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17DU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17DU Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E17DU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E17DU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E17DU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E17DU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E17DU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E17DU Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E17DU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E17DU Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E17DU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E17DU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E17DU Inter-IC Sound Interface (I2S) */
+  TCC3_IRQn                = 29, /**< 29 SAMD21E17DU Timer Counter Control 3 (TCC3) */
+
+  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+void TCC3_Handler                ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17DU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17DU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys_variant_d.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl_variant_d.h"
+#include "component/pac.h"
+#include "component/pm_variant_d.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_variant_d.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17DU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys_variant_d.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl_variant_d.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port_variant_d.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17DU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
+
+#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17DU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17DU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17du.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x10012695)
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
+#define PORT_GROUPS           1
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E17DU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17DU_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17l.h
index 47e0350..b5c2b83 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17l.h
@@ -1,551 +1,551 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E17L
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E17L_
-#define _SAMD21E17L_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E17L_definitions SAMD21E17L definitions
- * This file defines all structures and symbols for SAMD21E17L:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17L_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E17L-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E17L Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17L System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E17L Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E17L Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E17L External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17L Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E17L Direct Memory Access Controller (DMAC) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E17L Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17L Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17L Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17L Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17L Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E17L Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E17L Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E17L Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E17L Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E17L Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E17L Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E17L Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E17L Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E17L Digital Analog Converter (DAC) */
-  AC1_IRQn                 = 28, /**< 28 SAMD21E17L Analog Comparators 1 (AC1) */
-  TCC3_IRQn                = 29, /**< 29 SAMD21E17L Timer Counter Control 3 (TCC3) */
-
-  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pvReserved7;
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pvReserved26;
-  void* pvReserved27;
-  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
-  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void AC1_Handler                 ( void );
-void TCC3_Handler                ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17L_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys_variant_d.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/mtb.h"
-#include "component/nvmctrl_variant_d.h"
-#include "component/pac.h"
-#include "component/pm_variant_d.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_lighting.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17L_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/ac1.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys_variant_d.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl_variant_d.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port_variant_d.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17L_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
-#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
-
-#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17L_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
-#define AC1                           (0x42005400) /**< \brief (AC1) APB Base Address */
-#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
-#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
-#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
-#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21E17L_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e17l.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x10012697)
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              0
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E17L */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E17L_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17L
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17L_
+#define _SAMD21E17L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17L_definitions SAMD21E17L definitions
+ * This file defines all structures and symbols for SAMD21E17L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E17L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E17L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E17L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E17L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E17L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E17L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E17L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17L Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E17L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E17L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E17L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E17L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E17L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E17L Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E17L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E17L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E17L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21E17L Analog Comparators 1 (AC1) */
+  TCC3_IRQn                = 29, /**< 29 SAMD21E17L Timer Counter Control 3 (TCC3) */
+
+  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+void TCC3_Handler                ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys_variant_d.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl_variant_d.h"
+#include "component/pac.h"
+#include "component/pm_variant_d.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys_variant_d.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl_variant_d.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port_variant_d.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
+
+#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x10012697)
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E17L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17L_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h
index 6e52322..c6f6a3d 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h
@@ -1,547 +1,547 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21E18A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21E18A_
-#define _SAMD21E18A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
- * This file defines all structures and symbols for SAMD21E18A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21E18A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21E18A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E18A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21E18A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21E18A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21E18A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21E18A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21E18A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21E18A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pvReserved13;
-  void* pvReserved14;
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E18A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E18A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21E18A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21e18a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x40000UL /* 256 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     4096
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001000AUL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21E18A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21E18A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E18A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_
+#define _SAMD21E18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
+ * This file defines all structures and symbols for SAMD21E18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000AUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E18A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h
index 9257f68..6daafbd 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h
@@ -1,559 +1,559 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G15A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G15A_
-#define _SAMD21G15A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
- * This file defines all structures and symbols for SAMD21G15A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G15A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G15A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G15A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G15A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G15A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G15A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G15A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G15A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g15a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010008UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G15A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G15A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_
+#define _SAMD21G15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
+ * This file defines all structures and symbols for SAMD21G15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010008UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15b.h
index 041b54d..94bed1e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15b.h
@@ -1,563 +1,563 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G15B
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G15B_
-#define _SAMD21G15B_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G15B_definitions SAMD21G15B definitions
- * This file defines all structures and symbols for SAMD21G15B:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15B_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G15B-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G15B Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15B System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G15B Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G15B Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G15B External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G15B Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G15B Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G15B Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G15B Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15B_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15B_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15B_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15B_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15B_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g15b.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011424UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G15B */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G15B_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15B
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15B_
+#define _SAMD21G15B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15B_definitions SAMD21G15B definitions
+ * This file defines all structures and symbols for SAMD21G15B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G15B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011424UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15B_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15l.h
index 65f3645..0d22ea7 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15l.h
@@ -1,554 +1,554 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G15L
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G15L_
-#define _SAMD21G15L_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G15L_definitions SAMD21G15L definitions
- * This file defines all structures and symbols for SAMD21G15L:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15L_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G15L-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G15L Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15L System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G15L Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G15L Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G15L External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15L Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G15L Direct Memory Access Controller (DMAC) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G15L Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15L Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15L Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15L Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15L Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15L Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15L Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G15L Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G15L Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G15L Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G15L Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G15L Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G15L Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21G15L Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21G15L Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G15L Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G15L Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G15L Digital Analog Converter (DAC) */
-  AC1_IRQn                 = 28, /**< 28 SAMD21G15L Analog Comparators 1 (AC1) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pvReserved7;
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pvReserved26;
-  void* pvReserved27;
-  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void AC1_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15L_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_lighting.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15L_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/ac1.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15L_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
-
-#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15L_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G15L_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g15l.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011458UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              0
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G15L */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G15L_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15L
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15L_
+#define _SAMD21G15L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15L_definitions SAMD21G15L definitions
+ * This file defines all structures and symbols for SAMD21G15L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15L Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15L Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15L Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15L Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G15L Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G15L Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21G15L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011458UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15L_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h
index 1513991..7221652 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h
@@ -1,559 +1,559 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G16A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G16A_
-#define _SAMD21G16A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
- * This file defines all structures and symbols for SAMD21G16A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G16A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G16A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G16A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G16A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G16A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G16A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G16A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G16A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g16a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010007UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G16A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G16A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_
+#define _SAMD21G16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
+ * This file defines all structures and symbols for SAMD21G16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010007UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16b.h
index 55889e7..80af752 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16b.h
@@ -1,563 +1,563 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G16B
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G16B_
-#define _SAMD21G16B_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G16B_definitions SAMD21G16B definitions
- * This file defines all structures and symbols for SAMD21G16B:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16B_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G16B-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G16B Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16B System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G16B Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G16B Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G16B External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G16B Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G16B Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G16B Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G16B Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16B_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16B_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16B_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16B_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16B_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g16b.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011423UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G16B */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G16B_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16B
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16B_
+#define _SAMD21G16B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16B_definitions SAMD21G16B definitions
+ * This file defines all structures and symbols for SAMD21G16B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G16B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011423UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16B_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16l.h
index 7eef278..0447bdf 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16l.h
@@ -1,554 +1,554 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G16L
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G16L_
-#define _SAMD21G16L_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G16L_definitions SAMD21G16L definitions
- * This file defines all structures and symbols for SAMD21G16L:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16L_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G16L-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G16L Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16L System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G16L Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G16L Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G16L External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16L Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G16L Direct Memory Access Controller (DMAC) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G16L Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16L Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16L Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16L Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16L Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16L Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16L Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G16L Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G16L Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G16L Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G16L Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G16L Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G16L Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21G16L Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21G16L Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G16L Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G16L Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G16L Digital Analog Converter (DAC) */
-  AC1_IRQn                 = 28, /**< 28 SAMD21G16L Analog Comparators 1 (AC1) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pvReserved7;
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pvReserved26;
-  void* pvReserved27;
-  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void AC1_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16L_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_lighting.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16L_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/ac1.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16L_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
-
-#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16L_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G16L_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g16l.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011457UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              0
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G16L */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G16L_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16L
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16L_
+#define _SAMD21G16L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16L_definitions SAMD21G16L definitions
+ * This file defines all structures and symbols for SAMD21G16L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16L Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16L Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16L Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16L Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G16L Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G16L Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21G16L Analog Comparators 1 (AC1) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+
+#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011457UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16L_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h
index e85c4c7..502f955 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h
@@ -1,559 +1,559 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G17A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G17A_
-#define _SAMD21G17A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
- * This file defines all structures and symbols for SAMD21G17A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G17A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G17A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G17A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G17A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G17A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G17A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G17A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G17A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g17a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x20000UL /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010006UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G17A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G17A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_
+#define _SAMD21G17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
+ * This file defines all structures and symbols for SAMD21G17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010006UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17au.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17au.h
index 192c332..b2f4957 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17au.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17au.h
@@ -1,571 +1,571 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G17AU
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G17AU_
-#define _SAMD21G17AU_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions
- * This file defines all structures and symbols for SAMD21G17AU:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G17AU-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G17AU Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17AU System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G17AU Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G17AU Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G17AU External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G17AU Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G17AU Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17AU_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17AU_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17AU_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g17au.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x20000UL /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010010UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G17AU */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G17AU_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17AU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_
+#define _SAMD21G17AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions
+ * This file defines all structures and symbols for SAMD21G17AU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17AU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17AU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17AU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17AU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17AU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17AU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17AU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17AU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010010UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17AU_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17d.h
index 2d4fb6e..724aaf1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17d.h
@@ -1,586 +1,586 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G17D
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G17D_
-#define _SAMD21G17D_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G17D_definitions SAMD21G17D definitions
- * This file defines all structures and symbols for SAMD21G17D:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17D_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G17D-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G17D Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17D System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G17D Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G17D Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G17D External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17D Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G17D Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G17D Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G17D Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17D Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17D Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17D Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17D Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17D Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17D Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G17D Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G17D Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G17D Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G17D Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G17D Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G17D Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G17D Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G17D Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G17D Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G17D Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G17D Inter-IC Sound Interface (I2S) */
-  TCC3_IRQn                = 29, /**< 29 SAMD21G17D Timer Counter Control 3 (TCC3) */
-
-  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-void TCC3_Handler                ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17D_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys_variant_d.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl_variant_d.h"
-#include "component/pac.h"
-#include "component/pm_variant_d.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_variant_d.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17D_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys_variant_d.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl_variant_d.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port_variant_d.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17D_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
-
-#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17D_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
-#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
-#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
-#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
-#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
-
-#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17D_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g17d.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x10012693)
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G17D */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G17D_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17D
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17D_
+#define _SAMD21G17D_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17D_definitions SAMD21G17D definitions
+ * This file defines all structures and symbols for SAMD21G17D:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17D_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17D-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17D Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17D System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17D Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17D Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17D External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17D Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17D Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17D Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17D Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17D Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17D Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17D Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17D Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17D Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17D Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17D Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17D Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17D Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17D Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17D Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17D Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17D Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17D Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17D Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17D Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17D Inter-IC Sound Interface (I2S) */
+  TCC3_IRQn                = 29, /**< 29 SAMD21G17D Timer Counter Control 3 (TCC3) */
+
+  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+void TCC3_Handler                ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17D_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys_variant_d.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl_variant_d.h"
+#include "component/pac.h"
+#include "component/pm_variant_d.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_variant_d.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17D_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys_variant_d.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl_variant_d.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port_variant_d.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17D_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
+
+#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17D_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17D_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17d.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x10012693)
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17D */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17D_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17l.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17l.h
index ec18829..ba41d85 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17l.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17l.h
@@ -1,575 +1,575 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G17L
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G17L_
-#define _SAMD21G17L_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G17L_definitions SAMD21G17L definitions
- * This file defines all structures and symbols for SAMD21G17L:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17L_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G17L-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G17L Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17L System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G17L Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G17L Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G17L External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17L Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G17L Direct Memory Access Controller (DMAC) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G17L Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17L Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17L Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17L Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17L Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17L Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17L Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G17L Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G17L Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G17L Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G17L Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G17L Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G17L Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21G17L Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21G17L Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G17L Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G17L Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G17L Digital Analog Converter (DAC) */
-  AC1_IRQn                 = 28, /**< 28 SAMD21G17L Analog Comparators 1 (AC1) */
-  TCC3_IRQn                = 29, /**< 29 SAMD21G17L Timer Counter Control 3 (TCC3) */
-
-  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pvReserved7;
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pvReserved26;
-  void* pvReserved27;
-  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
-  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void AC1_Handler                 ( void );
-void TCC3_Handler                ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17L_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys_variant_d.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/mtb.h"
-#include "component/nvmctrl_variant_d.h"
-#include "component/pac.h"
-#include "component/pm_variant_d.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_lighting.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17L_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/ac1.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys_variant_d.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl_variant_d.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port_variant_d.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17L_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
-#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
-
-#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17L_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
-#define AC1                           (0x42005400) /**< \brief (AC1) APB Base Address */
-#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
-#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
-#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
-#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
-#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-/** \defgroup SAMD21G17L_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g17l.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x10012696)
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              0
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G17L */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G17L_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17L
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17L_
+#define _SAMD21G17L_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17L_definitions SAMD21G17L definitions
+ * This file defines all structures and symbols for SAMD21G17L:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17L_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17L-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17L Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17L System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17L Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17L Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17L External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17L Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17L Direct Memory Access Controller (DMAC) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17L Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17L Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17L Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17L Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17L Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17L Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17L Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17L Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17L Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17L Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17L Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17L Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17L Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G17L Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G17L Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17L Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17L Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17L Digital Analog Converter (DAC) */
+  AC1_IRQn                 = 28, /**< 28 SAMD21G17L Analog Comparators 1 (AC1) */
+  TCC3_IRQn                = 29, /**< 29 SAMD21G17L Timer Counter Control 3 (TCC3) */
+
+  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pvReserved7;
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pfnAC1_Handler;                   /* 28 Analog Comparators 1 */
+  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void AC1_Handler                 ( void );
+void TCC3_Handler                ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17L_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys_variant_d.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/mtb.h"
+#include "component/nvmctrl_variant_d.h"
+#include "component/pac.h"
+#include "component/pm_variant_d.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_lighting.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17L_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/ac1.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys_variant_d.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl_variant_d.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port_variant_d.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17L_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_AC1           85 /**< \brief Analog Comparators 1 (AC1) */
+#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
+
+#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17L_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define AC1                           (0x42005400) /**< \brief (AC1) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC1               ((Ac       *)0x42005400UL) /**< \brief (AC1) APB Base Address */
+#define AC_INST_NUM       2                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC, AC1 }                /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17L_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17l.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x10012696)
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              0
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17L */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17L_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h
index f03f09e..192800c 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h
@@ -1,559 +1,559 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G18A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G18A_
-#define _SAMD21G18A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
- * This file defines all structures and symbols for SAMD21G18A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G18A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G18A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G18A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G18A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G18A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G18A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G18A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G18A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pvReserved21;
-  void* pvReserved22;
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g18a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x40000UL /* 256 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     4096
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010005UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G18A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G18A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_
+#define _SAMD21G18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
+ * This file defines all structures and symbols for SAMD21G18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010005UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18au.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18au.h
index 08b694e..2a8915a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18au.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18au.h
@@ -1,571 +1,571 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21G18AU
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21G18AU_
-#define _SAMD21G18AU_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions
- * This file defines all structures and symbols for SAMD21G18AU:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21G18AU-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21G18AU Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18AU System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21G18AU Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21G18AU Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21G18AU External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21G18AU Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21G18AU Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18AU_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18AU_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-/** \defgroup SAMD21G18AU_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21g18au.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x40000UL /* 256 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     4096
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x1001000FUL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21G18AU */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21G18AU_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18AU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_
+#define _SAMD21G18AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions
+ * This file defines all structures and symbols for SAMD21G18AU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G18AU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G18AU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18AU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G18AU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G18AU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G18AU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G18AU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G18AU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x1001000FUL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18AU_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h
index 8790b53..b379244 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h
@@ -1,571 +1,571 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J15A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J15A_
-#define _SAMD21J15A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
- * This file defines all structures and symbols for SAMD21J15A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J15A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J15A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J15A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J15A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J15A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J15A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J15A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J15A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j15a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010003UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J15A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J15A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_
+#define _SAMD21J15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
+ * This file defines all structures and symbols for SAMD21J15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010003UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15b.h
index 19b0266..0aa1dc1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15b.h
@@ -1,575 +1,575 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J15B
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J15B_
-#define _SAMD21J15B_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J15B_definitions SAMD21J15B definitions
- * This file defines all structures and symbols for SAMD21J15B:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15B_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J15B-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J15B Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15B System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J15B Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J15B Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J15B External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J15B Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J15B Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J15B Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J15B Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15B_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15B_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15B_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15B_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J15B_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j15b.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x8000UL /* 32 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011421UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J15B */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J15B_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15B
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15B_
+#define _SAMD21J15B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15B_definitions SAMD21J15B definitions
+ * This file defines all structures and symbols for SAMD21J15B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J15B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J15B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J15B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J15B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J15B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J15B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J15B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J15B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J15B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x1000UL /* 4 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011421UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J15B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15B_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h
index 687a262..ae39701 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h
@@ -1,571 +1,571 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J16A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J16A_
-#define _SAMD21J16A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
- * This file defines all structures and symbols for SAMD21J16A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J16A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J16A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J16A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J16A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J16A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J16A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J16A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J16A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j16a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010002UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J16A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J16A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_
+#define _SAMD21J16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
+ * This file defines all structures and symbols for SAMD21J16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010002UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16b.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16b.h
index 1f2c069..5766e93 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16b.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16b.h
@@ -1,575 +1,575 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J16B
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J16B_
-#define _SAMD21J16B_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J16B_definitions SAMD21J16B definitions
- * This file defines all structures and symbols for SAMD21J16B:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16B_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J16B-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J16B Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16B System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J16B Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J16B Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J16B External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J16B Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J16B Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J16B Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J16B Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16B_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16B_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16B_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16B_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-/** \defgroup SAMD21J16B_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j16b.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x10000UL /* 64 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     1024
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10011420UL
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J16B */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J16B_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16B
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16B_
+#define _SAMD21J16B_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16B_definitions SAMD21J16B definitions
+ * This file defines all structures and symbols for SAMD21J16B:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J16B-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J16B Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16B System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J16B Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J16B Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J16B External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J16B Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J16B Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J16B Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J16B Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 29  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16B_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x2000UL /* 8 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10011420UL
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J16B */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16B_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h
index d8d3f1d..a8e8c50 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h
@@ -1,571 +1,571 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J17A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J17A_
-#define _SAMD21J17A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
- * This file defines all structures and symbols for SAMD21J17A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J17A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J17A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J17A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J17A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J17A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J17A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J17A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J17A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J17A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j17a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x20000UL /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010001UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J17A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J17A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_
+#define _SAMD21J17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
+ * This file defines all structures and symbols for SAMD21J17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x4000UL /* 16 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010001UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17d.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17d.h
index 7f181ab..148f5e1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17d.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17d.h
@@ -1,598 +1,598 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J17D
- *
- * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J17D_
-#define _SAMD21J17D_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J17D_definitions SAMD21J17D definitions
- * This file defines all structures and symbols for SAMD21J17D:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17D_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J17D-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J17D Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J17D System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J17D Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J17D Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J17D External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J17D Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J17D Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J17D Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J17D Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J17D Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J17D Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J17D Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J17D Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J17D Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J17D Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J17D Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J17D Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J17D Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J17D Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J17D Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J17D Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J17D Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J17D Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J17D Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J17D Analog Comparators  (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J17D Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J17D Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J17D Inter-IC Sound Interface (I2S) */
-  TCC3_IRQn                = 29, /**< 29 SAMD21J17D Timer Counter Control 3 (TCC3) */
-
-  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-void TCC3_Handler                ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17D_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys_variant_d.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl_variant_d.h"
-#include "component/pac.h"
-#include "component/pm_variant_d.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc_variant_d.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17D_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys_variant_d.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl_variant_d.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port_variant_d.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17D_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
-
-#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17D_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
-#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
-#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
-#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
-#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
-
-#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-/** \defgroup SAMD21J17D_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j17d.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     2048
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x10012692)
-#define EIC_EXTINT_NUM        16
-#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
-#define PORT_GROUPS           2
-#define USB_HOST              1
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J17D */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J17D_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17D
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17D_
+#define _SAMD21J17D_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17D_definitions SAMD21J17D definitions
+ * This file defines all structures and symbols for SAMD21J17D:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17D_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J17D-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J17D Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J17D System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J17D Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J17D Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J17D External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J17D Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J17D Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J17D Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J17D Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J17D Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J17D Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J17D Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J17D Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J17D Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J17D Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J17D Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J17D Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J17D Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J17D Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J17D Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J17D Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J17D Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J17D Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J17D Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J17D Analog Comparators  (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J17D Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J17D Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J17D Inter-IC Sound Interface (I2S) */
+  TCC3_IRQn                = 29, /**< 29 SAMD21J17D Timer Counter Control 3 (TCC3) */
+
+  PERIPH_COUNT_IRQn        = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators  */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+  void* pfnTCC3_Handler;                  /* 29 Timer Counter Control 3 */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+void TCC3_Handler                ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17D_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys_variant_d.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl_variant_d.h"
+#include "component/pac.h"
+#include "component/pm_variant_d.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc_variant_d.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17D_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys_variant_d.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl_variant_d.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port_variant_d.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17D_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators  (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_TCC3          88 /**< \brief Timer Counter Control 3 (TCC3) */
+
+#define ID_PERIPH_COUNT  89 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17D_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL_AUX3                  (0x0080A000) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42006000) /**< \brief (TCC3) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL_AUX3                  (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17D_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17d.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL_(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL_(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x10012692)
+#define EIC_EXTINT_NUM        16
+#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
+#define PORT_GROUPS           2
+#define USB_HOST              1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J17D */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17D_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h
index c6a3ffd..d155327 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h
@@ -1,571 +1,571 @@
-/**
- * \file
- *
- * \brief Header file for SAMD21J18A
- *
- * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD21J18A_
-#define _SAMD21J18A_
-
-/**
- * \ingroup SAMD21_definitions
- * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
- * This file defines all structures and symbols for SAMD21J18A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *)(value))
-#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
-  /******  SAMD21J18A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD21J18A Power Manager (PM) */
-  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J18A System Control (SYSCTRL) */
-  WDT_IRQn                 =  2, /**<  2 SAMD21J18A Watchdog Timer (WDT) */
-  RTC_IRQn                 =  3, /**<  3 SAMD21J18A Real-Time Counter (RTC) */
-  EIC_IRQn                 =  4, /**<  4 SAMD21J18A External Interrupt Controller (EIC) */
-  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
-  DMAC_IRQn                =  6, /**<  6 SAMD21J18A Direct Memory Access Controller (DMAC) */
-  USB_IRQn                 =  7, /**<  7 SAMD21J18A Universal Serial Bus (USB) */
-  EVSYS_IRQn               =  8, /**<  8 SAMD21J18A Event System Interface (EVSYS) */
-  SERCOM0_IRQn             =  9, /**<  9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
-  SERCOM1_IRQn             = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
-  SERCOM2_IRQn             = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
-  SERCOM3_IRQn             = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
-  SERCOM4_IRQn             = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
-  SERCOM5_IRQn             = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
-  TCC0_IRQn                = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
-  TCC1_IRQn                = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
-  TCC2_IRQn                = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
-  TC3_IRQn                 = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
-  TC6_IRQn                 = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
-  TC7_IRQn                 = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
-  ADC_IRQn                 = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
-  AC_IRQn                  = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
-  DAC_IRQn                 = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
-  PTC_IRQn                 = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
-  I2S_IRQn                 = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
-
-  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pvReservedM12;
-  void* pvReservedM11;
-  void* pvReservedM10;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pvReservedM4;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnSYSCTRL_Handler;               /*  1 System Control */
-  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
-  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
-  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
-  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
-  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
-  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
-  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
-  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
-  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
-  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
-  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
-  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
-  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
-  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
-  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
-  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
-  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
-  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
-  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
-  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
-  void* pfnAC_Handler;                    /* 24 Analog Comparators */
-  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
-  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
-  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
-  void* pvReserved28;
-} DeviceVectors;
-
-/* Cortex-M0+ processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void SVC_Handler                 ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void SYSCTRL_Handler             ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_Handler                 ( void );
-void NVMCTRL_Handler             ( void );
-void DMAC_Handler                ( void );
-void USB_Handler                 ( void );
-void EVSYS_Handler               ( void );
-void SERCOM0_Handler             ( void );
-void SERCOM1_Handler             ( void );
-void SERCOM2_Handler             ( void );
-void SERCOM3_Handler             ( void );
-void SERCOM4_Handler             ( void );
-void SERCOM5_Handler             ( void );
-void TCC0_Handler                ( void );
-void TCC1_Handler                ( void );
-void TCC2_Handler                ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void TC6_Handler                 ( void );
-void TC7_Handler                 ( void );
-void ADC_Handler                 ( void );
-void AC_Handler                  ( void );
-void DAC_Handler                 ( void );
-void PTC_Handler                 ( void );
-void I2S_Handler                 ( void );
-
-/*
- * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1
-#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
-#define __MPU_PRESENT          0         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm0plus.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd21.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J18A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/i2s.h"
-#include "component/mtb.h"
-#include "component/nvmctrl.h"
-#include "component/pac.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/rtc.h"
-#include "component/sercom.h"
-#include "component/sysctrl.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J18A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/gclk.h"
-#include "instance/sbmatrix.h"
-#include "instance/i2s.h"
-#include "instance/mtb.h"
-#include "instance/nvmctrl.h"
-#include "instance/pac0.h"
-#include "instance/pac1.h"
-#include "instance/pac2.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/rtc.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/sysctrl.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tc6.h"
-#include "instance/tc7.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
-#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_PORT          35 /**< \brief Port Module (PORT) */
-#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
-#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
-#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
-
-// Peripheral instances on HPB2 bridge
-#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
-#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
-#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
-#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
-#define ID_AC            81 /**< \brief Analog Comparators (AC) */
-#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
-#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
-#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
-
-#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
-#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
-#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
-
-#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
-
-#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
-#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
-#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
-#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
-#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
-#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
-#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
-#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
-#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
-#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
-#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PTC_GCLK_ID       34
-#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
-#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
-#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
-#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
-
-#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
-#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
-#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
-#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
-#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
-
-#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD21J18A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd21j18a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-
-#define FLASH_SIZE            0x40000UL /* 256 kB */
-#define FLASH_PAGE_SIZE       64
-#define FLASH_NB_OF_PAGES     4096
-#define FLASH_USER_PAGE_SIZE  64
-#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
-
-#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
-#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
-#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
-#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
-#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
-#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
-#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    0x10010000UL
-#define EIC_EXTINT_NUM        16
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD21J18A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD21J18A_H */
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC                           (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         0x8000UL /* 32 kB */
+
+#define FLASH_ADDR            (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR             (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR             (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR              (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    0x10010000UL
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
index 5bf0fae..d85c986 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
@@ -1,278 +1,278 @@
-/**
- * \file
- *
- * \brief gcc startup file for SAMD21
- *
- * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#include "samd21.h"
-
-/* Initialize segments */
-extern uint32_t _sfixed;
-extern uint32_t _efixed;
-extern uint32_t _etext;
-extern uint32_t _srelocate;
-extern uint32_t _erelocate;
-extern uint32_t _szero;
-extern uint32_t _ezero;
-extern uint32_t _sstack;
-extern uint32_t _estack;
-
-/** \cond DOXYGEN_SHOULD_SKIP_THIS */
-int main(void);
-/** \endcond */
-
-void __libc_init_array(void);
-
-/* Default empty handler */
-void Dummy_Handler(void);
-
-/* Cortex-M0+ core handlers */
-void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-
-/* Peripherals handlers */
-void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SYSCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void DMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef ID_USB
-void USB_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef ID_SERCOM4
-void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_SERCOM5
-void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-void TCC0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TCC1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TCC2_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef ID_TC6
-void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_TC7
-void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_ADC
-void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_AC
-void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_DAC
-void DAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_PTC
-void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_I2S
-void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_AC1
-void AC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-#ifdef ID_TCC3
-void TCC3_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif
-
-/* Exception Table */
-__attribute__ ((section(".vectors")))
-const DeviceVectors exception_table = {
-
-        /* Configure Initial Stack Pointer, using linker-generated symbols */
-        .pvStack                = (void*) (&_estack),
-
-        .pfnReset_Handler       = (void*) Reset_Handler,
-        .pfnNMI_Handler         = (void*) NMI_Handler,
-        .pfnHardFault_Handler   = (void*) HardFault_Handler,
-        .pvReservedM12          = (void*) (0UL), /* Reserved */
-        .pvReservedM11          = (void*) (0UL), /* Reserved */
-        .pvReservedM10          = (void*) (0UL), /* Reserved */
-        .pvReservedM9           = (void*) (0UL), /* Reserved */
-        .pvReservedM8           = (void*) (0UL), /* Reserved */
-        .pvReservedM7           = (void*) (0UL), /* Reserved */
-        .pvReservedM6           = (void*) (0UL), /* Reserved */
-        .pfnSVC_Handler         = (void*) SVC_Handler,
-        .pvReservedM4           = (void*) (0UL), /* Reserved */
-        .pvReservedM3           = (void*) (0UL), /* Reserved */
-        .pfnPendSV_Handler      = (void*) PendSV_Handler,
-        .pfnSysTick_Handler     = (void*) SysTick_Handler,
-
-        /* Configurable interrupts */
-        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
-        .pfnSYSCTRL_Handler     = (void*) SYSCTRL_Handler,        /*  1 System Control */
-        .pfnWDT_Handler         = (void*) WDT_Handler,            /*  2 Watchdog Timer */
-        .pfnRTC_Handler         = (void*) RTC_Handler,            /*  3 Real-Time Counter */
-        .pfnEIC_Handler         = (void*) EIC_Handler,            /*  4 External Interrupt Controller */
-        .pfnNVMCTRL_Handler     = (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
-        .pfnDMAC_Handler        = (void*) DMAC_Handler,           /*  6 Direct Memory Access Controller */
-#ifdef ID_USB
-        .pfnUSB_Handler         = (void*) USB_Handler,            /*  7 Universal Serial Bus */
-#else
-        .pvReserved7            = (void*) (0UL),                  /*  7 Reserved */
-#endif
-        .pfnEVSYS_Handler       = (void*) EVSYS_Handler,          /*  8 Event System Interface */
-        .pfnSERCOM0_Handler     = (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
-        .pfnSERCOM1_Handler     = (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
-        .pfnSERCOM2_Handler     = (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
-        .pfnSERCOM3_Handler     = (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
-#ifdef ID_SERCOM4
-        .pfnSERCOM4_Handler     = (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
-#else
-        .pvReserved13           = (void*) (0UL),                  /* 13 Reserved */
-#endif
-#ifdef ID_SERCOM5
-        .pfnSERCOM5_Handler     = (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
-#else
-        .pvReserved14           = (void*) (0UL),                  /* 14 Reserved */
-#endif
-        .pfnTCC0_Handler        = (void*) TCC0_Handler,           /* 15 Timer Counter Control 0 */
-        .pfnTCC1_Handler        = (void*) TCC1_Handler,           /* 16 Timer Counter Control 1 */
-        .pfnTCC2_Handler        = (void*) TCC2_Handler,           /* 17 Timer Counter Control 2 */
-        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 18 Basic Timer Counter 0 */
-        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 19 Basic Timer Counter 1 */
-        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 20 Basic Timer Counter 2 */
-#ifdef ID_TC6
-        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 21 Basic Timer Counter 3 */
-#else
-        .pvReserved21           = (void*) (0UL),                  /* 21 Reserved */
-#endif
-#ifdef ID_TC7
-        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 22 Basic Timer Counter 4 */
-#else
-        .pvReserved22           = (void*) (0UL),                  /* 22 Reserved */
-#endif
-#ifdef ID_ADC
-        .pfnADC_Handler         = (void*) ADC_Handler,            /* 23 Analog Digital Converter */
-#else
-        .pvReserved23           = (void*) (0UL),                  /* 23 Reserved */
-#endif
-#ifdef ID_AC
-        .pfnAC_Handler          = (void*) AC_Handler,             /* 24 Analog Comparators 0 */
-#else
-        .pvReserved24           = (void*) (0UL),                  /* 24 Reserved */
-#endif
-#ifdef ID_DAC
-        .pfnDAC_Handler         = (void*) DAC_Handler,            /* 25 Digital Analog Converter */
-#else
-        .pvReserved25           = (void*) (0UL),                  /* 25 Reserved */
-#endif
-#ifdef ID_PTC
-        .pfnPTC_Handler         = (void*) PTC_Handler,            /* 26 Peripheral Touch Controller */
-#else
-        .pvReserved26           = (void*) (0UL),                  /* 26 Reserved */
-#endif
-#ifdef ID_I2S
-        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 27 Inter-IC Sound Interface */
-#else
-        .pvReserved27           = (void*) (0UL),                  /* 27 Reserved */
-#endif
-#ifdef ID_AC1
-        .pfnAC1_Handler         = (void*) AC1_Handler,            /* 28 Analog Comparators 1 */
-#else
-        .pvReserved28           = (void*) (0UL),                  /* 28 Reserved */
-#endif
-#ifdef ID_TCC3
-        .pfnTCC3_Handler        = (void*) TCC3_Handler            /* 29 Timer Counter Control 3 */
-#endif
-};
-
-/**
- * \brief This is the code that gets called on processor reset.
- * To initialize the device, and call the main() routine.
- */
-void Reset_Handler(void)
-{
-        uint32_t *pSrc, *pDest;
-
-        /* Initialize the relocate segment */
-        pSrc = &_etext;
-        pDest = &_srelocate;
-
-        if (pSrc != pDest) {
-                for (; pDest < &_erelocate;) {
-                        *pDest++ = *pSrc++;
-                }
-        }
-
-        /* Clear the zero segment */
-        for (pDest = &_szero; pDest < &_ezero;) {
-                *pDest++ = 0;
-        }
-
-        /* Set the vector table base address */
-        pSrc = (uint32_t *) & _sfixed;
-        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
-
-        /* Change default QOS values to have the best performance and correct USB behaviour */
-        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
-#if defined(ID_USB)
-        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
-        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
-#endif
-        DMAC->QOSCTRL.bit.DQOS = 2;
-        DMAC->QOSCTRL.bit.FQOS = 2;
-        DMAC->QOSCTRL.bit.WRBQOS = 2;
-
-        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
-        NVMCTRL->CTRLB.bit.MANW = 1;
-
-        /* Initialize the C library */
-        __libc_init_array();
-
-        /* Branch to main function */
-        main();
-
-        /* Infinite loop */
-        while (1);
-}
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Dummy_Handler(void)
-{
-        while (1) {
-        }
-}
+/**
+ * \file
+ *
+ * \brief gcc startup file for SAMD21
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_ADC
+void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC1
+void AC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TCC3
+void TCC3_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNMI_Handler         = (void*) NMI_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pvReservedM12          = (void*) (0UL), /* Reserved */
+        .pvReservedM11          = (void*) (0UL), /* Reserved */
+        .pvReservedM10          = (void*) (0UL), /* Reserved */
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVC_Handler         = (void*) SVC_Handler,
+        .pvReservedM4           = (void*) (0UL), /* Reserved */
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnSYSCTRL_Handler     = (void*) SYSCTRL_Handler,        /*  1 System Control */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        .pfnEIC_Handler         = (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        .pfnNVMCTRL_Handler     = (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        .pfnDMAC_Handler        = (void*) DMAC_Handler,           /*  6 Direct Memory Access Controller */
+#ifdef ID_USB
+        .pfnUSB_Handler         = (void*) USB_Handler,            /*  7 Universal Serial Bus */
+#else
+        .pvReserved7            = (void*) (0UL),                  /*  7 Reserved */
+#endif
+        .pfnEVSYS_Handler       = (void*) EVSYS_Handler,          /*  8 Event System Interface */
+        .pfnSERCOM0_Handler     = (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
+        .pfnSERCOM1_Handler     = (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
+        .pfnSERCOM2_Handler     = (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
+        .pfnSERCOM3_Handler     = (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_Handler     = (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
+#else
+        .pvReserved13           = (void*) (0UL),                  /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_Handler     = (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
+#else
+        .pvReserved14           = (void*) (0UL),                  /* 14 Reserved */
+#endif
+        .pfnTCC0_Handler        = (void*) TCC0_Handler,           /* 15 Timer Counter Control 0 */
+        .pfnTCC1_Handler        = (void*) TCC1_Handler,           /* 16 Timer Counter Control 1 */
+        .pfnTCC2_Handler        = (void*) TCC2_Handler,           /* 17 Timer Counter Control 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 18 Basic Timer Counter 0 */
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 19 Basic Timer Counter 1 */
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 21 Basic Timer Counter 3 */
+#else
+        .pvReserved21           = (void*) (0UL),                  /* 21 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 22 Basic Timer Counter 4 */
+#else
+        .pvReserved22           = (void*) (0UL),                  /* 22 Reserved */
+#endif
+#ifdef ID_ADC
+        .pfnADC_Handler         = (void*) ADC_Handler,            /* 23 Analog Digital Converter */
+#else
+        .pvReserved23           = (void*) (0UL),                  /* 23 Reserved */
+#endif
+#ifdef ID_AC
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 24 Analog Comparators 0 */
+#else
+        .pvReserved24           = (void*) (0UL),                  /* 24 Reserved */
+#endif
+#ifdef ID_DAC
+        .pfnDAC_Handler         = (void*) DAC_Handler,            /* 25 Digital Analog Converter */
+#else
+        .pvReserved25           = (void*) (0UL),                  /* 25 Reserved */
+#endif
+#ifdef ID_PTC
+        .pfnPTC_Handler         = (void*) PTC_Handler,            /* 26 Peripheral Touch Controller */
+#else
+        .pvReserved26           = (void*) (0UL),                  /* 26 Reserved */
+#endif
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 27 Inter-IC Sound Interface */
+#else
+        .pvReserved27           = (void*) (0UL),                  /* 27 Reserved */
+#endif
+#ifdef ID_AC1
+        .pfnAC1_Handler         = (void*) AC1_Handler,            /* 28 Analog Comparators 1 */
+#else
+        .pvReserved28           = (void*) (0UL),                  /* 28 Reserved */
+#endif
+#ifdef ID_TCC3
+        .pfnTCC3_Handler        = (void*) TCC3_Handler            /* 29 Timer Counter Control 3 */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        /* Change default QOS values to have the best performance and correct USB behaviour */
+        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+        DMAC->QOSCTRL.bit.DQOS = 2;
+        DMAC->QOSCTRL.bit.FQOS = 2;
+        DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        /* Initialize the C library */
+        __libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
index 5e088bb..1e5aa3a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
@@ -1,71 +1,71 @@
-/**
- * \file
- *
- * \brief Low-level initialization functions called upon chip startup.
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "samd21.h"
-
-/**
- * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
- *  the source for the main clock at chip startup.
- */
-#define __SYSTEM_CLOCK    (1000000)
-
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-/**
- * Initialize the system
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-void SystemInit(void)
-{
-	// Keep the default device state after reset
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
-}
-
-/**
- * Update SystemCoreClock variable
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-void SystemCoreClockUpdate(void)
-{
-	// Not implemented
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
-}
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "samd21.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+	// Keep the default device state after reset
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+	// Not implemented
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h
index 90d9439..50929be 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h
@@ -1,55 +1,55 @@
-/**
- * \file
- *
- * \brief Low-level initialization functions called upon chip startup
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SYSTEM_SAMD21_H_INCLUDED_
-#define _SYSTEM_SAMD21_H_INCLUDED_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
-
-void SystemInit(void);
-void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_SAMD21_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/compiler.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/compiler.h
index a83b46c..6aa16d7 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/compiler.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/compiler.h
@@ -1,1166 +1,1166 @@
-/**
- * \file
- *
- * \brief Commonly used includes, types and macros.
- *
- * Copyright (c) 2012-2019 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef UTILS_COMPILER_H_INCLUDED
-#define UTILS_COMPILER_H_INCLUDED
-
-/**
- * \defgroup group_sam0_utils Compiler abstraction layer and code utilities
- *
- * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices.
- * This module provides various abstraction layers and utilities to make code compatible between different compilers.
- *
- * @{
- */
-
-#if (defined __ICCARM__)
-#  include <intrinsics.h>
-#endif
-
-#include <stddef.h>
-#include <parts.h>
-#include <status_codes.h>
-#include <preprocessor.h>
-#include <io.h>
-
-#ifndef __ASSEMBLY__
-
-#include <stdio.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-/**
- * \def UNUSED
- * \brief Marking \a v as a unused parameter or value.
- */
-#define UNUSED(v)          (void)(v)
-
-/**
- * \def barrier
- * \brief Memory barrier
- */
-#ifdef __GNUC__
-#  define barrier()        asm volatile("" ::: "memory")
-#else
-#  define barrier()        asm ("")
-#endif
-
-/**
- * \brief Emit the compiler pragma \a arg.
- *
- * \param[in] arg  The pragma directive as it would appear after \e \#pragma
- *             (i.e. not stringified).
- */
-#define COMPILER_PRAGMA(arg)          _Pragma(#arg)
-
-/**
- * \def COMPILER_PACK_SET(alignment)
- * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
- */
-#define COMPILER_PACK_SET(alignment)  COMPILER_PRAGMA(pack(alignment))
-
-/**
- * \def COMPILER_PACK_RESET()
- * \brief Set default alignment for subsequent struct and union definitions.
- */
-#define COMPILER_PACK_RESET()         COMPILER_PRAGMA(pack())
-
-
-/**
- * \brief Set aligned boundary.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-#   define COMPILER_ALIGNED(a)        __attribute__((__aligned__(a)))
-#elif (defined __ICCARM__)
-#   define COMPILER_ALIGNED(a)        COMPILER_PRAGMA(data_alignment = a)
-#endif
-
-/**
- * \brief Set word-aligned boundary.
- */
-#if (defined __GNUC__) || defined(__CC_ARM)
-#define COMPILER_WORD_ALIGNED         __attribute__((__aligned__(4)))
-#elif (defined __ICCARM__)
-#define COMPILER_WORD_ALIGNED         COMPILER_PRAGMA(data_alignment = 4)
-#endif
-
-/**
- * \def __always_inline
- * \brief The function should always be inlined.
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and inline the function no matter how big it thinks it
- * becomes.
- */
-#if defined(__CC_ARM)
-#  define __always_inline             __forceinline
-#elif (defined __GNUC__)
-#  define __always_inline             __attribute__((__always_inline__))
-#elif (defined __ICCARM__)
-#  define __always_inline             _Pragma("inline=forced")
-#endif
-
-/**
- * \def __no_inline
- * \brief The function should never be inlined
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and not inline the function no matter how small it thinks it
- * becomes.
- */
-#if defined(__CC_ARM)
-#  define __no_inline                 __attribute__((noinline))
-#elif (defined __GNUC__)
-#  define __no_inline                 __attribute__((noinline))
-#elif (defined __ICCARM__)
-#  define __no_inline                 _Pragma("inline=never")
-#endif
-
-
-/** \brief This macro is used to test fatal errors.
- *
- * The macro tests if the expression is false. If it is, a fatal error is
- * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO
- * is defined, a unit test version of the macro is used, to allow execution
- * of further tests after a false expression.
- *
- * \param[in] expr  Expression to evaluate and supposed to be nonzero.
- */
-#if defined(_ASSERT_ENABLE_)
-#  if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
-#    include "unit_test/suite.h"
-#  else
-#    undef TEST_SUITE_DEFINE_ASSERT_MACRO
-#    define Assert(expr) \
-        {\
-           if (!(expr)) asm("BKPT #0");\
-        }
-#  endif
-#else
-#  define Assert(expr) ((void) 0)
-#endif
-
-/* Define WEAK attribute */
-#if defined   ( __CC_ARM   )
-#   define WEAK __attribute__ ((weak))
-#elif defined ( __ICCARM__ )
-#   define WEAK __weak
-#elif defined (  __GNUC__  )
-#   define WEAK __attribute__ ((weak))
-#endif
-
-/* Define NO_INIT attribute */
-#if defined   ( __CC_ARM   )
-#   define NO_INIT __attribute__((zero_init))
-#elif defined ( __ICCARM__ )
-#   define NO_INIT __no_init
-#elif defined (  __GNUC__  )
-#   define NO_INIT __attribute__((section(".no_init")))
-#endif
-
-#include "interrupt.h"
-
-/** \name Usual Types
- * @{ */
-#ifndef __cplusplus
-#  if !defined(__bool_true_false_are_defined)
-typedef unsigned char           bool;
-#  endif
-#endif
-typedef uint16_t                le16_t;
-typedef uint16_t                be16_t;
-typedef uint32_t                le32_t;
-typedef uint32_t                be32_t;
-typedef uint32_t                iram_size_t;
-/** @} */
-
-/** \name Aliasing Aggregate Types
- * @{ */
-
-/** 16-bit union. */
-typedef union
-{
-  int16_t  s16;
-  uint16_t u16;
-  int8_t   s8[2];
-  uint8_t  u8[2];
-} Union16;
-
-/** 32-bit union. */
-typedef union
-{
-  int32_t  s32;
-  uint32_t u32;
-  int16_t  s16[2];
-  uint16_t u16[2];
-  int8_t   s8[4];
-  uint8_t  u8[4];
-} Union32;
-
-/** 64-bit union. */
-typedef union
-{
-  int64_t  s64;
-  uint64_t u64;
-  int32_t  s32[2];
-  uint32_t u32[2];
-  int16_t  s16[4];
-  uint16_t u16[4];
-  int8_t   s8[8];
-  uint8_t  u8[8];
-} Union64;
-
-/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union
-{
-  int64_t  *s64ptr;
-  uint64_t *u64ptr;
-  int32_t  *s32ptr;
-  uint32_t *u32ptr;
-  int16_t  *s16ptr;
-  uint16_t *u16ptr;
-  int8_t   *s8ptr;
-  uint8_t  *u8ptr;
-} UnionPtr;
-
-/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union
-{
-  volatile int64_t  *s64ptr;
-  volatile uint64_t *u64ptr;
-  volatile int32_t  *s32ptr;
-  volatile uint32_t *u32ptr;
-  volatile int16_t  *s16ptr;
-  volatile uint16_t *u16ptr;
-  volatile int8_t   *s8ptr;
-  volatile uint8_t  *u8ptr;
-} UnionVPtr;
-
-/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union
-{
-  const int64_t  *s64ptr;
-  const uint64_t *u64ptr;
-  const int32_t  *s32ptr;
-  const uint32_t *u32ptr;
-  const int16_t  *s16ptr;
-  const uint16_t *u16ptr;
-  const int8_t   *s8ptr;
-  const uint8_t  *u8ptr;
-} UnionCPtr;
-
-/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef union
-{
-  const volatile int64_t  *s64ptr;
-  const volatile uint64_t *u64ptr;
-  const volatile int32_t  *s32ptr;
-  const volatile uint32_t *u32ptr;
-  const volatile int16_t  *s16ptr;
-  const volatile uint16_t *u16ptr;
-  const volatile int8_t   *s8ptr;
-  const volatile uint8_t  *u8ptr;
-} UnionCVPtr;
-
-/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct
-{
-  int64_t  *s64ptr;
-  uint64_t *u64ptr;
-  int32_t  *s32ptr;
-  uint32_t *u32ptr;
-  int16_t  *s16ptr;
-  uint16_t *u16ptr;
-  int8_t   *s8ptr;
-  uint8_t  *u8ptr;
-} StructPtr;
-
-/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct
-{
-  volatile int64_t  *s64ptr;
-  volatile uint64_t *u64ptr;
-  volatile int32_t  *s32ptr;
-  volatile uint32_t *u32ptr;
-  volatile int16_t  *s16ptr;
-  volatile uint16_t *u16ptr;
-  volatile int8_t   *s8ptr;
-  volatile uint8_t  *u8ptr;
-} StructVPtr;
-
-/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct
-{
-  const int64_t  *s64ptr;
-  const uint64_t *u64ptr;
-  const int32_t  *s32ptr;
-  const uint32_t *u32ptr;
-  const int16_t  *s16ptr;
-  const uint16_t *u16ptr;
-  const int8_t   *s8ptr;
-  const uint8_t  *u8ptr;
-} StructCPtr;
-
-/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
-typedef struct
-{
-  const volatile int64_t  *s64ptr;
-  const volatile uint64_t *u64ptr;
-  const volatile int32_t  *s32ptr;
-  const volatile uint32_t *u32ptr;
-  const volatile int16_t  *s16ptr;
-  const volatile uint16_t *u16ptr;
-  const volatile int8_t   *s8ptr;
-  const volatile uint8_t  *u8ptr;
-} StructCVPtr;
-
-/** @} */
-
-#endif  /* #ifndef __ASSEMBLY__ */
-
-/** \name Usual Constants
- * @{ */
-#define DISABLE   0
-#define ENABLE    1
-
-#ifndef __cplusplus
-#  if !defined(__bool_true_false_are_defined)
-#    define false     0
-#    define true      1
-#  endif
-#endif
-/** @} */
-
-#ifndef __ASSEMBLY__
-
-/** \name Optimization Control
- * @{ */
-
-/**
- * \def likely(exp)
- * \brief The expression \a exp is likely to be true
- */
-#if !defined(likely) || defined(__DOXYGEN__)
-#   define likely(exp)    (exp)
-#endif
-
-/**
- * \def unlikely(exp)
- * \brief The expression \a exp is unlikely to be true
- */
-#if !defined(unlikely) || defined(__DOXYGEN__)
-#   define unlikely(exp)  (exp)
-#endif
-
-/**
- * \def is_constant(exp)
- * \brief Determine if an expression evaluates to a constant value.
- *
- * \param[in] exp Any expression
- *
- * \return true if \a exp is constant, false otherwise.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-#   define is_constant(exp)       __builtin_constant_p(exp)
-#else
-#   define is_constant(exp)       (0)
-#endif
-
-/** @} */
-
-/** \name Bit-Field Handling
- * @{ */
-
-/** \brief Reads the bits of a value specified by a given bit-mask.
- *
- * \param[in] value Value to read bits from.
- * \param[in] mask  Bit-mask indicating bits to read.
- *
- * \return Read bits.
- */
-#define Rd_bits( value, mask)        ((value) & (mask))
-
-/** \brief Writes the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue  C lvalue to write bits to.
- * \param[in] mask    Bit-mask indicating bits to write.
- * \param[in] bits    Bits to write.
- *
- * \return Resulting value with written bits.
- */
-#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
-                                                 ((bits  ) &  (mask)))
-
-/** \brief Tests the bits of a value specified by a given bit-mask.
- *
- * \param[in] value Value of which to test bits.
- * \param[in] mask  Bit-mask indicating bits to test.
- *
- * \return \c 1 if at least one of the tested bits is set, else \c 0.
- */
-#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
-
-/** \brief Clears the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue  C lvalue of which to clear bits.
- * \param[in] mask    Bit-mask indicating bits to clear.
- *
- * \return Resulting value with cleared bits.
- */
-#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
-
-/** \brief Sets the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue  C lvalue of which to set bits.
- * \param[in] mask    Bit-mask indicating bits to set.
- *
- * \return Resulting value with set bits.
- */
-#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
-
-/** \brief Toggles the bits of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue  C lvalue of which to toggle bits.
- * \param[in] mask    Bit-mask indicating bits to toggle.
- *
- * \return Resulting value with toggled bits.
- */
-#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
-
-/** \brief Reads the bit-field of a value specified by a given bit-mask.
- *
- * \param[in] value Value to read a bit-field from.
- * \param[in] mask  Bit-mask indicating the bit-field to read.
- *
- * \return Read bit-field.
- */
-#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
-
-/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
- *
- * \param[in] lvalue    C lvalue to write a bit-field to.
- * \param[in] mask      Bit-mask indicating the bit-field to write.
- * \param[in] bitfield  Bit-field to write.
- *
- * \return Resulting value with written bit-field.
- */
-#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))
-
-/** @} */
-
-
-/** \name Zero-Bit Counting
- *
- * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
- * applied to constant expressions (values known at compile time), so they are
- * more optimized than the use of the corresponding assembly instructions and
- * they can be used as constant expressions e.g. to initialize objects having
- * static storage duration, and like the corresponding assembly instructions
- * when applied to non-constant expressions (values unknown at compile time), so
- * they are more optimized than an assembly periphrasis. Hence, clz and ctz
- * ensure a possible and optimized behavior for both constant and non-constant
- * expressions.
- *
- * @{ */
-
-/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
- *
- * \param[in] u Value of which to count the leading zero bits.
- *
- * \return The count of leading zero bits in \a u.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-#   define clz(u)              ((u) ? __builtin_clz(u) : 32)
-#else
-#   define clz(u)              (((u) == 0)          ? 32 : \
-                                ((u) & (1ul << 31)) ?  0 : \
-                                ((u) & (1ul << 30)) ?  1 : \
-                                ((u) & (1ul << 29)) ?  2 : \
-                                ((u) & (1ul << 28)) ?  3 : \
-                                ((u) & (1ul << 27)) ?  4 : \
-                                ((u) & (1ul << 26)) ?  5 : \
-                                ((u) & (1ul << 25)) ?  6 : \
-                                ((u) & (1ul << 24)) ?  7 : \
-                                ((u) & (1ul << 23)) ?  8 : \
-                                ((u) & (1ul << 22)) ?  9 : \
-                                ((u) & (1ul << 21)) ? 10 : \
-                                ((u) & (1ul << 20)) ? 11 : \
-                                ((u) & (1ul << 19)) ? 12 : \
-                                ((u) & (1ul << 18)) ? 13 : \
-                                ((u) & (1ul << 17)) ? 14 : \
-                                ((u) & (1ul << 16)) ? 15 : \
-                                ((u) & (1ul << 15)) ? 16 : \
-                                ((u) & (1ul << 14)) ? 17 : \
-                                ((u) & (1ul << 13)) ? 18 : \
-                                ((u) & (1ul << 12)) ? 19 : \
-                                ((u) & (1ul << 11)) ? 20 : \
-                                ((u) & (1ul << 10)) ? 21 : \
-                                ((u) & (1ul <<  9)) ? 22 : \
-                                ((u) & (1ul <<  8)) ? 23 : \
-                                ((u) & (1ul <<  7)) ? 24 : \
-                                ((u) & (1ul <<  6)) ? 25 : \
-                                ((u) & (1ul <<  5)) ? 26 : \
-                                ((u) & (1ul <<  4)) ? 27 : \
-                                ((u) & (1ul <<  3)) ? 28 : \
-                                ((u) & (1ul <<  2)) ? 29 : \
-                                ((u) & (1ul <<  1)) ? 30 : \
-                                31)
-#endif
-
-/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
- *
- * \param[in] u Value of which to count the trailing zero bits.
- *
- * \return The count of trailing zero bits in \a u.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-#   define ctz(u)              ((u) ? __builtin_ctz(u) : 32)
-#else
-#   define ctz(u)              ((u) & (1ul <<  0) ?  0 : \
-                                (u) & (1ul <<  1) ?  1 : \
-                                (u) & (1ul <<  2) ?  2 : \
-                                (u) & (1ul <<  3) ?  3 : \
-                                (u) & (1ul <<  4) ?  4 : \
-                                (u) & (1ul <<  5) ?  5 : \
-                                (u) & (1ul <<  6) ?  6 : \
-                                (u) & (1ul <<  7) ?  7 : \
-                                (u) & (1ul <<  8) ?  8 : \
-                                (u) & (1ul <<  9) ?  9 : \
-                                (u) & (1ul << 10) ? 10 : \
-                                (u) & (1ul << 11) ? 11 : \
-                                (u) & (1ul << 12) ? 12 : \
-                                (u) & (1ul << 13) ? 13 : \
-                                (u) & (1ul << 14) ? 14 : \
-                                (u) & (1ul << 15) ? 15 : \
-                                (u) & (1ul << 16) ? 16 : \
-                                (u) & (1ul << 17) ? 17 : \
-                                (u) & (1ul << 18) ? 18 : \
-                                (u) & (1ul << 19) ? 19 : \
-                                (u) & (1ul << 20) ? 20 : \
-                                (u) & (1ul << 21) ? 21 : \
-                                (u) & (1ul << 22) ? 22 : \
-                                (u) & (1ul << 23) ? 23 : \
-                                (u) & (1ul << 24) ? 24 : \
-                                (u) & (1ul << 25) ? 25 : \
-                                (u) & (1ul << 26) ? 26 : \
-                                (u) & (1ul << 27) ? 27 : \
-                                (u) & (1ul << 28) ? 28 : \
-                                (u) & (1ul << 29) ? 29 : \
-                                (u) & (1ul << 30) ? 30 : \
-                                (u) & (1ul << 31) ? 31 : \
-                                32)
-#endif
-
-/** @} */
-
-
-/** \name Bit Reversing
- * @{ */
-
-/** \brief Reverses the bits of \a u8.
- *
- * \param[in] u8  U8 of which to reverse the bits.
- *
- * \return Value resulting from \a u8 with reversed bits.
- */
-#define bit_reverse8(u8)    ((U8)(bit_reverse32((U8)(u8)) >> 24))
-
-/** \brief Reverses the bits of \a u16.
- *
- * \param[in] u16 U16 of which to reverse the bits.
- *
- * \return Value resulting from \a u16 with reversed bits.
- */
-#define bit_reverse16(u16)  ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))
-
-/** \brief Reverses the bits of \a u32.
- *
- * \param[in] u32 U32 of which to reverse the bits.
- *
- * \return Value resulting from \a u32 with reversed bits.
- */
-#define bit_reverse32(u32)   __RBIT(u32)
-
-/** \brief Reverses the bits of \a u64.
- *
- * \param[in] u64 U64 of which to reverse the bits.
- *
- * \return Value resulting from \a u64 with reversed bits.
- */
-#define bit_reverse64(u64)  ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\
-                                   ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))
-
-/** @} */
-
-
-/** \name Alignment
- * @{ */
-
-/** \brief Tests alignment of the number \a val with the \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n   Boundary.
- *
- * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
- */
-#define Test_align(val, n) (!Tst_bits( val, (n) - 1     )   )
-
-/** \brief Gets alignment of the number \a val with respect to the \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n   Boundary.
- *
- * \return Alignment of the number \a val with respect to the \a n boundary.
- */
-#define Get_align(val, n) (  Rd_bits( val, (n) - 1     )   )
-
-/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
- *
- * \param[in] lval  Input/output lvalue.
- * \param[in] n     Boundary.
- * \param[in] alg   Alignment.
- *
- * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
- */
-#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )
-
-/** \brief Aligns the number \a val with the upper \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n   Boundary.
- *
- * \return Value resulting from the number \a val aligned with the upper \a n boundary.
- */
-#define Align_up(  val, n) (((val) + ((n) - 1)) & ~((n) - 1))
-
-/** \brief Aligns the number \a val with the lower \a n boundary.
- *
- * \param[in] val Input value.
- * \param[in] n   Boundary.
- *
- * \return Value resulting from the number \a val aligned with the lower \a n boundary.
- */
-#define Align_down(val, n) ( (val)              & ~((n) - 1))
-
-/** @} */
-
-
-/** \name Mathematics
- *
- * The same considerations as for clz and ctz apply here but GCC does not
- * provide built-in functions to access the assembly instructions abs, min and
- * max and it does not produce them by itself in most cases, so two sets of
- * macros are defined here:
- *   - Abs, Min and Max to apply to constant expressions (values known at
- *     compile time);
- *   - abs, min and max to apply to non-constant expressions (values unknown at
- *     compile time), abs is found in stdlib.h.
- *
- * @{ */
-
-/** \brief Takes the absolute value of \a a.
- *
- * \param[in] a Input value.
- *
- * \return Absolute value of \a a.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
-
-#ifndef __cplusplus
-/** \brief Takes the minimal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
-
-/** \brief Takes the maximal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
-
-/** \brief Takes the minimal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define min(a, b)   Min(a, b)
-
-/** \brief Takes the maximal value of \a a and \a b.
- *
- * \param[in] a Input value.
- * \param[in] b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define max(a, b)   Max(a, b)
-#endif
-
-/** @} */
-
-
-/** \brief Calls the routine at address \a addr.
- *
- * It generates a long call opcode.
- *
- * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
- * it is invoked from the CPU supervisor mode.
- *
- * \param[in] addr  Address of the routine to call.
- *
- * \note It may be used as a long jump opcode in some special cases.
- */
-#define Long_call(addr)                   ((*(void (*)(void))(addr))())
-
-
-/** \name MCU Endianism Handling
- *  ARM is MCU little endian.
- *
- * @{ */
-#define  BE16(x)        swap16(x)
-#define  LE16(x)        (x)
-
-#define  le16_to_cpu(x) (x)
-#define  cpu_to_le16(x) (x)
-#define  LE16_TO_CPU(x) (x)
-#define  CPU_TO_LE16(x) (x)
-
-#define  be16_to_cpu(x) swap16(x)
-#define  cpu_to_be16(x) swap16(x)
-#define  BE16_TO_CPU(x) swap16(x)
-#define  CPU_TO_BE16(x) swap16(x)
-
-#define  le32_to_cpu(x) (x)
-#define  cpu_to_le32(x) (x)
-#define  LE32_TO_CPU(x) (x)
-#define  CPU_TO_LE32(x) (x)
-
-#define  be32_to_cpu(x) swap32(x)
-#define  cpu_to_be32(x) swap32(x)
-#define  BE32_TO_CPU(x) swap32(x)
-#define  CPU_TO_BE32(x) swap32(x)
-/** @} */
-
-
-/** \name Endianism Conversion
- *
- * The same considerations as for clz and ctz apply here but GCC's
- * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
- * applied to constant expressions, so two sets of macros are defined here:
- *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
- *     at compile time);
- *   - swap16, swap32 and swap64 to apply to non-constant expressions (values
- *     unknown at compile time).
- *
- * @{ */
-
-/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param[in] u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\
-                           ((uint16_t)(u16) << 8)))
-
-/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param[in] u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\
-                           ((uint32_t)Swap16((uint32_t)(u32)) << 16)))
-
-/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param[in] u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\
-                           ((uint64_t)Swap32((uint64_t)(u64)) << 32)))
-
-/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param[in] u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define swap16(u16) Swap16(u16)
-
-/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param[in] u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#if (defined __GNUC__)
-#  define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))
-#else
-#  define swap32(u32) Swap32(u32)
-#endif
-
-/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param[in] u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#if (defined __GNUC__)
-#  define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))
-#else
-#  define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\
-                         ((uint64_t)swap32((uint64_t)(u64)) << 32)))
-#endif
-
-/** @} */
-
-
-/** \name Target Abstraction
- *
- * @{ */
-
-#define _GLOBEXT_           extern      /**< extern storage-class specifier. */
-#define _CONST_TYPE_        const       /**< const type qualifier. */
-#define _MEM_TYPE_SLOW_                 /**< Slow memory type. */
-#define _MEM_TYPE_MEDFAST_              /**< Fairly fast memory type. */
-#define _MEM_TYPE_FAST_                 /**< Fast memory type. */
-
-#define memcmp_ram2ram      memcmp      /**< Target-specific memcmp of RAM to RAM. */
-#define memcmp_code2ram     memcmp      /**< Target-specific memcmp of RAM to NVRAM. */
-#define memcpy_ram2ram      memcpy      /**< Target-specific memcpy from RAM to RAM. */
-#define memcpy_code2ram     memcpy      /**< Target-specific memcpy from NVRAM to RAM. */
-
-/** @} */
-
-/**
- * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
- * integer arithmetic.
- *
- * \param[in] a An integer
- * \param[in] b Another integer
- *
- * \return (\a a / \a b) rounded up to the nearest integer.
- */
-#define div_ceil(a, b)      (((a) + (b) - 1) / (b))
-
-#endif  /* #ifndef __ASSEMBLY__ */
-#ifdef __ICCARM__
-/** \name Compiler Keywords
- *
- * Port of some keywords from GCC to IAR Embedded Workbench.
- *
- * @{ */
-
-#define __asm__             asm
-#define __inline__          inline
-#define __volatile__
-
-/** @} */
-
-#endif
-
-#define FUNC_PTR                            void *
-/**
- * \def unused
- * \brief Marking \a v as a unused parameter or value.
- */
-#define unused(v)          do { (void)(v); } while(0)
-
-/* Define RAMFUNC attribute */
-#if defined   ( __CC_ARM   ) /* Keil uVision 4 */
-#   define RAMFUNC __attribute__ ((section(".ramfunc")))
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-#   define RAMFUNC __ramfunc
-#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
-#   define RAMFUNC __attribute__ ((section(".ramfunc")))
-#endif
-
-/* Define OPTIMIZE_HIGH attribute */
-#if defined   ( __CC_ARM   ) /* Keil uVision 4 */
-#   define OPTIMIZE_HIGH _Pragma("O3")
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-#   define OPTIMIZE_HIGH _Pragma("optimize=high")
-#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
-#   define OPTIMIZE_HIGH __attribute__((optimize("s")))
-#endif
-#define PASS      0
-#define FAIL      1
-#define LOW       0
-#define HIGH      1
-
-typedef int8_t                  S8 ;  //!< 8-bit signed integer.
-typedef uint8_t                 U8 ;  //!< 8-bit unsigned integer.
-typedef int16_t                 S16;  //!< 16-bit signed integer.
-typedef uint16_t                U16;  //!< 16-bit unsigned integer.
-typedef int32_t                 S32;  //!< 32-bit signed integer.
-typedef uint32_t                U32;  //!< 32-bit unsigned integer.
-typedef int64_t                 S64;  //!< 64-bit signed integer.
-typedef uint64_t                U64;  //!< 64-bit unsigned integer.
-typedef float                   F32;  //!< 32-bit floating-point number.
-typedef double                  F64;  //!< 64-bit floating-point number.
-
-#define  MSB(u16)       (((U8  *)&(u16))[1]) //!< Most significant byte of \a u16.
-#define  LSB(u16)       (((U8  *)&(u16))[0]) //!< Least significant byte of \a u16.
-
-#define  MSH(u32)       (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
-#define  LSH(u32)       (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
-#define  MSB0W(u32)     (((U8  *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
-#define  MSB1W(u32)     (((U8  *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
-#define  MSB2W(u32)     (((U8  *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
-#define  MSB3W(u32)     (((U8  *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
-#define  LSB3W(u32)     MSB0W(u32)           //!< Least significant byte of 4th rank of \a u32.
-#define  LSB2W(u32)     MSB1W(u32)           //!< Least significant byte of 3rd rank of \a u32.
-#define  LSB1W(u32)     MSB2W(u32)           //!< Least significant byte of 2nd rank of \a u32.
-#define  LSB0W(u32)     MSB3W(u32)           //!< Least significant byte of 1st rank of \a u32.
-
-#define  MSW(u64)       (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
-#define  LSW(u64)       (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
-#define  MSH0(u64)      (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
-#define  MSH1(u64)      (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
-#define  MSH2(u64)      (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
-#define  MSH3(u64)      (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
-#define  LSH3(u64)      MSH0(u64)            //!< Least significant half-word of 4th rank of \a u64.
-#define  LSH2(u64)      MSH1(u64)            //!< Least significant half-word of 3rd rank of \a u64.
-#define  LSH1(u64)      MSH2(u64)            //!< Least significant half-word of 2nd rank of \a u64.
-#define  LSH0(u64)      MSH3(u64)            //!< Least significant half-word of 1st rank of \a u64.
-#define  MSB0D(u64)     (((U8  *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
-#define  MSB1D(u64)     (((U8  *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
-#define  MSB2D(u64)     (((U8  *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
-#define  MSB3D(u64)     (((U8  *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
-#define  MSB4D(u64)     (((U8  *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
-#define  MSB5D(u64)     (((U8  *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
-#define  MSB6D(u64)     (((U8  *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
-#define  MSB7D(u64)     (((U8  *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
-#define  LSB7D(u64)     MSB0D(u64)           //!< Least significant byte of 8th rank of \a u64.
-#define  LSB6D(u64)     MSB1D(u64)           //!< Least significant byte of 7th rank of \a u64.
-#define  LSB5D(u64)     MSB2D(u64)           //!< Least significant byte of 6th rank of \a u64.
-#define  LSB4D(u64)     MSB3D(u64)           //!< Least significant byte of 5th rank of \a u64.
-#define  LSB3D(u64)     MSB4D(u64)           //!< Least significant byte of 4th rank of \a u64.
-#define  LSB2D(u64)     MSB5D(u64)           //!< Least significant byte of 3rd rank of \a u64.
-#define  LSB1D(u64)     MSB6D(u64)           //!< Least significant byte of 2nd rank of \a u64.
-#define  LSB0D(u64)     MSB7D(u64)           //!< Least significant byte of 1st rank of \a u64.
-
-#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.
-#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.
-#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.
-#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.
-#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.
-#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.
-#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.
-#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.
-
-#if defined(__ICCARM__)
-#define SHORTENUM           __packed
-#elif defined(__GNUC__)
-#define SHORTENUM           __attribute__((packed))
-#endif
-
-/* No operation */
-#if defined(__ICCARM__)
-#define nop()               __no_operation()
-#elif defined(__GNUC__)
-#define nop()               __NOP()
-#endif
-
-#define FLASH_DECLARE(x)  const x
-#define FLASH_EXTERN(x) extern const x
-#define PGM_READ_BYTE(x) *(x)
-#define PGM_READ_WORD(x) *(x)
-#define MEMCPY_ENDIAN memcpy
-#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
-
-/*Defines the Flash Storage for the request and response of MAC*/
-#define CMD_ID_OCTET    (0)
-
-/* Converting of values from CPU endian to little endian. */
-#define CPU_ENDIAN_TO_LE16(x)   (x)
-#define CPU_ENDIAN_TO_LE32(x)   (x)
-#define CPU_ENDIAN_TO_LE64(x)   (x)
-
-/* Converting of values from little endian to CPU endian. */
-#define LE16_TO_CPU_ENDIAN(x)   (x)
-#define LE32_TO_CPU_ENDIAN(x)   (x)
-#define LE64_TO_CPU_ENDIAN(x)   (x)
-
-/* Converting of constants from little endian to CPU endian. */
-#define CLE16_TO_CPU_ENDIAN(x)  (x)
-#define CLE32_TO_CPU_ENDIAN(x)  (x)
-#define CLE64_TO_CPU_ENDIAN(x)  (x)
-
-/* Converting of constants from CPU endian to little endian. */
-#define CCPU_ENDIAN_TO_LE16(x)  (x)
-#define CCPU_ENDIAN_TO_LE32(x)  (x)
-#define CCPU_ENDIAN_TO_LE64(x)  (x)
-
-#define ADDR_COPY_DST_SRC_16(dst, src)  ((dst) = (src))
-#define ADDR_COPY_DST_SRC_64(dst, src)  ((dst) = (src))
-
-/**
- * @brief Converts a 64-Bit value into  a 8 Byte array
- *
- * @param[in] value 64-Bit value
- * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
-{
-    uint8_t index = 0;
-
-    while (index < 8)
-    {
-        data[index++] = value & 0xFF;
-        value = value >> 8;
-    }
-}
-
-/**
- * @brief Converts a 16-Bit value into  a 2 Byte array
- *
- * @param[in] value 16-Bit value
- * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
-{
-    data[0] = value & 0xFF;
-    data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
-{
-    data[0] = value & 0xFF;
-    data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
-{
-    data[0] = value & 0xFF;
-    data[1] = (value >> 8) & 0xFF;
-}
-
-/*
- * @brief Converts a 2 Byte array into a 16-Bit value
- *
- * @param data Specifies the pointer to the 2 Byte array
- *
- * @return 16-Bit value
- * @ingroup apiPalApi
- */
-static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
-{
-    return (data[0] | ((uint16_t)data[1] << 8));
-}
-
-/* Converts a 4 Byte array into a 32-Bit value */
-static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
-{
-	union
-	{
-		uint32_t u32;
-		uint8_t u8[4];
-	}long_addr;
-	uint8_t index;
-	for (index = 0; index < 4; index++)
-	{
-		long_addr.u8[index] = *data++;
-	}
-	return long_addr.u32;
-}
-
-/**
- * @brief Converts a 8 Byte array into a 64-Bit value
- *
- * @param data Specifies the pointer to the 8 Byte array
- *
- * @return 64-Bit value
- * @ingroup apiPalApi
- */
-static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
-{
-    union
-    {
-        uint64_t u64;
-        uint8_t u8[8];
-    } long_addr;
-
-    uint8_t index;
-
-    for (index = 0; index < 8; index++)
-    {
-        long_addr.u8[index] = *data++;
-    }
-
-    return long_addr.u64;
-}
-
-/** @} */
-
-#endif /* UTILS_COMPILER_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief Commonly used includes, types and macros.
+ *
+ * Copyright (c) 2012-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef UTILS_COMPILER_H_INCLUDED
+#define UTILS_COMPILER_H_INCLUDED
+
+/**
+ * \defgroup group_sam0_utils Compiler abstraction layer and code utilities
+ *
+ * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices.
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.
+ *
+ * @{
+ */
+
+#if (defined __ICCARM__)
+#  include <intrinsics.h>
+#endif
+
+#include <stddef.h>
+#include <parts.h>
+#include <status_codes.h>
+#include <preprocessor.h>
+#include <io.h>
+
+#ifndef __ASSEMBLY__
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * \def UNUSED
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define UNUSED(v)          (void)(v)
+
+/**
+ * \def barrier
+ * \brief Memory barrier
+ */
+#ifdef __GNUC__
+#  define barrier()        asm volatile("" ::: "memory")
+#else
+#  define barrier()        asm ("")
+#endif
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg  The pragma directive as it would appear after \e \#pragma
+ *             (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg)          _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment)  COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET()         COMPILER_PRAGMA(pack())
+
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define COMPILER_ALIGNED(a)        __attribute__((__aligned__(a)))
+#elif (defined __ICCARM__)
+#   define COMPILER_ALIGNED(a)        COMPILER_PRAGMA(data_alignment = a)
+#endif
+
+/**
+ * \brief Set word-aligned boundary.
+ */
+#if (defined __GNUC__) || defined(__CC_ARM)
+#define COMPILER_WORD_ALIGNED         __attribute__((__aligned__(4)))
+#elif (defined __ICCARM__)
+#define COMPILER_WORD_ALIGNED         COMPILER_PRAGMA(data_alignment = 4)
+#endif
+
+/**
+ * \def __always_inline
+ * \brief The function should always be inlined.
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and inline the function no matter how big it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+#  define __always_inline             __forceinline
+#elif (defined __GNUC__)
+#  define __always_inline             __attribute__((__always_inline__))
+#elif (defined __ICCARM__)
+#  define __always_inline             _Pragma("inline=forced")
+#endif
+
+/**
+ * \def __no_inline
+ * \brief The function should never be inlined
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and not inline the function no matter how small it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+#  define __no_inline                 __attribute__((noinline))
+#elif (defined __GNUC__)
+#  define __no_inline                 __attribute__((noinline))
+#elif (defined __ICCARM__)
+#  define __no_inline                 _Pragma("inline=never")
+#endif
+
+
+/** \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is false. If it is, a fatal error is
+ * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO
+ * is defined, a unit test version of the macro is used, to allow execution
+ * of further tests after a false expression.
+ *
+ * \param[in] expr  Expression to evaluate and supposed to be nonzero.
+ */
+#if defined(_ASSERT_ENABLE_)
+#  if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
+#    include "unit_test/suite.h"
+#  else
+#    undef TEST_SUITE_DEFINE_ASSERT_MACRO
+#    define Assert(expr) \
+        {\
+           if (!(expr)) asm("BKPT #0");\
+        }
+#  endif
+#else
+#  define Assert(expr) ((void) 0)
+#endif
+
+/* Define WEAK attribute */
+#if defined   ( __CC_ARM   )
+#   define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ )
+#   define WEAK __weak
+#elif defined (  __GNUC__  )
+#   define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined   ( __CC_ARM   )
+#   define NO_INIT __attribute__((zero_init))
+#elif defined ( __ICCARM__ )
+#   define NO_INIT __no_init
+#elif defined (  __GNUC__  )
+#   define NO_INIT __attribute__((section(".no_init")))
+#endif
+
+#include "interrupt.h"
+
+/** \name Usual Types
+ * @{ */
+#ifndef __cplusplus
+#  if !defined(__bool_true_false_are_defined)
+typedef unsigned char           bool;
+#  endif
+#endif
+typedef uint16_t                le16_t;
+typedef uint16_t                be16_t;
+typedef uint32_t                le32_t;
+typedef uint32_t                be32_t;
+typedef uint32_t                iram_size_t;
+/** @} */
+
+/** \name Aliasing Aggregate Types
+ * @{ */
+
+/** 16-bit union. */
+typedef union
+{
+  int16_t  s16;
+  uint16_t u16;
+  int8_t   s8[2];
+  uint8_t  u8[2];
+} Union16;
+
+/** 32-bit union. */
+typedef union
+{
+  int32_t  s32;
+  uint32_t u32;
+  int16_t  s16[2];
+  uint16_t u16[2];
+  int8_t   s8[4];
+  uint8_t  u8[4];
+} Union32;
+
+/** 64-bit union. */
+typedef union
+{
+  int64_t  s64;
+  uint64_t u64;
+  int32_t  s32[2];
+  uint32_t u32[2];
+  int16_t  s16[4];
+  uint16_t u16[4];
+  int8_t   s8[8];
+  uint8_t  u8[8];
+} Union64;
+
+/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  int64_t  *s64ptr;
+  uint64_t *u64ptr;
+  int32_t  *s32ptr;
+  uint32_t *u32ptr;
+  int16_t  *s16ptr;
+  uint16_t *u16ptr;
+  int8_t   *s8ptr;
+  uint8_t  *u8ptr;
+} UnionPtr;
+
+/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  volatile int64_t  *s64ptr;
+  volatile uint64_t *u64ptr;
+  volatile int32_t  *s32ptr;
+  volatile uint32_t *u32ptr;
+  volatile int16_t  *s16ptr;
+  volatile uint16_t *u16ptr;
+  volatile int8_t   *s8ptr;
+  volatile uint8_t  *u8ptr;
+} UnionVPtr;
+
+/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  const int64_t  *s64ptr;
+  const uint64_t *u64ptr;
+  const int32_t  *s32ptr;
+  const uint32_t *u32ptr;
+  const int16_t  *s16ptr;
+  const uint16_t *u16ptr;
+  const int8_t   *s8ptr;
+  const uint8_t  *u8ptr;
+} UnionCPtr;
+
+/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+  const volatile int64_t  *s64ptr;
+  const volatile uint64_t *u64ptr;
+  const volatile int32_t  *s32ptr;
+  const volatile uint32_t *u32ptr;
+  const volatile int16_t  *s16ptr;
+  const volatile uint16_t *u16ptr;
+  const volatile int8_t   *s8ptr;
+  const volatile uint8_t  *u8ptr;
+} UnionCVPtr;
+
+/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  int64_t  *s64ptr;
+  uint64_t *u64ptr;
+  int32_t  *s32ptr;
+  uint32_t *u32ptr;
+  int16_t  *s16ptr;
+  uint16_t *u16ptr;
+  int8_t   *s8ptr;
+  uint8_t  *u8ptr;
+} StructPtr;
+
+/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  volatile int64_t  *s64ptr;
+  volatile uint64_t *u64ptr;
+  volatile int32_t  *s32ptr;
+  volatile uint32_t *u32ptr;
+  volatile int16_t  *s16ptr;
+  volatile uint16_t *u16ptr;
+  volatile int8_t   *s8ptr;
+  volatile uint8_t  *u8ptr;
+} StructVPtr;
+
+/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  const int64_t  *s64ptr;
+  const uint64_t *u64ptr;
+  const int32_t  *s32ptr;
+  const uint32_t *u32ptr;
+  const int16_t  *s16ptr;
+  const uint16_t *u16ptr;
+  const int8_t   *s8ptr;
+  const uint8_t  *u8ptr;
+} StructCPtr;
+
+/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+  const volatile int64_t  *s64ptr;
+  const volatile uint64_t *u64ptr;
+  const volatile int32_t  *s32ptr;
+  const volatile uint32_t *u32ptr;
+  const volatile int16_t  *s16ptr;
+  const volatile uint16_t *u16ptr;
+  const volatile int8_t   *s8ptr;
+  const volatile uint8_t  *u8ptr;
+} StructCVPtr;
+
+/** @} */
+
+#endif  /* #ifndef __ASSEMBLY__ */
+
+/** \name Usual Constants
+ * @{ */
+#define DISABLE   0
+#define ENABLE    1
+
+#ifndef __cplusplus
+#  if !defined(__bool_true_false_are_defined)
+#    define false     0
+#    define true      1
+#  endif
+#endif
+/** @} */
+
+#ifndef __ASSEMBLY__
+
+/** \name Optimization Control
+ * @{ */
+
+/**
+ * \def likely(exp)
+ * \brief The expression \a exp is likely to be true
+ */
+#if !defined(likely) || defined(__DOXYGEN__)
+#   define likely(exp)    (exp)
+#endif
+
+/**
+ * \def unlikely(exp)
+ * \brief The expression \a exp is unlikely to be true
+ */
+#if !defined(unlikely) || defined(__DOXYGEN__)
+#   define unlikely(exp)  (exp)
+#endif
+
+/**
+ * \def is_constant(exp)
+ * \brief Determine if an expression evaluates to a constant value.
+ *
+ * \param[in] exp Any expression
+ *
+ * \return true if \a exp is constant, false otherwise.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define is_constant(exp)       __builtin_constant_p(exp)
+#else
+#   define is_constant(exp)       (0)
+#endif
+
+/** @} */
+
+/** \name Bit-Field Handling
+ * @{ */
+
+/** \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read bits from.
+ * \param[in] mask  Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask)        ((value) & (mask))
+
+/** \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue to write bits to.
+ * \param[in] mask    Bit-mask indicating bits to write.
+ * \param[in] bits    Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
+                                                 ((bits  ) &  (mask)))
+
+/** \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value of which to test bits.
+ * \param[in] mask  Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
+
+/** \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue of which to clear bits.
+ * \param[in] mask    Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
+
+/** \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue of which to set bits.
+ * \param[in] mask    Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
+
+/** \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue  C lvalue of which to toggle bits.
+ * \param[in] mask    Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
+
+/** \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read a bit-field from.
+ * \param[in] mask  Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
+
+/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue    C lvalue to write a bit-field to.
+ * \param[in] mask      Bit-mask indicating the bit-field to write.
+ * \param[in] bitfield  Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))
+
+/** @} */
+
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define clz(u)              ((u) ? __builtin_clz(u) : 32)
+#else
+#   define clz(u)              (((u) == 0)          ? 32 : \
+                                ((u) & (1ul << 31)) ?  0 : \
+                                ((u) & (1ul << 30)) ?  1 : \
+                                ((u) & (1ul << 29)) ?  2 : \
+                                ((u) & (1ul << 28)) ?  3 : \
+                                ((u) & (1ul << 27)) ?  4 : \
+                                ((u) & (1ul << 26)) ?  5 : \
+                                ((u) & (1ul << 25)) ?  6 : \
+                                ((u) & (1ul << 24)) ?  7 : \
+                                ((u) & (1ul << 23)) ?  8 : \
+                                ((u) & (1ul << 22)) ?  9 : \
+                                ((u) & (1ul << 21)) ? 10 : \
+                                ((u) & (1ul << 20)) ? 11 : \
+                                ((u) & (1ul << 19)) ? 12 : \
+                                ((u) & (1ul << 18)) ? 13 : \
+                                ((u) & (1ul << 17)) ? 14 : \
+                                ((u) & (1ul << 16)) ? 15 : \
+                                ((u) & (1ul << 15)) ? 16 : \
+                                ((u) & (1ul << 14)) ? 17 : \
+                                ((u) & (1ul << 13)) ? 18 : \
+                                ((u) & (1ul << 12)) ? 19 : \
+                                ((u) & (1ul << 11)) ? 20 : \
+                                ((u) & (1ul << 10)) ? 21 : \
+                                ((u) & (1ul <<  9)) ? 22 : \
+                                ((u) & (1ul <<  8)) ? 23 : \
+                                ((u) & (1ul <<  7)) ? 24 : \
+                                ((u) & (1ul <<  6)) ? 25 : \
+                                ((u) & (1ul <<  5)) ? 26 : \
+                                ((u) & (1ul <<  4)) ? 27 : \
+                                ((u) & (1ul <<  3)) ? 28 : \
+                                ((u) & (1ul <<  2)) ? 29 : \
+                                ((u) & (1ul <<  1)) ? 30 : \
+                                31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define ctz(u)              ((u) ? __builtin_ctz(u) : 32)
+#else
+#   define ctz(u)              ((u) & (1ul <<  0) ?  0 : \
+                                (u) & (1ul <<  1) ?  1 : \
+                                (u) & (1ul <<  2) ?  2 : \
+                                (u) & (1ul <<  3) ?  3 : \
+                                (u) & (1ul <<  4) ?  4 : \
+                                (u) & (1ul <<  5) ?  5 : \
+                                (u) & (1ul <<  6) ?  6 : \
+                                (u) & (1ul <<  7) ?  7 : \
+                                (u) & (1ul <<  8) ?  8 : \
+                                (u) & (1ul <<  9) ?  9 : \
+                                (u) & (1ul << 10) ? 10 : \
+                                (u) & (1ul << 11) ? 11 : \
+                                (u) & (1ul << 12) ? 12 : \
+                                (u) & (1ul << 13) ? 13 : \
+                                (u) & (1ul << 14) ? 14 : \
+                                (u) & (1ul << 15) ? 15 : \
+                                (u) & (1ul << 16) ? 16 : \
+                                (u) & (1ul << 17) ? 17 : \
+                                (u) & (1ul << 18) ? 18 : \
+                                (u) & (1ul << 19) ? 19 : \
+                                (u) & (1ul << 20) ? 20 : \
+                                (u) & (1ul << 21) ? 21 : \
+                                (u) & (1ul << 22) ? 22 : \
+                                (u) & (1ul << 23) ? 23 : \
+                                (u) & (1ul << 24) ? 24 : \
+                                (u) & (1ul << 25) ? 25 : \
+                                (u) & (1ul << 26) ? 26 : \
+                                (u) & (1ul << 27) ? 27 : \
+                                (u) & (1ul << 28) ? 28 : \
+                                (u) & (1ul << 29) ? 29 : \
+                                (u) & (1ul << 30) ? 30 : \
+                                (u) & (1ul << 31) ? 31 : \
+                                32)
+#endif
+
+/** @} */
+
+
+/** \name Bit Reversing
+ * @{ */
+
+/** \brief Reverses the bits of \a u8.
+ *
+ * \param[in] u8  U8 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u8 with reversed bits.
+ */
+#define bit_reverse8(u8)    ((U8)(bit_reverse32((U8)(u8)) >> 24))
+
+/** \brief Reverses the bits of \a u16.
+ *
+ * \param[in] u16 U16 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u16 with reversed bits.
+ */
+#define bit_reverse16(u16)  ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))
+
+/** \brief Reverses the bits of \a u32.
+ *
+ * \param[in] u32 U32 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u32 with reversed bits.
+ */
+#define bit_reverse32(u32)   __RBIT(u32)
+
+/** \brief Reverses the bits of \a u64.
+ *
+ * \param[in] u64 U64 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u64 with reversed bits.
+ */
+#define bit_reverse64(u64)  ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\
+                                   ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))
+
+/** @} */
+
+
+/** \name Alignment
+ * @{ */
+
+/** \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n) (!Tst_bits( val, (n) - 1     )   )
+
+/** \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align(val, n) (  Rd_bits( val, (n) - 1     )   )
+
+/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param[in] lval  Input/output lvalue.
+ * \param[in] n     Boundary.
+ * \param[in] alg   Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )
+
+/** \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up(  val, n) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/** \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n) ( (val)              & ~((n) - 1))
+
+/** @} */
+
+
+/** \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ *   - Abs, Min and Max to apply to constant expressions (values known at
+ *     compile time);
+ *   - abs, min and max to apply to non-constant expressions (values unknown at
+ *     compile time), abs is found in stdlib.h.
+ *
+ * @{ */
+
+/** \brief Takes the absolute value of \a a.
+ *
+ * \param[in] a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
+
+#ifndef __cplusplus
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
+
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define min(a, b)   Min(a, b)
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define max(a, b)   Max(a, b)
+#endif
+
+/** @} */
+
+
+/** \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param[in] addr  Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr)                   ((*(void (*)(void))(addr))())
+
+
+/** \name MCU Endianism Handling
+ *  ARM is MCU little endian.
+ *
+ * @{ */
+#define  BE16(x)        swap16(x)
+#define  LE16(x)        (x)
+
+#define  le16_to_cpu(x) (x)
+#define  cpu_to_le16(x) (x)
+#define  LE16_TO_CPU(x) (x)
+#define  CPU_TO_LE16(x) (x)
+
+#define  be16_to_cpu(x) swap16(x)
+#define  cpu_to_be16(x) swap16(x)
+#define  BE16_TO_CPU(x) swap16(x)
+#define  CPU_TO_BE16(x) swap16(x)
+
+#define  le32_to_cpu(x) (x)
+#define  cpu_to_le32(x) (x)
+#define  LE32_TO_CPU(x) (x)
+#define  CPU_TO_LE32(x) (x)
+
+#define  be32_to_cpu(x) swap32(x)
+#define  cpu_to_be32(x) swap32(x)
+#define  BE32_TO_CPU(x) swap32(x)
+#define  CPU_TO_BE32(x) swap32(x)
+/** @} */
+
+
+/** \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but GCC's
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ *     at compile time);
+ *   - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ *     unknown at compile time).
+ *
+ * @{ */
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\
+                           ((uint16_t)(u16) << 8)))
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\
+                           ((uint32_t)Swap16((uint32_t)(u32)) << 16)))
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\
+                           ((uint64_t)Swap32((uint64_t)(u64)) << 32)))
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap16(u16) Swap16(u16)
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+#  define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))
+#else
+#  define swap32(u32) Swap32(u32)
+#endif
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+#  define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))
+#else
+#  define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\
+                         ((uint64_t)swap32((uint64_t)(u64)) << 32)))
+#endif
+
+/** @} */
+
+
+/** \name Target Abstraction
+ *
+ * @{ */
+
+#define _GLOBEXT_           extern      /**< extern storage-class specifier. */
+#define _CONST_TYPE_        const       /**< const type qualifier. */
+#define _MEM_TYPE_SLOW_                 /**< Slow memory type. */
+#define _MEM_TYPE_MEDFAST_              /**< Fairly fast memory type. */
+#define _MEM_TYPE_FAST_                 /**< Fast memory type. */
+
+#define memcmp_ram2ram      memcmp      /**< Target-specific memcmp of RAM to RAM. */
+#define memcmp_code2ram     memcmp      /**< Target-specific memcmp of RAM to NVRAM. */
+#define memcpy_ram2ram      memcpy      /**< Target-specific memcpy from RAM to RAM. */
+#define memcpy_code2ram     memcpy      /**< Target-specific memcpy from NVRAM to RAM. */
+
+/** @} */
+
+/**
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
+ * integer arithmetic.
+ *
+ * \param[in] a An integer
+ * \param[in] b Another integer
+ *
+ * \return (\a a / \a b) rounded up to the nearest integer.
+ */
+#define div_ceil(a, b)      (((a) + (b) - 1) / (b))
+
+#endif  /* #ifndef __ASSEMBLY__ */
+#ifdef __ICCARM__
+/** \name Compiler Keywords
+ *
+ * Port of some keywords from GCC to IAR Embedded Workbench.
+ *
+ * @{ */
+
+#define __asm__             asm
+#define __inline__          inline
+#define __volatile__
+
+/** @} */
+
+#endif
+
+#define FUNC_PTR                            void *
+/**
+ * \def unused
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define unused(v)          do { (void)(v); } while(0)
+
+/* Define RAMFUNC attribute */
+#if defined   ( __CC_ARM   ) /* Keil uVision 4 */
+#   define RAMFUNC __attribute__ ((section(".ramfunc")))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+#   define RAMFUNC __ramfunc
+#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
+#   define RAMFUNC __attribute__ ((section(".ramfunc")))
+#endif
+
+/* Define OPTIMIZE_HIGH attribute */
+#if defined   ( __CC_ARM   ) /* Keil uVision 4 */
+#   define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+#   define OPTIMIZE_HIGH _Pragma("optimize=high")
+#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
+#   define OPTIMIZE_HIGH __attribute__((optimize("s")))
+#endif
+#define PASS      0
+#define FAIL      1
+#define LOW       0
+#define HIGH      1
+
+typedef int8_t                  S8 ;  //!< 8-bit signed integer.
+typedef uint8_t                 U8 ;  //!< 8-bit unsigned integer.
+typedef int16_t                 S16;  //!< 16-bit signed integer.
+typedef uint16_t                U16;  //!< 16-bit unsigned integer.
+typedef int32_t                 S32;  //!< 32-bit signed integer.
+typedef uint32_t                U32;  //!< 32-bit unsigned integer.
+typedef int64_t                 S64;  //!< 64-bit signed integer.
+typedef uint64_t                U64;  //!< 64-bit unsigned integer.
+typedef float                   F32;  //!< 32-bit floating-point number.
+typedef double                  F64;  //!< 64-bit floating-point number.
+
+#define  MSB(u16)       (((U8  *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define  LSB(u16)       (((U8  *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+#define  MSH(u32)       (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
+#define  LSH(u32)       (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
+#define  MSB0W(u32)     (((U8  *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+#define  MSB1W(u32)     (((U8  *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define  MSB2W(u32)     (((U8  *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define  MSB3W(u32)     (((U8  *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define  LSB3W(u32)     MSB0W(u32)           //!< Least significant byte of 4th rank of \a u32.
+#define  LSB2W(u32)     MSB1W(u32)           //!< Least significant byte of 3rd rank of \a u32.
+#define  LSB1W(u32)     MSB2W(u32)           //!< Least significant byte of 2nd rank of \a u32.
+#define  LSB0W(u32)     MSB3W(u32)           //!< Least significant byte of 1st rank of \a u32.
+
+#define  MSW(u64)       (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
+#define  LSW(u64)       (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
+#define  MSH0(u64)      (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
+#define  MSH1(u64)      (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
+#define  MSH2(u64)      (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
+#define  MSH3(u64)      (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
+#define  LSH3(u64)      MSH0(u64)            //!< Least significant half-word of 4th rank of \a u64.
+#define  LSH2(u64)      MSH1(u64)            //!< Least significant half-word of 3rd rank of \a u64.
+#define  LSH1(u64)      MSH2(u64)            //!< Least significant half-word of 2nd rank of \a u64.
+#define  LSH0(u64)      MSH3(u64)            //!< Least significant half-word of 1st rank of \a u64.
+#define  MSB0D(u64)     (((U8  *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
+#define  MSB1D(u64)     (((U8  *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
+#define  MSB2D(u64)     (((U8  *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
+#define  MSB3D(u64)     (((U8  *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
+#define  MSB4D(u64)     (((U8  *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
+#define  MSB5D(u64)     (((U8  *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
+#define  MSB6D(u64)     (((U8  *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
+#define  MSB7D(u64)     (((U8  *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
+#define  LSB7D(u64)     MSB0D(u64)           //!< Least significant byte of 8th rank of \a u64.
+#define  LSB6D(u64)     MSB1D(u64)           //!< Least significant byte of 7th rank of \a u64.
+#define  LSB5D(u64)     MSB2D(u64)           //!< Least significant byte of 6th rank of \a u64.
+#define  LSB4D(u64)     MSB3D(u64)           //!< Least significant byte of 5th rank of \a u64.
+#define  LSB3D(u64)     MSB4D(u64)           //!< Least significant byte of 4th rank of \a u64.
+#define  LSB2D(u64)     MSB5D(u64)           //!< Least significant byte of 3rd rank of \a u64.
+#define  LSB1D(u64)     MSB6D(u64)           //!< Least significant byte of 2nd rank of \a u64.
+#define  LSB0D(u64)     MSB7D(u64)           //!< Least significant byte of 1st rank of \a u64.
+
+#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.
+
+#if defined(__ICCARM__)
+#define SHORTENUM           __packed
+#elif defined(__GNUC__)
+#define SHORTENUM           __attribute__((packed))
+#endif
+
+/* No operation */
+#if defined(__ICCARM__)
+#define nop()               __no_operation()
+#elif defined(__GNUC__)
+#define nop()               __NOP()
+#endif
+
+#define FLASH_DECLARE(x)  const x
+#define FLASH_EXTERN(x) extern const x
+#define PGM_READ_BYTE(x) *(x)
+#define PGM_READ_WORD(x) *(x)
+#define MEMCPY_ENDIAN memcpy
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
+
+/*Defines the Flash Storage for the request and response of MAC*/
+#define CMD_ID_OCTET    (0)
+
+/* Converting of values from CPU endian to little endian. */
+#define CPU_ENDIAN_TO_LE16(x)   (x)
+#define CPU_ENDIAN_TO_LE32(x)   (x)
+#define CPU_ENDIAN_TO_LE64(x)   (x)
+
+/* Converting of values from little endian to CPU endian. */
+#define LE16_TO_CPU_ENDIAN(x)   (x)
+#define LE32_TO_CPU_ENDIAN(x)   (x)
+#define LE64_TO_CPU_ENDIAN(x)   (x)
+
+/* Converting of constants from little endian to CPU endian. */
+#define CLE16_TO_CPU_ENDIAN(x)  (x)
+#define CLE32_TO_CPU_ENDIAN(x)  (x)
+#define CLE64_TO_CPU_ENDIAN(x)  (x)
+
+/* Converting of constants from CPU endian to little endian. */
+#define CCPU_ENDIAN_TO_LE16(x)  (x)
+#define CCPU_ENDIAN_TO_LE32(x)  (x)
+#define CCPU_ENDIAN_TO_LE64(x)  (x)
+
+#define ADDR_COPY_DST_SRC_16(dst, src)  ((dst) = (src))
+#define ADDR_COPY_DST_SRC_64(dst, src)  ((dst) = (src))
+
+/**
+ * @brief Converts a 64-Bit value into  a 8 Byte array
+ *
+ * @param[in] value 64-Bit value
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
+{
+    uint8_t index = 0;
+
+    while (index < 8)
+    {
+        data[index++] = value & 0xFF;
+        value = value >> 8;
+    }
+}
+
+/**
+ * @brief Converts a 16-Bit value into  a 2 Byte array
+ *
+ * @param[in] value 16-Bit value
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+    data[0] = value & 0xFF;
+    data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+    data[0] = value & 0xFF;
+    data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
+{
+    data[0] = value & 0xFF;
+    data[1] = (value >> 8) & 0xFF;
+}
+
+/*
+ * @brief Converts a 2 Byte array into a 16-Bit value
+ *
+ * @param data Specifies the pointer to the 2 Byte array
+ *
+ * @return 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
+{
+    return (data[0] | ((uint16_t)data[1] << 8));
+}
+
+/* Converts a 4 Byte array into a 32-Bit value */
+static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
+{
+	union
+	{
+		uint32_t u32;
+		uint8_t u8[4];
+	}long_addr;
+	uint8_t index;
+	for (index = 0; index < 4; index++)
+	{
+		long_addr.u8[index] = *data++;
+	}
+	return long_addr.u32;
+}
+
+/**
+ * @brief Converts a 8 Byte array into a 64-Bit value
+ *
+ * @param data Specifies the pointer to the 8 Byte array
+ *
+ * @return 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
+{
+    union
+    {
+        uint64_t u64;
+        uint8_t u8[8];
+    } long_addr;
+
+    uint8_t index;
+
+    for (index = 0; index < 8; index++)
+    {
+        long_addr.u8[index] = *data++;
+    }
+
+    return long_addr.u64;
+}
+
+/** @} */
+
+#endif /* UTILS_COMPILER_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/header_files/io.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/header_files/io.h
index 73e73a3..7908b72 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/header_files/io.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/header_files/io.h
@@ -1,115 +1,115 @@
-/**
- * \file
- *
- * \brief Arch file for SAM0.
- *
- * This file defines common SAM0 series.
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _SAM_IO_
-#define _SAM_IO_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-/* SAM D20 family */
-#if (SAMD20)
-#  include "samd20.h"
-#endif
-
-#if (SAMD21)
-#  include "samd21.h"
-#endif
-
-#if (SAMR21)
-#  include "samr21.h"
-#endif
-
-#if (SAMD09)
-#  include "samd09.h"
-#endif
-
-#if (SAMD10)
-#  include "samd10.h"
-#endif
-
-#if (SAMD11)
-#  include "samd11.h"
-#endif
-
-#if (SAML21)
-#  include "saml21.h"
-#endif
-
-#if (SAMR30)
-#  include "samr30.h"
-#endif
-
-#if (SAMR34)
-#  include "samr34.h"
-#endif
-
-#if (SAMR35)
-#  include "samr35.h"
-#endif
-
-#if (SAML22)
-#  include "saml22.h"
-#endif
-
-#if (SAMDA1)
-#  include "samda1.h"
-#endif
-
-#if (SAMC20)
-#  include "samc20.h"
-#endif
-
-#if (SAMC21)
-#  include "samc21.h"
-#endif
-
-#if (SAMHA1)
-#  include "samha1.h"
-#endif
-
-#if (SAMHA0)
-#  include "samha0.h"
-#endif
-
-#if (SAMB11)
-#  include "samb11.h"
-#endif
-
-#endif /* _SAM_IO_ */
+/**
+ * \file
+ *
+ * \brief Arch file for SAM0.
+ *
+ * This file defines common SAM0 series.
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _SAM_IO_
+#define _SAM_IO_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/* SAM D20 family */
+#if (SAMD20)
+#  include "samd20.h"
+#endif
+
+#if (SAMD21)
+#  include "samd21.h"
+#endif
+
+#if (SAMR21)
+#  include "samr21.h"
+#endif
+
+#if (SAMD09)
+#  include "samd09.h"
+#endif
+
+#if (SAMD10)
+#  include "samd10.h"
+#endif
+
+#if (SAMD11)
+#  include "samd11.h"
+#endif
+
+#if (SAML21)
+#  include "saml21.h"
+#endif
+
+#if (SAMR30)
+#  include "samr30.h"
+#endif
+
+#if (SAMR34)
+#  include "samr34.h"
+#endif
+
+#if (SAMR35)
+#  include "samr35.h"
+#endif
+
+#if (SAML22)
+#  include "saml22.h"
+#endif
+
+#if (SAMDA1)
+#  include "samda1.h"
+#endif
+
+#if (SAMC20)
+#  include "samc20.h"
+#endif
+
+#if (SAMC21)
+#  include "samc21.h"
+#endif
+
+#if (SAMHA1)
+#  include "samha1.h"
+#endif
+
+#if (SAMHA0)
+#  include "samha0.h"
+#endif
+
+#if (SAMB11)
+#  include "samb11.h"
+#endif
+
+#endif /* _SAM_IO_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld b/D21_ADC_with_DMA/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
index 17395a3..89dc411 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
@@ -1,157 +1,157 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21J18A
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- *    Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/make/Makefile.sam.in b/D21_ADC_with_DMA/src/ASF/sam0/utils/make/Makefile.sam.in
index f72b845..dcc4cd7 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/make/Makefile.sam.in
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/make/Makefile.sam.in
@@ -1,492 +1,492 @@
-# List of available make goals:
-#
-# all                     Default target, builds the project
-# clean                   Clean up the project
-# rebuild                 Rebuild the project
-# debug_flash             Builds the project and debug in flash
-# debug_sram              Builds the project and debug in sram
-#
-# doc                     Build the documentation
-# cleandoc                Clean up the documentation
-# rebuilddoc              Rebuild the documentation
-#
-# \file
-#
-# Copyright (c) 2011 - 2018 Microchip Technology Inc. and its subsidiaries.
-#
-# \asf_license_start
-#
-# \page License
-#
-# Subject to your compliance with these terms, you may use Microchip
-# software and any derivatives exclusively with Microchip products.
-# It is your responsibility to comply with third party license terms applicable
-# to your use of third party software (including open source software) that
-# may accompany Microchip software.
-#
-# THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
-# WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
-# INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
-# AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
-# LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
-# LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
-# SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
-# POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
-# ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
-# RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
-# THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
-#
-# \asf_license_stop
-#
-
-# Include the config.mk file from the current working path, e.g., where the
-# user called make.
-include config.mk
-
-# Tool to use to generate documentation from the source code
-DOCGEN          ?= doxygen
-
-# Look for source files relative to the top-level source directory
-VPATH           := $(PRJ_PATH)
-
-# Output target file
-project_type    := $(PROJECT_TYPE)
-
-# Output target file
-ifeq ($(project_type),flash)
-target          := $(TARGET_FLASH)
-linker_script   := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)
-debug_script    := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)
-else
-target          := $(TARGET_SRAM)
-linker_script   := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)
-debug_script    := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)
-endif
-
-# Output project name (target name minus suffix)
-project         := $(basename $(target))
-
-# Output target file (typically ELF or static library)
-ifeq ($(suffix $(target)),.a)
-target_type     := lib
-else
-ifeq ($(suffix $(target)),.elf)
-target_type     := elf
-else
-$(error "Target type $(target_type) is not supported")
-endif
-endif
-
-# Allow override of operating system detection. The user can add OS=Linux or
-# OS=Windows on the command line to explicit set the host OS.
-#
-# This allows to work around broken uname utility on certain systems.
-ifdef OS
-  ifeq ($(strip $(OS)), Linux)
-    os_type     := Linux
-  endif
-  ifeq ($(strip $(OS)), Windows)
-    os_type     := windows32_64
-  endif
-endif
-
-os_type         ?= $(strip $(shell uname))
-
-ifeq ($(os_type),windows32)
-os              := Windows
-else
-ifeq ($(os_type),windows64)
-os              := Windows
-else
-ifeq ($(os_type),windows32_64)
-os              ?= Windows
-else
-ifeq ($(os_type),)
-os              := Windows
-else
-# Default to Linux style operating system. Both Cygwin and mingw are fully
-# compatible (for this Makefile) with Linux.
-os              := Linux
-endif
-endif
-endif
-endif
-
-# Output documentation directory and configuration file.
-docdir          := ../doxygen/html
-doccfg          := ../doxygen/doxyfile.doxygen
-
-CROSS           ?= arm-none-eabi-
-AR              := $(CROSS)ar
-AS              := $(CROSS)as
-CC              := $(CROSS)gcc
-CPP             := $(CROSS)gcc -E
-CXX             := $(CROSS)g++
-LD              := $(CROSS)g++
-NM              := $(CROSS)nm
-OBJCOPY         := $(CROSS)objcopy
-OBJDUMP         := $(CROSS)objdump
-SIZE            := $(CROSS)size
-GDB             := $(CROSS)gdb
-
-RM              := rm
-ifeq ($(os),Windows)
-RMDIR           := rmdir /S /Q
-else
-RMDIR           := rmdir -p --ignore-fail-on-non-empty
-endif
-
-# On Windows, we need to override the shell to force the use of cmd.exe
-ifeq ($(os),Windows)
-SHELL           := cmd
-endif
-
-# Strings for beautifying output
-MSG_CLEAN_FILES         = "RM      *.o *.d"
-MSG_CLEAN_DIRS          = "RMDIR   $(strip $(clean-dirs))"
-MSG_CLEAN_DOC           = "RMDIR   $(docdir)"
-MSG_MKDIR               = "MKDIR   $(dir $@)"
-
-MSG_INFO                = "INFO    "
-MSG_PREBUILD            = "PREBUILD  $(PREBUILD_CMD)"
-MSG_POSTBUILD           = "POSTBUILD $(POSTBUILD_CMD)"
-
-MSG_ARCHIVING           = "AR      $@"
-MSG_ASSEMBLING          = "AS      $@"
-MSG_BINARY_IMAGE        = "OBJCOPY $@"
-MSG_COMPILING           = "CC      $@"
-MSG_COMPILING_CXX       = "CXX     $@"
-MSG_EXTENDED_LISTING    = "OBJDUMP $@"
-MSG_IHEX_IMAGE          = "OBJCOPY $@"
-MSG_LINKING             = "LN      $@"
-MSG_PREPROCESSING       = "CPP     $@"
-MSG_SIZE                = "SIZE    $@"
-MSG_SYMBOL_TABLE        = "NM      $@"
-
-MSG_GENERATING_DOC      = "DOXYGEN $(docdir)"
-
-# Don't use make's built-in rules and variables
-MAKEFLAGS       += -rR
-
-# Don't print 'Entering directory ...'
-MAKEFLAGS       += --no-print-directory
-
-# Function for reversing the order of a list
-reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
-
-# Hide command output by default, but allow the user to override this
-# by adding V=1 on the command line.
-#
-# This is inspired by the Kbuild system used by the Linux kernel.
-ifdef V
-  ifeq ("$(origin V)", "command line")
-    VERBOSE = $(V)
-  endif
-endif
-ifndef VERBOSE
-  VERBOSE = 0
-endif
-
-ifeq ($(VERBOSE), 1)
-  Q =
-else
-  Q = @
-endif
-
-arflags-gnu-y           := $(ARFLAGS)
-asflags-gnu-y           := $(ASFLAGS)
-cflags-gnu-y            := $(CFLAGS)
-cxxflags-gnu-y          := $(CXXFLAGS)
-cppflags-gnu-y          := $(CPPFLAGS)
-cpuflags-gnu-y          :=
-dbgflags-gnu-y          := $(DBGFLAGS)
-libflags-gnu-y          := $(foreach LIB,$(LIBS),-l$(LIB))
-ldflags-gnu-y           := $(LDFLAGS)
-flashflags-gnu-y        :=
-clean-files             :=
-clean-dirs              :=
-
-clean-files             += $(wildcard $(target) $(project).map)
-clean-files             += $(wildcard $(project).hex $(project).bin)
-clean-files             += $(wildcard $(project).lss $(project).sym)
-clean-files             += $(wildcard $(build))
-
-# Use pipes instead of temporary files for communication between processes
-cflags-gnu-y    += -pipe
-asflags-gnu-y   += -pipe
-ldflags-gnu-y   += -pipe
-
-# Archiver flags.
-arflags-gnu-y   += rcs
-
-# Always enable warnings. And be very careful about implicit
-# declarations.
-cflags-gnu-y    += -Wall -Wstrict-prototypes -Wmissing-prototypes
-cflags-gnu-y    += -Werror-implicit-function-declaration
-cxxflags-gnu-y  += -Wall
-# IAR doesn't allow arithmetic on void pointers, so warn about that.
-cflags-gnu-y    += -Wpointer-arith
-cxxflags-gnu-y  += -Wpointer-arith
-
-# Preprocessor flags.
-cppflags-gnu-y  += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
-asflags-gnu-y   += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
-
-# CPU specific flags.
-cpuflags-gnu-y  += -mcpu=$(ARCH) -mthumb -D=__$(PART)__
-
-# Dependency file flags.
-depflags        = -MD -MP -MQ $@
-
-# Debug specific flags.
-ifdef BUILD_DEBUG_LEVEL
-dbgflags-gnu-y  += -g$(BUILD_DEBUG_LEVEL)
-else
-dbgflags-gnu-y  += -g3
-endif
-
-# Optimization specific flags.
-ifdef BUILD_OPTIMIZATION
-optflags-gnu-y  = -O$(BUILD_OPTIMIZATION)
-else
-optflags-gnu-y  = $(OPTIMIZATION)
-endif
-
-# Always preprocess assembler files.
-asflags-gnu-y   += -x assembler-with-cpp
-# Compile C files using the GNU99 standard.
-cflags-gnu-y    += -std=gnu99
-# Compile C++ files using the GNU++98 standard.
-cxxflags-gnu-y  += -std=gnu++98
-
-# Don't use strict aliasing (very common in embedded applications).
-cflags-gnu-y    += -fno-strict-aliasing
-cxxflags-gnu-y  += -fno-strict-aliasing
-
-# Separate each function and data into its own separate section to allow
-# garbage collection of unused sections.
-cflags-gnu-y    += -ffunction-sections -fdata-sections
-cxxflags-gnu-y  += -ffunction-sections -fdata-sections
-
-# Various cflags.
-cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
-cflags-gnu-y += -Wmain -Wparentheses
-cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
-cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
-cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings
-cflags-gnu-y += -Wsign-compare -Waggregate-return
-cflags-gnu-y += -Wmissing-declarations
-cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
-cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long
-cflags-gnu-y += -Wunreachable-code
-cflags-gnu-y += -Wcast-align
-cflags-gnu-y += --param max-inline-insns-single=500
-
-# To reduce application size use only integer printf function.
-cflags-gnu-y += -Dprintf=iprintf
-
-# Use newlib-nano to reduce application size
-ldflags-gnu-y   += --specs=nano.specs
-
-# Garbage collect unreferred sections when linking.
-ldflags-gnu-y   += -Wl,--gc-sections
-
-# Use the linker script if provided by the project.
-ifneq ($(strip $(linker_script)),)
-ldflags-gnu-y   += -Wl,-T $(linker_script)
-endif
-
-# Output a link map file and a cross reference table
-ldflags-gnu-y   += -Wl,-Map=$(project).map,--cref
-
-# Add library search paths relative to the top level directory.
-ldflags-gnu-y   += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
-
-a_flags  = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
-c_flags  = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
-cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
-l_flags  = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
-ar_flags = $(arflags-gnu-y)
-
-# Source files list and part informations must already be included before
-# running this makefile
-
-# If a custom build directory is specified, use it -- force trailing / in directory name.
-ifdef BUILD_DIR
-	build-dir       := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
-else
-	build-dir        =
-endif
-
-# Create object files list from source files list.
-obj-y                   := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
-# Create dependency files list from source files list.
-dep-files               := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
-
-clean-files             += $(wildcard $(obj-y))
-clean-files             += $(dep-files)
-
-clean-dirs              += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
-
-# Default target.
-.PHONY: all
-ifeq ($(project_type),all)
-all:
-	$(MAKE) all PROJECT_TYPE=flash
-	$(MAKE) all PROJECT_TYPE=sram
-else
-ifeq ($(target_type),lib)
-all: $(target) $(project).lss $(project).sym
-else
-ifeq ($(target_type),elf)
-all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
-endif
-endif
-endif
-
-prebuild:
-ifneq ($(strip $(PREBUILD_CMD)),)
-	@echo $(MSG_PREBUILD)
-	$(Q)$(PREBUILD_CMD)
-endif
-
-postbuild:
-ifneq ($(strip $(POSTBUILD_CMD)),)
-	@echo $(MSG_POSTBUILD)
-	$(Q)$(POSTBUILD_CMD)
-endif
-
-# Clean up the project.
-.PHONY: clean
-clean:
-	@$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
-	$(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
-	@$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
-# Remove created directories, and make sure we only remove existing
-# directories, since recursive rmdir might help us a bit on the way.
-ifeq ($(os),Windows)
-	$(Q)$(if $(strip $(clean-dirs)),                        \
-			$(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
-else
-	$(Q)$(if $(strip $(clean-dirs)),                        \
-		for directory in $(strip $(clean-dirs)); do     \
-			if [ -d "$$directory" ]; then           \
-				$(RMDIR) $$directory;           \
-			fi                                      \
-		done                                            \
-	)
-endif
-
-# Rebuild the project.
-.PHONY: rebuild
-rebuild: clean all
-
-# Debug the project in flash.
-.PHONY: debug_flash
-debug_flash: all
-	$(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)
-
-# Debug the project in sram.
-.PHONY: debug_sram
-debug_sram: all
-	$(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)
-
-.PHONY: objfiles
-objfiles: $(obj-y)
-
-# Create object files from C source files.
-$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
-	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
-	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
-	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
-	@echo $(MSG_COMPILING)
-	$(Q)$(CC) $(c_flags) -c $< -o $@
-
-# Create object files from C++ source files.
-$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
-	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
-	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
-	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
-	@echo $(MSG_COMPILING_CXX)
-	$(Q)$(CXX) $(cxx_flags) -c $< -o $@
-
-# Preprocess and assemble: create object files from assembler source files.
-$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
-	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
-	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
-	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
-	@echo $(MSG_ASSEMBLING)
-	$(Q)$(CC) $(a_flags) -c $< -o $@
-
-# Include all dependency files to add depedency to all header files in use.
-include $(dep-files)
-
-ifeq ($(target_type),lib)
-# Archive object files into an archive
-$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
-	@echo $(MSG_ARCHIVING)
-	$(Q)$(AR) $(ar_flags) $@ $(obj-y)
-	@echo $(MSG_SIZE)
-	$(Q)$(SIZE) -Bxt $@
-else
-ifeq ($(target_type),elf)
-# Link the object files into an ELF file. Also make sure the target is rebuilt
-# if the common Makefile.sam.in or project config.mk is changed.
-$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)
-	@echo $(MSG_LINKING)
-	$(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
-	@echo $(MSG_SIZE)
-	$(Q)$(SIZE) -Ax $@
-	$(Q)$(SIZE) -Bx $@
-endif
-endif
-
-# Create extended function listing from target output file.
-%.lss: $(target)
-	@echo $(MSG_EXTENDED_LISTING)
-	$(Q)$(OBJDUMP) -h -S $< > $@
-
-# Create symbol table from target output file.
-%.sym: $(target)
-	@echo $(MSG_SYMBOL_TABLE)
-	$(Q)$(NM) -n $< > $@
-
-# Create Intel HEX image from ELF output file.
-%.hex: $(target)
-	@echo $(MSG_IHEX_IMAGE)
-	$(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y)  $< $@
-
-# Create binary image from ELF output file.
-%.bin: $(target)
-	@echo $(MSG_BINARY_IMAGE)
-	$(Q)$(OBJCOPY) -O binary $< $@
-
-# Provide information about the detected host operating system.
-.SECONDARY: info-os
-info-os:
-	@echo $(MSG_INFO)$(os) build host detected
-
-# Build Doxygen generated documentation.
-.PHONY: doc
-doc:
-	@echo $(MSG_GENERATING_DOC)
-	$(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
-
-# Clean Doxygen generated documentation.
-.PHONY: cleandoc
-cleandoc:
-	@$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
-	$(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
-
-# Rebuild the Doxygen generated documentation.
-.PHONY: rebuilddoc
-rebuilddoc: cleandoc doc
+# List of available make goals:
+#
+# all                     Default target, builds the project
+# clean                   Clean up the project
+# rebuild                 Rebuild the project
+# debug_flash             Builds the project and debug in flash
+# debug_sram              Builds the project and debug in sram
+#
+# doc                     Build the documentation
+# cleandoc                Clean up the documentation
+# rebuilddoc              Rebuild the documentation
+#
+# \file
+#
+# Copyright (c) 2011 - 2018 Microchip Technology Inc. and its subsidiaries.
+#
+# \asf_license_start
+#
+# \page License
+#
+# Subject to your compliance with these terms, you may use Microchip
+# software and any derivatives exclusively with Microchip products.
+# It is your responsibility to comply with third party license terms applicable
+# to your use of third party software (including open source software) that
+# may accompany Microchip software.
+#
+# THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+# WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+# INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+# AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+# LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+# LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+# SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+# POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+# ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+# RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+# THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+#
+# \asf_license_stop
+#
+
+# Include the config.mk file from the current working path, e.g., where the
+# user called make.
+include config.mk
+
+# Tool to use to generate documentation from the source code
+DOCGEN          ?= doxygen
+
+# Look for source files relative to the top-level source directory
+VPATH           := $(PRJ_PATH)
+
+# Output target file
+project_type    := $(PROJECT_TYPE)
+
+# Output target file
+ifeq ($(project_type),flash)
+target          := $(TARGET_FLASH)
+linker_script   := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)
+debug_script    := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)
+else
+target          := $(TARGET_SRAM)
+linker_script   := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)
+debug_script    := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)
+endif
+
+# Output project name (target name minus suffix)
+project         := $(basename $(target))
+
+# Output target file (typically ELF or static library)
+ifeq ($(suffix $(target)),.a)
+target_type     := lib
+else
+ifeq ($(suffix $(target)),.elf)
+target_type     := elf
+else
+$(error "Target type $(target_type) is not supported")
+endif
+endif
+
+# Allow override of operating system detection. The user can add OS=Linux or
+# OS=Windows on the command line to explicit set the host OS.
+#
+# This allows to work around broken uname utility on certain systems.
+ifdef OS
+  ifeq ($(strip $(OS)), Linux)
+    os_type     := Linux
+  endif
+  ifeq ($(strip $(OS)), Windows)
+    os_type     := windows32_64
+  endif
+endif
+
+os_type         ?= $(strip $(shell uname))
+
+ifeq ($(os_type),windows32)
+os              := Windows
+else
+ifeq ($(os_type),windows64)
+os              := Windows
+else
+ifeq ($(os_type),windows32_64)
+os              ?= Windows
+else
+ifeq ($(os_type),)
+os              := Windows
+else
+# Default to Linux style operating system. Both Cygwin and mingw are fully
+# compatible (for this Makefile) with Linux.
+os              := Linux
+endif
+endif
+endif
+endif
+
+# Output documentation directory and configuration file.
+docdir          := ../doxygen/html
+doccfg          := ../doxygen/doxyfile.doxygen
+
+CROSS           ?= arm-none-eabi-
+AR              := $(CROSS)ar
+AS              := $(CROSS)as
+CC              := $(CROSS)gcc
+CPP             := $(CROSS)gcc -E
+CXX             := $(CROSS)g++
+LD              := $(CROSS)g++
+NM              := $(CROSS)nm
+OBJCOPY         := $(CROSS)objcopy
+OBJDUMP         := $(CROSS)objdump
+SIZE            := $(CROSS)size
+GDB             := $(CROSS)gdb
+
+RM              := rm
+ifeq ($(os),Windows)
+RMDIR           := rmdir /S /Q
+else
+RMDIR           := rmdir -p --ignore-fail-on-non-empty
+endif
+
+# On Windows, we need to override the shell to force the use of cmd.exe
+ifeq ($(os),Windows)
+SHELL           := cmd
+endif
+
+# Strings for beautifying output
+MSG_CLEAN_FILES         = "RM      *.o *.d"
+MSG_CLEAN_DIRS          = "RMDIR   $(strip $(clean-dirs))"
+MSG_CLEAN_DOC           = "RMDIR   $(docdir)"
+MSG_MKDIR               = "MKDIR   $(dir $@)"
+
+MSG_INFO                = "INFO    "
+MSG_PREBUILD            = "PREBUILD  $(PREBUILD_CMD)"
+MSG_POSTBUILD           = "POSTBUILD $(POSTBUILD_CMD)"
+
+MSG_ARCHIVING           = "AR      $@"
+MSG_ASSEMBLING          = "AS      $@"
+MSG_BINARY_IMAGE        = "OBJCOPY $@"
+MSG_COMPILING           = "CC      $@"
+MSG_COMPILING_CXX       = "CXX     $@"
+MSG_EXTENDED_LISTING    = "OBJDUMP $@"
+MSG_IHEX_IMAGE          = "OBJCOPY $@"
+MSG_LINKING             = "LN      $@"
+MSG_PREPROCESSING       = "CPP     $@"
+MSG_SIZE                = "SIZE    $@"
+MSG_SYMBOL_TABLE        = "NM      $@"
+
+MSG_GENERATING_DOC      = "DOXYGEN $(docdir)"
+
+# Don't use make's built-in rules and variables
+MAKEFLAGS       += -rR
+
+# Don't print 'Entering directory ...'
+MAKEFLAGS       += --no-print-directory
+
+# Function for reversing the order of a list
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
+
+# Hide command output by default, but allow the user to override this
+# by adding V=1 on the command line.
+#
+# This is inspired by the Kbuild system used by the Linux kernel.
+ifdef V
+  ifeq ("$(origin V)", "command line")
+    VERBOSE = $(V)
+  endif
+endif
+ifndef VERBOSE
+  VERBOSE = 0
+endif
+
+ifeq ($(VERBOSE), 1)
+  Q =
+else
+  Q = @
+endif
+
+arflags-gnu-y           := $(ARFLAGS)
+asflags-gnu-y           := $(ASFLAGS)
+cflags-gnu-y            := $(CFLAGS)
+cxxflags-gnu-y          := $(CXXFLAGS)
+cppflags-gnu-y          := $(CPPFLAGS)
+cpuflags-gnu-y          :=
+dbgflags-gnu-y          := $(DBGFLAGS)
+libflags-gnu-y          := $(foreach LIB,$(LIBS),-l$(LIB))
+ldflags-gnu-y           := $(LDFLAGS)
+flashflags-gnu-y        :=
+clean-files             :=
+clean-dirs              :=
+
+clean-files             += $(wildcard $(target) $(project).map)
+clean-files             += $(wildcard $(project).hex $(project).bin)
+clean-files             += $(wildcard $(project).lss $(project).sym)
+clean-files             += $(wildcard $(build))
+
+# Use pipes instead of temporary files for communication between processes
+cflags-gnu-y    += -pipe
+asflags-gnu-y   += -pipe
+ldflags-gnu-y   += -pipe
+
+# Archiver flags.
+arflags-gnu-y   += rcs
+
+# Always enable warnings. And be very careful about implicit
+# declarations.
+cflags-gnu-y    += -Wall -Wstrict-prototypes -Wmissing-prototypes
+cflags-gnu-y    += -Werror-implicit-function-declaration
+cxxflags-gnu-y  += -Wall
+# IAR doesn't allow arithmetic on void pointers, so warn about that.
+cflags-gnu-y    += -Wpointer-arith
+cxxflags-gnu-y  += -Wpointer-arith
+
+# Preprocessor flags.
+cppflags-gnu-y  += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
+asflags-gnu-y   += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
+
+# CPU specific flags.
+cpuflags-gnu-y  += -mcpu=$(ARCH) -mthumb -D=__$(PART)__
+
+# Dependency file flags.
+depflags        = -MD -MP -MQ $@
+
+# Debug specific flags.
+ifdef BUILD_DEBUG_LEVEL
+dbgflags-gnu-y  += -g$(BUILD_DEBUG_LEVEL)
+else
+dbgflags-gnu-y  += -g3
+endif
+
+# Optimization specific flags.
+ifdef BUILD_OPTIMIZATION
+optflags-gnu-y  = -O$(BUILD_OPTIMIZATION)
+else
+optflags-gnu-y  = $(OPTIMIZATION)
+endif
+
+# Always preprocess assembler files.
+asflags-gnu-y   += -x assembler-with-cpp
+# Compile C files using the GNU99 standard.
+cflags-gnu-y    += -std=gnu99
+# Compile C++ files using the GNU++98 standard.
+cxxflags-gnu-y  += -std=gnu++98
+
+# Don't use strict aliasing (very common in embedded applications).
+cflags-gnu-y    += -fno-strict-aliasing
+cxxflags-gnu-y  += -fno-strict-aliasing
+
+# Separate each function and data into its own separate section to allow
+# garbage collection of unused sections.
+cflags-gnu-y    += -ffunction-sections -fdata-sections
+cxxflags-gnu-y  += -ffunction-sections -fdata-sections
+
+# Various cflags.
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+cflags-gnu-y += -Wmain -Wparentheses
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings
+cflags-gnu-y += -Wsign-compare -Waggregate-return
+cflags-gnu-y += -Wmissing-declarations
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long
+cflags-gnu-y += -Wunreachable-code
+cflags-gnu-y += -Wcast-align
+cflags-gnu-y += --param max-inline-insns-single=500
+
+# To reduce application size use only integer printf function.
+cflags-gnu-y += -Dprintf=iprintf
+
+# Use newlib-nano to reduce application size
+ldflags-gnu-y   += --specs=nano.specs
+
+# Garbage collect unreferred sections when linking.
+ldflags-gnu-y   += -Wl,--gc-sections
+
+# Use the linker script if provided by the project.
+ifneq ($(strip $(linker_script)),)
+ldflags-gnu-y   += -Wl,-T $(linker_script)
+endif
+
+# Output a link map file and a cross reference table
+ldflags-gnu-y   += -Wl,-Map=$(project).map,--cref
+
+# Add library search paths relative to the top level directory.
+ldflags-gnu-y   += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
+
+a_flags  = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
+c_flags  = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
+l_flags  = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
+ar_flags = $(arflags-gnu-y)
+
+# Source files list and part informations must already be included before
+# running this makefile
+
+# If a custom build directory is specified, use it -- force trailing / in directory name.
+ifdef BUILD_DIR
+	build-dir       := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
+else
+	build-dir        =
+endif
+
+# Create object files list from source files list.
+obj-y                   := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
+# Create dependency files list from source files list.
+dep-files               := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
+
+clean-files             += $(wildcard $(obj-y))
+clean-files             += $(dep-files)
+
+clean-dirs              += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
+
+# Default target.
+.PHONY: all
+ifeq ($(project_type),all)
+all:
+	$(MAKE) all PROJECT_TYPE=flash
+	$(MAKE) all PROJECT_TYPE=sram
+else
+ifeq ($(target_type),lib)
+all: $(target) $(project).lss $(project).sym
+else
+ifeq ($(target_type),elf)
+all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
+endif
+endif
+endif
+
+prebuild:
+ifneq ($(strip $(PREBUILD_CMD)),)
+	@echo $(MSG_PREBUILD)
+	$(Q)$(PREBUILD_CMD)
+endif
+
+postbuild:
+ifneq ($(strip $(POSTBUILD_CMD)),)
+	@echo $(MSG_POSTBUILD)
+	$(Q)$(POSTBUILD_CMD)
+endif
+
+# Clean up the project.
+.PHONY: clean
+clean:
+	@$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
+	$(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
+	@$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
+# Remove created directories, and make sure we only remove existing
+# directories, since recursive rmdir might help us a bit on the way.
+ifeq ($(os),Windows)
+	$(Q)$(if $(strip $(clean-dirs)),                        \
+			$(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
+else
+	$(Q)$(if $(strip $(clean-dirs)),                        \
+		for directory in $(strip $(clean-dirs)); do     \
+			if [ -d "$$directory" ]; then           \
+				$(RMDIR) $$directory;           \
+			fi                                      \
+		done                                            \
+	)
+endif
+
+# Rebuild the project.
+.PHONY: rebuild
+rebuild: clean all
+
+# Debug the project in flash.
+.PHONY: debug_flash
+debug_flash: all
+	$(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)
+
+# Debug the project in sram.
+.PHONY: debug_sram
+debug_sram: all
+	$(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)
+
+.PHONY: objfiles
+objfiles: $(obj-y)
+
+# Create object files from C source files.
+$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_COMPILING)
+	$(Q)$(CC) $(c_flags) -c $< -o $@
+
+# Create object files from C++ source files.
+$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_COMPILING_CXX)
+	$(Q)$(CXX) $(cxx_flags) -c $< -o $@
+
+# Preprocess and assemble: create object files from assembler source files.
+$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
+	$(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+	$(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+	$(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+	@echo $(MSG_ASSEMBLING)
+	$(Q)$(CC) $(a_flags) -c $< -o $@
+
+# Include all dependency files to add depedency to all header files in use.
+include $(dep-files)
+
+ifeq ($(target_type),lib)
+# Archive object files into an archive
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
+	@echo $(MSG_ARCHIVING)
+	$(Q)$(AR) $(ar_flags) $@ $(obj-y)
+	@echo $(MSG_SIZE)
+	$(Q)$(SIZE) -Bxt $@
+else
+ifeq ($(target_type),elf)
+# Link the object files into an ELF file. Also make sure the target is rebuilt
+# if the common Makefile.sam.in or project config.mk is changed.
+$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)
+	@echo $(MSG_LINKING)
+	$(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
+	@echo $(MSG_SIZE)
+	$(Q)$(SIZE) -Ax $@
+	$(Q)$(SIZE) -Bx $@
+endif
+endif
+
+# Create extended function listing from target output file.
+%.lss: $(target)
+	@echo $(MSG_EXTENDED_LISTING)
+	$(Q)$(OBJDUMP) -h -S $< > $@
+
+# Create symbol table from target output file.
+%.sym: $(target)
+	@echo $(MSG_SYMBOL_TABLE)
+	$(Q)$(NM) -n $< > $@
+
+# Create Intel HEX image from ELF output file.
+%.hex: $(target)
+	@echo $(MSG_IHEX_IMAGE)
+	$(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y)  $< $@
+
+# Create binary image from ELF output file.
+%.bin: $(target)
+	@echo $(MSG_BINARY_IMAGE)
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+# Provide information about the detected host operating system.
+.SECONDARY: info-os
+info-os:
+	@echo $(MSG_INFO)$(os) build host detected
+
+# Build Doxygen generated documentation.
+.PHONY: doc
+doc:
+	@echo $(MSG_GENERATING_DOC)
+	$(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
+
+# Clean Doxygen generated documentation.
+.PHONY: cleandoc
+cleandoc:
+	@$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
+	$(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
+
+# Rebuild the Doxygen generated documentation.
+.PHONY: rebuilddoc
+rebuilddoc: cleandoc doc
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrecursion.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrecursion.h
index 6e6a1d2..dc628e6 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrecursion.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrecursion.h
@@ -1,588 +1,588 @@
-/**
- * \file
- *
- * \brief Preprocessor macro recursion utils.
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _MRECURSION_H_
-#define _MRECURSION_H_
-
-/**
- * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion
- *
- * \ingroup group_sam0_utils
- *
- * @{
- */
-
-#include "preprocessor.h"
-
-#define DEC_256                                   255
-#define DEC_255                                   254
-#define DEC_254                                   253
-#define DEC_253                                   252
-#define DEC_252                                   251
-#define DEC_251                                   250
-#define DEC_250                                   249
-#define DEC_249                                   248
-#define DEC_248                                   247
-#define DEC_247                                   246
-#define DEC_246                                   245
-#define DEC_245                                   244
-#define DEC_244                                   243
-#define DEC_243                                   242
-#define DEC_242                                   241
-#define DEC_241                                   240
-#define DEC_240                                   239
-#define DEC_239                                   238
-#define DEC_238                                   237
-#define DEC_237                                   236
-#define DEC_236                                   235
-#define DEC_235                                   234
-#define DEC_234                                   233
-#define DEC_233                                   232
-#define DEC_232                                   231
-#define DEC_231                                   230
-#define DEC_230                                   229
-#define DEC_229                                   228
-#define DEC_228                                   227
-#define DEC_227                                   226
-#define DEC_226                                   225
-#define DEC_225                                   224
-#define DEC_224                                   223
-#define DEC_223                                   222
-#define DEC_222                                   221
-#define DEC_221                                   220
-#define DEC_220                                   219
-#define DEC_219                                   218
-#define DEC_218                                   217
-#define DEC_217                                   216
-#define DEC_216                                   215
-#define DEC_215                                   214
-#define DEC_214                                   213
-#define DEC_213                                   212
-#define DEC_212                                   211
-#define DEC_211                                   210
-#define DEC_210                                   209
-#define DEC_209                                   208
-#define DEC_208                                   207
-#define DEC_207                                   206
-#define DEC_206                                   205
-#define DEC_205                                   204
-#define DEC_204                                   203
-#define DEC_203                                   202
-#define DEC_202                                   201
-#define DEC_201                                   200
-#define DEC_200                                   199
-#define DEC_199                                   198
-#define DEC_198                                   197
-#define DEC_197                                   196
-#define DEC_196                                   195
-#define DEC_195                                   194
-#define DEC_194                                   193
-#define DEC_193                                   192
-#define DEC_192                                   191
-#define DEC_191                                   190
-#define DEC_190                                   189
-#define DEC_189                                   188
-#define DEC_188                                   187
-#define DEC_187                                   186
-#define DEC_186                                   185
-#define DEC_185                                   184
-#define DEC_184                                   183
-#define DEC_183                                   182
-#define DEC_182                                   181
-#define DEC_181                                   180
-#define DEC_180                                   179
-#define DEC_179                                   178
-#define DEC_178                                   177
-#define DEC_177                                   176
-#define DEC_176                                   175
-#define DEC_175                                   174
-#define DEC_174                                   173
-#define DEC_173                                   172
-#define DEC_172                                   171
-#define DEC_171                                   170
-#define DEC_170                                   169
-#define DEC_169                                   168
-#define DEC_168                                   167
-#define DEC_167                                   166
-#define DEC_166                                   165
-#define DEC_165                                   164
-#define DEC_164                                   163
-#define DEC_163                                   162
-#define DEC_162                                   161
-#define DEC_161                                   160
-#define DEC_160                                   159
-#define DEC_159                                   158
-#define DEC_158                                   157
-#define DEC_157                                   156
-#define DEC_156                                   155
-#define DEC_155                                   154
-#define DEC_154                                   153
-#define DEC_153                                   152
-#define DEC_152                                   151
-#define DEC_151                                   150
-#define DEC_150                                   149
-#define DEC_149                                   148
-#define DEC_148                                   147
-#define DEC_147                                   146
-#define DEC_146                                   145
-#define DEC_145                                   144
-#define DEC_144                                   143
-#define DEC_143                                   142
-#define DEC_142                                   141
-#define DEC_141                                   140
-#define DEC_140                                   139
-#define DEC_139                                   138
-#define DEC_138                                   137
-#define DEC_137                                   136
-#define DEC_136                                   135
-#define DEC_135                                   134
-#define DEC_134                                   133
-#define DEC_133                                   132
-#define DEC_132                                   131
-#define DEC_131                                   130
-#define DEC_130                                   129
-#define DEC_129                                   128
-#define DEC_128                                   127
-#define DEC_127                                   126
-#define DEC_126                                   125
-#define DEC_125                                   124
-#define DEC_124                                   123
-#define DEC_123                                   122
-#define DEC_122                                   121
-#define DEC_121                                   120
-#define DEC_120                                   119
-#define DEC_119                                   118
-#define DEC_118                                   117
-#define DEC_117                                   116
-#define DEC_116                                   115
-#define DEC_115                                   114
-#define DEC_114                                   113
-#define DEC_113                                   112
-#define DEC_112                                   111
-#define DEC_111                                   110
-#define DEC_110                                   109
-#define DEC_109                                   108
-#define DEC_108                                   107
-#define DEC_107                                   106
-#define DEC_106                                   105
-#define DEC_105                                   104
-#define DEC_104                                   103
-#define DEC_103                                   102
-#define DEC_102                                   101
-#define DEC_101                                   100
-#define DEC_100                                    99
-#define DEC_99                                     98
-#define DEC_98                                     97
-#define DEC_97                                     96
-#define DEC_96                                     95
-#define DEC_95                                     94
-#define DEC_94                                     93
-#define DEC_93                                     92
-#define DEC_92                                     91
-#define DEC_91                                     90
-#define DEC_90                                     89
-#define DEC_89                                     88
-#define DEC_88                                     87
-#define DEC_87                                     86
-#define DEC_86                                     85
-#define DEC_85                                     84
-#define DEC_84                                     83
-#define DEC_83                                     82
-#define DEC_82                                     81
-#define DEC_81                                     80
-#define DEC_80                                     79
-#define DEC_79                                     78
-#define DEC_78                                     77
-#define DEC_77                                     76
-#define DEC_76                                     75
-#define DEC_75                                     74
-#define DEC_74                                     73
-#define DEC_73                                     72
-#define DEC_72                                     71
-#define DEC_71                                     70
-#define DEC_70                                     69
-#define DEC_69                                     68
-#define DEC_68                                     67
-#define DEC_67                                     66
-#define DEC_66                                     65
-#define DEC_65                                     64
-#define DEC_64                                     63
-#define DEC_63                                     62
-#define DEC_62                                     61
-#define DEC_61                                     60
-#define DEC_60                                     59
-#define DEC_59                                     58
-#define DEC_58                                     57
-#define DEC_57                                     56
-#define DEC_56                                     55
-#define DEC_55                                     54
-#define DEC_54                                     53
-#define DEC_53                                     52
-#define DEC_52                                     51
-#define DEC_51                                     50
-#define DEC_50                                     49
-#define DEC_49                                     48
-#define DEC_48                                     47
-#define DEC_47                                     46
-#define DEC_46                                     45
-#define DEC_45                                     44
-#define DEC_44                                     43
-#define DEC_43                                     42
-#define DEC_42                                     41
-#define DEC_41                                     40
-#define DEC_40                                     39
-#define DEC_39                                     38
-#define DEC_38                                     37
-#define DEC_37                                     36
-#define DEC_36                                     35
-#define DEC_35                                     34
-#define DEC_34                                     33
-#define DEC_33                                     32
-#define DEC_32                                     31
-#define DEC_31                                     30
-#define DEC_30                                     29
-#define DEC_29                                     28
-#define DEC_28                                     27
-#define DEC_27                                     26
-#define DEC_26                                     25
-#define DEC_25                                     24
-#define DEC_24                                     23
-#define DEC_23                                     22
-#define DEC_22                                     21
-#define DEC_21                                     20
-#define DEC_20                                     19
-#define DEC_19                                     18
-#define DEC_18                                     17
-#define DEC_17                                     16
-#define DEC_16                                     15
-#define DEC_15                                     14
-#define DEC_14                                     13
-#define DEC_13                                     12
-#define DEC_12                                     11
-#define DEC_11                                     10
-#define DEC_10                                      9
-#define DEC_9                                       8
-#define DEC_8                                       7
-#define DEC_7                                       6
-#define DEC_6                                       5
-#define DEC_5                                       4
-#define DEC_4                                       3
-#define DEC_3                                       2
-#define DEC_2                                       1
-#define DEC_1                                       0
-#define DEC_(n)                                     DEC_##n
-
-
-/** Maximal number of repetitions supported by MRECURSION. */
-#define MRECURSION_LIMIT   256
-
-/** \brief Macro recursion.
- *
- * This macro represents a horizontal repetition construct.
- *
- * \param[in] count  The number of repetitious calls to macro. Valid values
- *                   range from 0 to MRECURSION_LIMIT.
- * \param[in] macro  A binary operation of the form macro(data, n).  This macro
- *                   is expanded by MRECURSION with the current repetition number
- *                   and the auxiliary data argument.
- * \param[in] data   A recursive threshold, building on this to decline by times 
- *                   defined with param count.
- *
- * \return       <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
- */
-#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data)
-
-#define MRECURSION0(  macro, data)
-#define MRECURSION1(  macro, data)    MRECURSION0(  macro, DEC_(data))   macro(data, 0)
-#define MRECURSION2(  macro, data)    MRECURSION1(  macro, DEC_(data))   macro(data, 1)
-#define MRECURSION3(  macro, data)    MRECURSION2(  macro, DEC_(data))   macro(data, 2)
-#define MRECURSION4(  macro, data)    MRECURSION3(  macro, DEC_(data))   macro(data, 3)
-#define MRECURSION5(  macro, data)    MRECURSION4(  macro, DEC_(data))   macro(data, 4)
-#define MRECURSION6(  macro, data)    MRECURSION5(  macro, DEC_(data))   macro(data, 5)
-#define MRECURSION7(  macro, data)    MRECURSION6(  macro, DEC_(data))   macro(data, 6)
-#define MRECURSION8(  macro, data)    MRECURSION7(  macro, DEC_(data))   macro(data, 7)
-#define MRECURSION9(  macro, data)    MRECURSION8(  macro, DEC_(data))   macro(data, 8)
-#define MRECURSION10( macro, data)    MRECURSION9(  macro, DEC_(data))   macro(data, 9)
-#define MRECURSION11( macro, data)    MRECURSION10(  macro, DEC_(data))   macro(data, 10)
-#define MRECURSION12( macro, data)    MRECURSION11(  macro, DEC_(data))   macro(data, 11)
-#define MRECURSION13( macro, data)    MRECURSION12(  macro, DEC_(data))   macro(data, 12)
-#define MRECURSION14( macro, data)    MRECURSION13(  macro, DEC_(data))   macro(data, 13)
-#define MRECURSION15( macro, data)    MRECURSION14(  macro, DEC_(data))   macro(data, 14)
-#define MRECURSION16( macro, data)    MRECURSION15(  macro, DEC_(data))   macro(data, 15)
-#define MRECURSION17( macro, data)    MRECURSION16(  macro, DEC_(data))   macro(data, 16)
-#define MRECURSION18( macro, data)    MRECURSION17(  macro, DEC_(data))   macro(data, 17)
-#define MRECURSION19( macro, data)    MRECURSION18(  macro, DEC_(data))   macro(data, 18)
-#define MRECURSION20( macro, data)    MRECURSION19(  macro, DEC_(data))   macro(data, 19)
-#define MRECURSION21( macro, data)    MRECURSION20(  macro, DEC_(data))   macro(data, 20)
-#define MRECURSION22( macro, data)    MRECURSION21(  macro, DEC_(data))   macro(data, 21)
-#define MRECURSION23( macro, data)    MRECURSION22(  macro, DEC_(data))   macro(data, 22)
-#define MRECURSION24( macro, data)    MRECURSION23(  macro, DEC_(data))   macro(data, 23)
-#define MRECURSION25( macro, data)    MRECURSION24(  macro, DEC_(data))   macro(data, 24)
-#define MRECURSION26( macro, data)    MRECURSION25(  macro, DEC_(data))   macro(data, 25)
-#define MRECURSION27( macro, data)    MRECURSION26(  macro, DEC_(data))   macro(data, 26)
-#define MRECURSION28( macro, data)    MRECURSION27(  macro, DEC_(data))   macro(data, 27)
-#define MRECURSION29( macro, data)    MRECURSION28(  macro, DEC_(data))   macro(data, 28)
-#define MRECURSION30( macro, data)    MRECURSION29(  macro, DEC_(data))   macro(data, 29)
-#define MRECURSION31( macro, data)    MRECURSION30(  macro, DEC_(data))   macro(data, 30)
-#define MRECURSION32( macro, data)    MRECURSION31(  macro, DEC_(data))   macro(data, 31)
-#define MRECURSION33( macro, data)    MRECURSION32(  macro, DEC_(data))   macro(data, 32)
-#define MRECURSION34( macro, data)    MRECURSION33(  macro, DEC_(data))   macro(data, 33)
-#define MRECURSION35( macro, data)    MRECURSION34(  macro, DEC_(data))   macro(data, 34)
-#define MRECURSION36( macro, data)    MRECURSION35(  macro, DEC_(data))   macro(data, 35)
-#define MRECURSION37( macro, data)    MRECURSION36(  macro, DEC_(data))   macro(data, 36)
-#define MRECURSION38( macro, data)    MRECURSION37(  macro, DEC_(data))   macro(data, 37)
-#define MRECURSION39( macro, data)    MRECURSION38(  macro, DEC_(data))   macro(data, 38)
-#define MRECURSION40( macro, data)    MRECURSION39(  macro, DEC_(data))   macro(data, 39)
-#define MRECURSION41( macro, data)    MRECURSION40(  macro, DEC_(data))   macro(data, 40)
-#define MRECURSION42( macro, data)    MRECURSION41(  macro, DEC_(data))   macro(data, 41)
-#define MRECURSION43( macro, data)    MRECURSION42(  macro, DEC_(data))   macro(data, 42)
-#define MRECURSION44( macro, data)    MRECURSION43(  macro, DEC_(data))   macro(data, 43)
-#define MRECURSION45( macro, data)    MRECURSION44(  macro, DEC_(data))   macro(data, 44)
-#define MRECURSION46( macro, data)    MRECURSION45(  macro, DEC_(data))   macro(data, 45)
-#define MRECURSION47( macro, data)    MRECURSION46(  macro, DEC_(data))   macro(data, 46)
-#define MRECURSION48( macro, data)    MRECURSION47(  macro, DEC_(data))   macro(data, 47)
-#define MRECURSION49( macro, data)    MRECURSION48(  macro, DEC_(data))   macro(data, 48)
-#define MRECURSION50( macro, data)    MRECURSION49(  macro, DEC_(data))   macro(data, 49)
-#define MRECURSION51( macro, data)    MRECURSION50(  macro, DEC_(data))   macro(data, 50)
-#define MRECURSION52( macro, data)    MRECURSION51(  macro, DEC_(data))   macro(data, 51)
-#define MRECURSION53( macro, data)    MRECURSION52(  macro, DEC_(data))   macro(data, 52)
-#define MRECURSION54( macro, data)    MRECURSION53(  macro, DEC_(data))   macro(data, 53)
-#define MRECURSION55( macro, data)    MRECURSION54(  macro, DEC_(data))   macro(data, 54)
-#define MRECURSION56( macro, data)    MRECURSION55(  macro, DEC_(data))   macro(data, 55)
-#define MRECURSION57( macro, data)    MRECURSION56(  macro, DEC_(data))   macro(data, 56)
-#define MRECURSION58( macro, data)    MRECURSION57(  macro, DEC_(data))   macro(data, 57)
-#define MRECURSION59( macro, data)    MRECURSION58(  macro, DEC_(data))   macro(data, 58)
-#define MRECURSION60( macro, data)    MRECURSION59(  macro, DEC_(data))   macro(data, 59)
-#define MRECURSION61( macro, data)    MRECURSION60(  macro, DEC_(data))   macro(data, 60)
-#define MRECURSION62( macro, data)    MRECURSION61(  macro, DEC_(data))   macro(data, 61)
-#define MRECURSION63( macro, data)    MRECURSION62(  macro, DEC_(data))   macro(data, 62)
-#define MRECURSION64( macro, data)    MRECURSION63(  macro, DEC_(data))   macro(data, 63)
-#define MRECURSION65( macro, data)    MRECURSION64(  macro, DEC_(data))   macro(data, 64)
-#define MRECURSION66( macro, data)    MRECURSION65(  macro, DEC_(data))   macro(data, 65)
-#define MRECURSION67( macro, data)    MRECURSION66(  macro, DEC_(data))   macro(data, 66)
-#define MRECURSION68( macro, data)    MRECURSION67(  macro, DEC_(data))   macro(data, 67)
-#define MRECURSION69( macro, data)    MRECURSION68(  macro, DEC_(data))   macro(data, 68)
-#define MRECURSION70( macro, data)    MRECURSION69(  macro, DEC_(data))   macro(data, 69)
-#define MRECURSION71( macro, data)    MRECURSION70(  macro, DEC_(data))   macro(data, 70)
-#define MRECURSION72( macro, data)    MRECURSION71(  macro, DEC_(data))   macro(data, 71)
-#define MRECURSION73( macro, data)    MRECURSION72(  macro, DEC_(data))   macro(data, 72)
-#define MRECURSION74( macro, data)    MRECURSION73(  macro, DEC_(data))   macro(data, 73)
-#define MRECURSION75( macro, data)    MRECURSION74(  macro, DEC_(data))   macro(data, 74)
-#define MRECURSION76( macro, data)    MRECURSION75(  macro, DEC_(data))   macro(data, 75)
-#define MRECURSION77( macro, data)    MRECURSION76(  macro, DEC_(data))   macro(data, 76)
-#define MRECURSION78( macro, data)    MRECURSION77(  macro, DEC_(data))   macro(data, 77)
-#define MRECURSION79( macro, data)    MRECURSION78(  macro, DEC_(data))   macro(data, 78)
-#define MRECURSION80( macro, data)    MRECURSION79(  macro, DEC_(data))   macro(data, 79)
-#define MRECURSION81( macro, data)    MRECURSION80(  macro, DEC_(data))   macro(data, 80)
-#define MRECURSION82( macro, data)    MRECURSION81(  macro, DEC_(data))   macro(data, 81)
-#define MRECURSION83( macro, data)    MRECURSION82(  macro, DEC_(data))   macro(data, 82)
-#define MRECURSION84( macro, data)    MRECURSION83(  macro, DEC_(data))   macro(data, 83)
-#define MRECURSION85( macro, data)    MRECURSION84(  macro, DEC_(data))   macro(data, 84)
-#define MRECURSION86( macro, data)    MRECURSION85(  macro, DEC_(data))   macro(data, 85)
-#define MRECURSION87( macro, data)    MRECURSION86(  macro, DEC_(data))   macro(data, 86)
-#define MRECURSION88( macro, data)    MRECURSION87(  macro, DEC_(data))   macro(data, 87)
-#define MRECURSION89( macro, data)    MRECURSION88(  macro, DEC_(data))   macro(data, 88)
-#define MRECURSION90( macro, data)    MRECURSION89(  macro, DEC_(data))   macro(data, 89)
-#define MRECURSION91( macro, data)    MRECURSION90(  macro, DEC_(data))   macro(data, 90)
-#define MRECURSION92( macro, data)    MRECURSION91(  macro, DEC_(data))   macro(data, 91)
-#define MRECURSION93( macro, data)    MRECURSION92(  macro, DEC_(data))   macro(data, 92)
-#define MRECURSION94( macro, data)    MRECURSION93(  macro, DEC_(data))   macro(data, 93)
-#define MRECURSION95( macro, data)    MRECURSION94(  macro, DEC_(data))   macro(data, 94)
-#define MRECURSION96( macro, data)    MRECURSION95(  macro, DEC_(data))   macro(data, 95)
-#define MRECURSION97( macro, data)    MRECURSION96(  macro, DEC_(data))   macro(data, 96)
-#define MRECURSION98( macro, data)    MRECURSION97(  macro, DEC_(data))   macro(data, 97)
-#define MRECURSION99( macro, data)    MRECURSION98(  macro, DEC_(data))   macro(data, 98)
-#define MRECURSION100(macro, data)    MRECURSION99(  macro, DEC_(data))   macro(data, 99)
-#define MRECURSION101(macro, data)    MRECURSION100(  macro, DEC_(data))   macro(data, 100)
-#define MRECURSION102(macro, data)    MRECURSION101(  macro, DEC_(data))   macro(data, 101)
-#define MRECURSION103(macro, data)    MRECURSION102(  macro, DEC_(data))   macro(data, 102)
-#define MRECURSION104(macro, data)    MRECURSION103(  macro, DEC_(data))   macro(data, 103)
-#define MRECURSION105(macro, data)    MRECURSION104(  macro, DEC_(data))   macro(data, 104)
-#define MRECURSION106(macro, data)    MRECURSION105(  macro, DEC_(data))   macro(data, 105)
-#define MRECURSION107(macro, data)    MRECURSION106(  macro, DEC_(data))   macro(data, 106)
-#define MRECURSION108(macro, data)    MRECURSION107(  macro, DEC_(data))   macro(data, 107)
-#define MRECURSION109(macro, data)    MRECURSION108(  macro, DEC_(data))   macro(data, 108)
-#define MRECURSION110(macro, data)    MRECURSION109(  macro, DEC_(data))   macro(data, 109)
-#define MRECURSION111(macro, data)    MRECURSION110(  macro, DEC_(data))   macro(data, 110)
-#define MRECURSION112(macro, data)    MRECURSION111(  macro, DEC_(data))   macro(data, 111)
-#define MRECURSION113(macro, data)    MRECURSION112(  macro, DEC_(data))   macro(data, 112)
-#define MRECURSION114(macro, data)    MRECURSION113(  macro, DEC_(data))   macro(data, 113)
-#define MRECURSION115(macro, data)    MRECURSION114(  macro, DEC_(data))   macro(data, 114)
-#define MRECURSION116(macro, data)    MRECURSION115(  macro, DEC_(data))   macro(data, 115)
-#define MRECURSION117(macro, data)    MRECURSION116(  macro, DEC_(data))   macro(data, 116)
-#define MRECURSION118(macro, data)    MRECURSION117(  macro, DEC_(data))   macro(data, 117)
-#define MRECURSION119(macro, data)    MRECURSION118(  macro, DEC_(data))   macro(data, 118)
-#define MRECURSION120(macro, data)    MRECURSION119(  macro, DEC_(data))   macro(data, 119)
-#define MRECURSION121(macro, data)    MRECURSION120(  macro, DEC_(data))   macro(data, 120)
-#define MRECURSION122(macro, data)    MRECURSION121(  macro, DEC_(data))   macro(data, 121)
-#define MRECURSION123(macro, data)    MRECURSION122(  macro, DEC_(data))   macro(data, 122)
-#define MRECURSION124(macro, data)    MRECURSION123(  macro, DEC_(data))   macro(data, 123)
-#define MRECURSION125(macro, data)    MRECURSION124(  macro, DEC_(data))   macro(data, 124)
-#define MRECURSION126(macro, data)    MRECURSION125(  macro, DEC_(data))   macro(data, 125)
-#define MRECURSION127(macro, data)    MRECURSION126(  macro, DEC_(data))   macro(data, 126)
-#define MRECURSION128(macro, data)    MRECURSION127(  macro, DEC_(data))   macro(data, 127)
-#define MRECURSION129(macro, data)    MRECURSION128(  macro, DEC_(data))   macro(data, 128)
-#define MRECURSION130(macro, data)    MRECURSION129(  macro, DEC_(data))   macro(data, 129)
-#define MRECURSION131(macro, data)    MRECURSION130(  macro, DEC_(data))   macro(data, 130)
-#define MRECURSION132(macro, data)    MRECURSION131(  macro, DEC_(data))   macro(data, 131)
-#define MRECURSION133(macro, data)    MRECURSION132(  macro, DEC_(data))   macro(data, 132)
-#define MRECURSION134(macro, data)    MRECURSION133(  macro, DEC_(data))   macro(data, 133)
-#define MRECURSION135(macro, data)    MRECURSION134(  macro, DEC_(data))   macro(data, 134)
-#define MRECURSION136(macro, data)    MRECURSION135(  macro, DEC_(data))   macro(data, 135)
-#define MRECURSION137(macro, data)    MRECURSION136(  macro, DEC_(data))   macro(data, 136)
-#define MRECURSION138(macro, data)    MRECURSION137(  macro, DEC_(data))   macro(data, 137)
-#define MRECURSION139(macro, data)    MRECURSION138(  macro, DEC_(data))   macro(data, 138)
-#define MRECURSION140(macro, data)    MRECURSION139(  macro, DEC_(data))   macro(data, 139)
-#define MRECURSION141(macro, data)    MRECURSION140(  macro, DEC_(data))   macro(data, 140)
-#define MRECURSION142(macro, data)    MRECURSION141(  macro, DEC_(data))   macro(data, 141)
-#define MRECURSION143(macro, data)    MRECURSION142(  macro, DEC_(data))   macro(data, 142)
-#define MRECURSION144(macro, data)    MRECURSION143(  macro, DEC_(data))   macro(data, 143)
-#define MRECURSION145(macro, data)    MRECURSION144(  macro, DEC_(data))   macro(data, 144)
-#define MRECURSION146(macro, data)    MRECURSION145(  macro, DEC_(data))   macro(data, 145)
-#define MRECURSION147(macro, data)    MRECURSION146(  macro, DEC_(data))   macro(data, 146)
-#define MRECURSION148(macro, data)    MRECURSION147(  macro, DEC_(data))   macro(data, 147)
-#define MRECURSION149(macro, data)    MRECURSION148(  macro, DEC_(data))   macro(data, 148)
-#define MRECURSION150(macro, data)    MRECURSION149(  macro, DEC_(data))   macro(data, 149)
-#define MRECURSION151(macro, data)    MRECURSION150(  macro, DEC_(data))   macro(data, 150)
-#define MRECURSION152(macro, data)    MRECURSION151(  macro, DEC_(data))   macro(data, 151)
-#define MRECURSION153(macro, data)    MRECURSION152(  macro, DEC_(data))   macro(data, 152)
-#define MRECURSION154(macro, data)    MRECURSION153(  macro, DEC_(data))   macro(data, 153)
-#define MRECURSION155(macro, data)    MRECURSION154(  macro, DEC_(data))   macro(data, 154)
-#define MRECURSION156(macro, data)    MRECURSION155(  macro, DEC_(data))   macro(data, 155)
-#define MRECURSION157(macro, data)    MRECURSION156(  macro, DEC_(data))   macro(data, 156)
-#define MRECURSION158(macro, data)    MRECURSION157(  macro, DEC_(data))   macro(data, 157)
-#define MRECURSION159(macro, data)    MRECURSION158(  macro, DEC_(data))   macro(data, 158)
-#define MRECURSION160(macro, data)    MRECURSION159(  macro, DEC_(data))   macro(data, 159)
-#define MRECURSION161(macro, data)    MRECURSION160(  macro, DEC_(data))   macro(data, 160)
-#define MRECURSION162(macro, data)    MRECURSION161(  macro, DEC_(data))   macro(data, 161)
-#define MRECURSION163(macro, data)    MRECURSION162(  macro, DEC_(data))   macro(data, 162)
-#define MRECURSION164(macro, data)    MRECURSION163(  macro, DEC_(data))   macro(data, 163)
-#define MRECURSION165(macro, data)    MRECURSION164(  macro, DEC_(data))   macro(data, 164)
-#define MRECURSION166(macro, data)    MRECURSION165(  macro, DEC_(data))   macro(data, 165)
-#define MRECURSION167(macro, data)    MRECURSION166(  macro, DEC_(data))   macro(data, 166)
-#define MRECURSION168(macro, data)    MRECURSION167(  macro, DEC_(data))   macro(data, 167)
-#define MRECURSION169(macro, data)    MRECURSION168(  macro, DEC_(data))   macro(data, 168)
-#define MRECURSION170(macro, data)    MRECURSION169(  macro, DEC_(data))   macro(data, 169)
-#define MRECURSION171(macro, data)    MRECURSION170(  macro, DEC_(data))   macro(data, 170)
-#define MRECURSION172(macro, data)    MRECURSION171(  macro, DEC_(data))   macro(data, 171)
-#define MRECURSION173(macro, data)    MRECURSION172(  macro, DEC_(data))   macro(data, 172)
-#define MRECURSION174(macro, data)    MRECURSION173(  macro, DEC_(data))   macro(data, 173)
-#define MRECURSION175(macro, data)    MRECURSION174(  macro, DEC_(data))   macro(data, 174)
-#define MRECURSION176(macro, data)    MRECURSION175(  macro, DEC_(data))   macro(data, 175)
-#define MRECURSION177(macro, data)    MRECURSION176(  macro, DEC_(data))   macro(data, 176)
-#define MRECURSION178(macro, data)    MRECURSION177(  macro, DEC_(data))   macro(data, 177)
-#define MRECURSION179(macro, data)    MRECURSION178(  macro, DEC_(data))   macro(data, 178)
-#define MRECURSION180(macro, data)    MRECURSION179(  macro, DEC_(data))   macro(data, 179)
-#define MRECURSION181(macro, data)    MRECURSION180(  macro, DEC_(data))   macro(data, 180)
-#define MRECURSION182(macro, data)    MRECURSION181(  macro, DEC_(data))   macro(data, 181)
-#define MRECURSION183(macro, data)    MRECURSION182(  macro, DEC_(data))   macro(data, 182)
-#define MRECURSION184(macro, data)    MRECURSION183(  macro, DEC_(data))   macro(data, 183)
-#define MRECURSION185(macro, data)    MRECURSION184(  macro, DEC_(data))   macro(data, 184)
-#define MRECURSION186(macro, data)    MRECURSION185(  macro, DEC_(data))   macro(data, 185)
-#define MRECURSION187(macro, data)    MRECURSION186(  macro, DEC_(data))   macro(data, 186)
-#define MRECURSION188(macro, data)    MRECURSION187(  macro, DEC_(data))   macro(data, 187)
-#define MRECURSION189(macro, data)    MRECURSION188(  macro, DEC_(data))   macro(data, 188)
-#define MRECURSION190(macro, data)    MRECURSION189(  macro, DEC_(data))   macro(data, 189)
-#define MRECURSION191(macro, data)    MRECURSION190(  macro, DEC_(data))   macro(data, 190)
-#define MRECURSION192(macro, data)    MRECURSION191(  macro, DEC_(data))   macro(data, 191)
-#define MRECURSION193(macro, data)    MRECURSION192(  macro, DEC_(data))   macro(data, 192)
-#define MRECURSION194(macro, data)    MRECURSION193(  macro, DEC_(data))   macro(data, 193)
-#define MRECURSION195(macro, data)    MRECURSION194(  macro, DEC_(data))   macro(data, 194)
-#define MRECURSION196(macro, data)    MRECURSION195(  macro, DEC_(data))   macro(data, 195)
-#define MRECURSION197(macro, data)    MRECURSION196(  macro, DEC_(data))   macro(data, 196)
-#define MRECURSION198(macro, data)    MRECURSION197(  macro, DEC_(data))   macro(data, 197)
-#define MRECURSION199(macro, data)    MRECURSION198(  macro, DEC_(data))   macro(data, 198)
-#define MRECURSION200(macro, data)    MRECURSION199(  macro, DEC_(data))   macro(data, 199)
-#define MRECURSION201(macro, data)    MRECURSION200(  macro, DEC_(data))   macro(data, 200)
-#define MRECURSION202(macro, data)    MRECURSION201(  macro, DEC_(data))   macro(data, 201)
-#define MRECURSION203(macro, data)    MRECURSION202(  macro, DEC_(data))   macro(data, 202)
-#define MRECURSION204(macro, data)    MRECURSION203(  macro, DEC_(data))   macro(data, 203)
-#define MRECURSION205(macro, data)    MRECURSION204(  macro, DEC_(data))   macro(data, 204)
-#define MRECURSION206(macro, data)    MRECURSION205(  macro, DEC_(data))   macro(data, 205)
-#define MRECURSION207(macro, data)    MRECURSION206(  macro, DEC_(data))   macro(data, 206)
-#define MRECURSION208(macro, data)    MRECURSION207(  macro, DEC_(data))   macro(data, 207)
-#define MRECURSION209(macro, data)    MRECURSION208(  macro, DEC_(data))   macro(data, 208)
-#define MRECURSION210(macro, data)    MRECURSION209(  macro, DEC_(data))   macro(data, 209)
-#define MRECURSION211(macro, data)    MRECURSION210(  macro, DEC_(data))   macro(data, 210)
-#define MRECURSION212(macro, data)    MRECURSION211(  macro, DEC_(data))   macro(data, 211)
-#define MRECURSION213(macro, data)    MRECURSION212(  macro, DEC_(data))   macro(data, 212)
-#define MRECURSION214(macro, data)    MRECURSION213(  macro, DEC_(data))   macro(data, 213)
-#define MRECURSION215(macro, data)    MRECURSION214(  macro, DEC_(data))   macro(data, 214)
-#define MRECURSION216(macro, data)    MRECURSION215(  macro, DEC_(data))   macro(data, 215)
-#define MRECURSION217(macro, data)    MRECURSION216(  macro, DEC_(data))   macro(data, 216)
-#define MRECURSION218(macro, data)    MRECURSION217(  macro, DEC_(data))   macro(data, 217)
-#define MRECURSION219(macro, data)    MRECURSION218(  macro, DEC_(data))   macro(data, 218)
-#define MRECURSION220(macro, data)    MRECURSION219(  macro, DEC_(data))   macro(data, 219)
-#define MRECURSION221(macro, data)    MRECURSION220(  macro, DEC_(data))   macro(data, 220)
-#define MRECURSION222(macro, data)    MRECURSION221(  macro, DEC_(data))   macro(data, 221)
-#define MRECURSION223(macro, data)    MRECURSION222(  macro, DEC_(data))   macro(data, 222)
-#define MRECURSION224(macro, data)    MRECURSION223(  macro, DEC_(data))   macro(data, 223)
-#define MRECURSION225(macro, data)    MRECURSION224(  macro, DEC_(data))   macro(data, 224)
-#define MRECURSION226(macro, data)    MRECURSION225(  macro, DEC_(data))   macro(data, 225)
-#define MRECURSION227(macro, data)    MRECURSION226(  macro, DEC_(data))   macro(data, 226)
-#define MRECURSION228(macro, data)    MRECURSION227(  macro, DEC_(data))   macro(data, 227)
-#define MRECURSION229(macro, data)    MRECURSION228(  macro, DEC_(data))   macro(data, 228)
-#define MRECURSION230(macro, data)    MRECURSION229(  macro, DEC_(data))   macro(data, 229)
-#define MRECURSION231(macro, data)    MRECURSION230(  macro, DEC_(data))   macro(data, 230)
-#define MRECURSION232(macro, data)    MRECURSION231(  macro, DEC_(data))   macro(data, 231)
-#define MRECURSION233(macro, data)    MRECURSION232(  macro, DEC_(data))   macro(data, 232)
-#define MRECURSION234(macro, data)    MRECURSION233(  macro, DEC_(data))   macro(data, 233)
-#define MRECURSION235(macro, data)    MRECURSION234(  macro, DEC_(data))   macro(data, 234)
-#define MRECURSION236(macro, data)    MRECURSION235(  macro, DEC_(data))   macro(data, 235)
-#define MRECURSION237(macro, data)    MRECURSION236(  macro, DEC_(data))   macro(data, 236)
-#define MRECURSION238(macro, data)    MRECURSION237(  macro, DEC_(data))   macro(data, 237)
-#define MRECURSION239(macro, data)    MRECURSION238(  macro, DEC_(data))   macro(data, 238)
-#define MRECURSION240(macro, data)    MRECURSION239(  macro, DEC_(data))   macro(data, 239)
-#define MRECURSION241(macro, data)    MRECURSION240(  macro, DEC_(data))   macro(data, 240)
-#define MRECURSION242(macro, data)    MRECURSION241(  macro, DEC_(data))   macro(data, 241)
-#define MRECURSION243(macro, data)    MRECURSION242(  macro, DEC_(data))   macro(data, 242)
-#define MRECURSION244(macro, data)    MRECURSION243(  macro, DEC_(data))   macro(data, 243)
-#define MRECURSION245(macro, data)    MRECURSION244(  macro, DEC_(data))   macro(data, 244)
-#define MRECURSION246(macro, data)    MRECURSION245(  macro, DEC_(data))   macro(data, 245)
-#define MRECURSION247(macro, data)    MRECURSION246(  macro, DEC_(data))   macro(data, 246)
-#define MRECURSION248(macro, data)    MRECURSION247(  macro, DEC_(data))   macro(data, 247)
-#define MRECURSION249(macro, data)    MRECURSION248(  macro, DEC_(data))   macro(data, 248)
-#define MRECURSION250(macro, data)    MRECURSION249(  macro, DEC_(data))   macro(data, 249)
-#define MRECURSION251(macro, data)    MRECURSION250(  macro, DEC_(data))   macro(data, 250)
-#define MRECURSION252(macro, data)    MRECURSION251(  macro, DEC_(data))   macro(data, 251)
-#define MRECURSION253(macro, data)    MRECURSION252(  macro, DEC_(data))   macro(data, 252)
-#define MRECURSION254(macro, data)    MRECURSION253(  macro, DEC_(data))   macro(data, 253)
-#define MRECURSION255(macro, data)    MRECURSION254(  macro, DEC_(data))   macro(data, 254)
-#define MRECURSION256(macro, data)    MRECURSION255(  macro, DEC_(data))   macro(data, 255)
-
-/** @} */
-
-#endif  /* _MRECURSION_H_ */
+/**
+ * \file
+ *
+ * \brief Preprocessor macro recursion utils.
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _MRECURSION_H_
+#define _MRECURSION_H_
+
+/**
+ * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+#define DEC_256                                   255
+#define DEC_255                                   254
+#define DEC_254                                   253
+#define DEC_253                                   252
+#define DEC_252                                   251
+#define DEC_251                                   250
+#define DEC_250                                   249
+#define DEC_249                                   248
+#define DEC_248                                   247
+#define DEC_247                                   246
+#define DEC_246                                   245
+#define DEC_245                                   244
+#define DEC_244                                   243
+#define DEC_243                                   242
+#define DEC_242                                   241
+#define DEC_241                                   240
+#define DEC_240                                   239
+#define DEC_239                                   238
+#define DEC_238                                   237
+#define DEC_237                                   236
+#define DEC_236                                   235
+#define DEC_235                                   234
+#define DEC_234                                   233
+#define DEC_233                                   232
+#define DEC_232                                   231
+#define DEC_231                                   230
+#define DEC_230                                   229
+#define DEC_229                                   228
+#define DEC_228                                   227
+#define DEC_227                                   226
+#define DEC_226                                   225
+#define DEC_225                                   224
+#define DEC_224                                   223
+#define DEC_223                                   222
+#define DEC_222                                   221
+#define DEC_221                                   220
+#define DEC_220                                   219
+#define DEC_219                                   218
+#define DEC_218                                   217
+#define DEC_217                                   216
+#define DEC_216                                   215
+#define DEC_215                                   214
+#define DEC_214                                   213
+#define DEC_213                                   212
+#define DEC_212                                   211
+#define DEC_211                                   210
+#define DEC_210                                   209
+#define DEC_209                                   208
+#define DEC_208                                   207
+#define DEC_207                                   206
+#define DEC_206                                   205
+#define DEC_205                                   204
+#define DEC_204                                   203
+#define DEC_203                                   202
+#define DEC_202                                   201
+#define DEC_201                                   200
+#define DEC_200                                   199
+#define DEC_199                                   198
+#define DEC_198                                   197
+#define DEC_197                                   196
+#define DEC_196                                   195
+#define DEC_195                                   194
+#define DEC_194                                   193
+#define DEC_193                                   192
+#define DEC_192                                   191
+#define DEC_191                                   190
+#define DEC_190                                   189
+#define DEC_189                                   188
+#define DEC_188                                   187
+#define DEC_187                                   186
+#define DEC_186                                   185
+#define DEC_185                                   184
+#define DEC_184                                   183
+#define DEC_183                                   182
+#define DEC_182                                   181
+#define DEC_181                                   180
+#define DEC_180                                   179
+#define DEC_179                                   178
+#define DEC_178                                   177
+#define DEC_177                                   176
+#define DEC_176                                   175
+#define DEC_175                                   174
+#define DEC_174                                   173
+#define DEC_173                                   172
+#define DEC_172                                   171
+#define DEC_171                                   170
+#define DEC_170                                   169
+#define DEC_169                                   168
+#define DEC_168                                   167
+#define DEC_167                                   166
+#define DEC_166                                   165
+#define DEC_165                                   164
+#define DEC_164                                   163
+#define DEC_163                                   162
+#define DEC_162                                   161
+#define DEC_161                                   160
+#define DEC_160                                   159
+#define DEC_159                                   158
+#define DEC_158                                   157
+#define DEC_157                                   156
+#define DEC_156                                   155
+#define DEC_155                                   154
+#define DEC_154                                   153
+#define DEC_153                                   152
+#define DEC_152                                   151
+#define DEC_151                                   150
+#define DEC_150                                   149
+#define DEC_149                                   148
+#define DEC_148                                   147
+#define DEC_147                                   146
+#define DEC_146                                   145
+#define DEC_145                                   144
+#define DEC_144                                   143
+#define DEC_143                                   142
+#define DEC_142                                   141
+#define DEC_141                                   140
+#define DEC_140                                   139
+#define DEC_139                                   138
+#define DEC_138                                   137
+#define DEC_137                                   136
+#define DEC_136                                   135
+#define DEC_135                                   134
+#define DEC_134                                   133
+#define DEC_133                                   132
+#define DEC_132                                   131
+#define DEC_131                                   130
+#define DEC_130                                   129
+#define DEC_129                                   128
+#define DEC_128                                   127
+#define DEC_127                                   126
+#define DEC_126                                   125
+#define DEC_125                                   124
+#define DEC_124                                   123
+#define DEC_123                                   122
+#define DEC_122                                   121
+#define DEC_121                                   120
+#define DEC_120                                   119
+#define DEC_119                                   118
+#define DEC_118                                   117
+#define DEC_117                                   116
+#define DEC_116                                   115
+#define DEC_115                                   114
+#define DEC_114                                   113
+#define DEC_113                                   112
+#define DEC_112                                   111
+#define DEC_111                                   110
+#define DEC_110                                   109
+#define DEC_109                                   108
+#define DEC_108                                   107
+#define DEC_107                                   106
+#define DEC_106                                   105
+#define DEC_105                                   104
+#define DEC_104                                   103
+#define DEC_103                                   102
+#define DEC_102                                   101
+#define DEC_101                                   100
+#define DEC_100                                    99
+#define DEC_99                                     98
+#define DEC_98                                     97
+#define DEC_97                                     96
+#define DEC_96                                     95
+#define DEC_95                                     94
+#define DEC_94                                     93
+#define DEC_93                                     92
+#define DEC_92                                     91
+#define DEC_91                                     90
+#define DEC_90                                     89
+#define DEC_89                                     88
+#define DEC_88                                     87
+#define DEC_87                                     86
+#define DEC_86                                     85
+#define DEC_85                                     84
+#define DEC_84                                     83
+#define DEC_83                                     82
+#define DEC_82                                     81
+#define DEC_81                                     80
+#define DEC_80                                     79
+#define DEC_79                                     78
+#define DEC_78                                     77
+#define DEC_77                                     76
+#define DEC_76                                     75
+#define DEC_75                                     74
+#define DEC_74                                     73
+#define DEC_73                                     72
+#define DEC_72                                     71
+#define DEC_71                                     70
+#define DEC_70                                     69
+#define DEC_69                                     68
+#define DEC_68                                     67
+#define DEC_67                                     66
+#define DEC_66                                     65
+#define DEC_65                                     64
+#define DEC_64                                     63
+#define DEC_63                                     62
+#define DEC_62                                     61
+#define DEC_61                                     60
+#define DEC_60                                     59
+#define DEC_59                                     58
+#define DEC_58                                     57
+#define DEC_57                                     56
+#define DEC_56                                     55
+#define DEC_55                                     54
+#define DEC_54                                     53
+#define DEC_53                                     52
+#define DEC_52                                     51
+#define DEC_51                                     50
+#define DEC_50                                     49
+#define DEC_49                                     48
+#define DEC_48                                     47
+#define DEC_47                                     46
+#define DEC_46                                     45
+#define DEC_45                                     44
+#define DEC_44                                     43
+#define DEC_43                                     42
+#define DEC_42                                     41
+#define DEC_41                                     40
+#define DEC_40                                     39
+#define DEC_39                                     38
+#define DEC_38                                     37
+#define DEC_37                                     36
+#define DEC_36                                     35
+#define DEC_35                                     34
+#define DEC_34                                     33
+#define DEC_33                                     32
+#define DEC_32                                     31
+#define DEC_31                                     30
+#define DEC_30                                     29
+#define DEC_29                                     28
+#define DEC_28                                     27
+#define DEC_27                                     26
+#define DEC_26                                     25
+#define DEC_25                                     24
+#define DEC_24                                     23
+#define DEC_23                                     22
+#define DEC_22                                     21
+#define DEC_21                                     20
+#define DEC_20                                     19
+#define DEC_19                                     18
+#define DEC_18                                     17
+#define DEC_17                                     16
+#define DEC_16                                     15
+#define DEC_15                                     14
+#define DEC_14                                     13
+#define DEC_13                                     12
+#define DEC_12                                     11
+#define DEC_11                                     10
+#define DEC_10                                      9
+#define DEC_9                                       8
+#define DEC_8                                       7
+#define DEC_7                                       6
+#define DEC_6                                       5
+#define DEC_5                                       4
+#define DEC_4                                       3
+#define DEC_3                                       2
+#define DEC_2                                       1
+#define DEC_1                                       0
+#define DEC_(n)                                     DEC_##n
+
+
+/** Maximal number of repetitions supported by MRECURSION. */
+#define MRECURSION_LIMIT   256
+
+/** \brief Macro recursion.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count  The number of repetitious calls to macro. Valid values
+ *                   range from 0 to MRECURSION_LIMIT.
+ * \param[in] macro  A binary operation of the form macro(data, n).  This macro
+ *                   is expanded by MRECURSION with the current repetition number
+ *                   and the auxiliary data argument.
+ * \param[in] data   A recursive threshold, building on this to decline by times 
+ *                   defined with param count.
+ *
+ * \return       <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
+ */
+#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data)
+
+#define MRECURSION0(  macro, data)
+#define MRECURSION1(  macro, data)    MRECURSION0(  macro, DEC_(data))   macro(data, 0)
+#define MRECURSION2(  macro, data)    MRECURSION1(  macro, DEC_(data))   macro(data, 1)
+#define MRECURSION3(  macro, data)    MRECURSION2(  macro, DEC_(data))   macro(data, 2)
+#define MRECURSION4(  macro, data)    MRECURSION3(  macro, DEC_(data))   macro(data, 3)
+#define MRECURSION5(  macro, data)    MRECURSION4(  macro, DEC_(data))   macro(data, 4)
+#define MRECURSION6(  macro, data)    MRECURSION5(  macro, DEC_(data))   macro(data, 5)
+#define MRECURSION7(  macro, data)    MRECURSION6(  macro, DEC_(data))   macro(data, 6)
+#define MRECURSION8(  macro, data)    MRECURSION7(  macro, DEC_(data))   macro(data, 7)
+#define MRECURSION9(  macro, data)    MRECURSION8(  macro, DEC_(data))   macro(data, 8)
+#define MRECURSION10( macro, data)    MRECURSION9(  macro, DEC_(data))   macro(data, 9)
+#define MRECURSION11( macro, data)    MRECURSION10(  macro, DEC_(data))   macro(data, 10)
+#define MRECURSION12( macro, data)    MRECURSION11(  macro, DEC_(data))   macro(data, 11)
+#define MRECURSION13( macro, data)    MRECURSION12(  macro, DEC_(data))   macro(data, 12)
+#define MRECURSION14( macro, data)    MRECURSION13(  macro, DEC_(data))   macro(data, 13)
+#define MRECURSION15( macro, data)    MRECURSION14(  macro, DEC_(data))   macro(data, 14)
+#define MRECURSION16( macro, data)    MRECURSION15(  macro, DEC_(data))   macro(data, 15)
+#define MRECURSION17( macro, data)    MRECURSION16(  macro, DEC_(data))   macro(data, 16)
+#define MRECURSION18( macro, data)    MRECURSION17(  macro, DEC_(data))   macro(data, 17)
+#define MRECURSION19( macro, data)    MRECURSION18(  macro, DEC_(data))   macro(data, 18)
+#define MRECURSION20( macro, data)    MRECURSION19(  macro, DEC_(data))   macro(data, 19)
+#define MRECURSION21( macro, data)    MRECURSION20(  macro, DEC_(data))   macro(data, 20)
+#define MRECURSION22( macro, data)    MRECURSION21(  macro, DEC_(data))   macro(data, 21)
+#define MRECURSION23( macro, data)    MRECURSION22(  macro, DEC_(data))   macro(data, 22)
+#define MRECURSION24( macro, data)    MRECURSION23(  macro, DEC_(data))   macro(data, 23)
+#define MRECURSION25( macro, data)    MRECURSION24(  macro, DEC_(data))   macro(data, 24)
+#define MRECURSION26( macro, data)    MRECURSION25(  macro, DEC_(data))   macro(data, 25)
+#define MRECURSION27( macro, data)    MRECURSION26(  macro, DEC_(data))   macro(data, 26)
+#define MRECURSION28( macro, data)    MRECURSION27(  macro, DEC_(data))   macro(data, 27)
+#define MRECURSION29( macro, data)    MRECURSION28(  macro, DEC_(data))   macro(data, 28)
+#define MRECURSION30( macro, data)    MRECURSION29(  macro, DEC_(data))   macro(data, 29)
+#define MRECURSION31( macro, data)    MRECURSION30(  macro, DEC_(data))   macro(data, 30)
+#define MRECURSION32( macro, data)    MRECURSION31(  macro, DEC_(data))   macro(data, 31)
+#define MRECURSION33( macro, data)    MRECURSION32(  macro, DEC_(data))   macro(data, 32)
+#define MRECURSION34( macro, data)    MRECURSION33(  macro, DEC_(data))   macro(data, 33)
+#define MRECURSION35( macro, data)    MRECURSION34(  macro, DEC_(data))   macro(data, 34)
+#define MRECURSION36( macro, data)    MRECURSION35(  macro, DEC_(data))   macro(data, 35)
+#define MRECURSION37( macro, data)    MRECURSION36(  macro, DEC_(data))   macro(data, 36)
+#define MRECURSION38( macro, data)    MRECURSION37(  macro, DEC_(data))   macro(data, 37)
+#define MRECURSION39( macro, data)    MRECURSION38(  macro, DEC_(data))   macro(data, 38)
+#define MRECURSION40( macro, data)    MRECURSION39(  macro, DEC_(data))   macro(data, 39)
+#define MRECURSION41( macro, data)    MRECURSION40(  macro, DEC_(data))   macro(data, 40)
+#define MRECURSION42( macro, data)    MRECURSION41(  macro, DEC_(data))   macro(data, 41)
+#define MRECURSION43( macro, data)    MRECURSION42(  macro, DEC_(data))   macro(data, 42)
+#define MRECURSION44( macro, data)    MRECURSION43(  macro, DEC_(data))   macro(data, 43)
+#define MRECURSION45( macro, data)    MRECURSION44(  macro, DEC_(data))   macro(data, 44)
+#define MRECURSION46( macro, data)    MRECURSION45(  macro, DEC_(data))   macro(data, 45)
+#define MRECURSION47( macro, data)    MRECURSION46(  macro, DEC_(data))   macro(data, 46)
+#define MRECURSION48( macro, data)    MRECURSION47(  macro, DEC_(data))   macro(data, 47)
+#define MRECURSION49( macro, data)    MRECURSION48(  macro, DEC_(data))   macro(data, 48)
+#define MRECURSION50( macro, data)    MRECURSION49(  macro, DEC_(data))   macro(data, 49)
+#define MRECURSION51( macro, data)    MRECURSION50(  macro, DEC_(data))   macro(data, 50)
+#define MRECURSION52( macro, data)    MRECURSION51(  macro, DEC_(data))   macro(data, 51)
+#define MRECURSION53( macro, data)    MRECURSION52(  macro, DEC_(data))   macro(data, 52)
+#define MRECURSION54( macro, data)    MRECURSION53(  macro, DEC_(data))   macro(data, 53)
+#define MRECURSION55( macro, data)    MRECURSION54(  macro, DEC_(data))   macro(data, 54)
+#define MRECURSION56( macro, data)    MRECURSION55(  macro, DEC_(data))   macro(data, 55)
+#define MRECURSION57( macro, data)    MRECURSION56(  macro, DEC_(data))   macro(data, 56)
+#define MRECURSION58( macro, data)    MRECURSION57(  macro, DEC_(data))   macro(data, 57)
+#define MRECURSION59( macro, data)    MRECURSION58(  macro, DEC_(data))   macro(data, 58)
+#define MRECURSION60( macro, data)    MRECURSION59(  macro, DEC_(data))   macro(data, 59)
+#define MRECURSION61( macro, data)    MRECURSION60(  macro, DEC_(data))   macro(data, 60)
+#define MRECURSION62( macro, data)    MRECURSION61(  macro, DEC_(data))   macro(data, 61)
+#define MRECURSION63( macro, data)    MRECURSION62(  macro, DEC_(data))   macro(data, 62)
+#define MRECURSION64( macro, data)    MRECURSION63(  macro, DEC_(data))   macro(data, 63)
+#define MRECURSION65( macro, data)    MRECURSION64(  macro, DEC_(data))   macro(data, 64)
+#define MRECURSION66( macro, data)    MRECURSION65(  macro, DEC_(data))   macro(data, 65)
+#define MRECURSION67( macro, data)    MRECURSION66(  macro, DEC_(data))   macro(data, 66)
+#define MRECURSION68( macro, data)    MRECURSION67(  macro, DEC_(data))   macro(data, 67)
+#define MRECURSION69( macro, data)    MRECURSION68(  macro, DEC_(data))   macro(data, 68)
+#define MRECURSION70( macro, data)    MRECURSION69(  macro, DEC_(data))   macro(data, 69)
+#define MRECURSION71( macro, data)    MRECURSION70(  macro, DEC_(data))   macro(data, 70)
+#define MRECURSION72( macro, data)    MRECURSION71(  macro, DEC_(data))   macro(data, 71)
+#define MRECURSION73( macro, data)    MRECURSION72(  macro, DEC_(data))   macro(data, 72)
+#define MRECURSION74( macro, data)    MRECURSION73(  macro, DEC_(data))   macro(data, 73)
+#define MRECURSION75( macro, data)    MRECURSION74(  macro, DEC_(data))   macro(data, 74)
+#define MRECURSION76( macro, data)    MRECURSION75(  macro, DEC_(data))   macro(data, 75)
+#define MRECURSION77( macro, data)    MRECURSION76(  macro, DEC_(data))   macro(data, 76)
+#define MRECURSION78( macro, data)    MRECURSION77(  macro, DEC_(data))   macro(data, 77)
+#define MRECURSION79( macro, data)    MRECURSION78(  macro, DEC_(data))   macro(data, 78)
+#define MRECURSION80( macro, data)    MRECURSION79(  macro, DEC_(data))   macro(data, 79)
+#define MRECURSION81( macro, data)    MRECURSION80(  macro, DEC_(data))   macro(data, 80)
+#define MRECURSION82( macro, data)    MRECURSION81(  macro, DEC_(data))   macro(data, 81)
+#define MRECURSION83( macro, data)    MRECURSION82(  macro, DEC_(data))   macro(data, 82)
+#define MRECURSION84( macro, data)    MRECURSION83(  macro, DEC_(data))   macro(data, 83)
+#define MRECURSION85( macro, data)    MRECURSION84(  macro, DEC_(data))   macro(data, 84)
+#define MRECURSION86( macro, data)    MRECURSION85(  macro, DEC_(data))   macro(data, 85)
+#define MRECURSION87( macro, data)    MRECURSION86(  macro, DEC_(data))   macro(data, 86)
+#define MRECURSION88( macro, data)    MRECURSION87(  macro, DEC_(data))   macro(data, 87)
+#define MRECURSION89( macro, data)    MRECURSION88(  macro, DEC_(data))   macro(data, 88)
+#define MRECURSION90( macro, data)    MRECURSION89(  macro, DEC_(data))   macro(data, 89)
+#define MRECURSION91( macro, data)    MRECURSION90(  macro, DEC_(data))   macro(data, 90)
+#define MRECURSION92( macro, data)    MRECURSION91(  macro, DEC_(data))   macro(data, 91)
+#define MRECURSION93( macro, data)    MRECURSION92(  macro, DEC_(data))   macro(data, 92)
+#define MRECURSION94( macro, data)    MRECURSION93(  macro, DEC_(data))   macro(data, 93)
+#define MRECURSION95( macro, data)    MRECURSION94(  macro, DEC_(data))   macro(data, 94)
+#define MRECURSION96( macro, data)    MRECURSION95(  macro, DEC_(data))   macro(data, 95)
+#define MRECURSION97( macro, data)    MRECURSION96(  macro, DEC_(data))   macro(data, 96)
+#define MRECURSION98( macro, data)    MRECURSION97(  macro, DEC_(data))   macro(data, 97)
+#define MRECURSION99( macro, data)    MRECURSION98(  macro, DEC_(data))   macro(data, 98)
+#define MRECURSION100(macro, data)    MRECURSION99(  macro, DEC_(data))   macro(data, 99)
+#define MRECURSION101(macro, data)    MRECURSION100(  macro, DEC_(data))   macro(data, 100)
+#define MRECURSION102(macro, data)    MRECURSION101(  macro, DEC_(data))   macro(data, 101)
+#define MRECURSION103(macro, data)    MRECURSION102(  macro, DEC_(data))   macro(data, 102)
+#define MRECURSION104(macro, data)    MRECURSION103(  macro, DEC_(data))   macro(data, 103)
+#define MRECURSION105(macro, data)    MRECURSION104(  macro, DEC_(data))   macro(data, 104)
+#define MRECURSION106(macro, data)    MRECURSION105(  macro, DEC_(data))   macro(data, 105)
+#define MRECURSION107(macro, data)    MRECURSION106(  macro, DEC_(data))   macro(data, 106)
+#define MRECURSION108(macro, data)    MRECURSION107(  macro, DEC_(data))   macro(data, 107)
+#define MRECURSION109(macro, data)    MRECURSION108(  macro, DEC_(data))   macro(data, 108)
+#define MRECURSION110(macro, data)    MRECURSION109(  macro, DEC_(data))   macro(data, 109)
+#define MRECURSION111(macro, data)    MRECURSION110(  macro, DEC_(data))   macro(data, 110)
+#define MRECURSION112(macro, data)    MRECURSION111(  macro, DEC_(data))   macro(data, 111)
+#define MRECURSION113(macro, data)    MRECURSION112(  macro, DEC_(data))   macro(data, 112)
+#define MRECURSION114(macro, data)    MRECURSION113(  macro, DEC_(data))   macro(data, 113)
+#define MRECURSION115(macro, data)    MRECURSION114(  macro, DEC_(data))   macro(data, 114)
+#define MRECURSION116(macro, data)    MRECURSION115(  macro, DEC_(data))   macro(data, 115)
+#define MRECURSION117(macro, data)    MRECURSION116(  macro, DEC_(data))   macro(data, 116)
+#define MRECURSION118(macro, data)    MRECURSION117(  macro, DEC_(data))   macro(data, 117)
+#define MRECURSION119(macro, data)    MRECURSION118(  macro, DEC_(data))   macro(data, 118)
+#define MRECURSION120(macro, data)    MRECURSION119(  macro, DEC_(data))   macro(data, 119)
+#define MRECURSION121(macro, data)    MRECURSION120(  macro, DEC_(data))   macro(data, 120)
+#define MRECURSION122(macro, data)    MRECURSION121(  macro, DEC_(data))   macro(data, 121)
+#define MRECURSION123(macro, data)    MRECURSION122(  macro, DEC_(data))   macro(data, 122)
+#define MRECURSION124(macro, data)    MRECURSION123(  macro, DEC_(data))   macro(data, 123)
+#define MRECURSION125(macro, data)    MRECURSION124(  macro, DEC_(data))   macro(data, 124)
+#define MRECURSION126(macro, data)    MRECURSION125(  macro, DEC_(data))   macro(data, 125)
+#define MRECURSION127(macro, data)    MRECURSION126(  macro, DEC_(data))   macro(data, 126)
+#define MRECURSION128(macro, data)    MRECURSION127(  macro, DEC_(data))   macro(data, 127)
+#define MRECURSION129(macro, data)    MRECURSION128(  macro, DEC_(data))   macro(data, 128)
+#define MRECURSION130(macro, data)    MRECURSION129(  macro, DEC_(data))   macro(data, 129)
+#define MRECURSION131(macro, data)    MRECURSION130(  macro, DEC_(data))   macro(data, 130)
+#define MRECURSION132(macro, data)    MRECURSION131(  macro, DEC_(data))   macro(data, 131)
+#define MRECURSION133(macro, data)    MRECURSION132(  macro, DEC_(data))   macro(data, 132)
+#define MRECURSION134(macro, data)    MRECURSION133(  macro, DEC_(data))   macro(data, 133)
+#define MRECURSION135(macro, data)    MRECURSION134(  macro, DEC_(data))   macro(data, 134)
+#define MRECURSION136(macro, data)    MRECURSION135(  macro, DEC_(data))   macro(data, 135)
+#define MRECURSION137(macro, data)    MRECURSION136(  macro, DEC_(data))   macro(data, 136)
+#define MRECURSION138(macro, data)    MRECURSION137(  macro, DEC_(data))   macro(data, 137)
+#define MRECURSION139(macro, data)    MRECURSION138(  macro, DEC_(data))   macro(data, 138)
+#define MRECURSION140(macro, data)    MRECURSION139(  macro, DEC_(data))   macro(data, 139)
+#define MRECURSION141(macro, data)    MRECURSION140(  macro, DEC_(data))   macro(data, 140)
+#define MRECURSION142(macro, data)    MRECURSION141(  macro, DEC_(data))   macro(data, 141)
+#define MRECURSION143(macro, data)    MRECURSION142(  macro, DEC_(data))   macro(data, 142)
+#define MRECURSION144(macro, data)    MRECURSION143(  macro, DEC_(data))   macro(data, 143)
+#define MRECURSION145(macro, data)    MRECURSION144(  macro, DEC_(data))   macro(data, 144)
+#define MRECURSION146(macro, data)    MRECURSION145(  macro, DEC_(data))   macro(data, 145)
+#define MRECURSION147(macro, data)    MRECURSION146(  macro, DEC_(data))   macro(data, 146)
+#define MRECURSION148(macro, data)    MRECURSION147(  macro, DEC_(data))   macro(data, 147)
+#define MRECURSION149(macro, data)    MRECURSION148(  macro, DEC_(data))   macro(data, 148)
+#define MRECURSION150(macro, data)    MRECURSION149(  macro, DEC_(data))   macro(data, 149)
+#define MRECURSION151(macro, data)    MRECURSION150(  macro, DEC_(data))   macro(data, 150)
+#define MRECURSION152(macro, data)    MRECURSION151(  macro, DEC_(data))   macro(data, 151)
+#define MRECURSION153(macro, data)    MRECURSION152(  macro, DEC_(data))   macro(data, 152)
+#define MRECURSION154(macro, data)    MRECURSION153(  macro, DEC_(data))   macro(data, 153)
+#define MRECURSION155(macro, data)    MRECURSION154(  macro, DEC_(data))   macro(data, 154)
+#define MRECURSION156(macro, data)    MRECURSION155(  macro, DEC_(data))   macro(data, 155)
+#define MRECURSION157(macro, data)    MRECURSION156(  macro, DEC_(data))   macro(data, 156)
+#define MRECURSION158(macro, data)    MRECURSION157(  macro, DEC_(data))   macro(data, 157)
+#define MRECURSION159(macro, data)    MRECURSION158(  macro, DEC_(data))   macro(data, 158)
+#define MRECURSION160(macro, data)    MRECURSION159(  macro, DEC_(data))   macro(data, 159)
+#define MRECURSION161(macro, data)    MRECURSION160(  macro, DEC_(data))   macro(data, 160)
+#define MRECURSION162(macro, data)    MRECURSION161(  macro, DEC_(data))   macro(data, 161)
+#define MRECURSION163(macro, data)    MRECURSION162(  macro, DEC_(data))   macro(data, 162)
+#define MRECURSION164(macro, data)    MRECURSION163(  macro, DEC_(data))   macro(data, 163)
+#define MRECURSION165(macro, data)    MRECURSION164(  macro, DEC_(data))   macro(data, 164)
+#define MRECURSION166(macro, data)    MRECURSION165(  macro, DEC_(data))   macro(data, 165)
+#define MRECURSION167(macro, data)    MRECURSION166(  macro, DEC_(data))   macro(data, 166)
+#define MRECURSION168(macro, data)    MRECURSION167(  macro, DEC_(data))   macro(data, 167)
+#define MRECURSION169(macro, data)    MRECURSION168(  macro, DEC_(data))   macro(data, 168)
+#define MRECURSION170(macro, data)    MRECURSION169(  macro, DEC_(data))   macro(data, 169)
+#define MRECURSION171(macro, data)    MRECURSION170(  macro, DEC_(data))   macro(data, 170)
+#define MRECURSION172(macro, data)    MRECURSION171(  macro, DEC_(data))   macro(data, 171)
+#define MRECURSION173(macro, data)    MRECURSION172(  macro, DEC_(data))   macro(data, 172)
+#define MRECURSION174(macro, data)    MRECURSION173(  macro, DEC_(data))   macro(data, 173)
+#define MRECURSION175(macro, data)    MRECURSION174(  macro, DEC_(data))   macro(data, 174)
+#define MRECURSION176(macro, data)    MRECURSION175(  macro, DEC_(data))   macro(data, 175)
+#define MRECURSION177(macro, data)    MRECURSION176(  macro, DEC_(data))   macro(data, 176)
+#define MRECURSION178(macro, data)    MRECURSION177(  macro, DEC_(data))   macro(data, 177)
+#define MRECURSION179(macro, data)    MRECURSION178(  macro, DEC_(data))   macro(data, 178)
+#define MRECURSION180(macro, data)    MRECURSION179(  macro, DEC_(data))   macro(data, 179)
+#define MRECURSION181(macro, data)    MRECURSION180(  macro, DEC_(data))   macro(data, 180)
+#define MRECURSION182(macro, data)    MRECURSION181(  macro, DEC_(data))   macro(data, 181)
+#define MRECURSION183(macro, data)    MRECURSION182(  macro, DEC_(data))   macro(data, 182)
+#define MRECURSION184(macro, data)    MRECURSION183(  macro, DEC_(data))   macro(data, 183)
+#define MRECURSION185(macro, data)    MRECURSION184(  macro, DEC_(data))   macro(data, 184)
+#define MRECURSION186(macro, data)    MRECURSION185(  macro, DEC_(data))   macro(data, 185)
+#define MRECURSION187(macro, data)    MRECURSION186(  macro, DEC_(data))   macro(data, 186)
+#define MRECURSION188(macro, data)    MRECURSION187(  macro, DEC_(data))   macro(data, 187)
+#define MRECURSION189(macro, data)    MRECURSION188(  macro, DEC_(data))   macro(data, 188)
+#define MRECURSION190(macro, data)    MRECURSION189(  macro, DEC_(data))   macro(data, 189)
+#define MRECURSION191(macro, data)    MRECURSION190(  macro, DEC_(data))   macro(data, 190)
+#define MRECURSION192(macro, data)    MRECURSION191(  macro, DEC_(data))   macro(data, 191)
+#define MRECURSION193(macro, data)    MRECURSION192(  macro, DEC_(data))   macro(data, 192)
+#define MRECURSION194(macro, data)    MRECURSION193(  macro, DEC_(data))   macro(data, 193)
+#define MRECURSION195(macro, data)    MRECURSION194(  macro, DEC_(data))   macro(data, 194)
+#define MRECURSION196(macro, data)    MRECURSION195(  macro, DEC_(data))   macro(data, 195)
+#define MRECURSION197(macro, data)    MRECURSION196(  macro, DEC_(data))   macro(data, 196)
+#define MRECURSION198(macro, data)    MRECURSION197(  macro, DEC_(data))   macro(data, 197)
+#define MRECURSION199(macro, data)    MRECURSION198(  macro, DEC_(data))   macro(data, 198)
+#define MRECURSION200(macro, data)    MRECURSION199(  macro, DEC_(data))   macro(data, 199)
+#define MRECURSION201(macro, data)    MRECURSION200(  macro, DEC_(data))   macro(data, 200)
+#define MRECURSION202(macro, data)    MRECURSION201(  macro, DEC_(data))   macro(data, 201)
+#define MRECURSION203(macro, data)    MRECURSION202(  macro, DEC_(data))   macro(data, 202)
+#define MRECURSION204(macro, data)    MRECURSION203(  macro, DEC_(data))   macro(data, 203)
+#define MRECURSION205(macro, data)    MRECURSION204(  macro, DEC_(data))   macro(data, 204)
+#define MRECURSION206(macro, data)    MRECURSION205(  macro, DEC_(data))   macro(data, 205)
+#define MRECURSION207(macro, data)    MRECURSION206(  macro, DEC_(data))   macro(data, 206)
+#define MRECURSION208(macro, data)    MRECURSION207(  macro, DEC_(data))   macro(data, 207)
+#define MRECURSION209(macro, data)    MRECURSION208(  macro, DEC_(data))   macro(data, 208)
+#define MRECURSION210(macro, data)    MRECURSION209(  macro, DEC_(data))   macro(data, 209)
+#define MRECURSION211(macro, data)    MRECURSION210(  macro, DEC_(data))   macro(data, 210)
+#define MRECURSION212(macro, data)    MRECURSION211(  macro, DEC_(data))   macro(data, 211)
+#define MRECURSION213(macro, data)    MRECURSION212(  macro, DEC_(data))   macro(data, 212)
+#define MRECURSION214(macro, data)    MRECURSION213(  macro, DEC_(data))   macro(data, 213)
+#define MRECURSION215(macro, data)    MRECURSION214(  macro, DEC_(data))   macro(data, 214)
+#define MRECURSION216(macro, data)    MRECURSION215(  macro, DEC_(data))   macro(data, 215)
+#define MRECURSION217(macro, data)    MRECURSION216(  macro, DEC_(data))   macro(data, 216)
+#define MRECURSION218(macro, data)    MRECURSION217(  macro, DEC_(data))   macro(data, 217)
+#define MRECURSION219(macro, data)    MRECURSION218(  macro, DEC_(data))   macro(data, 218)
+#define MRECURSION220(macro, data)    MRECURSION219(  macro, DEC_(data))   macro(data, 219)
+#define MRECURSION221(macro, data)    MRECURSION220(  macro, DEC_(data))   macro(data, 220)
+#define MRECURSION222(macro, data)    MRECURSION221(  macro, DEC_(data))   macro(data, 221)
+#define MRECURSION223(macro, data)    MRECURSION222(  macro, DEC_(data))   macro(data, 222)
+#define MRECURSION224(macro, data)    MRECURSION223(  macro, DEC_(data))   macro(data, 223)
+#define MRECURSION225(macro, data)    MRECURSION224(  macro, DEC_(data))   macro(data, 224)
+#define MRECURSION226(macro, data)    MRECURSION225(  macro, DEC_(data))   macro(data, 225)
+#define MRECURSION227(macro, data)    MRECURSION226(  macro, DEC_(data))   macro(data, 226)
+#define MRECURSION228(macro, data)    MRECURSION227(  macro, DEC_(data))   macro(data, 227)
+#define MRECURSION229(macro, data)    MRECURSION228(  macro, DEC_(data))   macro(data, 228)
+#define MRECURSION230(macro, data)    MRECURSION229(  macro, DEC_(data))   macro(data, 229)
+#define MRECURSION231(macro, data)    MRECURSION230(  macro, DEC_(data))   macro(data, 230)
+#define MRECURSION232(macro, data)    MRECURSION231(  macro, DEC_(data))   macro(data, 231)
+#define MRECURSION233(macro, data)    MRECURSION232(  macro, DEC_(data))   macro(data, 232)
+#define MRECURSION234(macro, data)    MRECURSION233(  macro, DEC_(data))   macro(data, 233)
+#define MRECURSION235(macro, data)    MRECURSION234(  macro, DEC_(data))   macro(data, 234)
+#define MRECURSION236(macro, data)    MRECURSION235(  macro, DEC_(data))   macro(data, 235)
+#define MRECURSION237(macro, data)    MRECURSION236(  macro, DEC_(data))   macro(data, 236)
+#define MRECURSION238(macro, data)    MRECURSION237(  macro, DEC_(data))   macro(data, 237)
+#define MRECURSION239(macro, data)    MRECURSION238(  macro, DEC_(data))   macro(data, 238)
+#define MRECURSION240(macro, data)    MRECURSION239(  macro, DEC_(data))   macro(data, 239)
+#define MRECURSION241(macro, data)    MRECURSION240(  macro, DEC_(data))   macro(data, 240)
+#define MRECURSION242(macro, data)    MRECURSION241(  macro, DEC_(data))   macro(data, 241)
+#define MRECURSION243(macro, data)    MRECURSION242(  macro, DEC_(data))   macro(data, 242)
+#define MRECURSION244(macro, data)    MRECURSION243(  macro, DEC_(data))   macro(data, 243)
+#define MRECURSION245(macro, data)    MRECURSION244(  macro, DEC_(data))   macro(data, 244)
+#define MRECURSION246(macro, data)    MRECURSION245(  macro, DEC_(data))   macro(data, 245)
+#define MRECURSION247(macro, data)    MRECURSION246(  macro, DEC_(data))   macro(data, 246)
+#define MRECURSION248(macro, data)    MRECURSION247(  macro, DEC_(data))   macro(data, 247)
+#define MRECURSION249(macro, data)    MRECURSION248(  macro, DEC_(data))   macro(data, 248)
+#define MRECURSION250(macro, data)    MRECURSION249(  macro, DEC_(data))   macro(data, 249)
+#define MRECURSION251(macro, data)    MRECURSION250(  macro, DEC_(data))   macro(data, 250)
+#define MRECURSION252(macro, data)    MRECURSION251(  macro, DEC_(data))   macro(data, 251)
+#define MRECURSION253(macro, data)    MRECURSION252(  macro, DEC_(data))   macro(data, 252)
+#define MRECURSION254(macro, data)    MRECURSION253(  macro, DEC_(data))   macro(data, 253)
+#define MRECURSION255(macro, data)    MRECURSION254(  macro, DEC_(data))   macro(data, 254)
+#define MRECURSION256(macro, data)    MRECURSION255(  macro, DEC_(data))   macro(data, 255)
+
+/** @} */
+
+#endif  /* _MRECURSION_H_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrepeat.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrepeat.h
index 5b0eb0a..045c197 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrepeat.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/mrepeat.h
@@ -1,328 +1,328 @@
-/**
- * \file
- *
- * \brief Preprocessor macro repeating utils.
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _MREPEAT_H_
-#define _MREPEAT_H_
-
-/**
- * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat
- *
- * \ingroup group_sam0_utils
- *
- * @{
- */
-
-#include "preprocessor.h"
-
-/** Maximal number of repetitions supported by MREPEAT. */
-#define MREPEAT_LIMIT   256
-
-/** \brief Macro repeat.
- *
- * This macro represents a horizontal repetition construct.
- *
- * \param[in] count  The number of repetitious calls to macro. Valid values
- *                   range from 0 to MREPEAT_LIMIT.
- * \param[in] macro  A binary operation of the form macro(n, data). This macro
- *                   is expanded by MREPEAT with the current repetition number
- *                   and the auxiliary data argument.
- * \param[in] data   Auxiliary data passed to macro.
- *
- * \return       <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
- */
-#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)
-
-#define MREPEAT0(  macro, data)
-#define MREPEAT1(  macro, data)    MREPEAT0(  macro, data)   macro(  0, data)
-#define MREPEAT2(  macro, data)    MREPEAT1(  macro, data)   macro(  1, data)
-#define MREPEAT3(  macro, data)    MREPEAT2(  macro, data)   macro(  2, data)
-#define MREPEAT4(  macro, data)    MREPEAT3(  macro, data)   macro(  3, data)
-#define MREPEAT5(  macro, data)    MREPEAT4(  macro, data)   macro(  4, data)
-#define MREPEAT6(  macro, data)    MREPEAT5(  macro, data)   macro(  5, data)
-#define MREPEAT7(  macro, data)    MREPEAT6(  macro, data)   macro(  6, data)
-#define MREPEAT8(  macro, data)    MREPEAT7(  macro, data)   macro(  7, data)
-#define MREPEAT9(  macro, data)    MREPEAT8(  macro, data)   macro(  8, data)
-#define MREPEAT10( macro, data)    MREPEAT9(  macro, data)   macro(  9, data)
-#define MREPEAT11( macro, data)    MREPEAT10( macro, data)   macro( 10, data)
-#define MREPEAT12( macro, data)    MREPEAT11( macro, data)   macro( 11, data)
-#define MREPEAT13( macro, data)    MREPEAT12( macro, data)   macro( 12, data)
-#define MREPEAT14( macro, data)    MREPEAT13( macro, data)   macro( 13, data)
-#define MREPEAT15( macro, data)    MREPEAT14( macro, data)   macro( 14, data)
-#define MREPEAT16( macro, data)    MREPEAT15( macro, data)   macro( 15, data)
-#define MREPEAT17( macro, data)    MREPEAT16( macro, data)   macro( 16, data)
-#define MREPEAT18( macro, data)    MREPEAT17( macro, data)   macro( 17, data)
-#define MREPEAT19( macro, data)    MREPEAT18( macro, data)   macro( 18, data)
-#define MREPEAT20( macro, data)    MREPEAT19( macro, data)   macro( 19, data)
-#define MREPEAT21( macro, data)    MREPEAT20( macro, data)   macro( 20, data)
-#define MREPEAT22( macro, data)    MREPEAT21( macro, data)   macro( 21, data)
-#define MREPEAT23( macro, data)    MREPEAT22( macro, data)   macro( 22, data)
-#define MREPEAT24( macro, data)    MREPEAT23( macro, data)   macro( 23, data)
-#define MREPEAT25( macro, data)    MREPEAT24( macro, data)   macro( 24, data)
-#define MREPEAT26( macro, data)    MREPEAT25( macro, data)   macro( 25, data)
-#define MREPEAT27( macro, data)    MREPEAT26( macro, data)   macro( 26, data)
-#define MREPEAT28( macro, data)    MREPEAT27( macro, data)   macro( 27, data)
-#define MREPEAT29( macro, data)    MREPEAT28( macro, data)   macro( 28, data)
-#define MREPEAT30( macro, data)    MREPEAT29( macro, data)   macro( 29, data)
-#define MREPEAT31( macro, data)    MREPEAT30( macro, data)   macro( 30, data)
-#define MREPEAT32( macro, data)    MREPEAT31( macro, data)   macro( 31, data)
-#define MREPEAT33( macro, data)    MREPEAT32( macro, data)   macro( 32, data)
-#define MREPEAT34( macro, data)    MREPEAT33( macro, data)   macro( 33, data)
-#define MREPEAT35( macro, data)    MREPEAT34( macro, data)   macro( 34, data)
-#define MREPEAT36( macro, data)    MREPEAT35( macro, data)   macro( 35, data)
-#define MREPEAT37( macro, data)    MREPEAT36( macro, data)   macro( 36, data)
-#define MREPEAT38( macro, data)    MREPEAT37( macro, data)   macro( 37, data)
-#define MREPEAT39( macro, data)    MREPEAT38( macro, data)   macro( 38, data)
-#define MREPEAT40( macro, data)    MREPEAT39( macro, data)   macro( 39, data)
-#define MREPEAT41( macro, data)    MREPEAT40( macro, data)   macro( 40, data)
-#define MREPEAT42( macro, data)    MREPEAT41( macro, data)   macro( 41, data)
-#define MREPEAT43( macro, data)    MREPEAT42( macro, data)   macro( 42, data)
-#define MREPEAT44( macro, data)    MREPEAT43( macro, data)   macro( 43, data)
-#define MREPEAT45( macro, data)    MREPEAT44( macro, data)   macro( 44, data)
-#define MREPEAT46( macro, data)    MREPEAT45( macro, data)   macro( 45, data)
-#define MREPEAT47( macro, data)    MREPEAT46( macro, data)   macro( 46, data)
-#define MREPEAT48( macro, data)    MREPEAT47( macro, data)   macro( 47, data)
-#define MREPEAT49( macro, data)    MREPEAT48( macro, data)   macro( 48, data)
-#define MREPEAT50( macro, data)    MREPEAT49( macro, data)   macro( 49, data)
-#define MREPEAT51( macro, data)    MREPEAT50( macro, data)   macro( 50, data)
-#define MREPEAT52( macro, data)    MREPEAT51( macro, data)   macro( 51, data)
-#define MREPEAT53( macro, data)    MREPEAT52( macro, data)   macro( 52, data)
-#define MREPEAT54( macro, data)    MREPEAT53( macro, data)   macro( 53, data)
-#define MREPEAT55( macro, data)    MREPEAT54( macro, data)   macro( 54, data)
-#define MREPEAT56( macro, data)    MREPEAT55( macro, data)   macro( 55, data)
-#define MREPEAT57( macro, data)    MREPEAT56( macro, data)   macro( 56, data)
-#define MREPEAT58( macro, data)    MREPEAT57( macro, data)   macro( 57, data)
-#define MREPEAT59( macro, data)    MREPEAT58( macro, data)   macro( 58, data)
-#define MREPEAT60( macro, data)    MREPEAT59( macro, data)   macro( 59, data)
-#define MREPEAT61( macro, data)    MREPEAT60( macro, data)   macro( 60, data)
-#define MREPEAT62( macro, data)    MREPEAT61( macro, data)   macro( 61, data)
-#define MREPEAT63( macro, data)    MREPEAT62( macro, data)   macro( 62, data)
-#define MREPEAT64( macro, data)    MREPEAT63( macro, data)   macro( 63, data)
-#define MREPEAT65( macro, data)    MREPEAT64( macro, data)   macro( 64, data)
-#define MREPEAT66( macro, data)    MREPEAT65( macro, data)   macro( 65, data)
-#define MREPEAT67( macro, data)    MREPEAT66( macro, data)   macro( 66, data)
-#define MREPEAT68( macro, data)    MREPEAT67( macro, data)   macro( 67, data)
-#define MREPEAT69( macro, data)    MREPEAT68( macro, data)   macro( 68, data)
-#define MREPEAT70( macro, data)    MREPEAT69( macro, data)   macro( 69, data)
-#define MREPEAT71( macro, data)    MREPEAT70( macro, data)   macro( 70, data)
-#define MREPEAT72( macro, data)    MREPEAT71( macro, data)   macro( 71, data)
-#define MREPEAT73( macro, data)    MREPEAT72( macro, data)   macro( 72, data)
-#define MREPEAT74( macro, data)    MREPEAT73( macro, data)   macro( 73, data)
-#define MREPEAT75( macro, data)    MREPEAT74( macro, data)   macro( 74, data)
-#define MREPEAT76( macro, data)    MREPEAT75( macro, data)   macro( 75, data)
-#define MREPEAT77( macro, data)    MREPEAT76( macro, data)   macro( 76, data)
-#define MREPEAT78( macro, data)    MREPEAT77( macro, data)   macro( 77, data)
-#define MREPEAT79( macro, data)    MREPEAT78( macro, data)   macro( 78, data)
-#define MREPEAT80( macro, data)    MREPEAT79( macro, data)   macro( 79, data)
-#define MREPEAT81( macro, data)    MREPEAT80( macro, data)   macro( 80, data)
-#define MREPEAT82( macro, data)    MREPEAT81( macro, data)   macro( 81, data)
-#define MREPEAT83( macro, data)    MREPEAT82( macro, data)   macro( 82, data)
-#define MREPEAT84( macro, data)    MREPEAT83( macro, data)   macro( 83, data)
-#define MREPEAT85( macro, data)    MREPEAT84( macro, data)   macro( 84, data)
-#define MREPEAT86( macro, data)    MREPEAT85( macro, data)   macro( 85, data)
-#define MREPEAT87( macro, data)    MREPEAT86( macro, data)   macro( 86, data)
-#define MREPEAT88( macro, data)    MREPEAT87( macro, data)   macro( 87, data)
-#define MREPEAT89( macro, data)    MREPEAT88( macro, data)   macro( 88, data)
-#define MREPEAT90( macro, data)    MREPEAT89( macro, data)   macro( 89, data)
-#define MREPEAT91( macro, data)    MREPEAT90( macro, data)   macro( 90, data)
-#define MREPEAT92( macro, data)    MREPEAT91( macro, data)   macro( 91, data)
-#define MREPEAT93( macro, data)    MREPEAT92( macro, data)   macro( 92, data)
-#define MREPEAT94( macro, data)    MREPEAT93( macro, data)   macro( 93, data)
-#define MREPEAT95( macro, data)    MREPEAT94( macro, data)   macro( 94, data)
-#define MREPEAT96( macro, data)    MREPEAT95( macro, data)   macro( 95, data)
-#define MREPEAT97( macro, data)    MREPEAT96( macro, data)   macro( 96, data)
-#define MREPEAT98( macro, data)    MREPEAT97( macro, data)   macro( 97, data)
-#define MREPEAT99( macro, data)    MREPEAT98( macro, data)   macro( 98, data)
-#define MREPEAT100(macro, data)    MREPEAT99( macro, data)   macro( 99, data)
-#define MREPEAT101(macro, data)    MREPEAT100(macro, data)   macro(100, data)
-#define MREPEAT102(macro, data)    MREPEAT101(macro, data)   macro(101, data)
-#define MREPEAT103(macro, data)    MREPEAT102(macro, data)   macro(102, data)
-#define MREPEAT104(macro, data)    MREPEAT103(macro, data)   macro(103, data)
-#define MREPEAT105(macro, data)    MREPEAT104(macro, data)   macro(104, data)
-#define MREPEAT106(macro, data)    MREPEAT105(macro, data)   macro(105, data)
-#define MREPEAT107(macro, data)    MREPEAT106(macro, data)   macro(106, data)
-#define MREPEAT108(macro, data)    MREPEAT107(macro, data)   macro(107, data)
-#define MREPEAT109(macro, data)    MREPEAT108(macro, data)   macro(108, data)
-#define MREPEAT110(macro, data)    MREPEAT109(macro, data)   macro(109, data)
-#define MREPEAT111(macro, data)    MREPEAT110(macro, data)   macro(110, data)
-#define MREPEAT112(macro, data)    MREPEAT111(macro, data)   macro(111, data)
-#define MREPEAT113(macro, data)    MREPEAT112(macro, data)   macro(112, data)
-#define MREPEAT114(macro, data)    MREPEAT113(macro, data)   macro(113, data)
-#define MREPEAT115(macro, data)    MREPEAT114(macro, data)   macro(114, data)
-#define MREPEAT116(macro, data)    MREPEAT115(macro, data)   macro(115, data)
-#define MREPEAT117(macro, data)    MREPEAT116(macro, data)   macro(116, data)
-#define MREPEAT118(macro, data)    MREPEAT117(macro, data)   macro(117, data)
-#define MREPEAT119(macro, data)    MREPEAT118(macro, data)   macro(118, data)
-#define MREPEAT120(macro, data)    MREPEAT119(macro, data)   macro(119, data)
-#define MREPEAT121(macro, data)    MREPEAT120(macro, data)   macro(120, data)
-#define MREPEAT122(macro, data)    MREPEAT121(macro, data)   macro(121, data)
-#define MREPEAT123(macro, data)    MREPEAT122(macro, data)   macro(122, data)
-#define MREPEAT124(macro, data)    MREPEAT123(macro, data)   macro(123, data)
-#define MREPEAT125(macro, data)    MREPEAT124(macro, data)   macro(124, data)
-#define MREPEAT126(macro, data)    MREPEAT125(macro, data)   macro(125, data)
-#define MREPEAT127(macro, data)    MREPEAT126(macro, data)   macro(126, data)
-#define MREPEAT128(macro, data)    MREPEAT127(macro, data)   macro(127, data)
-#define MREPEAT129(macro, data)    MREPEAT128(macro, data)   macro(128, data)
-#define MREPEAT130(macro, data)    MREPEAT129(macro, data)   macro(129, data)
-#define MREPEAT131(macro, data)    MREPEAT130(macro, data)   macro(130, data)
-#define MREPEAT132(macro, data)    MREPEAT131(macro, data)   macro(131, data)
-#define MREPEAT133(macro, data)    MREPEAT132(macro, data)   macro(132, data)
-#define MREPEAT134(macro, data)    MREPEAT133(macro, data)   macro(133, data)
-#define MREPEAT135(macro, data)    MREPEAT134(macro, data)   macro(134, data)
-#define MREPEAT136(macro, data)    MREPEAT135(macro, data)   macro(135, data)
-#define MREPEAT137(macro, data)    MREPEAT136(macro, data)   macro(136, data)
-#define MREPEAT138(macro, data)    MREPEAT137(macro, data)   macro(137, data)
-#define MREPEAT139(macro, data)    MREPEAT138(macro, data)   macro(138, data)
-#define MREPEAT140(macro, data)    MREPEAT139(macro, data)   macro(139, data)
-#define MREPEAT141(macro, data)    MREPEAT140(macro, data)   macro(140, data)
-#define MREPEAT142(macro, data)    MREPEAT141(macro, data)   macro(141, data)
-#define MREPEAT143(macro, data)    MREPEAT142(macro, data)   macro(142, data)
-#define MREPEAT144(macro, data)    MREPEAT143(macro, data)   macro(143, data)
-#define MREPEAT145(macro, data)    MREPEAT144(macro, data)   macro(144, data)
-#define MREPEAT146(macro, data)    MREPEAT145(macro, data)   macro(145, data)
-#define MREPEAT147(macro, data)    MREPEAT146(macro, data)   macro(146, data)
-#define MREPEAT148(macro, data)    MREPEAT147(macro, data)   macro(147, data)
-#define MREPEAT149(macro, data)    MREPEAT148(macro, data)   macro(148, data)
-#define MREPEAT150(macro, data)    MREPEAT149(macro, data)   macro(149, data)
-#define MREPEAT151(macro, data)    MREPEAT150(macro, data)   macro(150, data)
-#define MREPEAT152(macro, data)    MREPEAT151(macro, data)   macro(151, data)
-#define MREPEAT153(macro, data)    MREPEAT152(macro, data)   macro(152, data)
-#define MREPEAT154(macro, data)    MREPEAT153(macro, data)   macro(153, data)
-#define MREPEAT155(macro, data)    MREPEAT154(macro, data)   macro(154, data)
-#define MREPEAT156(macro, data)    MREPEAT155(macro, data)   macro(155, data)
-#define MREPEAT157(macro, data)    MREPEAT156(macro, data)   macro(156, data)
-#define MREPEAT158(macro, data)    MREPEAT157(macro, data)   macro(157, data)
-#define MREPEAT159(macro, data)    MREPEAT158(macro, data)   macro(158, data)
-#define MREPEAT160(macro, data)    MREPEAT159(macro, data)   macro(159, data)
-#define MREPEAT161(macro, data)    MREPEAT160(macro, data)   macro(160, data)
-#define MREPEAT162(macro, data)    MREPEAT161(macro, data)   macro(161, data)
-#define MREPEAT163(macro, data)    MREPEAT162(macro, data)   macro(162, data)
-#define MREPEAT164(macro, data)    MREPEAT163(macro, data)   macro(163, data)
-#define MREPEAT165(macro, data)    MREPEAT164(macro, data)   macro(164, data)
-#define MREPEAT166(macro, data)    MREPEAT165(macro, data)   macro(165, data)
-#define MREPEAT167(macro, data)    MREPEAT166(macro, data)   macro(166, data)
-#define MREPEAT168(macro, data)    MREPEAT167(macro, data)   macro(167, data)
-#define MREPEAT169(macro, data)    MREPEAT168(macro, data)   macro(168, data)
-#define MREPEAT170(macro, data)    MREPEAT169(macro, data)   macro(169, data)
-#define MREPEAT171(macro, data)    MREPEAT170(macro, data)   macro(170, data)
-#define MREPEAT172(macro, data)    MREPEAT171(macro, data)   macro(171, data)
-#define MREPEAT173(macro, data)    MREPEAT172(macro, data)   macro(172, data)
-#define MREPEAT174(macro, data)    MREPEAT173(macro, data)   macro(173, data)
-#define MREPEAT175(macro, data)    MREPEAT174(macro, data)   macro(174, data)
-#define MREPEAT176(macro, data)    MREPEAT175(macro, data)   macro(175, data)
-#define MREPEAT177(macro, data)    MREPEAT176(macro, data)   macro(176, data)
-#define MREPEAT178(macro, data)    MREPEAT177(macro, data)   macro(177, data)
-#define MREPEAT179(macro, data)    MREPEAT178(macro, data)   macro(178, data)
-#define MREPEAT180(macro, data)    MREPEAT179(macro, data)   macro(179, data)
-#define MREPEAT181(macro, data)    MREPEAT180(macro, data)   macro(180, data)
-#define MREPEAT182(macro, data)    MREPEAT181(macro, data)   macro(181, data)
-#define MREPEAT183(macro, data)    MREPEAT182(macro, data)   macro(182, data)
-#define MREPEAT184(macro, data)    MREPEAT183(macro, data)   macro(183, data)
-#define MREPEAT185(macro, data)    MREPEAT184(macro, data)   macro(184, data)
-#define MREPEAT186(macro, data)    MREPEAT185(macro, data)   macro(185, data)
-#define MREPEAT187(macro, data)    MREPEAT186(macro, data)   macro(186, data)
-#define MREPEAT188(macro, data)    MREPEAT187(macro, data)   macro(187, data)
-#define MREPEAT189(macro, data)    MREPEAT188(macro, data)   macro(188, data)
-#define MREPEAT190(macro, data)    MREPEAT189(macro, data)   macro(189, data)
-#define MREPEAT191(macro, data)    MREPEAT190(macro, data)   macro(190, data)
-#define MREPEAT192(macro, data)    MREPEAT191(macro, data)   macro(191, data)
-#define MREPEAT193(macro, data)    MREPEAT192(macro, data)   macro(192, data)
-#define MREPEAT194(macro, data)    MREPEAT193(macro, data)   macro(193, data)
-#define MREPEAT195(macro, data)    MREPEAT194(macro, data)   macro(194, data)
-#define MREPEAT196(macro, data)    MREPEAT195(macro, data)   macro(195, data)
-#define MREPEAT197(macro, data)    MREPEAT196(macro, data)   macro(196, data)
-#define MREPEAT198(macro, data)    MREPEAT197(macro, data)   macro(197, data)
-#define MREPEAT199(macro, data)    MREPEAT198(macro, data)   macro(198, data)
-#define MREPEAT200(macro, data)    MREPEAT199(macro, data)   macro(199, data)
-#define MREPEAT201(macro, data)    MREPEAT200(macro, data)   macro(200, data)
-#define MREPEAT202(macro, data)    MREPEAT201(macro, data)   macro(201, data)
-#define MREPEAT203(macro, data)    MREPEAT202(macro, data)   macro(202, data)
-#define MREPEAT204(macro, data)    MREPEAT203(macro, data)   macro(203, data)
-#define MREPEAT205(macro, data)    MREPEAT204(macro, data)   macro(204, data)
-#define MREPEAT206(macro, data)    MREPEAT205(macro, data)   macro(205, data)
-#define MREPEAT207(macro, data)    MREPEAT206(macro, data)   macro(206, data)
-#define MREPEAT208(macro, data)    MREPEAT207(macro, data)   macro(207, data)
-#define MREPEAT209(macro, data)    MREPEAT208(macro, data)   macro(208, data)
-#define MREPEAT210(macro, data)    MREPEAT209(macro, data)   macro(209, data)
-#define MREPEAT211(macro, data)    MREPEAT210(macro, data)   macro(210, data)
-#define MREPEAT212(macro, data)    MREPEAT211(macro, data)   macro(211, data)
-#define MREPEAT213(macro, data)    MREPEAT212(macro, data)   macro(212, data)
-#define MREPEAT214(macro, data)    MREPEAT213(macro, data)   macro(213, data)
-#define MREPEAT215(macro, data)    MREPEAT214(macro, data)   macro(214, data)
-#define MREPEAT216(macro, data)    MREPEAT215(macro, data)   macro(215, data)
-#define MREPEAT217(macro, data)    MREPEAT216(macro, data)   macro(216, data)
-#define MREPEAT218(macro, data)    MREPEAT217(macro, data)   macro(217, data)
-#define MREPEAT219(macro, data)    MREPEAT218(macro, data)   macro(218, data)
-#define MREPEAT220(macro, data)    MREPEAT219(macro, data)   macro(219, data)
-#define MREPEAT221(macro, data)    MREPEAT220(macro, data)   macro(220, data)
-#define MREPEAT222(macro, data)    MREPEAT221(macro, data)   macro(221, data)
-#define MREPEAT223(macro, data)    MREPEAT222(macro, data)   macro(222, data)
-#define MREPEAT224(macro, data)    MREPEAT223(macro, data)   macro(223, data)
-#define MREPEAT225(macro, data)    MREPEAT224(macro, data)   macro(224, data)
-#define MREPEAT226(macro, data)    MREPEAT225(macro, data)   macro(225, data)
-#define MREPEAT227(macro, data)    MREPEAT226(macro, data)   macro(226, data)
-#define MREPEAT228(macro, data)    MREPEAT227(macro, data)   macro(227, data)
-#define MREPEAT229(macro, data)    MREPEAT228(macro, data)   macro(228, data)
-#define MREPEAT230(macro, data)    MREPEAT229(macro, data)   macro(229, data)
-#define MREPEAT231(macro, data)    MREPEAT230(macro, data)   macro(230, data)
-#define MREPEAT232(macro, data)    MREPEAT231(macro, data)   macro(231, data)
-#define MREPEAT233(macro, data)    MREPEAT232(macro, data)   macro(232, data)
-#define MREPEAT234(macro, data)    MREPEAT233(macro, data)   macro(233, data)
-#define MREPEAT235(macro, data)    MREPEAT234(macro, data)   macro(234, data)
-#define MREPEAT236(macro, data)    MREPEAT235(macro, data)   macro(235, data)
-#define MREPEAT237(macro, data)    MREPEAT236(macro, data)   macro(236, data)
-#define MREPEAT238(macro, data)    MREPEAT237(macro, data)   macro(237, data)
-#define MREPEAT239(macro, data)    MREPEAT238(macro, data)   macro(238, data)
-#define MREPEAT240(macro, data)    MREPEAT239(macro, data)   macro(239, data)
-#define MREPEAT241(macro, data)    MREPEAT240(macro, data)   macro(240, data)
-#define MREPEAT242(macro, data)    MREPEAT241(macro, data)   macro(241, data)
-#define MREPEAT243(macro, data)    MREPEAT242(macro, data)   macro(242, data)
-#define MREPEAT244(macro, data)    MREPEAT243(macro, data)   macro(243, data)
-#define MREPEAT245(macro, data)    MREPEAT244(macro, data)   macro(244, data)
-#define MREPEAT246(macro, data)    MREPEAT245(macro, data)   macro(245, data)
-#define MREPEAT247(macro, data)    MREPEAT246(macro, data)   macro(246, data)
-#define MREPEAT248(macro, data)    MREPEAT247(macro, data)   macro(247, data)
-#define MREPEAT249(macro, data)    MREPEAT248(macro, data)   macro(248, data)
-#define MREPEAT250(macro, data)    MREPEAT249(macro, data)   macro(249, data)
-#define MREPEAT251(macro, data)    MREPEAT250(macro, data)   macro(250, data)
-#define MREPEAT252(macro, data)    MREPEAT251(macro, data)   macro(251, data)
-#define MREPEAT253(macro, data)    MREPEAT252(macro, data)   macro(252, data)
-#define MREPEAT254(macro, data)    MREPEAT253(macro, data)   macro(253, data)
-#define MREPEAT255(macro, data)    MREPEAT254(macro, data)   macro(254, data)
-#define MREPEAT256(macro, data)    MREPEAT255(macro, data)   macro(255, data)
-
-/** @} */
-
-#endif  /* _MREPEAT_H_ */
+/**
+ * \file
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+/**
+ * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+/** Maximal number of repetitions supported by MREPEAT. */
+#define MREPEAT_LIMIT   256
+
+/** \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count  The number of repetitious calls to macro. Valid values
+ *                   range from 0 to MREPEAT_LIMIT.
+ * \param[in] macro  A binary operation of the form macro(n, data). This macro
+ *                   is expanded by MREPEAT with the current repetition number
+ *                   and the auxiliary data argument.
+ * \param[in] data   Auxiliary data passed to macro.
+ *
+ * \return       <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
+ */
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)
+
+#define MREPEAT0(  macro, data)
+#define MREPEAT1(  macro, data)    MREPEAT0(  macro, data)   macro(  0, data)
+#define MREPEAT2(  macro, data)    MREPEAT1(  macro, data)   macro(  1, data)
+#define MREPEAT3(  macro, data)    MREPEAT2(  macro, data)   macro(  2, data)
+#define MREPEAT4(  macro, data)    MREPEAT3(  macro, data)   macro(  3, data)
+#define MREPEAT5(  macro, data)    MREPEAT4(  macro, data)   macro(  4, data)
+#define MREPEAT6(  macro, data)    MREPEAT5(  macro, data)   macro(  5, data)
+#define MREPEAT7(  macro, data)    MREPEAT6(  macro, data)   macro(  6, data)
+#define MREPEAT8(  macro, data)    MREPEAT7(  macro, data)   macro(  7, data)
+#define MREPEAT9(  macro, data)    MREPEAT8(  macro, data)   macro(  8, data)
+#define MREPEAT10( macro, data)    MREPEAT9(  macro, data)   macro(  9, data)
+#define MREPEAT11( macro, data)    MREPEAT10( macro, data)   macro( 10, data)
+#define MREPEAT12( macro, data)    MREPEAT11( macro, data)   macro( 11, data)
+#define MREPEAT13( macro, data)    MREPEAT12( macro, data)   macro( 12, data)
+#define MREPEAT14( macro, data)    MREPEAT13( macro, data)   macro( 13, data)
+#define MREPEAT15( macro, data)    MREPEAT14( macro, data)   macro( 14, data)
+#define MREPEAT16( macro, data)    MREPEAT15( macro, data)   macro( 15, data)
+#define MREPEAT17( macro, data)    MREPEAT16( macro, data)   macro( 16, data)
+#define MREPEAT18( macro, data)    MREPEAT17( macro, data)   macro( 17, data)
+#define MREPEAT19( macro, data)    MREPEAT18( macro, data)   macro( 18, data)
+#define MREPEAT20( macro, data)    MREPEAT19( macro, data)   macro( 19, data)
+#define MREPEAT21( macro, data)    MREPEAT20( macro, data)   macro( 20, data)
+#define MREPEAT22( macro, data)    MREPEAT21( macro, data)   macro( 21, data)
+#define MREPEAT23( macro, data)    MREPEAT22( macro, data)   macro( 22, data)
+#define MREPEAT24( macro, data)    MREPEAT23( macro, data)   macro( 23, data)
+#define MREPEAT25( macro, data)    MREPEAT24( macro, data)   macro( 24, data)
+#define MREPEAT26( macro, data)    MREPEAT25( macro, data)   macro( 25, data)
+#define MREPEAT27( macro, data)    MREPEAT26( macro, data)   macro( 26, data)
+#define MREPEAT28( macro, data)    MREPEAT27( macro, data)   macro( 27, data)
+#define MREPEAT29( macro, data)    MREPEAT28( macro, data)   macro( 28, data)
+#define MREPEAT30( macro, data)    MREPEAT29( macro, data)   macro( 29, data)
+#define MREPEAT31( macro, data)    MREPEAT30( macro, data)   macro( 30, data)
+#define MREPEAT32( macro, data)    MREPEAT31( macro, data)   macro( 31, data)
+#define MREPEAT33( macro, data)    MREPEAT32( macro, data)   macro( 32, data)
+#define MREPEAT34( macro, data)    MREPEAT33( macro, data)   macro( 33, data)
+#define MREPEAT35( macro, data)    MREPEAT34( macro, data)   macro( 34, data)
+#define MREPEAT36( macro, data)    MREPEAT35( macro, data)   macro( 35, data)
+#define MREPEAT37( macro, data)    MREPEAT36( macro, data)   macro( 36, data)
+#define MREPEAT38( macro, data)    MREPEAT37( macro, data)   macro( 37, data)
+#define MREPEAT39( macro, data)    MREPEAT38( macro, data)   macro( 38, data)
+#define MREPEAT40( macro, data)    MREPEAT39( macro, data)   macro( 39, data)
+#define MREPEAT41( macro, data)    MREPEAT40( macro, data)   macro( 40, data)
+#define MREPEAT42( macro, data)    MREPEAT41( macro, data)   macro( 41, data)
+#define MREPEAT43( macro, data)    MREPEAT42( macro, data)   macro( 42, data)
+#define MREPEAT44( macro, data)    MREPEAT43( macro, data)   macro( 43, data)
+#define MREPEAT45( macro, data)    MREPEAT44( macro, data)   macro( 44, data)
+#define MREPEAT46( macro, data)    MREPEAT45( macro, data)   macro( 45, data)
+#define MREPEAT47( macro, data)    MREPEAT46( macro, data)   macro( 46, data)
+#define MREPEAT48( macro, data)    MREPEAT47( macro, data)   macro( 47, data)
+#define MREPEAT49( macro, data)    MREPEAT48( macro, data)   macro( 48, data)
+#define MREPEAT50( macro, data)    MREPEAT49( macro, data)   macro( 49, data)
+#define MREPEAT51( macro, data)    MREPEAT50( macro, data)   macro( 50, data)
+#define MREPEAT52( macro, data)    MREPEAT51( macro, data)   macro( 51, data)
+#define MREPEAT53( macro, data)    MREPEAT52( macro, data)   macro( 52, data)
+#define MREPEAT54( macro, data)    MREPEAT53( macro, data)   macro( 53, data)
+#define MREPEAT55( macro, data)    MREPEAT54( macro, data)   macro( 54, data)
+#define MREPEAT56( macro, data)    MREPEAT55( macro, data)   macro( 55, data)
+#define MREPEAT57( macro, data)    MREPEAT56( macro, data)   macro( 56, data)
+#define MREPEAT58( macro, data)    MREPEAT57( macro, data)   macro( 57, data)
+#define MREPEAT59( macro, data)    MREPEAT58( macro, data)   macro( 58, data)
+#define MREPEAT60( macro, data)    MREPEAT59( macro, data)   macro( 59, data)
+#define MREPEAT61( macro, data)    MREPEAT60( macro, data)   macro( 60, data)
+#define MREPEAT62( macro, data)    MREPEAT61( macro, data)   macro( 61, data)
+#define MREPEAT63( macro, data)    MREPEAT62( macro, data)   macro( 62, data)
+#define MREPEAT64( macro, data)    MREPEAT63( macro, data)   macro( 63, data)
+#define MREPEAT65( macro, data)    MREPEAT64( macro, data)   macro( 64, data)
+#define MREPEAT66( macro, data)    MREPEAT65( macro, data)   macro( 65, data)
+#define MREPEAT67( macro, data)    MREPEAT66( macro, data)   macro( 66, data)
+#define MREPEAT68( macro, data)    MREPEAT67( macro, data)   macro( 67, data)
+#define MREPEAT69( macro, data)    MREPEAT68( macro, data)   macro( 68, data)
+#define MREPEAT70( macro, data)    MREPEAT69( macro, data)   macro( 69, data)
+#define MREPEAT71( macro, data)    MREPEAT70( macro, data)   macro( 70, data)
+#define MREPEAT72( macro, data)    MREPEAT71( macro, data)   macro( 71, data)
+#define MREPEAT73( macro, data)    MREPEAT72( macro, data)   macro( 72, data)
+#define MREPEAT74( macro, data)    MREPEAT73( macro, data)   macro( 73, data)
+#define MREPEAT75( macro, data)    MREPEAT74( macro, data)   macro( 74, data)
+#define MREPEAT76( macro, data)    MREPEAT75( macro, data)   macro( 75, data)
+#define MREPEAT77( macro, data)    MREPEAT76( macro, data)   macro( 76, data)
+#define MREPEAT78( macro, data)    MREPEAT77( macro, data)   macro( 77, data)
+#define MREPEAT79( macro, data)    MREPEAT78( macro, data)   macro( 78, data)
+#define MREPEAT80( macro, data)    MREPEAT79( macro, data)   macro( 79, data)
+#define MREPEAT81( macro, data)    MREPEAT80( macro, data)   macro( 80, data)
+#define MREPEAT82( macro, data)    MREPEAT81( macro, data)   macro( 81, data)
+#define MREPEAT83( macro, data)    MREPEAT82( macro, data)   macro( 82, data)
+#define MREPEAT84( macro, data)    MREPEAT83( macro, data)   macro( 83, data)
+#define MREPEAT85( macro, data)    MREPEAT84( macro, data)   macro( 84, data)
+#define MREPEAT86( macro, data)    MREPEAT85( macro, data)   macro( 85, data)
+#define MREPEAT87( macro, data)    MREPEAT86( macro, data)   macro( 86, data)
+#define MREPEAT88( macro, data)    MREPEAT87( macro, data)   macro( 87, data)
+#define MREPEAT89( macro, data)    MREPEAT88( macro, data)   macro( 88, data)
+#define MREPEAT90( macro, data)    MREPEAT89( macro, data)   macro( 89, data)
+#define MREPEAT91( macro, data)    MREPEAT90( macro, data)   macro( 90, data)
+#define MREPEAT92( macro, data)    MREPEAT91( macro, data)   macro( 91, data)
+#define MREPEAT93( macro, data)    MREPEAT92( macro, data)   macro( 92, data)
+#define MREPEAT94( macro, data)    MREPEAT93( macro, data)   macro( 93, data)
+#define MREPEAT95( macro, data)    MREPEAT94( macro, data)   macro( 94, data)
+#define MREPEAT96( macro, data)    MREPEAT95( macro, data)   macro( 95, data)
+#define MREPEAT97( macro, data)    MREPEAT96( macro, data)   macro( 96, data)
+#define MREPEAT98( macro, data)    MREPEAT97( macro, data)   macro( 97, data)
+#define MREPEAT99( macro, data)    MREPEAT98( macro, data)   macro( 98, data)
+#define MREPEAT100(macro, data)    MREPEAT99( macro, data)   macro( 99, data)
+#define MREPEAT101(macro, data)    MREPEAT100(macro, data)   macro(100, data)
+#define MREPEAT102(macro, data)    MREPEAT101(macro, data)   macro(101, data)
+#define MREPEAT103(macro, data)    MREPEAT102(macro, data)   macro(102, data)
+#define MREPEAT104(macro, data)    MREPEAT103(macro, data)   macro(103, data)
+#define MREPEAT105(macro, data)    MREPEAT104(macro, data)   macro(104, data)
+#define MREPEAT106(macro, data)    MREPEAT105(macro, data)   macro(105, data)
+#define MREPEAT107(macro, data)    MREPEAT106(macro, data)   macro(106, data)
+#define MREPEAT108(macro, data)    MREPEAT107(macro, data)   macro(107, data)
+#define MREPEAT109(macro, data)    MREPEAT108(macro, data)   macro(108, data)
+#define MREPEAT110(macro, data)    MREPEAT109(macro, data)   macro(109, data)
+#define MREPEAT111(macro, data)    MREPEAT110(macro, data)   macro(110, data)
+#define MREPEAT112(macro, data)    MREPEAT111(macro, data)   macro(111, data)
+#define MREPEAT113(macro, data)    MREPEAT112(macro, data)   macro(112, data)
+#define MREPEAT114(macro, data)    MREPEAT113(macro, data)   macro(113, data)
+#define MREPEAT115(macro, data)    MREPEAT114(macro, data)   macro(114, data)
+#define MREPEAT116(macro, data)    MREPEAT115(macro, data)   macro(115, data)
+#define MREPEAT117(macro, data)    MREPEAT116(macro, data)   macro(116, data)
+#define MREPEAT118(macro, data)    MREPEAT117(macro, data)   macro(117, data)
+#define MREPEAT119(macro, data)    MREPEAT118(macro, data)   macro(118, data)
+#define MREPEAT120(macro, data)    MREPEAT119(macro, data)   macro(119, data)
+#define MREPEAT121(macro, data)    MREPEAT120(macro, data)   macro(120, data)
+#define MREPEAT122(macro, data)    MREPEAT121(macro, data)   macro(121, data)
+#define MREPEAT123(macro, data)    MREPEAT122(macro, data)   macro(122, data)
+#define MREPEAT124(macro, data)    MREPEAT123(macro, data)   macro(123, data)
+#define MREPEAT125(macro, data)    MREPEAT124(macro, data)   macro(124, data)
+#define MREPEAT126(macro, data)    MREPEAT125(macro, data)   macro(125, data)
+#define MREPEAT127(macro, data)    MREPEAT126(macro, data)   macro(126, data)
+#define MREPEAT128(macro, data)    MREPEAT127(macro, data)   macro(127, data)
+#define MREPEAT129(macro, data)    MREPEAT128(macro, data)   macro(128, data)
+#define MREPEAT130(macro, data)    MREPEAT129(macro, data)   macro(129, data)
+#define MREPEAT131(macro, data)    MREPEAT130(macro, data)   macro(130, data)
+#define MREPEAT132(macro, data)    MREPEAT131(macro, data)   macro(131, data)
+#define MREPEAT133(macro, data)    MREPEAT132(macro, data)   macro(132, data)
+#define MREPEAT134(macro, data)    MREPEAT133(macro, data)   macro(133, data)
+#define MREPEAT135(macro, data)    MREPEAT134(macro, data)   macro(134, data)
+#define MREPEAT136(macro, data)    MREPEAT135(macro, data)   macro(135, data)
+#define MREPEAT137(macro, data)    MREPEAT136(macro, data)   macro(136, data)
+#define MREPEAT138(macro, data)    MREPEAT137(macro, data)   macro(137, data)
+#define MREPEAT139(macro, data)    MREPEAT138(macro, data)   macro(138, data)
+#define MREPEAT140(macro, data)    MREPEAT139(macro, data)   macro(139, data)
+#define MREPEAT141(macro, data)    MREPEAT140(macro, data)   macro(140, data)
+#define MREPEAT142(macro, data)    MREPEAT141(macro, data)   macro(141, data)
+#define MREPEAT143(macro, data)    MREPEAT142(macro, data)   macro(142, data)
+#define MREPEAT144(macro, data)    MREPEAT143(macro, data)   macro(143, data)
+#define MREPEAT145(macro, data)    MREPEAT144(macro, data)   macro(144, data)
+#define MREPEAT146(macro, data)    MREPEAT145(macro, data)   macro(145, data)
+#define MREPEAT147(macro, data)    MREPEAT146(macro, data)   macro(146, data)
+#define MREPEAT148(macro, data)    MREPEAT147(macro, data)   macro(147, data)
+#define MREPEAT149(macro, data)    MREPEAT148(macro, data)   macro(148, data)
+#define MREPEAT150(macro, data)    MREPEAT149(macro, data)   macro(149, data)
+#define MREPEAT151(macro, data)    MREPEAT150(macro, data)   macro(150, data)
+#define MREPEAT152(macro, data)    MREPEAT151(macro, data)   macro(151, data)
+#define MREPEAT153(macro, data)    MREPEAT152(macro, data)   macro(152, data)
+#define MREPEAT154(macro, data)    MREPEAT153(macro, data)   macro(153, data)
+#define MREPEAT155(macro, data)    MREPEAT154(macro, data)   macro(154, data)
+#define MREPEAT156(macro, data)    MREPEAT155(macro, data)   macro(155, data)
+#define MREPEAT157(macro, data)    MREPEAT156(macro, data)   macro(156, data)
+#define MREPEAT158(macro, data)    MREPEAT157(macro, data)   macro(157, data)
+#define MREPEAT159(macro, data)    MREPEAT158(macro, data)   macro(158, data)
+#define MREPEAT160(macro, data)    MREPEAT159(macro, data)   macro(159, data)
+#define MREPEAT161(macro, data)    MREPEAT160(macro, data)   macro(160, data)
+#define MREPEAT162(macro, data)    MREPEAT161(macro, data)   macro(161, data)
+#define MREPEAT163(macro, data)    MREPEAT162(macro, data)   macro(162, data)
+#define MREPEAT164(macro, data)    MREPEAT163(macro, data)   macro(163, data)
+#define MREPEAT165(macro, data)    MREPEAT164(macro, data)   macro(164, data)
+#define MREPEAT166(macro, data)    MREPEAT165(macro, data)   macro(165, data)
+#define MREPEAT167(macro, data)    MREPEAT166(macro, data)   macro(166, data)
+#define MREPEAT168(macro, data)    MREPEAT167(macro, data)   macro(167, data)
+#define MREPEAT169(macro, data)    MREPEAT168(macro, data)   macro(168, data)
+#define MREPEAT170(macro, data)    MREPEAT169(macro, data)   macro(169, data)
+#define MREPEAT171(macro, data)    MREPEAT170(macro, data)   macro(170, data)
+#define MREPEAT172(macro, data)    MREPEAT171(macro, data)   macro(171, data)
+#define MREPEAT173(macro, data)    MREPEAT172(macro, data)   macro(172, data)
+#define MREPEAT174(macro, data)    MREPEAT173(macro, data)   macro(173, data)
+#define MREPEAT175(macro, data)    MREPEAT174(macro, data)   macro(174, data)
+#define MREPEAT176(macro, data)    MREPEAT175(macro, data)   macro(175, data)
+#define MREPEAT177(macro, data)    MREPEAT176(macro, data)   macro(176, data)
+#define MREPEAT178(macro, data)    MREPEAT177(macro, data)   macro(177, data)
+#define MREPEAT179(macro, data)    MREPEAT178(macro, data)   macro(178, data)
+#define MREPEAT180(macro, data)    MREPEAT179(macro, data)   macro(179, data)
+#define MREPEAT181(macro, data)    MREPEAT180(macro, data)   macro(180, data)
+#define MREPEAT182(macro, data)    MREPEAT181(macro, data)   macro(181, data)
+#define MREPEAT183(macro, data)    MREPEAT182(macro, data)   macro(182, data)
+#define MREPEAT184(macro, data)    MREPEAT183(macro, data)   macro(183, data)
+#define MREPEAT185(macro, data)    MREPEAT184(macro, data)   macro(184, data)
+#define MREPEAT186(macro, data)    MREPEAT185(macro, data)   macro(185, data)
+#define MREPEAT187(macro, data)    MREPEAT186(macro, data)   macro(186, data)
+#define MREPEAT188(macro, data)    MREPEAT187(macro, data)   macro(187, data)
+#define MREPEAT189(macro, data)    MREPEAT188(macro, data)   macro(188, data)
+#define MREPEAT190(macro, data)    MREPEAT189(macro, data)   macro(189, data)
+#define MREPEAT191(macro, data)    MREPEAT190(macro, data)   macro(190, data)
+#define MREPEAT192(macro, data)    MREPEAT191(macro, data)   macro(191, data)
+#define MREPEAT193(macro, data)    MREPEAT192(macro, data)   macro(192, data)
+#define MREPEAT194(macro, data)    MREPEAT193(macro, data)   macro(193, data)
+#define MREPEAT195(macro, data)    MREPEAT194(macro, data)   macro(194, data)
+#define MREPEAT196(macro, data)    MREPEAT195(macro, data)   macro(195, data)
+#define MREPEAT197(macro, data)    MREPEAT196(macro, data)   macro(196, data)
+#define MREPEAT198(macro, data)    MREPEAT197(macro, data)   macro(197, data)
+#define MREPEAT199(macro, data)    MREPEAT198(macro, data)   macro(198, data)
+#define MREPEAT200(macro, data)    MREPEAT199(macro, data)   macro(199, data)
+#define MREPEAT201(macro, data)    MREPEAT200(macro, data)   macro(200, data)
+#define MREPEAT202(macro, data)    MREPEAT201(macro, data)   macro(201, data)
+#define MREPEAT203(macro, data)    MREPEAT202(macro, data)   macro(202, data)
+#define MREPEAT204(macro, data)    MREPEAT203(macro, data)   macro(203, data)
+#define MREPEAT205(macro, data)    MREPEAT204(macro, data)   macro(204, data)
+#define MREPEAT206(macro, data)    MREPEAT205(macro, data)   macro(205, data)
+#define MREPEAT207(macro, data)    MREPEAT206(macro, data)   macro(206, data)
+#define MREPEAT208(macro, data)    MREPEAT207(macro, data)   macro(207, data)
+#define MREPEAT209(macro, data)    MREPEAT208(macro, data)   macro(208, data)
+#define MREPEAT210(macro, data)    MREPEAT209(macro, data)   macro(209, data)
+#define MREPEAT211(macro, data)    MREPEAT210(macro, data)   macro(210, data)
+#define MREPEAT212(macro, data)    MREPEAT211(macro, data)   macro(211, data)
+#define MREPEAT213(macro, data)    MREPEAT212(macro, data)   macro(212, data)
+#define MREPEAT214(macro, data)    MREPEAT213(macro, data)   macro(213, data)
+#define MREPEAT215(macro, data)    MREPEAT214(macro, data)   macro(214, data)
+#define MREPEAT216(macro, data)    MREPEAT215(macro, data)   macro(215, data)
+#define MREPEAT217(macro, data)    MREPEAT216(macro, data)   macro(216, data)
+#define MREPEAT218(macro, data)    MREPEAT217(macro, data)   macro(217, data)
+#define MREPEAT219(macro, data)    MREPEAT218(macro, data)   macro(218, data)
+#define MREPEAT220(macro, data)    MREPEAT219(macro, data)   macro(219, data)
+#define MREPEAT221(macro, data)    MREPEAT220(macro, data)   macro(220, data)
+#define MREPEAT222(macro, data)    MREPEAT221(macro, data)   macro(221, data)
+#define MREPEAT223(macro, data)    MREPEAT222(macro, data)   macro(222, data)
+#define MREPEAT224(macro, data)    MREPEAT223(macro, data)   macro(223, data)
+#define MREPEAT225(macro, data)    MREPEAT224(macro, data)   macro(224, data)
+#define MREPEAT226(macro, data)    MREPEAT225(macro, data)   macro(225, data)
+#define MREPEAT227(macro, data)    MREPEAT226(macro, data)   macro(226, data)
+#define MREPEAT228(macro, data)    MREPEAT227(macro, data)   macro(227, data)
+#define MREPEAT229(macro, data)    MREPEAT228(macro, data)   macro(228, data)
+#define MREPEAT230(macro, data)    MREPEAT229(macro, data)   macro(229, data)
+#define MREPEAT231(macro, data)    MREPEAT230(macro, data)   macro(230, data)
+#define MREPEAT232(macro, data)    MREPEAT231(macro, data)   macro(231, data)
+#define MREPEAT233(macro, data)    MREPEAT232(macro, data)   macro(232, data)
+#define MREPEAT234(macro, data)    MREPEAT233(macro, data)   macro(233, data)
+#define MREPEAT235(macro, data)    MREPEAT234(macro, data)   macro(234, data)
+#define MREPEAT236(macro, data)    MREPEAT235(macro, data)   macro(235, data)
+#define MREPEAT237(macro, data)    MREPEAT236(macro, data)   macro(236, data)
+#define MREPEAT238(macro, data)    MREPEAT237(macro, data)   macro(237, data)
+#define MREPEAT239(macro, data)    MREPEAT238(macro, data)   macro(238, data)
+#define MREPEAT240(macro, data)    MREPEAT239(macro, data)   macro(239, data)
+#define MREPEAT241(macro, data)    MREPEAT240(macro, data)   macro(240, data)
+#define MREPEAT242(macro, data)    MREPEAT241(macro, data)   macro(241, data)
+#define MREPEAT243(macro, data)    MREPEAT242(macro, data)   macro(242, data)
+#define MREPEAT244(macro, data)    MREPEAT243(macro, data)   macro(243, data)
+#define MREPEAT245(macro, data)    MREPEAT244(macro, data)   macro(244, data)
+#define MREPEAT246(macro, data)    MREPEAT245(macro, data)   macro(245, data)
+#define MREPEAT247(macro, data)    MREPEAT246(macro, data)   macro(246, data)
+#define MREPEAT248(macro, data)    MREPEAT247(macro, data)   macro(247, data)
+#define MREPEAT249(macro, data)    MREPEAT248(macro, data)   macro(248, data)
+#define MREPEAT250(macro, data)    MREPEAT249(macro, data)   macro(249, data)
+#define MREPEAT251(macro, data)    MREPEAT250(macro, data)   macro(250, data)
+#define MREPEAT252(macro, data)    MREPEAT251(macro, data)   macro(251, data)
+#define MREPEAT253(macro, data)    MREPEAT252(macro, data)   macro(252, data)
+#define MREPEAT254(macro, data)    MREPEAT253(macro, data)   macro(253, data)
+#define MREPEAT255(macro, data)    MREPEAT254(macro, data)   macro(254, data)
+#define MREPEAT256(macro, data)    MREPEAT255(macro, data)   macro(255, data)
+
+/** @} */
+
+#endif  /* _MREPEAT_H_ */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/preprocessor.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/preprocessor.h
index d28f8b0..7e02523 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/preprocessor.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/preprocessor.h
@@ -1,45 +1,45 @@
-/**
- * \file
- *
- * \brief Preprocessor utils.
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _PREPROCESSOR_H_
-#define _PREPROCESSOR_H_
-
-#include "tpaste.h"
-#include "stringz.h"
-#include "mrepeat.h"
-#include "mrecursion.h"
-
-#endif  // _PREPROCESSOR_H_
+/**
+ * \file
+ *
+ * \brief Preprocessor utils.
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _PREPROCESSOR_H_
+#define _PREPROCESSOR_H_
+
+#include "tpaste.h"
+#include "stringz.h"
+#include "mrepeat.h"
+#include "mrecursion.h"
+
+#endif  // _PREPROCESSOR_H_
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/stringz.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/stringz.h
index cf307d1..3de964a 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/stringz.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/stringz.h
@@ -1,74 +1,74 @@
-/**
- * \file
- *
- * \brief Preprocessor stringizing utils.
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _STRINGZ_H_
-#define _STRINGZ_H_
-
-/**
- * \defgroup group_sam0_utils_stringz Preprocessor - Stringize
- *
- * \ingroup group_sam0_utils
- *
- * @{
- */
-
-/** \brief Stringize.
- *
- * Stringize a preprocessing token, this token being allowed to be \#defined.
- *
- * May be used only within macros with the token passed as an argument if the
- * token is \#defined.
- *
- * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
- * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
- * writing "A0".
- */
-#define STRINGZ(x)                                #x
-
-/** \brief Absolute stringize.
- *
- * Stringize a preprocessing token, this token being allowed to be \#defined.
- *
- * No restriction of use if the token is \#defined.
- *
- * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
- * equivalent to writing "A0".
- */
-#define ASTRINGZ(x)                               STRINGZ(x)
-
-/** @} */
-
-#endif  // _STRINGZ_H_
+/**
+ * \file
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+/**
+ * \defgroup group_sam0_utils_stringz Preprocessor - Stringize
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the
+ * token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x)                                #x
+
+/** \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x)                               STRINGZ(x)
+
+/** @} */
+
+#endif  // _STRINGZ_H_
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/tpaste.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/tpaste.h
index dd1033a..9555334 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/tpaste.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/preprocessor/tpaste.h
@@ -1,93 +1,93 @@
-/**
- * \file
- *
- * \brief Preprocessor token pasting utils.
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef _TPASTE_H_
-#define _TPASTE_H_
-
-/**
- * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste
- *
- * \ingroup group_sam0_utils
- *
- * @{
- */
-
-/** \name Token Paste
- *
- * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
- *
- * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
- *
- * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
- * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
- * equivalent to writing U32.
- *
- * @{ */
-#define TPASTE2( a, b)                            a##b
-#define TPASTE3( a, b, c)                         a##b##c
-#define TPASTE4( a, b, c, d)                      a##b##c##d
-#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
-#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
-#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
-#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
-#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
-#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
-/** @} */
-
-/** \name Absolute Token Paste
- *
- * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
- *
- * No restriction of use if the tokens are \#defined.
- *
- * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
- * as 32 is equivalent to writing U32.
- *
- * @{ */
-#define ATPASTE2( a, b)                           TPASTE2( a, b)
-#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
-#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
-#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
-#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
-#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
-#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
-#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
-#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
-/** @} */
-
-/** @} */
-
-#endif  // _TPASTE_H_
+/**
+ * \file
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+/**
+ * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ *
+ * @{ */
+#define TPASTE2( a, b)                            a##b
+#define TPASTE3( a, b, c)                         a##b##c
+#define TPASTE4( a, b, c, d)                      a##b##c##d
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
+/** @} */
+
+/** \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ *
+ * @{ */
+#define ATPASTE2( a, b)                           TPASTE2( a, b)
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
+/** @} */
+
+/** @} */
+
+#endif  // _TPASTE_H_
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/status_codes.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/status_codes.h
index 532f8b2..5f2769e 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/status_codes.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/status_codes.h
@@ -1,148 +1,148 @@
-/**
- * \file
- *
- * \brief Status code definitions.
- *
- * This file defines various status codes returned by functions,
- * indicating success or failure as well as what kind of failure.
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef STATUS_CODES_H_INCLUDED
-#define STATUS_CODES_H_INCLUDED
-
-#include <stdint.h>
-
-/**
- * \defgroup group_sam0_utils_status_codes Status Codes
- *
- * \ingroup group_sam0_utils
- *
- * @{
- */
-
-/** Mask to retrieve the error category of a status code. */
-#define STATUS_CATEGORY_MASK  0xF0
-
-/** Mask to retrieve the error code within the category of a status code. */
-#define STATUS_ERROR_MASK     0x0F
-
-/** Status code error categories. */
-enum status_categories {
-	STATUS_CATEGORY_OK                = 0x00,
-	STATUS_CATEGORY_COMMON            = 0x10,
-	STATUS_CATEGORY_ANALOG            = 0x30,
-	STATUS_CATEGORY_COM               = 0x40,
-	STATUS_CATEGORY_IO                = 0x50,
-};
-
-/**
- * Status code that may be returned by shell commands and protocol
- * implementations.
- *
- * \note Any change to these status codes and the corresponding
- * message strings is strictly forbidden. New codes can be added,
- * however, but make sure that any message string tables are updated
- * at the same time.
- */
-enum status_code {
-	STATUS_OK                         = STATUS_CATEGORY_OK     | 0x00,
-	STATUS_VALID_DATA                 = STATUS_CATEGORY_OK     | 0x01,
-	STATUS_NO_CHANGE                  = STATUS_CATEGORY_OK     | 0x02,
-	STATUS_ABORTED                    = STATUS_CATEGORY_OK     | 0x04,
-	STATUS_BUSY                       = STATUS_CATEGORY_OK     | 0x05,
-	STATUS_SUSPEND                    = STATUS_CATEGORY_OK     | 0x06,
-
-	STATUS_ERR_IO                     = STATUS_CATEGORY_COMMON | 0x00,
-	STATUS_ERR_REQ_FLUSHED            = STATUS_CATEGORY_COMMON | 0x01,
-	STATUS_ERR_TIMEOUT                = STATUS_CATEGORY_COMMON | 0x02,
-	STATUS_ERR_BAD_DATA               = STATUS_CATEGORY_COMMON | 0x03,
-	STATUS_ERR_NOT_FOUND              = STATUS_CATEGORY_COMMON | 0x04,
-	STATUS_ERR_UNSUPPORTED_DEV        = STATUS_CATEGORY_COMMON | 0x05,
-	STATUS_ERR_NO_MEMORY              = STATUS_CATEGORY_COMMON | 0x06,
-	STATUS_ERR_INVALID_ARG            = STATUS_CATEGORY_COMMON | 0x07,
-	STATUS_ERR_BAD_ADDRESS            = STATUS_CATEGORY_COMMON | 0x08,
-	STATUS_ERR_BAD_FORMAT             = STATUS_CATEGORY_COMMON | 0x0A,
-	STATUS_ERR_BAD_FRQ                = STATUS_CATEGORY_COMMON | 0x0B,
-	STATUS_ERR_DENIED                 = STATUS_CATEGORY_COMMON | 0x0c,
-	STATUS_ERR_ALREADY_INITIALIZED    = STATUS_CATEGORY_COMMON | 0x0d,
-	STATUS_ERR_OVERFLOW               = STATUS_CATEGORY_COMMON | 0x0e,
-	STATUS_ERR_NOT_INITIALIZED        = STATUS_CATEGORY_COMMON | 0x0f,
-
-	STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
-	STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
-
-	STATUS_ERR_BAUDRATE_UNAVAILABLE   = STATUS_CATEGORY_COM    | 0x00,
-	STATUS_ERR_PACKET_COLLISION       = STATUS_CATEGORY_COM    | 0x01,
-	STATUS_ERR_PROTOCOL               = STATUS_CATEGORY_COM    | 0x02,
-
-	STATUS_ERR_PIN_MUX_INVALID        = STATUS_CATEGORY_IO     | 0x00,
-};
-typedef enum status_code status_code_genare_t;
-
-/**
-  Status codes used by MAC stack.
- */
-enum status_code_wireless {
-	//STATUS_OK               =  0, //!< Success
-	ERR_IO_ERROR            =  -1, //!< I/O error
-	ERR_FLUSHED             =  -2, //!< Request flushed from queue
-	ERR_TIMEOUT             =  -3, //!< Operation timed out
-	ERR_BAD_DATA            =  -4, //!< Data integrity check failed
-	ERR_PROTOCOL            =  -5, //!< Protocol error
-	ERR_UNSUPPORTED_DEV     =  -6, //!< Unsupported device
-	ERR_NO_MEMORY           =  -7, //!< Insufficient memory
-	ERR_INVALID_ARG         =  -8, //!< Invalid argument
-	ERR_BAD_ADDRESS         =  -9, //!< Bad address
-	ERR_BUSY                =  -10, //!< Resource is busy
-	ERR_BAD_FORMAT          =  -11, //!< Data format not recognized
-	ERR_NO_TIMER            =  -12, //!< No timer available
-	ERR_TIMER_ALREADY_RUNNING   =  -13, //!< Timer already running
-	ERR_TIMER_NOT_RUNNING   =  -14, //!< Timer not running
-
-	/**
-	 * \brief Operation in progress
-	 *
-	 * This status code is for driver-internal use when an operation
-	 * is currently being performed.
-	 *
-	 * \note Drivers should never return this status code to any
-	 * callers. It is strictly for internal use.
-	 */
-	OPERATION_IN_PROGRESS	= -128,
-};
-
-typedef enum status_code_wireless status_code_t;
-
-/** @} */
-
-#endif /* STATUS_CODES_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief Status code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef STATUS_CODES_H_INCLUDED
+#define STATUS_CODES_H_INCLUDED
+
+#include <stdint.h>
+
+/**
+ * \defgroup group_sam0_utils_status_codes Status Codes
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** Mask to retrieve the error category of a status code. */
+#define STATUS_CATEGORY_MASK  0xF0
+
+/** Mask to retrieve the error code within the category of a status code. */
+#define STATUS_ERROR_MASK     0x0F
+
+/** Status code error categories. */
+enum status_categories {
+	STATUS_CATEGORY_OK                = 0x00,
+	STATUS_CATEGORY_COMMON            = 0x10,
+	STATUS_CATEGORY_ANALOG            = 0x30,
+	STATUS_CATEGORY_COM               = 0x40,
+	STATUS_CATEGORY_IO                = 0x50,
+};
+
+/**
+ * Status code that may be returned by shell commands and protocol
+ * implementations.
+ *
+ * \note Any change to these status codes and the corresponding
+ * message strings is strictly forbidden. New codes can be added,
+ * however, but make sure that any message string tables are updated
+ * at the same time.
+ */
+enum status_code {
+	STATUS_OK                         = STATUS_CATEGORY_OK     | 0x00,
+	STATUS_VALID_DATA                 = STATUS_CATEGORY_OK     | 0x01,
+	STATUS_NO_CHANGE                  = STATUS_CATEGORY_OK     | 0x02,
+	STATUS_ABORTED                    = STATUS_CATEGORY_OK     | 0x04,
+	STATUS_BUSY                       = STATUS_CATEGORY_OK     | 0x05,
+	STATUS_SUSPEND                    = STATUS_CATEGORY_OK     | 0x06,
+
+	STATUS_ERR_IO                     = STATUS_CATEGORY_COMMON | 0x00,
+	STATUS_ERR_REQ_FLUSHED            = STATUS_CATEGORY_COMMON | 0x01,
+	STATUS_ERR_TIMEOUT                = STATUS_CATEGORY_COMMON | 0x02,
+	STATUS_ERR_BAD_DATA               = STATUS_CATEGORY_COMMON | 0x03,
+	STATUS_ERR_NOT_FOUND              = STATUS_CATEGORY_COMMON | 0x04,
+	STATUS_ERR_UNSUPPORTED_DEV        = STATUS_CATEGORY_COMMON | 0x05,
+	STATUS_ERR_NO_MEMORY              = STATUS_CATEGORY_COMMON | 0x06,
+	STATUS_ERR_INVALID_ARG            = STATUS_CATEGORY_COMMON | 0x07,
+	STATUS_ERR_BAD_ADDRESS            = STATUS_CATEGORY_COMMON | 0x08,
+	STATUS_ERR_BAD_FORMAT             = STATUS_CATEGORY_COMMON | 0x0A,
+	STATUS_ERR_BAD_FRQ                = STATUS_CATEGORY_COMMON | 0x0B,
+	STATUS_ERR_DENIED                 = STATUS_CATEGORY_COMMON | 0x0c,
+	STATUS_ERR_ALREADY_INITIALIZED    = STATUS_CATEGORY_COMMON | 0x0d,
+	STATUS_ERR_OVERFLOW               = STATUS_CATEGORY_COMMON | 0x0e,
+	STATUS_ERR_NOT_INITIALIZED        = STATUS_CATEGORY_COMMON | 0x0f,
+
+	STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
+	STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
+
+	STATUS_ERR_BAUDRATE_UNAVAILABLE   = STATUS_CATEGORY_COM    | 0x00,
+	STATUS_ERR_PACKET_COLLISION       = STATUS_CATEGORY_COM    | 0x01,
+	STATUS_ERR_PROTOCOL               = STATUS_CATEGORY_COM    | 0x02,
+
+	STATUS_ERR_PIN_MUX_INVALID        = STATUS_CATEGORY_IO     | 0x00,
+};
+typedef enum status_code status_code_genare_t;
+
+/**
+  Status codes used by MAC stack.
+ */
+enum status_code_wireless {
+	//STATUS_OK               =  0, //!< Success
+	ERR_IO_ERROR            =  -1, //!< I/O error
+	ERR_FLUSHED             =  -2, //!< Request flushed from queue
+	ERR_TIMEOUT             =  -3, //!< Operation timed out
+	ERR_BAD_DATA            =  -4, //!< Data integrity check failed
+	ERR_PROTOCOL            =  -5, //!< Protocol error
+	ERR_UNSUPPORTED_DEV     =  -6, //!< Unsupported device
+	ERR_NO_MEMORY           =  -7, //!< Insufficient memory
+	ERR_INVALID_ARG         =  -8, //!< Invalid argument
+	ERR_BAD_ADDRESS         =  -9, //!< Bad address
+	ERR_BUSY                =  -10, //!< Resource is busy
+	ERR_BAD_FORMAT          =  -11, //!< Data format not recognized
+	ERR_NO_TIMER            =  -12, //!< No timer available
+	ERR_TIMER_ALREADY_RUNNING   =  -13, //!< Timer already running
+	ERR_TIMER_NOT_RUNNING   =  -14, //!< Timer not running
+
+	/**
+	 * \brief Operation in progress
+	 *
+	 * This status code is for driver-internal use when an operation
+	 * is currently being performed.
+	 *
+	 * \note Drivers should never return this status code to any
+	 * callers. It is strictly for internal use.
+	 */
+	OPERATION_IN_PROGRESS	= -128,
+};
+
+typedef enum status_code_wireless status_code_t;
+
+/** @} */
+
+#endif /* STATUS_CODES_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/read.c b/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/read.c
index 3dd571b..58053dc 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/read.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/read.c
@@ -1,152 +1,152 @@
-/**
- * \file
- *
- * \brief System-specific implementation of the \ref _read function used by
- *         the standard library.
- *
- * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "compiler.h"
-
-/**
- * \defgroup group_common_utils_stdio Standard I/O (stdio)
- *
- * Common standard I/O driver that implements the stdio
- * read and write functions on AVR and SAM devices.
- *
- * \{
- */
-
-extern volatile void *volatile stdio_base;
-void (*ptr_get)(void volatile*, char*);
-
-
-// IAR common implementation
-#if ( defined(__ICCARM__) )
-
-#include <yfuns.h>
-
-#if (__VER__ < 8010000)
-// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
-_STD_BEGIN
-#endif
-
-#pragma module_name = "?__read"
-
-/*! \brief Reads a number of bytes, at most \a size, into the memory area
- *         pointed to by \a buffer.
- *
- * \param handle File handle to read from.
- * \param buffer Pointer to buffer to write read bytes to.
- * \param size Number of bytes to read.
- *
- * \return The number of bytes read, \c 0 at the end of the file, or
- *         \c _LLIO_ERROR on failure.
- */
-size_t __read(int handle, unsigned char *buffer, size_t size)
-{
-	int nChars = 0;
-	// This implementation only reads from stdin.
-	// For all other file handles, it returns failure.
-	if (handle != _LLIO_STDIN) {
-		return _LLIO_ERROR;
-	}
-	for (; size > 0; --size) {
-		ptr_get(stdio_base, (char*)buffer);
-		buffer++;
-		nChars++;
-	}
-	return nChars;
-}
-
-/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
- * the implementation is empty to be compatible with old IAR version.
- */
-int __close(int handle)
-{
-	UNUSED(handle);
-	return 0;
-}
-
-/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
- * the implementation is empty to be compatible with old IAR version.
- */
-int remove(const char* val)
-{
-	UNUSED(val);
-	return 0;
-}
-
-/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
- * the implementation is empty to be compatible with old IAR version.
- */
-long __lseek(int handle, long val, int val2)
-{
-	UNUSED(handle);
-	UNUSED(val2);
-	return val;
-}
-
-#if (__VER__ < 8010000)
-// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
-_STD_END
-#endif
-
-// GCC implementation
-#elif (defined(__GNUC__))
-
-int __attribute__((weak))
-_read (int file, char * ptr, int len); // Remove GCC compiler warning
-
-int __attribute__((weak))
-_read (int file, char * ptr, int len)
-{
-	int nChars = 0;
-
-	if (file != 0) {
-		return -1;
-	}
-
-	for (; len > 0; --len) {
-		ptr_get(stdio_base, ptr);
-		ptr++;
-		nChars++;
-	}
-	return nChars;
-}
-
-#endif
-
-/**
- * \}
- */
-
+/**
+ * \file
+ *
+ * \brief System-specific implementation of the \ref _read function used by
+ *         the standard library.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "compiler.h"
+
+/**
+ * \defgroup group_common_utils_stdio Standard I/O (stdio)
+ *
+ * Common standard I/O driver that implements the stdio
+ * read and write functions on AVR and SAM devices.
+ *
+ * \{
+ */
+
+extern volatile void *volatile stdio_base;
+void (*ptr_get)(void volatile*, char*);
+
+
+// IAR common implementation
+#if ( defined(__ICCARM__) )
+
+#include <yfuns.h>
+
+#if (__VER__ < 8010000)
+// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
+_STD_BEGIN
+#endif
+
+#pragma module_name = "?__read"
+
+/*! \brief Reads a number of bytes, at most \a size, into the memory area
+ *         pointed to by \a buffer.
+ *
+ * \param handle File handle to read from.
+ * \param buffer Pointer to buffer to write read bytes to.
+ * \param size Number of bytes to read.
+ *
+ * \return The number of bytes read, \c 0 at the end of the file, or
+ *         \c _LLIO_ERROR on failure.
+ */
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+	int nChars = 0;
+	// This implementation only reads from stdin.
+	// For all other file handles, it returns failure.
+	if (handle != _LLIO_STDIN) {
+		return _LLIO_ERROR;
+	}
+	for (; size > 0; --size) {
+		ptr_get(stdio_base, (char*)buffer);
+		buffer++;
+		nChars++;
+	}
+	return nChars;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+int __close(int handle)
+{
+	UNUSED(handle);
+	return 0;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+int remove(const char* val)
+{
+	UNUSED(val);
+	return 0;
+}
+
+/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
+ * the implementation is empty to be compatible with old IAR version.
+ */
+long __lseek(int handle, long val, int val2)
+{
+	UNUSED(handle);
+	UNUSED(val2);
+	return val;
+}
+
+#if (__VER__ < 8010000)
+// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
+_STD_END
+#endif
+
+// GCC implementation
+#elif (defined(__GNUC__))
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len); // Remove GCC compiler warning
+
+int __attribute__((weak))
+_read (int file, char * ptr, int len)
+{
+	int nChars = 0;
+
+	if (file != 0) {
+		return -1;
+	}
+
+	for (; len > 0; --len) {
+		ptr_get(stdio_base, ptr);
+		ptr++;
+		nChars++;
+	}
+	return nChars;
+}
+
+#endif
+
+/**
+ * \}
+ */
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h b/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h
index 954ea65..b9d3874 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/stdio_serial/stdio_serial.h
@@ -1,140 +1,140 @@
-/**
- *
- * \file
- *
- * \brief Common Standard I/O Serial Management.
- *
- * This file defines a useful set of functions for the Stdio Serial interface on
- * SAM0 devices.
- *
- * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- ******************************************************************************/
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-
-#ifndef STDIO_SERIAL_H_INCLUDED
-#define STDIO_SERIAL_H_INCLUDED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio)
- * \ingroup group_common_utils_stdio
- *
- * Common standard serial I/O management driver that
- * implements a stdio serial interface on AVR and SAM devices.
- *
- * @{
- */
-
-#include <serial.h>
-#include <stdio.h>
-#include <compiler.h>
-
-/** Pointer to the base of the USART module instance to use for stdio. */
-extern volatile void *volatile stdio_base;
-
-/** Pointer to the external low level write function. */
-extern int (*ptr_put)(void volatile*, char);
-
-/** Pointer to the external low level read function. */
-extern void (*ptr_get)(void volatile*, char*);
-
-#if SAM0
-/** \brief Initializes the stdio in Serial Mode.
- *
- * \param module       Software USART instance to associate with the hardware.
- * \param hw           Base address of the USART hardware instance.
- * \param config       USART configuration parameters for the STDIO stream.
- *
- */
-static inline void stdio_serial_init(
-		struct usart_module *const module,
-		usart_inst_t const hw,
-		const struct usart_config *const config)
-{
-	stdio_base = (void *)module;
-	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
-	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
-
-	usart_serial_init(module, hw, config);
-# if defined(__GNUC__)
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-	setbuf(stdin, NULL);
-	// Note: Already the case in IAR's Normal DLIB default configuration
-	// and AVR GCC library:
-	// - printf() emits one character at a time.
-	// - getchar() requests only 1 byte to exit.
-#  endif
-}
-#endif
-
-#if SAMB
-/** \brief Initializes the stdio in Serial Mode.
- *
- * \param module       Software UART instance to associate with the hardware.
- * \param hw           Base address of the UART hardware instance.
- * \param config       UART configuration parameters for the STDIO stream.
- *
- */
-static inline void stdio_serial_init(
-		struct uart_module *const module,
-		Uart * const hw,
-		const struct uart_config *const config)
-{
-	stdio_base = (void *)module;
-	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
-	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
-
-	usart_serial_init(module, hw, config);
-# if defined(__GNUC__)
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-	setbuf(stdin, NULL);
-	// Note: Already the case in IAR's Normal DLIB default configuration
-	// and AVR GCC library:
-	// - printf() emits one character at a time.
-	// - getchar() requests only 1 byte to exit.
-#  endif
-}
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  // _STDIO_SERIAL_H_
+/**
+ *
+ * \file
+ *
+ * \brief Common Standard I/O Serial Management.
+ *
+ * This file defines a useful set of functions for the Stdio Serial interface on
+ * SAM0 devices.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+
+#ifndef STDIO_SERIAL_H_INCLUDED
+#define STDIO_SERIAL_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio)
+ * \ingroup group_common_utils_stdio
+ *
+ * Common standard serial I/O management driver that
+ * implements a stdio serial interface on AVR and SAM devices.
+ *
+ * @{
+ */
+
+#include <serial.h>
+#include <stdio.h>
+#include <compiler.h>
+
+/** Pointer to the base of the USART module instance to use for stdio. */
+extern volatile void *volatile stdio_base;
+
+/** Pointer to the external low level write function. */
+extern int (*ptr_put)(void volatile*, char);
+
+/** Pointer to the external low level read function. */
+extern void (*ptr_get)(void volatile*, char*);
+
+#if SAM0
+/** \brief Initializes the stdio in Serial Mode.
+ *
+ * \param module       Software USART instance to associate with the hardware.
+ * \param hw           Base address of the USART hardware instance.
+ * \param config       USART configuration parameters for the STDIO stream.
+ *
+ */
+static inline void stdio_serial_init(
+		struct usart_module *const module,
+		usart_inst_t const hw,
+		const struct usart_config *const config)
+{
+	stdio_base = (void *)module;
+	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+
+	usart_serial_init(module, hw, config);
+# if defined(__GNUC__)
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+	setbuf(stdin, NULL);
+	// Note: Already the case in IAR's Normal DLIB default configuration
+	// and AVR GCC library:
+	// - printf() emits one character at a time.
+	// - getchar() requests only 1 byte to exit.
+#  endif
+}
+#endif
+
+#if SAMB
+/** \brief Initializes the stdio in Serial Mode.
+ *
+ * \param module       Software UART instance to associate with the hardware.
+ * \param hw           Base address of the UART hardware instance.
+ * \param config       UART configuration parameters for the STDIO stream.
+ *
+ */
+static inline void stdio_serial_init(
+		struct uart_module *const module,
+		Uart * const hw,
+		const struct uart_config *const config)
+{
+	stdio_base = (void *)module;
+	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+
+	usart_serial_init(module, hw, config);
+# if defined(__GNUC__)
+	// Specify that stdout and stdin should not be buffered.
+	setbuf(stdout, NULL);
+	setbuf(stdin, NULL);
+	// Note: Already the case in IAR's Normal DLIB default configuration
+	// and AVR GCC library:
+	// - printf() emits one character at a time.
+	// - getchar() requests only 1 byte to exit.
+#  endif
+}
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _STDIO_SERIAL_H_
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/write.c b/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/write.c
index 1007ba8..30bdaaf 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/write.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/stdio/write.c
@@ -1,132 +1,132 @@
-/**
- * \file
- *
- * \brief System-specific implementation of the \ref _write function used by
- *         the standard library.
- *
- * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include "compiler.h"
-
-/**
- * \addtogroup group_common_utils_stdio
- *
- * \{
- */
-
-volatile void *volatile stdio_base;
-int (*ptr_put)(void volatile*, char);
-
-
-#if ( defined(__ICCARM__))
-
-#include <yfuns.h>
-
-#if (__VER__ < 8010000)
-// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
-_STD_BEGIN
-#endif
-
-#pragma module_name = "?__write"
-
-/*! \brief Writes a number of bytes, at most \a size, from the memory area
- *         pointed to by \a buffer.
- *
- * If \a buffer is zero then \ref __write performs flushing of internal buffers,
- * if any. In this case, \a handle can be \c -1 to indicate that all handles
- * should be flushed.
- *
- * \param handle File handle to write to.
- * \param buffer Pointer to buffer to read bytes to write from.
- * \param size Number of bytes to write.
- *
- * \return The number of bytes written, or \c _LLIO_ERROR on failure.
- */
-size_t __write(int handle, const unsigned char *buffer, size_t size)
-{
-	size_t nChars = 0;
-
-	if (buffer == 0) {
-		// This means that we should flush internal buffers.
-		return 0;
-	}
-
-	// This implementation only writes to stdout and stderr.
-	// For all other file handles, it returns failure.
-	if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
-		return _LLIO_ERROR;
-	}
-
-	for (; size != 0; --size) {
-		if (ptr_put(stdio_base, *buffer++) < 0) {
-			return _LLIO_ERROR;
-		}
-		++nChars;
-	}
-	return nChars;
-}
-
-#if (__VER__ < 8010000)
-// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
-_STD_END
-#endif
-
-
-#elif (defined(__GNUC__))
-
-int __attribute__((weak))
-_write (int file, char * ptr, int len);
-
-int __attribute__((weak))
-_write (int file, char * ptr, int len)
-{
-	int nChars = 0;
-
-	if ((file != 1) && (file != 2) && (file!=3)) {
-		return -1;
-	}
-
-	for (; len != 0; --len) {
-		if (ptr_put(stdio_base, *ptr++) < 0) {
-			return -1;
-		}
-		++nChars;
-	}
-	return nChars;
-}
-
-#endif
-
-/**
- * \}
- */
-
+/**
+ * \file
+ *
+ * \brief System-specific implementation of the \ref _write function used by
+ *         the standard library.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "compiler.h"
+
+/**
+ * \addtogroup group_common_utils_stdio
+ *
+ * \{
+ */
+
+volatile void *volatile stdio_base;
+int (*ptr_put)(void volatile*, char);
+
+
+#if ( defined(__ICCARM__))
+
+#include <yfuns.h>
+
+#if (__VER__ < 8010000)
+// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
+_STD_BEGIN
+#endif
+
+#pragma module_name = "?__write"
+
+/*! \brief Writes a number of bytes, at most \a size, from the memory area
+ *         pointed to by \a buffer.
+ *
+ * If \a buffer is zero then \ref __write performs flushing of internal buffers,
+ * if any. In this case, \a handle can be \c -1 to indicate that all handles
+ * should be flushed.
+ *
+ * \param handle File handle to write to.
+ * \param buffer Pointer to buffer to read bytes to write from.
+ * \param size Number of bytes to write.
+ *
+ * \return The number of bytes written, or \c _LLIO_ERROR on failure.
+ */
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+	size_t nChars = 0;
+
+	if (buffer == 0) {
+		// This means that we should flush internal buffers.
+		return 0;
+	}
+
+	// This implementation only writes to stdout and stderr.
+	// For all other file handles, it returns failure.
+	if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
+		return _LLIO_ERROR;
+	}
+
+	for (; size != 0; --size) {
+		if (ptr_put(stdio_base, *buffer++) < 0) {
+			return _LLIO_ERROR;
+		}
+		++nChars;
+	}
+	return nChars;
+}
+
+#if (__VER__ < 8010000)
+// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf
+_STD_END
+#endif
+
+
+#elif (defined(__GNUC__))
+
+int __attribute__((weak))
+_write (int file, char * ptr, int len);
+
+int __attribute__((weak))
+_write (int file, char * ptr, int len)
+{
+	int nChars = 0;
+
+	if ((file != 1) && (file != 2) && (file!=3)) {
+		return -1;
+	}
+
+	for (; len != 0; --len) {
+		if (ptr_put(stdio_base, *ptr++) < 0) {
+			return -1;
+		}
+		++nChars;
+	}
+	return nChars;
+}
+
+#endif
+
+/**
+ * \}
+ */
+
diff --git a/D21_ADC_with_DMA/src/ASF/sam0/utils/syscalls/gcc/syscalls.c b/D21_ADC_with_DMA/src/ASF/sam0/utils/syscalls/gcc/syscalls.c
index 3079234..ef46ff1 100644
--- a/D21_ADC_with_DMA/src/ASF/sam0/utils/syscalls/gcc/syscalls.c
+++ b/D21_ADC_with_DMA/src/ASF/sam0/utils/syscalls/gcc/syscalls.c
@@ -1,120 +1,120 @@
-/**
- * \file
- *
- * \brief Syscalls for SAM0 (GCC).
- *
- * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#undef errno
-extern int errno;
-extern int _end;
-
-extern caddr_t _sbrk(int incr);
-extern int link(char *old, char *new);
-extern int _close(int file);
-extern int _fstat(int file, struct stat *st);
-extern int _isatty(int file);
-extern int _lseek(int file, int ptr, int dir);
-extern void _exit(int status);
-extern void _kill(int pid, int sig);
-extern int _getpid(void);
-
-extern caddr_t _sbrk(int incr)
-{
-	static unsigned char *heap = NULL;
-	unsigned char *prev_heap;
-
-	if (heap == NULL) {
-		heap = (unsigned char *)&_end;
-	}
-	prev_heap = heap;
-
-	heap += incr;
-
-	return (caddr_t) prev_heap;
-}
-
-extern int link(char *old, char *new)
-{
-	return -1;
-}
-
-extern int _close(int file)
-{
-	return -1;
-}
-
-extern int _fstat(int file, struct stat *st)
-{
-	st->st_mode = S_IFCHR;
-
-	return 0;
-}
-
-extern int _isatty(int file)
-{
-	return 1;
-}
-
-extern int _lseek(int file, int ptr, int dir)
-{
-	return 0;
-}
-
-extern void _exit(int status)
-{
-	asm("BKPT #0");
-	for (;;);
-}
-
-extern void _kill(int pid, int sig)
-{
-	return;
-}
-
-extern int _getpid(void)
-{
-	return -1;
-}
-
-#ifdef __cplusplus
-}
-#endif
+/**
+ * \file
+ *
+ * \brief Syscalls for SAM0 (GCC).
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef errno
+extern int errno;
+extern int _end;
+
+extern caddr_t _sbrk(int incr);
+extern int link(char *old, char *new);
+extern int _close(int file);
+extern int _fstat(int file, struct stat *st);
+extern int _isatty(int file);
+extern int _lseek(int file, int ptr, int dir);
+extern void _exit(int status);
+extern void _kill(int pid, int sig);
+extern int _getpid(void);
+
+extern caddr_t _sbrk(int incr)
+{
+	static unsigned char *heap = NULL;
+	unsigned char *prev_heap;
+
+	if (heap == NULL) {
+		heap = (unsigned char *)&_end;
+	}
+	prev_heap = heap;
+
+	heap += incr;
+
+	return (caddr_t) prev_heap;
+}
+
+extern int link(char *old, char *new)
+{
+	return -1;
+}
+
+extern int _close(int file)
+{
+	return -1;
+}
+
+extern int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+
+	return 0;
+}
+
+extern int _isatty(int file)
+{
+	return 1;
+}
+
+extern int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+extern void _exit(int status)
+{
+	asm("BKPT #0");
+	for (;;);
+}
+
+extern void _kill(int pid, int sig)
+{
+	return;
+}
+
+extern int _getpid(void)
+{
+	return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
index 422f7fe..ad0f942 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
@@ -1,20 +1,20 @@
-/*
- * Only the CMSIS required parts for ASF are included here, go to the below
- * address for the full package:
- * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php
- *
- * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which
- * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that
- * have FPU module and enabled.
- * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library
- * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for
- * -mfloat-abi=hard configration.
- *
- * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file 
- * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning.
- * Modified from: 
- *  #if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- * to:
- * #if       (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
- *
- */
+/*
+ * Only the CMSIS required parts for ASF are included here, go to the below
+ * address for the full package:
+ * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php
+ *
+ * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which
+ * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that
+ * have FPU module and enabled.
+ * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library
+ * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for
+ * -mfloat-abi=hard configration.
+ *
+ * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file 
+ * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning.
+ * Modified from: 
+ *  #if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+ * to:
+ * #if       (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
+ *
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/arm_math.h b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/arm_math.h
index ea9dd26..997aeae 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/arm_math.h
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/arm_math.h
@@ -1,7157 +1,7157 @@
-/******************************************************************************
- * @file     arm_math.h
- * @brief    Public header file for CMSIS DSP LibraryU
- * @version  V1.5.3
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
-   * 
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
-   *
-   * Preprocessor Macros
-   * ------------
-   *
-   * Each library project have different preprocessor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - ARM_MATH_ARMV8MxL:
-   *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
-   * on Armv8-M Mainline target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
-   *
-   * - __DSP_PRESENT:
-   *
-   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
-  #error Unknown compiler
-#endif
-
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-  #include "core_cm7.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-  #include "core_cm0plus.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
-  #include "core_armv8mbl.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
-  #include "core_armv8mml.h"
-  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
-    #define ARM_MATH_DSP
-  #endif
-#else
-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31          (0x100)
-#define DELTA_Q15          0x5
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-  #define PI               3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if   defined ( __CC_ARM )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
-  #define __SIMD32_TYPE __unaligned int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-#define __SIMD64(addr)        (*(int64_t **) & (addr))
-
-#if !defined (ARM_MATH_DSP)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-#endif /* !defined (ARM_MATH_DSP) */
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else
-    {
-      signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0U; i < 2U; i++)
-    {
-      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-      tempVal = 0x7FFFFFFFu - tempVal;
-      /*      1.31 with exp 1 */
-      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1U);
-  }
-
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else
-    {
-      signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0U; i < 2U; i++)
-    {
-      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFFu - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-  }
-
-
-/*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-#if !defined (ARM_MATH_DSP)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
-  uint32_t x)
-  {
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-  }
-
-  /*
-   * @brief C custom defined SMMLA for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
-  int32_t x,
-  int32_t y,
-  int32_t sum)
-  {
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-  }
-
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed.
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in]  S          points to an instance of the Q15 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in]  S          points to an instance of the floating-point FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q15;
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_casd_df1_inst_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q31;
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]   pSrcA  points to the first input matrix structure
-   * @param[in]   pSrcB  points to the second input matrix structure
-   * @param[out]  pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  pSrc   points to the input matrix
-   * @param[in]  scale  scale factor
-   * @param[out] pDst   points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];     /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;          /**< The proportional gain. */
-    float32_t Ki;          /**< The integral gain. */
-    float32_t Kd;          /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] S               points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] S  is an instance of the floating-point PID Control structure
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] S   points to an instance of the Q31 PID Control structure
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] S  points to an instance of the q15 PID Control structure
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;        /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15 * S,
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31 * S,
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;             /**< length of the real sequence */
-    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-   arm_rfft_fast_instance_f32 * S,
-   uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    float32_t normalize;                 /**< normalizing factor. */
-    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;               /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q31_t normalize;                     /**< normalizing factor. */
-    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q15_t normalize;                     /**< normalizing factor. */
-    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  scale      scale factor to be applied
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q15(
-          q15_t * pSrcA,
-          uint32_t srcALen,
-          q15_t * pSrcB,
-          uint32_t srcBLen,
-          q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc  points to the block of input data.
-   * @param[out] pDst  points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   */
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  float64_t * pSrc,
-  float64_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.   The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] S          points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to the state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] S          points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;         /**< step size that control filter coefficient updates. */
-    float32_t energy;     /**< saves previous frame energy. */
-    float32_t x0;         /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
-    q15_t energy;         /**< saves previous frame energy. */
-    q15_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta   input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cos output.
-   */
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCosVal);
-
-
-  /**
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cosine output.
-   */
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] S   is an instance of the floating-point PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] S  points to an instance of the Q31 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31U);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] S   points to an instance of the Q15 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-  }
-
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-  }
-
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output   rotor reference frame d
-   * @param[out] pIq     points to output   rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-  }
-
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output rotor reference frame d
-   * @param[out] pIq     points to output rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for   Q31 version
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
-   * @param[in]     x  input sample to process
-   * @return y processed output sample.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if ((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 +  i      * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q31 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1U);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q15 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (q15_t) (y >> 20);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q7 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (q7_t) (y >> 20);
-     }
-  }
-
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  sin(x).
-   */
-  float32_t arm_sin_f32(
-  float32_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q31_t arm_sin_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q15_t arm_sin_q15(
-  q15_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  cos(x).
-   */
-  float32_t arm_cos_f32(
-  float32_t x);
-
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q31_t arm_cos_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in    input value.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if (in >= 0.0f)
-    {
-
-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
-      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] result     is output pointer
-   * @param[in]  index      is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q31 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q15 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q7 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate.
-  * @param[in]     Y  interpolation coordinate.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11U;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11U;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-  }
-
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-  }
-
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("push")         \
-       _Pragma ("O1")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_EXIT \
-       _Pragma ("pop")
-  #else
-    #define LOW_OPTIMIZATION_EXIT
-  #endif
-
-  /* Enter low optimization region - place directly above function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-  #define LOW_OPTIMIZATION_ENTER \
-       __attribute__(( optimize("-O1") ))
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define LOW_OPTIMIZATION_EXIT
-
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
-  #error Unknown compiler
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
+/******************************************************************************
+ * @file     arm_math.h
+ * @brief    Public header file for CMSIS DSP LibraryU
+ * @version  V1.5.3
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+   * 
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+   *
+   * Preprocessor Macros
+   * ------------
+   *
+   * Each library project have different preprocessor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+   * on Armv8-M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1U);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31U);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1U);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h
index 94212eb..79a2cac 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h
@@ -1,266 +1,266 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * Arm Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-
-/*
- * Arm Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iccarm.h>
-
-
-/*
- * TI Arm Compiler
- */
-#elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __attribute__((packed))
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)                           __attribute__((aligned(x)))
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __packed__
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __packed__
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
-
- #ifndef   __ASM
-    #define __ASM                                  _asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    // NO RETURN is automatically detected hence no warning here
-    #define __NO_RETURN
-  #endif
-  #ifndef   __USED
-    #warning No compiler specific solution for __USED. __USED is ignored.
-    #define __USED
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        @packed struct
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         @packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-#else
-  #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h
index 2d9db15..1bd41a4 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h
@@ -1,2085 +1,2085 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.0.4
- * @date     09. April 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* Fallback for __has_builtin */
-#ifndef __has_builtin
-  #define __has_builtin(x) (0)
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE                 
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-  
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-  
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  return __builtin_arm_get_fpscr();
-#else
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#endif
-#else
-  return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_set_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  __builtin_arm_set_fpscr(fpscr);
-#else
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
-  (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP()                             __ASM volatile ("nop")
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI()                             __ASM volatile ("wfi")
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE()                             __ASM volatile ("wfe")
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV()                             __ASM volatile ("sev")
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__STATIC_FORCEINLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (int16_t)__builtin_bswap16(value);
-#else
-  int16_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return result;
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             (uint8_t)__builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__STATIC_FORCEINLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-__extension__ \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
- __extension__ \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h
index 3b6bae4..a523d70 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/cmsis_version.h
@@ -1,39 +1,39 @@
-/**************************************************************************//**
- * @file     cmsis_version.h
- * @brief    CMSIS Core(M) Version definitions
- * @version  V5.4.0
- * @date     19. April 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CMSIS_VERSION_H
-#define __CMSIS_VERSION_H
-
-/*  CMSIS Version definitions */
-#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
-#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
-#endif
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.4.0
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h
index 424011a..b9377e8 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h
@@ -1,1083 +1,1083 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.6
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
-  @{
- */
-
-#include "cmsis_version.h"
- 
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000U
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-    uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h
index 0142203..7d4b600 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h
@@ -1,270 +1,270 @@
-/******************************************************************************
- * @file     mpu_armv7.h
- * @brief    CMSIS MPU API for Armv7-M MPU
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- 
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
- 
-#ifndef ARM_MPU_ARMV7_H
-#define ARM_MPU_ARMV7_H
-
-#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
-#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
-#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
-#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
-#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
-#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
-#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
-#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
-#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
-#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
-#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
-#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
-#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
-#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
-#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
-#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
-#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
-#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
-#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
-#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
-#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
-#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
-#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
-#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
-#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
-#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
-#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
-#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
-
-#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
-#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
-#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
-#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
-#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
-#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
-
-/** MPU Region Base Address Register Value
-*
-* \param Region The region to be configured, number 0 to 15.
-* \param BaseAddress The base address for the region.
-*/
-#define ARM_MPU_RBAR(Region, BaseAddress) \
-  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
-   ((Region) & MPU_RBAR_REGION_Msk)    |  \
-   (MPU_RBAR_VALID_Msk))
-
-/**
-* MPU Memory Access Attributes
-* 
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable       Region is shareable between multiple bus masters.
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/  
-#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
-  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
-   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
-   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
-   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
-
-/**
-* MPU Region Attribute and Size Register Value
-* 
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
-* \param SubRegionDisable  Sub-region disable field.
-* \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/
-#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
-  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
-   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
-   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
-  
-/**
-* MPU Region Attribute and Size Register Value
-* 
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable       Region is shareable between multiple bus masters.
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-* \param SubRegionDisable  Sub-region disable field.
-* \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/                         
-#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
-  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
-
-/**
-* MPU Memory Access Attribute for strongly ordered memory.
-*  - TEX: 000b
-*  - Shareable
-*  - Non-cacheable
-*  - Non-bufferable
-*/ 
-#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
-
-/**
-* MPU Memory Access Attribute for device memory.
-*  - TEX: 000b (if non-shareable) or 010b (if shareable)
-*  - Shareable or non-shareable
-*  - Non-cacheable
-*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
-*
-* \param IsShareable Configures the device memory as shareable or non-shareable.
-*/ 
-#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
-
-/**
-* MPU Memory Access Attribute for normal memory.
-*  - TEX: 1BBb (reflecting outer cacheability rules)
-*  - Shareable or non-shareable
-*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
-*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
-*
-* \param OuterCp Configures the outer cache policy.
-* \param InnerCp Configures the inner cache policy.
-* \param IsShareable Configures the memory as shareable or non-shareable.
-*/ 
-#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
-
-/**
-* MPU Memory Access Attribute non-cacheable policy.
-*/
-#define ARM_MPU_CACHEP_NOCACHE 0U
-
-/**
-* MPU Memory Access Attribute write-back, write and read allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_WRA 1U
-
-/**
-* MPU Memory Access Attribute write-through, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WT_NWA 2U
-
-/**
-* MPU Memory Access Attribute write-back, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_NWA 3U
-
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
-  uint32_t RBAR; //!< The region base address register value (RBAR)
-  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
-} ARM_MPU_Region_t;
-    
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
-  __DSB();
-  __ISB();
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
-  __DSB();
-  __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
-  MPU->RNR = rnr;
-  MPU->RASR = 0U;
-}
-
-/** Configure an MPU region.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
-{
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
-{
-  MPU->RNR = rnr;
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
-}
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
-  uint32_t i;
-  for (i = 0U; i < len; ++i) 
-  {
-    dst[i] = src[i];
-  }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
-  while (cnt > MPU_TYPE_RALIASES) {
-    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
-    table += MPU_TYPE_RALIASES;
-    cnt -= MPU_TYPE_RALIASES;
-  }
-  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
-}
-
-#endif
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Lib/license.txt b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Lib/license.txt
index 139c1ff..a4487ff 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Lib/license.txt
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/Lib/license.txt
@@ -1,28 +1,28 @@
-All pre-build libraries contained in the folders "ARM" and "GCC"
-are guided by the following license:
-
-Copyright (C) 2009-2014 ARM Limited. 
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used 
-   to endorse or promote products derived from this software without 
-   specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
+All pre-build libraries contained in the folders "ARM" and "GCC"
+are guided by the following license:
+
+Copyright (C) 2009-2014 ARM Limited. 
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used 
+   to endorse or promote products derived from this software without 
+   specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/README.txt b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/README.txt
index e42a543..44bef56 100644
--- a/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/README.txt
+++ b/D21_ADC_with_DMA/src/ASF/thirdparty/CMSIS/README.txt
@@ -1,42 +1,42 @@
-* -------------------------------------------------------------------
-* Copyright (C) 2011-2014 ARM Limited. All rights reserved.  
-* 
-* Date:        17 February 2014  
-* Revision:    V4.00 
-*  
-* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
-* Title:       Release Note for CMSIS
-*
-* -------------------------------------------------------------------
-
-
-NOTE - Open the index.html file to access CMSIS documentation
-
-
-The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
-Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
-and reduces time-to-market for new embedded applications.
-
-CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf").
-Any user of the software package is bound to the terms and conditions of the end user license agreement.
-
-
-You will find the following sub-directories:
-
-Documentation           - Contains CMSIS documentation.
- 
-DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
-                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
-
-Include                 - CMSIS Core Support and CMSIS DSP Include Files.
-
-Lib                     - CMSIS DSP Libraries.
-
-RTOS                    - CMSIS RTOS API template header file.
-
-Driver                  - CMSIS Peripheral Driver Interface.
-
-Pack                    - CMSIS Software Packs.
-                          Mechanism to install software, device support, APIs, and example projects.
-
-SVD                     - CMSIS SVD Schema files and Conversion Utility.
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2014 ARM Limited. All rights reserved.  
+* 
+* Date:        17 February 2014  
+* Revision:    V4.00 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+Driver                  - CMSIS Peripheral Driver Interface.
+
+Pack                    - CMSIS Software Packs.
+                          Mechanism to install software, device support, APIs, and example projects.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.
diff --git a/D21_ADC_with_DMA/src/asf.h b/D21_ADC_with_DMA/src/asf.h
index 5cf5bde..148c08f 100644
--- a/D21_ADC_with_DMA/src/asf.h
+++ b/D21_ADC_with_DMA/src/asf.h
@@ -1,114 +1,114 @@
-/**
- * \file
- *
- * \brief Autogenerated API include file for the Atmel Software Framework (ASF)
- *
- * Copyright (c) 2012 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- *    Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef ASF_H
-#define ASF_H
-
-/*
- * This file includes all API header files for the selected drivers from ASF.
- * Note: There might be duplicate includes required by more than one driver.
- *
- * The file is automatically generated and will be re-written when
- * running the ASF driver selector tool. Any changes will be discarded.
- */
-
-// From module: ADC - Analog-to-Digital Converter (Polled APIs)
-#include <adc.h>
-
-// From module: Common SAM0 compiler driver
-#include <compiler.h>
-#include <status_codes.h>
-
-// From module: DMAC - Direct Memory Access Controller
-#include <dma.h>
-#include <dma_crc.h>
-
-// From module: Delay routines
-#include <delay.h>
-
-// From module: Generic board support
-#include <board.h>
-
-// From module: Interrupt management - SAM implementation
-#include <interrupt.h>
-
-// From module: PORT - GPIO Pin Control
-#include <port.h>
-
-// From module: Part identification macros
-#include <parts.h>
-
-// From module: SERCOM Callback API
-#include <sercom.h>
-#include <sercom_interrupt.h>
-
-// From module: SERCOM USART - Serial Communications (Callback APIs)
-#include <usart.h>
-#include <usart_interrupt.h>
-
-// From module: SYSTEM - Clock Management for SAMD21/R21/DA/HA
-#include <clock.h>
-#include <gclk.h>
-
-// From module: SYSTEM - Core System Driver
-#include <system.h>
-
-// From module: SYSTEM - I/O Pin Multiplexer
-#include <pinmux.h>
-
-// From module: SYSTEM - Interrupt Driver
-#include <system_interrupt.h>
-
-// From module: SYSTEM - Power Management for SAM D20/D21/R21/D09/D10/D11/DA/HA
-#include <power.h>
-
-// From module: SYSTEM - Reset Management for SAM D20/D21/R21/D09/D10/D11/DA/HA
-#include <reset.h>
-
-// From module: Standard serial I/O (stdio)
-#include <stdio_serial.h>
-
-// From module: USART - Serial interface- SAM implementation for devices with only USART
-#include <serial.h>
-
-#endif // ASF_H
+/**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ASF_H
+#define ASF_H
+
+/*
+ * This file includes all API header files for the selected drivers from ASF.
+ * Note: There might be duplicate includes required by more than one driver.
+ *
+ * The file is automatically generated and will be re-written when
+ * running the ASF driver selector tool. Any changes will be discarded.
+ */
+
+// From module: ADC - Analog-to-Digital Converter (Polled APIs)
+#include <adc.h>
+
+// From module: Common SAM0 compiler driver
+#include <compiler.h>
+#include <status_codes.h>
+
+// From module: DMAC - Direct Memory Access Controller
+#include <dma.h>
+#include <dma_crc.h>
+
+// From module: Delay routines
+#include <delay.h>
+
+// From module: Generic board support
+#include <board.h>
+
+// From module: Interrupt management - SAM implementation
+#include <interrupt.h>
+
+// From module: PORT - GPIO Pin Control
+#include <port.h>
+
+// From module: Part identification macros
+#include <parts.h>
+
+// From module: SERCOM Callback API
+#include <sercom.h>
+#include <sercom_interrupt.h>
+
+// From module: SERCOM USART - Serial Communications (Callback APIs)
+#include <usart.h>
+#include <usart_interrupt.h>
+
+// From module: SYSTEM - Clock Management for SAMD21/R21/DA/HA
+#include <clock.h>
+#include <gclk.h>
+
+// From module: SYSTEM - Core System Driver
+#include <system.h>
+
+// From module: SYSTEM - I/O Pin Multiplexer
+#include <pinmux.h>
+
+// From module: SYSTEM - Interrupt Driver
+#include <system_interrupt.h>
+
+// From module: SYSTEM - Power Management for SAM D20/D21/R21/D09/D10/D11/DA/HA
+#include <power.h>
+
+// From module: SYSTEM - Reset Management for SAM D20/D21/R21/D09/D10/D11/DA/HA
+#include <reset.h>
+
+// From module: Standard serial I/O (stdio)
+#include <stdio_serial.h>
+
+// From module: USART - Serial interface- SAM implementation for devices with only USART
+#include <serial.h>
+
+#endif // ASF_H
diff --git a/D21_ADC_with_DMA/src/config/conf_board.h b/D21_ADC_with_DMA/src/config/conf_board.h
index 7cebc16..a3ed306 100644
--- a/D21_ADC_with_DMA/src/config/conf_board.h
+++ b/D21_ADC_with_DMA/src/config/conf_board.h
@@ -1,64 +1,64 @@
-/**
- * \file
- *
- * \brief SAM D21 Xplained Pro board configuration.
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-
-#ifndef CONF_BOARD_H_INCLUDED
-#define CONF_BOARD_H_INCLUDED
-
-// Debug Terminal Config
-#define DEBUG_USART_MODULE			SERCOM3
-#define DEBUG_USART_PINMUX_PAD0		PINMUX_PA22C_SERCOM3_PAD0
-#define DEBUG_USART_PINMUX_PAD1		PINMUX_PA23C_SERCOM3_PAD1
-#define DEBUG_USART_PINMUX_PAD2		PINMUX_UNUSED
-#define DEBUG_USART_PINMUX_PAD3		PINMUX_UNUSED
-#define DEBUG_USART_BAUDRATE		115200
-#define DEBUG_USART_MUX_SETTING		USART_RX_1_TX_0_XCK_1
-
-// ADC Config
-#define P_ADC_RESOLUTION			ADC_RESOLUTION_12BIT
-#define P_ADC_CLOCK_PRESCALAR		ADC_CLOCK_PRESCALER_DIV8
-#define P_ADC_GAIN_FACTOR			ADC_GAIN_FACTOR_1X
-// 1/1.48V<SUB>CC</SUB> reference so
-// 1 / 1.48 * 3.3 (ideally) = 2.2297
-#define P_ADC_VREF					ADC_REFERENCE_INTVCC0
-#define P_ADC_VREF_VAL				(2.2297f)
-#define P_ADC_POSITIVE_INPUT_PIN	ADC_POSITIVE_INPUT_PIN4		// PA04
-#define P_ADC_NEGATIVE_INPUT_PIN	ADC_NEGATIVE_INPUT_GND
-// How many values we want to grab out of our buffer
-#define P_ADC_OVERSAMPLE_RATE		16
-// How big we want our buffer to be							
-#define P_ADC_BUFFER_SIZE			16
-
-#endif /* CONF_BOARD_H_INCLUDED */
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board configuration.
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef CONF_BOARD_H_INCLUDED
+#define CONF_BOARD_H_INCLUDED
+
+// Debug Terminal Config
+#define DEBUG_USART_MODULE			SERCOM3
+#define DEBUG_USART_PINMUX_PAD0		PINMUX_PA22C_SERCOM3_PAD0
+#define DEBUG_USART_PINMUX_PAD1		PINMUX_PA23C_SERCOM3_PAD1
+#define DEBUG_USART_PINMUX_PAD2		PINMUX_UNUSED
+#define DEBUG_USART_PINMUX_PAD3		PINMUX_UNUSED
+#define DEBUG_USART_BAUDRATE		115200
+#define DEBUG_USART_MUX_SETTING		USART_RX_1_TX_0_XCK_1
+
+// ADC Config
+#define P_ADC_RESOLUTION			ADC_RESOLUTION_12BIT
+#define P_ADC_CLOCK_PRESCALAR		ADC_CLOCK_PRESCALER_DIV8
+#define P_ADC_GAIN_FACTOR			ADC_GAIN_FACTOR_1X
+// 1/1.48V<SUB>CC</SUB> reference so
+// 1 / 1.48 * 3.3 (ideally) = 2.2297
+#define P_ADC_VREF					ADC_REFERENCE_INTVCC0
+#define P_ADC_VREF_VAL				(2.2297f)
+#define P_ADC_POSITIVE_INPUT_PIN	ADC_POSITIVE_INPUT_PIN4		// PA04
+#define P_ADC_NEGATIVE_INPUT_PIN	ADC_NEGATIVE_INPUT_GND
+// How many values we want to grab out of our buffer
+#define P_ADC_OVERSAMPLE_RATE		16
+// How big we want our buffer to be							
+#define P_ADC_BUFFER_SIZE			16
+
+#endif /* CONF_BOARD_H_INCLUDED */
diff --git a/D21_ADC_with_DMA/src/config/conf_clocks.h b/D21_ADC_with_DMA/src/config/conf_clocks.h
index a055080..e1e0df2 100644
--- a/D21_ADC_with_DMA/src/config/conf_clocks.h
+++ b/D21_ADC_with_DMA/src/config/conf_clocks.h
@@ -1,188 +1,188 @@
-/**
- * \file
- *
- * \brief SAM D21 Clock configuration
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include <clock.h>
-
-#ifndef CONF_CLOCKS_H_INCLUDED
-#  define CONF_CLOCKS_H_INCLUDED
-
-/* System clock bus configuration */
-#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
-#  define CONF_CLOCK_FLASH_WAIT_STATES            0
-#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
-#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
-#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
-#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
-
-/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
-#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
-#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
-#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
-
-/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
-#  define CONF_CLOCK_XOSC_ENABLE                  false
-#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
-#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
-#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
-#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
-#  define CONF_CLOCK_XOSC_ON_DEMAND               true
-#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
-
-/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
-#  define CONF_CLOCK_XOSC32K_ENABLE               false
-#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
-#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
-#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
-#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
-#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
-#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
-#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
-
-/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
-#  define CONF_CLOCK_OSC32K_ENABLE                false
-#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
-#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
-#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
-#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
-#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
-
-/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
-#  define CONF_CLOCK_DFLL_ENABLE                  false
-#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
-#  define CONF_CLOCK_DFLL_ON_DEMAND               false
-
-/* DFLL open loop mode configuration */
-#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
-
-/* DFLL closed loop mode configuration */
-#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
-#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
-#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
-#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
-#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
-#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
-#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
-#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
-
-/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
-#  define CONF_CLOCK_DPLL_ENABLE                  false
-#  define CONF_CLOCK_DPLL_ON_DEMAND               true
-#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
-#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
-#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
-#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
-
-#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
-#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
-#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
-
-#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
-#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
-#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
-
-/* DPLL GCLK reference configuration */
-#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
-/* DPLL GCLK lock timer configuration */
-#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
-
-/* Set this to true to configure the GCLK when running clocks_init. If set to
- * false, none of the GCLK generators will be configured in clocks_init(). */
-#  define CONF_CLOCK_CONFIGURE_GCLK               true
-
-/* Configure GCLK generator 0 (Main Clock) */
-#  define CONF_CLOCK_GCLK_0_ENABLE                true
-#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_0_PRESCALER             1
-#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 1 */
-#  define CONF_CLOCK_GCLK_1_ENABLE                false
-#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
-#  define CONF_CLOCK_GCLK_1_PRESCALER             1
-#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 2 (RTC) */
-#  define CONF_CLOCK_GCLK_2_ENABLE                false
-#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
-#  define CONF_CLOCK_GCLK_2_PRESCALER             32
-#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 3 */
-#  define CONF_CLOCK_GCLK_3_ENABLE                false
-#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_3_PRESCALER             1
-#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 4 */
-#  define CONF_CLOCK_GCLK_4_ENABLE                false
-#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_4_PRESCALER             1
-#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 5 */
-#  define CONF_CLOCK_GCLK_5_ENABLE                false
-#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_5_PRESCALER             1
-#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 6 */
-#  define CONF_CLOCK_GCLK_6_ENABLE                false
-#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_6_PRESCALER             1
-#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 7 */
-#  define CONF_CLOCK_GCLK_7_ENABLE                false
-#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_7_PRESCALER             1
-#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
-
-/* Configure GCLK generator 8 */
-#  define CONF_CLOCK_GCLK_8_ENABLE                false
-#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
-#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
-#  define CONF_CLOCK_GCLK_8_PRESCALER             1
-#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
-
-#endif /* CONF_CLOCKS_H_INCLUDED */
-
+/**
+ * \file
+ *
+ * \brief SAM D21 Clock configuration
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
+#  define CONF_CLOCK_FLASH_WAIT_STATES            0
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               false
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  false
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               false
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
+#  define CONF_CLOCK_DPLL_ENABLE                  false
+#  define CONF_CLOCK_DPLL_ON_DEMAND               true
+#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
+#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
+#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
+#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
+
+#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
+#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
+#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
+#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
+#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
+
+/* DPLL GCLK reference configuration */
+#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
+/* DPLL GCLK lock timer configuration */
+#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                false
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             32
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 8 */
+#  define CONF_CLOCK_GCLK_8_ENABLE                false
+#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_8_PRESCALER             1
+#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+
diff --git a/D21_ADC_with_DMA/src/config/conf_dma.h b/D21_ADC_with_DMA/src/config/conf_dma.h
index 54f075c..2cfde0d 100644
--- a/D21_ADC_with_DMA/src/config/conf_dma.h
+++ b/D21_ADC_with_DMA/src/config/conf_dma.h
@@ -1,41 +1,41 @@
-/**
- * \file
- *
- * \brief SAM Direct Memory Access Driver Configuration Header
- *
- * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#ifndef CONF_DMA_H_INCLUDED
-#define CONF_DMA_H_INCLUDED
-
-#  define CONF_MAX_USED_CHANNEL_NUM     5
-
-#endif
+/**
+ * \file
+ *
+ * \brief SAM Direct Memory Access Driver Configuration Header
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef CONF_DMA_H_INCLUDED
+#define CONF_DMA_H_INCLUDED
+
+#  define CONF_MAX_USED_CHANNEL_NUM     5
+
+#endif
diff --git a/D21_ADC_with_DMA/src/drivers/padc.c b/D21_ADC_with_DMA/src/drivers/padc.c
index 44dc93b..0ed9553 100644
--- a/D21_ADC_with_DMA/src/drivers/padc.c
+++ b/D21_ADC_with_DMA/src/drivers/padc.c
@@ -1,76 +1,76 @@
-#include "padc.h"
-
-static uint16_t raw_adc_values[P_ADC_BUFFER_SIZE];
-
-static struct adc_module adc_mod;
-static struct dma_resource adc_resource;
-
-COMPILER_ALIGNED(16)
-DmacDescriptor adc_descriptor SECTION_DMAC_DESCRIPTOR;
-
-void padc_init(void)
-{
-	// configure adc
-	struct adc_config adc_conf;
-	adc_get_config_defaults(&adc_conf);
-	adc_conf.gain_factor = P_ADC_GAIN_FACTOR;
-	adc_conf.resolution = P_ADC_RESOLUTION;
-	adc_conf.clock_prescaler = P_ADC_CLOCK_PRESCALAR;
-	adc_conf.reference = P_ADC_VREF;
-	adc_conf.positive_input = P_ADC_POSITIVE_INPUT_PIN;
-	adc_conf.negative_input = P_ADC_NEGATIVE_INPUT_PIN;
-	adc_conf.freerunning = true;
-	adc_conf.left_adjust = false;
-	
-	adc_init(&adc_mod, ADC, &adc_conf);
-	adc_enable(&adc_mod);
-	
-	// configure dma resource
-	struct dma_resource_config dma_resource_conf;
-	dma_get_config_defaults(&dma_resource_conf);
-	dma_resource_conf.peripheral_trigger = ADC_DMAC_ID_RESRDY;
-	dma_resource_conf.trigger_action = DMA_TRIGGER_ACTION_BLOCK;
-	// allocate dma resource
-	dma_allocate(&adc_resource, &dma_resource_conf);
-	// setup transfer descriptor
-	struct dma_descriptor_config dma_desc_conf;
-	dma_descriptor_get_config_defaults(&dma_desc_conf);
-	dma_desc_conf.beat_size = DMA_BEAT_SIZE_HWORD;	// 16 bit
-	dma_desc_conf.dst_increment_enable = true;
-	dma_desc_conf.src_increment_enable = false;
-	dma_desc_conf.block_transfer_count = sizeof(raw_adc_values) / 2;
-	dma_desc_conf.source_address = (uint32_t)(&adc_mod.hw->RESULT.reg);
-	dma_desc_conf.destination_address = (uint32_t)(raw_adc_values + (sizeof(raw_adc_values) / 2));
-	dma_desc_conf.next_descriptor_address = (uint32_t)&adc_descriptor;
-	dma_descriptor_create(&adc_descriptor, &dma_desc_conf);
-	dma_add_descriptor(&adc_resource, &adc_descriptor);
-}
-
-void padc_start(void)
-{
-	adc_start_conversion(&adc_mod);
-	dma_start_transfer_job(&adc_resource);
-}
-
-float padc_get_voltage(void)
-{
-	uint16_t raw = padc_get_raw();
-	// raw reading / 2^n * Vref
-	// n = bit resolution
-	// vref = 1/1.48 * Vcc
-	// Vcc is supposed to be 3.3, which would give a Vref of 2.2297
-	// My vcc is dipping a bit low at 3.26-3.28 so my vref is slightly lower.
-	return (float)((float)raw / 4096.0f * 2.2027f);
-}
-
-uint16_t padc_get_raw(void)
-{
-	uint32_t sum = 0;
-	for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
-	{
-		//printf("Raw: [%d]: %u\r\n", ind, raw_adc_values[ind]);
-		sum += (uint32_t)raw_adc_values[ind];
-	}
-	sum /= P_ADC_OVERSAMPLE_RATE;
-	return (uint16_t)sum;
+#include "padc.h"
+
+static uint16_t raw_adc_values[P_ADC_BUFFER_SIZE];
+
+static struct adc_module adc_mod;
+static struct dma_resource adc_resource;
+
+COMPILER_ALIGNED(16)
+DmacDescriptor adc_descriptor SECTION_DMAC_DESCRIPTOR;
+
+void padc_init(void)
+{
+	// configure adc
+	struct adc_config adc_conf;
+	adc_get_config_defaults(&adc_conf);
+	adc_conf.gain_factor = P_ADC_GAIN_FACTOR;
+	adc_conf.resolution = P_ADC_RESOLUTION;
+	adc_conf.clock_prescaler = P_ADC_CLOCK_PRESCALAR;
+	adc_conf.reference = P_ADC_VREF;
+	adc_conf.positive_input = P_ADC_POSITIVE_INPUT_PIN;
+	adc_conf.negative_input = P_ADC_NEGATIVE_INPUT_PIN;
+	adc_conf.freerunning = true;
+	adc_conf.left_adjust = false;
+	
+	adc_init(&adc_mod, ADC, &adc_conf);
+	adc_enable(&adc_mod);
+	
+	// configure dma resource
+	struct dma_resource_config dma_resource_conf;
+	dma_get_config_defaults(&dma_resource_conf);
+	dma_resource_conf.peripheral_trigger = ADC_DMAC_ID_RESRDY;
+	dma_resource_conf.trigger_action = DMA_TRIGGER_ACTION_BLOCK;
+	// allocate dma resource
+	dma_allocate(&adc_resource, &dma_resource_conf);
+	// setup transfer descriptor
+	struct dma_descriptor_config dma_desc_conf;
+	dma_descriptor_get_config_defaults(&dma_desc_conf);
+	dma_desc_conf.beat_size = DMA_BEAT_SIZE_HWORD;	// 16 bit
+	dma_desc_conf.dst_increment_enable = true;
+	dma_desc_conf.src_increment_enable = false;
+	dma_desc_conf.block_transfer_count = sizeof(raw_adc_values) / 2;
+	dma_desc_conf.source_address = (uint32_t)(&adc_mod.hw->RESULT.reg);
+	dma_desc_conf.destination_address = (uint32_t)(raw_adc_values + (sizeof(raw_adc_values) / 2));
+	dma_desc_conf.next_descriptor_address = (uint32_t)&adc_descriptor;
+	dma_descriptor_create(&adc_descriptor, &dma_desc_conf);
+	dma_add_descriptor(&adc_resource, &adc_descriptor);
+}
+
+void padc_start(void)
+{
+	adc_start_conversion(&adc_mod);
+	dma_start_transfer_job(&adc_resource);
+}
+
+float padc_get_voltage(void)
+{
+	uint16_t raw = padc_get_raw();
+	// raw reading / 2^n * Vref
+	// n = bit resolution
+	// vref = 1/1.48 * Vcc
+	// Vcc is supposed to be 3.3, which would give a Vref of 2.2297
+	// My vcc is dipping a bit low at 3.26-3.28 so my vref is slightly lower.
+	return (float)((float)raw / 4096.0f * 2.2027f);
+}
+
+uint16_t padc_get_raw(void)
+{
+	uint32_t sum = 0;
+	for(int ind = 0; ind < P_ADC_OVERSAMPLE_RATE; ind++)
+	{
+		//printf("Raw: [%d]: %u\r\n", ind, raw_adc_values[ind]);
+		sum += (uint32_t)raw_adc_values[ind];
+	}
+	sum /= P_ADC_OVERSAMPLE_RATE;
+	return (uint16_t)sum;
 }
\ No newline at end of file
diff --git a/D21_ADC_with_DMA/src/drivers/padc.h b/D21_ADC_with_DMA/src/drivers/padc.h
index 54d3f41..f517212 100644
--- a/D21_ADC_with_DMA/src/drivers/padc.h
+++ b/D21_ADC_with_DMA/src/drivers/padc.h
@@ -1,12 +1,12 @@
-#ifndef _PADC_H_
-#define _PADC_H_
-
-#include <asf.h>
-
-void padc_init(void);
-void padc_start(void);
-
-float padc_get_voltage(void);
-
-uint16_t padc_get_raw(void);
+#ifndef _PADC_H_
+#define _PADC_H_
+
+#include <asf.h>
+
+void padc_init(void);
+void padc_start(void);
+
+float padc_get_voltage(void);
+
+uint16_t padc_get_raw(void);
 #endif
\ No newline at end of file
diff --git a/D21_ADC_with_DMA/src/drivers/pusart.c b/D21_ADC_with_DMA/src/drivers/pusart.c
index d738d31..c5916e6 100644
--- a/D21_ADC_with_DMA/src/drivers/pusart.c
+++ b/D21_ADC_with_DMA/src/drivers/pusart.c
@@ -1,16 +1,16 @@
-#include "pusart.h"
-
-void pusart_init(void)
-{
-	static struct usart_config uconf;
-	usart_get_config_defaults(&uconf);
-	uconf.pinmux_pad0 = DEBUG_USART_PINMUX_PAD0;
-	uconf.pinmux_pad1 = DEBUG_USART_PINMUX_PAD1;
-	uconf.pinmux_pad2 = DEBUG_USART_PINMUX_PAD2;
-	uconf.pinmux_pad3 = DEBUG_USART_PINMUX_PAD3;
-	uconf.mux_setting = DEBUG_USART_MUX_SETTING;
-	uconf.baudrate = DEBUG_USART_BAUDRATE;
-	stdio_serial_init(&umod, DEBUG_USART_MODULE, &uconf);
-	usart_enable(&umod);
-}
-
+#include "pusart.h"
+
+void pusart_init(void)
+{
+	static struct usart_config uconf;
+	usart_get_config_defaults(&uconf);
+	uconf.pinmux_pad0 = DEBUG_USART_PINMUX_PAD0;
+	uconf.pinmux_pad1 = DEBUG_USART_PINMUX_PAD1;
+	uconf.pinmux_pad2 = DEBUG_USART_PINMUX_PAD2;
+	uconf.pinmux_pad3 = DEBUG_USART_PINMUX_PAD3;
+	uconf.mux_setting = DEBUG_USART_MUX_SETTING;
+	uconf.baudrate = DEBUG_USART_BAUDRATE;
+	stdio_serial_init(&umod, DEBUG_USART_MODULE, &uconf);
+	usart_enable(&umod);
+}
+
diff --git a/D21_ADC_with_DMA/src/drivers/pusart.h b/D21_ADC_with_DMA/src/drivers/pusart.h
index b184159..f0d9e1f 100644
--- a/D21_ADC_with_DMA/src/drivers/pusart.h
+++ b/D21_ADC_with_DMA/src/drivers/pusart.h
@@ -1,7 +1,7 @@
-#ifndef _PUSART_H_
-#define _PUSART_H_
-
-#include <asf.h>
-void pusart_init(void);
-struct usart_module umod;
+#ifndef _PUSART_H_
+#define _PUSART_H_
+
+#include <asf.h>
+void pusart_init(void);
+struct usart_module umod;
 #endif
\ No newline at end of file
diff --git a/D21_ADC_with_DMA/src/main.c b/D21_ADC_with_DMA/src/main.c
index 9a6e0b4..5030cfd 100644
--- a/D21_ADC_with_DMA/src/main.c
+++ b/D21_ADC_with_DMA/src/main.c
@@ -1,63 +1,75 @@
-/**
- * \file
- *
- * \brief Empty user application template
- *
- */
-
-/**
- * \mainpage User Application template doxygen documentation
- *
- * \par Empty user application template
- *
- * This is a bare minimum user application template.
- *
- * For documentation of the board, go \ref group_common_boards "here" for a link
- * to the board-specific documentation.
- *
- * \par Content
- *
- * -# Include the ASF header files (through asf.h)
- * -# Minimal main function that starts with a call to system_init()
- * -# Basic usage of on-board LED and button
- * -# "Insert application code here" comment
- *
- */
-
-/*
- * Include header files for all drivers that have been imported from
- * Atmel Software Framework (ASF).
- */
-/*
- * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
- */
-#include <asf.h>
-#include "pusart.h"
-#include "padc.h"
-int main (void)
-{
-	system_init();
-	delay_init();
-	system_interrupt_enable_global();
-	pusart_init();
-	padc_init();
-	padc_start();
-	
-	// Clear screen
-	printf("%c[2J", 27);
-	// reset cursor pos
-	printf("%c[u", 27);
-	printf(" --\033[31;1m Penguin's\033[0;;40m SAMD21 ADC Demo using DMA -- \r\n");
-	for (;;)
-	{
-		float voltage = padc_get_voltage();
-		printf("Voltage: %d.%03d", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
-		delay_ms(500);
-		// clear line
-		printf("%c[2K", 27);
-		// reset cursor pos
-		printf("%c[u", 27);
-		// moves cursor one down
-		printf("%c[1B", 27);
-	}
-}
+/**
+ * \file
+ *
+ * \brief Empty user application template
+ *
+ */
+
+/**
+ * \mainpage User Application template doxygen documentation
+ *
+ * \par Empty user application template
+ *
+ * This is a bare minimum user application template.
+ *
+ * For documentation of the board, go \ref group_common_boards "here" for a link
+ * to the board-specific documentation.
+ *
+ * \par Content
+ *
+ * -# Include the ASF header files (through asf.h)
+ * -# Minimal main function that starts with a call to system_init()
+ * -# Basic usage of on-board LED and button
+ * -# "Insert application code here" comment
+ *
+ */
+
+/*
+ * Include header files for all drivers that have been imported from
+ * Atmel Software Framework (ASF).
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <asf.h>
+#include "pusart.h"
+#include "padc.h"
+#include <math.h>
+int main (void)
+{
+	system_init();
+	delay_init();
+	system_interrupt_enable_global();
+	pusart_init();
+	padc_init();
+	padc_start();
+	
+	// Clear screen
+	printf("%c[2J", 27);
+	// reset cursor pos
+	printf("%c[u", 27);
+	printf(" --\033[31;1m Penguin's\033[0;;40m SAMD21 ADC Demo using DMA -- \r\n");
+	for (;;)
+	{
+		float voltage = padc_get_voltage();
+		uint32_t resistance = (voltage * 10000) / (3.3 - voltage);
+		double var_a = 0.003354016;
+		double var_b =  0.0002569850 * log(resistance/10000.0);
+		double var_c =  0.000002620131 * (2 * (log(resistance/10000.0)));
+		double var_d =  0.00000006383091 * (3 * (log(resistance/10000.0)));
+		float temp_in_kelvin = (float)(1/(var_a + var_b + var_c + var_d));
+		float temp_in_c = (temp_in_kelvin - 273.15);
+		printf("Voltage: %d.%03d\t", (int)voltage, ((int)((voltage - (int)voltage) * 1000)));
+		printf("Temperature: %d.%03d", (int)temp_in_c, ((int)((temp_in_c) - (int)temp_in_c) * 1000));
+		delay_ms(500);
+		// clear line
+		printf("%c[2K", 27);
+		// reset cursor pos
+		printf("%c[u", 27);
+		// moves cursor one down
+		printf("%c[1B", 27);
+	}
+}
+
+
+RTC->MODE0
\ No newline at end of file